diff options
| author | Curtis Dunham <Curtis.Dunham@arm.com> | 2016-10-13 23:21:40 +0100 |
|---|---|---|
| committer | Curtis Dunham <Curtis.Dunham@arm.com> | 2016-10-13 23:21:40 +0100 |
| commit | c87b717dbdf36f4b0ebef1df4592f1ebabad15a5 (patch) | |
| tree | e8dab9b58aef6394538af96fd1c7f1f2ffaf5775 /tests/quick | |
| parent | 78dd152a0d5e55e26cd6c501dbc4f73e316937d9 (diff) | |
| download | gem5-c87b717dbdf36f4b0ebef1df4592f1ebabad15a5.tar.xz | |
stats: update references
Diffstat (limited to 'tests/quick')
166 files changed, 28883 insertions, 22303 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini index 3ede85d66..7dde96a20 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini @@ -25,7 +25,7 @@ kernel_addr_check=true load_addr_mask=1099511627775 load_offset=0 mem_mode=timing -mem_ranges=0:134217727 +mem_ranges=0:134217727:0:0:0:0 memories=system.physmem mmap_using_noreserve=false multi_thread=false @@ -60,7 +60,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -ranges=8796093022208:18446744073709551615 +ranges=8796093022208:18446744073709551615:0:0:0:0 req_size=16 resp_size=16 master=system.iobus.slave[0] @@ -115,7 +115,7 @@ icache_port=system.cpu0.icache.cpu_side [system.cpu0.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=4 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -166,7 +166,7 @@ size=64 [system.cpu0.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=1 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -268,7 +268,7 @@ icache_port=system.cpu1.icache.cpu_side [system.cpu1.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=4 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -319,7 +319,7 @@ size=64 [system.cpu1.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=1 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -467,7 +467,7 @@ slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma [system.iocache] type=Cache children=tags -addr_ranges=0:134217727 +addr_ranges=0:134217727:0:0:0:0 assoc=8 clk_domain=system.clk_domain clusivity=mostly_incl @@ -513,7 +513,7 @@ size=1024 [system.l2c] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -611,27 +611,27 @@ system=system [system.physmem] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -651,6 +651,7 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 @@ -660,7 +661,7 @@ p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 page_policy=open_adaptive power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 @@ -682,9 +683,9 @@ tRTW=2500 tWR=15000 tWTR=7500 tXAW=30000 -tXP=0 +tXP=6000 tXPDLL=0 -tXS=0 +tXS=270000 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout index 5e8bf0780..d5fb9a1a9 100755 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout @@ -3,14 +3,14 @@ Redirecting stderr to build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/t gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 19 2016 12:23:51 -gem5 started Jul 19 2016 12:24:25 -gem5 executing on e108600-lin, pid 39587 +gem5 compiled Oct 11 2016 00:00:58 +gem5 started Oct 13 2016 20:19:44 +gem5 executing on e108600-lin, pid 28056 command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual Global frequency set at 1000000000000 ticks per second info: kernel located at: /arm/projectscratch/randd/systems/dist/binaries/vmlinux 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 info: Entering event queue @ 0. Starting simulation... -info: Launching CPU 1 @ 722572000 -Exiting @ tick 1963612574000 because m5_exit instruction encountered +info: Launching CPU 1 @ 752919000 +Exiting @ tick 1966741627000 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt index a66428f0b..de3485335 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt @@ -1,119 +1,119 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.962627 # Number of seconds simulated -sim_ticks 1962626573500 # Number of ticks simulated -final_tick 1962626573500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.966742 # Number of seconds simulated +sim_ticks 1966741627000 # Number of ticks simulated +final_tick 1966741627000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 944250 # Simulator instruction rate (inst/s) -host_op_rate 944250 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 30421290331 # Simulator tick rate (ticks/s) -host_mem_usage 338248 # Number of bytes of host memory used -host_seconds 64.52 # Real time elapsed on the host -sim_insts 60918166 # Number of instructions simulated -sim_ops 60918166 # Number of ops (including micro ops) simulated +host_inst_rate 801704 # Simulator instruction rate (inst/s) +host_op_rate 801704 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 25865455419 # Simulator tick rate (ticks/s) +host_mem_usage 334360 # Number of bytes of host memory used +host_seconds 76.04 # Real time elapsed on the host +sim_insts 60959478 # Number of instructions simulated +sim_ops 60959478 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu0.inst 831680 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24730496 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 27968 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 420288 # Number of bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu0.inst 796480 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24829632 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 62464 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 430848 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 26011392 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 831680 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 27968 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 859648 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7700672 # Number of bytes written to this memory -system.physmem.bytes_written::total 7700672 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 12995 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 386414 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 437 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 6567 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 26120384 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 796480 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 62464 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 858944 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7775296 # Number of bytes written to this memory +system.physmem.bytes_written::total 7775296 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 12445 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 387963 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 976 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 6732 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 406428 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 120323 # Number of write requests responded to by this memory -system.physmem.num_writes::total 120323 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 423759 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 12600714 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 14250 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 214146 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 489 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13253358 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 423759 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 14250 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 438009 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3923656 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3923656 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3923656 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 423759 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 12600714 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 14250 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 214146 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 489 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17177014 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 406428 # Number of read requests accepted -system.physmem.writeReqs 120323 # Number of write requests accepted -system.physmem.readBursts 406428 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 120323 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 26003904 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7488 # Total number of bytes read from write queue -system.physmem.bytesWritten 7699456 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 26011392 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7700672 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 117 # Number of DRAM read bursts serviced by the write queue +system.physmem.num_reads::total 408131 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 121489 # Number of write requests responded to by this memory +system.physmem.num_writes::total 121489 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 404974 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12624755 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 31760 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 219067 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 488 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 13281045 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 404974 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 31760 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 436735 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3953390 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3953390 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3953390 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 404974 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 12624755 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 31760 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 219067 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 488 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 17234435 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 408131 # Number of read requests accepted +system.physmem.writeReqs 121489 # Number of write requests accepted +system.physmem.readBursts 408131 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 121489 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 26113216 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7168 # Total number of bytes read from write queue +system.physmem.bytesWritten 7773568 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 26120384 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7775296 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 112 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 25480 # Per bank write bursts -system.physmem.perBankRdBursts::1 25719 # Per bank write bursts -system.physmem.perBankRdBursts::2 25425 # Per bank write bursts -system.physmem.perBankRdBursts::3 24952 # Per bank write bursts -system.physmem.perBankRdBursts::4 24963 # Per bank write bursts -system.physmem.perBankRdBursts::5 25448 # Per bank write bursts -system.physmem.perBankRdBursts::6 25036 # Per bank write bursts -system.physmem.perBankRdBursts::7 25388 # Per bank write bursts -system.physmem.perBankRdBursts::8 25382 # Per bank write bursts -system.physmem.perBankRdBursts::9 25021 # Per bank write bursts -system.physmem.perBankRdBursts::10 25321 # Per bank write bursts -system.physmem.perBankRdBursts::11 25245 # Per bank write bursts -system.physmem.perBankRdBursts::12 25883 # Per bank write bursts -system.physmem.perBankRdBursts::13 25960 # Per bank write bursts -system.physmem.perBankRdBursts::14 25500 # Per bank write bursts -system.physmem.perBankRdBursts::15 25588 # Per bank write bursts -system.physmem.perBankWrBursts::0 8093 # Per bank write bursts -system.physmem.perBankWrBursts::1 7861 # Per bank write bursts -system.physmem.perBankWrBursts::2 7317 # Per bank write bursts -system.physmem.perBankWrBursts::3 6760 # Per bank write bursts -system.physmem.perBankWrBursts::4 6801 # Per bank write bursts -system.physmem.perBankWrBursts::5 7296 # Per bank write bursts -system.physmem.perBankWrBursts::6 7054 # Per bank write bursts -system.physmem.perBankWrBursts::7 7130 # Per bank write bursts -system.physmem.perBankWrBursts::8 7229 # Per bank write bursts -system.physmem.perBankWrBursts::9 7212 # Per bank write bursts -system.physmem.perBankWrBursts::10 7633 # Per bank write bursts -system.physmem.perBankWrBursts::11 7389 # Per bank write bursts -system.physmem.perBankWrBursts::12 8081 # Per bank write bursts -system.physmem.perBankWrBursts::13 8482 # Per bank write bursts -system.physmem.perBankWrBursts::14 7977 # Per bank write bursts -system.physmem.perBankWrBursts::15 7989 # Per bank write bursts +system.physmem.perBankRdBursts::0 25299 # Per bank write bursts +system.physmem.perBankRdBursts::1 25599 # Per bank write bursts +system.physmem.perBankRdBursts::2 25910 # Per bank write bursts +system.physmem.perBankRdBursts::3 25657 # Per bank write bursts +system.physmem.perBankRdBursts::4 25586 # Per bank write bursts +system.physmem.perBankRdBursts::5 25177 # Per bank write bursts +system.physmem.perBankRdBursts::6 26012 # Per bank write bursts +system.physmem.perBankRdBursts::7 25110 # Per bank write bursts +system.physmem.perBankRdBursts::8 25002 # Per bank write bursts +system.physmem.perBankRdBursts::9 25326 # Per bank write bursts +system.physmem.perBankRdBursts::10 25348 # Per bank write bursts +system.physmem.perBankRdBursts::11 25350 # Per bank write bursts +system.physmem.perBankRdBursts::12 25736 # Per bank write bursts +system.physmem.perBankRdBursts::13 25396 # Per bank write bursts +system.physmem.perBankRdBursts::14 25673 # Per bank write bursts +system.physmem.perBankRdBursts::15 25838 # Per bank write bursts +system.physmem.perBankWrBursts::0 7888 # Per bank write bursts +system.physmem.perBankWrBursts::1 7973 # Per bank write bursts +system.physmem.perBankWrBursts::2 7891 # Per bank write bursts +system.physmem.perBankWrBursts::3 7697 # Per bank write bursts +system.physmem.perBankWrBursts::4 7528 # Per bank write bursts +system.physmem.perBankWrBursts::5 7375 # Per bank write bursts +system.physmem.perBankWrBursts::6 8079 # Per bank write bursts +system.physmem.perBankWrBursts::7 7030 # Per bank write bursts +system.physmem.perBankWrBursts::8 7056 # Per bank write bursts +system.physmem.perBankWrBursts::9 7058 # Per bank write bursts +system.physmem.perBankWrBursts::10 7243 # Per bank write bursts +system.physmem.perBankWrBursts::11 7671 # Per bank write bursts +system.physmem.perBankWrBursts::12 7657 # Per bank write bursts +system.physmem.perBankWrBursts::13 7555 # Per bank write bursts +system.physmem.perBankWrBursts::14 7813 # Per bank write bursts +system.physmem.perBankWrBursts::15 7948 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 19 # Number of times write queue was full causing retry -system.physmem.totGap 1962619726500 # Total gap between requests +system.physmem.numWrRetry 71 # Number of times write queue was full causing retry +system.physmem.totGap 1966734334500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 406428 # Read request sizes (log2) +system.physmem.readPktSize::6 408131 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 120323 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 406236 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 62 # What read queue length does an incoming req see +system.physmem.writePktSize::6 121489 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 407926 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 80 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see @@ -159,195 +159,195 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1824 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3074 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5838 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5952 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6657 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6742 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7801 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 8946 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7245 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7909 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 8569 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 6978 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7037 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5737 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5675 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5612 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 195 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 232 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 221 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 209 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 173 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 163 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 164 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 186 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 185 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 196 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 201 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 190 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 196 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 217 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 207 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 167 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 194 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 137 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 202 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 160 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 107 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 83 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 108 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 92 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 62 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 48 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 65759 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 512.528475 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 309.841182 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 413.690018 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 15231 23.16% 23.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 12147 18.47% 41.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5552 8.44% 50.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3316 5.04% 55.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2308 3.51% 58.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1955 2.97% 61.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1491 2.27% 63.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1296 1.97% 65.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 22463 34.16% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 65759 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5364 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 75.747390 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2879.661653 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 5361 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1643 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2752 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5759 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5841 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6396 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6541 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7366 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 8415 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 6986 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7365 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 8033 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7676 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 6912 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7040 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6284 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6217 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5993 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5793 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 415 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 410 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 293 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 317 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 250 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 276 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 265 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 272 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 261 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 288 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 315 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 340 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 315 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 287 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 286 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 292 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 287 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 265 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 188 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 200 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 214 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 205 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 238 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 331 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 265 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 195 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 356 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 350 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 199 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 124 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 163 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 65984 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 513.560621 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 309.956643 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 413.656575 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 15493 23.48% 23.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 12381 18.76% 42.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4640 7.03% 49.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3311 5.02% 54.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3269 4.95% 59.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1542 2.34% 61.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1639 2.48% 64.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1098 1.66% 65.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 22611 34.27% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 65984 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5405 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 75.487327 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2871.274927 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 5402 99.94% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5364 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5364 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 22.428039 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.999012 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 22.364771 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 4746 88.48% 88.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 15 0.28% 88.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 16 0.30% 89.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 23 0.43% 89.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 212 3.95% 93.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 26 0.48% 93.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 13 0.24% 94.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 6 0.11% 94.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 2 0.04% 94.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 8 0.15% 94.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 3 0.06% 94.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 8 0.15% 94.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 13 0.24% 94.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 1 0.02% 94.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 2 0.04% 94.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 2 0.04% 95.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 18 0.34% 95.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 4 0.07% 95.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 23 0.43% 95.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 3 0.06% 95.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 170 3.17% 99.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 3 0.06% 99.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 1 0.02% 99.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 1 0.02% 99.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 4 0.07% 99.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 1 0.02% 99.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 1 0.02% 99.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 1 0.02% 99.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 2 0.04% 99.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 1 0.02% 99.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 8 0.15% 99.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 3 0.06% 99.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-187 1 0.02% 99.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 4 0.07% 99.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-195 2 0.04% 99.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::196-199 2 0.04% 99.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::204-207 1 0.02% 99.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::212-215 1 0.02% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-227 12 0.22% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::244-247 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5364 # Writes before turning the bus around for reads -system.physmem.totQLat 2137214000 # Total ticks spent queuing -system.physmem.totMemAccLat 9755545250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2031555000 # Total ticks spent in databus transfers -system.physmem.avgQLat 5260.04 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5405 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5405 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.472155 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.786030 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 24.242091 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 4888 90.43% 90.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 28 0.52% 90.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 175 3.24% 94.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 6 0.11% 94.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 5 0.09% 94.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 18 0.33% 94.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 9 0.17% 94.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 2 0.04% 94.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 25 0.46% 95.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 5 0.09% 95.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 152 2.81% 98.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 23 0.43% 98.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-119 6 0.11% 98.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-127 3 0.06% 98.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 4 0.07% 98.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-143 5 0.09% 99.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-151 2 0.04% 99.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-159 1 0.02% 99.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-167 1 0.02% 99.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 6 0.11% 99.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 7 0.13% 99.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-191 9 0.17% 99.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-199 7 0.13% 99.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-207 4 0.07% 99.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-215 1 0.02% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-223 6 0.11% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-231 3 0.06% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-263 2 0.04% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::264-271 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::336-343 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5405 # Writes before turning the bus around for reads +system.physmem.totQLat 6252046750 # Total ticks spent queuing +system.physmem.totMemAccLat 13902403000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2040095000 # Total ticks spent in databus transfers +system.physmem.avgQLat 15322.93 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 24010.04 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 13.25 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.92 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 13.25 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.92 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 34072.93 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 13.28 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 3.95 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 13.28 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.95 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.13 # Data bus utilization in percentage system.physmem.busUtilRead 0.10 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.34 # Average write queue length when enqueuing -system.physmem.readRowHits 364061 # Number of row buffer hits during reads -system.physmem.writeRowHits 96795 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.60 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 80.45 # Row buffer hit rate for writes -system.physmem.avgGap 3725896.54 # Average gap between requests -system.physmem.pageHitRate 87.51 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 244346760 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 133324125 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1578805800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 377861760 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 128189159280 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 66163184910 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1119537594750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1316224277385 # Total energy per rank (pJ) -system.physmem_0.averagePower 670.644542 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 1862206979750 # Time in different power states -system.physmem_0.memoryStateTime::REF 65536380000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 34882447750 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 252791280 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 137931750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1590420000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 401708160 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 128189159280 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 66247264755 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1119463832250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1316283107475 # Total energy per rank (pJ) -system.physmem_1.averagePower 670.674522 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1862086480750 # Time in different power states -system.physmem_1.memoryStateTime::REF 65536380000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 35002933000 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states +system.physmem.avgWrQLen 22.83 # Average write queue length when enqueuing +system.physmem.readRowHits 365911 # Number of row buffer hits during reads +system.physmem.writeRowHits 97586 # Number of row buffer hits during writes +system.physmem.readRowHitRate 89.68 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 80.32 # Row buffer hit rate for writes +system.physmem.avgGap 3713482.00 # Average gap between requests +system.physmem.pageHitRate 87.53 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 236241180 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 125565165 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1459059000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 320826420 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 5643624480.000001 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 5139412980 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 370844640 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 13440056220 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 6440902560 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 458973488295 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 492152011950 # Total energy per rank (pJ) +system.physmem_0.averagePower 250.237247 # Core power per rank (mW) +system.physmem_0.totalIdleTime 1954499558250 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 615960500 # Time in different power states +system.physmem_0.memoryStateTime::REF 2400520000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 1908253811750 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 16773151500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 9224451750 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 29473731500 # Time in different power states +system.physmem_1.actEnergy 234884580 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 124844115 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1454196660 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 313205220 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 5773313520.000001 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 5158429890 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 364374240 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 13818451860 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 6703686720 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 458612092095 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 492560034510 # Total energy per rank (pJ) +system.physmem_1.averagePower 250.444709 # Core power per rank (mW) +system.physmem_1.totalIdleTime 1954406570250 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 598675750 # Time in different power states +system.physmem_1.memoryStateTime::REF 2455572000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 1906713566750 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 17457468500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 9212976500 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 30303367500 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 7493005 # DTB read hits -system.cpu0.dtb.read_misses 7443 # DTB read misses +system.cpu0.dtb.read_hits 7479115 # DTB read hits +system.cpu0.dtb.read_misses 7764 # DTB read misses system.cpu0.dtb.read_acv 210 # DTB read access violations -system.cpu0.dtb.read_accesses 490673 # DTB read accesses -system.cpu0.dtb.write_hits 5064687 # DTB write hits -system.cpu0.dtb.write_misses 813 # DTB write misses -system.cpu0.dtb.write_acv 134 # DTB write access violations -system.cpu0.dtb.write_accesses 187452 # DTB write accesses -system.cpu0.dtb.data_hits 12557692 # DTB hits -system.cpu0.dtb.data_misses 8256 # DTB misses -system.cpu0.dtb.data_acv 344 # DTB access violations -system.cpu0.dtb.data_accesses 678125 # DTB accesses -system.cpu0.itb.fetch_hits 3501057 # ITB hits -system.cpu0.itb.fetch_misses 3871 # ITB misses +system.cpu0.dtb.read_accesses 524068 # DTB read accesses +system.cpu0.dtb.write_hits 5079820 # DTB write hits +system.cpu0.dtb.write_misses 909 # DTB write misses +system.cpu0.dtb.write_acv 133 # DTB write access violations +system.cpu0.dtb.write_accesses 202594 # DTB write accesses +system.cpu0.dtb.data_hits 12558935 # DTB hits +system.cpu0.dtb.data_misses 8673 # DTB misses +system.cpu0.dtb.data_acv 343 # DTB access violations +system.cpu0.dtb.data_accesses 726662 # DTB accesses +system.cpu0.itb.fetch_hits 3638634 # ITB hits +system.cpu0.itb.fetch_misses 3984 # ITB misses system.cpu0.itb.fetch_acv 184 # ITB acv -system.cpu0.itb.fetch_accesses 3504928 # ITB accesses +system.cpu0.itb.fetch_accesses 3642618 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -360,427 +360,430 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numPwrStateTransitions 13585 # Number of power state transitions -system.cpu0.pwrStateClkGateDist::samples 6793 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::mean 272297667.010158 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::stdev 432721655.998866 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1000-5e+10 6793 100.00% 100.00% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::min_value 104000 # Distribution of time spent in the clock gated state +system.cpu0.numPwrStateTransitions 13588 # Number of power state transitions +system.cpu0.pwrStateClkGateDist::samples 6794 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::mean 272289101.854578 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::stdev 432882462.064242 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1000-5e+10 6794 100.00% 100.00% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::min_value 249000 # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::max_value 2000000000 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::total 6793 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateResidencyTicks::ON 112908521500 # Cumulative time (in ticks) in various power states -system.cpu0.pwrStateResidencyTicks::CLK_GATED 1849718052000 # Cumulative time (in ticks) in various power states -system.cpu0.numCycles 3923838819 # number of cpu cycles simulated +system.cpu0.pwrStateClkGateDist::total 6794 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateResidencyTicks::ON 116809469000 # Cumulative time (in ticks) in various power states +system.cpu0.pwrStateResidencyTicks::CLK_GATED 1849932158000 # Cumulative time (in ticks) in various power states +system.cpu0.numCycles 3933483254 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6793 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 164897 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 56819 40.19% 40.19% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 131 0.09% 40.28% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1973 1.40% 41.68% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 423 0.30% 41.98% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 82035 58.02% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 141381 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 56285 49.08% 49.08% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 131 0.11% 49.20% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1973 1.72% 50.92% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 423 0.37% 51.29% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 55862 48.71% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 114674 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1900334186500 96.86% 96.86% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 93688500 0.00% 96.87% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 789357000 0.04% 96.91% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 314729500 0.02% 96.92% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 60387418000 3.08% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1961919379500 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.990602 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.quiesce 6794 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 163850 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 56218 40.17% 40.17% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 131 0.09% 40.26% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1975 1.41% 41.67% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 433 0.31% 41.98% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 81195 58.02% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 139952 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 55706 49.07% 49.07% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 131 0.12% 49.19% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1975 1.74% 50.93% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 433 0.38% 51.31% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 55273 48.69% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 113518 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1903167810000 96.77% 96.77% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 93266000 0.00% 96.77% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 790441500 0.04% 96.81% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 321171500 0.02% 96.83% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 62368212000 3.17% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1966740901000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.990893 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.680953 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.811099 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.syscall::2 8 3.60% 3.60% # number of syscalls executed -system.cpu0.kern.syscall::3 19 8.56% 12.16% # number of syscalls executed -system.cpu0.kern.syscall::4 4 1.80% 13.96% # number of syscalls executed -system.cpu0.kern.syscall::6 32 14.41% 28.38% # number of syscalls executed -system.cpu0.kern.syscall::12 1 0.45% 28.83% # number of syscalls executed -system.cpu0.kern.syscall::17 9 4.05% 32.88% # number of syscalls executed -system.cpu0.kern.syscall::19 10 4.50% 37.39% # number of syscalls executed -system.cpu0.kern.syscall::20 6 2.70% 40.09% # number of syscalls executed -system.cpu0.kern.syscall::23 1 0.45% 40.54% # number of syscalls executed -system.cpu0.kern.syscall::24 3 1.35% 41.89% # number of syscalls executed -system.cpu0.kern.syscall::33 7 3.15% 45.05% # number of syscalls executed -system.cpu0.kern.syscall::41 2 0.90% 45.95% # number of syscalls executed -system.cpu0.kern.syscall::45 36 16.22% 62.16% # number of syscalls executed -system.cpu0.kern.syscall::47 3 1.35% 63.51% # number of syscalls executed -system.cpu0.kern.syscall::48 10 4.50% 68.02% # number of syscalls executed -system.cpu0.kern.syscall::54 10 4.50% 72.52% # number of syscalls executed -system.cpu0.kern.syscall::58 1 0.45% 72.97% # number of syscalls executed -system.cpu0.kern.syscall::59 6 2.70% 75.68% # number of syscalls executed -system.cpu0.kern.syscall::71 23 10.36% 86.04% # number of syscalls executed -system.cpu0.kern.syscall::73 3 1.35% 87.39% # number of syscalls executed -system.cpu0.kern.syscall::74 6 2.70% 90.09% # number of syscalls executed -system.cpu0.kern.syscall::87 1 0.45% 90.54% # number of syscalls executed -system.cpu0.kern.syscall::90 3 1.35% 91.89% # number of syscalls executed -system.cpu0.kern.syscall::92 9 4.05% 95.95% # number of syscalls executed -system.cpu0.kern.syscall::97 2 0.90% 96.85% # number of syscalls executed -system.cpu0.kern.syscall::98 2 0.90% 97.75% # number of syscalls executed -system.cpu0.kern.syscall::132 1 0.45% 98.20% # number of syscalls executed -system.cpu0.kern.syscall::144 2 0.90% 99.10% # number of syscalls executed -system.cpu0.kern.syscall::147 2 0.90% 100.00% # number of syscalls executed -system.cpu0.kern.syscall::total 222 # number of syscalls executed +system.cpu0.kern.ipl_used::31 0.680744 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.811121 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.syscall::2 8 3.42% 3.42% # number of syscalls executed +system.cpu0.kern.syscall::3 20 8.55% 11.97% # number of syscalls executed +system.cpu0.kern.syscall::4 4 1.71% 13.68% # number of syscalls executed +system.cpu0.kern.syscall::6 33 14.10% 27.78% # number of syscalls executed +system.cpu0.kern.syscall::12 1 0.43% 28.21% # number of syscalls executed +system.cpu0.kern.syscall::17 10 4.27% 32.48% # number of syscalls executed +system.cpu0.kern.syscall::19 10 4.27% 36.75% # number of syscalls executed +system.cpu0.kern.syscall::20 6 2.56% 39.32% # number of syscalls executed +system.cpu0.kern.syscall::23 1 0.43% 39.74% # number of syscalls executed +system.cpu0.kern.syscall::24 3 1.28% 41.03% # number of syscalls executed +system.cpu0.kern.syscall::33 8 3.42% 44.44% # number of syscalls executed +system.cpu0.kern.syscall::41 2 0.85% 45.30% # number of syscalls executed +system.cpu0.kern.syscall::45 39 16.67% 61.97% # number of syscalls executed +system.cpu0.kern.syscall::47 3 1.28% 63.25% # number of syscalls executed +system.cpu0.kern.syscall::48 10 4.27% 67.52% # number of syscalls executed +system.cpu0.kern.syscall::54 10 4.27% 71.79% # number of syscalls executed +system.cpu0.kern.syscall::58 1 0.43% 72.22% # number of syscalls executed +system.cpu0.kern.syscall::59 6 2.56% 74.79% # number of syscalls executed +system.cpu0.kern.syscall::71 27 11.54% 86.32% # number of syscalls executed +system.cpu0.kern.syscall::73 3 1.28% 87.61% # number of syscalls executed +system.cpu0.kern.syscall::74 7 2.99% 90.60% # number of syscalls executed +system.cpu0.kern.syscall::87 1 0.43% 91.03% # number of syscalls executed +system.cpu0.kern.syscall::90 3 1.28% 92.31% # number of syscalls executed +system.cpu0.kern.syscall::92 9 3.85% 96.15% # number of syscalls executed +system.cpu0.kern.syscall::97 2 0.85% 97.01% # number of syscalls executed +system.cpu0.kern.syscall::98 2 0.85% 97.86% # number of syscalls executed +system.cpu0.kern.syscall::132 1 0.43% 98.29% # number of syscalls executed +system.cpu0.kern.syscall::144 2 0.85% 99.15% # number of syscalls executed +system.cpu0.kern.syscall::147 2 0.85% 100.00% # number of syscalls executed +system.cpu0.kern.syscall::total 234 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 504 0.34% 0.34% # number of callpals executed -system.cpu0.kern.callpal::wrmces 1 0.00% 0.34% # number of callpals executed -system.cpu0.kern.callpal::wrfen 1 0.00% 0.34% # number of callpals executed -system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.34% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3063 2.05% 2.39% # number of callpals executed -system.cpu0.kern.callpal::tbi 51 0.03% 2.42% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.00% 2.42% # number of callpals executed -system.cpu0.kern.callpal::swpipl 134520 89.85% 92.28% # number of callpals executed -system.cpu0.kern.callpal::rdps 6699 4.47% 96.75% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 96.75% # number of callpals executed -system.cpu0.kern.callpal::wrusp 3 0.00% 96.75% # number of callpals executed -system.cpu0.kern.callpal::rdusp 9 0.01% 96.76% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 96.76% # number of callpals executed -system.cpu0.kern.callpal::rti 4333 2.89% 99.65% # number of callpals executed -system.cpu0.kern.callpal::callsys 381 0.25% 99.91% # number of callpals executed -system.cpu0.kern.callpal::imb 136 0.09% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 149713 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 6886 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1283 # number of protection mode switches +system.cpu0.kern.callpal::wripir 525 0.35% 0.36% # number of callpals executed +system.cpu0.kern.callpal::wrmces 1 0.00% 0.36% # number of callpals executed +system.cpu0.kern.callpal::wrfen 1 0.00% 0.36% # number of callpals executed +system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.36% # number of callpals executed +system.cpu0.kern.callpal::swpctx 3064 2.07% 2.43% # number of callpals executed +system.cpu0.kern.callpal::tbi 51 0.03% 2.46% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.00% 2.46% # number of callpals executed +system.cpu0.kern.callpal::swpipl 133000 89.79% 92.25% # number of callpals executed +system.cpu0.kern.callpal::rdps 6513 4.40% 96.65% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 96.65% # number of callpals executed +system.cpu0.kern.callpal::wrusp 4 0.00% 96.65% # number of callpals executed +system.cpu0.kern.callpal::rdusp 9 0.01% 96.66% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 96.66% # number of callpals executed +system.cpu0.kern.callpal::rti 4412 2.98% 99.64% # number of callpals executed +system.cpu0.kern.callpal::callsys 394 0.27% 99.91% # number of callpals executed +system.cpu0.kern.callpal::imb 139 0.09% 100.00% # number of callpals executed +system.cpu0.kern.callpal::total 148125 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 6988 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1369 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1283 -system.cpu0.kern.mode_good::user 1283 +system.cpu0.kern.mode_good::kernel 1368 +system.cpu0.kern.mode_good::user 1369 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.186320 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.195764 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.314114 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1958165685500 99.82% 99.82% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 3548030000 0.18% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.327510 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1962821824500 99.80% 99.80% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 3919074500 0.20% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3064 # number of times the context was actually changed -system.cpu0.committedInsts 47738229 # Number of instructions committed -system.cpu0.committedOps 47738229 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 44272305 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 210363 # Number of float alu accesses -system.cpu0.num_func_calls 1201649 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 5610320 # number of instructions that are conditional controls -system.cpu0.num_int_insts 44272305 # number of integer instructions -system.cpu0.num_fp_insts 210363 # number of float instructions -system.cpu0.num_int_register_reads 60851829 # number of times the integer registers were read -system.cpu0.num_int_register_writes 32993694 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 102169 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 104020 # number of times the floating registers were written -system.cpu0.num_mem_refs 12597866 # number of memory refs -system.cpu0.num_load_insts 7520141 # Number of load instructions -system.cpu0.num_store_insts 5077725 # Number of store instructions -system.cpu0.num_idle_cycles 3698103141.291685 # Number of idle cycles -system.cpu0.num_busy_cycles 225735677.708315 # Number of busy cycles -system.cpu0.not_idle_fraction 0.057529 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.942471 # Percentage of idle cycles -system.cpu0.Branches 7202811 # Number of branches fetched -system.cpu0.op_class::No_OpClass 2726604 5.71% 5.71% # Class of executed instruction -system.cpu0.op_class::IntAlu 31424940 65.82% 71.53% # Class of executed instruction -system.cpu0.op_class::IntMult 52727 0.11% 71.64% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 71.64% # Class of executed instruction -system.cpu0.op_class::FloatAdd 25705 0.05% 71.69% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::FloatDiv 1656 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 71.69% # Class of executed instruction -system.cpu0.op_class::MemRead 7695505 16.12% 87.81% # Class of executed instruction -system.cpu0.op_class::MemWrite 5083820 10.65% 98.46% # Class of executed instruction -system.cpu0.op_class::IprAccess 735872 1.54% 100.00% # Class of executed instruction +system.cpu0.kern.swap_context 3065 # number of times the context was actually changed +system.cpu0.committedInsts 47690735 # Number of instructions committed +system.cpu0.committedOps 47690735 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 44243506 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 210072 # Number of float alu accesses +system.cpu0.num_func_calls 1190980 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 5607273 # number of instructions that are conditional controls +system.cpu0.num_int_insts 44243506 # number of integer instructions +system.cpu0.num_fp_insts 210072 # number of float instructions +system.cpu0.num_int_register_reads 60857324 # number of times the integer registers were read +system.cpu0.num_int_register_writes 32955789 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 102653 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 104432 # number of times the floating registers were written +system.cpu0.num_mem_refs 12599733 # number of memory refs +system.cpu0.num_load_insts 7506744 # Number of load instructions +system.cpu0.num_store_insts 5092989 # Number of store instructions +system.cpu0.num_idle_cycles 3699864315.998118 # Number of idle cycles +system.cpu0.num_busy_cycles 233618938.001881 # Number of busy cycles +system.cpu0.not_idle_fraction 0.059392 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.940608 # Percentage of idle cycles +system.cpu0.Branches 7182999 # Number of branches fetched +system.cpu0.op_class::No_OpClass 2715471 5.69% 5.69% # Class of executed instruction +system.cpu0.op_class::IntAlu 31387897 65.80% 71.50% # Class of executed instruction +system.cpu0.op_class::IntMult 52053 0.11% 71.61% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 71.61% # Class of executed instruction +system.cpu0.op_class::FloatAdd 26676 0.06% 71.66% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 71.66% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 71.66% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 71.66% # Class of executed instruction +system.cpu0.op_class::FloatDiv 1883 0.00% 71.66% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 71.66% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 71.66% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 71.66% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 71.66% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 71.66% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 71.66% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 71.66% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 71.66% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 71.66% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 71.66% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 71.66% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 71.66% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 71.66% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 71.66% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 71.66% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 71.66% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 71.66% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 0 0.00% 71.66% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 71.66% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 71.66% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 71.66% # Class of executed instruction +system.cpu0.op_class::MemRead 7680863 16.10% 87.77% # Class of executed instruction +system.cpu0.op_class::MemWrite 5099104 10.69% 98.46% # Class of executed instruction +system.cpu0.op_class::IprAccess 735804 1.54% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 47746829 # Class of executed instruction -system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.tags.replacements 1179926 # number of replacements -system.cpu0.dcache.tags.tagsinuse 505.222517 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 11367443 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1180345 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 9.630611 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 114940500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.222517 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.986763 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.986763 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 419 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 394 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::3 25 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 0.818359 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 51462845 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 51462845 # Number of data accesses -system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.ReadReq_hits::cpu0.data 6409921 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6409921 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 4656712 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 4656712 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 143926 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 143926 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 147979 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 147979 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 11066633 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 11066633 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 11066633 # number of overall hits -system.cpu0.dcache.overall_hits::total 11066633 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 937871 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 937871 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 251485 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 251485 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13660 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 13660 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 5430 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 5430 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1189356 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1189356 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1189356 # number of overall misses -system.cpu0.dcache.overall_misses::total 1189356 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 29160615500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 29160615500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 10889573000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 10889573000 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 150754500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 150754500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 30482000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 30482000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 40050188500 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 40050188500 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 40050188500 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 40050188500 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 7347792 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 7347792 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 4908197 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 4908197 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 157586 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 157586 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 153409 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 153409 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 12255989 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 12255989 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 12255989 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 12255989 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.127640 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.127640 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051238 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.051238 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.086683 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.086683 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.035396 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.035396 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.097043 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.097043 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.097043 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.097043 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 31092.352253 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 31092.352253 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 43301.083564 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 43301.083564 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 11036.200586 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 11036.200586 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5613.627993 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5613.627993 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33673.844080 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 33673.844080 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33673.844080 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 33673.844080 # average overall miss latency +system.cpu0.op_class::total 47699751 # Class of executed instruction +system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.tags.replacements 1183172 # number of replacements +system.cpu0.dcache.tags.tagsinuse 505.236482 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 11369674 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1183684 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 9.605329 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 121324500 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.236482 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.986790 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.986790 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 115 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 329 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 51472726 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 51472726 # Number of data accesses +system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.ReadReq_hits::cpu0.data 6400739 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6400739 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 4669408 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 4669408 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 138994 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 138994 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 146309 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 146309 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 11070147 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 11070147 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 11070147 # number of overall hits +system.cpu0.dcache.overall_hits::total 11070147 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 938380 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 938380 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 255338 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 255338 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13584 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 13584 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 5728 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 5728 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1193718 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1193718 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1193718 # number of overall misses +system.cpu0.dcache.overall_misses::total 1193718 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 31213946000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 31213946000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 12660198000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 12660198000 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 149666500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 149666500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 31954500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 31954500 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 43874144000 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 43874144000 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 43874144000 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 43874144000 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 7339119 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 7339119 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4924746 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4924746 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 152578 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 152578 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 152037 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 152037 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 12263865 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 12263865 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 12263865 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 12263865 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.127860 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.127860 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051848 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.051848 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.089030 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.089030 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.037675 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.037675 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.097336 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.097336 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.097336 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.097336 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 33263.652252 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 33263.652252 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 49582.114687 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 49582.114687 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 11017.851885 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 11017.851885 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5578.648743 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5578.648743 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 36754.194877 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 36754.194877 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 36754.194877 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 36754.194877 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 679177 # number of writebacks -system.cpu0.dcache.writebacks::total 679177 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 937871 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 937871 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 251485 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 251485 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13660 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13660 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5430 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 5430 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1189356 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1189356 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1189356 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1189356 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 7110 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 7110 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 10837 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 10837 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 17947 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 17947 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 28222744500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 28222744500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 10638088000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 10638088000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 137094500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 137094500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 25052000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 25052000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 38860832500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 38860832500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 38860832500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 38860832500 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1578478000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1578478000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 1578478000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1578478000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.127640 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.127640 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051238 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051238 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.086683 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.086683 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.035396 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.035396 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.097043 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.097043 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.097043 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.097043 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 30092.352253 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 30092.352253 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 42301.083564 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 42301.083564 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 10036.200586 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 10036.200586 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4613.627993 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4613.627993 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 32673.844080 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 32673.844080 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 32673.844080 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 32673.844080 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 222008.157525 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 222008.157525 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 87952.192567 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 87952.192567 # average overall mshr uncacheable latency -system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states -system.cpu0.icache.tags.replacements 698827 # number of replacements -system.cpu0.icache.tags.tagsinuse 508.151884 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 47047389 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 699339 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 67.274082 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 42438027500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.151884 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.992484 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.992484 # Average percentage of cache occupancy +system.cpu0.dcache.writebacks::writebacks 681271 # number of writebacks +system.cpu0.dcache.writebacks::total 681271 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 938380 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 938380 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 255338 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 255338 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13584 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13584 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5728 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 5728 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1193718 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1193718 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1193718 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1193718 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 7073 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 7073 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 10752 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 10752 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 17825 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 17825 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 30275566000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 30275566000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 12404860000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 12404860000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 136082500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 136082500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 26226500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 26226500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 42680426000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 42680426000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 42680426000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 42680426000 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1572135500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1572135500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 1572135500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1572135500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.127860 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.127860 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051848 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051848 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.089030 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.089030 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.037675 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.037675 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.097336 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.097336 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.097336 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.097336 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 32263.652252 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 32263.652252 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 48582.114687 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 48582.114687 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 10017.851885 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 10017.851885 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4578.648743 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4578.648743 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 35754.194877 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 35754.194877 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 35754.194877 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 35754.194877 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 222272.797964 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 222272.797964 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 88198.345021 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 88198.345021 # average overall mshr uncacheable latency +system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.cpu0.icache.tags.replacements 692001 # number of replacements +system.cpu0.icache.tags.tagsinuse 507.922544 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 47007113 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 692513 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 67.879033 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 44813245500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 507.922544 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.992036 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.992036 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 349 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 163 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 435 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 11 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 48446269 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 48446269 # Number of data accesses -system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states -system.cpu0.icache.ReadReq_hits::cpu0.inst 47047389 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 47047389 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 47047389 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 47047389 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 47047389 # number of overall hits -system.cpu0.icache.overall_hits::total 47047389 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 699440 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 699440 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 699440 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 699440 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 699440 # number of overall misses -system.cpu0.icache.overall_misses::total 699440 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 10201863500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 10201863500 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 10201863500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 10201863500 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 10201863500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 10201863500 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 47746829 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 47746829 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 47746829 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 47746829 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 47746829 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 47746829 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014649 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.014649 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014649 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.014649 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014649 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.014649 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14585.759322 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14585.759322 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14585.759322 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14585.759322 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14585.759322 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14585.759322 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 48392391 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 48392391 # Number of data accesses +system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.cpu0.icache.ReadReq_hits::cpu0.inst 47007113 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 47007113 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 47007113 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 47007113 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 47007113 # number of overall hits +system.cpu0.icache.overall_hits::total 47007113 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 692639 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 692639 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 692639 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 692639 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 692639 # number of overall misses +system.cpu0.icache.overall_misses::total 692639 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 10340404000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 10340404000 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 10340404000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 10340404000 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 10340404000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 10340404000 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 47699752 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 47699752 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 47699752 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 47699752 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 47699752 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 47699752 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014521 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.014521 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014521 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.014521 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014521 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.014521 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14928.994758 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 14928.994758 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14928.994758 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 14928.994758 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14928.994758 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 14928.994758 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.writebacks::writebacks 698827 # number of writebacks -system.cpu0.icache.writebacks::total 698827 # number of writebacks -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 699440 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 699440 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 699440 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 699440 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 699440 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 699440 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 9502423500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 9502423500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 9502423500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 9502423500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 9502423500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 9502423500 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014649 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014649 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014649 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.014649 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014649 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.014649 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13585.759322 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13585.759322 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13585.759322 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 13585.759322 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13585.759322 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 13585.759322 # average overall mshr miss latency +system.cpu0.icache.writebacks::writebacks 692001 # number of writebacks +system.cpu0.icache.writebacks::total 692001 # number of writebacks +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 692639 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 692639 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 692639 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 692639 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 692639 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 692639 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 9647765000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 9647765000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 9647765000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 9647765000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 9647765000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 9647765000 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014521 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014521 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014521 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.014521 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014521 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.014521 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13928.994758 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13928.994758 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13928.994758 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 13928.994758 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13928.994758 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 13928.994758 # average overall mshr miss latency system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 2422670 # DTB read hits -system.cpu1.dtb.read_misses 2992 # DTB read misses +system.cpu1.dtb.read_hits 2442522 # DTB read hits +system.cpu1.dtb.read_misses 2621 # DTB read misses system.cpu1.dtb.read_acv 0 # DTB read access violations -system.cpu1.dtb.read_accesses 239363 # DTB read accesses -system.cpu1.dtb.write_hits 1760134 # DTB write hits -system.cpu1.dtb.write_misses 341 # DTB write misses -system.cpu1.dtb.write_acv 29 # DTB write access violations -system.cpu1.dtb.write_accesses 105247 # DTB write accesses -system.cpu1.dtb.data_hits 4182804 # DTB hits -system.cpu1.dtb.data_misses 3333 # DTB misses -system.cpu1.dtb.data_acv 29 # DTB access violations -system.cpu1.dtb.data_accesses 344610 # DTB accesses -system.cpu1.itb.fetch_hits 1965215 # ITB hits -system.cpu1.itb.fetch_misses 1216 # ITB misses +system.cpu1.dtb.read_accesses 205338 # DTB read accesses +system.cpu1.dtb.write_hits 1749235 # DTB write hits +system.cpu1.dtb.write_misses 236 # DTB write misses +system.cpu1.dtb.write_acv 24 # DTB write access violations +system.cpu1.dtb.write_accesses 89740 # DTB write accesses +system.cpu1.dtb.data_hits 4191757 # DTB hits +system.cpu1.dtb.data_misses 2857 # DTB misses +system.cpu1.dtb.data_acv 24 # DTB access violations +system.cpu1.dtb.data_accesses 295078 # DTB accesses +system.cpu1.itb.fetch_hits 1826928 # ITB hits +system.cpu1.itb.fetch_misses 1064 # ITB misses system.cpu1.itb.fetch_acv 0 # ITB acv -system.cpu1.itb.fetch_accesses 1966431 # ITB accesses +system.cpu1.itb.fetch_accesses 1827992 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -793,389 +796,387 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numPwrStateTransitions 5486 # Number of power state transitions -system.cpu1.pwrStateClkGateDist::samples 2743 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::mean 706502118.118848 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::stdev 410575500.110236 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1000-5e+10 2743 100.00% 100.00% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::min_value 98500 # Distribution of time spent in the clock gated state +system.cpu1.numPwrStateTransitions 5609 # Number of power state transitions +system.cpu1.pwrStateClkGateDist::samples 2805 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::mean 692202308.556150 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::stdev 417084374.205506 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1000-5e+10 2805 100.00% 100.00% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::min_value 82000 # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::max_value 974673500 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::total 2743 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateResidencyTicks::ON 24691263500 # Cumulative time (in ticks) in various power states -system.cpu1.pwrStateResidencyTicks::CLK_GATED 1937935310000 # Cumulative time (in ticks) in various power states -system.cpu1.numCycles 3925253147 # number of cpu cycles simulated +system.cpu1.pwrStateClkGateDist::total 2805 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateResidencyTicks::ON 25114151500 # Cumulative time (in ticks) in various power states +system.cpu1.pwrStateResidencyTicks::CLK_GATED 1941627475500 # Cumulative time (in ticks) in various power states +system.cpu1.numCycles 3931646339 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2743 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 78622 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 26563 38.35% 38.35% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1967 2.84% 41.19% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 504 0.73% 41.91% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 40238 58.09% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 69272 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 25720 48.16% 48.16% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1967 3.68% 51.84% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 504 0.94% 52.79% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 25216 47.21% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 53407 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1909399868000 97.29% 97.29% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 730527500 0.04% 97.33% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 354535500 0.02% 97.34% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 52140917500 2.66% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1962625848500 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.968264 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 2805 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 79700 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 27196 38.42% 38.42% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1969 2.78% 41.20% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 525 0.74% 41.94% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 41097 58.06% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 70787 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 26331 48.20% 48.20% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1969 3.60% 51.80% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 525 0.96% 52.76% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 25806 47.24% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 54631 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1909855366000 97.15% 97.15% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 731068500 0.04% 97.19% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 371926000 0.02% 97.21% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 54864779000 2.79% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1965823139500 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.968194 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.626671 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.770975 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.syscall::3 11 10.58% 10.58% # number of syscalls executed -system.cpu1.kern.syscall::6 10 9.62% 20.19% # number of syscalls executed -system.cpu1.kern.syscall::15 1 0.96% 21.15% # number of syscalls executed -system.cpu1.kern.syscall::17 6 5.77% 26.92% # number of syscalls executed -system.cpu1.kern.syscall::23 3 2.88% 29.81% # number of syscalls executed -system.cpu1.kern.syscall::24 3 2.88% 32.69% # number of syscalls executed -system.cpu1.kern.syscall::33 4 3.85% 36.54% # number of syscalls executed -system.cpu1.kern.syscall::45 18 17.31% 53.85% # number of syscalls executed -system.cpu1.kern.syscall::47 3 2.88% 56.73% # number of syscalls executed -system.cpu1.kern.syscall::59 1 0.96% 57.69% # number of syscalls executed -system.cpu1.kern.syscall::71 31 29.81% 87.50% # number of syscalls executed -system.cpu1.kern.syscall::74 10 9.62% 97.12% # number of syscalls executed -system.cpu1.kern.syscall::132 3 2.88% 100.00% # number of syscalls executed -system.cpu1.kern.syscall::total 104 # number of syscalls executed +system.cpu1.kern.ipl_used::31 0.627929 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.771766 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.syscall::3 10 10.87% 10.87% # number of syscalls executed +system.cpu1.kern.syscall::6 9 9.78% 20.65% # number of syscalls executed +system.cpu1.kern.syscall::15 1 1.09% 21.74% # number of syscalls executed +system.cpu1.kern.syscall::17 5 5.43% 27.17% # number of syscalls executed +system.cpu1.kern.syscall::23 3 3.26% 30.43% # number of syscalls executed +system.cpu1.kern.syscall::24 3 3.26% 33.70% # number of syscalls executed +system.cpu1.kern.syscall::33 3 3.26% 36.96% # number of syscalls executed +system.cpu1.kern.syscall::45 15 16.30% 53.26% # number of syscalls executed +system.cpu1.kern.syscall::47 3 3.26% 56.52% # number of syscalls executed +system.cpu1.kern.syscall::59 1 1.09% 57.61% # number of syscalls executed +system.cpu1.kern.syscall::71 27 29.35% 86.96% # number of syscalls executed +system.cpu1.kern.syscall::74 9 9.78% 96.74% # number of syscalls executed +system.cpu1.kern.syscall::132 3 3.26% 100.00% # number of syscalls executed +system.cpu1.kern.syscall::total 92 # number of syscalls executed system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 423 0.59% 0.59% # number of callpals executed +system.cpu1.kern.callpal::wripir 433 0.59% 0.59% # number of callpals executed system.cpu1.kern.callpal::wrmces 1 0.00% 0.59% # number of callpals executed system.cpu1.kern.callpal::wrfen 1 0.00% 0.60% # number of callpals executed -system.cpu1.kern.callpal::swpctx 2001 2.80% 3.39% # number of callpals executed -system.cpu1.kern.callpal::tbi 3 0.00% 3.40% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.01% 3.41% # number of callpals executed -system.cpu1.kern.callpal::swpipl 63023 88.06% 91.46% # number of callpals executed -system.cpu1.kern.callpal::rdps 2145 3.00% 94.46% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 94.46% # number of callpals executed -system.cpu1.kern.callpal::wrusp 4 0.01% 94.47% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.00% 94.47% # number of callpals executed -system.cpu1.kern.callpal::rti 3777 5.28% 99.75% # number of callpals executed -system.cpu1.kern.callpal::callsys 136 0.19% 99.94% # number of callpals executed -system.cpu1.kern.callpal::imb 44 0.06% 100.00% # number of callpals executed +system.cpu1.kern.callpal::swpctx 2016 2.75% 3.35% # number of callpals executed +system.cpu1.kern.callpal::tbi 3 0.00% 3.35% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.01% 3.36% # number of callpals executed +system.cpu1.kern.callpal::swpipl 64567 88.14% 91.50% # number of callpals executed +system.cpu1.kern.callpal::rdps 2334 3.19% 94.68% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 94.68% # number of callpals executed +system.cpu1.kern.callpal::wrusp 3 0.00% 94.69% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.00% 94.69% # number of callpals executed +system.cpu1.kern.callpal::rti 3725 5.08% 99.78% # number of callpals executed +system.cpu1.kern.callpal::callsys 121 0.17% 99.94% # number of callpals executed +system.cpu1.kern.callpal::imb 42 0.06% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 71571 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 2066 # number of protection mode switches -system.cpu1.kern.mode_switch::user 464 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2880 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 892 -system.cpu1.kern.mode_good::user 464 -system.cpu1.kern.mode_good::idle 428 -system.cpu1.kern.mode_switch_good::kernel 0.431752 # fraction of useful protection mode switches +system.cpu1.kern.callpal::total 73259 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 1964 # number of protection mode switches +system.cpu1.kern.mode_switch::user 367 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2923 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 816 +system.cpu1.kern.mode_good::user 367 +system.cpu1.kern.mode_good::idle 449 +system.cpu1.kern.mode_switch_good::kernel 0.415479 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.148611 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.329760 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 17773252500 0.91% 0.91% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 1704242000 0.09% 0.99% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1943148352000 99.01% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 2002 # number of times the context was actually changed -system.cpu1.committedInsts 13179937 # Number of instructions committed -system.cpu1.committedOps 13179937 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 12156604 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 173446 # Number of float alu accesses -system.cpu1.num_func_calls 411985 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1307841 # number of instructions that are conditional controls -system.cpu1.num_int_insts 12156604 # number of integer instructions -system.cpu1.num_fp_insts 173446 # number of float instructions -system.cpu1.num_int_register_reads 16739384 # number of times the integer registers were read -system.cpu1.num_int_register_writes 8921370 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 90735 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 92616 # number of times the floating registers were written -system.cpu1.num_mem_refs 4206400 # number of memory refs -system.cpu1.num_load_insts 2436997 # Number of load instructions -system.cpu1.num_store_insts 1769403 # Number of store instructions -system.cpu1.num_idle_cycles 3875870619.998025 # Number of idle cycles -system.cpu1.num_busy_cycles 49382527.001975 # Number of busy cycles -system.cpu1.not_idle_fraction 0.012581 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.987419 # Percentage of idle cycles -system.cpu1.Branches 1874664 # Number of branches fetched -system.cpu1.op_class::No_OpClass 705658 5.35% 5.35% # Class of executed instruction -system.cpu1.op_class::IntAlu 7796168 59.14% 64.49% # Class of executed instruction -system.cpu1.op_class::IntMult 21633 0.16% 64.65% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 64.65% # Class of executed instruction -system.cpu1.op_class::FloatAdd 14181 0.11% 64.76% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 64.76% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 64.76% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 64.76% # Class of executed instruction -system.cpu1.op_class::FloatDiv 1986 0.02% 64.78% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 64.78% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 64.78% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 64.78% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 64.78% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 64.78% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 64.78% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 64.78% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 64.78% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 64.78% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 64.78% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 64.78% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 64.78% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 64.78% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 64.78% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 64.78% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 64.78% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 64.78% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 64.78% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 64.78% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.78% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.78% # Class of executed instruction -system.cpu1.op_class::MemRead 2508903 19.03% 83.81% # Class of executed instruction -system.cpu1.op_class::MemWrite 1770394 13.43% 97.24% # Class of executed instruction -system.cpu1.op_class::IprAccess 364376 2.76% 100.00% # Class of executed instruction +system.cpu1.kern.mode_switch_good::idle 0.153609 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.310620 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 18376717500 0.94% 0.94% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 1492465500 0.08% 1.01% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1945081083000 98.99% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 2017 # number of times the context was actually changed +system.cpu1.committedInsts 13268743 # Number of instructions committed +system.cpu1.committedOps 13268743 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 12224543 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 175144 # Number of float alu accesses +system.cpu1.num_func_calls 423393 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 1315452 # number of instructions that are conditional controls +system.cpu1.num_int_insts 12224543 # number of integer instructions +system.cpu1.num_fp_insts 175144 # number of float instructions +system.cpu1.num_int_register_reads 16795911 # number of times the integer registers were read +system.cpu1.num_int_register_writes 8988763 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 90944 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 92918 # number of times the floating registers were written +system.cpu1.num_mem_refs 4214824 # number of memory refs +system.cpu1.num_load_insts 2456352 # Number of load instructions +system.cpu1.num_store_insts 1758472 # Number of store instructions +system.cpu1.num_idle_cycles 3881441492.340690 # Number of idle cycles +system.cpu1.num_busy_cycles 50204846.659310 # Number of busy cycles +system.cpu1.not_idle_fraction 0.012769 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.987231 # Percentage of idle cycles +system.cpu1.Branches 1899015 # Number of branches fetched +system.cpu1.op_class::No_OpClass 719201 5.42% 5.42% # Class of executed instruction +system.cpu1.op_class::IntAlu 7861154 59.23% 64.65% # Class of executed instruction +system.cpu1.op_class::IntMult 22602 0.17% 64.82% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 64.82% # Class of executed instruction +system.cpu1.op_class::FloatAdd 13252 0.10% 64.92% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 64.92% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 64.92% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 64.92% # Class of executed instruction +system.cpu1.op_class::FloatDiv 1759 0.01% 64.94% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 64.94% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 64.94% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 64.94% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 64.94% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 64.94% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 64.94% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 64.94% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 64.94% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 64.94% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 64.94% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 64.94% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 64.94% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 64.94% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 64.94% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 64.94% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 64.94% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 64.94% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 64.94% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 64.94% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.94% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.94% # Class of executed instruction +system.cpu1.op_class::MemRead 2529811 19.06% 84.00% # Class of executed instruction +system.cpu1.op_class::MemWrite 1759476 13.26% 97.25% # Class of executed instruction +system.cpu1.op_class::IprAccess 364369 2.75% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 13183299 # Class of executed instruction -system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.tags.replacements 166569 # number of replacements -system.cpu1.dcache.tags.tagsinuse 484.920851 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 4014072 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 167081 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 24.024707 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 79208580000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 484.920851 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.947111 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.947111 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 121 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 325 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 66 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 16965673 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 16965673 # Number of data accesses -system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.ReadReq_hits::cpu1.data 2258295 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 2258295 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 1642687 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 1642687 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 48217 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 48217 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 50804 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 50804 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 3900982 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 3900982 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 3900982 # number of overall hits -system.cpu1.dcache.overall_hits::total 3900982 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 118473 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 118473 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 62672 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 62672 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 8931 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 8931 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 5870 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 5870 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 181145 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 181145 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 181145 # number of overall misses -system.cpu1.dcache.overall_misses::total 181145 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1450679500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 1450679500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1216299000 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 1216299000 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 81854000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 81854000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 32847500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 32847500 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 2666978500 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 2666978500 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 2666978500 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 2666978500 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 2376768 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 2376768 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 1705359 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 1705359 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 57148 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 57148 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 56674 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 56674 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 4082127 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 4082127 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 4082127 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 4082127 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.049846 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.049846 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.036750 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.036750 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.156278 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.156278 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.103575 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.103575 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.044375 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.044375 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.044375 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.044375 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12244.811054 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 12244.811054 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 19407.374904 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 19407.374904 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9165.155078 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9165.155078 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5595.826235 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5595.826235 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14722.893262 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 14722.893262 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14722.893262 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 14722.893262 # average overall miss latency +system.cpu1.op_class::total 13271624 # Class of executed instruction +system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.tags.replacements 162095 # number of replacements +system.cpu1.dcache.tags.tagsinuse 484.320037 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 4015175 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 162424 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 24.720331 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 72635663500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 484.320037 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.945938 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.945938 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 329 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 32 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::3 297 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.642578 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 16996897 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 16996897 # Number of data accesses +system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.ReadReq_hits::cpu1.data 2273870 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 2273870 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 1634166 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 1634166 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 51918 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 51918 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 52084 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 52084 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 3908036 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 3908036 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 3908036 # number of overall hits +system.cpu1.dcache.overall_hits::total 3908036 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 118670 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 118670 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 58749 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 58749 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 9148 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 9148 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 6116 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 6116 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 177419 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 177419 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 177419 # number of overall misses +system.cpu1.dcache.overall_misses::total 177419 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1466187000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 1466187000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1296760000 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 1296760000 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 84020000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 84020000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 34172000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 34172000 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 2762947000 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 2762947000 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 2762947000 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 2762947000 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 2392540 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 2392540 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 1692915 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 1692915 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 61066 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 61066 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 58200 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 58200 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 4085455 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 4085455 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 4085455 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 4085455 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.049600 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.049600 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.034703 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.034703 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.149805 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.149805 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.105086 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.105086 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.043427 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.043427 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.043427 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.043427 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12355.161372 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 12355.161372 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 22072.886347 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 22072.886347 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9184.521207 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9184.521207 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5587.311969 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5587.311969 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15573.005146 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 15573.005146 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15573.005146 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 15573.005146 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.dcache.writebacks::writebacks 114559 # number of writebacks -system.cpu1.dcache.writebacks::total 114559 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 118473 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 118473 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 62672 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 62672 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 8931 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 8931 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 5870 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 5870 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 181145 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 181145 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 181145 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 181145 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 89 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.ReadReq_mshr_uncacheable::total 89 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 3221 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 3221 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 3310 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 3310 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1332206500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1332206500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1153627000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1153627000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 72923000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 72923000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 26977500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 26977500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2485833500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 2485833500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2485833500 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 2485833500 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 20174000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 20174000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 20174000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 20174000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.049846 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.049846 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036750 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.036750 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.156278 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.156278 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.103575 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.103575 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.044375 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.044375 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.044375 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.044375 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11244.811054 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11244.811054 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 18407.374904 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 18407.374904 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8165.155078 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8165.155078 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 4595.826235 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 4595.826235 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 13722.893262 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 13722.893262 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13722.893262 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 13722.893262 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 226674.157303 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 226674.157303 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 6094.864048 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 6094.864048 # average overall mshr uncacheable latency -system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states -system.cpu1.icache.tags.replacements 316020 # number of replacements -system.cpu1.icache.tags.tagsinuse 445.922081 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 12866727 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 316532 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 40.649056 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 1960698705500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 445.922081 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.870942 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.870942 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 444 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::3 13 # Occupied blocks per task id -system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 13499873 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 13499873 # Number of data accesses -system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states -system.cpu1.icache.ReadReq_hits::cpu1.inst 12866727 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 12866727 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 12866727 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 12866727 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 12866727 # number of overall hits -system.cpu1.icache.overall_hits::total 12866727 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 316573 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 316573 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 316573 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 316573 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 316573 # number of overall misses -system.cpu1.icache.overall_misses::total 316573 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4250508000 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 4250508000 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 4250508000 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 4250508000 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 4250508000 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 4250508000 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 13183300 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 13183300 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 13183300 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 13183300 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 13183300 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 13183300 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024013 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.024013 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024013 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.024013 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024013 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.024013 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13426.628297 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13426.628297 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13426.628297 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13426.628297 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13426.628297 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13426.628297 # average overall miss latency +system.cpu1.dcache.writebacks::writebacks 111600 # number of writebacks +system.cpu1.dcache.writebacks::total 111600 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 118670 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 118670 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 58749 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 58749 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 9148 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 9148 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 6116 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 6116 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 177419 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 177419 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 177419 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 177419 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 125 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 125 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 3371 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 3371 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 3496 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 3496 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1347517000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1347517000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1238011000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1238011000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 74872000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 74872000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 28056000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 28056000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2585528000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 2585528000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2585528000 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 2585528000 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 26291000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 26291000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 26291000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 26291000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.049600 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.049600 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.034703 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.034703 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.149805 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.149805 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.105086 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.105086 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.043427 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.043427 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.043427 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.043427 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11355.161372 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11355.161372 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 21072.886347 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 21072.886347 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8184.521207 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8184.521207 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 4587.311969 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 4587.311969 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14573.005146 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14573.005146 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14573.005146 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 14573.005146 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 210328 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 210328 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 7520.308924 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 7520.308924 # average overall mshr uncacheable latency +system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.cpu1.icache.tags.replacements 326538 # number of replacements +system.cpu1.icache.tags.tagsinuse 445.783445 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 12944535 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 327049 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 39.579803 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 1960887554500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 445.783445 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.870671 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.870671 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 75 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 434 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::4 2 # Occupied blocks per task id +system.cpu1.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id +system.cpu1.icache.tags.tag_accesses 13598713 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 13598713 # Number of data accesses +system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.cpu1.icache.ReadReq_hits::cpu1.inst 12944535 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 12944535 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 12944535 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 12944535 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 12944535 # number of overall hits +system.cpu1.icache.overall_hits::total 12944535 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 327089 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 327089 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 327089 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 327089 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 327089 # number of overall misses +system.cpu1.icache.overall_misses::total 327089 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4450039000 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 4450039000 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 4450039000 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 4450039000 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 4450039000 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 4450039000 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 13271624 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 13271624 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 13271624 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 13271624 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 13271624 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 13271624 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024646 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.024646 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024646 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.024646 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024646 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.024646 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13604.979073 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13604.979073 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13604.979073 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13604.979073 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13604.979073 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13604.979073 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.icache.writebacks::writebacks 316020 # number of writebacks -system.cpu1.icache.writebacks::total 316020 # number of writebacks -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 316573 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 316573 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 316573 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 316573 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 316573 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 316573 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3933935000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 3933935000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3933935000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 3933935000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3933935000 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 3933935000 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024013 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024013 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024013 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.024013 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024013 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.024013 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12426.628297 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12426.628297 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12426.628297 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 12426.628297 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12426.628297 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 12426.628297 # average overall mshr miss latency +system.cpu1.icache.writebacks::writebacks 326538 # number of writebacks +system.cpu1.icache.writebacks::total 326538 # number of writebacks +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 327089 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 327089 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 327089 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 327089 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 327089 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 327089 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4122950000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 4122950000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4122950000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 4122950000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4122950000 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 4122950000 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024646 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024646 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024646 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.024646 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024646 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.024646 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12604.979073 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12604.979073 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12604.979073 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 12604.979073 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12604.979073 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 12604.979073 # average overall mshr miss latency system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -1188,13 +1189,13 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.iobus.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states -system.iobus.trans_dist::ReadReq 7375 # Transaction distribution -system.iobus.trans_dist::ReadResp 7375 # Transaction distribution -system.iobus.trans_dist::WriteReq 55610 # Transaction distribution -system.iobus.trans_dist::WriteResp 55610 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 13904 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1014 # Packet count per connected master and slave (bytes) +system.iobus.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.iobus.trans_dist::ReadReq 7376 # Transaction distribution +system.iobus.trans_dist::ReadResp 7376 # Transaction distribution +system.iobus.trans_dist::WriteReq 55675 # Transaction distribution +system.iobus.trans_dist::WriteResp 55675 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 14036 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1010 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) @@ -1202,12 +1203,12 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 1814 system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2474 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 42514 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83456 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::total 83456 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 125970 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 55616 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2749 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 42642 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83460 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::total 83460 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 126102 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 56144 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2733 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) @@ -1215,74 +1216,74 @@ system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9074 system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9876 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 81882 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661632 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.tsunami.ide.dma::total 2661632 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2743514 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 14952500 # Layer occupancy (ticks) +system.iobus.pkt_size_system.bridge.master::total 82394 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661648 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.tsunami.ide.dma::total 2661648 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2744042 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 15108500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 763000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 758000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer6.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer22.occupancy 175000 # Layer occupancy (ticks) +system.iobus.reqLayer22.occupancy 174000 # Layer occupancy (ticks) system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 15838000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 15840500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer24.occupancy 2459000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 6057500 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 6051000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 82500 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 216134056 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 216235265 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 28456000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 28519000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 41952000 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 41956000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states -system.iocache.tags.replacements 41696 # number of replacements -system.iocache.tags.tagsinuse 0.568010 # Cycle average of tags in use +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.iocache.tags.replacements 41698 # number of replacements +system.iocache.tags.tagsinuse 0.568421 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 41712 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 41714 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1756490226000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 0.568010 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.035501 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.035501 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1760410342000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 0.568421 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.035526 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.035526 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 375552 # Number of tag accesses -system.iocache.tags.data_accesses 375552 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states -system.iocache.ReadReq_misses::tsunami.ide 176 # number of ReadReq misses -system.iocache.ReadReq_misses::total 176 # number of ReadReq misses +system.iocache.tags.tag_accesses 375570 # Number of tag accesses +system.iocache.tags.data_accesses 375570 # Number of data accesses +system.iocache.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.iocache.ReadReq_misses::tsunami.ide 178 # number of ReadReq misses +system.iocache.ReadReq_misses::total 178 # number of ReadReq misses system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses -system.iocache.demand_misses::tsunami.ide 41728 # number of demand (read+write) misses -system.iocache.demand_misses::total 41728 # number of demand (read+write) misses -system.iocache.overall_misses::tsunami.ide 41728 # number of overall misses -system.iocache.overall_misses::total 41728 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 22088883 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 22088883 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::tsunami.ide 4858687173 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4858687173 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 4880776056 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 4880776056 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 4880776056 # number of overall miss cycles -system.iocache.overall_miss_latency::total 4880776056 # number of overall miss cycles -system.iocache.ReadReq_accesses::tsunami.ide 176 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 176 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::tsunami.ide 41730 # number of demand (read+write) misses +system.iocache.demand_misses::total 41730 # number of demand (read+write) misses +system.iocache.overall_misses::tsunami.ide 41730 # number of overall misses +system.iocache.overall_misses::total 41730 # number of overall misses +system.iocache.ReadReq_miss_latency::tsunami.ide 22412883 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 22412883 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::tsunami.ide 4956087382 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4956087382 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 4978500265 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 4978500265 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 4978500265 # number of overall miss cycles +system.iocache.overall_miss_latency::total 4978500265 # number of overall miss cycles +system.iocache.ReadReq_accesses::tsunami.ide 178 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 178 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 41728 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 41728 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 41728 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 41728 # number of overall (read+write) accesses +system.iocache.demand_accesses::tsunami.ide 41730 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 41730 # number of demand (read+write) accesses +system.iocache.overall_accesses::tsunami.ide 41730 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 41730 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses @@ -1291,38 +1292,38 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125505.017045 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 125505.017045 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 116930.284294 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 116930.284294 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 116966.450729 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 116966.450729 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 116966.450729 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 116966.450729 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 16 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125915.073034 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 125915.073034 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 119274.340152 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 119274.340152 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 119302.666307 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 119302.666307 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 119302.666307 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 119302.666307 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 1665 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 2 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 10 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 166.500000 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 41520 # number of writebacks system.iocache.writebacks::total 41520 # number of writebacks -system.iocache.ReadReq_mshr_misses::tsunami.ide 176 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 176 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::tsunami.ide 178 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 178 # number of ReadReq MSHR misses system.iocache.WriteLineReq_mshr_misses::tsunami.ide 41552 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 41552 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 41728 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 41728 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 41728 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 41728 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13288883 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 13288883 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2778678942 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2778678942 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 2791967825 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 2791967825 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 2791967825 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 2791967825 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::tsunami.ide 41730 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 41730 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 41730 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 41730 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13512883 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 13512883 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2876027417 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2876027417 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 2889540300 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 2889540300 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 2889540300 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 2889540300 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1331,196 +1332,196 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 75505.017045 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 75505.017045 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 66872.327253 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 66872.327253 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 66908.738137 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 66908.738137 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 66908.738137 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 66908.738137 # average overall mshr miss latency -system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states -system.l2c.tags.replacements 341251 # number of replacements -system.l2c.tags.tagsinuse 65397.203087 # Cycle average of tags in use -system.l2c.tags.total_refs 3991452 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 406774 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 9.812456 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 7305719000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 281.092347 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4857.550126 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 59344.826381 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 110.880269 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 802.853964 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.004289 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.074120 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.905530 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.001692 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.012251 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.997882 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 65523 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 485 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 770 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 6255 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 57986 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.999802 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 35595123 # Number of tag accesses -system.l2c.tags.data_accesses 35595123 # Number of data accesses -system.l2c.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states -system.l2c.WritebackDirty_hits::writebacks 793736 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 793736 # number of WritebackDirty hits -system.l2c.WritebackClean_hits::writebacks 747944 # number of WritebackClean hits -system.l2c.WritebackClean_hits::total 747944 # number of WritebackClean hits -system.l2c.UpgradeReq_hits::cpu0.data 3115 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 2258 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 5373 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 912 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 927 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 1839 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 126843 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 47590 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 174433 # number of ReadExReq hits -system.l2c.ReadCleanReq_hits::cpu0.inst 686424 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu1.inst 316124 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::total 1002548 # number of ReadCleanReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 663180 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 109254 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 772434 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.inst 686424 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 790023 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 316124 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 156844 # number of demand (read+write) hits -system.l2c.demand_hits::total 1949415 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 686424 # number of overall hits -system.l2c.overall_hits::cpu0.data 790023 # number of overall hits -system.l2c.overall_hits::cpu1.inst 316124 # number of overall hits -system.l2c.overall_hits::cpu1.data 156844 # number of overall hits -system.l2c.overall_hits::total 1949415 # number of overall hits +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 75915.073034 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 75915.073034 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 69215.138068 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 69215.138068 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 69243.716751 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 69243.716751 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 69243.716751 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 69243.716751 # average overall mshr miss latency +system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.l2c.tags.replacements 342937 # number of replacements +system.l2c.tags.tagsinuse 65389.954388 # Cycle average of tags in use +system.l2c.tags.total_refs 3989146 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 408458 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 9.766355 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 7750506000 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 285.827023 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4791.190703 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 59306.187710 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 166.825599 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 839.923352 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.004361 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.073108 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.904941 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.002546 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.012816 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.997772 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1024 65521 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 23 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 697 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 1597 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 6182 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 57022 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1024 0.999771 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 35591920 # Number of tag accesses +system.l2c.tags.data_accesses 35591920 # Number of data accesses +system.l2c.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.l2c.WritebackDirty_hits::writebacks 792871 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 792871 # 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mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.173230 # mshr miss rate for overall accesses system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 50000 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19500 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 44916.666667 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 67128.746754 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 72597.285782 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 67414.036388 # average ReadExReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 71685.802232 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 72461.098398 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 71711.025908 # average ReadCleanReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 63242.401431 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 69739.316239 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 63247.992806 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 71685.802232 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 64399.203973 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72461.098398 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 72495.510577 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 64771.410451 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 71685.802232 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 64399.203973 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72461.098398 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 72495.510577 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 64771.410451 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 209503.516174 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 214168.539326 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 209561.189054 # average ReadReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 82998.272692 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 5758.610272 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 70971.021311 # average overall mshr uncacheable latency -system.membus.snoop_filter.tot_requests 851905 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 404237 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 411 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18500 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 44750 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 80922.669691 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 92439.554448 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 81522.486998 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 93000.321414 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 92837.090164 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 92988.450935 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 70829.226163 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 113794.117647 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 70882.960527 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 93000.321414 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 73865.729618 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 92837.090164 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 93513.759432 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 74819.025425 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 93000.321414 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 73865.729618 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 92837.090164 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 93513.759432 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 74819.025425 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 209766.859890 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 197824 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 209559.460961 # average ReadReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 83235.960729 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 7073.226545 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 70747.572816 # average overall mshr uncacheable latency +system.membus.snoop_filter.tot_requests 856503 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 407142 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 413 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 7199 # Transaction distribution -system.membus.trans_dist::ReadResp 292704 # Transaction distribution -system.membus.trans_dist::WriteReq 14058 # Transaction distribution -system.membus.trans_dist::WriteResp 14058 # Transaction distribution -system.membus.trans_dist::WritebackDirty 120323 # Transaction distribution -system.membus.trans_dist::CleanEvict 261806 # Transaction distribution -system.membus.trans_dist::UpgradeReq 11056 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 9461 # Transaction distribution +system.membus.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadReq 7198 # Transaction distribution +system.membus.trans_dist::ReadResp 292654 # Transaction distribution +system.membus.trans_dist::WriteReq 14123 # Transaction distribution +system.membus.trans_dist::WriteResp 14123 # Transaction distribution +system.membus.trans_dist::WritebackDirty 121489 # Transaction distribution +system.membus.trans_dist::CleanEvict 262335 # Transaction distribution +system.membus.trans_dist::UpgradeReq 11693 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 9938 # Transaction distribution system.membus.trans_dist::UpgradeResp 3 # Transaction distribution -system.membus.trans_dist::ReadExReq 122183 # Transaction distribution -system.membus.trans_dist::ReadExResp 121347 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 285505 # Transaction distribution +system.membus.trans_dist::ReadExReq 123969 # Transaction distribution +system.membus.trans_dist::ReadExResp 123101 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 285456 # Transaction distribution system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 42514 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1174875 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 1217389 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83439 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 83439 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1300828 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 81882 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31053824 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 31135706 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 42642 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1181120 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 1223762 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83443 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 83443 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1307205 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 82394 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31237440 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 31319834 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2658240 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2658240 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 33793946 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 21651 # Total snoops (count) -system.membus.snoopTraffic 27136 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 491014 # Request fanout histogram -system.membus.snoop_fanout::mean 0.001340 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.036583 # Request fanout histogram +system.membus.pkt_size::total 33978074 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 22774 # Total snoops (count) +system.membus.snoopTraffic 27264 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 493929 # Request fanout histogram +system.membus.snoop_fanout::mean 0.001371 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.036997 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 490356 99.87% 99.87% # Request fanout histogram -system.membus.snoop_fanout::1 658 0.13% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 493252 99.86% 99.86% # Request fanout histogram +system.membus.snoop_fanout::1 677 0.14% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 491014 # Request fanout histogram -system.membus.reqLayer0.occupancy 40347000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 493929 # Request fanout histogram +system.membus.reqLayer0.occupancy 40493000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1314918038 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1323047597 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 2173304250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2182313750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 904117 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 915117 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states -system.toL2Bus.snoop_filter.tot_requests 4781747 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 2390985 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 355114 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 992 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 932 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 60 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states -system.toL2Bus.trans_dist::ReadReq 7199 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2102308 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 14058 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 14058 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 872539 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 1014847 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 815207 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 16306 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 11300 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 27606 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 297851 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 297851 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 1016013 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 1079098 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 229 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2097686 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3605272 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 949165 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 535742 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7187865 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 89487744 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 118850496 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 40485888 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 17815770 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 266639898 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 398766 # Total snoops (count) -system.toL2Bus.snoopTraffic 7394432 # Total snoop traffic (bytes) -system.toL2Bus.snoop_fanout::samples 2783305 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.138476 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.345638 # Request fanout histogram +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.toL2Bus.snoop_filter.tot_requests 4789247 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 2394847 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 361788 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 989 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 928 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 61 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.toL2Bus.trans_dist::ReadReq 7198 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2106871 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 14123 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 14123 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 872840 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 1018539 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 815364 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 17050 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 11844 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 28894 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 297037 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 297037 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 1019728 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 1079947 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 246 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2077258 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3616236 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 980715 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 523549 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7197758 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 88615616 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 119196292 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 41832064 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 17309590 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 266953562 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 403246 # Total snoops (count) +system.toL2Bus.snoopTraffic 7576960 # Total snoop traffic (bytes) +system.toL2Bus.snoop_fanout::samples 2790110 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.141029 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.348296 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 2398113 86.16% 86.16% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 384964 13.83% 99.99% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 227 0.01% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 2396861 85.91% 85.91% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 393013 14.09% 99.99% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 235 0.01% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::3 1 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 2783305 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 4217117493 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 2790110 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 4223757496 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 299383 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 302383 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1049361097 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1039141633 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1811830165 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 1817975093 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 476124465 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 491872018 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 281628843 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 276251327 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states -system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states -system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states -system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states +system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -1788,28 +1789,28 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states -system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states -system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states -system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states -system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1962626573500 # Cumulative time (in ticks) in various power states +system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states +system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/system.terminal b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/system.terminal index b603b455c..fff26b301 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/system.terminal +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/system.terminal @@ -27,7 +27,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
memcluster 1, usage 0, start 392, end 16384
freeing pages 1069:16384
reserving pages 1069:1070 -
4096K Bcache detected; load hit latency 38 cycles, load miss latency 162 cycles +
4096K Bcache detected; load hit latency 38 cycles, load miss latency 175 cycles
SMP: 2 CPUs probed -- cpu_present_mask = 3
Built 1 zonelists
Kernel command line: root=/dev/hda1 console=ttyS0 diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini index b5a7841a1..7a4d88e30 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini @@ -25,7 +25,7 @@ kernel_addr_check=true load_addr_mask=1099511627775 load_offset=0 mem_mode=timing -mem_ranges=0:134217727 +mem_ranges=0:134217727:0:0:0:0 memories=system.physmem mmap_using_noreserve=false multi_thread=false @@ -60,7 +60,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -ranges=8796093022208:18446744073709551615 +ranges=8796093022208:18446744073709551615:0:0:0:0 req_size=16 resp_size=16 master=system.iobus.slave[0] @@ -115,7 +115,7 @@ icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=4 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -166,7 +166,7 @@ size=64 [system.cpu.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=1 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -226,7 +226,7 @@ size=48 [system.cpu.l2cache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -389,7 +389,7 @@ slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma [system.iocache] type=Cache children=tags -addr_ranges=0:134217727 +addr_ranges=0:134217727:0:0:0:0 assoc=8 clk_domain=system.clk_domain clusivity=mostly_incl @@ -434,7 +434,7 @@ size=1024 [system.membus] type=CoherentXBar -children=badaddr_responder +children=badaddr_responder snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -446,7 +446,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -478,29 +478,36 @@ update_data=false warn_access= pio=system.membus.default +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -520,6 +527,7 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 @@ -529,7 +537,7 @@ p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 page_policy=open_adaptive power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 @@ -551,9 +559,9 @@ tRTW=2500 tWR=15000 tWTR=7500 tXAW=30000 -tXP=0 +tXP=6000 tXPDLL=0 -tXS=0 +tXS=270000 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout index ef6ffb4a6..1d59c0edc 100755 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout @@ -3,13 +3,13 @@ Redirecting stderr to build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/t gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 19 2016 12:23:51 -gem5 started Jul 19 2016 12:24:24 -gem5 executing on e108600-lin, pid 39578 +gem5 compiled Oct 11 2016 00:00:58 +gem5 started Oct 13 2016 20:19:45 +gem5 executing on e108600-lin, pid 28068 command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing Global frequency set at 1000000000000 ticks per second info: kernel located at: /arm/projectscratch/randd/systems/dist/binaries/vmlinux 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 1941275996000 because m5_exit instruction encountered +Exiting @ tick 1926421414000 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt index 23c45cb03..e8b92466f 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt @@ -1,108 +1,108 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.922415 # Number of seconds simulated -sim_ticks 1922415409000 # Number of ticks simulated -final_tick 1922415409000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.926421 # Number of seconds simulated +sim_ticks 1926421414000 # Number of ticks simulated +final_tick 1926421414000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 933149 # Simulator instruction rate (inst/s) -host_op_rate 933149 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 31931169584 # Simulator tick rate (ticks/s) -host_mem_usage 334404 # Number of bytes of host memory used -host_seconds 60.21 # Real time elapsed on the host -sim_insts 56180200 # Number of instructions simulated -sim_ops 56180200 # Number of ops (including micro ops) simulated +host_inst_rate 779030 # Simulator instruction rate (inst/s) +host_op_rate 779030 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 26705916367 # Simulator tick rate (ticks/s) +host_mem_usage 331544 # Number of bytes of host memory used +host_seconds 72.13 # Real time elapsed on the host +sim_insts 56195014 # Number of instructions simulated +sim_ops 56195014 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 844608 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24856576 # Number of bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 844672 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24856896 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 25702144 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 844608 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 844608 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7408512 # Number of bytes written to this memory -system.physmem.bytes_written::total 7408512 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 13197 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388384 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 25702528 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 844672 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 844672 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7408960 # Number of bytes written to this memory +system.physmem.bytes_written::total 7408960 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 13198 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388389 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 401596 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 115758 # Number of write requests responded to by this memory -system.physmem.num_writes::total 115758 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 439347 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 12929867 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 499 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13369714 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 439347 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 439347 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3853752 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3853752 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3853752 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 439347 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 12929867 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 499 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17223466 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 401596 # Number of read requests accepted -system.physmem.writeReqs 115758 # Number of write requests accepted -system.physmem.readBursts 401596 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 115758 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 25695616 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 6528 # Total number of bytes read from write queue -system.physmem.bytesWritten 7407424 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 25702144 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7408512 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 102 # Number of DRAM read bursts serviced by the write queue +system.physmem.num_reads::total 401602 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 115765 # Number of write requests responded to by this memory +system.physmem.num_writes::total 115765 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 438467 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 12903146 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 498 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 13342111 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 438467 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 438467 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3845971 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3845971 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3845971 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 438467 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 12903146 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 498 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 17188081 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 401602 # Number of read requests accepted +system.physmem.writeReqs 115765 # Number of write requests accepted +system.physmem.readBursts 401602 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 115765 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 25695552 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 6976 # Total number of bytes read from write queue +system.physmem.bytesWritten 7408000 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 25702528 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7408960 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 109 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 25227 # Per bank write bursts -system.physmem.perBankRdBursts::1 25633 # Per bank write bursts -system.physmem.perBankRdBursts::2 25570 # Per bank write bursts -system.physmem.perBankRdBursts::3 25510 # Per bank write bursts -system.physmem.perBankRdBursts::4 24963 # Per bank write bursts -system.physmem.perBankRdBursts::5 24975 # Per bank write bursts -system.physmem.perBankRdBursts::6 24200 # Per bank write bursts +system.physmem.perBankRdBursts::0 25229 # Per bank write bursts +system.physmem.perBankRdBursts::1 25631 # Per bank write bursts +system.physmem.perBankRdBursts::2 25563 # Per bank write bursts +system.physmem.perBankRdBursts::3 25503 # Per bank write bursts +system.physmem.perBankRdBursts::4 24978 # Per bank write bursts +system.physmem.perBankRdBursts::5 24964 # Per bank write bursts +system.physmem.perBankRdBursts::6 24209 # Per bank write bursts system.physmem.perBankRdBursts::7 24494 # Per bank write bursts -system.physmem.perBankRdBursts::8 25179 # Per bank write bursts -system.physmem.perBankRdBursts::9 24767 # Per bank write bursts -system.physmem.perBankRdBursts::10 25265 # Per bank write bursts -system.physmem.perBankRdBursts::11 24877 # Per bank write bursts -system.physmem.perBankRdBursts::12 24504 # Per bank write bursts -system.physmem.perBankRdBursts::13 25368 # Per bank write bursts +system.physmem.perBankRdBursts::8 25180 # Per bank write bursts +system.physmem.perBankRdBursts::9 24757 # Per bank write bursts +system.physmem.perBankRdBursts::10 25269 # Per bank write bursts +system.physmem.perBankRdBursts::11 24873 # Per bank write bursts +system.physmem.perBankRdBursts::12 24512 # Per bank write bursts +system.physmem.perBankRdBursts::13 25367 # Per bank write bursts system.physmem.perBankRdBursts::14 25615 # Per bank write bursts -system.physmem.perBankRdBursts::15 25347 # Per bank write bursts -system.physmem.perBankWrBursts::0 7623 # Per bank write bursts -system.physmem.perBankWrBursts::1 7643 # Per bank write bursts -system.physmem.perBankWrBursts::2 7871 # Per bank write bursts -system.physmem.perBankWrBursts::3 7543 # Per bank write bursts -system.physmem.perBankWrBursts::4 7113 # Per bank write bursts -system.physmem.perBankWrBursts::5 6990 # Per bank write bursts -system.physmem.perBankWrBursts::6 6317 # Per bank write bursts -system.physmem.perBankWrBursts::7 6320 # Per bank write bursts -system.physmem.perBankWrBursts::8 7316 # Per bank write bursts -system.physmem.perBankWrBursts::9 6519 # Per bank write bursts -system.physmem.perBankWrBursts::10 7114 # Per bank write bursts -system.physmem.perBankWrBursts::11 6905 # Per bank write bursts -system.physmem.perBankWrBursts::12 7090 # Per bank write bursts +system.physmem.perBankRdBursts::15 25349 # Per bank write bursts +system.physmem.perBankWrBursts::0 7626 # Per bank write bursts +system.physmem.perBankWrBursts::1 7640 # Per bank write bursts +system.physmem.perBankWrBursts::2 7866 # Per bank write bursts +system.physmem.perBankWrBursts::3 7539 # Per bank write bursts +system.physmem.perBankWrBursts::4 7128 # Per bank write bursts +system.physmem.perBankWrBursts::5 6982 # Per bank write bursts +system.physmem.perBankWrBursts::6 6324 # Per bank write bursts +system.physmem.perBankWrBursts::7 6321 # Per bank write bursts +system.physmem.perBankWrBursts::8 7317 # Per bank write bursts +system.physmem.perBankWrBursts::9 6511 # Per bank write bursts +system.physmem.perBankWrBursts::10 7117 # Per bank write bursts +system.physmem.perBankWrBursts::11 6900 # Per bank write bursts +system.physmem.perBankWrBursts::12 7101 # Per bank write bursts system.physmem.perBankWrBursts::13 7827 # Per bank write bursts system.physmem.perBankWrBursts::14 7864 # Per bank write bursts -system.physmem.perBankWrBursts::15 7686 # Per bank write bursts +system.physmem.perBankWrBursts::15 7687 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 12 # Number of times write queue was full causing retry -system.physmem.totGap 1922403535500 # Total gap between requests +system.physmem.numWrRetry 65 # Number of times write queue was full causing retry +system.physmem.totGap 1926409540500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 401596 # Read request sizes (log2) +system.physmem.readPktSize::6 401602 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 115758 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 401480 # What read queue length does an incoming req see +system.physmem.writePktSize::6 115765 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 401479 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see @@ -149,197 +149,192 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1798 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3043 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5632 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5708 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6464 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6441 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7460 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 8593 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 6948 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7656 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 8317 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7511 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 6845 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6921 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6031 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5597 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5475 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5364 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 235 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 218 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 176 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 145 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 101 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 165 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 158 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 160 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 132 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 165 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 165 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 168 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 154 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 133 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 149 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 158 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 193 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 133 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 131 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 63 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 71 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 69 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 84 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 69 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 49 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 44 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 22 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 29 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 63567 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 520.758255 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 315.623593 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 415.134860 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 14658 23.06% 23.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 11541 18.16% 41.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4861 7.65% 48.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3298 5.19% 54.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2285 3.59% 57.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1919 3.02% 60.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1565 2.46% 63.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1066 1.68% 64.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 22374 35.20% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 63567 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5112 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 78.539124 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2951.473216 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 5109 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1555 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2761 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5433 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5447 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5972 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6087 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6885 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7936 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 6558 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6936 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7510 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7184 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 6518 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6660 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5973 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5861 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5660 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5576 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 497 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 477 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 395 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 374 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 327 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 340 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 292 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 286 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 316 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 351 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 363 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 345 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 332 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 283 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 347 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 309 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 304 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 296 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 281 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 260 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 211 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 202 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 216 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 341 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 238 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 176 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 335 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 300 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 190 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 95 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 159 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 63474 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 521.529319 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 315.079750 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 415.298836 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 14953 23.56% 23.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 11433 18.01% 41.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4319 6.80% 48.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3083 4.86% 53.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3219 5.07% 58.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1509 2.38% 60.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1583 2.49% 63.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 998 1.57% 64.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 22377 35.25% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 63474 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5049 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 79.519311 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2969.676150 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 5046 99.94% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5112 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5112 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 22.641041 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 19.167929 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 21.759533 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 4475 87.54% 87.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 34 0.67% 88.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 11 0.22% 88.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 14 0.27% 88.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 223 4.36% 93.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 16 0.31% 93.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 14 0.27% 93.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 12 0.23% 93.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 3 0.06% 93.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 7 0.14% 94.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 5 0.10% 94.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 2 0.04% 94.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 12 0.23% 94.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 2 0.04% 94.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 3 0.06% 94.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 1 0.02% 94.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 33 0.65% 95.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 3 0.06% 95.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 18 0.35% 95.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 1 0.02% 95.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 174 3.40% 99.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 4 0.08% 99.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 1 0.02% 99.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 4 0.08% 99.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 2 0.04% 99.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 2 0.04% 99.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 2 0.04% 99.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 1 0.02% 99.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 1 0.02% 99.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 1 0.02% 99.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 1 0.02% 99.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 1 0.02% 99.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 4 0.08% 99.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 1 0.02% 99.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 9 0.18% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 2 0.04% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 2 0.04% 99.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 3 0.06% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::196-199 1 0.02% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-211 1 0.02% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-227 5 0.10% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::248-251 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5112 # Writes before turning the bus around for reads -system.physmem.totQLat 2082530750 # Total ticks spent queuing -system.physmem.totMemAccLat 9610543250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2007470000 # Total ticks spent in databus transfers -system.physmem.avgQLat 5186.95 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5049 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5049 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.925332 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.952060 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 24.989890 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 4540 89.92% 89.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 33 0.65% 90.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 164 3.25% 93.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 7 0.14% 93.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 1 0.02% 93.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 14 0.28% 94.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 7 0.14% 94.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 4 0.08% 94.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 36 0.71% 95.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 2 0.04% 95.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 139 2.75% 97.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 18 0.36% 98.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-119 13 0.26% 98.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-127 3 0.06% 98.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 6 0.12% 98.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-143 6 0.12% 98.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-159 3 0.06% 98.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-167 2 0.04% 98.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 13 0.26% 99.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 4 0.08% 99.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-191 12 0.24% 99.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-199 10 0.20% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-207 1 0.02% 99.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-215 1 0.02% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-223 6 0.12% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-231 2 0.04% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-263 2 0.04% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5049 # Writes before turning the bus around for reads +system.physmem.totQLat 6110965000 # Total ticks spent queuing +system.physmem.totMemAccLat 13638958750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2007465000 # Total ticks spent in databus transfers +system.physmem.avgQLat 15220.60 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 23936.95 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 13.37 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 33970.60 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 13.34 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 3.85 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 13.37 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 13.34 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 3.85 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.13 # Data bus utilization in percentage system.physmem.busUtilRead 0.10 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.01 # Average write queue length when enqueuing -system.physmem.readRowHits 359878 # Number of row buffer hits during reads -system.physmem.writeRowHits 93790 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.63 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 81.02 # Row buffer hit rate for writes -system.physmem.avgGap 3715837.77 # Average gap between requests -system.physmem.pageHitRate 87.71 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 235297440 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 128386500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1564461600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 372081600 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 125562446880 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 64706229855 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1096686028500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1289254932375 # Total energy per rank (pJ) -system.physmem_0.averagePower 670.645215 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 1824198256500 # Time in different power states -system.physmem_0.memoryStateTime::REF 64193480000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 34018076000 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 245269080 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 133827375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1567191600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 377920080 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 125562446880 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 65408106195 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1096070355750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1289365116960 # Total energy per rank (pJ) -system.physmem_1.averagePower 670.702526 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1823171088500 # Time in different power states -system.physmem_1.memoryStateTime::REF 64193480000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 35045257750 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states +system.physmem.avgWrQLen 24.93 # Average write queue length when enqueuing +system.physmem.readRowHits 360227 # Number of row buffer hits during reads +system.physmem.writeRowHits 93542 # Number of row buffer hits during writes +system.physmem.readRowHitRate 89.72 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 80.80 # Row buffer hit rate for writes +system.physmem.avgGap 3723487.47 # Average gap between requests +system.physmem.pageHitRate 87.73 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 220840200 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 117379350 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1432076940 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 299763720 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 5519467200.000001 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 5038358250 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 366301440 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 13030830420 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 6357713760 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 449603447400 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 481990669050 # Total energy per rank (pJ) +system.physmem_0.averagePower 250.200016 # Core power per rank (mW) +system.physmem_0.totalIdleTime 1914256960750 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 613825000 # Time in different power states +system.physmem_0.memoryStateTime::REF 2347892000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 1869275563500 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 16556600250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 9050884750 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 28576648500 # Time in different power states +system.physmem_1.actEnergy 232364160 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 123504480 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1434583080 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 304451280 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 5706932400.000001 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 5157840510 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 361297920 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 13647845730 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 6595007040 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 449082638955 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 482651277075 # Total energy per rank (pJ) +system.physmem_1.averagePower 250.542936 # Core power per rank (mW) +system.physmem_1.totalIdleTime 1914153639500 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 598128250 # Time in different power states +system.physmem_1.memoryStateTime::REF 2427510000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 1867054823500 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 17174624250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 9236704750 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 29929623250 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9064160 # DTB read hits -system.cpu.dtb.read_misses 10312 # DTB read misses +system.cpu.dtb.read_hits 9066536 # DTB read hits +system.cpu.dtb.read_misses 10331 # DTB read misses system.cpu.dtb.read_acv 210 # DTB read access violations -system.cpu.dtb.read_accesses 728817 # DTB read accesses -system.cpu.dtb.write_hits 6356116 # DTB write hits -system.cpu.dtb.write_misses 1140 # DTB write misses +system.cpu.dtb.read_accesses 728865 # DTB read accesses +system.cpu.dtb.write_hits 6357492 # DTB write hits +system.cpu.dtb.write_misses 1143 # DTB write misses system.cpu.dtb.write_acv 157 # DTB write access violations -system.cpu.dtb.write_accesses 291929 # DTB write accesses -system.cpu.dtb.data_hits 15420276 # DTB hits -system.cpu.dtb.data_misses 11452 # DTB misses +system.cpu.dtb.write_accesses 291932 # DTB write accesses +system.cpu.dtb.data_hits 15424028 # DTB hits +system.cpu.dtb.data_misses 11474 # DTB misses system.cpu.dtb.data_acv 367 # DTB access violations -system.cpu.dtb.data_accesses 1020746 # DTB accesses -system.cpu.itb.fetch_hits 4973965 # ITB hits -system.cpu.itb.fetch_misses 4997 # ITB misses +system.cpu.dtb.data_accesses 1020797 # DTB accesses +system.cpu.itb.fetch_hits 4975201 # ITB hits +system.cpu.itb.fetch_misses 5010 # ITB misses system.cpu.itb.fetch_acv 184 # ITB acv -system.cpu.itb.fetch_accesses 4978962 # ITB accesses +system.cpu.itb.fetch_accesses 4980211 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -352,43 +347,43 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numPwrStateTransitions 12754 # Number of power state transitions -system.cpu.pwrStateClkGateDist::samples 6377 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::mean 281224726.046887 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::stdev 439034613.415905 # Distribution of time spent in the clock gated state +system.cpu.numPwrStateTransitions 12758 # Number of power state transitions +system.cpu.pwrStateClkGateDist::samples 6379 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::mean 281128919.188117 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::stdev 439406492.836173 # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::underflows 1 0.02% 0.02% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::1000-5e+10 6376 99.98% 100.00% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::1000-5e+10 6378 99.98% 100.00% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::max_value 2000000000 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::total 6377 # Distribution of time spent in the clock gated state -system.cpu.pwrStateResidencyTicks::ON 129045330999 # Cumulative time (in ticks) in various power states -system.cpu.pwrStateResidencyTicks::CLK_GATED 1793370078001 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 3844830818 # number of cpu cycles simulated +system.cpu.pwrStateClkGateDist::total 6379 # Distribution of time spent in the clock gated state +system.cpu.pwrStateResidencyTicks::ON 133100038499 # Cumulative time (in ticks) in various power states +system.cpu.pwrStateResidencyTicks::CLK_GATED 1793321375501 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 3852842828 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6377 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211971 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74899 40.89% 40.89% # number of times we switched to this ipl +system.cpu.kern.inst.quiesce 6379 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 212049 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74911 40.89% 40.89% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 131 0.07% 40.96% # number of times we switched to this ipl -system.cpu.kern.ipl_count::22 1932 1.05% 42.01% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 106221 57.99% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 183183 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73532 49.31% 49.31% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_count::22 1934 1.06% 42.01% # number of times we switched to this ipl +system.cpu.kern.ipl_count::31 106246 57.99% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 183222 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73544 49.31% 49.31% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::22 1932 1.30% 50.69% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73532 49.31% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 149127 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1857710123500 96.63% 96.63% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 93945500 0.00% 96.64% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 769790000 0.04% 96.68% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 63840816000 3.32% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1922414675000 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981749 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_good::22 1934 1.30% 50.69% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::31 73544 49.31% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 149153 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1859428695000 96.52% 96.52% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 94503000 0.00% 96.53% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 772442000 0.04% 96.57% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 66125040000 3.43% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1926420680000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981752 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.692255 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.814088 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.692205 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.814056 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -424,58 +419,58 @@ system.cpu.kern.callpal::cserve 1 0.00% 0.00% # nu system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal::swpctx 4174 2.16% 2.17% # number of callpals executed +system.cpu.kern.callpal::swpctx 4177 2.16% 2.17% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.19% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal::swpipl 175962 91.22% 93.41% # number of callpals executed -system.cpu.kern.callpal::rdps 6833 3.54% 96.96% # number of callpals executed +system.cpu.kern.callpal::swpipl 175997 91.22% 93.41% # number of callpals executed +system.cpu.kern.callpal::rdps 6834 3.54% 96.96% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal::rdusp 9 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal::whami 2 0.00% 96.97% # number of callpals executed -system.cpu.kern.callpal::rti 5157 2.67% 99.64% # number of callpals executed +system.cpu.kern.callpal::rti 5159 2.67% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192906 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5901 # number of protection mode switches -system.cpu.kern.mode_switch::user 1741 # number of protection mode switches +system.cpu.kern.callpal::total 192947 # number of callpals executed +system.cpu.kern.mode_switch::kernel 5906 # number of protection mode switches +system.cpu.kern.mode_switch::user 1738 # number of protection mode switches system.cpu.kern.mode_switch::idle 2096 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1910 -system.cpu.kern.mode_good::user 1741 -system.cpu.kern.mode_good::idle 169 -system.cpu.kern.mode_switch_good::kernel 0.323674 # fraction of useful protection mode switches +system.cpu.kern.mode_good::kernel 1908 +system.cpu.kern.mode_good::user 1738 +system.cpu.kern.mode_good::idle 170 +system.cpu.kern.mode_switch_good::kernel 0.323061 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.080630 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.392278 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 46528757000 2.42% 2.42% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 5244548000 0.27% 2.69% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1870641368000 97.31% 100.00% # number of ticks spent at the given mode -system.cpu.kern.swap_context 4175 # number of times the context was actually changed -system.cpu.committedInsts 56180200 # Number of instructions committed -system.cpu.committedOps 56180200 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 52052716 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 324259 # Number of float alu accesses -system.cpu.num_func_calls 1483318 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 6468478 # number of instructions that are conditional controls -system.cpu.num_int_insts 52052716 # number of integer instructions -system.cpu.num_fp_insts 324259 # number of float instructions -system.cpu.num_int_register_reads 71320481 # number of times the integer registers were read -system.cpu.num_int_register_writes 38519316 # number of times the integer registers were written -system.cpu.num_fp_register_reads 163543 # number of times the floating registers were read -system.cpu.num_fp_register_writes 166418 # number of times the floating registers were written -system.cpu.num_mem_refs 15472847 # number of memory refs -system.cpu.num_load_insts 9100978 # Number of load instructions -system.cpu.num_store_insts 6371869 # Number of store instructions -system.cpu.num_idle_cycles 3586740156.000134 # Number of idle cycles -system.cpu.num_busy_cycles 258090661.999866 # Number of busy cycles -system.cpu.not_idle_fraction 0.067127 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.932873 # Percentage of idle cycles -system.cpu.Branches 8422318 # Number of branches fetched -system.cpu.op_class::No_OpClass 3200272 5.70% 5.70% # Class of executed instruction -system.cpu.op_class::IntAlu 36230015 64.48% 70.17% # Class of executed instruction -system.cpu.op_class::IntMult 60990 0.11% 70.28% # Class of executed instruction +system.cpu.kern.mode_switch_good::idle 0.081107 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 0.391786 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 47043056000 2.44% 2.44% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 5370301500 0.28% 2.72% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1874007320500 97.28% 100.00% # number of ticks spent at the given mode +system.cpu.kern.swap_context 4178 # number of times the context was actually changed +system.cpu.committedInsts 56195014 # Number of instructions committed +system.cpu.committedOps 56195014 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 52066552 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 324460 # Number of float alu accesses +system.cpu.num_func_calls 1483758 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 6469897 # number of instructions that are conditional controls +system.cpu.num_int_insts 52066552 # number of integer instructions +system.cpu.num_fp_insts 324460 # number of float instructions +system.cpu.num_int_register_reads 71340789 # number of times the integer registers were read +system.cpu.num_int_register_writes 38530081 # number of times the integer registers were written +system.cpu.num_fp_register_reads 163642 # number of times the floating registers were read +system.cpu.num_fp_register_writes 166520 # number of times the floating registers were written +system.cpu.num_mem_refs 15476659 # number of memory refs +system.cpu.num_load_insts 9103400 # Number of load instructions +system.cpu.num_store_insts 6373259 # Number of store instructions +system.cpu.num_idle_cycles 3586642751.000138 # Number of idle cycles +system.cpu.num_busy_cycles 266200076.999862 # Number of busy cycles +system.cpu.not_idle_fraction 0.069092 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.930908 # Percentage of idle cycles +system.cpu.Branches 8424278 # Number of branches fetched +system.cpu.op_class::No_OpClass 3201027 5.70% 5.70% # Class of executed instruction +system.cpu.op_class::IntAlu 36239709 64.48% 70.17% # Class of executed instruction +system.cpu.op_class::IntMult 61024 0.11% 70.28% # Class of executed instruction system.cpu.op_class::IntDiv 0 0.00% 70.28% # Class of executed instruction -system.cpu.op_class::FloatAdd 38081 0.07% 70.35% # Class of executed instruction +system.cpu.op_class::FloatAdd 38087 0.07% 70.35% # Class of executed instruction system.cpu.op_class::FloatCmp 0 0.00% 70.35% # Class of executed instruction system.cpu.op_class::FloatCvt 0 0.00% 70.35% # Class of executed instruction system.cpu.op_class::FloatMult 0 0.00% 70.35% # Class of executed instruction @@ -501,482 +496,482 @@ system.cpu.op_class::SimdFloatMisc 0 0.00% 70.35% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 70.35% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 70.35% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::MemRead 9328048 16.60% 86.95% # Class of executed instruction -system.cpu.op_class::MemWrite 6377943 11.35% 98.30% # Class of executed instruction -system.cpu.op_class::IprAccess 953034 1.70% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 9330523 16.60% 86.95% # Class of executed instruction +system.cpu.op_class::MemWrite 6379338 11.35% 98.30% # Class of executed instruction +system.cpu.op_class::IprAccess 953511 1.70% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 56192019 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 1390892 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.977567 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 14047886 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1391404 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 10.096195 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 114940500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.977567 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999956 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999956 # Average percentage of cache occupancy +system.cpu.op_class::total 56206855 # Class of executed instruction +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 1390811 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.976541 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 14051752 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1391323 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 10.099561 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 121311500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.976541 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999954 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999954 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 187 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 258 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 256 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 63148569 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 63148569 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 7813455 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7813455 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 5852226 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 5852226 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 182968 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 182968 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 199220 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 199220 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 13665681 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 13665681 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 13665681 # number of overall hits -system.cpu.dcache.overall_hits::total 13665681 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1069828 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1069828 # number of ReadReq misses +system.cpu.dcache.tags.tag_accesses 63163628 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 63163628 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 7815905 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7815905 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 5853570 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 5853570 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 183002 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 183002 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 199258 # 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number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 15039828 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15039828 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120432 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.120432 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049430 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.049430 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086270 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086270 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.091367 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.091367 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.091367 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.091367 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28958.793843 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 28958.793843 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38655.800328 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 38655.800328 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13332.850941 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13332.850941 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 31106.295760 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 31106.295760 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 31106.295760 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 31106.295760 # average overall miss latency +system.cpu.dcache.LoadLockedReq_misses::cpu.data 17279 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 17279 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1374062 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1374062 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1374062 # number of overall misses +system.cpu.dcache.overall_misses::total 1374062 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 33050586500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 33050586500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 13442150000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 13442150000 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 232520000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 232520000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 46492736500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 46492736500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 46492736500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 46492736500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 8885648 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 8885648 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6157889 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6157889 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200281 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 200281 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 199258 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 199258 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 15043537 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15043537 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15043537 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15043537 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120390 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.120390 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049419 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.049419 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086274 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086274 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.091339 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.091339 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.091339 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.091339 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30895.819370 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 30895.819370 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44171.247934 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 44171.247934 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13456.797268 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13456.797268 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 33835.981564 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 33835.981564 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 33835.981564 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 33835.981564 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 835265 # number of writebacks -system.cpu.dcache.writebacks::total 835265 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069828 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1069828 # number of ReadReq MSHR misses +system.cpu.dcache.writebacks::writebacks 835205 # number of writebacks +system.cpu.dcache.writebacks::total 835205 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069743 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1069743 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304319 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 304319 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17275 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 17275 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1374147 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1374147 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1374147 # 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number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 41370476000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 41370476000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1533911000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1533911000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 1533911000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 1533911000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120432 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120432 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049430 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049430 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086270 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086270 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091367 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.091367 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091367 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.091367 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27958.793843 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27958.793843 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37655.800328 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37655.800328 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12332.850941 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12332.850941 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30106.295760 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 30106.295760 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30106.295760 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 30106.295760 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 221343.578644 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 221343.578644 # average ReadReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92515.741858 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92515.741858 # average overall mshr uncacheable latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 928034 # number of replacements -system.cpu.icache.tags.tagsinuse 508.064469 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 55263315 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 928545 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 59.516033 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 42160205500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 508.064469 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.992313 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.992313 # 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number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 13023819500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 13023819500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 13023819500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 56192020 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 56192020 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 56192020 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 56192020 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 56192020 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 56192020 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016527 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.016527 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.016527 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.016527 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.016527 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.016527 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14023.634523 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14023.634523 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14023.634523 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14023.634523 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14023.634523 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14023.634523 # average overall miss latency +system.cpu.icache.tags.tag_accesses 57136210 # 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average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14321.430800 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14321.430800 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14321.430800 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 928034 # number of writebacks -system.cpu.icache.writebacks::total 928034 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 928705 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 928705 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 928705 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 928705 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 928705 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 928705 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12095114500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12095114500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12095114500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12095114500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12095114500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12095114500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016527 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016527 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016527 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.016527 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016527 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.016527 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13023.634523 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13023.634523 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13023.634523 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 13023.634523 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13023.634523 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 13023.634523 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 336391 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65395.484463 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 4235202 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 401913 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 10.537609 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 7260348000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 235.775942 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 4738.507265 # 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number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 74246 # number of writebacks -system.cpu.l2cache.writebacks::total 74246 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 74253 # number of writebacks +system.cpu.l2cache.writebacks::total 74253 # number of writebacks system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 5 # number of UpgradeReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::total 5 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116811 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 116811 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 13197 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 13197 # 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number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 13198 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 271974 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 271974 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 13198 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 388791 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 401989 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 13198 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 388791 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 401989 # number of overall MSHR misses system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable system.cpu.l2cache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable -system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 9650 # number of WriteReq MSHR uncacheable -system.cpu.l2cache.WriteReq_mshr_uncacheable::total 9650 # number of WriteReq MSHR uncacheable -system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 16580 # number of overall MSHR uncacheable misses -system.cpu.l2cache.overall_mshr_uncacheable_misses::total 16580 # number of overall MSHR uncacheable misses +system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 9652 # number of WriteReq MSHR uncacheable +system.cpu.l2cache.WriteReq_mshr_uncacheable::total 9652 # number of WriteReq MSHR uncacheable +system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 16582 # number of overall MSHR uncacheable misses +system.cpu.l2cache.overall_mshr_uncacheable_misses::total 16582 # number of overall MSHR uncacheable misses system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 196500 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 196500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7862462500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7862462500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 944176500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 944176500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 17200833000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 17200833000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 944176500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 25063295500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 26007472000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 944176500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 25063295500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 26007472000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1447255500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1447255500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 1447255500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 1447255500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 9540870500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 9540870500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1221558000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1221558000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 19273752000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 19273752000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1221558000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 28814622500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 30036180500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1221558000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 28814622500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 30036180500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1447252500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1447252500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 1447252500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 1447252500 # number of overall MSHR uncacheable cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.294118 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.294118 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383865 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383865 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.014210 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.014210 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.250183 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.250183 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014210 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279420 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.173262 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014210 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279420 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.173262 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383885 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383885 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.014202 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.014202 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.250201 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.250201 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014202 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279440 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.173222 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014202 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279440 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.173222 # mshr miss rate for overall accesses system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 39300 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 39300 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67309.264538 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67309.264538 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 71544.782905 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 71544.782905 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 63244.169501 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 63244.169501 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71544.782905 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64465.529880 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64697.939963 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71544.782905 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64465.529880 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64697.939963 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 208839.177489 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 208839.177489 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 87289.234017 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 87289.234017 # average overall mshr uncacheable latency -system.cpu.toL2Bus.snoop_filter.tot_requests 4639053 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2319092 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1505 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 81673.647671 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 81673.647671 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 92556.296409 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 92556.296409 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70866.156324 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70866.156324 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 92556.296409 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 74113.398973 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 74718.911463 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 92556.296409 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 74113.398973 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 74718.911463 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 208838.744589 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 208838.744589 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 87278.524907 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 87278.524907 # average overall mshr uncacheable latency +system.cpu.toL2Bus.snoop_filter.tot_requests 4640189 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2319660 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1516 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 884 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 884 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadReq 6930 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2022895 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 9650 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 9650 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 909511 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 928034 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 817772 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2023463 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 9652 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 9652 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 909458 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 928683 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 817750 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 17 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 17 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 304302 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 304302 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 928705 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1087263 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 929354 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1087182 # Transaction distribution system.cpu.toL2Bus.trans_dist::InvalidateReq 219 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2785424 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4207053 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 6992477 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 118830016 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142561492 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 261391508 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 336947 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 4763072 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 2673477 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.000954 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.030869 # Request fanout histogram +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2787371 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4206814 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 6994185 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 118913088 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142552484 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 261465572 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 336953 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 4763520 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 2674053 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000958 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.030932 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 2670927 99.90% 99.90% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 2550 0.10% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 2671492 99.90% 99.90% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 2561 0.10% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 2673477 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4095940500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 2674053 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4097099500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 293383 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1393057500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1394031000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2098871000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2098750500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -990,12 +985,12 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.iobus.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states +system.iobus.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states system.iobus.trans_dist::ReadReq 7103 # Transaction distribution system.iobus.trans_dist::ReadResp 7103 # Transaction distribution -system.iobus.trans_dist::WriteReq 51202 # Transaction distribution -system.iobus.trans_dist::WriteResp 51202 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5156 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::WriteReq 51204 # Transaction distribution +system.iobus.trans_dist::WriteResp 51204 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5160 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1006 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) @@ -1004,11 +999,11 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 1812 system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 33160 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 33164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 116610 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20624 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 116614 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20640 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2717 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) @@ -1017,13 +1012,13 @@ system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 44564 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 44580 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2706172 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 5337500 # Layer occupancy (ticks) +system.iobus.pkt_size::total 2706188 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 5344500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 758500 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 757500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) @@ -1031,36 +1026,36 @@ system.iobus.reqLayer6.occupancy 10000 # La system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer22.occupancy 174000 # Layer occupancy (ticks) system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 15814000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 15813000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer24.occupancy 1891500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer25.occupancy 6041500 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 82000 # Layer occupancy (ticks) +system.iobus.reqLayer26.occupancy 82500 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 216133054 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 216215769 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 23510000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 23512000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer1.occupancy 41946000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.342865 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.340614 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1756469369000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.342865 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.083929 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.083929 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1760392723000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.340614 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.083788 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.083788 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 375525 # Number of tag accesses system.iocache.tags.data_accesses 375525 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states +system.iocache.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses @@ -1069,14 +1064,14 @@ system.iocache.demand_misses::tsunami.ide 41725 # n system.iocache.demand_misses::total 41725 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses system.iocache.overall_misses::total 41725 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21758883 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21758883 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::tsunami.ide 4857806171 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4857806171 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 4879565054 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 4879565054 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 4879565054 # number of overall miss cycles -system.iocache.overall_miss_latency::total 4879565054 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 21848883 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21848883 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::tsunami.ide 4937126886 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4937126886 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 4958975769 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 4958975769 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 4958975769 # number of overall miss cycles +system.iocache.overall_miss_latency::total 4958975769 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) @@ -1093,19 +1088,19 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125773.890173 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 125773.890173 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 116909.081897 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 116909.081897 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 116945.837124 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 116945.837124 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 116945.837124 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 116945.837124 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126294.121387 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 126294.121387 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 118818.032489 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 118818.032489 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 118849.029814 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 118849.029814 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 118849.029814 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 118849.029814 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 700 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 4 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 175 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 41512 # number of writebacks system.iocache.writebacks::total 41512 # number of writebacks @@ -1117,14 +1112,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 41725 system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13108883 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 13108883 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2777800981 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2777800981 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 2790909864 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 2790909864 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 2790909864 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 2790909864 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13198883 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 13198883 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2857073994 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2857073994 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 2870272877 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 2870272877 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 2870272877 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 2870272877 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1133,71 +1128,71 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 75773.890173 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 75773.890173 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 66851.198041 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 66851.198041 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 66888.193265 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 66888.193265 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 66888.193265 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 66888.193265 # average overall mshr miss latency -system.membus.snoop_filter.tot_requests 821076 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 378187 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76294.121387 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 76294.121387 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68759.000626 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68759.000626 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 68790.242708 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 68790.242708 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 68790.242708 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 68790.242708 # average overall mshr miss latency +system.membus.snoop_filter.tot_requests 821141 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 378246 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 407 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 6930 # Transaction distribution system.membus.trans_dist::ReadResp 292275 # Transaction distribution -system.membus.trans_dist::WriteReq 9650 # Transaction distribution -system.membus.trans_dist::WriteResp 9650 # Transaction distribution -system.membus.trans_dist::WritebackDirty 115758 # Transaction distribution -system.membus.trans_dist::CleanEvict 261593 # Transaction distribution +system.membus.trans_dist::WriteReq 9652 # Transaction distribution +system.membus.trans_dist::WriteResp 9652 # Transaction distribution +system.membus.trans_dist::WritebackDirty 115765 # Transaction distribution +system.membus.trans_dist::CleanEvict 261592 # Transaction distribution system.membus.trans_dist::UpgradeReq 136 # Transaction distribution system.membus.trans_dist::UpgradeResp 2 # Transaction distribution -system.membus.trans_dist::ReadExReq 116680 # Transaction distribution -system.membus.trans_dist::ReadExResp 116680 # Transaction distribution +system.membus.trans_dist::ReadExReq 116686 # Transaction distribution +system.membus.trans_dist::ReadExResp 116686 # Transaction distribution system.membus.trans_dist::ReadSharedReq 285345 # Transaction distribution system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33160 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1139235 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1172395 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33164 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1139253 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1172417 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83425 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 83425 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1255820 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44564 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30452928 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30497492 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 1255842 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44580 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30453760 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30498340 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2657728 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2657728 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 33155220 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 33156068 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 431 # Total snoops (count) system.membus.snoopTraffic 27456 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 460293 # Request fanout histogram +system.membus.snoop_fanout::samples 460301 # Request fanout histogram system.membus.snoop_fanout::mean 0.001416 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.037610 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.037609 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 459641 99.86% 99.86% # Request fanout histogram +system.membus.snoop_fanout::0 459649 99.86% 99.86% # Request fanout histogram system.membus.snoop_fanout::1 652 0.14% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 460293 # Request fanout histogram -system.membus.reqLayer0.occupancy 30118500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 460301 # Request fanout histogram +system.membus.reqLayer0.occupancy 30124000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1286935040 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1287045337 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 2142767250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2142987750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) system.membus.respLayer2.occupancy 887117 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states -system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states -system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states -system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states -system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states +system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states +system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states +system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states +system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -1229,28 +1224,28 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states -system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states -system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states -system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states -system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1922415409000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states +system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states +system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states +system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states +system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states +system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/system.terminal b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/system.terminal index 9603a7507..d82c05314 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/system.terminal +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/system.terminal @@ -24,7 +24,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
memcluster 1, usage 0, start 392, end 16384
freeing pages 1069:16384
reserving pages 1069:1070 -
4096K Bcache detected; load hit latency 38 cycles, load miss latency 263 cycles +
4096K Bcache detected; load hit latency 38 cycles, load miss latency 175 cycles
SMP: 1 CPUs probed -- cpu_present_mask = 1
Built 1 zonelists
Kernel command line: root=/dev/hda1 console=ttyS0 diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini index 942d8ed5e..d7e6fcfdf 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini @@ -36,7 +36,7 @@ load_addr_mask=268435455 load_offset=2147483648 machine_type=VExpress_EMM mem_mode=timing -mem_ranges=2147483648:2415919103 +mem_ranges=2147483648:2415919103:0:0:0:0 memories=system.physmem system.realview.nvmem system.realview.vram mmap_using_noreserve=false multi_proc=true @@ -73,7 +73,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911 +ranges=788529152:805306367:0:0:0:0 721420288:725614591:0:0:0:0 805306368:1073741823:0:0:0:0 1073741824:1610612735:0:0:0:0 402653184:469762047:0:0:0:0 469762048:536870911:0:0:0:0 req_size=16 resp_size=16 master=system.iobus.slave[0] @@ -153,7 +153,7 @@ icache_port=system.cpu0.icache.cpu_side [system.cpu0.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -250,7 +250,7 @@ port=system.cpu0.toL2Bus.slave[3] [system.cpu0.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -382,7 +382,7 @@ port=system.cpu0.toL2Bus.slave[2] [system.cpu0.l2cache] type=Cache children=prefetcher tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=16 clk_domain=system.cpu_clk_domain clusivity=mostly_excl @@ -531,7 +531,7 @@ icache_port=system.cpu1.icache.cpu_side [system.cpu1.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -628,7 +628,7 @@ port=system.cpu1.toL2Bus.slave[3] [system.cpu1.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -760,7 +760,7 @@ port=system.cpu1.toL2Bus.slave[2] [system.cpu1.l2cache] type=Cache children=prefetcher tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=16 clk_domain=system.cpu_clk_domain clusivity=mostly_excl @@ -907,7 +907,7 @@ slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma [system.iocache] type=Cache children=tags -addr_ranges=2147483648:2415919103 +addr_ranges=2147483648:2415919103:0:0:0:0 assoc=8 clk_domain=system.clk_domain clusivity=mostly_incl @@ -953,7 +953,7 @@ size=1024 [system.l2c] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -1051,27 +1051,27 @@ system=system [system.physmem] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -1091,6 +1091,7 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 @@ -1100,7 +1101,7 @@ p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 page_policy=open_adaptive power_model=Null -range=2147483648:2415919103 +range=2147483648:2415919103:0:0:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 @@ -1122,9 +1123,9 @@ tRTW=2500 tWR=15000 tWTR=7500 tXAW=30000 -tXP=0 +tXP=6000 tXPDLL=0 -tXS=0 +tXS=270000 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 @@ -1477,7 +1478,7 @@ default_p_state=UNDEFINED dist_addr=738201600 dist_pio_delay=10000 eventq_index=0 -gem5_extensions=true +gem5_extensions=false int_latency=10000 it_lines=128 p_state_clk_gate_bins=20 @@ -1794,6 +1795,7 @@ conf_table_reported=false default_p_state=UNDEFINED eventq_index=0 in_addr_map=true +kvm_map=true latency=30000 latency_var=0 null=false @@ -1801,7 +1803,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -range=0:67108863 +range=0:67108863:0:0:0:0 port=system.membus.master[1] [system.realview.pci_host] @@ -2032,6 +2034,7 @@ conf_table_reported=false default_p_state=UNDEFINED eventq_index=0 in_addr_map=true +kvm_map=true latency=30000 latency_var=0 null=false @@ -2039,7 +2042,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -range=402653184:436207615 +range=402653184:436207615:0:0:0:0 port=system.iobus.master[11] [system.realview.watchdog_fake] diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout index 8023e7aa6..c41a1ac7e 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realv gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 1 2016 17:10:05 -gem5 started Aug 1 2016 17:10:34 -gem5 executing on e108600-lin, pid 12233 +gem5 compiled Oct 11 2016 00:00:58 +gem5 started Oct 13 2016 20:54:49 +gem5 executing on e108600-lin, pid 17501 command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual Global frequency set at 1000000000000 ticks per second @@ -29,4 +29,4 @@ info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 -Exiting @ tick 2869796829000 because m5_exit instruction encountered +Exiting @ tick 2870822663000 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt index dc9310742..bd324667f 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt @@ -1,163 +1,159 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.870001 # Number of seconds simulated -sim_ticks 2870000710000 # Number of ticks simulated -final_tick 2870000710000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.870823 # Number of seconds simulated +sim_ticks 2870822663000 # Number of ticks simulated +final_tick 2870822663000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 371570 # Simulator instruction rate (inst/s) -host_op_rate 449436 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 8101953096 # Simulator tick rate (ticks/s) -host_mem_usage 621024 # Number of bytes of host memory used -host_seconds 354.24 # Real time elapsed on the host -sim_insts 131623434 # Number of instructions simulated -sim_ops 159206188 # Number of ops (including micro ops) simulated +host_inst_rate 442891 # Simulator instruction rate (inst/s) +host_op_rate 535691 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 9664154143 # Simulator tick rate (ticks/s) +host_mem_usage 616988 # Number of bytes of host memory used +host_seconds 297.06 # Real time elapsed on the host +sim_insts 131564747 # Number of instructions simulated +sim_ops 159131669 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu0.dtb.walker 448 # Number of bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu0.dtb.walker 576 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 1182180 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 1312420 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 8596224 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 150484 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 578772 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 396096 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 1180196 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 1289828 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 8538816 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 149012 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 568660 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 388160 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 12217776 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 1182180 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 150484 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1332664 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8789056 # Number of bytes written to this memory +system.physmem.bytes_read::total 12116336 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 1180196 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 149012 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1329208 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8714368 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory -system.physmem.bytes_written::total 8806620 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 7 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 8731932 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 9 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 26925 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 21026 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 134316 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2506 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 9064 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 6189 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 26894 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 20673 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 133419 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2483 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 8906 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 6065 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 200051 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 137329 # Number of write requests responded to by this memory +system.physmem.num_reads::total 198466 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 136162 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory -system.physmem.num_writes::total 141720 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 156 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 140553 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 201 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 45 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 411909 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 457289 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 2995199 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 22 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 52433 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 201663 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 138013 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 411100 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 449289 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 2974345 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 51906 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 198083 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 135209 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 334 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4257064 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 411909 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 52433 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 464343 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3062388 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 6106 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4220510 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 411100 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 51906 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 463006 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3035495 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 6104 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3068508 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3062388 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 156 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 3041613 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3035495 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 201 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 45 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 411909 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 463395 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 2995199 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 22 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 52433 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 201677 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 138013 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 411100 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 455393 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 2974345 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 51906 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 198097 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 135209 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 334 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7325572 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 200051 # Number of read requests accepted -system.physmem.writeReqs 141720 # Number of write requests accepted -system.physmem.readBursts 200051 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 141720 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 12793920 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 9344 # Total number of bytes read from write queue -system.physmem.bytesWritten 8819520 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 12217776 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 8806620 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 146 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 3896 # Number of DRAM write bursts merged with an existing one +system.physmem.bw_total::total 7262123 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 198466 # Number of read requests accepted +system.physmem.writeReqs 140553 # Number of write requests accepted +system.physmem.readBursts 198466 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 140553 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 12692032 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 9792 # Total number of bytes read from write queue +system.physmem.bytesWritten 8744000 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 12116336 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 8731932 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 153 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 3897 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 11709 # Per bank write bursts -system.physmem.perBankRdBursts::1 12160 # Per bank write bursts -system.physmem.perBankRdBursts::2 12038 # Per bank write bursts -system.physmem.perBankRdBursts::3 12178 # Per bank write bursts -system.physmem.perBankRdBursts::4 20671 # Per bank write bursts -system.physmem.perBankRdBursts::5 12806 # Per bank write bursts -system.physmem.perBankRdBursts::6 12086 # Per bank write bursts -system.physmem.perBankRdBursts::7 12477 # Per bank write bursts -system.physmem.perBankRdBursts::8 12638 # Per bank write bursts -system.physmem.perBankRdBursts::9 12504 # Per bank write bursts -system.physmem.perBankRdBursts::10 11795 # Per bank write bursts -system.physmem.perBankRdBursts::11 11324 # Per bank write bursts -system.physmem.perBankRdBursts::12 11594 # Per bank write bursts -system.physmem.perBankRdBursts::13 11843 # Per bank write bursts -system.physmem.perBankRdBursts::14 11003 # Per bank write bursts -system.physmem.perBankRdBursts::15 11079 # Per bank write bursts -system.physmem.perBankWrBursts::0 8559 # Per bank write bursts -system.physmem.perBankWrBursts::1 9022 # Per bank write bursts -system.physmem.perBankWrBursts::2 9017 # Per bank write bursts -system.physmem.perBankWrBursts::3 8844 # Per bank write bursts -system.physmem.perBankWrBursts::4 8437 # Per bank write bursts -system.physmem.perBankWrBursts::5 9230 # Per bank write bursts -system.physmem.perBankWrBursts::6 8825 # Per bank write bursts -system.physmem.perBankWrBursts::7 8866 # Per bank write bursts -system.physmem.perBankWrBursts::8 9056 # Per bank write bursts -system.physmem.perBankWrBursts::9 8974 # Per bank write bursts -system.physmem.perBankWrBursts::10 8482 # Per bank write bursts -system.physmem.perBankWrBursts::11 8329 # Per bank write bursts -system.physmem.perBankWrBursts::12 8472 # Per bank write bursts -system.physmem.perBankWrBursts::13 8225 # Per bank write bursts -system.physmem.perBankWrBursts::14 7833 # Per bank write bursts -system.physmem.perBankWrBursts::15 7634 # Per bank write bursts +system.physmem.perBankRdBursts::0 11821 # Per bank write bursts +system.physmem.perBankRdBursts::1 11810 # Per bank write bursts +system.physmem.perBankRdBursts::2 12062 # Per bank write bursts +system.physmem.perBankRdBursts::3 12027 # Per bank write bursts +system.physmem.perBankRdBursts::4 20473 # Per bank write bursts +system.physmem.perBankRdBursts::5 12098 # Per bank write bursts +system.physmem.perBankRdBursts::6 12277 # Per bank write bursts +system.physmem.perBankRdBursts::7 12432 # Per bank write bursts +system.physmem.perBankRdBursts::8 12179 # Per bank write bursts +system.physmem.perBankRdBursts::9 12459 # Per bank write bursts +system.physmem.perBankRdBursts::10 11810 # Per bank write bursts +system.physmem.perBankRdBursts::11 11367 # Per bank write bursts +system.physmem.perBankRdBursts::12 11535 # Per bank write bursts +system.physmem.perBankRdBursts::13 11583 # Per bank write bursts +system.physmem.perBankRdBursts::14 11073 # Per bank write bursts +system.physmem.perBankRdBursts::15 11307 # Per bank write bursts +system.physmem.perBankWrBursts::0 8516 # Per bank write bursts +system.physmem.perBankWrBursts::1 8730 # Per bank write bursts +system.physmem.perBankWrBursts::2 8955 # Per bank write bursts +system.physmem.perBankWrBursts::3 8735 # Per bank write bursts +system.physmem.perBankWrBursts::4 8248 # Per bank write bursts +system.physmem.perBankWrBursts::5 8655 # Per bank write bursts +system.physmem.perBankWrBursts::6 8964 # Per bank write bursts +system.physmem.perBankWrBursts::7 8852 # Per bank write bursts +system.physmem.perBankWrBursts::8 8742 # Per bank write bursts +system.physmem.perBankWrBursts::9 8980 # Per bank write bursts +system.physmem.perBankWrBursts::10 8644 # Per bank write bursts +system.physmem.perBankWrBursts::11 8478 # Per bank write bursts +system.physmem.perBankWrBursts::12 8438 # Per bank write bursts +system.physmem.perBankWrBursts::13 8004 # Per bank write bursts +system.physmem.perBankWrBursts::14 7925 # Per bank write bursts +system.physmem.perBankWrBursts::15 7759 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 37 # Number of times write queue was full causing retry -system.physmem.totGap 2870000192000 # Total gap between requests +system.physmem.numWrRetry 91 # Number of times write queue was full causing retry +system.physmem.totGap 2870821632000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 9732 # Read request sizes (log2) system.physmem.readPktSize::3 28 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 190291 # Read request sizes (log2) +system.physmem.readPktSize::6 188706 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4391 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 137329 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 139673 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 16007 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 10455 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 8865 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 7050 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 5558 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 4708 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 3913 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3442 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 97 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 65 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 43 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 15 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 6 # What read queue length does an incoming req see +system.physmem.writePktSize::6 136162 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 135157 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 17197 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 10634 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 8782 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7390 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 5915 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 5070 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 4238 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3688 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 106 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 63 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 39 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 13 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 7 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -185,164 +181,178 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2714 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3656 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4613 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5803 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6737 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6707 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7345 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7866 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8699 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 8644 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 9954 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 10413 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8708 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8669 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 10166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 8149 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7598 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7446 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 368 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 301 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 249 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 200 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 123 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 140 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 158 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 113 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 150 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 146 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 133 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 134 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 88 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 173 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 120 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 84 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 99 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 118 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 78 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 97 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 59 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 75 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 94 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 90 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 53 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 66 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 85 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 48 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 46 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 128 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 85925 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 251.537690 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 143.363316 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 306.826134 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 42893 49.92% 49.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 18336 21.34% 71.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6281 7.31% 78.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3896 4.53% 83.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2533 2.95% 86.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1590 1.85% 87.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1050 1.22% 89.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 985 1.15% 90.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8361 9.73% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 85925 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6834 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 29.251244 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 562.918265 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6833 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 2427 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3371 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4356 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5347 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6308 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6371 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7021 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7533 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8400 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 8212 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 9528 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 9966 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8517 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8109 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 8451 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 9511 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7906 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7646 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 714 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 476 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 416 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 331 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 256 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 247 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 300 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 229 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 232 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 267 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 230 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 245 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 253 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 236 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 187 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 187 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 199 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 194 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 156 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 227 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 198 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 142 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 187 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 228 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 178 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 178 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 214 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 214 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 171 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 133 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 236 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 84864 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 252.592006 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 143.738576 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 307.804055 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 42330 49.88% 49.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 18020 21.23% 71.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6191 7.30% 78.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3740 4.41% 82.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2680 3.16% 85.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1634 1.93% 87.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 923 1.09% 88.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 980 1.15% 90.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8366 9.86% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 84864 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6753 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 29.364283 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 566.459907 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6751 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-4095 1 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::45056-47103 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6834 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6834 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.164618 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.651361 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 12.320527 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5790 84.72% 84.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 323 4.73% 89.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 59 0.86% 90.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 46 0.67% 90.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 267 3.91% 94.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 35 0.51% 95.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 21 0.31% 95.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 28 0.41% 96.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 23 0.34% 96.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 7 0.10% 96.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 4 0.06% 96.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 12 0.18% 96.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 155 2.27% 99.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 3 0.04% 99.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 5 0.07% 99.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 6 0.09% 99.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 12 0.18% 99.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 2 0.03% 99.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 2 0.03% 99.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 1 0.01% 99.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 2 0.03% 99.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 6 0.09% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 1 0.01% 99.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.01% 99.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 11 0.16% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 2 0.03% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 1 0.01% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 3 0.04% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 1 0.01% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 1 0.01% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 1 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 2 0.03% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6834 # Writes before turning the bus around for reads -system.physmem.totQLat 4674239132 # Total ticks spent queuing -system.physmem.totMemAccLat 8422457882 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 999525000 # Total ticks spent in databus transfers -system.physmem.avgQLat 23382.30 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 6753 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6753 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.231749 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.531627 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 14.015829 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5781 85.61% 85.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 288 4.26% 89.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 56 0.83% 90.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 54 0.80% 91.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 265 3.92% 95.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 16 0.24% 95.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 17 0.25% 95.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 13 0.19% 96.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 10 0.15% 96.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 4 0.06% 96.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 4 0.06% 96.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 11 0.16% 96.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 146 2.16% 98.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 5 0.07% 98.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 7 0.10% 98.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 6 0.09% 98.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 12 0.18% 99.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 2 0.03% 99.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 1 0.01% 99.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 4 0.06% 99.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 4 0.06% 99.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 1 0.01% 99.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 3 0.04% 99.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 6 0.09% 99.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 1 0.01% 99.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 2 0.03% 99.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 11 0.16% 99.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 4 0.06% 99.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 3 0.04% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 1 0.01% 99.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 2 0.03% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 4 0.06% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 3 0.04% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-187 1 0.01% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 1 0.01% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-195 4 0.06% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6753 # Writes before turning the bus around for reads +system.physmem.totQLat 9353740299 # Total ticks spent queuing +system.physmem.totMemAccLat 13072109049 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 991565000 # Total ticks spent in databus transfers +system.physmem.avgQLat 47166.55 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 42132.30 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 4.46 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.07 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 4.26 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.07 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 65916.55 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 4.42 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 3.05 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 4.22 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.04 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.06 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.74 # Average write queue length when enqueuing -system.physmem.readRowHits 166683 # Number of row buffer hits during reads -system.physmem.writeRowHits 85101 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.38 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 61.75 # Row buffer hit rate for writes -system.physmem.avgGap 8397436.27 # Average gap between requests -system.physmem.pageHitRate 74.55 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 335240640 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 182919000 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 827767200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 458784000 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 187454198880 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 84698340030 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1647701064750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1921658314500 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.568191 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2740964082488 # Time in different power states -system.physmem_0.memoryStateTime::REF 95835480000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 33201034512 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 314352360 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 171521625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 731484000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 434192400 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 187454198880 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 83981561895 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1648329817500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1921417128660 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.484154 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2742009812705 # Time in different power states -system.physmem_1.memoryStateTime::REF 95835480000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 32151144795 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states +system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.09 # Average write queue length when enqueuing +system.physmem.readRowHits 165583 # Number of row buffer hits during reads +system.physmem.writeRowHits 84490 # Number of row buffer hits during writes +system.physmem.readRowHitRate 83.50 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 61.83 # Row buffer hit rate for writes +system.physmem.avgGap 8468025.78 # Average gap between requests +system.physmem.pageHitRate 74.66 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 311268300 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 165439230 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 749700000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 363599100 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 6175288080.000001 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 5556148530 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 353114880 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 11660360040 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 9231007680 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 675128481165 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 709697287665 # Total energy per rank (pJ) +system.physmem_0.averagePower 247.210424 # Core power per rank (mW) +system.physmem_0.totalIdleTime 2857712170474 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 646078467 # Time in different power states +system.physmem_0.memoryStateTime::REF 2625372000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 2808102138000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 24039125004 # Time in different power states +system.physmem_0.memoryStateTime::ACT 9838978559 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 25570970970 # Time in different power states +system.physmem_1.actEnergy 294667800 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 156619650 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 666254820 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 349583400 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 6182663760.000001 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 5620280370 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 353139840 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 11082999060 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 9548118720 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 675230388855 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 709488226485 # Total energy per rank (pJ) +system.physmem_1.averagePower 247.137601 # Core power per rank (mW) +system.physmem_1.totalIdleTime 2857213980946 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 650996744 # Time in different power states +system.physmem_1.memoryStateTime::REF 2628804000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 2808400306500 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 24864927177 # Time in different power states +system.physmem_1.memoryStateTime::ACT 9973048810 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 24304579769 # Time in different power states +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory @@ -361,9 +371,9 @@ system.realview.nvmem.bw_inst_read::total 24 # I system.realview.nvmem.bw_total::cpu0.inst 7 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.inst 17 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 24 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -371,7 +381,7 @@ system.cf0.dma_write_full_pages 540 # Nu system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states +system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -401,61 +411,59 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states -system.cpu0.dtb.walker.walks 7878 # Table walker walks requested -system.cpu0.dtb.walker.walksShort 7878 # Table walker walks initiated with short descriptors -system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 1506 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 6372 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walkWaitTime::samples 7878 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 7878 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 7878 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 6484 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 12295.265268 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 11397.219739 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 5676.180841 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-16383 5980 92.23% 92.23% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::16384-32767 464 7.16% 99.38% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::32768-49151 34 0.52% 99.91% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::49152-65535 1 0.02% 99.92% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::81920-98303 2 0.03% 99.95% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::98304-114687 2 0.03% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::196608-212991 1 0.02% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 6484 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 1125817500 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0 1125817500 100.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 1125817500 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 5017 77.38% 77.38% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 1467 22.62% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 6484 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 7878 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.walker.walks 7793 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 7793 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 1456 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 6337 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walkWaitTime::samples 7793 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 7793 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 7793 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 6399 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 12413.189561 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 11268.612574 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 10437.446912 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-65535 6392 99.89% 99.89% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::65536-131071 4 0.06% 99.95% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-196607 1 0.02% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::262144-327679 1 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::589824-655359 1 0.02% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 6399 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 1181299500 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 1181299500 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 1181299500 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 4982 77.86% 77.86% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1417 22.14% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 6399 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 7793 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 7878 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6484 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 7793 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6399 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6484 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 14362 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6399 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 14192 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 25174501 # DTB read hits -system.cpu0.dtb.read_misses 6776 # DTB read misses -system.cpu0.dtb.write_hits 18763964 # DTB write hits -system.cpu0.dtb.write_misses 1102 # DTB write misses +system.cpu0.dtb.read_hits 25156364 # DTB read hits +system.cpu0.dtb.read_misses 6669 # DTB read misses +system.cpu0.dtb.write_hits 18748845 # DTB write hits +system.cpu0.dtb.write_misses 1124 # DTB write misses system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3391 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 3378 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 1765 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 1745 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 282 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 25181277 # DTB read accesses -system.cpu0.dtb.write_accesses 18765066 # DTB write accesses +system.cpu0.dtb.read_accesses 25163033 # DTB read accesses +system.cpu0.dtb.write_accesses 18749969 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 43938465 # DTB hits -system.cpu0.dtb.misses 7878 # DTB misses -system.cpu0.dtb.accesses 43946343 # DTB accesses -system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.hits 43905209 # DTB hits +system.cpu0.dtb.misses 7793 # DTB misses +system.cpu0.dtb.accesses 43913002 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -485,7 +493,7 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states +system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states system.cpu0.itb.walker.walks 3349 # Table walker walks requested system.cpu0.itb.walker.walksShort 3349 # Table walker walks initiated with short descriptors system.cpu0.itb.walker.walksShortTerminationLevel::Level1 299 # Level at which table walker walks with short descriptors terminate @@ -494,22 +502,23 @@ system.cpu0.itb.walker.walkWaitTime::samples 3349 system.cpu0.itb.walker.walkWaitTime::0 3349 100.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu0.itb.walker.walkWaitTime::total 3349 # Table walker wait (enqueue to first request) latency system.cpu0.itb.walker.walkCompletionTime::samples 2333 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 12613.587655 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 11778.875659 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 5637.639193 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-8191 386 16.55% 16.55% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::8192-16383 1666 71.41% 87.96% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::16384-24575 225 9.64% 97.60% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::24576-32767 26 1.11% 98.71% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::32768-40959 26 1.11% 99.83% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 12610.587227 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 11657.853110 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 5955.666994 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-8191 437 18.73% 18.73% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::8192-16383 1604 68.75% 87.48% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::16384-24575 228 9.77% 97.26% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::24576-32767 34 1.46% 98.71% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::32768-40959 24 1.03% 99.74% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::40960-49151 2 0.09% 99.83% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::49152-57343 1 0.04% 99.87% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::57344-65535 1 0.04% 99.91% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::90112-98303 1 0.04% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::98304-106495 1 0.04% 99.96% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::122880-131071 1 0.04% 100.00% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::total 2333 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples 1125441500 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 1125441500 100.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 1125441500 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::samples 1180899500 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 1180899500 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 1180899500 # Table walker pending requests distribution system.cpu0.itb.walker.walkPageSizes::4K 2034 87.18% 87.18% # Table walker page sizes translated system.cpu0.itb.walker.walkPageSizes::1M 299 12.82% 100.00% # Table walker page sizes translated system.cpu0.itb.walker.walkPageSizes::total 2333 # Table walker page sizes translated @@ -520,7 +529,7 @@ system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2333 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2333 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin::total 5682 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 119077538 # ITB inst hits +system.cpu0.itb.inst_hits 119019454 # ITB inst hits system.cpu0.itb.inst_misses 3349 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses @@ -537,660 +546,663 @@ system.cpu0.itb.domain_faults 0 # Nu system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 119080887 # ITB inst accesses -system.cpu0.itb.hits 119077538 # DTB hits +system.cpu0.itb.inst_accesses 119022803 # ITB inst accesses +system.cpu0.itb.hits 119019454 # DTB hits system.cpu0.itb.misses 3349 # DTB misses -system.cpu0.itb.accesses 119080887 # DTB accesses -system.cpu0.numPwrStateTransitions 3762 # Number of power state transitions -system.cpu0.pwrStateClkGateDist::samples 1881 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::mean 1452265205.015417 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::stdev 23608911235.366570 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::underflows 1082 57.52% 57.52% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1000-5e+10 794 42.21% 99.73% # Distribution of time spent in the clock gated state +system.cpu0.itb.accesses 119022803 # DTB accesses +system.cpu0.numPwrStateTransitions 3740 # Number of power state transitions +system.cpu0.pwrStateClkGateDist::samples 1870 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::mean 1460468935.028877 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::stdev 23678191319.145061 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::underflows 1076 57.54% 57.54% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1000-5e+10 789 42.19% 99.73% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.05% 99.79% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 4 0.21% 100.00% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::max_value 499963656512 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::total 1881 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateResidencyTicks::ON 138289859366 # Cumulative time (in ticks) in various power states -system.cpu0.pwrStateResidencyTicks::CLK_GATED 2731710850634 # Cumulative time (in ticks) in various power states -system.cpu0.numCycles 5740001420 # number of cpu cycles simulated +system.cpu0.pwrStateClkGateDist::max_value 499962822056 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::total 1870 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateResidencyTicks::ON 139745754496 # Cumulative time (in ticks) in various power states +system.cpu0.pwrStateResidencyTicks::CLK_GATED 2731076908504 # Cumulative time (in ticks) in various power states +system.cpu0.numCycles 5741645326 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 1881 # number of quiesce instructions executed -system.cpu0.committedInsts 115412619 # Number of instructions committed -system.cpu0.committedOps 139453859 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 123427491 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 9820 # Number of float alu accesses -system.cpu0.num_func_calls 12678366 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 15706258 # number of instructions that are conditional controls -system.cpu0.num_int_insts 123427491 # number of integer instructions -system.cpu0.num_fp_insts 9820 # number of float instructions -system.cpu0.num_int_register_reads 227200136 # number of times the integer registers were read -system.cpu0.num_int_register_writes 85767213 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 7560 # number of times the floating registers were read +system.cpu0.kern.inst.quiesce 1870 # number of quiesce instructions executed +system.cpu0.committedInsts 115354991 # Number of instructions committed +system.cpu0.committedOps 139381682 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 123361088 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 9690 # Number of float alu accesses +system.cpu0.num_func_calls 12675511 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 15701045 # number of instructions that are conditional controls +system.cpu0.num_int_insts 123361088 # number of integer instructions +system.cpu0.num_fp_insts 9690 # number of float instructions +system.cpu0.num_int_register_reads 227079516 # number of times the integer registers were read +system.cpu0.num_int_register_writes 85717450 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 7430 # number of times the floating registers were read system.cpu0.num_fp_register_writes 2264 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 505219370 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 52317118 # number of times the CC registers were written -system.cpu0.num_mem_refs 45075192 # number of memory refs -system.cpu0.num_load_insts 25426401 # Number of load instructions -system.cpu0.num_store_insts 19648791 # Number of store instructions -system.cpu0.num_idle_cycles 5463421701.266096 # Number of idle cycles -system.cpu0.num_busy_cycles 276579718.733904 # Number of busy cycles -system.cpu0.not_idle_fraction 0.048185 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.951815 # Percentage of idle cycles -system.cpu0.Branches 29123439 # Number of branches fetched +system.cpu0.num_cc_register_reads 504946337 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 52296035 # number of times the CC registers were written +system.cpu0.num_mem_refs 45041487 # number of memory refs +system.cpu0.num_load_insts 25408167 # Number of load instructions +system.cpu0.num_store_insts 19633320 # Number of store instructions +system.cpu0.num_idle_cycles 5462153817.006098 # Number of idle cycles +system.cpu0.num_busy_cycles 279491508.993903 # Number of busy cycles +system.cpu0.not_idle_fraction 0.048678 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.951322 # Percentage of idle cycles +system.cpu0.Branches 29114863 # Number of branches fetched system.cpu0.op_class::No_OpClass 2273 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 98023875 68.44% 68.44% # Class of executed instruction -system.cpu0.op_class::IntMult 109907 0.08% 68.52% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 68.52% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 68.52% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 68.52% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 68.52% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 68.52% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 68.52% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 68.52% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 68.52% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 68.52% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 68.52% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 68.52% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 68.52% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 68.52% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 68.52% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 68.52% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 68.52% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.52% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 68.52% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.52% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.52% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.52% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.52% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.52% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 8209 0.01% 68.53% # Class of executed instruction +system.cpu0.op_class::IntAlu 97984598 68.45% 68.45% # Class of executed instruction +system.cpu0.op_class::IntMult 109968 0.08% 68.53% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 8149 0.01% 68.53% # Class of executed instruction system.cpu0.op_class::SimdFloatMult 0 0.00% 68.53% # Class of executed instruction system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.53% # Class of executed instruction system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::MemRead 25426401 17.75% 86.28% # Class of executed instruction -system.cpu0.op_class::MemWrite 19648791 13.72% 100.00% # Class of executed instruction +system.cpu0.op_class::MemRead 25408167 17.75% 86.28% # Class of executed instruction +system.cpu0.op_class::MemWrite 19633320 13.72% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 143219456 # Class of executed instruction -system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.tags.replacements 693439 # number of replacements -system.cpu0.dcache.tags.tagsinuse 491.449824 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 43066582 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 693951 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 62.059975 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 1151827000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 491.449824 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.959863 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.959863 # Average percentage of cache occupancy +system.cpu0.op_class::total 143146475 # Class of executed instruction +system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.tags.replacements 692883 # number of replacements +system.cpu0.dcache.tags.tagsinuse 489.706194 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 43033783 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 693395 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 62.062436 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 1207347000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 489.706194 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.956457 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.956457 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 102 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 328 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 82 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 101 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 317 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 94 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 88514427 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 88514427 # Number of data accesses -system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.ReadReq_hits::cpu0.data 23911425 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 23911425 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 18032865 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 18032865 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 319065 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 319065 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 365782 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 365782 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 362736 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 362736 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 41944290 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 41944290 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 42263355 # number of overall hits -system.cpu0.dcache.overall_hits::total 42263355 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 397667 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 397667 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 324388 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 324388 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 127754 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 127754 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21573 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 21573 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 19602 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 19602 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 722055 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 722055 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 849809 # number of overall misses -system.cpu0.dcache.overall_misses::total 849809 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5269907000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 5269907000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 5597938000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 5597938000 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 327322000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 327322000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 460475500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 460475500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1158000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1158000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 10867845000 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 10867845000 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 10867845000 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 10867845000 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 24309092 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 24309092 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 18357253 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 18357253 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 446819 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 446819 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 387355 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 387355 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 382338 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 382338 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 42666345 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 42666345 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 43113164 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 43113164 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.016359 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.016359 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.017671 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.017671 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.285919 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.285919 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.055693 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.055693 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.051269 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051269 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.016923 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.016923 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.019711 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.019711 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13252.060141 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 13252.060141 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 17256.920725 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 17256.920725 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15172.762249 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15172.762249 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23491.250893 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23491.250893 # average StoreCondReq miss latency +system.cpu0.dcache.tags.tag_accesses 88447658 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 88447658 # Number of data accesses +system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.ReadReq_hits::cpu0.data 23895020 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 23895020 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 18016527 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 18016527 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 319201 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 319201 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 365698 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 365698 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 362461 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 362461 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 41911547 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 41911547 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 42230748 # number of overall hits +system.cpu0.dcache.overall_hits::total 42230748 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 396353 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 396353 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 325830 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 325830 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 127542 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 127542 # number of SoftPFReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21311 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 21311 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 19654 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 19654 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 722183 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 722183 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 849725 # number of overall misses +system.cpu0.dcache.overall_misses::total 849725 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5544958500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 5544958500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 6307912000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 6307912000 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 337776000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 337776000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 461133500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 461133500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1598000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1598000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 11852870500 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 11852870500 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 11852870500 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 11852870500 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 24291373 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 24291373 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 18342357 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 18342357 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 446743 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 446743 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 387009 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 387009 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 382115 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 382115 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 42633730 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 42633730 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 43080473 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 43080473 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.016317 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.016317 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.017764 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.017764 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.285493 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.285493 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.055066 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.055066 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.051435 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051435 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.016939 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.016939 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.019724 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.019724 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13989.949616 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 13989.949616 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 19359.518767 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 19359.518767 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15849.842804 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15849.842804 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23462.577592 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23462.577592 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 15051.270333 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 15051.270333 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 12788.573668 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 12788.573668 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16412.558174 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 16412.558174 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 13949.066463 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 13949.066463 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 693439 # number of writebacks -system.cpu0.dcache.writebacks::total 693439 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 25271 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 25271 # number of ReadReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 15260 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 15260 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 25271 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 25271 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 25271 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 25271 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 372396 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 372396 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 324388 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 324388 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 100689 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 100689 # number of SoftPFReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6313 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6313 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 19602 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 19602 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 696784 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 696784 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 797473 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 797473 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 31786 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31786 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 28463 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 28463 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 60249 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 60249 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4503432000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4503432000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5273550000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5273550000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1615902000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1615902000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 94571500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 94571500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 440907500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 440907500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1124000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1124000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9776982000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 9776982000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11392884000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 11392884000 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6628627500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6628627500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6628627500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6628627500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.015319 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.015319 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.017671 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017671 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.225346 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.225346 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016298 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016298 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051269 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051269 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016331 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.016331 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.018497 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.018497 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12093.126672 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12093.126672 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 16256.920725 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 16256.920725 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16048.446206 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16048.446206 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14980.437193 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14980.437193 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22492.985410 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22492.985410 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 692883 # number of writebacks +system.cpu0.dcache.writebacks::total 692883 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 25228 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 25228 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 15026 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 15026 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 25229 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 25229 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 25229 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 25229 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 371125 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 371125 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 325829 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 325829 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 100399 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 100399 # number of SoftPFReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6285 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6285 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 19654 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 19654 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 696954 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 696954 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 797353 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 797353 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 31790 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31790 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 28464 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 28464 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 60254 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 60254 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4765649500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4765649500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5981552000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5981552000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1664266000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1664266000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 99162500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 99162500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 441526500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 441526500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1551000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1551000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10747201500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 10747201500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 12411467500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 12411467500 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6632422500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6632422500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6632422500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6632422500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.015278 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.015278 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.017764 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017764 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.224735 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.224735 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016240 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016240 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051435 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051435 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016347 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.016347 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.018508 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.018508 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12841.089929 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12841.089929 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 18357.948494 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 18357.948494 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16576.519686 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16576.519686 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15777.645187 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15777.645187 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22464.968963 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22464.968963 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 14031.582241 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 14031.582241 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 14286.231634 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 14286.231634 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208539.215378 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208539.215378 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 110020.539760 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 110020.539760 # average overall mshr uncacheable latency -system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.tags.replacements 1105141 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.449200 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 117971876 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1105653 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 106.698825 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 14058125000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.449200 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998924 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.998924 # Average percentage of cache occupancy +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 15420.245095 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15420.245095 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15565.837841 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15565.837841 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208632.352941 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208632.352941 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 110074.393401 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 110074.393401 # average overall mshr uncacheable latency +system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states +system.cpu0.icache.tags.replacements 1103683 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.436898 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 117915250 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1104195 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 106.788430 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 14180312000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.436898 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998900 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.998900 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::0 85 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::1 213 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::2 214 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 239260738 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 239260738 # Number of data accesses -system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.ReadReq_hits::cpu0.inst 117971876 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 117971876 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 117971876 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 117971876 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 117971876 # number of overall hits -system.cpu0.icache.overall_hits::total 117971876 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 1105662 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1105662 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 1105662 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1105662 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 1105662 # number of overall misses -system.cpu0.icache.overall_misses::total 1105662 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 11445416000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 11445416000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 11445416000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 11445416000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 11445416000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 11445416000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 119077538 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 119077538 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 119077538 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 119077538 # number of demand (read+write) accesses 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overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 10351.640917 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10351.640917 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 10351.640917 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 239143112 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 239143112 # Number of data accesses +system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states +system.cpu0.icache.ReadReq_hits::cpu0.inst 117915250 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 117915250 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 117915250 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 117915250 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 117915250 # number of overall hits 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-system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 89937.541565 # average overall mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 89937.541565 # average overall mshr uncacheable latency -system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.prefetcher.num_hwpf_issued 1836809 # number of hwpf issued -system.cpu0.l2cache.prefetcher.pfIdentified 1836835 # number of prefetch candidates identified -system.cpu0.l2cache.prefetcher.pfBufferHit 22 # number of redundant prefetches already in prefetch queue +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 11358993000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 11358993000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 11358993000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 11358993000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 11358993000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 11358993000 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 863305500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 863305500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 863305500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 863305500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.009278 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009278 # mshr miss rate for ReadReq accesses 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10287.042068 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 95688.927067 # average ReadReq mshr uncacheable latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 95688.927067 # average ReadReq mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 95688.927067 # average overall mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 95688.927067 # average overall mshr uncacheable latency +system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states +system.cpu0.l2cache.prefetcher.num_hwpf_issued 1852661 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 1852734 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 64 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu0.l2cache.prefetcher.pfSpanPage 235109 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.tags.replacements 260353 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 15640.705301 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 1686155 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 275976 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 6.109789 # Average number of references to valid blocks. +system.cpu0.l2cache.prefetcher.pfSpanPage 236762 # number of prefetches not generated due to page crossing +system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states +system.cpu0.l2cache.tags.replacements 259898 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 15638.452129 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 1682248 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 275540 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 6.105277 # Average number of references to valid blocks. system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 14471.492082 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 1.272651 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.132938 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1167.807630 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.883270 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000078 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_blocks::writebacks 14455.048208 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 1.347817 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.124083 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1181.932022 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.882266 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000082 # Average percentage of cache occupancy system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000008 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.071277 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.954633 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 311 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 4 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15308 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.072139 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.954495 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1022 340 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 9 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15293 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 7 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 29 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 131 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 144 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 30 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 149 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 154 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 2 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 2 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 177 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 815 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 6065 # Occupied blocks per task id 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of ReadExReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 2205065500 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 3053362500 # number of ReadCleanReq MSHR miss cycles +system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 3053362500 # number of ReadCleanReq MSHR miss cycles +system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 2745598500 # number of ReadSharedReq MSHR miss cycles +system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 2745598500 # number of ReadSharedReq MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 7105000 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 2775500 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 3053362500 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 4950664000 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::total 8013907000 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 7105000 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 2775500 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 3053362500 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 4950664000 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 16752910842 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::total 24766817842 # number of overall MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 795640500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 6377687500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 7173328000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 795640500 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 6377687500 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 7173328000 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.031180 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.035531 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.032543 # mshr miss rate for ReadReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for UpgradeReq accesses @@ -1199,118 +1211,118 @@ system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.154909 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.154909 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.056407 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.056407 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.211578 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.211578 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.025468 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.031119 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.056407 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.191195 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.110166 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.025468 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.031119 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.056407 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.191195 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.153928 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.153928 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.056280 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.056280 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.212451 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.212451 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.031180 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.035531 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.056280 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.191291 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.110222 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.031180 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.035531 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.056280 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.191291 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.249260 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 18143.678161 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17514.184397 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 17922.885572 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 53346.929538 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 53346.929538 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17108.334694 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17108.334694 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15005.995510 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15005.995510 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 216874.500000 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 216874.500000 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 40084.971472 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 40084.971472 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 41306.780830 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 41306.780830 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 23832.746722 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 23832.746722 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 18143.678161 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17514.184397 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 41306.780830 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 28568.853742 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 32406.137544 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 18143.678161 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17514.184397 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 41306.780830 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 28568.853742 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 53346.929538 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 44091.685230 # average overall mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 82437.541565 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200526.253697 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 174418.716918 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 82437.541565 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 105793.083703 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 102751.209020 # average overall mshr uncacheable latency -system.cpu0.toL2Bus.snoop_filter.tot_requests 3740310 # Total number of requests made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_requests 1886004 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 27868 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.snoop_filter.tot_snoops 209163 # Total number of snoops made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 207471 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 1692 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states -system.cpu0.toL2Bus.trans_dist::ReadReq 61471 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 1694410 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 28463 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 28463 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackDirty 706729 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackClean 1319793 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::CleanEvict 79890 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 307615 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 87684 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 41751 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 111919 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 49 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 79 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 288494 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 284839 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1105662 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadSharedReq 565382 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateReq 3277 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3334509 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2561453 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 10930 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 24498 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 5931390 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 141527480 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 96553100 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 18124 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 40992 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 238139696 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 885320 # Total snoops (count) -system.cpu0.toL2Bus.snoopTraffic 18675332 # Total snoop traffic (bytes) -system.cpu0.toL2Bus.snoop_fanout::samples 2797680 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 0.089870 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.288103 # Request fanout histogram +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.251989 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 23218.954248 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17455.974843 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 21248.387097 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 63298.311238 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 63298.311238 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17135.000543 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17135.000543 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14982.087426 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14982.087426 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 399500 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 399500 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 52937.665050 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 52937.665050 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 49132.874728 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49132.874728 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 27047.300293 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 27047.300293 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 23218.954248 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17455.974843 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 49132.874728 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 34580.127825 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 38944.998178 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 23218.954248 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17455.974843 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 49132.874728 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 34580.127825 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 63298.311238 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 52645.959519 # average overall mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 88188.927067 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200619.298522 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 175765.167108 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 88188.927067 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 105846.707273 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 103547.087014 # average overall mshr uncacheable latency +system.cpu0.toL2Bus.snoop_filter.tot_requests 3736636 # Total number of requests made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_requests 1884055 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 27898 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.snoop_filter.tot_snoops 214108 # Total number of snoops made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 212409 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 1699 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states +system.cpu0.toL2Bus.trans_dist::ReadReq 61364 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 1691356 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 28464 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 28464 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackDirty 703950 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackClean 1320281 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::CleanEvict 79590 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 311154 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 87625 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 41858 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 112323 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 44 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 88 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 289865 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 286282 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1104204 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 563680 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateReq 3258 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3330135 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2561187 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 10874 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 23944 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 5926140 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 141340856 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 96515744 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 17900 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 39256 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 237913756 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 888922 # Total snoops (count) +system.cpu0.toL2Bus.snoopTraffic 18673228 # Total snoop traffic (bytes) +system.cpu0.toL2Bus.snoop_fanout::samples 2798771 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 0.091578 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.290526 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::0 2547944 91.07% 91.07% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 248044 8.87% 99.94% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 1692 0.06% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 2544165 90.90% 90.90% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 252907 9.04% 99.94% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 1699 0.06% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 2797680 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 3721587498 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 2798771 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 3717731500 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 113922479 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 114379544 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 1667515000 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 1665328000 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 1206437474 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 1206139485 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu0.toL2Bus.respLayer2.occupancy 6399000 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 14255489 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 14135489 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states +system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1340,62 +1352,67 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states -system.cpu1.dtb.walker.walks 3379 # Table walker walks requested -system.cpu1.dtb.walker.walksShort 3379 # Table walker walks initiated with short descriptors -system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 683 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 2696 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walkWaitTime::samples 3379 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 3379 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 3379 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 2609 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 12498.275201 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 11540.409783 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 5547.212388 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-8191 616 23.61% 23.61% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::8192-16383 1660 63.63% 87.24% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::16384-24575 255 9.77% 97.01% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::24576-32767 67 2.57% 99.58% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::32768-40959 5 0.19% 99.77% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::40960-49151 3 0.11% 99.89% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::49152-57343 2 0.08% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::98304-106495 1 0.04% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 2609 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples -2073200828 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 -2073200828 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total -2073200828 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 1934 74.13% 74.13% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::1M 675 25.87% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 2609 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 3379 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.walker.walks 3333 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 3333 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 662 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 2671 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walkWaitTime::samples 3333 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 3333 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 3333 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 2563 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 11950.253609 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 10994.949142 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 5354.487249 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-4095 3 0.12% 0.12% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::4096-8191 723 28.21% 28.33% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::8192-12287 1059 41.32% 69.64% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::12288-16383 482 18.81% 88.45% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::16384-20479 76 2.97% 91.42% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::20480-24575 147 5.74% 97.15% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::24576-28671 46 1.79% 98.95% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::28672-32767 15 0.59% 99.53% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::32768-36863 4 0.16% 99.69% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::36864-40959 3 0.12% 99.80% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::40960-45055 2 0.08% 99.88% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::49152-53247 1 0.04% 99.92% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::53248-57343 2 0.08% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 2563 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples -1936423828 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 -1936423828 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total -1936423828 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 1909 74.48% 74.48% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 654 25.52% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 2563 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 3333 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 3379 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2609 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 3333 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2563 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2609 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 5988 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2563 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 5896 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 3943912 # DTB read hits -system.cpu1.dtb.read_misses 2863 # DTB read misses -system.cpu1.dtb.write_hits 3421052 # DTB write hits -system.cpu1.dtb.write_misses 516 # DTB write misses +system.cpu1.dtb.read_hits 3943012 # DTB read hits +system.cpu1.dtb.read_misses 2827 # DTB read misses +system.cpu1.dtb.write_hits 3420749 # DTB write hits +system.cpu1.dtb.write_misses 506 # DTB write misses system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1981 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 1972 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 312 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 323 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 163 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 3946775 # DTB read accesses -system.cpu1.dtb.write_accesses 3421568 # DTB write accesses +system.cpu1.dtb.read_accesses 3945839 # DTB read accesses +system.cpu1.dtb.write_accesses 3421255 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 7364964 # DTB hits -system.cpu1.dtb.misses 3379 # DTB misses -system.cpu1.dtb.accesses 7368343 # DTB accesses -system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.hits 7363761 # DTB hits +system.cpu1.dtb.misses 3333 # DTB misses +system.cpu1.dtb.accesses 7367094 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1425,7 +1442,7 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states +system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states system.cpu1.itb.walker.walks 1746 # Table walker walks requested system.cpu1.itb.walker.walksShort 1746 # Table walker walks initiated with short descriptors system.cpu1.itb.walker.walksShortTerminationLevel::Level1 168 # Level at which table walker walks with short descriptors terminate @@ -1434,24 +1451,24 @@ system.cpu1.itb.walker.walkWaitTime::samples 1746 system.cpu1.itb.walker.walkWaitTime::0 1746 100.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu1.itb.walker.walkWaitTime::total 1746 # Table walker wait (enqueue to first request) latency system.cpu1.itb.walker.walkCompletionTime::samples 1107 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 13079.042457 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 12148.751119 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 5740.258970 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::4096-8191 165 14.91% 14.91% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::8192-12287 593 53.57% 68.47% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::12288-16383 181 16.35% 84.82% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::16384-20479 52 4.70% 89.52% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::20480-24575 63 5.69% 95.21% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::24576-28671 26 2.35% 97.56% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::28672-32767 17 1.54% 99.10% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::32768-36863 3 0.27% 99.37% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::36864-40959 1 0.09% 99.46% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 12715.898826 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 11637.572785 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 6041.889650 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::4096-8191 210 18.97% 18.97% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::8192-12287 573 51.76% 70.73% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::12288-16383 161 14.54% 85.28% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::16384-20479 52 4.70% 89.97% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::20480-24575 52 4.70% 94.67% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::24576-28671 26 2.35% 97.02% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::28672-32767 21 1.90% 98.92% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::32768-36863 3 0.27% 99.19% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::36864-40959 3 0.27% 99.46% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::40960-45055 4 0.36% 99.82% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::49152-53247 2 0.18% 100.00% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::total 1107 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples -2073744828 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 -2073744828 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total -2073744828 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::samples -1937292828 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 -1937292828 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total -1937292828 # Table walker pending requests distribution system.cpu1.itb.walker.walkPageSizes::4K 939 84.82% 84.82% # Table walker page sizes translated system.cpu1.itb.walker.walkPageSizes::1M 168 15.18% 100.00% # Table walker page sizes translated system.cpu1.itb.walker.walkPageSizes::total 1107 # Table walker page sizes translated @@ -1462,7 +1479,7 @@ system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1107 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1107 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin::total 2853 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 16566340 # ITB inst hits +system.cpu1.itb.inst_hits 16565425 # ITB inst hits system.cpu1.itb.inst_misses 1746 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses @@ -1479,56 +1496,56 @@ system.cpu1.itb.domain_faults 0 # Nu system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 16568086 # ITB inst accesses -system.cpu1.itb.hits 16566340 # DTB hits +system.cpu1.itb.inst_accesses 16567171 # ITB inst accesses +system.cpu1.itb.hits 16565425 # DTB hits system.cpu1.itb.misses 1746 # DTB misses -system.cpu1.itb.accesses 16568086 # DTB accesses -system.cpu1.numPwrStateTransitions 5497 # Number of power state transitions -system.cpu1.pwrStateClkGateDist::samples 2749 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::mean 1034540641.602037 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::stdev 25769735768.471432 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::underflows 1960 71.30% 71.30% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1000-5e+10 783 28.48% 99.78% # Distribution of time spent in the clock gated state +system.cpu1.itb.accesses 16567171 # DTB accesses +system.cpu1.numPwrStateTransitions 5507 # Number of power state transitions +system.cpu1.pwrStateClkGateDist::samples 2754 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::mean 1032876592.840595 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::stdev 25746480816.391750 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::underflows 1963 71.28% 71.28% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1000-5e+10 785 28.50% 99.78% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::5e+10-1e+11 2 0.07% 99.85% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 1 0.04% 99.89% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::5e+11-5.5e+11 1 0.04% 99.93% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::8e+11-8.5e+11 1 0.04% 99.96% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::9e+11-9.5e+11 1 0.04% 100.00% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::max_value 929980464320 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::total 2749 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateResidencyTicks::ON 26048486236 # Cumulative time (in ticks) in various power states -system.cpu1.pwrStateResidencyTicks::CLK_GATED 2843952223764 # Cumulative time (in ticks) in various power states -system.cpu1.numCycles 5739069639 # number of cpu cycles simulated +system.cpu1.pwrStateClkGateDist::max_value 929980503556 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::total 2754 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateResidencyTicks::ON 26280526317 # Cumulative time (in ticks) in various power states +system.cpu1.pwrStateResidencyTicks::CLK_GATED 2844542136683 # Cumulative time (in ticks) in various power states +system.cpu1.numCycles 5740713090 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2749 # number of quiesce instructions executed -system.cpu1.committedInsts 16210815 # Number of instructions committed -system.cpu1.committedOps 19752329 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 17813732 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 1857 # Number of float alu accesses -system.cpu1.num_func_calls 1029438 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1815045 # number of instructions that are conditional controls -system.cpu1.num_int_insts 17813732 # number of integer instructions -system.cpu1.num_fp_insts 1857 # number of float instructions -system.cpu1.num_int_register_reads 32326512 # number of times the integer registers were read -system.cpu1.num_int_register_writes 12493939 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 1341 # number of times the floating registers were read +system.cpu1.kern.inst.quiesce 2754 # number of quiesce instructions executed +system.cpu1.committedInsts 16209756 # Number of instructions committed +system.cpu1.committedOps 19749987 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 17811459 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 1792 # Number of float alu accesses +system.cpu1.num_func_calls 1029227 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 1814790 # number of instructions that are conditional controls +system.cpu1.num_int_insts 17811459 # number of integer instructions +system.cpu1.num_fp_insts 1792 # number of float instructions +system.cpu1.num_int_register_reads 32322640 # number of times the integer registers were read +system.cpu1.num_int_register_writes 12491718 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 1276 # number of times the floating registers were read system.cpu1.num_fp_register_writes 516 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 72207765 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 6423893 # number of times the CC registers were written -system.cpu1.num_mem_refs 7598514 # number of memory refs -system.cpu1.num_load_insts 4055507 # Number of load instructions -system.cpu1.num_store_insts 3543007 # Number of store instructions -system.cpu1.num_idle_cycles 5686981123.489185 # Number of idle cycles -system.cpu1.num_busy_cycles 52088515.510815 # Number of busy cycles -system.cpu1.not_idle_fraction 0.009076 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.990924 # Percentage of idle cycles -system.cpu1.Branches 2922923 # Number of branches fetched +system.cpu1.num_cc_register_reads 72198073 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 6423445 # number of times the CC registers were written +system.cpu1.num_mem_refs 7597281 # number of memory refs +system.cpu1.num_load_insts 4054552 # Number of load instructions +system.cpu1.num_store_insts 3542729 # Number of store instructions +system.cpu1.num_idle_cycles 5688160571.384175 # Number of idle cycles +system.cpu1.num_busy_cycles 52552518.615825 # Number of busy cycles +system.cpu1.not_idle_fraction 0.009154 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.990846 # Percentage of idle cycles +system.cpu1.Branches 2922489 # Number of branches fetched system.cpu1.op_class::No_OpClass 66 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 12474914 62.05% 62.05% # Class of executed instruction -system.cpu1.op_class::IntMult 26468 0.13% 62.19% # Class of executed instruction +system.cpu1.op_class::IntAlu 12473914 62.06% 62.06% # Class of executed instruction +system.cpu1.op_class::IntMult 26414 0.13% 62.19% # Class of executed instruction system.cpu1.op_class::IntDiv 0 0.00% 62.19% # Class of executed instruction system.cpu1.op_class::FloatAdd 0 0.00% 62.19% # Class of executed instruction system.cpu1.op_class::FloatCmp 0 0.00% 62.19% # Class of executed instruction @@ -1552,583 +1569,584 @@ system.cpu1.op_class::SimdFloatAlu 0 0.00% 62.19% # Cl system.cpu1.op_class::SimdFloatCmp 0 0.00% 62.19% # Class of executed instruction system.cpu1.op_class::SimdFloatCvt 0 0.00% 62.19% # Class of executed instruction system.cpu1.op_class::SimdFloatDiv 0 0.00% 62.19% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 3329 0.02% 62.20% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 3315 0.02% 62.20% # Class of executed instruction system.cpu1.op_class::SimdFloatMult 0 0.00% 62.20% # Class of executed instruction system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 62.20% # Class of executed instruction system.cpu1.op_class::SimdFloatSqrt 0 0.00% 62.20% # Class of executed instruction -system.cpu1.op_class::MemRead 4055507 20.17% 82.38% # Class of executed instruction -system.cpu1.op_class::MemWrite 3543007 17.62% 100.00% # Class of executed instruction +system.cpu1.op_class::MemRead 4054552 20.17% 82.38% # Class of executed instruction +system.cpu1.op_class::MemWrite 3542729 17.62% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 20103291 # Class of executed instruction -system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.tags.replacements 186972 # number of replacements -system.cpu1.dcache.tags.tagsinuse 469.131643 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 7097155 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 187306 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 37.890698 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 127531940000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 469.131643 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.916273 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.916273 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 334 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 255 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::3 79 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.652344 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 14948788 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 14948788 # Number of data accesses -system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.ReadReq_hits::cpu1.data 3631994 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 3631994 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 3232351 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 3232351 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 48894 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 48894 # number of SoftPFReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 78959 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 78959 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 70892 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 70892 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 6864345 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 6864345 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 6913239 # number of overall hits -system.cpu1.dcache.overall_hits::total 6913239 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 133677 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 133677 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 91948 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 91948 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30343 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 30343 # number of SoftPFReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 16973 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 16973 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23209 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 23209 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 225625 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 225625 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 255968 # number of overall misses -system.cpu1.dcache.overall_misses::total 255968 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2021367000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 2021367000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2373794500 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 2373794500 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 317489000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 317489000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 544203500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 544203500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1998500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1998500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 4395161500 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 4395161500 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 4395161500 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 4395161500 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 3765671 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 3765671 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 3324299 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 3324299 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 79237 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 79237 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 95932 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 95932 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 94101 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 94101 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 7089970 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 7089970 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 7169207 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 7169207 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.035499 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.035499 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.027659 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.027659 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.382940 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.382940 # miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.176927 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.176927 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.246639 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.246639 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.031823 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.031823 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.035704 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.035704 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15121.277407 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 15121.277407 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 25816.706182 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 25816.706182 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18705.532316 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18705.532316 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23447.951226 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23447.951226 # average StoreCondReq miss latency +system.cpu1.op_class::total 20100990 # Class of executed instruction +system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.tags.replacements 186832 # number of replacements +system.cpu1.dcache.tags.tagsinuse 467.596388 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 7094042 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 187196 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 37.896333 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 105561729000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 467.596388 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.913274 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.913274 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 364 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 276 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::3 88 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.710938 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 14946466 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 14946466 # Number of data accesses +system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.ReadReq_hits::cpu1.data 3631076 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 3631076 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 3232073 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 3232073 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 48864 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 48864 # number of SoftPFReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 78973 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 78973 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 70916 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 70916 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 6863149 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 6863149 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 6912013 # number of overall hits +system.cpu1.dcache.overall_hits::total 6912013 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 133685 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 133685 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 91868 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 91868 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30333 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 30333 # number of SoftPFReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 17012 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 17012 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23235 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 23235 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 225553 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 225553 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 255886 # number of overall misses +system.cpu1.dcache.overall_misses::total 255886 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2037941500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 2037941500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2527681500 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 2527681500 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 319638500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 319638500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 545121500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 545121500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1812500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1812500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 4565623000 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 4565623000 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 4565623000 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 4565623000 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 3764761 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 3764761 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 3323941 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 3323941 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 79197 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 79197 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 95985 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 95985 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 94151 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 94151 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 7088702 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 7088702 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 7167899 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 7167899 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.035510 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.035510 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.027638 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.027638 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.383007 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.383007 # miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.177236 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.177236 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.246784 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.246784 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.031819 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.031819 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.035699 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.035699 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15244.354266 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 15244.354266 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 27514.275918 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 27514.275918 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18789.001881 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18789.001881 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23461.222294 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23461.222294 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19479.940166 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 19479.940166 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17170.745953 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 17170.745953 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20241.907667 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 20241.907667 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17842.410292 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 17842.410292 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.dcache.writebacks::writebacks 186972 # number of writebacks -system.cpu1.dcache.writebacks::total 186972 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 283 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 283 # number of ReadReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12048 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12048 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 283 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 283 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 283 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 283 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 133394 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 133394 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 91948 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 91948 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 29641 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 29641 # number of SoftPFReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4925 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4925 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23209 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 23209 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 225342 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 225342 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 254983 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 254983 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 3099 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.ReadReq_mshr_uncacheable::total 3099 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2450 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2450 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 5549 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 5549 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1881488500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1881488500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2281846500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2281846500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 500338500 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 500338500 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 85063000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 85063000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 521039500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 521039500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1953500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1953500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4163335000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 4163335000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4663673500 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 4663673500 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 443787500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 443787500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 443787500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 443787500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035424 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035424 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027659 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027659 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.374080 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.374080 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.051338 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.051338 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.246639 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.246639 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.writebacks::writebacks 186832 # number of writebacks +system.cpu1.dcache.writebacks::total 186832 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 254 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 254 # number of ReadReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12014 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12014 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 254 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 254 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 254 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 254 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 133431 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 133431 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 91868 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 91868 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 29599 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 29599 # number of SoftPFReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4998 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4998 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23235 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 23235 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 225299 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 225299 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 254898 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 254898 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 3096 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 3096 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2451 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2451 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 5547 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 5547 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1895035500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1895035500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2435813500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2435813500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 504348000 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 504348000 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 87440500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 87440500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 521927500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 521927500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1771500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1771500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4330849000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 4330849000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4835197000 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 4835197000 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 443722000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 443722000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 443722000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 443722000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035442 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035442 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027638 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027638 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.373739 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.373739 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.052071 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.052071 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.246784 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.246784 # mshr miss rate for StoreCondReq accesses system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031783 # mshr miss rate for demand accesses system.cpu1.dcache.demand_mshr_miss_rate::total 0.031783 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035566 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.035566 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14104.746091 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14104.746091 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 24816.706182 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 24816.706182 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16879.946695 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 16879.946695 # average SoftPFReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17271.675127 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17271.675127 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22449.890129 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22449.890129 # average StoreCondReq mshr miss latency +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035561 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.035561 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14202.363019 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14202.363019 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26514.275918 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 26514.275918 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17039.359438 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17039.359438 # average SoftPFReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17495.098039 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17495.098039 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22462.986873 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22462.986873 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18475.628156 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18475.628156 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18290.135029 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18290.135029 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 143203.452727 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 143203.452727 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 79976.121824 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 79976.121824 # average overall mshr uncacheable latency -system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states -system.cpu1.icache.tags.replacements 505656 # number of replacements -system.cpu1.icache.tags.tagsinuse 498.477037 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 16060167 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 506168 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 31.728926 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 85274966000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.477037 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.973588 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.973588 # Average percentage of cache occupancy +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19222.672981 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19222.672981 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18969.144521 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18969.144521 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 143321.059432 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 143321.059432 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 79993.149450 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 79993.149450 # average overall mshr uncacheable latency +system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states 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system.cpu1.icache.tags.age_task_id_blocks_1024::3 121 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::4 3 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 33638838 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 33638838 # Number of data accesses -system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states -system.cpu1.icache.ReadReq_hits::cpu1.inst 16060167 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 16060167 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 16060167 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 16060167 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 16060167 # number of overall hits -system.cpu1.icache.overall_hits::total 16060167 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 506168 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 506168 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 506168 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 506168 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 506168 # number of overall misses -system.cpu1.icache.overall_misses::total 506168 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4710776500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 4710776500 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 4710776500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 4710776500 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 4710776500 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 4710776500 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 16566335 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 16566335 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 16566335 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 16566335 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 16566335 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 16566335 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.030554 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.030554 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.030554 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.030554 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.030554 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.030554 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9306.744994 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 9306.744994 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9306.744994 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 9306.744994 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9306.744994 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 9306.744994 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 33637116 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 33637116 # Number of data accesses +system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states +system.cpu1.icache.ReadReq_hits::cpu1.inst 16059144 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 16059144 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 16059144 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 16059144 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 16059144 # number of overall hits +system.cpu1.icache.overall_hits::total 16059144 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 506276 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 506276 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 506276 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 506276 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 506276 # number of overall misses +system.cpu1.icache.overall_misses::total 506276 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4773110000 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 4773110000 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 4773110000 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 4773110000 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 4773110000 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 4773110000 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 16565420 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 16565420 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 16565420 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 16565420 # number of demand (read+write) accesses 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overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 9427.881235 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9427.881235 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 9427.881235 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.icache.writebacks::writebacks 505656 # number of writebacks -system.cpu1.icache.writebacks::total 505656 # number of writebacks -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 506168 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 506168 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 506168 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 506168 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 506168 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 506168 # number of overall MSHR misses +system.cpu1.icache.writebacks::writebacks 505764 # number of writebacks +system.cpu1.icache.writebacks::total 505764 # number of writebacks +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 506276 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 506276 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 506276 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 506276 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 506276 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 506276 # number of overall MSHR misses system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 177 # number of ReadReq MSHR uncacheable system.cpu1.icache.ReadReq_mshr_uncacheable::total 177 # number of ReadReq MSHR uncacheable system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 177 # number of overall MSHR uncacheable misses system.cpu1.icache.overall_mshr_uncacheable_misses::total 177 # number of overall MSHR uncacheable misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4457692500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 4457692500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4457692500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 4457692500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4457692500 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 4457692500 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 15627500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 15627500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 15627500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 15627500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.030554 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.030554 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.030554 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.030554 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.030554 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.030554 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8806.744994 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8806.744994 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8806.744994 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 8806.744994 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8806.744994 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 8806.744994 # average overall mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 88290.960452 # average ReadReq mshr uncacheable latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 88290.960452 # average ReadReq mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 88290.960452 # average overall mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 88290.960452 # average overall mshr uncacheable latency -system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.prefetcher.num_hwpf_issued 198543 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 198543 # number of prefetch candidates identified +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4519972000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 4519972000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4519972000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 4519972000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4519972000 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 4519972000 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 17010500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 17010500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 17010500 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 17010500 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.030562 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.030562 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.030562 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.030562 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.030562 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.030562 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8927.881235 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8927.881235 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8927.881235 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 8927.881235 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8927.881235 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 8927.881235 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 96104.519774 # average ReadReq mshr uncacheable latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 96104.519774 # average ReadReq mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 96104.519774 # average overall mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 96104.519774 # average overall mshr uncacheable latency +system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states +system.cpu1.l2cache.prefetcher.num_hwpf_issued 197759 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 197759 # number of prefetch candidates identified system.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 58537 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.tags.replacements 43670 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 14604.323800 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 603874 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 58010 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 10.409826 # Average number of references to valid blocks. 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blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 304 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_blocks::writebacks 14134.079332 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 3.459040 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.079959 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 410.926752 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.862676 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000211 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000127 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.025081 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.888095 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ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 418649000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 432949000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 14300000 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 418649000 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 432949000 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.104875 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.146362 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.119638 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 5547 # number of overall MSHR uncacheable misses +system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 5724 # number of overall MSHR uncacheable misses +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 6050000 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 4606500 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 10656500 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 879904235 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 879904235 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 451017000 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 451017000 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 347632000 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 347632000 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 1463500 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1463500 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1270463000 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1270463000 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 708558500 # number of ReadCleanReq MSHR miss cycles +system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 708558500 # number of ReadCleanReq MSHR miss cycles +system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 1173383500 # number of ReadSharedReq MSHR miss cycles +system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 1173383500 # number of ReadSharedReq MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 6050000 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 4606500 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 708558500 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2443846500 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::total 3163061500 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 6050000 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 4606500 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 708558500 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2443846500 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 879904235 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::total 4042965735 # number of overall MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 15683000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 418607000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 434290000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 15683000 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 418607000 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 434290000 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.109072 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.148367 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.123333 # mshr miss rate for ReadReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses @@ -2137,118 +2155,118 @@ system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.557598 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.557598 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.042134 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.042134 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.416486 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.416486 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.104875 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.146362 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.042134 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.454667 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.170670 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.104875 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.146362 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.042134 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.454667 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.554559 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.554559 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.041716 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.041716 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.414300 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.414300 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.109072 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.148367 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.041716 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.452250 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.169714 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.109072 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.148367 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.041716 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.452250 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.205250 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 14476.190476 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14110.294118 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 14316.901408 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 31612.145031 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 31612.145031 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 15295.007590 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15295.007590 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14951.027707 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14951.027707 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 807750 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 807750 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 32081.102476 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 32081.102476 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 30344.305341 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 30344.305341 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 16498.234529 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 16498.234529 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 14476.190476 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14110.294118 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 30344.305341 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 21669.056193 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 23082.885782 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 14476.190476 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14110.294118 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 30344.305341 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 21669.056193 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 31612.145031 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 24519.847717 # average overall mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 80790.960452 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 135091.642465 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 132157.814408 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 80790.960452 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 75445.846098 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 75611.072302 # average overall mshr uncacheable latency -system.cpu1.toL2Bus.snoop_filter.tot_requests 1488311 # Total number of requests made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_requests 751924 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 11152 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.snoop_filter.tot_snoops 112911 # Total number of snoops made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 104591 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 8320 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states -system.cpu1.toL2Bus.trans_dist::ReadReq 12675 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 724258 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 2450 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 2450 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackDirty 148574 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackClean 578366 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::CleanEvict 28228 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 30717 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 71065 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 40939 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 85439 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 36 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 79 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 69452 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 66978 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadCleanReq 506168 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadSharedReq 262948 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateReq 236 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1518346 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 839098 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 5647 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 10280 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 2373371 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 64757444 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 29422876 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 9292 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 16820 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 94206432 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 332481 # Total snoops (count) -system.cpu1.toL2Bus.snoopTraffic 4905948 # Total snoop traffic (bytes) -system.cpu1.toL2Bus.snoop_fanout::samples 1059226 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 0.131024 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.359953 # Request fanout histogram +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.203710 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 14336.492891 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14087.155963 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 14227.636849 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 34849.072637 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 34849.072637 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 15267.492637 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15267.492637 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14962.854560 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14962.854560 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 731750 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 731750 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 36756.827913 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 36756.827913 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 33549.171402 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 33549.171402 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 16855.567846 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 16855.567846 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 14336.492891 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14087.155963 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 33549.171402 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 23458.374129 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 25094.302125 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 14336.492891 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14087.155963 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 33549.171402 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 23458.374129 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 34849.072637 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 26722.224877 # average overall mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 88604.519774 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 135208.979328 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 132688.664833 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 88604.519774 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 75465.476834 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 75871.767994 # average overall mshr uncacheable latency +system.cpu1.toL2Bus.snoop_filter.tot_requests 1488382 # Total number of requests made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_requests 751796 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 11114 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.snoop_filter.tot_snoops 112776 # Total number of snoops made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 104479 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 8297 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states +system.cpu1.toL2Bus.trans_dist::ReadReq 12601 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 724485 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 2451 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 2451 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackDirty 147576 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackClean 578148 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::CleanEvict 27257 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 30156 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 71390 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 40982 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 85466 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 49 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 88 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 69531 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 66980 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadCleanReq 506276 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadSharedReq 263615 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateReq 248 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1518670 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 839199 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 5528 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 9873 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 2373270 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 64771268 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 29426964 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 8816 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 15476 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 94222524 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 331491 # Total snoops (count) +system.cpu1.toL2Bus.snoopTraffic 4839132 # Total snoop traffic (bytes) +system.cpu1.toL2Bus.snoop_fanout::samples 1057684 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 0.131012 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.359912 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::0 928762 87.68% 87.68% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 122144 11.53% 99.21% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 8320 0.79% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 927412 87.68% 87.68% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 121975 11.53% 99.22% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 8297 0.78% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 1059226 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 1442372000 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 1057684 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 1442349000 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 79594348 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 79817806 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 759429000 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 759591000 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 376190500 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 376283000 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu1.toL2Bus.respLayer2.occupancy 3324000 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 6075998 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 6005497 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states +system.iobus.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states system.iobus.trans_dist::ReadReq 31015 # Transaction distribution system.iobus.trans_dist::ReadResp 31015 # Transaction distribution system.iobus.trans_dist::WriteReq 59422 # Transaction distribution @@ -2299,27 +2317,27 @@ system.iobus.pkt_size_system.bridge.master::total 162796 system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321272 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 2321272 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 2484068 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 48721500 # Layer occupancy (ticks) +system.iobus.reqLayer0.occupancy 48719500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 106500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 321000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 321500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer3.occupancy 32000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 16500 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 94000 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 94500 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer8.occupancy 622500 # Layer occupancy (ticks) +system.iobus.reqLayer8.occupancy 610000 # Layer occupancy (ticks) system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer10.occupancy 23000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 12000 # Layer occupancy (ticks) +system.iobus.reqLayer13.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer14.occupancy 12000 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer15.occupancy 12000 # Layer occupancy (ticks) +system.iobus.reqLayer15.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer16.occupancy 48500 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) @@ -2333,32 +2351,32 @@ system.iobus.reqLayer20.occupancy 9000 # La system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer21.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 6160000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 6166000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 32045000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 32044000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 187728827 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 187769062 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 84718000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer3.occupancy 36782000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states system.iocache.tags.replacements 36445 # number of replacements -system.iocache.tags.tagsinuse 14.386151 # Cycle average of tags in use +system.iocache.tags.tagsinuse 14.383154 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36461 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 289285136000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 14.386151 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.899134 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.899134 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 289903742000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 14.383154 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.898947 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.898947 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 328311 # Number of tag accesses system.iocache.tags.data_accesses 328311 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states +system.iocache.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ide 255 # number of ReadReq misses system.iocache.ReadReq_misses::total 255 # number of ReadReq misses system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses @@ -2367,14 +2385,14 @@ system.iocache.demand_misses::realview.ide 36479 # system.iocache.demand_misses::total 36479 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 36479 # number of overall misses system.iocache.overall_misses::total 36479 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 34821377 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 34821377 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 4306604450 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4306604450 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 4341425827 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 4341425827 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 4341425827 # number of overall miss cycles -system.iocache.overall_miss_latency::total 4341425827 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 40888377 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 40888377 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 4391190685 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4391190685 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 4432079062 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 4432079062 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 4432079062 # number of overall miss cycles +system.iocache.overall_miss_latency::total 4432079062 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 255 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 255 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) @@ -2391,19 +2409,19 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 136554.419608 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 136554.419608 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118888.152882 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 118888.152882 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 119011.645796 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 119011.645796 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 119011.645796 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 119011.645796 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 6 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 160346.576471 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 160346.576471 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 121223.241083 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 121223.241083 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 121496.725842 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 121496.725842 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 121496.725842 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 121496.725842 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 70 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 2 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 10 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 3 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 7 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 36190 # number of writebacks system.iocache.writebacks::total 36190 # number of writebacks @@ -2415,14 +2433,14 @@ system.iocache.demand_mshr_misses::realview.ide 36479 system.iocache.demand_mshr_misses::total 36479 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 36479 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 36479 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 22071377 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 22071377 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2493082245 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2493082245 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 2515153622 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 2515153622 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 2515153622 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 2515153622 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 28138377 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 28138377 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2577641992 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2577641992 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 2605780369 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 2605780369 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 2605780369 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 2605780369 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses @@ -2431,591 +2449,565 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 86554.419608 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 86554.419608 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68824.046074 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68824.046074 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 68947.987116 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 68947.987116 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 68947.987116 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 68947.987116 # average overall mshr miss latency -system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states -system.l2c.tags.replacements 137913 # number of replacements -system.l2c.tags.tagsinuse 65077.078827 # Cycle average of tags in use -system.l2c.tags.total_refs 526584 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 203352 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 2.589520 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 102405123000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 6467.156176 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 3.052663 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.040623 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 7119.410088 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 6998.473757 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 37485.432069 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.004586 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 1431.375532 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 3211.021288 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 2361.112045 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.098681 # Average percentage of cache occupancy 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6923.893951 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 37646.371687 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 1427.225105 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 3211.431328 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 2259.694892 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.097329 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000060 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000001 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.108634 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.106788 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.571982 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.021841 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.048996 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.036028 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.992997 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 34227 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 4 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 31208 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 194 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 4904 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 29129 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id +system.l2c.tags.occ_percent::cpu0.inst 0.110219 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.105650 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.574438 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.021778 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.049003 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.034480 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.992957 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 34321 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 31064 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::1 5 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 178 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 4958 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 29180 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 96 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 1170 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 29939 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.522263 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.000061 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.476196 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 6120881 # Number of tag accesses -system.l2c.tags.data_accesses 6120881 # Number of data accesses -system.l2c.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states -system.l2c.WritebackDirty_hits::writebacks 260820 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 260820 # number of WritebackDirty hits -system.l2c.UpgradeReq_hits::cpu0.data 40104 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 5060 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 45164 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 2347 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 2252 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 4599 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 4026 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 1389 # number of ReadExReq hits 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task id +system.l2c.tags.tag_accesses 6089608 # Number of tag accesses +system.l2c.tags.data_accesses 6089608 # Number of data accesses +system.l2c.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states +system.l2c.WritebackDirty_hits::writebacks 259449 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 259449 # number of WritebackDirty hits +system.l2c.UpgradeReq_hits::cpu0.data 40103 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 4906 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 45009 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 2386 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 2218 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 4604 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 4006 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 1413 # number of ReadExReq hits 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7 # number of ReadSharedReq misses +system.l2c.overall_hits::cpu1.itb.walker 20 # number of overall hits +system.l2c.overall_hits::cpu1.inst 18793 # number of overall hits +system.l2c.overall_hits::cpu1.data 12238 # number of overall hits +system.l2c.overall_hits::cpu1.l2cache.prefetcher 5311 # number of overall hits +system.l2c.overall_hits::total 183489 # number of overall hits +system.l2c.UpgradeReq_misses::cpu0.data 592 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 252 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 844 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 118 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 92 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 210 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 11217 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 8015 # number of ReadExReq misses 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(read+write) misses +system.l2c.ReadSharedReq_misses::cpu0.inst 17886 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.data 9091 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 133589 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.inst 2327 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.data 875 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 6065 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::total 169844 # number of ReadSharedReq misses +system.l2c.demand_misses::cpu0.dtb.walker 9 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 17911 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 20658 # number of demand (read+write) misses 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-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 153288.321522 # average ReadReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 64437.486145 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 96296.444771 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 62788.135593 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 65429.047962 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 90101.908166 # average overall mshr uncacheable latency -system.membus.snoop_filter.tot_requests 504508 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 283356 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.014547 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.048856 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.018407 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.047125 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.039827 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.043623 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.736846 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.850127 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.780171 # mshr miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.059603 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.024096 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.287698 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.146823 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.744797 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.109754 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.074786 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.533140 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.488132 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.059603 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.024096 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.287698 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.263258 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.744797 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.109754 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.420769 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.533140 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.507455 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.059603 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.024096 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.287698 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.263258 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.744797 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.109754 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.420769 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.533140 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.507455 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 23138.513514 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 21724.206349 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 22716.232227 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 26203.389831 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 23603.260870 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 25064.285714 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 135808.282072 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 92844.479102 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 117902.974210 # average ReadExReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 207388.888889 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 80000 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 99332.513004 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 113679.903201 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109332.090696 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 102799.180328 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 114310.286857 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 115793.712778 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 108684.198324 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 207388.888889 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 80000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 99332.513004 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 125902.378373 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109332.090696 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 102799.180328 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 94957.255456 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 115793.712778 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 109621.972035 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 207388.888889 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 80000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 99332.513004 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 125902.378373 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109332.090696 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 102799.180328 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 94957.255456 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 115793.712778 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 109621.972035 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 70188.871647 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182618.763762 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 70604.519774 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 117321.532493 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 154577.083617 # average ReadReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 70188.871647 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 96349.628240 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 70604.519774 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 65453.733766 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 90857.860981 # average overall mshr uncacheable latency +system.membus.snoop_filter.tot_requests 501880 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 282396 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 588 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 44081 # Transaction distribution -system.membus.trans_dist::ReadResp 215279 # Transaction distribution -system.membus.trans_dist::WriteReq 30913 # Transaction distribution -system.membus.trans_dist::WriteResp 30913 # Transaction distribution -system.membus.trans_dist::WritebackDirty 137329 # Transaction distribution -system.membus.trans_dist::CleanEvict 16651 # Transaction distribution -system.membus.trans_dist::UpgradeReq 64792 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 38133 # Transaction distribution +system.membus.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadReq 44082 # Transaction distribution +system.membus.trans_dist::ReadResp 214165 # Transaction distribution +system.membus.trans_dist::WriteReq 30915 # Transaction distribution +system.membus.trans_dist::WriteResp 30915 # Transaction distribution +system.membus.trans_dist::WritebackDirty 136162 # Transaction distribution +system.membus.trans_dist::CleanEvict 16178 # Transaction distribution +system.membus.trans_dist::UpgradeReq 65137 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 38197 # Transaction distribution system.membus.trans_dist::UpgradeResp 16 # Transaction distribution -system.membus.trans_dist::SCUpgradeFailReq 2 # Transaction distribution -system.membus.trans_dist::ReadExReq 40131 # Transaction distribution -system.membus.trans_dist::ReadExResp 19681 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 171198 # Transaction distribution +system.membus.trans_dist::ReadExReq 39788 # Transaction distribution +system.membus.trans_dist::ReadExResp 19211 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 170083 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107916 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13736 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 650114 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 771800 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13742 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 645838 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 767530 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72939 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 72939 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 844739 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 840469 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162796 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27472 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18707276 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 18897612 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27484 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18531148 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 18721496 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 21214732 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 123049 # Total snoops (count) +system.membus.pkt_size::total 21038616 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 123440 # Total snoops (count) system.membus.snoopTraffic 37632 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 425474 # Request fanout histogram -system.membus.snoop_fanout::mean 0.012172 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.109655 # Request fanout histogram +system.membus.snoop_fanout::samples 424426 # Request fanout histogram +system.membus.snoop_fanout::mean 0.012207 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.109809 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 420295 98.78% 98.78% # Request fanout histogram -system.membus.snoop_fanout::1 5179 1.22% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 419245 98.78% 98.78% # Request fanout histogram +system.membus.snoop_fanout::1 5181 1.22% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 425474 # Request fanout histogram -system.membus.reqLayer0.occupancy 88273000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 424426 # Request fanout histogram +system.membus.reqLayer0.occupancy 88263500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 19000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 11470000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 11456000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 976922430 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 968117274 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1118158241 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1108847564 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 1366131 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 1391627 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -3047,77 +3039,77 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states -system.toL2Bus.snoop_filter.tot_requests 1015113 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 540228 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 174806 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 29447 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 28379 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 1068 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2870000710000 # Cumulative time (in ticks) in various power states -system.toL2Bus.trans_dist::ReadReq 44084 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 511780 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 30913 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 30913 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 361959 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 119582 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 109939 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 42732 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 152671 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 79 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 79 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 51282 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 51282 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 467698 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 4573 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1273273 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 316945 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 1590218 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 35272632 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 5631700 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 40904332 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 389588 # Total snoops (count) -system.toL2Bus.snoopTraffic 15743116 # Total snoop traffic (bytes) -system.toL2Bus.snoop_fanout::samples 889230 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.395392 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.491385 # Request fanout histogram +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states +system.toL2Bus.snoop_filter.tot_requests 1012066 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 538478 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 175231 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 28833 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 27811 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 1022 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2870822663000 # Cumulative time (in ticks) in various power states +system.toL2Bus.trans_dist::ReadReq 44085 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 510917 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 30915 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 30915 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 359421 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 118152 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 110125 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 42801 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 152926 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 88 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 88 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 50897 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 50897 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 466834 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 4575 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1272193 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 313311 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 1585504 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 35206412 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 5504908 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 40711320 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 388372 # Total snoops (count) +system.toL2Bus.snoopTraffic 15694348 # Total snoop traffic (bytes) +system.toL2Bus.snoop_fanout::samples 886366 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.396986 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.491624 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 538704 60.58% 60.58% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 349458 39.30% 99.88% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 1068 0.12% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 535513 60.42% 60.42% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 349831 39.47% 99.88% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 1022 0.12% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 889230 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 894701567 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 886366 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 892357874 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 360619 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 360373 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 677372101 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 676996738 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 239236747 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 237913566 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini index 657e88994..5d8ec5a8f 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini @@ -36,7 +36,7 @@ load_addr_mask=268435455 load_offset=2147483648 machine_type=VExpress_EMM mem_mode=timing -mem_ranges=2147483648:2415919103 +mem_ranges=2147483648:2415919103:0:0:0:0 memories=system.physmem system.realview.nvmem system.realview.vram mmap_using_noreserve=false multi_proc=true @@ -73,7 +73,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911 +ranges=788529152:805306367:0:0:0:0 721420288:725614591:0:0:0:0 805306368:1073741823:0:0:0:0 1073741824:1610612735:0:0:0:0 402653184:469762047:0:0:0:0 469762048:536870911:0:0:0:0 req_size=16 resp_size=16 master=system.iobus.slave[0] @@ -153,7 +153,7 @@ icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=4 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -250,7 +250,7 @@ port=system.cpu.toL2Bus.slave[3] [system.cpu.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=1 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -382,7 +382,7 @@ port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -499,7 +499,7 @@ slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma [system.iocache] type=Cache children=tags -addr_ranges=2147483648:2415919103 +addr_ranges=2147483648:2415919103:0:0:0:0 assoc=8 clk_domain=system.clk_domain clusivity=mostly_incl @@ -544,7 +544,7 @@ size=1024 [system.membus] type=CoherentXBar -children=badaddr_responder +children=badaddr_responder snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -556,7 +556,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -588,29 +588,36 @@ update_data=false warn_access=warn pio=system.membus.default +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -630,6 +637,7 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 @@ -639,7 +647,7 @@ p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 page_policy=open_adaptive power_model=Null -range=2147483648:2415919103 +range=2147483648:2415919103:0:0:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 @@ -661,9 +669,9 @@ tRTW=2500 tWR=15000 tWTR=7500 tXAW=30000 -tXP=0 +tXP=6000 tXPDLL=0 -tXS=0 +tXS=270000 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 @@ -1016,7 +1024,7 @@ default_p_state=UNDEFINED dist_addr=738201600 dist_pio_delay=10000 eventq_index=0 -gem5_extensions=true +gem5_extensions=false int_latency=10000 it_lines=128 p_state_clk_gate_bins=20 @@ -1333,6 +1341,7 @@ conf_table_reported=false default_p_state=UNDEFINED eventq_index=0 in_addr_map=true +kvm_map=true latency=30000 latency_var=0 null=false @@ -1340,7 +1349,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -range=0:67108863 +range=0:67108863:0:0:0:0 port=system.membus.master[1] [system.realview.pci_host] @@ -1571,6 +1580,7 @@ conf_table_reported=false default_p_state=UNDEFINED eventq_index=0 in_addr_map=true +kvm_map=true latency=30000 latency_var=0 null=false @@ -1578,7 +1588,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -range=402653184:436207615 +range=402653184:436207615:0:0:0:0 port=system.iobus.master[11] [system.realview.watchdog_fake] diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout index 6d681649a..03ec36b9d 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realv gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 1 2016 17:10:05 -gem5 started Aug 1 2016 17:28:47 -gem5 executing on e108600-lin, pid 12530 +gem5 compiled Oct 11 2016 00:00:58 +gem5 started Oct 13 2016 21:01:25 +gem5 executing on e108600-lin, pid 17555 command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/fs/10.linux-boot/arm/linux/realview-simple-timing Global frequency set at 1000000000000 ticks per second @@ -29,4 +29,4 @@ info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 -Exiting @ tick 2909582799500 because m5_exit instruction encountered +Exiting @ tick 2905297782500 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt index dd34564a7..aaea4a10c 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt @@ -1,121 +1,121 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.903737 # Number of seconds simulated -sim_ticks 2903736790500 # Number of ticks simulated -final_tick 2903736790500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.905298 # Number of seconds simulated +sim_ticks 2905297782500 # Number of ticks simulated +final_tick 2905297782500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 515424 # Simulator instruction rate (inst/s) -host_op_rate 621448 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 13306386787 # Simulator tick rate (ticks/s) -host_mem_usage 582748 # Number of bytes of host memory used -host_seconds 218.22 # Real time elapsed on the host -sim_insts 112476413 # Number of instructions simulated -sim_ops 135613231 # Number of ops (including micro ops) simulated +host_inst_rate 483331 # Simulator instruction rate (inst/s) +host_op_rate 582745 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 12486239543 # Simulator tick rate (ticks/s) +host_mem_usage 580500 # Number of bytes of host memory used +host_seconds 232.68 # Real time elapsed on the host +sim_insts 112461365 # Number of instructions simulated +sim_ops 135593151 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.dtb.walker 512 # Number of bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.dtb.walker 448 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1188964 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9028260 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1184612 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 8933156 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 10218824 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1188964 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1188964 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7618752 # Number of bytes written to this memory +system.physmem.bytes_read::total 10119304 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1184612 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1184612 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7531136 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory -system.physmem.bytes_written::total 7636276 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 8 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 7548660 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 7 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 27031 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 141586 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 26963 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 140100 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 168642 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 119043 # Number of write requests responded to by this memory +system.physmem.num_reads::total 167087 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 117674 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory -system.physmem.num_writes::total 123424 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 176 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 122055 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 154 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 44 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 409460 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3109187 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 331 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3519198 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 409460 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 409460 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2623775 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 6035 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2629810 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2623775 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 176 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 407742 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3074782 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 330 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3483052 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 407742 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 407742 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2592208 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 6032 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2598240 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2592208 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 154 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 44 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 409460 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3115222 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 331 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6149008 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 168642 # Number of read requests accepted -system.physmem.writeReqs 123424 # Number of write requests accepted -system.physmem.readBursts 168642 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 123424 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10783744 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 9344 # Total number of bytes read from write queue -system.physmem.bytesWritten 7648256 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10218824 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7636276 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 146 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 3888 # Number of DRAM write bursts merged with an existing one +system.physmem.bw_total::cpu.inst 407742 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3080813 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 330 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6081292 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 167087 # Number of read requests accepted +system.physmem.writeReqs 122055 # Number of write requests accepted +system.physmem.readBursts 167087 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 122055 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10685312 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 8256 # Total number of bytes read from write queue +system.physmem.bytesWritten 7561344 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10119304 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7548660 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 129 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 3887 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 9943 # Per bank write bursts -system.physmem.perBankRdBursts::1 9648 # Per bank write bursts -system.physmem.perBankRdBursts::2 10560 # Per bank write bursts -system.physmem.perBankRdBursts::3 10245 # Per bank write bursts -system.physmem.perBankRdBursts::4 18706 # Per bank write bursts -system.physmem.perBankRdBursts::5 9867 # Per bank write bursts -system.physmem.perBankRdBursts::6 9999 # Per bank write bursts -system.physmem.perBankRdBursts::7 10271 # Per bank write bursts -system.physmem.perBankRdBursts::8 9694 # Per bank write bursts -system.physmem.perBankRdBursts::9 10419 # Per bank write bursts -system.physmem.perBankRdBursts::10 9828 # Per bank write bursts -system.physmem.perBankRdBursts::11 9028 # Per bank write bursts -system.physmem.perBankRdBursts::12 10140 # Per bank write bursts -system.physmem.perBankRdBursts::13 10489 # Per bank write bursts -system.physmem.perBankRdBursts::14 10151 # Per bank write bursts -system.physmem.perBankRdBursts::15 9508 # Per bank write bursts -system.physmem.perBankWrBursts::0 7397 # Per bank write bursts -system.physmem.perBankWrBursts::1 7199 # Per bank write bursts -system.physmem.perBankWrBursts::2 8385 # Per bank write bursts -system.physmem.perBankWrBursts::3 7801 # Per bank write bursts -system.physmem.perBankWrBursts::4 7213 # Per bank write bursts -system.physmem.perBankWrBursts::5 7134 # Per bank write bursts -system.physmem.perBankWrBursts::6 7314 # Per bank write bursts -system.physmem.perBankWrBursts::7 7590 # Per bank write bursts -system.physmem.perBankWrBursts::8 7388 # Per bank write bursts -system.physmem.perBankWrBursts::9 8015 # Per bank write bursts -system.physmem.perBankWrBursts::10 7407 # Per bank write bursts -system.physmem.perBankWrBursts::11 6899 # Per bank write bursts -system.physmem.perBankWrBursts::12 7622 # Per bank write bursts -system.physmem.perBankWrBursts::13 7751 # Per bank write bursts -system.physmem.perBankWrBursts::14 7507 # Per bank write bursts -system.physmem.perBankWrBursts::15 6882 # Per bank write bursts +system.physmem.perBankRdBursts::0 9954 # Per bank write bursts +system.physmem.perBankRdBursts::1 9813 # Per bank write bursts +system.physmem.perBankRdBursts::2 10094 # Per bank write bursts +system.physmem.perBankRdBursts::3 9518 # Per bank write bursts +system.physmem.perBankRdBursts::4 18811 # Per bank write bursts +system.physmem.perBankRdBursts::5 10188 # Per bank write bursts +system.physmem.perBankRdBursts::6 10467 # Per bank write bursts +system.physmem.perBankRdBursts::7 10858 # Per bank write bursts +system.physmem.perBankRdBursts::8 9262 # Per bank write bursts +system.physmem.perBankRdBursts::9 10094 # Per bank write bursts +system.physmem.perBankRdBursts::10 9505 # Per bank write bursts +system.physmem.perBankRdBursts::11 9184 # Per bank write bursts +system.physmem.perBankRdBursts::12 9983 # Per bank write bursts +system.physmem.perBankRdBursts::13 9847 # Per bank write bursts +system.physmem.perBankRdBursts::14 9958 # Per bank write bursts +system.physmem.perBankRdBursts::15 9422 # Per bank write bursts +system.physmem.perBankWrBursts::0 7103 # Per bank write bursts +system.physmem.perBankWrBursts::1 7218 # Per bank write bursts +system.physmem.perBankWrBursts::2 7869 # Per bank write bursts +system.physmem.perBankWrBursts::3 7374 # Per bank write bursts +system.physmem.perBankWrBursts::4 7424 # Per bank write bursts +system.physmem.perBankWrBursts::5 7558 # Per bank write bursts +system.physmem.perBankWrBursts::6 7579 # Per bank write bursts +system.physmem.perBankWrBursts::7 7921 # Per bank write bursts +system.physmem.perBankWrBursts::8 6916 # Per bank write bursts +system.physmem.perBankWrBursts::9 7516 # Per bank write bursts +system.physmem.perBankWrBursts::10 7047 # Per bank write bursts +system.physmem.perBankWrBursts::11 7122 # Per bank write bursts +system.physmem.perBankWrBursts::12 7779 # Per bank write bursts +system.physmem.perBankWrBursts::13 7383 # Per bank write bursts +system.physmem.perBankWrBursts::14 7451 # Per bank write bursts +system.physmem.perBankWrBursts::15 6886 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 9 # Number of times write queue was full causing retry -system.physmem.totGap 2903736355000 # Total gap between requests +system.physmem.numWrRetry 65 # Number of times write queue was full causing retry +system.physmem.totGap 2905297420500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 9558 # Read request sizes (log2) system.physmem.readPktSize::3 14 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 159070 # Read request sizes (log2) +system.physmem.readPktSize::6 157515 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4381 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 119043 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 167708 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 529 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 247 # What read queue length does an incoming req see +system.physmem.writePktSize::6 117674 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 166128 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 554 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 264 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see @@ -160,163 +160,178 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2046 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2984 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6117 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6096 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6314 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6034 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6526 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6858 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7526 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7572 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 8704 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 8960 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7233 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6955 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6927 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6384 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6223 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6226 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 280 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 300 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 148 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 141 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 174 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 137 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 114 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 146 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 171 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 158 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 138 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 168 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 108 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 130 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 97 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 89 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 60 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 68 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 43 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 51 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 39 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 30 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 27 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 58618 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 314.441571 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 184.322128 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 334.751512 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 21316 36.36% 36.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 14773 25.20% 61.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5607 9.57% 71.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3267 5.57% 76.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2505 4.27% 80.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1471 2.51% 83.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1045 1.78% 85.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1040 1.77% 87.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7594 12.96% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 58618 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5878 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 28.661279 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 584.674226 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 5877 99.98% 99.98% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1886 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2786 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5910 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5857 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6173 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5767 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6250 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6643 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7263 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7223 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 8271 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8725 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7065 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6628 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6527 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6281 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6129 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6179 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 401 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 430 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 376 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 293 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 265 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 238 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 238 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 204 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 241 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 193 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 256 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 229 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 186 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 214 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 208 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 196 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 167 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 159 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 135 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 153 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 134 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 132 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 206 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 171 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 113 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 234 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 180 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 151 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 78 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 163 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 57323 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 318.311882 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 186.988870 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 336.470779 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 20402 35.59% 35.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 14531 25.35% 60.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5716 9.97% 70.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3104 5.41% 76.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2370 4.13% 80.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1421 2.48% 82.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1241 2.16% 85.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 946 1.65% 86.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7592 13.24% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 57323 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5761 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 28.979865 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 590.542998 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 5760 99.98% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5878 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5878 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.330725 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.604611 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 13.460490 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5095 86.68% 86.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 41 0.70% 87.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 85 1.45% 88.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 37 0.63% 89.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 285 4.85% 94.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 59 1.00% 95.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 13 0.22% 95.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 14 0.24% 95.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 9 0.15% 95.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 4 0.07% 95.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 6 0.10% 96.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 8 0.14% 96.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 168 2.86% 99.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 3 0.05% 99.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 2 0.03% 99.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 6 0.10% 99.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 7 0.12% 99.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 1 0.02% 99.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 1 0.02% 99.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 2 0.03% 99.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 2 0.03% 99.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 5 0.09% 99.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.02% 99.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 11 0.19% 99.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 1 0.02% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 1 0.02% 99.81% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 5761 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5761 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.507898 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.546505 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 15.055833 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5040 87.48% 87.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 23 0.40% 87.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 68 1.18% 89.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 38 0.66% 89.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 294 5.10% 94.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 33 0.57% 95.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 2 0.03% 95.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 7 0.12% 95.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 6 0.10% 95.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 3 0.05% 95.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 2 0.03% 95.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 5 0.09% 95.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 158 2.74% 98.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 4 0.07% 98.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 6 0.10% 98.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 3 0.05% 98.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 10 0.17% 98.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 2 0.03% 99.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 2 0.03% 99.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 1 0.02% 99.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 2 0.03% 99.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 11 0.19% 99.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 2 0.03% 99.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 1 0.02% 99.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 3 0.05% 99.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 8 0.14% 99.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 7 0.12% 99.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 4 0.07% 99.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 4 0.07% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 1 0.02% 99.81% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::148-151 1 0.02% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 1 0.02% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 6 0.10% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 1 0.02% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::252-255 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5878 # Writes before turning the bus around for reads -system.physmem.totQLat 1493636250 # Total ticks spent queuing -system.physmem.totMemAccLat 4652936250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 842480000 # Total ticks spent in databus transfers -system.physmem.avgQLat 8864.52 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::156-159 2 0.03% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 3 0.05% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 2 0.03% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 1 0.02% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-195 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-203 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5761 # Writes before turning the bus around for reads +system.physmem.totQLat 4504540500 # Total ticks spent queuing +system.physmem.totMemAccLat 7635003000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 834790000 # Total ticks spent in databus transfers +system.physmem.avgQLat 26980.08 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27614.52 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 3.71 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.63 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 3.52 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.63 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 45730.08 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 3.68 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.60 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 3.48 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.60 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.05 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.41 # Average write queue length when enqueuing -system.physmem.readRowHits 138583 # Number of row buffer hits during reads -system.physmem.writeRowHits 90798 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.25 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.96 # Row buffer hit rate for writes -system.physmem.avgGap 9942055.41 # Average gap between requests -system.physmem.pageHitRate 79.64 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 226187640 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 123415875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 696064200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 389013840 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 189657789360 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 86978464290 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1665943648500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1944014583705 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.487777 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2771286006000 # Time in different power states -system.physmem_0.memoryStateTime::REF 96962060000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 35486192750 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 216964440 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 118383375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 618196800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 385372080 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 189657789360 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 85605070095 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1667148388500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1943750164650 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.396712 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2773305848750 # Time in different power states -system.physmem_1.memoryStateTime::REF 96962060000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 33468782750 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states +system.physmem.avgWrQLen 25.28 # Average write queue length when enqueuing +system.physmem.readRowHits 138094 # Number of row buffer hits during reads +system.physmem.writeRowHits 89686 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.71 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.90 # Row buffer hit rate for writes +system.physmem.avgGap 10047995.17 # Average gap between requests +system.physmem.pageHitRate 79.89 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 210115920 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 111679260 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 640479420 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 313440120 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 6609223920.000002 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 4735061820 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 414343200 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 13903412640 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 9310120320 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 682719565725 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 718969243965 # Total energy per rank (pJ) +system.physmem_0.averagePower 247.468348 # Core power per rank (mW) +system.physmem_0.totalIdleTime 2893307612500 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 778413000 # Time in different power states +system.physmem_0.memoryStateTime::REF 2810438000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 2839095824500 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 24245244750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 7877734000 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 30490128250 # Time in different power states +system.physmem_1.actEnergy 199177440 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 105861525 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 551600700 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 303282000 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 6621516720.000002 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 4536550200 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 409678080 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 13514783790 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 9490661760 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 682993594335 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 718728215280 # Total energy per rank (pJ) +system.physmem_1.averagePower 247.385386 # Core power per rank (mW) +system.physmem_1.totalIdleTime 2894278953000 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 777246000 # Time in different power states +system.physmem_1.memoryStateTime::REF 2816412000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 2839926040500 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 24715420500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 7425105000 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 29637558500 # Time in different power states +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory @@ -329,9 +344,9 @@ system.realview.nvmem.bw_inst_read::cpu.inst 7 system.realview.nvmem.bw_inst_read::total 7 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 7 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 7 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -339,7 +354,7 @@ system.cf0.dma_write_full_pages 540 # Nu system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -369,58 +384,58 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.walks 9520 # Table walker walks requested -system.cpu.dtb.walker.walksShort 9520 # Table walker walks initiated with short descriptors -system.cpu.dtb.walker.walksShortTerminationLevel::Level1 1252 # Level at which table walker walks with short descriptors terminate -system.cpu.dtb.walker.walksShortTerminationLevel::Level2 8268 # Level at which table walker walks with short descriptors terminate -system.cpu.dtb.walker.walkWaitTime::samples 9520 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0 9520 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 9520 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkCompletionTime::samples 7356 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 10060.290919 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 8514.979061 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 6541.334463 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::0-16383 6558 89.15% 89.15% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::16384-32767 793 10.78% 99.93% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.walks 9547 # Table walker walks requested +system.cpu.dtb.walker.walksShort 9547 # Table walker walks initiated with short descriptors +system.cpu.dtb.walker.walksShortTerminationLevel::Level1 1253 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walksShortTerminationLevel::Level2 8294 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walkWaitTime::samples 9547 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0 9547 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 9547 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 7383 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 9942.435324 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 8397.692517 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 6587.109188 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-16383 6605 89.46% 89.46% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::16384-32767 773 10.47% 99.93% # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walkCompletionTime::81920-98303 4 0.05% 99.99% # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walkCompletionTime::180224-196607 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::total 7356 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walksPending::samples 941563500 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::0 941563500 100.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::total 941563500 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 6151 83.62% 83.62% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::1M 1205 16.38% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 7356 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 9520 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkCompletionTime::total 7383 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walksPending::samples 1003066500 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::0 1003066500 100.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::total 1003066500 # Table walker pending requests distribution +system.cpu.dtb.walker.walkPageSizes::4K 6177 83.67% 83.67% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::1M 1206 16.33% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 7383 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 9547 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 9520 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7356 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 9547 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7383 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7356 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 16876 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7383 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 16930 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 24525489 # DTB read hits -system.cpu.dtb.read_misses 8109 # DTB read misses -system.cpu.dtb.write_hits 19608938 # DTB write hits -system.cpu.dtb.write_misses 1411 # DTB write misses +system.cpu.dtb.read_hits 24520121 # DTB read hits +system.cpu.dtb.read_misses 8133 # DTB read misses +system.cpu.dtb.write_hits 19605715 # DTB write hits +system.cpu.dtb.write_misses 1414 # DTB write misses system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 4199 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_entries 4209 # Number of entries that have been flushed from TLB system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 1636 # Number of TLB faults due to prefetch +system.cpu.dtb.prefetch_faults 1628 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 24533598 # DTB read accesses -system.cpu.dtb.write_accesses 19610349 # DTB write accesses +system.cpu.dtb.read_accesses 24528254 # DTB read accesses +system.cpu.dtb.write_accesses 19607129 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 44134427 # DTB hits -system.cpu.dtb.misses 9520 # DTB misses -system.cpu.dtb.accesses 44143947 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.hits 44125836 # DTB hits +system.cpu.dtb.misses 9547 # DTB misses +system.cpu.dtb.accesses 44135383 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -450,39 +465,39 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.walks 4762 # Table walker walks requested -system.cpu.itb.walker.walksShort 4762 # Table walker walks initiated with short descriptors -system.cpu.itb.walker.walksShortTerminationLevel::Level1 309 # Level at which table walker walks with short descriptors terminate +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.walks 4763 # Table walker walks requested +system.cpu.itb.walker.walksShort 4763 # Table walker walks initiated with short descriptors +system.cpu.itb.walker.walksShortTerminationLevel::Level1 310 # Level at which table walker walks with short descriptors terminate system.cpu.itb.walker.walksShortTerminationLevel::Level2 4453 # Level at which table walker walks with short descriptors terminate -system.cpu.itb.walker.walkWaitTime::samples 4762 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0 4762 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 4762 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkCompletionTime::samples 3107 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::mean 10273.897650 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::gmean 8288.299297 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::stdev 7346.561217 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::0-8191 1812 58.32% 58.32% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::8192-16383 745 23.98% 82.30% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::16384-24575 548 17.64% 99.94% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::81920-90111 1 0.03% 99.97% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::90112-98303 1 0.03% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::total 3107 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walksPending::samples 941232000 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::0 941232000 100.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::total 941232000 # Table walker pending requests distribution -system.cpu.itb.walker.walkPageSizes::4K 2798 90.05% 90.05% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::1M 309 9.95% 100.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::total 3107 # Table walker page sizes translated +system.cpu.itb.walker.walkWaitTime::samples 4763 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0 4763 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 4763 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 3108 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 10156.853282 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 8221.468352 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 7284.204444 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-8191 1821 58.59% 58.59% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::8192-16383 769 24.74% 83.33% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::16384-24575 516 16.60% 99.94% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::90112-98303 1 0.03% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::98304-106495 1 0.03% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::total 3108 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walksPending::samples 1002711000 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::0 1002711000 100.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::total 1002711000 # Table walker pending requests distribution +system.cpu.itb.walker.walkPageSizes::4K 2798 90.03% 90.03% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::1M 310 9.97% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 3108 # Table walker page sizes translated system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 4762 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 4762 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 4763 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 4763 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3107 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 3107 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 7869 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 115574516 # ITB inst hits -system.cpu.itb.inst_misses 4762 # ITB inst misses +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3108 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 3108 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 7871 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 115559307 # ITB inst hits +system.cpu.itb.inst_misses 4763 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -498,55 +513,55 @@ system.cpu.itb.domain_faults 0 # Nu system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 115579278 # ITB inst accesses -system.cpu.itb.hits 115574516 # DTB hits -system.cpu.itb.misses 4762 # DTB misses -system.cpu.itb.accesses 115579278 # DTB accesses -system.cpu.numPwrStateTransitions 6062 # Number of power state transitions -system.cpu.pwrStateClkGateDist::samples 3031 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::mean 888232478.174860 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::stdev 17469824950.226959 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::underflows 2968 97.92% 97.92% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::1000-5e+10 57 1.88% 99.80% # Distribution of time spent in the clock gated state +system.cpu.itb.inst_accesses 115564070 # ITB inst accesses +system.cpu.itb.hits 115559307 # DTB hits +system.cpu.itb.misses 4763 # DTB misses +system.cpu.itb.accesses 115564070 # DTB accesses +system.cpu.numPwrStateTransitions 6066 # Number of power state transitions +system.cpu.pwrStateClkGateDist::samples 3033 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::mean 887205638.526871 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::stdev 17463817933.974155 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::underflows 2968 97.86% 97.86% # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::1000-5e+10 59 1.95% 99.80% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 1 0.03% 99.84% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 1 0.03% 99.87% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 1 0.03% 99.90% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 3 0.10% 100.00% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::max_value 499964073052 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::total 3031 # Distribution of time spent in the clock gated state -system.cpu.pwrStateResidencyTicks::ON 211504149152 # Cumulative time (in ticks) in various power states -system.cpu.pwrStateResidencyTicks::CLK_GATED 2692232641348 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 5807473581 # number of cpu cycles simulated +system.cpu.pwrStateClkGateDist::max_value 499962880972 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::total 3033 # Distribution of time spent in the clock gated state +system.cpu.pwrStateResidencyTicks::ON 214403080848 # Cumulative time (in ticks) in various power states +system.cpu.pwrStateResidencyTicks::CLK_GATED 2690894701652 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 5810595565 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 3031 # number of quiesce instructions executed -system.cpu.committedInsts 112476413 # Number of instructions committed -system.cpu.committedOps 135613231 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 119916333 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 11161 # Number of float alu accesses -system.cpu.num_func_calls 9896179 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 15232917 # number of instructions that are conditional controls -system.cpu.num_int_insts 119916333 # number of integer instructions -system.cpu.num_fp_insts 11161 # number of float instructions -system.cpu.num_int_register_reads 218092554 # number of times the integer registers were read -system.cpu.num_int_register_writes 82663252 # number of times the integer registers were written -system.cpu.num_fp_register_reads 8449 # number of times the floating registers were read +system.cpu.kern.inst.quiesce 3033 # number of quiesce instructions executed +system.cpu.committedInsts 112461365 # Number of instructions committed +system.cpu.committedOps 135593151 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 119897812 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 11226 # Number of float alu accesses +system.cpu.num_func_calls 9894928 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 15231225 # number of instructions that are conditional controls +system.cpu.num_int_insts 119897812 # number of integer instructions +system.cpu.num_fp_insts 11226 # number of float instructions +system.cpu.num_int_register_reads 218061607 # number of times the integer registers were read +system.cpu.num_int_register_writes 82648736 # number of times the integer registers were written +system.cpu.num_fp_register_reads 8514 # number of times the floating registers were read system.cpu.num_fp_register_writes 2716 # number of times the floating registers were written -system.cpu.num_cc_register_reads 489835813 # number of times the CC registers were read -system.cpu.num_cc_register_writes 51902110 # number of times the CC registers were written -system.cpu.num_mem_refs 45414800 # number of memory refs -system.cpu.num_load_insts 24847736 # Number of load instructions -system.cpu.num_store_insts 20567064 # Number of store instructions -system.cpu.num_idle_cycles 5384465282.694146 # Number of idle cycles -system.cpu.num_busy_cycles 423008298.305854 # Number of busy cycles -system.cpu.not_idle_fraction 0.072839 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.927161 # Percentage of idle cycles -system.cpu.Branches 25923023 # Number of branches fetched +system.cpu.num_cc_register_reads 489758493 # number of times the CC registers were read +system.cpu.num_cc_register_writes 51897030 # number of times the CC registers were written +system.cpu.num_mem_refs 45406070 # number of memory refs +system.cpu.num_load_insts 24842315 # Number of load instructions +system.cpu.num_store_insts 20563755 # Number of store instructions +system.cpu.num_idle_cycles 5381789403.302147 # Number of idle cycles +system.cpu.num_busy_cycles 428806161.697852 # Number of busy cycles +system.cpu.not_idle_fraction 0.073797 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.926203 # Percentage of idle cycles +system.cpu.Branches 25920117 # Number of branches fetched system.cpu.op_class::No_OpClass 2337 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 93194210 67.17% 67.18% # Class of executed instruction -system.cpu.op_class::IntMult 114540 0.08% 67.26% # Class of executed instruction +system.cpu.op_class::IntAlu 93182494 67.18% 67.18% # Class of executed instruction +system.cpu.op_class::IntMult 114558 0.08% 67.26% # Class of executed instruction system.cpu.op_class::IntDiv 0 0.00% 67.26% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 67.26% # Class of executed instruction system.cpu.op_class::FloatCmp 0 0.00% 67.26% # Class of executed instruction @@ -570,502 +585,502 @@ system.cpu.op_class::SimdFloatAlu 0 0.00% 67.26% # Cl system.cpu.op_class::SimdFloatCmp 0 0.00% 67.26% # Class of executed instruction system.cpu.op_class::SimdFloatCvt 0 0.00% 67.26% # Class of executed instruction system.cpu.op_class::SimdFloatDiv 0 0.00% 67.26% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 8453 0.01% 67.26% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 67.26% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.26% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.26% # Class of executed instruction -system.cpu.op_class::MemRead 24847736 17.91% 85.18% # Class of executed instruction -system.cpu.op_class::MemWrite 20567064 14.82% 100.00% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 8431 0.01% 67.27% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 67.27% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.27% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.27% # Class of executed instruction +system.cpu.op_class::MemRead 24842315 17.91% 85.18% # Class of executed instruction +system.cpu.op_class::MemWrite 20563755 14.82% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 138734340 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 819770 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.827215 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 43243016 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 820282 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 52.717256 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 1013099500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.827215 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999663 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999663 # Average percentage of cache occupancy +system.cpu.op_class::total 138713890 # Class of executed instruction +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 821351 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.816254 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 43232645 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 821863 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 52.603226 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 1078145500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.816254 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999641 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999641 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 366 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 86 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 362 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 94 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 177141047 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 177141047 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 23117557 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 23117557 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18826251 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18826251 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 392764 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 392764 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 443415 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 443415 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 460277 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 460277 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 41943808 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 41943808 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 42336572 # number of overall hits -system.cpu.dcache.overall_hits::total 42336572 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 400061 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 400061 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 298752 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 298752 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 118460 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 118460 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 22645 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 22645 # number of LoadLockedReq misses +system.cpu.dcache.tags.tag_accesses 177108261 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 177108261 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 23111024 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 23111024 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 18823159 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 18823159 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 392414 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 392414 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 443071 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 443071 # number of LoadLockedReq hits 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demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 20802666000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 20802666000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 20802666000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 23512476 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 23512476 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 19121896 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 19121896 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 511126 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 511126 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 465932 # number of LoadLockedReq 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accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14917.056399 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14917.056399 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42163.372965 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 42163.372965 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12371.362332 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12371.362332 # average LoadLockedReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.016423 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.016423 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.018980 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.018980 # miss rate for overall accesses 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-system.cpu.dcache.overall_avg_miss_latency::cpu.data 22714.716502 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 22714.716502 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 29710.072566 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 29710.072566 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 25403.151297 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 25403.151297 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 76 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 19 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs 4 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 683946 # number of writebacks -system.cpu.dcache.writebacks::total 683946 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 680 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 680 # number of ReadReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14146 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 14146 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 680 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 680 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 680 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 680 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 399381 # number of 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-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 19383034500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 19383034500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6281205500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6281205500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6281205500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 6281205500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016982 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016982 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015621 # mshr miss rate for WriteReq accesses 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ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13910.005734 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 41163.372965 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 41163.372965 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13141.077395 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13141.077395 # average SoftPFReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12808.389222 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12808.389222 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016407 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.016407 # mshr miss rate for demand accesses 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-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 106956.008310 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 106956.008310 # average overall mshr uncacheable latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 1698000 # number of replacements -system.cpu.icache.tags.tagsinuse 510.728664 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 113875998 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1698512 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 67.044565 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 25832791500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.728664 # Average occupied blocks per requestor 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# Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 195 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 264 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 211 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 246 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 9 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 117273034 # Number of tag accesses -system.cpu.icache.tags.data_accesses 117273034 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 113875998 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 113875998 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 113875998 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 113875998 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 113875998 # number of overall hits -system.cpu.icache.overall_hits::total 113875998 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1698518 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1698518 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1698518 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1698518 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1698518 # number of overall misses -system.cpu.icache.overall_misses::total 1698518 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 23414403500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 23414403500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 23414403500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 23414403500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 23414403500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 23414403500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 115574516 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 115574516 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 115574516 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 115574516 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 115574516 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 115574516 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014696 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.014696 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.014696 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.014696 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.014696 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.014696 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13785.195977 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13785.195977 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13785.195977 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13785.195977 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13785.195977 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13785.195977 # average overall miss latency +system.cpu.icache.tags.tag_accesses 117259828 # Number of tag accesses +system.cpu.icache.tags.data_accesses 117259828 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 113858786 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 113858786 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 113858786 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 113858786 # number of demand (read+write) hits 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demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 24021238000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 24021238000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 115559307 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 115559307 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 115559307 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 115559307 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 115559307 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 115559307 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014716 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.014716 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.014716 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.014716 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.014716 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.014716 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14125.810854 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 14125.810854 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14125.810854 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14125.810854 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14125.810854 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14125.810854 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 1698000 # number of writebacks -system.cpu.icache.writebacks::total 1698000 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1698518 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1698518 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1698518 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1698518 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1698518 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1698518 # number of overall MSHR misses +system.cpu.icache.writebacks::writebacks 1700003 # number of writebacks +system.cpu.icache.writebacks::total 1700003 # number of writebacks +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1700521 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1700521 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1700521 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1700521 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1700521 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1700521 # number of overall MSHR misses system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 9022 # number of ReadReq MSHR uncacheable system.cpu.icache.ReadReq_mshr_uncacheable::total 9022 # number of ReadReq MSHR uncacheable system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 9022 # number of overall MSHR uncacheable misses system.cpu.icache.overall_mshr_uncacheable_misses::total 9022 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 21715885500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 21715885500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 21715885500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 21715885500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 21715885500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 21715885500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 687287000 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 687287000 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 687287000 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 687287000 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014696 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014696 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014696 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.014696 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014696 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.014696 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12785.195977 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12785.195977 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12785.195977 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 12785.195977 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12785.195977 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 12785.195977 # average overall mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 76179.006872 # average ReadReq mshr uncacheable latency -system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 76179.006872 # average ReadReq mshr uncacheable latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 76179.006872 # average overall mshr uncacheable latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 76179.006872 # average overall mshr uncacheable latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 89464 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65017.694965 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 4847707 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 154877 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 31.300367 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 144041988000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 3.877834 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.040783 # Average occupied blocks per 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-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.436872 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.010607 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.010607 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.431842 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.431842 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.010555 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.010555 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.023076 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.023076 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001562 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000729 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010607 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.172391 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.063103 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001562 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000729 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010607 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.172391 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.063103 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 93687.500000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 74000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 89750 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19050 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19050 # average UpgradeReq mshr miss latency +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001401 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000749 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010555 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.170253 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.062404 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001401 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000749 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010555 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.170253 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.062404 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 154928.571429 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 80000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 138277.777778 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19236.842105 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19236.842105 # average UpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 70500 # average SCUpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 70500 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67844.557863 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67844.557863 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 71264.459369 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 71264.459369 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73668.237044 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73668.237044 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 93687.500000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 74000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71264.459369 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68342.816129 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68674.291269 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 93687.500000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 74000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71264.459369 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68342.816129 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68674.291269 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 63679.006872 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189217.692209 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 161015.251494 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 63679.006872 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 100326.263899 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 95446.021343 # average overall mshr uncacheable latency -system.cpu.toL2Bus.snoop_filter.tot_requests 5058492 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2539687 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 38280 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 250 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 250 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 82462.928039 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 82462.928039 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 103832.265433 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 103832.265433 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 115003.419296 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 115003.419296 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 154928.571429 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 80000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 103832.265433 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 85285.387589 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 87396.760954 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 154928.571429 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 80000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 103832.265433 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 85285.387589 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 87396.760954 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 70098.426070 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189334.494829 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 162547.945717 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 70098.426070 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 100388.194527 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 96354.566119 # average overall mshr uncacheable latency +system.cpu.toL2Bus.snoop_filter.tot_requests 5065968 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2543576 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 39287 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 219 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 219 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadReq 67163 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2290209 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadReq 67217 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2293895 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 27589 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 27589 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 766799 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 1698000 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 142435 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2750 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 767045 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 1700003 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 142341 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2814 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2752 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 296002 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 296002 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1698518 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 524530 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateReq 4455 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5113056 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2583569 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 11960 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 22910 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7731495 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 217411704 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96469597 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 10980 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 20488 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 313912769 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 113519 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 5394688 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 2710473 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.021286 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.144336 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::UpgradeResp 2816 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 295923 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 295923 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1700521 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 526163 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateReq 4351 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5119073 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2588406 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 11887 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 22839 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7742205 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 217668600 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96672157 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 10684 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 19992 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 314371433 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 112178 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 5305776 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 2712615 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.021718 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.145761 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 2652778 97.87% 97.87% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 57695 2.13% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 2653703 97.83% 97.83% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 58912 2.17% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 2710473 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4962792000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 2712615 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4970051500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 389377 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 347876 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 2556799000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 2559803500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1276777495 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1279174000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 9215000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 9216000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 17788000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 17841000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states -system.iobus.trans_dist::ReadReq 30183 # Transaction distribution -system.iobus.trans_dist::ReadResp 30183 # Transaction distribution +system.iobus.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states +system.iobus.trans_dist::ReadReq 30159 # Transaction distribution +system.iobus.trans_dist::ReadResp 30159 # Transaction distribution system.iobus.trans_dist::WriteReq 59014 # Transaction distribution system.iobus.trans_dist::WriteResp 59014 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54170 # Packet count per connected master and slave (bytes) @@ -1237,9 +1252,9 @@ system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 105478 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72916 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 72916 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 178394 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72868 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 72868 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 178346 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67887 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes) @@ -1260,22 +1275,22 @@ system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 159125 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321104 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 2321104 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2480229 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 46334000 # Layer occupancy (ticks) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2320912 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 2320912 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2480037 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 46338000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 97000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 338500 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 338000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer3.occupancy 29500 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 15500 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 95000 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 94500 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer8.occupancy 642000 # Layer occupancy (ticks) +system.iobus.reqLayer8.occupancy 642500 # Layer occupancy (ticks) system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer10.occupancy 21000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) @@ -1297,56 +1312,56 @@ system.iobus.reqLayer20.occupancy 9000 # La system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer21.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 6273000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 6292000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer24.occupancy 36469500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 187671849 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 187581870 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36740000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36692000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states -system.iocache.tags.replacements 36424 # number of replacements -system.iocache.tags.tagsinuse 1.078594 # Cycle average of tags in use +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states +system.iocache.tags.replacements 36400 # number of replacements +system.iocache.tags.tagsinuse 1.079755 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 36440 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 36416 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 309373303000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 1.078594 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.067412 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.067412 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 310620847000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 1.079755 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.067485 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.067485 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 328122 # Number of tag accesses -system.iocache.tags.data_accesses 328122 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states -system.iocache.ReadReq_misses::realview.ide 234 # number of ReadReq misses -system.iocache.ReadReq_misses::total 234 # number of ReadReq misses +system.iocache.tags.tag_accesses 327906 # Number of tag accesses +system.iocache.tags.data_accesses 327906 # Number of data accesses +system.iocache.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states +system.iocache.ReadReq_misses::realview.ide 210 # number of ReadReq misses +system.iocache.ReadReq_misses::total 210 # number of ReadReq misses system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses -system.iocache.demand_misses::realview.ide 36458 # number of demand (read+write) misses -system.iocache.demand_misses::total 36458 # number of demand (read+write) misses -system.iocache.overall_misses::realview.ide 36458 # number of overall misses -system.iocache.overall_misses::total 36458 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 28897377 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 28897377 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 4278807472 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4278807472 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 4307704849 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 4307704849 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 4307704849 # number of overall miss cycles -system.iocache.overall_miss_latency::total 4307704849 # number of overall miss cycles -system.iocache.ReadReq_accesses::realview.ide 234 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 234 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::realview.ide 36434 # number of demand (read+write) misses +system.iocache.demand_misses::total 36434 # number of demand (read+write) misses +system.iocache.overall_misses::realview.ide 36434 # number of overall misses +system.iocache.overall_misses::total 36434 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ide 34066376 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 34066376 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 4367688494 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4367688494 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 4401754870 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 4401754870 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 4401754870 # number of overall miss cycles +system.iocache.overall_miss_latency::total 4401754870 # number of overall miss cycles +system.iocache.ReadReq_accesses::realview.ide 210 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 210 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::realview.ide 36458 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 36458 # number of demand (read+write) accesses -system.iocache.overall_accesses::realview.ide 36458 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 36458 # number of overall (read+write) accesses +system.iocache.demand_accesses::realview.ide 36434 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 36434 # number of demand (read+write) accesses +system.iocache.overall_accesses::realview.ide 36434 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 36434 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses @@ -1355,14 +1370,14 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 123493.064103 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 123493.064103 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118120.789311 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 118120.789311 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 118155.270421 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 118155.270421 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 118155.270421 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 118155.270421 # average overall miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 162220.838095 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 162220.838095 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120574.439432 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 120574.439432 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 120814.482901 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 120814.482901 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 120814.482901 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 120814.482901 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1371,22 +1386,22 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 36190 # number of writebacks system.iocache.writebacks::total 36190 # number of writebacks -system.iocache.ReadReq_mshr_misses::realview.ide 234 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 234 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 210 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 210 # number of ReadReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::realview.ide 36458 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 36458 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::realview.ide 36458 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 36458 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 17197377 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 17197377 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2465502723 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2465502723 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 2482700100 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 2482700100 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 2482700100 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 2482700100 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::realview.ide 36434 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 36434 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::realview.ide 36434 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 36434 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ide 23566376 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 23566376 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2554457612 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2554457612 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 2578023988 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 2578023988 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 2578023988 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 2578023988 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1395,90 +1410,90 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 73493.064103 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 73493.064103 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68062.685595 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68062.685595 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 68097.539635 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 68097.539635 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 68097.539635 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 68097.539635 # average overall mshr miss latency -system.membus.snoop_filter.tot_requests 321817 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 130498 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 482 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 112220.838095 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 112220.838095 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70518.374890 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70518.374890 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 70758.741505 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 70758.741505 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 70758.741505 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 70758.741505 # average overall mshr miss latency +system.membus.snoop_filter.tot_requests 318841 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 128997 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 458 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 40160 # Transaction distribution -system.membus.trans_dist::ReadResp 70519 # Transaction distribution +system.membus.trans_dist::ReadResp 70464 # Transaction distribution system.membus.trans_dist::WriteReq 27589 # Transaction distribution system.membus.trans_dist::WriteResp 27589 # Transaction distribution -system.membus.trans_dist::WritebackDirty 119043 # Transaction distribution -system.membus.trans_dist::CleanEvict 6845 # Transaction distribution +system.membus.trans_dist::WritebackDirty 117674 # Transaction distribution +system.membus.trans_dist::CleanEvict 6761 # Transaction distribution system.membus.trans_dist::UpgradeReq 128 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution system.membus.trans_dist::UpgradeResp 2 # Transaction distribution -system.membus.trans_dist::ReadExReq 129207 # Transaction distribution -system.membus.trans_dist::ReadExResp 129207 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 30359 # Transaction distribution +system.membus.trans_dist::ReadExReq 127683 # Transaction distribution +system.membus.trans_dist::ReadExResp 127683 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 30304 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2104 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 435887 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 543479 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72897 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 72897 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 616376 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 431348 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 538940 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72849 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 72849 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 611789 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4208 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15537980 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 15701333 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15350844 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 15514197 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 18018453 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 498 # Total snoops (count) -system.membus.snoopTraffic 31744 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 263669 # Request fanout histogram -system.membus.snoop_fanout::mean 0.018793 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.135792 # Request fanout histogram +system.membus.pkt_size::total 17831317 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 474 # Total snoops (count) +system.membus.snoopTraffic 30208 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 262090 # Request fanout histogram +system.membus.snoop_fanout::mean 0.018417 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.134455 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 258714 98.12% 98.12% # Request fanout histogram -system.membus.snoop_fanout::1 4955 1.88% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 257263 98.16% 98.16% # Request fanout histogram +system.membus.snoop_fanout::1 4827 1.84% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 263669 # Request fanout histogram -system.membus.reqLayer0.occupancy 90449000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 262090 # Request fanout histogram +system.membus.reqLayer0.occupancy 90471500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 7500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1734500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1726500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 828323280 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 819732726 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 954014500 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 945419750 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 1219623 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 1085624 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -1510,28 +1525,28 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2903736790500 # Cumulative time (in ticks) in various power states +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2905297782500 # Cumulative time (in ticks) in various power states ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/config.ini index 6320b231e..fcd6df11a 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/config.ini @@ -149,7 +149,7 @@ useIndirect=true [system.cpu.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -583,7 +583,7 @@ opClass=InstPrefetch [system.cpu.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -643,7 +643,7 @@ size=48 [system.cpu.l2cache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -760,6 +760,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -771,7 +772,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -779,29 +780,36 @@ width=16 master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -821,6 +829,7 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 @@ -830,7 +839,7 @@ p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 page_policy=open_adaptive power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 @@ -852,9 +861,9 @@ tRTW=2500 tWR=15000 tWTR=7500 tXAW=30000 -tXP=0 +tXP=6000 tXPDLL=0 -tXS=0 +tXS=270000 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 diff --git a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/simout b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/simout index 70f465dc7..321da6ba3 100755 --- a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/simout +++ b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/simout @@ -3,13 +3,13 @@ Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/minor- gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 19 2016 12:23:51 -gem5 started Jul 19 2016 12:24:27 -gem5 executing on e108600-lin, pid 39611 +gem5 compiled Oct 11 2016 00:00:58 +gem5 started Oct 13 2016 20:19:43 +gem5 executing on e108600-lin, pid 28041 command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/minor-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/alpha/linux/minor-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 37822000 because target called exit() +Exiting @ tick 41083000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt index 5987fdc63..6227dc2b6 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000038 # Number of seconds simulated -sim_ticks 38282000 # Number of ticks simulated -final_tick 38282000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000041 # Number of seconds simulated +sim_ticks 41083000 # Number of ticks simulated +final_tick 41083000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 159466 # Simulator instruction rate (inst/s) -host_op_rate 159415 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 951356890 # Simulator tick rate (ticks/s) -host_mem_usage 253388 # Number of bytes of host memory used +host_inst_rate 172605 # Simulator instruction rate (inst/s) +host_op_rate 172547 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1105034404 # Simulator tick rate (ticks/s) +host_mem_usage 251288 # Number of bytes of host memory used host_seconds 0.04 # Real time elapsed on the host sim_insts 6413 # Number of instructions simulated sim_ops 6413 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 38282000 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 41083000 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 23232 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 10816 # Number of bytes read from this memory system.physmem.bytes_read::total 34048 # Number of bytes read from this memory @@ -22,14 +22,14 @@ system.physmem.bytes_inst_read::total 23232 # Nu system.physmem.num_reads::cpu.inst 363 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 169 # Number of read requests responded to by this memory system.physmem.num_reads::total 532 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 606864845 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 282534873 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 889399718 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 606864845 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 606864845 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 606864845 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 282534873 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 889399718 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 565489375 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 263271913 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 828761288 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 565489375 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 565489375 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 565489375 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 263271913 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 828761288 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 532 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 532 # Number of DRAM read bursts, including those serviced by the write queue @@ -76,7 +76,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 38177000 # Total gap between requests +system.physmem.totGap 40972000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -91,9 +91,9 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 446 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 83 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 443 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 85 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -187,83 +187,93 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 83 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 377.831325 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 247.256857 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 329.629090 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 18 21.69% 21.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 20 24.10% 45.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 11 13.25% 59.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 11 13.25% 72.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3 3.61% 75.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 4 4.82% 80.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 3 3.61% 84.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 4 4.82% 89.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 9 10.84% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 83 # Bytes accessed per row activation -system.physmem.totQLat 3252000 # Total ticks spent queuing -system.physmem.totMemAccLat 13227000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 91 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 363.604396 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 235.588514 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 321.826485 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 22 24.18% 24.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 22 24.18% 48.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 13 14.29% 62.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 8 8.79% 71.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 5 5.49% 76.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 4 4.40% 81.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 3 3.30% 84.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 8 8.79% 93.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 6 6.59% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 91 # Bytes accessed per row activation +system.physmem.totQLat 6580250 # Total ticks spent queuing +system.physmem.totMemAccLat 16555250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2660000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6112.78 # Average queueing delay per DRAM burst +system.physmem.avgQLat 12368.89 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 24862.78 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 889.40 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 31118.89 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 828.76 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 889.40 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 828.76 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 6.95 # Data bus utilization in percentage -system.physmem.busUtilRead 6.95 # Data bus utilization in percentage for reads +system.physmem.busUtil 6.47 # Data bus utilization in percentage +system.physmem.busUtilRead 6.47 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.18 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 437 # Number of row buffer hits during reads +system.physmem.readRowHits 436 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.14 # Row buffer hit rate for reads +system.physmem.readRowHitRate 81.95 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 71761.28 # Average gap between requests -system.physmem.pageHitRate 82.14 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 234360 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 127875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 2020200 # Energy for read commands per rank (pJ) +system.physmem.avgGap 77015.04 # Average gap between requests +system.physmem.pageHitRate 81.95 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 264180 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 136620 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1956360 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 2034240 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 21270690 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 184500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 25871865 # Total energy per rank (pJ) -system.physmem_0.averagePower 823.813565 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 196750 # Time in different power states -system.physmem_0.memoryStateTime::REF 1040000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 30182000 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 347760 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 189750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1505400 # Energy for read commands per rank (pJ) +system.physmem_0.refreshEnergy 3073200.000000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 3932430 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 68640 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 13617300 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 928800 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 23977530 # Total energy per rank (pJ) +system.physmem_0.averagePower 583.625643 # Core power per rank (mW) +system.physmem_0.totalIdleTime 32009500 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 39500 # Time in different power states +system.physmem_0.memoryStateTime::REF 1300000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 0 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 2418500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 7463000 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 29862000 # Time in different power states +system.physmem_1.actEnergy 421260 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 208725 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1842120 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 2034240 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 20078820 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1230000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 25385970 # Total energy per rank (pJ) -system.physmem_1.averagePower 808.341665 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2146500 # Time in different power states -system.physmem_1.memoryStateTime::REF 1040000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 28481000 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 38282000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 2005 # Number of BP lookups -system.cpu.branchPred.condPredicted 1239 # Number of conditional branches predicted +system.physmem_1.refreshEnergy 3073200.000000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 4022490 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 174720 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 14292750 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 178080 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 24213345 # Total energy per rank (pJ) +system.physmem_1.averagePower 589.365503 # Core power per rank (mW) +system.physmem_1.totalIdleTime 31744250 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 288500 # Time in different power states +system.physmem_1.memoryStateTime::REF 1300000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 0 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 464250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 7679500 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 31350750 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 41083000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 2003 # Number of BP lookups +system.cpu.branchPred.condPredicted 1238 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 379 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 1607 # Number of BTB lookups +system.cpu.branchPred.BTBLookups 1605 # Number of BTB lookups system.cpu.branchPred.BTBHits 377 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 23.459863 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 23.489097 # BTB Hit Percentage system.cpu.branchPred.usedRAS 235 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 14 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 336 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectLookups 335 # Number of indirect predictor lookups. system.cpu.branchPred.indirectHits 13 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 323 # Number of indirect misses. +system.cpu.branchPred.indirectMisses 322 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 113 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits @@ -299,16 +309,16 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 38282000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 76564 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 41083000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 82166 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 6413 # Number of instructions committed system.cpu.committedOps 6413 # Number of ops (including micro ops) committed system.cpu.discardedOps 1095 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 11.938874 # CPI: cycles per instruction -system.cpu.ipc 0.083760 # IPC: instructions per cycle +system.cpu.cpi 12.812412 # CPI: cycles per instruction +system.cpu.ipc 0.078049 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 19 0.30% 0.30% # Class of committed instruction system.cpu.op_class_0::IntAlu 4331 67.53% 67.83% # Class of committed instruction system.cpu.op_class_0::IntMult 1 0.02% 67.85% # Class of committed instruction @@ -344,25 +354,25 @@ system.cpu.op_class_0::MemWrite 868 13.54% 100.00% # Cl system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 6413 # Class of committed instruction -system.cpu.tickCycles 12651 # Number of cycles that the object actually ticked -system.cpu.idleCycles 63913 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 38282000 # Cumulative time (in ticks) in various power states +system.cpu.tickCycles 12644 # Number of cycles that the object actually ticked +system.cpu.idleCycles 69522 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 41083000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 103.736314 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 103.984752 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1990 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 169 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 11.775148 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 103.736314 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.025326 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.025326 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 103.984752 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.025387 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.025387 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 169 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 147 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 151 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.041260 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 4591 # Number of tag accesses system.cpu.dcache.tags.data_accesses 4591 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 38282000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 41083000 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 1250 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1250 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 740 # number of WriteReq hits @@ -379,14 +389,14 @@ system.cpu.dcache.demand_misses::cpu.data 221 # n system.cpu.dcache.demand_misses::total 221 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 221 # number of overall misses system.cpu.dcache.overall_misses::total 221 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 7713000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 7713000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 9281000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 9281000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 16994000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 16994000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 16994000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 16994000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 8545500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 8545500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 10429000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 10429000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 18974500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 18974500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 18974500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 18974500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1346 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1346 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) @@ -403,14 +413,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.099955 system.cpu.dcache.demand_miss_rate::total 0.099955 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.099955 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.099955 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 80343.750000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 80343.750000 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 74248 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 74248 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 76895.927602 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 76895.927602 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 76895.927602 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 76895.927602 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 89015.625000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 89015.625000 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 83432 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 83432 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 85857.466063 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 85857.466063 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 85857.466063 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 85857.466063 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -431,14 +441,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 169 system.cpu.dcache.demand_mshr_misses::total 169 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 169 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 169 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7617000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 7617000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5452500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5452500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13069500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 13069500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13069500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 13069500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8449500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 8449500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6089500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 6089500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14539000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 14539000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14539000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 14539000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.071322 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.071322 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses @@ -447,31 +457,31 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.076436 system.cpu.dcache.demand_mshr_miss_rate::total 0.076436 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076436 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.076436 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 79343.750000 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 79343.750000 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74691.780822 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74691.780822 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77334.319527 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 77334.319527 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77334.319527 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 77334.319527 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 38282000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 88015.625000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 88015.625000 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 83417.808219 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 83417.808219 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 86029.585799 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 86029.585799 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 86029.585799 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 86029.585799 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 41083000 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 174.445567 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 175.153182 # Cycle average of tags in use system.cpu.icache.tags.total_refs 2322 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 364 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 6.379121 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 174.445567 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.085178 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.085178 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 175.153182 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.085524 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.085524 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 364 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 260 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 93 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 271 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.177734 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 5736 # Number of tag accesses system.cpu.icache.tags.data_accesses 5736 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 38282000 # Cumulative time (in ticks) in various power states +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 41083000 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 2322 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 2322 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 2322 # number of demand (read+write) hits @@ -484,12 +494,12 @@ system.cpu.icache.demand_misses::cpu.inst 364 # n system.cpu.icache.demand_misses::total 364 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 364 # number of overall misses system.cpu.icache.overall_misses::total 364 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 28460500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 28460500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 28460500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 28460500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 28460500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 28460500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 30317500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 30317500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 30317500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 30317500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 30317500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 30317500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 2686 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 2686 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 2686 # number of demand (read+write) accesses @@ -502,12 +512,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.135517 system.cpu.icache.demand_miss_rate::total 0.135517 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.135517 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.135517 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 78188.186813 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 78188.186813 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 78188.186813 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 78188.186813 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 78188.186813 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 78188.186813 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 83289.835165 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 83289.835165 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 83289.835165 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 83289.835165 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 83289.835165 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 83289.835165 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -520,43 +530,43 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 364 system.cpu.icache.demand_mshr_misses::total 364 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 364 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 364 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 28096500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 28096500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 28096500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 28096500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 28096500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 28096500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 29953500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 29953500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 29953500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 29953500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 29953500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 29953500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.135517 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.135517 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.135517 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.135517 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.135517 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.135517 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 77188.186813 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 77188.186813 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 77188.186813 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 77188.186813 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 77188.186813 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 77188.186813 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 38282000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 82289.835165 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 82289.835165 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 82289.835165 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 82289.835165 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 82289.835165 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 82289.835165 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 41083000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 278.242026 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 279.180738 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 532 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.001880 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 174.459359 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 103.782667 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005324 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.003167 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.008491 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 175.152793 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 104.027945 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005345 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.003175 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.008520 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 532 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 407 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 110 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 422 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.016235 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 4796 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 4796 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 38282000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 41083000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1 # number of ReadCleanReq hits system.cpu.l2cache.ReadCleanReq_hits::total 1 # number of ReadCleanReq hits system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits @@ -575,18 +585,18 @@ system.cpu.l2cache.demand_misses::total 532 # nu system.cpu.l2cache.overall_misses::cpu.inst 363 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 169 # number of overall misses system.cpu.l2cache.overall_misses::total 532 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5343000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5343000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 27539000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 27539000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 7471500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 7471500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 27539000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 12814500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 40353500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 27539000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 12814500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 40353500 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5980000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5980000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 29396000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 29396000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 8304000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 8304000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 29396000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 14284000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 43680000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 29396000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 14284000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 43680000 # number of overall miss cycles system.cpu.l2cache.ReadExReq_accesses::cpu.data 73 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 364 # number of ReadCleanReq accesses(hits+misses) @@ -611,18 +621,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.998124 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.997253 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.998124 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73191.780822 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73191.780822 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75865.013774 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75865.013774 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 77828.125000 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 77828.125000 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75865.013774 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75825.443787 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 75852.443609 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75865.013774 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75825.443787 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 75852.443609 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81917.808219 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81917.808219 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 80980.716253 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 80980.716253 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 86500 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 86500 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80980.716253 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 84520.710059 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 82105.263158 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80980.716253 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 84520.710059 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 82105.263158 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -641,18 +651,18 @@ system.cpu.l2cache.demand_mshr_misses::total 532 system.cpu.l2cache.overall_mshr_misses::cpu.inst 363 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 169 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 532 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4613000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4613000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 23909000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 23909000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6511500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 6511500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 23909000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11124500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 35033500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 23909000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11124500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 35033500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5250000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5250000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 25766000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 25766000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7344000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7344000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 25766000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 12594000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 38360000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 25766000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12594000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 38360000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.997253 # mshr miss rate for ReadCleanReq accesses @@ -665,25 +675,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.998124 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.997253 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.998124 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63191.780822 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63191.780822 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65865.013774 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65865.013774 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 67828.125000 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 67828.125000 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65865.013774 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65825.443787 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65852.443609 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65865.013774 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65825.443787 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65852.443609 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71917.808219 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71917.808219 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70980.716253 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70980.716253 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70980.716253 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 74520.710059 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72105.263158 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70980.716253 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 74520.710059 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72105.263158 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 533 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 38282000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 41083000 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 460 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 73 # Transaction distribution @@ -709,18 +719,18 @@ system.cpu.toL2Bus.snoop_fanout::min_value 0 # system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 533 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 266500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) +system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 546000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 1.4 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.utilization 1.3 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 253500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.utilization 0.6 # Layer utilization (%) system.membus.snoop_filter.tot_requests 532 # Total number of requests made to the snoop filter. system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 38282000 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 41083000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 459 # Transaction distribution system.membus.trans_dist::ReadExReq 73 # Transaction distribution system.membus.trans_dist::ReadExResp 73 # Transaction distribution @@ -741,9 +751,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 532 # Request fanout histogram -system.membus.reqLayer0.occupancy 608000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.6 # Layer utilization (%) -system.membus.respLayer1.occupancy 2826500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 7.4 # Layer utilization (%) +system.membus.reqLayer0.occupancy 607500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.5 # Layer utilization (%) +system.membus.respLayer1.occupancy 2825000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 6.9 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini index 81c1646b5..dc66b2c5c 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini @@ -173,7 +173,7 @@ useIndirect=true [system.cpu.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -531,7 +531,7 @@ pipelined=false [system.cpu.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -591,7 +591,7 @@ size=48 [system.cpu.l2cache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -708,6 +708,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -719,7 +720,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -727,29 +728,36 @@ width=16 master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -769,6 +777,7 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 @@ -778,7 +787,7 @@ p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 page_policy=open_adaptive power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 @@ -800,9 +809,9 @@ tRTW=2500 tWR=15000 tWTR=7500 tXAW=30000 -tXP=0 +tXP=6000 tXPDLL=0 -tXS=0 +tXS=270000 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout index b4b146baf..27b942df1 100755 --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout @@ -3,13 +3,13 @@ Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-tim gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 19 2016 12:23:51 -gem5 started Jul 19 2016 12:24:27 -gem5 executing on e108600-lin, pid 39605 +gem5 compiled Oct 11 2016 00:00:58 +gem5 started Oct 13 2016 20:19:49 +gem5 executing on e108600-lin, pid 28099 command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/alpha/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 22019000 because target called exit() +Exiting @ tick 23776000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt index 1341b2242..518b46438 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000022 # Number of seconds simulated -sim_ticks 22248000 # Number of ticks simulated -final_tick 22248000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000024 # Number of seconds simulated +sim_ticks 23776000 # Number of ticks simulated +final_tick 23776000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 114507 # Simulator instruction rate (inst/s) -host_op_rate 114481 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 398824007 # Simulator tick rate (ticks/s) -host_mem_usage 254412 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host +host_inst_rate 93889 # Simulator instruction rate (inst/s) +host_op_rate 93856 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 349385939 # Simulator tick rate (ticks/s) +host_mem_usage 252568 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host sim_insts 6385 # Number of instructions simulated sim_ops 6385 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 22248000 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 23776000 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 19968 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 11072 # Number of bytes read from this memory system.physmem.bytes_read::total 31040 # Number of bytes read from this memory @@ -22,14 +22,14 @@ system.physmem.bytes_inst_read::total 19968 # Nu system.physmem.num_reads::cpu.inst 312 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 173 # Number of read requests responded to by this memory system.physmem.num_reads::total 485 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 897518878 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 497662711 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1395181589 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 897518878 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 897518878 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 897518878 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 497662711 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1395181589 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 839838493 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 465679677 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1305518170 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 839838493 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 839838493 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 839838493 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 465679677 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1305518170 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 485 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 485 # Number of DRAM read bursts, including those serviced by the write queue @@ -76,7 +76,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 22109000 # Total gap between requests +system.physmem.totGap 23381000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -91,11 +91,11 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 272 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 135 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 55 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 15 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 260 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 141 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 52 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 21 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 11 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -187,104 +187,115 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 76 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 352.842105 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 230.159600 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 321.021248 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 18 23.68% 23.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 19 25.00% 48.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 9 11.84% 60.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 11 14.47% 75.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 6 7.89% 82.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1 1.32% 84.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 2 2.63% 86.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 10 13.16% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 76 # Bytes accessed per row activation -system.physmem.totQLat 4498250 # Total ticks spent queuing -system.physmem.totMemAccLat 13592000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 89 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 348.044944 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 230.274346 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 313.082327 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 21 23.60% 23.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 22 24.72% 48.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 15 16.85% 65.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 9 10.11% 75.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 6 6.74% 82.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 3 3.37% 85.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 2 2.25% 87.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1 1.12% 88.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 10 11.24% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 89 # Bytes accessed per row activation +system.physmem.totQLat 8009750 # Total ticks spent queuing +system.physmem.totMemAccLat 17103500 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2425000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9274.74 # Average queueing delay per DRAM burst +system.physmem.avgQLat 16514.95 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28024.74 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1395.18 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 35264.95 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1305.52 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1395.18 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1305.52 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 10.90 # Data bus utilization in percentage -system.physmem.busUtilRead 10.90 # Data bus utilization in percentage for reads +system.physmem.busUtil 10.20 # Data bus utilization in percentage +system.physmem.busUtilRead 10.20 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.73 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.82 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 394 # Number of row buffer hits during reads +system.physmem.readRowHits 395 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.24 # Row buffer hit rate for reads +system.physmem.readRowHitRate 81.44 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 45585.57 # Average gap between requests -system.physmem.pageHitRate 81.24 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 196560 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 107250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1645800 # Energy for read commands per rank (pJ) +system.physmem.avgGap 48208.25 # Average gap between requests +system.physmem.pageHitRate 81.44 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 242760 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 125235 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1763580 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 10785825 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 38250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 13790805 # Total energy per rank (pJ) -system.physmem_0.averagePower 871.044055 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 22500 # Time in different power states -system.physmem_0.memoryStateTime::REF 520000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 15303750 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 294840 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 160875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1255800 # Energy for read commands per rank (pJ) +system.physmem_0.refreshEnergy 1843920.000000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 3005040 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 47520 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 7623180 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 132480 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 14783715 # Total energy per rank (pJ) +system.physmem_0.averagePower 621.784975 # Core power per rank (mW) +system.physmem_0.totalIdleTime 16957250 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 40500 # Time in different power states +system.physmem_0.memoryStateTime::REF 780000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 0 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 344500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 5900500 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 16710500 # Time in different power states +system.physmem_1.actEnergy 399840 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 212520 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1699320 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 10074465 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 662250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 13465350 # Total energy per rank (pJ) -system.physmem_1.averagePower 850.487920 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1034500 # Time in different power states -system.physmem_1.memoryStateTime::REF 520000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 14291750 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 22248000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 2853 # Number of BP lookups -system.cpu.branchPred.condPredicted 1680 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 481 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 2201 # Number of BTB lookups +system.physmem_1.refreshEnergy 1843920.000000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 2978250 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 130080 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 7628310 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 68160 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 14960400 # Total energy per rank (pJ) +system.physmem_1.averagePower 629.216130 # Core power per rank (mW) +system.physmem_1.totalIdleTime 16769000 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 214000 # Time in different power states +system.physmem_1.memoryStateTime::REF 780000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 0 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 178500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 5875500 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 16728000 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 23776000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 2854 # Number of BP lookups +system.cpu.branchPred.condPredicted 1681 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 482 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 2203 # Number of BTB lookups system.cpu.branchPred.BTBHits 713 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 32.394366 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 442 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 41 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 461 # Number of indirect predictor lookups. +system.cpu.branchPred.BTBHitPct 32.364957 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 441 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 42 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 462 # Number of indirect predictor lookups. system.cpu.branchPred.indirectHits 25 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 436 # Number of indirect misses. +system.cpu.branchPred.indirectMisses 437 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 123 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 2261 # DTB read hits +system.cpu.dtb.read_hits 2252 # DTB read hits system.cpu.dtb.read_misses 48 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 2309 # DTB read accesses -system.cpu.dtb.write_hits 1039 # DTB write hits +system.cpu.dtb.read_accesses 2300 # DTB read accesses +system.cpu.dtb.write_hits 1038 # DTB write hits system.cpu.dtb.write_misses 28 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 1067 # DTB write accesses -system.cpu.dtb.data_hits 3300 # DTB hits +system.cpu.dtb.write_accesses 1066 # DTB write accesses +system.cpu.dtb.data_hits 3290 # DTB hits system.cpu.dtb.data_misses 76 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 3376 # DTB accesses -system.cpu.itb.fetch_hits 2294 # ITB hits +system.cpu.dtb.data_accesses 3366 # DTB accesses +system.cpu.itb.fetch_hits 2295 # ITB hits system.cpu.itb.fetch_misses 27 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 2321 # ITB accesses +system.cpu.itb.fetch_accesses 2322 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -298,236 +309,236 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 22248000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 44497 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 23776000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 47553 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 8475 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 16557 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2853 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 1180 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 5121 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1044 # Number of cycles fetch has spent squashing +system.cpu.fetch.icacheStallCycles 8496 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 16559 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2854 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 1179 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 5759 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1046 # Number of cycles fetch has spent squashing system.cpu.fetch.MiscStallCycles 22 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 656 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 2294 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 333 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 14796 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.119019 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.502117 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 2295 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 335 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 15456 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.071364 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.458774 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 11808 79.81% 79.81% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 299 2.02% 81.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 232 1.57% 83.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 257 1.74% 85.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 292 1.97% 87.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 233 1.57% 88.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 283 1.91% 90.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 144 0.97% 91.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1248 8.43% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 12470 80.68% 80.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 297 1.92% 82.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 230 1.49% 84.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 258 1.67% 85.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 292 1.89% 87.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 234 1.51% 89.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 282 1.82% 90.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 146 0.94% 91.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1247 8.07% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 14796 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.064117 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.372093 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8328 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 3356 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2449 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 215 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 448 # Number of cycles decode is squashing +system.cpu.fetch.rateDist::total 15456 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.060017 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.348222 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8339 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 4008 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2446 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 214 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 449 # Number of cycles decode is squashing system.cpu.decode.BranchResolved 226 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 75 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 15018 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 15004 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 221 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 448 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 8488 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 1745 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 620 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2480 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 1015 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 14460 # Number of instructions processed by rename +system.cpu.rename.SquashCycles 449 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 8498 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 1841 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 655 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2476 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 1537 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 14448 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 2 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 21 # Number of times rename has blocked due to IQ full system.cpu.rename.LQFullEvents 10 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 949 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 10938 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 17913 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 17904 # Number of integer rename lookups +system.cpu.rename.SQFullEvents 1471 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 10929 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 17896 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 17887 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 8 # Number of floating rename lookups system.cpu.rename.CommittedMaps 4577 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 6361 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 6352 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 28 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 22 # count of temporary serializing insts renamed system.cpu.rename.skidInsts 585 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2839 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1293 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.insertedLoads 2834 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1292 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 18 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 6 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 13069 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 13054 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 27 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 10787 # Number of instructions issued +system.cpu.iq.iqInstsIssued 10776 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 17 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 6710 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3679 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedInstsExamined 6695 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3669 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 10 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 14796 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.729048 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.467428 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 15456 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.697205 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.442232 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 10757 72.70% 72.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1291 8.73% 81.43% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 918 6.20% 87.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 680 4.60% 92.23% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 521 3.52% 95.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 349 2.36% 98.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 197 1.33% 99.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 55 0.37% 99.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 28 0.19% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 11416 73.86% 73.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1297 8.39% 82.25% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 916 5.93% 88.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 681 4.41% 92.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 517 3.34% 95.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 347 2.25% 98.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 200 1.29% 99.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 55 0.36% 99.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 27 0.17% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 14796 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 15456 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 21 15.00% 15.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 15.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 15.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 15.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 15.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 15.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 15.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 15.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 15.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 15.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 15.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 15.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 15.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 15.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 15.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 15.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 15.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 15.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 15.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 15.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 15.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 15.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 15.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 15.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 15.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 15.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 15.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 15.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 15.00% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 82 58.57% 73.57% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 37 26.43% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 21 14.89% 14.89% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 14.89% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 14.89% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 14.89% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 14.89% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 14.89% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 14.89% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 14.89% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 14.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 14.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 14.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 14.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 14.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 14.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 14.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 14.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 14.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 14.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 14.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 14.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 14.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 14.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 14.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 14.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 14.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 14.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 14.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 14.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 14.89% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 83 58.87% 73.76% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 37 26.24% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 7188 66.64% 66.65% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.01% 66.66% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.66% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 66.68% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.68% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.68% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.68% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.68% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.68% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2482 23.01% 89.69% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1112 10.31% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 7185 66.68% 66.69% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.01% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 66.72% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.72% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.72% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.72% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.72% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.72% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2475 22.97% 89.69% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1111 10.31% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 10787 # Type of FU issued -system.cpu.iq.rate 0.242421 # Inst issue rate -system.cpu.iq.fu_busy_cnt 140 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.012979 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 36506 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 19817 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 9751 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 10776 # Type of FU issued +system.cpu.iq.rate 0.226610 # Inst issue rate +system.cpu.iq.fu_busy_cnt 141 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.013085 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 37145 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 19787 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 9745 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 21 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 10 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 10914 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 10904 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 11 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 119 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1654 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1649 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 8 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 23 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 428 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 427 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 89 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 78 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 448 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1381 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 302 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 13180 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 449 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1429 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 338 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 13165 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 125 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2839 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1293 # Number of dispatched store instructions +system.cpu.iew.iewDispLoadInsts 2834 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1292 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 27 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 7 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 295 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 331 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 23 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 107 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 390 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 497 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 10303 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2309 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 484 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 10290 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2300 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 486 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 84 # number of nop insts executed -system.cpu.iew.exec_refs 3386 # number of memory reference insts executed -system.cpu.iew.exec_branches 1643 # Number of branches executed -system.cpu.iew.exec_stores 1077 # Number of stores executed -system.cpu.iew.exec_rate 0.231544 # Inst execution rate -system.cpu.iew.wb_sent 9957 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 9761 # cumulative count of insts written-back -system.cpu.iew.wb_producers 5150 # num instructions producing a value -system.cpu.iew.wb_consumers 7013 # num instructions consuming a value -system.cpu.iew.wb_rate 0.219363 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.734350 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 6727 # The number of squashed insts skipped by commit +system.cpu.iew.exec_refs 3376 # number of memory reference insts executed +system.cpu.iew.exec_branches 1642 # Number of branches executed +system.cpu.iew.exec_stores 1076 # Number of stores executed +system.cpu.iew.exec_rate 0.216390 # Inst execution rate +system.cpu.iew.wb_sent 9948 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 9755 # cumulative count of insts written-back +system.cpu.iew.wb_producers 5155 # num instructions producing a value +system.cpu.iew.wb_consumers 7025 # num instructions consuming a value +system.cpu.iew.wb_rate 0.205140 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.733808 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 6712 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 407 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 13560 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.472124 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.390428 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 408 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 14219 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.450243 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.361136 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 11134 82.11% 82.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1157 8.53% 90.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 469 3.46% 94.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 205 1.51% 95.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 133 0.98% 96.59% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 85 0.63% 97.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 96 0.71% 97.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 89 0.66% 98.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 192 1.42% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 11792 82.93% 82.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1158 8.14% 91.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 469 3.30% 94.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 205 1.44% 95.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 133 0.94% 96.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 85 0.60% 97.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 97 0.68% 98.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 88 0.62% 98.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 192 1.35% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 13560 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 14219 # Number of insts commited each cycle system.cpu.commit.committedInsts 6402 # Number of instructions committed system.cpu.commit.committedOps 6402 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -574,47 +585,47 @@ system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Cl system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 6402 # Class of committed instruction system.cpu.commit.bw_lim_events 192 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 26146 # The number of ROB reads -system.cpu.rob.rob_writes 27511 # The number of ROB writes +system.cpu.rob.rob_reads 26790 # The number of ROB reads +system.cpu.rob.rob_writes 27482 # The number of ROB writes system.cpu.timesIdled 250 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 29701 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 32097 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 6385 # Number of Instructions Simulated system.cpu.committedOps 6385 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 6.968990 # CPI: Cycles Per Instruction -system.cpu.cpi_total 6.968990 # CPI: Total CPI of All Threads -system.cpu.ipc 0.143493 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.143493 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 12938 # number of integer regfile reads -system.cpu.int_regfile_writes 7444 # number of integer regfile writes +system.cpu.cpi 7.447612 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.447612 # CPI: Total CPI of All Threads +system.cpu.ipc 0.134271 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.134271 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 12923 # number of integer regfile reads +system.cpu.int_regfile_writes 7437 # number of integer regfile writes system.cpu.fp_regfile_reads 8 # number of floating regfile reads system.cpu.fp_regfile_writes 2 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 22248000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 23776000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 109.756228 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2407 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 110.182603 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2402 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 173 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 13.913295 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 13.884393 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 109.756228 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.026796 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.026796 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 110.182603 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.026900 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.026900 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 173 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 129 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.042236 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 6061 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 6061 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 22248000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 1899 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1899 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 6051 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 6051 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 23776000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 1894 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1894 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 508 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 508 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2407 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2407 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2407 # number of overall hits -system.cpu.dcache.overall_hits::total 2407 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 2402 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2402 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2402 # number of overall hits +system.cpu.dcache.overall_hits::total 2402 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 180 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 180 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 357 # number of WriteReq misses @@ -623,43 +634,43 @@ system.cpu.dcache.demand_misses::cpu.data 537 # n system.cpu.dcache.demand_misses::total 537 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 537 # number of overall misses system.cpu.dcache.overall_misses::total 537 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 12910000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 12910000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 24562475 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 24562475 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 37472475 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 37472475 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 37472475 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 37472475 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 2079 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 2079 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_latency::cpu.data 13953000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 13953000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 31158482 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 31158482 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 45111482 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 45111482 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 45111482 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 45111482 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 2074 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 2074 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2944 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2944 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2944 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2944 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.086580 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.086580 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2939 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2939 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2939 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2939 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.086789 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.086789 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.412717 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.412717 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.182405 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.182405 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.182405 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.182405 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 71722.222222 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 71722.222222 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 68802.450980 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 68802.450980 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 69781.145251 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 69781.145251 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 69781.145251 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 69781.145251 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 2459 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.182715 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.182715 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.182715 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.182715 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 77516.666667 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 77516.666667 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 87278.661064 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 87278.661064 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 84006.484171 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 84006.484171 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 84006.484171 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 84006.484171 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 3098 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 43 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 37 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 57.186047 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 83.729730 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.ReadReq_mshr_hits::cpu.data 79 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 79 # number of ReadReq MSHR hits @@ -677,138 +688,138 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 173 system.cpu.dcache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 173 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 173 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8568000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 8568000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6031500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 6031500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14599500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 14599500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14599500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 14599500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.048581 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.048581 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9401500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 9401500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7013500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 7013500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16415000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 16415000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16415000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 16415000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.048698 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.048698 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083237 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.083237 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.058764 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.058764 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.058764 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.058764 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 84831.683168 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 84831.683168 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 83770.833333 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 83770.833333 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 84390.173410 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 84390.173410 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 84390.173410 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 84390.173410 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 22248000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.058864 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.058864 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.058864 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.058864 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 93084.158416 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 93084.158416 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 97409.722222 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 97409.722222 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 94884.393064 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 94884.393064 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 94884.393064 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 94884.393064 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 23776000 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 159.084059 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1838 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 160.538154 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1837 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 313 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 5.872204 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 5.869010 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 159.084059 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.077678 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.077678 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 160.538154 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.078388 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.078388 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 313 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 137 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 176 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 126 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 187 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.152832 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 4901 # Number of tag accesses -system.cpu.icache.tags.data_accesses 4901 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 22248000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 1838 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1838 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1838 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1838 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1838 # number of overall hits -system.cpu.icache.overall_hits::total 1838 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 456 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 456 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 456 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 456 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 456 # number of overall misses -system.cpu.icache.overall_misses::total 456 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 32999500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 32999500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 32999500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 32999500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 32999500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 32999500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2294 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2294 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2294 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2294 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2294 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2294 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.198779 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.198779 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.198779 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.198779 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.198779 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.198779 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72367.324561 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 72367.324561 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 72367.324561 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 72367.324561 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 72367.324561 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 72367.324561 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 56 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 4903 # Number of tag accesses +system.cpu.icache.tags.data_accesses 4903 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 23776000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 1837 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1837 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1837 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1837 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1837 # number of overall hits +system.cpu.icache.overall_hits::total 1837 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 458 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 458 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 458 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 458 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 458 # number of overall misses +system.cpu.icache.overall_misses::total 458 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 35507500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 35507500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 35507500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 35507500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 35507500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 35507500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 2295 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 2295 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 2295 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 2295 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 2295 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 2295 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.199564 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.199564 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.199564 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.199564 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.199564 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.199564 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77527.292576 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 77527.292576 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 77527.292576 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 77527.292576 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 77527.292576 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 77527.292576 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 67 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 56 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 67 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 143 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 143 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 143 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 143 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 143 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 143 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 145 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 145 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 145 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 145 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 145 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 145 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 313 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 313 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 313 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 313 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 313 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 313 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24573000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 24573000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24573000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 24573000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24573000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 24573000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.136443 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.136443 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.136443 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.136443 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.136443 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.136443 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 78507.987220 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 78507.987220 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 78507.987220 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 78507.987220 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 78507.987220 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 78507.987220 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 22248000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 26275500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 26275500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 26275500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 26275500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 26275500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 26275500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.136383 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.136383 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.136383 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.136383 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.136383 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.136383 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 83947.284345 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 83947.284345 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 83947.284345 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 83947.284345 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 83947.284345 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 83947.284345 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 23776000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 268.962928 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 270.818986 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 485 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.002062 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 159.125052 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 109.837876 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004856 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.003352 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.008208 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 160.559983 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 110.259003 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004900 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.003365 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.008265 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 485 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 180 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 305 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 167 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 318 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.014801 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 4373 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 4373 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 22248000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 23776000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1 # number of ReadCleanReq hits system.cpu.l2cache.ReadCleanReq_hits::total 1 # number of ReadCleanReq hits system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits @@ -827,18 +838,18 @@ system.cpu.l2cache.demand_misses::total 485 # nu system.cpu.l2cache.overall_misses::cpu.inst 312 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 173 # number of overall misses system.cpu.l2cache.overall_misses::total 485 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5920500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5920500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 24090000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 24090000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 8408000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 8408000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 24090000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 14328500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 38418500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 24090000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 14328500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 38418500 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6902500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 6902500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 25792500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 25792500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 9241500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 9241500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 25792500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 16144000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 41936500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 25792500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 16144000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 41936500 # number of overall miss cycles system.cpu.l2cache.ReadExReq_accesses::cpu.data 72 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 72 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 313 # number of ReadCleanReq accesses(hits+misses) @@ -863,18 +874,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.997942 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996805 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.997942 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 82229.166667 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 82229.166667 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 77211.538462 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 77211.538462 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83247.524752 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83247.524752 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77211.538462 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 82823.699422 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 79213.402062 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77211.538462 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 82823.699422 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 79213.402062 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 95868.055556 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 95868.055556 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82668.269231 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82668.269231 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 91500 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 91500 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82668.269231 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 93317.919075 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 86467.010309 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82668.269231 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 93317.919075 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 86467.010309 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -893,18 +904,18 @@ system.cpu.l2cache.demand_mshr_misses::total 485 system.cpu.l2cache.overall_mshr_misses::cpu.inst 312 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 173 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 485 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5200500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5200500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 20970000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 20970000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7398000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7398000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 20970000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 12598500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 33568500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 20970000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12598500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 33568500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6182500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6182500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 22672500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 22672500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 8231500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 8231500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22672500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 14414000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 37086500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22672500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 14414000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 37086500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for ReadCleanReq accesses @@ -917,25 +928,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.997942 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.997942 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 72229.166667 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 72229.166667 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67211.538462 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67211.538462 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73247.524752 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73247.524752 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67211.538462 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72823.699422 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69213.402062 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67211.538462 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72823.699422 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69213.402062 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 85868.055556 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 85868.055556 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72668.269231 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72668.269231 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 81500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 81500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72668.269231 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 83317.919075 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 76467.010309 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72668.269231 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 83317.919075 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 76467.010309 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 486 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 22248000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 23776000 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 414 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 72 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 72 # Transaction distribution @@ -961,18 +972,18 @@ system.cpu.toL2Bus.snoop_fanout::min_value 0 # system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 486 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 243000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) +system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 469500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.utilization 2.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 259500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) system.membus.snoop_filter.tot_requests 485 # Total number of requests made to the snoop filter. system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 22248000 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 23776000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 413 # Transaction distribution system.membus.trans_dist::ReadExReq 72 # Transaction distribution system.membus.trans_dist::ReadExResp 72 # Transaction distribution @@ -993,9 +1004,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 485 # Request fanout histogram -system.membus.reqLayer0.occupancy 591500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 2578750 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 11.6 # Layer utilization (%) +system.membus.reqLayer0.occupancy 595000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.5 # Layer utilization (%) +system.membus.respLayer1.occupancy 2572250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 10.8 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/config.ini index b9631a6d8..067911f85 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/config.ini @@ -14,6 +14,7 @@ children=clk_domain cpu dvfs_handler mem_ctrls ruby sys_port_proxy voltage_domai boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 exit_on_work_items=false init_param=0 @@ -22,11 +23,15 @@ kernel_addr_check=true load_addr_mask=1099511627775 load_offset=0 mem_mode=timing -mem_ranges=0:268435455 +mem_ranges=0:268435455:0:0:0:0 memories=system.mem_ctrls mmap_using_noreserve=false multi_thread=false num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null readfile= symbolfile= thermal_components= @@ -55,6 +60,7 @@ branchPred=Null checker=Null clk_domain=system.cpu.clk_domain cpu_id=0 +default_p_state=UNDEFINED do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true @@ -70,6 +76,10 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null profile=0 progress_interval=0 simpoint_start_insts= @@ -122,7 +132,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/hello/bin/alpha/linux/hello +executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin kvmInSE=false @@ -145,27 +155,27 @@ transition_latency=100000 [system.mem_ctrls] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -177,6 +187,7 @@ burst_length=8 channels=1 clk_domain=system.clk_domain conf_table_reported=true +default_p_state=UNDEFINED device_bus_width=8 device_rowbuffer_size=1024 device_size=536870912 @@ -184,12 +195,17 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 page_policy=open_adaptive -range=0:268435455 +power_model=Null +range=0:268435455:5:19:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10 @@ -211,9 +227,9 @@ tRTW=3 tWR=15 tWTR=8 tXAW=30 -tXP=0 +tXP=6 tXPDLL=0 -tXS=0 +tXS=270 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 @@ -227,12 +243,17 @@ access_backing_store=false all_instructions=false block_size_bytes=64 clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED eventq_index=0 hot_lines=false memory_size_bits=48 num_of_sequencers=1 number_of_virtual_networks=3 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 phys_mem=Null +power_model=Null randomization=false [system.ruby.clk_domain] @@ -249,10 +270,15 @@ children=directory requestToDir responseFromDir responseFromMemory responseToDir buffer_size=0 clk_domain=system.ruby.clk_domain cluster_id=0 +default_p_state=UNDEFINED directory=system.ruby.dir_cntrl0.directory directory_latency=6 eventq_index=0 number_of_TBEs=256 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null recycle_latency=10 requestToDir=system.ruby.dir_cntrl0.requestToDir responseFromDir=system.ruby.dir_cntrl0.responseFromDir @@ -311,6 +337,7 @@ L1Icache=system.ruby.l1_cntrl0.L1Icache buffer_size=0 clk_domain=system.cpu.clk_domain cluster_id=0 +default_p_state=UNDEFINED enable_prefetch=false eventq_index=0 l1_request_latency=2 @@ -319,6 +346,10 @@ l2_select_num_bits=0 mandatoryQueue=system.ruby.l1_cntrl0.mandatoryQueue number_of_TBEs=256 optionalQueue=system.ruby.l1_cntrl0.optionalQueue +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null prefetcher=system.ruby.l1_cntrl0.prefetcher recycle_latency=10 requestFromL1Cache=system.ruby.l1_cntrl0.requestFromL1Cache @@ -447,17 +478,22 @@ coreid=99 dcache=system.ruby.l1_cntrl0.L1Dcache dcache_hit_latency=1 deadlock_threshold=500000 +default_p_state=UNDEFINED eventq_index=0 +garnet_standalone=false icache=system.ruby.l1_cntrl0.L1Icache icache_hit_latency=1 is_cpu_sequencer=true max_outstanding_requests=16 no_retry_on_stall=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null ruby_system=system.ruby support_data_reqs=true support_inst_reqs=true system=system -using_network_tester=false using_ruby_tester=false version=0 slave=system.cpu.icache_port system.cpu.dcache_port @@ -480,10 +516,15 @@ L2cache=system.ruby.l2_cntrl0.L2cache buffer_size=0 clk_domain=system.ruby.clk_domain cluster_id=0 +default_p_state=UNDEFINED eventq_index=0 l2_request_latency=2 l2_response_latency=2 number_of_TBEs=256 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null recycle_latency=10 responseFromL2Cache=system.ruby.l2_cntrl0.responseFromL2Cache responseToL2Cache=system.ruby.l2_cntrl0.responseToL2Cache @@ -574,18 +615,23 @@ eventq_index=0 [system.ruby.network] type=SimpleNetwork -children=ext_links0 ext_links1 ext_links2 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_links0 int_links1 int_links2 routers0 routers1 routers2 routers3 +children=ext_links0 ext_links1 ext_links2 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_link_buffers20 int_link_buffers21 int_link_buffers22 int_link_buffers23 int_link_buffers24 int_link_buffers25 int_link_buffers26 int_link_buffers27 int_link_buffers28 int_link_buffers29 int_link_buffers30 int_link_buffers31 int_link_buffers32 int_link_buffers33 int_link_buffers34 int_link_buffers35 int_links0 int_links1 int_links2 int_links3 int_links4 int_links5 routers0 routers1 routers2 routers3 adaptive_routing=false buffer_size=0 clk_domain=system.ruby.clk_domain control_msg_size=8 +default_p_state=UNDEFINED endpoint_bandwidth=1000 eventq_index=0 ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1 system.ruby.network.ext_links2 -int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 -int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2 +int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19 system.ruby.network.int_link_buffers20 system.ruby.network.int_link_buffers21 system.ruby.network.int_link_buffers22 system.ruby.network.int_link_buffers23 system.ruby.network.int_link_buffers24 system.ruby.network.int_link_buffers25 system.ruby.network.int_link_buffers26 system.ruby.network.int_link_buffers27 system.ruby.network.int_link_buffers28 system.ruby.network.int_link_buffers29 system.ruby.network.int_link_buffers30 system.ruby.network.int_link_buffers31 system.ruby.network.int_link_buffers32 system.ruby.network.int_link_buffers33 system.ruby.network.int_link_buffers34 system.ruby.network.int_link_buffers35 +int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2 system.ruby.network.int_links3 system.ruby.network.int_links4 system.ruby.network.int_links5 netifs= number_of_virtual_networks=3 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null routers=system.ruby.network.routers0 system.ruby.network.routers1 system.ruby.network.routers2 system.ruby.network.routers3 ruby_system=system.ruby topology=Crossbar @@ -748,42 +794,216 @@ eventq_index=0 ordered=true randomization=false +[system.ruby.network.int_link_buffers18] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers19] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers20] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers21] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers22] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers23] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers24] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers25] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers26] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers27] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers28] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers29] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers30] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers31] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers32] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers33] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers34] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers35] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + [system.ruby.network.int_links0] type=SimpleIntLink bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers3 eventq_index=0 latency=1 link_id=3 -node_a=system.ruby.network.routers0 -node_b=system.ruby.network.routers3 +src_node=system.ruby.network.routers0 +src_outport= weight=1 [system.ruby.network.int_links1] type=SimpleIntLink bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers3 eventq_index=0 latency=1 link_id=4 -node_a=system.ruby.network.routers1 -node_b=system.ruby.network.routers3 +src_node=system.ruby.network.routers1 +src_outport= weight=1 [system.ruby.network.int_links2] type=SimpleIntLink bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers3 eventq_index=0 latency=1 link_id=5 -node_a=system.ruby.network.routers2 -node_b=system.ruby.network.routers3 +src_node=system.ruby.network.routers2 +src_outport= +weight=1 + +[system.ruby.network.int_links3] +type=SimpleIntLink +bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers0 +eventq_index=0 +latency=1 +link_id=6 +src_node=system.ruby.network.routers3 +src_outport= +weight=1 + +[system.ruby.network.int_links4] +type=SimpleIntLink +bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers1 +eventq_index=0 +latency=1 +link_id=7 +src_node=system.ruby.network.routers3 +src_outport= +weight=1 + +[system.ruby.network.int_links5] +type=SimpleIntLink +bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers2 +eventq_index=0 +latency=1 +link_id=8 +src_node=system.ruby.network.routers3 +src_outport= weight=1 [system.ruby.network.routers0] type=Switch children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED eventq_index=0 +latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 port_buffers=system.ruby.network.routers0.port_buffers00 system.ruby.network.routers0.port_buffers01 system.ruby.network.routers0.port_buffers02 system.ruby.network.routers0.port_buffers03 system.ruby.network.routers0.port_buffers04 system.ruby.network.routers0.port_buffers05 system.ruby.network.routers0.port_buffers06 system.ruby.network.routers0.port_buffers07 system.ruby.network.routers0.port_buffers08 system.ruby.network.routers0.port_buffers09 system.ruby.network.routers0.port_buffers10 system.ruby.network.routers0.port_buffers11 +power_model=Null router_id=0 virt_nets=3 @@ -875,8 +1095,14 @@ randomization=false type=Switch children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED eventq_index=0 +latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 port_buffers=system.ruby.network.routers1.port_buffers00 system.ruby.network.routers1.port_buffers01 system.ruby.network.routers1.port_buffers02 system.ruby.network.routers1.port_buffers03 system.ruby.network.routers1.port_buffers04 system.ruby.network.routers1.port_buffers05 system.ruby.network.routers1.port_buffers06 system.ruby.network.routers1.port_buffers07 system.ruby.network.routers1.port_buffers08 system.ruby.network.routers1.port_buffers09 system.ruby.network.routers1.port_buffers10 system.ruby.network.routers1.port_buffers11 +power_model=Null router_id=1 virt_nets=3 @@ -968,8 +1194,14 @@ randomization=false type=Switch children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED eventq_index=0 +latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 port_buffers=system.ruby.network.routers2.port_buffers00 system.ruby.network.routers2.port_buffers01 system.ruby.network.routers2.port_buffers02 system.ruby.network.routers2.port_buffers03 system.ruby.network.routers2.port_buffers04 system.ruby.network.routers2.port_buffers05 system.ruby.network.routers2.port_buffers06 system.ruby.network.routers2.port_buffers07 system.ruby.network.routers2.port_buffers08 system.ruby.network.routers2.port_buffers09 system.ruby.network.routers2.port_buffers10 system.ruby.network.routers2.port_buffers11 +power_model=Null router_id=2 virt_nets=3 @@ -1061,8 +1293,14 @@ randomization=false type=Switch children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17 clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED eventq_index=0 +latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 port_buffers=system.ruby.network.routers3.port_buffers00 system.ruby.network.routers3.port_buffers01 system.ruby.network.routers3.port_buffers02 system.ruby.network.routers3.port_buffers03 system.ruby.network.routers3.port_buffers04 system.ruby.network.routers3.port_buffers05 system.ruby.network.routers3.port_buffers06 system.ruby.network.routers3.port_buffers07 system.ruby.network.routers3.port_buffers08 system.ruby.network.routers3.port_buffers09 system.ruby.network.routers3.port_buffers10 system.ruby.network.routers3.port_buffers11 system.ruby.network.routers3.port_buffers12 system.ruby.network.routers3.port_buffers13 system.ruby.network.routers3.port_buffers14 system.ruby.network.routers3.port_buffers15 system.ruby.network.routers3.port_buffers16 system.ruby.network.routers3.port_buffers17 +power_model=Null router_id=3 virt_nets=3 @@ -1195,9 +1433,14 @@ randomization=false [system.sys_port_proxy] type=RubyPortProxy clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 is_cpu_sequencer=true no_retry_on_stall=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null ruby_system=system.ruby support_data_reqs=true support_inst_reqs=true diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/simerr b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/simerr index ccfdd3697..f6f6f15a5 100755 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/simerr +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/simerr @@ -4,8 +4,7 @@ warn: rounding error > tolerance 1.250000 rounded to 1 warn: rounding error > tolerance 1.250000 rounded to 1 -warn: rounding error > tolerance - 1.250000 rounded to 1 warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes) warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files! diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/simout b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/simout index 838211534..1a88d47ac 100755 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/simout +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/simout @@ -3,13 +3,13 @@ Redirecting stderr to build/ALPHA_MESI_Two_Level/tests/opt/quick/se/00.hello/alp gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 14 2016 22:00:08 -gem5 started Mar 14 2016 22:01:20 -gem5 executing on phenom, pid 28860 -command line: build/ALPHA_MESI_Two_Level/gem5.opt -d build/ALPHA_MESI_Two_Level/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MESI_Two_Level -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA_MESI_Two_Level/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MESI_Two_Level +gem5 compiled Oct 13 2016 20:28:06 +gem5 started Oct 13 2016 20:28:31 +gem5 executing on e108600-lin, pid 8233 +command line: /work/curdun01/gem5-external.hg/build/ALPHA_MESI_Two_Level/gem5.opt -d build/ALPHA_MESI_Two_Level/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MESI_Two_Level -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/alpha/linux/simple-timing-ruby-MESI_Two_Level Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 121535 because target called exit() +Exiting @ tick 129075 because target called exit() diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/stats.txt index d17f0dc2a..66e7aabe9 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000122 # Number of seconds simulated -sim_ticks 121535 # Number of ticks simulated -final_tick 121535 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000129 # Number of seconds simulated +sim_ticks 129075 # Number of ticks simulated +final_tick 129075 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 67126 # Simulator instruction rate (inst/s) -host_op_rate 67120 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1273887 # Simulator tick rate (ticks/s) -host_mem_usage 453732 # Number of bytes of host memory used -host_seconds 0.10 # Real time elapsed on the host +host_inst_rate 59192 # Simulator instruction rate (inst/s) +host_op_rate 59185 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1192972 # Simulator tick rate (ticks/s) +host_mem_usage 410988 # Number of bytes of host memory used +host_seconds 0.11 # Real time elapsed on the host sim_insts 6403 # Number of instructions simulated sim_ops 6403 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks -system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 121535 # Cumulative time (in ticks) in various power states +system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 129075 # Cumulative time (in ticks) in various power states system.mem_ctrls.bytes_read::ruby.dir_cntrl0 93504 # Number of bytes read from this memory system.mem_ctrls.bytes_read::total 93504 # Number of bytes read from this memory system.mem_ctrls.bytes_written::ruby.dir_cntrl0 17728 # Number of bytes written to this memory @@ -22,35 +22,35 @@ system.mem_ctrls.num_reads::ruby.dir_cntrl0 1461 # system.mem_ctrls.num_reads::total 1461 # Number of read requests responded to by this memory system.mem_ctrls.num_writes::ruby.dir_cntrl0 277 # Number of write requests responded to by this memory system.mem_ctrls.num_writes::total 277 # Number of write requests responded to by this memory -system.mem_ctrls.bw_read::ruby.dir_cntrl0 769358621 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_read::total 769358621 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::ruby.dir_cntrl0 145867446 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::total 145867446 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_total::ruby.dir_cntrl0 915226067 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.bw_total::total 915226067 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_read::ruby.dir_cntrl0 724416037 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 724416037 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::ruby.dir_cntrl0 137346504 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::total 137346504 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::ruby.dir_cntrl0 861762541 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 861762541 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrls.readReqs 1461 # Number of read requests accepted system.mem_ctrls.writeReqs 277 # Number of write requests accepted system.mem_ctrls.readBursts 1461 # Number of DRAM read bursts, including those serviced by the write queue system.mem_ctrls.writeBursts 277 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrls.bytesReadDRAM 74240 # Total number of bytes read from DRAM -system.mem_ctrls.bytesReadWrQ 19264 # Total number of bytes read from write queue -system.mem_ctrls.bytesWritten 5376 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadDRAM 74368 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 19136 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 6400 # Total number of bytes written to DRAM system.mem_ctrls.bytesReadSys 93504 # Total read bytes from the system interface side system.mem_ctrls.bytesWrittenSys 17728 # Total written bytes from the system interface side -system.mem_ctrls.servicedByWrQ 301 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrls.mergedWrBursts 163 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.servicedByWrQ 299 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 160 # Number of DRAM write bursts merged with an existing one system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.mem_ctrls.perBankRdBursts::0 102 # Per bank write bursts system.mem_ctrls.perBankRdBursts::1 61 # Per bank write bursts system.mem_ctrls.perBankRdBursts::2 90 # Per bank write bursts system.mem_ctrls.perBankRdBursts::3 90 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::4 94 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::5 21 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 101 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 22 # Per bank write bursts system.mem_ctrls.perBankRdBursts::6 1 # Per bank write bursts system.mem_ctrls.perBankRdBursts::7 4 # Per bank write bursts system.mem_ctrls.perBankRdBursts::8 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::9 1 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::10 84 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 78 # Per bank write bursts system.mem_ctrls.perBankRdBursts::11 75 # Per bank write bursts system.mem_ctrls.perBankRdBursts::12 26 # Per bank write bursts system.mem_ctrls.perBankRdBursts::13 395 # Per bank write bursts @@ -60,21 +60,21 @@ system.mem_ctrls.perBankWrBursts::0 0 # Pe system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::4 18 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::5 6 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 24 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 7 # Per bank write bursts system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::10 3 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 7 # Per bank write bursts system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::13 16 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 21 # Per bank write bursts system.mem_ctrls.perBankWrBursts::14 41 # Per bank write bursts system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrls.totGap 121448 # Total gap between requests +system.mem_ctrls.totGap 128982 # Total gap between requests system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) @@ -89,7 +89,7 @@ system.mem_ctrls.writePktSize::3 0 # Wr system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::6 277 # Write request sizes (log2) -system.mem_ctrls.rdQLenPdf::0 1160 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::0 1162 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see @@ -151,9 +151,9 @@ system.mem_ctrls.wrQLenPdf::26 6 # Wh system.mem_ctrls.wrQLenPdf::27 6 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::28 6 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::29 6 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::30 5 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::31 5 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::32 5 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 6 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 6 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::32 6 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see @@ -185,88 +185,99 @@ system.mem_ctrls.wrQLenPdf::60 0 # Wh system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrls.bytesPerActivate::samples 217 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::mean 357.751152 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::gmean 214.775071 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::stdev 343.064988 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::0-127 66 30.41% 30.41% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::128-255 51 23.50% 53.92% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::256-383 17 7.83% 61.75% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::384-511 18 8.29% 70.05% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::512-639 15 6.91% 76.96% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::640-767 6 2.76% 79.72% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::768-895 12 5.53% 85.25% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::896-1023 4 1.84% 87.10% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::1024-1151 28 12.90% 100.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::total 217 # Bytes accessed per row activation -system.mem_ctrls.rdPerTurnAround::samples 5 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::mean 150.400000 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::gmean 107.633945 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::stdev 97.202366 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::16-23 1 20.00% 20.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::72-79 1 20.00% 40.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::200-207 1 20.00% 60.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::208-215 1 20.00% 80.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::240-247 1 20.00% 100.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::total 5 # Reads before turning the bus around for writes -system.mem_ctrls.wrPerTurnAround::samples 5 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::mean 16.800000 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::gmean 16.771851 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::stdev 1.095445 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::16 3 60.00% 60.00% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::18 2 40.00% 100.00% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::total 5 # Writes before turning the bus around for reads -system.mem_ctrls.totQLat 8011 # Total ticks spent queuing -system.mem_ctrls.totMemAccLat 30051 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrls.totBusLat 5800 # Total ticks spent in databus transfers -system.mem_ctrls.avgQLat 6.91 # Average queueing delay per DRAM burst +system.mem_ctrls.bytesPerActivate::samples 215 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 364.055814 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 222.075931 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 347.859995 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 60 27.91% 27.91% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 55 25.58% 53.49% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 24 11.16% 64.65% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 15 6.98% 71.63% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 8 3.72% 75.35% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 9 4.19% 79.53% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 8 3.72% 83.26% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 5 2.33% 85.58% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 31 14.42% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 215 # Bytes accessed per row activation +system.mem_ctrls.rdPerTurnAround::samples 6 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::mean 193.166667 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::gmean 134.817545 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::stdev 132.906609 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::16-31 1 16.67% 16.67% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::64-79 1 16.67% 33.33% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::192-207 1 16.67% 50.00% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::224-239 1 16.67% 66.67% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::240-255 1 16.67% 83.33% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::384-399 1 16.67% 100.00% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::total 6 # Reads before turning the bus around for writes +system.mem_ctrls.wrPerTurnAround::samples 6 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::mean 16.666667 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::gmean 16.640671 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::stdev 1.032796 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::16 4 66.67% 66.67% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::18 2 33.33% 100.00% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::total 6 # Writes before turning the bus around for reads +system.mem_ctrls.totQLat 15493 # Total ticks spent queuing +system.mem_ctrls.totMemAccLat 37571 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.totBusLat 5810 # Total ticks spent in databus transfers +system.mem_ctrls.avgQLat 13.33 # Average queueing delay per DRAM burst system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst -system.mem_ctrls.avgMemAccLat 25.91 # Average memory access latency per DRAM burst -system.mem_ctrls.avgRdBW 610.85 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrls.avgWrBW 44.23 # Average achieved write bandwidth in MiByte/s -system.mem_ctrls.avgRdBWSys 769.36 # Average system read bandwidth in MiByte/s -system.mem_ctrls.avgWrBWSys 145.87 # Average system write bandwidth in MiByte/s +system.mem_ctrls.avgMemAccLat 32.33 # Average memory access latency per DRAM burst +system.mem_ctrls.avgRdBW 576.16 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 49.58 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 724.42 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 137.35 # Average system write bandwidth in MiByte/s system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrls.busUtil 5.12 # Data bus utilization in percentage -system.mem_ctrls.busUtilRead 4.77 # Data bus utilization in percentage for reads -system.mem_ctrls.busUtilWrite 0.35 # Data bus utilization in percentage for writes +system.mem_ctrls.busUtil 4.89 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 4.50 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 0.39 # Data bus utilization in percentage for writes system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing -system.mem_ctrls.avgWrQLen 22.41 # Average write queue length when enqueuing -system.mem_ctrls.readRowHits 943 # Number of row buffer hits during reads -system.mem_ctrls.writeRowHits 78 # Number of row buffer hits during writes -system.mem_ctrls.readRowHitRate 81.29 # Row buffer hit rate for reads -system.mem_ctrls.writeRowHitRate 68.42 # Row buffer hit rate for writes -system.mem_ctrls.avgGap 69.88 # Average gap between requests -system.mem_ctrls.pageHitRate 80.14 # Row buffer hit rate, read and write combined -system.mem_ctrls_0.actEnergy 506520 # Energy for activate commands per rank (pJ) -system.mem_ctrls_0.preEnergy 281400 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_0.readEnergy 5703360 # Energy for read commands per rank (pJ) -system.mem_ctrls_0.writeEnergy 248832 # Energy for write commands per rank (pJ) -system.mem_ctrls_0.refreshEnergy 7628400 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_0.actBackEnergy 65986164 # Energy for active background per rank (pJ) -system.mem_ctrls_0.preBackEnergy 12347400 # Energy for precharge background per rank (pJ) -system.mem_ctrls_0.totalEnergy 92702076 # Total energy per rank (pJ) -system.mem_ctrls_0.averagePower 791.986980 # Core power per rank (mW) -system.mem_ctrls_0.memoryStateTime::IDLE 22788 # Time in different power states -system.mem_ctrls_0.memoryStateTime::REF 3900 # Time in different power states -system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT 92991 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrls_1.actEnergy 1103760 # Energy for activate commands per rank (pJ) -system.mem_ctrls_1.preEnergy 613200 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_1.readEnergy 8236800 # Energy for read commands per rank (pJ) -system.mem_ctrls_1.writeEnergy 622080 # Energy for write commands per rank (pJ) -system.mem_ctrls_1.refreshEnergy 7628400 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_1.actBackEnergy 78402132 # Energy for active background per rank (pJ) -system.mem_ctrls_1.preBackEnergy 1456200 # Energy for precharge background per rank (pJ) -system.mem_ctrls_1.totalEnergy 98062572 # Total energy per rank (pJ) -system.mem_ctrls_1.averagePower 837.783614 # Core power per rank (mW) -system.mem_ctrls_1.memoryStateTime::IDLE 1811 # Time in different power states -system.mem_ctrls_1.memoryStateTime::REF 3900 # Time in different power states -system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT 111353 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 121535 # Cumulative time (in ticks) in various power states +system.mem_ctrls.avgWrQLen 22.78 # Average write queue length when enqueuing +system.mem_ctrls.readRowHits 949 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 91 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 81.67 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate 77.78 # Row buffer hit rate for writes +system.mem_ctrls.avgGap 74.21 # Average gap between requests +system.mem_ctrls.pageHitRate 81.31 # Row buffer hit rate, read and write combined +system.mem_ctrls_0.actEnergy 514080 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 270480 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 5380704 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 258912 # Energy for write commands per rank (pJ) +system.mem_ctrls_0.refreshEnergy 9834240.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 8608824 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 320256 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.actPowerDownEnergy 37409784 # Energy for active power-down per rank (pJ) +system.mem_ctrls_0.prePowerDownEnergy 6725376 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls_0.selfRefreshEnergy 2906400 # Energy for self refresh per rank (pJ) +system.mem_ctrls_0.totalEnergy 72229056 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 559.589820 # Core power per rank (mW) +system.mem_ctrls_0.totalIdleTime 109312 # Total Idle time Per DRAM Rank +system.mem_ctrls_0.memoryStateTime::IDLE 366 # Time in different power states +system.mem_ctrls_0.memoryStateTime::REF 4166 # Time in different power states +system.mem_ctrls_0.memoryStateTime::SREF 9809 # Time in different power states +system.mem_ctrls_0.memoryStateTime::PRE_PDN 17514 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 15181 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT_PDN 82039 # Time in different power states +system.mem_ctrls_1.actEnergy 1071000 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 560280 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 7893984 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 576288 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.refreshEnergy 9834240.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 12597000 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 372480 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.actPowerDownEnergy 45058272 # Energy for active power-down per rank (pJ) +system.mem_ctrls_1.prePowerDownEnergy 640512 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls_1.totalEnergy 78604056 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 608.979709 # Core power per rank (mW) +system.mem_ctrls_1.totalIdleTime 100248 # Total Idle time Per DRAM Rank +system.mem_ctrls_1.memoryStateTime::IDLE 270 # Time in different power states +system.mem_ctrls_1.memoryStateTime::REF 4160 # Time in different power states +system.mem_ctrls_1.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls_1.memoryStateTime::PRE_PDN 1668 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 24165 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT_PDN 98812 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 129075 # Cumulative time (in ticks) in various power states system.cpu.clk_domain.clock 1 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -301,8 +312,8 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 121535 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 121535 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 129075 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 129075 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 6403 # Number of instructions committed @@ -321,7 +332,7 @@ system.cpu.num_mem_refs 2060 # nu system.cpu.num_load_insts 1192 # Number of load instructions system.cpu.num_store_insts 868 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 121535 # Number of busy cycles +system.cpu.num_busy_cycles 129075 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 1056 # Number of branches fetched @@ -361,13 +372,13 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 6413 # Class of executed instruction system.ruby.clk_domain.clock 1 # Clock period in ticks -system.ruby.pwrStateResidencyTicks::UNDEFINED 121535 # Cumulative time (in ticks) in various power states +system.ruby.pwrStateResidencyTicks::UNDEFINED 129075 # Cumulative time (in ticks) in various power states system.ruby.delayHist::bucket_size 1 # delay histogram for all message system.ruby.delayHist::max_bucket 9 # delay histogram for all message system.ruby.delayHist::samples 9652 # delay histogram for all message -system.ruby.delayHist::mean 0.164525 # delay histogram for all message -system.ruby.delayHist::stdev 1.011525 # delay histogram for all message -system.ruby.delayHist | 9293 96.28% 96.28% | 0 0.00% 96.28% | 214 2.22% 98.50% | 0 0.00% 98.50% | 0 0.00% 98.50% | 0 0.00% 98.50% | 0 0.00% 98.50% | 0 0.00% 98.50% | 145 1.50% 100.00% | 0 0.00% 100.00% # delay histogram for all message +system.ruby.delayHist::mean 0.163697 # delay histogram for all message +system.ruby.delayHist::stdev 1.010840 # delay histogram for all message +system.ruby.delayHist | 9297 96.32% 96.32% | 0 0.00% 96.32% | 210 2.18% 98.50% | 0 0.00% 98.50% | 0 0.00% 98.50% | 0 0.00% 98.50% | 0 0.00% 98.50% | 0 0.00% 98.50% | 145 1.50% 100.00% | 0 0.00% 100.00% # delay histogram for all message system.ruby.delayHist::total 9652 # delay histogram for all message system.ruby.outstanding_req_hist_seqr::bucket_size 1 system.ruby.outstanding_req_hist_seqr::max_bucket 9 @@ -379,10 +390,10 @@ system.ruby.outstanding_req_hist_seqr::total 8464 system.ruby.latency_hist_seqr::bucket_size 64 system.ruby.latency_hist_seqr::max_bucket 639 system.ruby.latency_hist_seqr::samples 8463 -system.ruby.latency_hist_seqr::mean 13.360747 -system.ruby.latency_hist_seqr::gmean 2.097350 -system.ruby.latency_hist_seqr::stdev 29.565169 -system.ruby.latency_hist_seqr | 7303 86.29% 86.29% | 1141 13.48% 99.78% | 4 0.05% 99.82% | 1 0.01% 99.83% | 8 0.09% 99.93% | 6 0.07% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.latency_hist_seqr::mean 14.251684 +system.ruby.latency_hist_seqr::gmean 2.119385 +system.ruby.latency_hist_seqr::stdev 32.289040 +system.ruby.latency_hist_seqr | 7301 86.27% 86.27% | 1142 13.49% 99.76% | 3 0.04% 99.80% | 1 0.01% 99.81% | 6 0.07% 99.88% | 9 0.11% 99.99% | 0 0.00% 99.99% | 0 0.00% 99.99% | 0 0.00% 99.99% | 1 0.01% 100.00% system.ruby.latency_hist_seqr::total 8463 system.ruby.hit_latency_hist_seqr::bucket_size 1 system.ruby.hit_latency_hist_seqr::max_bucket 9 @@ -394,12 +405,12 @@ system.ruby.hit_latency_hist_seqr::total 6972 system.ruby.miss_latency_hist_seqr::bucket_size 64 system.ruby.miss_latency_hist_seqr::max_bucket 639 system.ruby.miss_latency_hist_seqr::samples 1491 -system.ruby.miss_latency_hist_seqr::mean 71.160295 -system.ruby.miss_latency_hist_seqr::gmean 66.961050 -system.ruby.miss_latency_hist_seqr::stdev 30.103565 -system.ruby.miss_latency_hist_seqr | 331 22.20% 22.20% | 1141 76.53% 98.73% | 4 0.27% 98.99% | 1 0.07% 99.06% | 8 0.54% 99.60% | 6 0.40% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.miss_latency_hist_seqr::mean 76.217304 +system.ruby.miss_latency_hist_seqr::gmean 71.053455 +system.ruby.miss_latency_hist_seqr::stdev 35.454362 +system.ruby.miss_latency_hist_seqr | 329 22.07% 22.07% | 1142 76.59% 98.66% | 3 0.20% 98.86% | 1 0.07% 98.93% | 6 0.40% 99.33% | 9 0.60% 99.93% | 0 0.00% 99.93% | 0 0.00% 99.93% | 0 0.00% 99.93% | 1 0.07% 100.00% system.ruby.miss_latency_hist_seqr::total 1491 -system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 121535 # Cumulative time (in ticks) in various power states +system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 129075 # Cumulative time (in ticks) in various power states system.ruby.l1_cntrl0.L1Dcache.demand_hits 1250 # Number of cache demand hits system.ruby.l1_cntrl0.L1Dcache.demand_misses 800 # Number of cache demand misses system.ruby.l1_cntrl0.L1Dcache.demand_accesses 2050 # Number of cache demand accesses @@ -415,15 +426,15 @@ system.ruby.l1_cntrl0.prefetcher.hits 0 # nu system.ruby.l1_cntrl0.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched system.ruby.l1_cntrl0.prefetcher.pages_crossed 0 # number of prefetches across pages system.ruby.l1_cntrl0.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed -system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 121535 # Cumulative time (in ticks) in various power states -system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 121535 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 129075 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 129075 # Cumulative time (in ticks) in various power states system.ruby.l2_cntrl0.L2cache.demand_hits 30 # Number of cache demand hits system.ruby.l2_cntrl0.L2cache.demand_misses 1461 # Number of cache demand misses system.ruby.l2_cntrl0.L2cache.demand_accesses 1491 # Number of cache demand accesses -system.ruby.l2_cntrl0.pwrStateResidencyTicks::UNDEFINED 121535 # Cumulative time (in ticks) in various power states +system.ruby.l2_cntrl0.pwrStateResidencyTicks::UNDEFINED 129075 # Cumulative time (in ticks) in various power states system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 121535 # Cumulative time (in ticks) in various power states -system.ruby.network.routers0.percent_links_utilized 4.310281 +system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 129075 # Cumulative time (in ticks) in various power states +system.ruby.network.routers0.percent_links_utilized 4.058493 system.ruby.network.routers0.msg_count.Control::0 1491 system.ruby.network.routers0.msg_count.Request_Control::2 1041 system.ruby.network.routers0.msg_count.Response_Data::1 1491 @@ -440,8 +451,8 @@ system.ruby.network.routers0.msg_bytes.Response_Control::2 6400 system.ruby.network.routers0.msg_bytes.Writeback_Data::0 10440 system.ruby.network.routers0.msg_bytes.Writeback_Data::1 10152 system.ruby.network.routers0.msg_bytes.Writeback_Control::0 2336 -system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 121535 # Cumulative time (in ticks) in various power states -system.ruby.network.routers1.percent_links_utilized 8.369194 +system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 129075 # Cumulative time (in ticks) in various power states +system.ruby.network.routers1.percent_links_utilized 7.880302 system.ruby.network.routers1.msg_count.Control::0 2952 system.ruby.network.routers1.msg_count.Request_Control::2 1041 system.ruby.network.routers1.msg_count.Response_Data::1 3229 @@ -458,16 +469,16 @@ system.ruby.network.routers1.msg_bytes.Response_Control::2 6400 system.ruby.network.routers1.msg_bytes.Writeback_Data::0 10440 system.ruby.network.routers1.msg_bytes.Writeback_Data::1 10152 system.ruby.network.routers1.msg_bytes.Writeback_Control::0 2336 -system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 121535 # Cumulative time (in ticks) in various power states -system.ruby.network.routers2.percent_links_utilized 4.058913 +system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 129075 # Cumulative time (in ticks) in various power states +system.ruby.network.routers2.percent_links_utilized 3.821809 system.ruby.network.routers2.msg_count.Control::0 1461 system.ruby.network.routers2.msg_count.Response_Data::1 1738 system.ruby.network.routers2.msg_count.Response_Control::1 2629 system.ruby.network.routers2.msg_bytes.Control::0 11688 system.ruby.network.routers2.msg_bytes.Response_Data::1 125136 system.ruby.network.routers2.msg_bytes.Response_Control::1 21032 -system.ruby.network.routers3.pwrStateResidencyTicks::UNDEFINED 121535 # Cumulative time (in ticks) in various power states -system.ruby.network.routers3.percent_links_utilized 5.579463 +system.ruby.network.routers3.pwrStateResidencyTicks::UNDEFINED 129075 # Cumulative time (in ticks) in various power states +system.ruby.network.routers3.percent_links_utilized 5.253535 system.ruby.network.routers3.msg_count.Control::0 2952 system.ruby.network.routers3.msg_count.Request_Control::2 1041 system.ruby.network.routers3.msg_count.Response_Data::1 3229 @@ -484,7 +495,7 @@ system.ruby.network.routers3.msg_bytes.Response_Control::2 6400 system.ruby.network.routers3.msg_bytes.Writeback_Data::0 10440 system.ruby.network.routers3.msg_bytes.Writeback_Data::1 10152 system.ruby.network.routers3.msg_bytes.Writeback_Control::0 2336 -system.ruby.network.pwrStateResidencyTicks::UNDEFINED 121535 # Cumulative time (in ticks) in various power states +system.ruby.network.pwrStateResidencyTicks::UNDEFINED 129075 # Cumulative time (in ticks) in various power states system.ruby.network.msg_count.Control 8856 system.ruby.network.msg_count.Request_Control 3123 system.ruby.network.msg_count.Response_Data 9687 @@ -497,15 +508,15 @@ system.ruby.network.msg_byte.Response_Data 697464 system.ruby.network.msg_byte.Response_Control 114384 system.ruby.network.msg_byte.Writeback_Data 61776 system.ruby.network.msg_byte.Writeback_Control 7008 -system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 121535 # Cumulative time (in ticks) in various power states -system.ruby.network.routers0.throttle0.link_utilization 6.128687 +system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 129075 # Cumulative time (in ticks) in various power states +system.ruby.network.routers0.throttle0.link_utilization 5.770676 system.ruby.network.routers0.throttle0.msg_count.Request_Control::2 1041 system.ruby.network.routers0.throttle0.msg_count.Response_Data::1 1491 system.ruby.network.routers0.throttle0.msg_count.Response_Control::1 437 system.ruby.network.routers0.throttle0.msg_bytes.Request_Control::2 8328 system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::1 107352 system.ruby.network.routers0.throttle0.msg_bytes.Response_Control::1 3496 -system.ruby.network.routers0.throttle1.link_utilization 2.491875 +system.ruby.network.routers0.throttle1.link_utilization 2.346310 system.ruby.network.routers0.throttle1.msg_count.Control::0 1491 system.ruby.network.routers0.throttle1.msg_count.Response_Control::1 900 system.ruby.network.routers0.throttle1.msg_count.Response_Control::2 800 @@ -518,7 +529,7 @@ system.ruby.network.routers0.throttle1.msg_bytes.Response_Control::2 640 system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::0 10440 system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::1 10152 system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::0 2336 -system.ruby.network.routers1.throttle0.link_utilization 8.499198 +system.ruby.network.routers1.throttle0.link_utilization 8.002712 system.ruby.network.routers1.throttle0.msg_count.Control::0 1491 system.ruby.network.routers1.throttle0.msg_count.Response_Data::1 1461 system.ruby.network.routers1.throttle0.msg_count.Response_Control::1 2353 @@ -533,7 +544,7 @@ system.ruby.network.routers1.throttle0.msg_bytes.Response_Control::2 640 system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::0 10440 system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::1 10152 system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::0 2336 -system.ruby.network.routers1.throttle1.link_utilization 8.239190 +system.ruby.network.routers1.throttle1.link_utilization 7.757893 system.ruby.network.routers1.throttle1.msg_count.Control::0 1461 system.ruby.network.routers1.throttle1.msg_count.Request_Control::2 1041 system.ruby.network.routers1.throttle1.msg_count.Response_Data::1 1768 @@ -542,26 +553,26 @@ system.ruby.network.routers1.throttle1.msg_bytes.Control::0 11688 system.ruby.network.routers1.throttle1.msg_bytes.Request_Control::2 8328 system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::1 127296 system.ruby.network.routers1.throttle1.msg_bytes.Response_Control::1 12904 -system.ruby.network.routers2.throttle0.link_utilization 2.110503 +system.ruby.network.routers2.throttle0.link_utilization 1.987217 system.ruby.network.routers2.throttle0.msg_count.Control::0 1461 system.ruby.network.routers2.throttle0.msg_count.Response_Data::1 277 system.ruby.network.routers2.throttle0.msg_count.Response_Control::1 1176 system.ruby.network.routers2.throttle0.msg_bytes.Control::0 11688 system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::1 19944 system.ruby.network.routers2.throttle0.msg_bytes.Response_Control::1 9408 -system.ruby.network.routers2.throttle1.link_utilization 6.007323 +system.ruby.network.routers2.throttle1.link_utilization 5.656401 system.ruby.network.routers2.throttle1.msg_count.Response_Data::1 1461 system.ruby.network.routers2.throttle1.msg_count.Response_Control::1 1453 system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::1 105192 system.ruby.network.routers2.throttle1.msg_bytes.Response_Control::1 11624 -system.ruby.network.routers3.throttle0.link_utilization 6.128687 +system.ruby.network.routers3.throttle0.link_utilization 5.770676 system.ruby.network.routers3.throttle0.msg_count.Request_Control::2 1041 system.ruby.network.routers3.throttle0.msg_count.Response_Data::1 1491 system.ruby.network.routers3.throttle0.msg_count.Response_Control::1 437 system.ruby.network.routers3.throttle0.msg_bytes.Request_Control::2 8328 system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::1 107352 system.ruby.network.routers3.throttle0.msg_bytes.Response_Control::1 3496 -system.ruby.network.routers3.throttle1.link_utilization 8.499198 +system.ruby.network.routers3.throttle1.link_utilization 8.002712 system.ruby.network.routers3.throttle1.msg_count.Control::0 1491 system.ruby.network.routers3.throttle1.msg_count.Response_Data::1 1461 system.ruby.network.routers3.throttle1.msg_count.Response_Control::1 2353 @@ -576,7 +587,7 @@ system.ruby.network.routers3.throttle1.msg_bytes.Response_Control::2 640 system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::0 10440 system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::1 10152 system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::0 2336 -system.ruby.network.routers3.throttle2.link_utilization 2.110503 +system.ruby.network.routers3.throttle2.link_utilization 1.987217 system.ruby.network.routers3.throttle2.msg_count.Control::0 1461 system.ruby.network.routers3.throttle2.msg_count.Response_Data::1 277 system.ruby.network.routers3.throttle2.msg_count.Response_Control::1 1176 @@ -593,9 +604,9 @@ system.ruby.delayVCHist.vnet_0::total 2728 # de system.ruby.delayVCHist.vnet_1::bucket_size 1 # delay histogram for vnet_1 system.ruby.delayVCHist.vnet_1::max_bucket 9 # delay histogram for vnet_1 system.ruby.delayVCHist.vnet_1::samples 5883 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::mean 0.072752 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::stdev 0.374480 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1 | 5669 96.36% 96.36% | 0 0.00% 96.36% | 214 3.64% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::mean 0.071392 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::stdev 0.371094 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1 | 5673 96.43% 96.43% | 0 0.00% 96.43% | 210 3.57% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1 system.ruby.delayVCHist.vnet_1::total 5883 # delay histogram for vnet_1 system.ruby.delayVCHist.vnet_2::bucket_size 1 # delay histogram for vnet_2 system.ruby.delayVCHist.vnet_2::max_bucket 9 # delay histogram for vnet_2 @@ -605,10 +616,10 @@ system.ruby.delayVCHist.vnet_2::total 1041 # de system.ruby.LD.latency_hist_seqr::bucket_size 64 system.ruby.LD.latency_hist_seqr::max_bucket 639 system.ruby.LD.latency_hist_seqr::samples 1185 -system.ruby.LD.latency_hist_seqr::mean 33.565401 -system.ruby.LD.latency_hist_seqr::gmean 7.686795 -system.ruby.LD.latency_hist_seqr::stdev 38.515936 -system.ruby.LD.latency_hist_seqr | 803 67.76% 67.76% | 378 31.90% 99.66% | 0 0.00% 99.66% | 0 0.00% 99.66% | 3 0.25% 99.92% | 1 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.latency_hist_seqr::mean 36.416034 +system.ruby.LD.latency_hist_seqr::gmean 7.907367 +system.ruby.LD.latency_hist_seqr::stdev 46.041898 +system.ruby.LD.latency_hist_seqr | 802 67.68% 67.68% | 375 31.65% 99.32% | 1 0.08% 99.41% | 0 0.00% 99.41% | 3 0.25% 99.66% | 3 0.25% 99.92% | 0 0.00% 99.92% | 0 0.00% 99.92% | 0 0.00% 99.92% | 1 0.08% 100.00% system.ruby.LD.latency_hist_seqr::total 1185 system.ruby.LD.hit_latency_hist_seqr::bucket_size 1 system.ruby.LD.hit_latency_hist_seqr::max_bucket 9 @@ -620,18 +631,18 @@ system.ruby.LD.hit_latency_hist_seqr::total 601 system.ruby.LD.miss_latency_hist_seqr::bucket_size 64 system.ruby.LD.miss_latency_hist_seqr::max_bucket 639 system.ruby.LD.miss_latency_hist_seqr::samples 584 -system.ruby.LD.miss_latency_hist_seqr::mean 67.078767 -system.ruby.LD.miss_latency_hist_seqr::gmean 62.700967 -system.ruby.LD.miss_latency_hist_seqr::stdev 28.185747 -system.ruby.LD.miss_latency_hist_seqr | 202 34.59% 34.59% | 378 64.73% 99.32% | 0 0.00% 99.32% | 0 0.00% 99.32% | 3 0.51% 99.83% | 1 0.17% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.miss_latency_hist_seqr::mean 72.863014 +system.ruby.LD.miss_latency_hist_seqr::gmean 66.405671 +system.ruby.LD.miss_latency_hist_seqr::stdev 41.005857 +system.ruby.LD.miss_latency_hist_seqr | 201 34.42% 34.42% | 375 64.21% 98.63% | 1 0.17% 98.80% | 0 0.00% 98.80% | 3 0.51% 99.32% | 3 0.51% 99.83% | 0 0.00% 99.83% | 0 0.00% 99.83% | 0 0.00% 99.83% | 1 0.17% 100.00% system.ruby.LD.miss_latency_hist_seqr::total 584 -system.ruby.ST.latency_hist_seqr::bucket_size 64 -system.ruby.ST.latency_hist_seqr::max_bucket 639 +system.ruby.ST.latency_hist_seqr::bucket_size 16 +system.ruby.ST.latency_hist_seqr::max_bucket 159 system.ruby.ST.latency_hist_seqr::samples 865 -system.ruby.ST.latency_hist_seqr::mean 15.551445 -system.ruby.ST.latency_hist_seqr::gmean 2.706248 -system.ruby.ST.latency_hist_seqr::stdev 29.831548 -system.ruby.ST.latency_hist_seqr | 773 89.36% 89.36% | 90 10.40% 99.77% | 0 0.00% 99.77% | 0 0.00% 99.77% | 1 0.12% 99.88% | 1 0.12% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.latency_hist_seqr::mean 15.646243 +system.ruby.ST.latency_hist_seqr::gmean 2.719887 +system.ruby.ST.latency_hist_seqr::stdev 27.764380 +system.ruby.ST.latency_hist_seqr | 649 75.03% 75.03% | 12 1.39% 76.42% | 101 11.68% 88.09% | 10 1.16% 89.25% | 36 4.16% 93.41% | 52 6.01% 99.42% | 4 0.46% 99.88% | 1 0.12% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ST.latency_hist_seqr::total 865 system.ruby.ST.hit_latency_hist_seqr::bucket_size 1 system.ruby.ST.hit_latency_hist_seqr::max_bucket 9 @@ -640,21 +651,21 @@ system.ruby.ST.hit_latency_hist_seqr::mean 1 system.ruby.ST.hit_latency_hist_seqr::gmean 1 system.ruby.ST.hit_latency_hist_seqr | 0 0.00% 0.00% | 649 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ST.hit_latency_hist_seqr::total 649 -system.ruby.ST.miss_latency_hist_seqr::bucket_size 64 -system.ruby.ST.miss_latency_hist_seqr::max_bucket 639 +system.ruby.ST.miss_latency_hist_seqr::bucket_size 16 +system.ruby.ST.miss_latency_hist_seqr::max_bucket 159 system.ruby.ST.miss_latency_hist_seqr::samples 216 -system.ruby.ST.miss_latency_hist_seqr::mean 59.273148 -system.ruby.ST.miss_latency_hist_seqr::gmean 53.885554 -system.ruby.ST.miss_latency_hist_seqr::stdev 31.884011 -system.ruby.ST.miss_latency_hist_seqr | 124 57.41% 57.41% | 90 41.67% 99.07% | 0 0.00% 99.07% | 0 0.00% 99.07% | 1 0.46% 99.54% | 1 0.46% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.miss_latency_hist_seqr::mean 59.652778 +system.ruby.ST.miss_latency_hist_seqr::gmean 54.981344 +system.ruby.ST.miss_latency_hist_seqr::stdev 22.464955 +system.ruby.ST.miss_latency_hist_seqr | 0 0.00% 0.00% | 12 5.56% 5.56% | 101 46.76% 52.31% | 10 4.63% 56.94% | 36 16.67% 73.61% | 52 24.07% 97.69% | 4 1.85% 99.54% | 1 0.46% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ST.miss_latency_hist_seqr::total 216 system.ruby.IFETCH.latency_hist_seqr::bucket_size 64 system.ruby.IFETCH.latency_hist_seqr::max_bucket 639 system.ruby.IFETCH.latency_hist_seqr::samples 6413 -system.ruby.IFETCH.latency_hist_seqr::mean 9.331826 -system.ruby.IFETCH.latency_hist_seqr::gmean 1.594079 -system.ruby.IFETCH.latency_hist_seqr::stdev 25.833878 -system.ruby.IFETCH.latency_hist_seqr | 5727 89.30% 89.30% | 673 10.49% 99.80% | 4 0.06% 99.86% | 1 0.02% 99.88% | 4 0.06% 99.94% | 4 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.latency_hist_seqr::mean 9.968034 +system.ruby.IFETCH.latency_hist_seqr::gmean 1.606700 +system.ruby.IFETCH.latency_hist_seqr::stdev 27.770381 +system.ruby.IFETCH.latency_hist_seqr | 5727 89.30% 89.30% | 674 10.51% 99.81% | 2 0.03% 99.84% | 1 0.02% 99.86% | 3 0.05% 99.91% | 6 0.09% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.latency_hist_seqr::total 6413 system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 1 system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 9 @@ -666,10 +677,10 @@ system.ruby.IFETCH.hit_latency_hist_seqr::total 5722 system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 64 system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 639 system.ruby.IFETCH.miss_latency_hist_seqr::samples 691 -system.ruby.IFETCH.miss_latency_hist_seqr::mean 78.325615 -system.ruby.IFETCH.miss_latency_hist_seqr::gmean 75.760449 -system.ruby.IFETCH.miss_latency_hist_seqr::stdev 29.311514 -system.ruby.IFETCH.miss_latency_hist_seqr | 5 0.72% 0.72% | 673 97.40% 98.12% | 4 0.58% 98.70% | 1 0.14% 98.84% | 4 0.58% 99.42% | 4 0.58% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.miss_latency_hist_seqr::mean 84.230101 +system.ruby.IFETCH.miss_latency_hist_seqr::gmean 81.513388 +system.ruby.IFETCH.miss_latency_hist_seqr::stdev 31.252511 +system.ruby.IFETCH.miss_latency_hist_seqr | 5 0.72% 0.72% | 674 97.54% 98.26% | 2 0.29% 98.55% | 1 0.14% 98.70% | 3 0.43% 99.13% | 6 0.87% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.miss_latency_hist_seqr::total 691 system.ruby.Directory_Controller.Fetch 1461 0.00% 0.00% system.ruby.Directory_Controller.Data 277 0.00% 0.00% diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini index 7127384c1..2e87336b3 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini @@ -14,6 +14,7 @@ children=clk_domain cpu dvfs_handler mem_ctrls ruby sys_port_proxy voltage_domai boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 exit_on_work_items=false init_param=0 @@ -22,11 +23,15 @@ kernel_addr_check=true load_addr_mask=1099511627775 load_offset=0 mem_mode=timing -mem_ranges=0:268435455 +mem_ranges=0:268435455:0:0:0:0 memories=system.mem_ctrls mmap_using_noreserve=false multi_thread=false num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null readfile= symbolfile= thermal_components= @@ -55,6 +60,7 @@ branchPred=Null checker=Null clk_domain=system.cpu.clk_domain cpu_id=0 +default_p_state=UNDEFINED do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true @@ -70,6 +76,10 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null profile=0 progress_interval=0 simpoint_start_insts= @@ -122,7 +132,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/hello/bin/alpha/linux/hello +executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin kvmInSE=false @@ -145,27 +155,27 @@ transition_latency=100000 [system.mem_ctrls] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -177,6 +187,7 @@ burst_length=8 channels=1 clk_domain=system.clk_domain conf_table_reported=true +default_p_state=UNDEFINED device_bus_width=8 device_rowbuffer_size=1024 device_size=536870912 @@ -184,12 +195,17 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 page_policy=open_adaptive -range=0:268435455 +power_model=Null +range=0:268435455:5:19:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10 @@ -211,9 +227,9 @@ tRTW=3 tWR=15 tWTR=8 tXAW=30 -tXP=0 +tXP=6 tXPDLL=0 -tXS=0 +tXS=270 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 @@ -227,12 +243,17 @@ access_backing_store=false all_instructions=false block_size_bytes=64 clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED eventq_index=0 hot_lines=false memory_size_bits=48 num_of_sequencers=1 number_of_virtual_networks=3 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 phys_mem=Null +power_model=Null randomization=false [system.ruby.clk_domain] @@ -249,11 +270,16 @@ children=directory forwardFromDir requestToDir responseFromDir responseFromMemor buffer_size=0 clk_domain=system.ruby.clk_domain cluster_id=0 +default_p_state=UNDEFINED directory=system.ruby.dir_cntrl0.directory directory_latency=6 eventq_index=0 forwardFromDir=system.ruby.dir_cntrl0.forwardFromDir number_of_TBEs=256 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null recycle_latency=10 requestToDir=system.ruby.dir_cntrl0.requestToDir responseFromDir=system.ruby.dir_cntrl0.responseFromDir @@ -320,10 +346,15 @@ L1Icache=system.ruby.l1_cntrl0.L1Icache buffer_size=0 clk_domain=system.cpu.clk_domain cluster_id=0 +default_p_state=UNDEFINED eventq_index=0 l2_select_num_bits=0 mandatoryQueue=system.ruby.l1_cntrl0.mandatoryQueue number_of_TBEs=256 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null recycle_latency=10 requestFromL1Cache=system.ruby.l1_cntrl0.requestFromL1Cache requestToL1Cache=system.ruby.l1_cntrl0.requestToL1Cache @@ -433,17 +464,22 @@ coreid=99 dcache=system.ruby.l1_cntrl0.L1Dcache dcache_hit_latency=1 deadlock_threshold=500000 +default_p_state=UNDEFINED eventq_index=0 +garnet_standalone=false icache=system.ruby.l1_cntrl0.L1Icache icache_hit_latency=1 is_cpu_sequencer=true max_outstanding_requests=16 no_retry_on_stall=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null ruby_system=system.ruby support_data_reqs=true support_inst_reqs=true system=system -using_network_tester=false using_ruby_tester=false version=0 slave=system.cpu.icache_port system.cpu.dcache_port @@ -466,8 +502,13 @@ L2cache=system.ruby.l2_cntrl0.L2cache buffer_size=0 clk_domain=system.ruby.clk_domain cluster_id=0 +default_p_state=UNDEFINED eventq_index=0 number_of_TBEs=256 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null recycle_latency=10 request_latency=2 responseFromL2Cache=system.ruby.l2_cntrl0.responseFromL2Cache @@ -566,18 +607,23 @@ eventq_index=0 [system.ruby.network] type=SimpleNetwork -children=ext_links0 ext_links1 ext_links2 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_links0 int_links1 int_links2 routers0 routers1 routers2 routers3 +children=ext_links0 ext_links1 ext_links2 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_link_buffers20 int_link_buffers21 int_link_buffers22 int_link_buffers23 int_link_buffers24 int_link_buffers25 int_link_buffers26 int_link_buffers27 int_link_buffers28 int_link_buffers29 int_link_buffers30 int_link_buffers31 int_link_buffers32 int_link_buffers33 int_link_buffers34 int_link_buffers35 int_links0 int_links1 int_links2 int_links3 int_links4 int_links5 routers0 routers1 routers2 routers3 adaptive_routing=false buffer_size=0 clk_domain=system.ruby.clk_domain control_msg_size=8 +default_p_state=UNDEFINED endpoint_bandwidth=1000 eventq_index=0 ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1 system.ruby.network.ext_links2 -int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 -int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2 +int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19 system.ruby.network.int_link_buffers20 system.ruby.network.int_link_buffers21 system.ruby.network.int_link_buffers22 system.ruby.network.int_link_buffers23 system.ruby.network.int_link_buffers24 system.ruby.network.int_link_buffers25 system.ruby.network.int_link_buffers26 system.ruby.network.int_link_buffers27 system.ruby.network.int_link_buffers28 system.ruby.network.int_link_buffers29 system.ruby.network.int_link_buffers30 system.ruby.network.int_link_buffers31 system.ruby.network.int_link_buffers32 system.ruby.network.int_link_buffers33 system.ruby.network.int_link_buffers34 system.ruby.network.int_link_buffers35 +int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2 system.ruby.network.int_links3 system.ruby.network.int_links4 system.ruby.network.int_links5 netifs= number_of_virtual_networks=3 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null routers=system.ruby.network.routers0 system.ruby.network.routers1 system.ruby.network.routers2 system.ruby.network.routers3 ruby_system=system.ruby topology=Crossbar @@ -740,42 +786,216 @@ eventq_index=0 ordered=true randomization=false +[system.ruby.network.int_link_buffers18] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers19] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers20] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers21] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers22] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers23] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers24] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers25] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers26] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers27] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers28] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers29] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers30] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers31] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers32] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers33] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers34] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers35] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + [system.ruby.network.int_links0] type=SimpleIntLink bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers3 eventq_index=0 latency=1 link_id=3 -node_a=system.ruby.network.routers0 -node_b=system.ruby.network.routers3 +src_node=system.ruby.network.routers0 +src_outport= weight=1 [system.ruby.network.int_links1] type=SimpleIntLink bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers3 eventq_index=0 latency=1 link_id=4 -node_a=system.ruby.network.routers1 -node_b=system.ruby.network.routers3 +src_node=system.ruby.network.routers1 +src_outport= weight=1 [system.ruby.network.int_links2] type=SimpleIntLink bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers3 eventq_index=0 latency=1 link_id=5 -node_a=system.ruby.network.routers2 -node_b=system.ruby.network.routers3 +src_node=system.ruby.network.routers2 +src_outport= +weight=1 + +[system.ruby.network.int_links3] +type=SimpleIntLink +bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers0 +eventq_index=0 +latency=1 +link_id=6 +src_node=system.ruby.network.routers3 +src_outport= +weight=1 + +[system.ruby.network.int_links4] +type=SimpleIntLink +bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers1 +eventq_index=0 +latency=1 +link_id=7 +src_node=system.ruby.network.routers3 +src_outport= +weight=1 + +[system.ruby.network.int_links5] +type=SimpleIntLink +bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers2 +eventq_index=0 +latency=1 +link_id=8 +src_node=system.ruby.network.routers3 +src_outport= weight=1 [system.ruby.network.routers0] type=Switch children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED eventq_index=0 +latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 port_buffers=system.ruby.network.routers0.port_buffers00 system.ruby.network.routers0.port_buffers01 system.ruby.network.routers0.port_buffers02 system.ruby.network.routers0.port_buffers03 system.ruby.network.routers0.port_buffers04 system.ruby.network.routers0.port_buffers05 system.ruby.network.routers0.port_buffers06 system.ruby.network.routers0.port_buffers07 system.ruby.network.routers0.port_buffers08 system.ruby.network.routers0.port_buffers09 system.ruby.network.routers0.port_buffers10 system.ruby.network.routers0.port_buffers11 +power_model=Null router_id=0 virt_nets=3 @@ -867,8 +1087,14 @@ randomization=false type=Switch children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED eventq_index=0 +latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 port_buffers=system.ruby.network.routers1.port_buffers00 system.ruby.network.routers1.port_buffers01 system.ruby.network.routers1.port_buffers02 system.ruby.network.routers1.port_buffers03 system.ruby.network.routers1.port_buffers04 system.ruby.network.routers1.port_buffers05 system.ruby.network.routers1.port_buffers06 system.ruby.network.routers1.port_buffers07 system.ruby.network.routers1.port_buffers08 system.ruby.network.routers1.port_buffers09 system.ruby.network.routers1.port_buffers10 system.ruby.network.routers1.port_buffers11 +power_model=Null router_id=1 virt_nets=3 @@ -960,8 +1186,14 @@ randomization=false type=Switch children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED eventq_index=0 +latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 port_buffers=system.ruby.network.routers2.port_buffers00 system.ruby.network.routers2.port_buffers01 system.ruby.network.routers2.port_buffers02 system.ruby.network.routers2.port_buffers03 system.ruby.network.routers2.port_buffers04 system.ruby.network.routers2.port_buffers05 system.ruby.network.routers2.port_buffers06 system.ruby.network.routers2.port_buffers07 system.ruby.network.routers2.port_buffers08 system.ruby.network.routers2.port_buffers09 system.ruby.network.routers2.port_buffers10 system.ruby.network.routers2.port_buffers11 +power_model=Null router_id=2 virt_nets=3 @@ -1053,8 +1285,14 @@ randomization=false type=Switch children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17 clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED eventq_index=0 +latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 port_buffers=system.ruby.network.routers3.port_buffers00 system.ruby.network.routers3.port_buffers01 system.ruby.network.routers3.port_buffers02 system.ruby.network.routers3.port_buffers03 system.ruby.network.routers3.port_buffers04 system.ruby.network.routers3.port_buffers05 system.ruby.network.routers3.port_buffers06 system.ruby.network.routers3.port_buffers07 system.ruby.network.routers3.port_buffers08 system.ruby.network.routers3.port_buffers09 system.ruby.network.routers3.port_buffers10 system.ruby.network.routers3.port_buffers11 system.ruby.network.routers3.port_buffers12 system.ruby.network.routers3.port_buffers13 system.ruby.network.routers3.port_buffers14 system.ruby.network.routers3.port_buffers15 system.ruby.network.routers3.port_buffers16 system.ruby.network.routers3.port_buffers17 +power_model=Null router_id=3 virt_nets=3 @@ -1187,9 +1425,14 @@ randomization=false [system.sys_port_proxy] type=RubyPortProxy clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 is_cpu_sequencer=true no_retry_on_stall=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null ruby_system=system.ruby support_data_reqs=true support_inst_reqs=true diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simerr b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simerr index ccfdd3697..f6f6f15a5 100755 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simerr +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simerr @@ -4,8 +4,7 @@ warn: rounding error > tolerance 1.250000 rounded to 1 warn: rounding error > tolerance 1.250000 rounded to 1 -warn: rounding error > tolerance - 1.250000 rounded to 1 warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes) warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files! diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout index c750cc80b..3faf7299f 100755 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout @@ -3,13 +3,13 @@ Redirecting stderr to build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hell gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 14 2016 22:01:23 -gem5 started Mar 14 2016 22:02:29 -gem5 executing on phenom, pid 29128 -command line: build/ALPHA_MOESI_CMP_directory/gem5.opt -d build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory +gem5 compiled Oct 13 2016 20:30:58 +gem5 started Oct 13 2016 20:31:25 +gem5 executing on e108600-lin, pid 17789 +command line: /work/curdun01/gem5-external.hg/build/ALPHA_MOESI_CMP_directory/gem5.opt -d build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 108878 because target called exit() +Exiting @ tick 115948 because target called exit() diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt index 99bf8d33d..0d7120e11 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000109 # Number of seconds simulated -sim_ticks 108878 # Number of ticks simulated -final_tick 108878 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000116 # Number of seconds simulated +sim_ticks 115948 # Number of ticks simulated +final_tick 115948 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 66441 # Simulator instruction rate (inst/s) -host_op_rate 66435 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1129573 # Simulator tick rate (ticks/s) -host_mem_usage 461124 # Number of bytes of host memory used +host_inst_rate 62775 # Simulator instruction rate (inst/s) +host_op_rate 62768 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1136521 # Simulator tick rate (ticks/s) +host_mem_usage 416956 # Number of bytes of host memory used host_seconds 0.10 # Real time elapsed on the host sim_insts 6403 # Number of instructions simulated sim_ops 6403 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks -system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 108878 # Cumulative time (in ticks) in various power states +system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 115948 # Cumulative time (in ticks) in various power states system.mem_ctrls.bytes_read::ruby.dir_cntrl0 75712 # Number of bytes read from this memory system.mem_ctrls.bytes_read::total 75712 # Number of bytes read from this memory system.mem_ctrls.bytes_written::ruby.dir_cntrl0 12416 # Number of bytes written to this memory @@ -22,29 +22,29 @@ system.mem_ctrls.num_reads::ruby.dir_cntrl0 1183 # system.mem_ctrls.num_reads::total 1183 # Number of read requests responded to by this memory system.mem_ctrls.num_writes::ruby.dir_cntrl0 194 # Number of write requests responded to by this memory system.mem_ctrls.num_writes::total 194 # Number of write requests responded to by this memory -system.mem_ctrls.bw_read::ruby.dir_cntrl0 695383824 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_read::total 695383824 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::ruby.dir_cntrl0 114035893 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::total 114035893 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_total::ruby.dir_cntrl0 809419717 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.bw_total::total 809419717 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_read::ruby.dir_cntrl0 652982371 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 652982371 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::ruby.dir_cntrl0 107082485 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::total 107082485 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::ruby.dir_cntrl0 760064857 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 760064857 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrls.readReqs 1183 # Number of read requests accepted system.mem_ctrls.writeReqs 194 # Number of write requests accepted system.mem_ctrls.readBursts 1183 # Number of DRAM read bursts, including those serviced by the write queue system.mem_ctrls.writeBursts 194 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrls.bytesReadDRAM 64576 # Total number of bytes read from DRAM -system.mem_ctrls.bytesReadWrQ 11136 # Total number of bytes read from write queue -system.mem_ctrls.bytesWritten 5504 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadDRAM 65152 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 10560 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 5440 # Total number of bytes written to DRAM system.mem_ctrls.bytesReadSys 75712 # Total read bytes from the system interface side system.mem_ctrls.bytesWrittenSys 12416 # Total written bytes from the system interface side -system.mem_ctrls.servicedByWrQ 174 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrls.mergedWrBursts 81 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.servicedByWrQ 165 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 79 # Number of DRAM write bursts merged with an existing one system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.mem_ctrls.perBankRdBursts::0 83 # Per bank write bursts system.mem_ctrls.perBankRdBursts::1 51 # Per bank write bursts system.mem_ctrls.perBankRdBursts::2 81 # Per bank write bursts system.mem_ctrls.perBankRdBursts::3 75 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::4 94 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 99 # Per bank write bursts system.mem_ctrls.perBankRdBursts::5 18 # Per bank write bursts system.mem_ctrls.perBankRdBursts::6 2 # Per bank write bursts system.mem_ctrls.perBankRdBursts::7 3 # Per bank write bursts @@ -53,15 +53,15 @@ system.mem_ctrls.perBankRdBursts::9 1 # Pe system.mem_ctrls.perBankRdBursts::10 56 # Per bank write bursts system.mem_ctrls.perBankRdBursts::11 51 # Per bank write bursts system.mem_ctrls.perBankRdBursts::12 21 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::13 365 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::14 67 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 367 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 69 # Per bank write bursts system.mem_ctrls.perBankRdBursts::15 41 # Per bank write bursts system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::4 18 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::5 6 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 19 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts @@ -69,12 +69,12 @@ system.mem_ctrls.perBankWrBursts::9 0 # Pe system.mem_ctrls.perBankWrBursts::10 3 # Per bank write bursts system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::13 18 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::14 41 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 20 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 43 # Per bank write bursts system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrls.totGap 108826 # Total gap between requests +system.mem_ctrls.totGap 115890 # Total gap between requests system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) @@ -89,7 +89,7 @@ system.mem_ctrls.writePktSize::3 0 # Wr system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::6 194 # Write request sizes (log2) -system.mem_ctrls.rdQLenPdf::0 1009 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::0 1018 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see @@ -136,21 +136,21 @@ system.mem_ctrls.wrQLenPdf::11 1 # Wh system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::15 4 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 3 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::16 4 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::17 4 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 6 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::18 6 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::19 6 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::20 6 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::21 6 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::22 6 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::23 7 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 6 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::24 6 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::25 6 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::26 7 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::27 5 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::28 5 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::29 5 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 6 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 6 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::28 6 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 6 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::30 5 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::31 5 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::32 5 # What write queue length does an incoming req see @@ -185,88 +185,99 @@ system.mem_ctrls.wrQLenPdf::60 0 # Wh system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrls.bytesPerActivate::samples 203 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::mean 334.817734 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::gmean 202.715946 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::stdev 328.878595 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::0-127 65 32.02% 32.02% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::128-255 47 23.15% 55.17% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::256-383 25 12.32% 67.49% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::384-511 11 5.42% 72.91% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::512-639 11 5.42% 78.33% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::640-767 10 4.93% 83.25% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::768-895 5 2.46% 85.71% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::896-1023 8 3.94% 89.66% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::1024-1151 21 10.34% 100.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::total 203 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::samples 208 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 330.153846 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 204.681326 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 325.358480 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 61 29.33% 29.33% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 54 25.96% 55.29% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 30 14.42% 69.71% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 9 4.33% 74.04% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 16 7.69% 81.73% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 5 2.40% 84.13% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 5 2.40% 86.54% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 4 1.92% 88.46% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 24 11.54% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 208 # Bytes accessed per row activation system.mem_ctrls.rdPerTurnAround::samples 5 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::mean 138.600000 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::gmean 101.703151 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::stdev 85.219129 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::mean 142.600000 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::gmean 108.227176 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::stdev 79.531755 # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::16-23 1 20.00% 20.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::80-87 1 20.00% 40.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::168-175 1 20.00% 60.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::192-199 1 20.00% 80.00% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::128-135 1 20.00% 40.00% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::136-143 1 20.00% 60.00% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::200-207 1 20.00% 80.00% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::216-223 1 20.00% 100.00% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::total 5 # Reads before turning the bus around for writes system.mem_ctrls.wrPerTurnAround::samples 5 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::mean 17.200000 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::gmean 17.171629 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::stdev 1.095445 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::mean 17 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::gmean 16.976446 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::stdev 1 # Writes before turning the bus around for reads system.mem_ctrls.wrPerTurnAround::16 2 40.00% 40.00% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::18 3 60.00% 100.00% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::17 1 20.00% 60.00% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::18 2 40.00% 100.00% # Writes before turning the bus around for reads system.mem_ctrls.wrPerTurnAround::total 5 # Writes before turning the bus around for reads -system.mem_ctrls.totQLat 7036 # Total ticks spent queuing -system.mem_ctrls.totMemAccLat 26207 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrls.totBusLat 5045 # Total ticks spent in databus transfers -system.mem_ctrls.avgQLat 6.97 # Average queueing delay per DRAM burst +system.mem_ctrls.totQLat 13845 # Total ticks spent queuing +system.mem_ctrls.totMemAccLat 33187 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.totBusLat 5090 # Total ticks spent in databus transfers +system.mem_ctrls.avgQLat 13.60 # Average queueing delay per DRAM burst system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst -system.mem_ctrls.avgMemAccLat 25.97 # Average memory access latency per DRAM burst -system.mem_ctrls.avgRdBW 593.10 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrls.avgWrBW 50.55 # Average achieved write bandwidth in MiByte/s -system.mem_ctrls.avgRdBWSys 695.38 # Average system read bandwidth in MiByte/s -system.mem_ctrls.avgWrBWSys 114.04 # Average system write bandwidth in MiByte/s +system.mem_ctrls.avgMemAccLat 32.60 # Average memory access latency per DRAM burst +system.mem_ctrls.avgRdBW 561.91 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 46.92 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 652.98 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 107.08 # Average system write bandwidth in MiByte/s system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrls.busUtil 5.03 # Data bus utilization in percentage -system.mem_ctrls.busUtilRead 4.63 # Data bus utilization in percentage for reads -system.mem_ctrls.busUtilWrite 0.39 # Data bus utilization in percentage for writes +system.mem_ctrls.busUtil 4.76 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 4.39 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 0.37 # Data bus utilization in percentage for writes system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing -system.mem_ctrls.avgWrQLen 21.05 # Average write queue length when enqueuing -system.mem_ctrls.readRowHits 806 # Number of row buffer hits during reads -system.mem_ctrls.writeRowHits 80 # Number of row buffer hits during writes -system.mem_ctrls.readRowHitRate 79.88 # Row buffer hit rate for reads -system.mem_ctrls.writeRowHitRate 70.80 # Row buffer hit rate for writes -system.mem_ctrls.avgGap 79.03 # Average gap between requests -system.mem_ctrls.pageHitRate 78.97 # Row buffer hit rate, read and write combined -system.mem_ctrls_0.actEnergy 529200 # Energy for activate commands per rank (pJ) -system.mem_ctrls_0.preEnergy 294000 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_0.readEnergy 5004480 # Energy for read commands per rank (pJ) -system.mem_ctrls_0.writeEnergy 248832 # Energy for write commands per rank (pJ) -system.mem_ctrls_0.refreshEnergy 6611280 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_0.actBackEnergy 61961508 # Energy for active background per rank (pJ) -system.mem_ctrls_0.preBackEnergy 6534600 # Energy for precharge background per rank (pJ) -system.mem_ctrls_0.totalEnergy 81183900 # Total energy per rank (pJ) -system.mem_ctrls_0.averagePower 800.014782 # Core power per rank (mW) -system.mem_ctrls_0.memoryStateTime::IDLE 16245 # Time in different power states -system.mem_ctrls_0.memoryStateTime::REF 3380 # Time in different power states -system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT 87571 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrls_1.actEnergy 907200 # Energy for activate commands per rank (pJ) -system.mem_ctrls_1.preEnergy 504000 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_1.readEnergy 6764160 # Energy for read commands per rank (pJ) -system.mem_ctrls_1.writeEnergy 642816 # Energy for write commands per rank (pJ) -system.mem_ctrls_1.refreshEnergy 6611280 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_1.actBackEnergy 67902048 # Energy for active background per rank (pJ) -system.mem_ctrls_1.preBackEnergy 1323600 # Energy for precharge background per rank (pJ) -system.mem_ctrls_1.totalEnergy 84655104 # Total energy per rank (pJ) -system.mem_ctrls_1.averagePower 834.221250 # Core power per rank (mW) -system.mem_ctrls_1.memoryStateTime::IDLE 1730 # Time in different power states -system.mem_ctrls_1.memoryStateTime::REF 3380 # Time in different power states -system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT 96382 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 108878 # Cumulative time (in ticks) in various power states +system.mem_ctrls.avgWrQLen 21.83 # Average write queue length when enqueuing +system.mem_ctrls.readRowHits 811 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 78 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 79.67 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate 67.83 # Row buffer hit rate for writes +system.mem_ctrls.avgGap 84.16 # Average gap between requests +system.mem_ctrls.pageHitRate 78.46 # Row buffer hit rate, read and write combined +system.mem_ctrls_0.actEnergy 528360 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 278208 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 4706688 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 158688 # Energy for write commands per rank (pJ) +system.mem_ctrls_0.refreshEnergy 9219600.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 8177904 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 299520 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.actPowerDownEnergy 33992976 # Energy for active power-down per rank (pJ) +system.mem_ctrls_0.prePowerDownEnergy 6547200 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls_0.selfRefreshEnergy 1905360 # Energy for self refresh per rank (pJ) +system.mem_ctrls_0.totalEnergy 65814504 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 567.620865 # Core power per rank (mW) +system.mem_ctrls_0.totalIdleTime 97183 # Total Idle time Per DRAM Rank +system.mem_ctrls_0.memoryStateTime::IDLE 354 # Time in different power states +system.mem_ctrls_0.memoryStateTime::REF 3906 # Time in different power states +system.mem_ctrls_0.memoryStateTime::SREF 5638 # Time in different power states +system.mem_ctrls_0.memoryStateTime::PRE_PDN 17050 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 14454 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT_PDN 74546 # Time in different power states +system.mem_ctrls_1.actEnergy 999600 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 525504 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 6922944 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 551232 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.refreshEnergy 8604960.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 10734696 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 319488 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.actPowerDownEnergy 40821120 # Energy for active power-down per rank (pJ) +system.mem_ctrls_1.prePowerDownEnergy 789120 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls_1.totalEnergy 70268664 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 606.036016 # Core power per rank (mW) +system.mem_ctrls_1.totalIdleTime 91295 # Total Idle time Per DRAM Rank +system.mem_ctrls_1.memoryStateTime::IDLE 272 # Time in different power states +system.mem_ctrls_1.memoryStateTime::REF 3640 # Time in different power states +system.mem_ctrls_1.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls_1.memoryStateTime::PRE_PDN 2055 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 20461 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT_PDN 89520 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 115948 # Cumulative time (in ticks) in various power states system.cpu.clk_domain.clock 1 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -301,8 +312,8 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 108878 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 108878 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 115948 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 115948 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 6403 # Number of instructions committed @@ -321,7 +332,7 @@ system.cpu.num_mem_refs 2060 # nu system.cpu.num_load_insts 1192 # Number of load instructions system.cpu.num_store_insts 868 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 108878 # Number of busy cycles +system.cpu.num_busy_cycles 115948 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 1056 # Number of branches fetched @@ -361,7 +372,7 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 6413 # Class of executed instruction system.ruby.clk_domain.clock 1 # Clock period in ticks -system.ruby.pwrStateResidencyTicks::UNDEFINED 108878 # Cumulative time (in ticks) in various power states +system.ruby.pwrStateResidencyTicks::UNDEFINED 115948 # Cumulative time (in ticks) in various power states system.ruby.outstanding_req_hist_seqr::bucket_size 1 system.ruby.outstanding_req_hist_seqr::max_bucket 9 system.ruby.outstanding_req_hist_seqr::samples 8464 @@ -372,10 +383,10 @@ system.ruby.outstanding_req_hist_seqr::total 8464 system.ruby.latency_hist_seqr::bucket_size 64 system.ruby.latency_hist_seqr::max_bucket 639 system.ruby.latency_hist_seqr::samples 8463 -system.ruby.latency_hist_seqr::mean 11.865178 -system.ruby.latency_hist_seqr::gmean 1.973283 -system.ruby.latency_hist_seqr::stdev 27.863065 -system.ruby.latency_hist_seqr | 7453 88.07% 88.07% | 995 11.76% 99.82% | 2 0.02% 99.85% | 0 0.00% 99.85% | 9 0.11% 99.95% | 4 0.05% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.latency_hist_seqr::mean 12.700579 +system.ruby.latency_hist_seqr::gmean 1.992540 +system.ruby.latency_hist_seqr::stdev 30.668579 +system.ruby.latency_hist_seqr | 7444 87.96% 87.96% | 1001 11.83% 99.79% | 3 0.04% 99.82% | 0 0.00% 99.82% | 6 0.07% 99.89% | 8 0.09% 99.99% | 0 0.00% 99.99% | 0 0.00% 99.99% | 0 0.00% 99.99% | 1 0.01% 100.00% system.ruby.latency_hist_seqr::total 8463 system.ruby.hit_latency_hist_seqr::bucket_size 1 system.ruby.hit_latency_hist_seqr::max_bucket 9 @@ -387,27 +398,27 @@ system.ruby.hit_latency_hist_seqr::total 7041 system.ruby.miss_latency_hist_seqr::bucket_size 64 system.ruby.miss_latency_hist_seqr::max_bucket 639 system.ruby.miss_latency_hist_seqr::samples 1422 -system.ruby.miss_latency_hist_seqr::mean 65.663854 -system.ruby.miss_latency_hist_seqr::gmean 57.123275 -system.ruby.miss_latency_hist_seqr::stdev 33.791401 -system.ruby.miss_latency_hist_seqr | 412 28.97% 28.97% | 995 69.97% 98.95% | 2 0.14% 99.09% | 0 0.00% 99.09% | 9 0.63% 99.72% | 4 0.28% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.miss_latency_hist_seqr::mean 70.635724 +system.ruby.miss_latency_hist_seqr::gmean 60.522119 +system.ruby.miss_latency_hist_seqr::stdev 39.545085 +system.ruby.miss_latency_hist_seqr | 403 28.34% 28.34% | 1001 70.39% 98.73% | 3 0.21% 98.95% | 0 0.00% 98.95% | 6 0.42% 99.37% | 8 0.56% 99.93% | 0 0.00% 99.93% | 0 0.00% 99.93% | 0 0.00% 99.93% | 1 0.07% 100.00% system.ruby.miss_latency_hist_seqr::total 1422 -system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 108878 # Cumulative time (in ticks) in various power states +system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 115948 # Cumulative time (in ticks) in various power states system.ruby.l1_cntrl0.L1Dcache.demand_hits 1274 # Number of cache demand hits system.ruby.l1_cntrl0.L1Dcache.demand_misses 776 # Number of cache demand misses system.ruby.l1_cntrl0.L1Dcache.demand_accesses 2050 # Number of cache demand accesses system.ruby.l1_cntrl0.L1Icache.demand_hits 5767 # Number of cache demand hits system.ruby.l1_cntrl0.L1Icache.demand_misses 646 # Number of cache demand misses system.ruby.l1_cntrl0.L1Icache.demand_accesses 6413 # Number of cache demand accesses -system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 108878 # Cumulative time (in ticks) in various power states -system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 108878 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 115948 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 115948 # Cumulative time (in ticks) in various power states system.ruby.l2_cntrl0.L2cache.demand_hits 239 # Number of cache demand hits system.ruby.l2_cntrl0.L2cache.demand_misses 1183 # Number of cache demand misses system.ruby.l2_cntrl0.L2cache.demand_accesses 1422 # Number of cache demand accesses -system.ruby.l2_cntrl0.pwrStateResidencyTicks::UNDEFINED 108878 # Cumulative time (in ticks) in various power states +system.ruby.l2_cntrl0.pwrStateResidencyTicks::UNDEFINED 115948 # Cumulative time (in ticks) in various power states system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 108878 # Cumulative time (in ticks) in various power states -system.ruby.network.routers0.percent_links_utilized 6.929545 +system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 115948 # Cumulative time (in ticks) in various power states +system.ruby.network.routers0.percent_links_utilized 6.507012 system.ruby.network.routers0.msg_count.Request_Control::0 1422 system.ruby.network.routers0.msg_count.Response_Data::2 1183 system.ruby.network.routers0.msg_count.ResponseL2hit_Data::2 239 @@ -420,8 +431,8 @@ system.ruby.network.routers0.msg_bytes.ResponseL2hit_Data::2 17208 system.ruby.network.routers0.msg_bytes.Writeback_Data::2 94248 system.ruby.network.routers0.msg_bytes.Writeback_Control::0 21680 system.ruby.network.routers0.msg_bytes.Unblock_Control::2 11744 -system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 108878 # Cumulative time (in ticks) in various power states -system.ruby.network.routers1.percent_links_utilized 10.407520 +system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 115948 # Cumulative time (in ticks) in various power states +system.ruby.network.routers1.percent_links_utilized 9.772915 system.ruby.network.routers1.msg_count.Request_Control::0 1422 system.ruby.network.routers1.msg_count.Request_Control::1 1183 system.ruby.network.routers1.msg_count.Response_Data::2 2366 @@ -438,8 +449,8 @@ system.ruby.network.routers1.msg_bytes.Writeback_Data::2 108216 system.ruby.network.routers1.msg_bytes.Writeback_Control::0 21680 system.ruby.network.routers1.msg_bytes.Writeback_Control::1 3104 system.ruby.network.routers1.msg_bytes.Unblock_Control::2 21208 -system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 108878 # Cumulative time (in ticks) in various power states -system.ruby.network.routers2.percent_links_utilized 3.477975 +system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 115948 # Cumulative time (in ticks) in various power states +system.ruby.network.routers2.percent_links_utilized 3.265904 system.ruby.network.routers2.msg_count.Request_Control::1 1183 system.ruby.network.routers2.msg_count.Response_Data::2 1183 system.ruby.network.routers2.msg_count.Writeback_Data::2 194 @@ -450,8 +461,8 @@ system.ruby.network.routers2.msg_bytes.Response_Data::2 85176 system.ruby.network.routers2.msg_bytes.Writeback_Data::2 13968 system.ruby.network.routers2.msg_bytes.Writeback_Control::1 3104 system.ruby.network.routers2.msg_bytes.Unblock_Control::2 9464 -system.ruby.network.routers3.pwrStateResidencyTicks::UNDEFINED 108878 # Cumulative time (in ticks) in various power states -system.ruby.network.routers3.percent_links_utilized 6.938347 +system.ruby.network.routers3.pwrStateResidencyTicks::UNDEFINED 115948 # Cumulative time (in ticks) in various power states +system.ruby.network.routers3.percent_links_utilized 6.515277 system.ruby.network.routers3.msg_count.Request_Control::0 1422 system.ruby.network.routers3.msg_count.Request_Control::1 1183 system.ruby.network.routers3.msg_count.Response_Data::2 2366 @@ -468,7 +479,7 @@ system.ruby.network.routers3.msg_bytes.Writeback_Data::2 108216 system.ruby.network.routers3.msg_bytes.Writeback_Control::0 21680 system.ruby.network.routers3.msg_bytes.Writeback_Control::1 3104 system.ruby.network.routers3.msg_bytes.Unblock_Control::2 21208 -system.ruby.network.pwrStateResidencyTicks::UNDEFINED 108878 # Cumulative time (in ticks) in various power states +system.ruby.network.pwrStateResidencyTicks::UNDEFINED 115948 # Cumulative time (in ticks) in various power states system.ruby.network.msg_count.Request_Control 7815 system.ruby.network.msg_count.Response_Data 7098 system.ruby.network.msg_count.ResponseL2hit_Data 717 @@ -481,15 +492,15 @@ system.ruby.network.msg_byte.ResponseL2hit_Data 51624 system.ruby.network.msg_byte.Writeback_Data 324648 system.ruby.network.msg_byte.Writeback_Control 74352 system.ruby.network.msg_byte.Unblock_Control 63624 -system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 108878 # Cumulative time (in ticks) in various power states -system.ruby.network.routers0.throttle0.link_utilization 6.499476 +system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 115948 # Cumulative time (in ticks) in various power states +system.ruby.network.routers0.throttle0.link_utilization 6.103167 system.ruby.network.routers0.throttle0.msg_count.Response_Data::2 1183 system.ruby.network.routers0.throttle0.msg_count.ResponseL2hit_Data::2 239 system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::0 1355 system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::2 85176 system.ruby.network.routers0.throttle0.msg_bytes.ResponseL2hit_Data::2 17208 system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::0 10840 -system.ruby.network.routers0.throttle1.link_utilization 7.359614 +system.ruby.network.routers0.throttle1.link_utilization 6.910857 system.ruby.network.routers0.throttle1.msg_count.Request_Control::0 1422 system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::2 1309 system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::0 1355 @@ -498,7 +509,7 @@ system.ruby.network.routers0.throttle1.msg_bytes.Request_Control::0 11376 system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::2 94248 system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::0 10840 system.ruby.network.routers0.throttle1.msg_bytes.Unblock_Control::2 11744 -system.ruby.network.routers1.throttle0.link_utilization 12.338122 +system.ruby.network.routers1.throttle0.link_utilization 11.585797 system.ruby.network.routers1.throttle0.msg_count.Request_Control::0 1422 system.ruby.network.routers1.throttle0.msg_count.Response_Data::2 1183 system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::2 1309 @@ -511,7 +522,7 @@ system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::2 94248 system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::0 10840 system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::1 1552 system.ruby.network.routers1.throttle0.msg_bytes.Unblock_Control::2 11744 -system.ruby.network.routers1.throttle1.link_utilization 8.476919 +system.ruby.network.routers1.throttle1.link_utilization 7.960034 system.ruby.network.routers1.throttle1.msg_count.Request_Control::1 1183 system.ruby.network.routers1.throttle1.msg_count.Response_Data::2 1183 system.ruby.network.routers1.throttle1.msg_count.ResponseL2hit_Data::2 239 @@ -526,7 +537,7 @@ system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Data::2 13968 system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::0 10840 system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::1 1552 system.ruby.network.routers1.throttle1.msg_bytes.Unblock_Control::2 9464 -system.ruby.network.routers2.throttle0.link_utilization 1.977443 +system.ruby.network.routers2.throttle0.link_utilization 1.856867 system.ruby.network.routers2.throttle0.msg_count.Request_Control::1 1183 system.ruby.network.routers2.throttle0.msg_count.Writeback_Data::2 194 system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::1 194 @@ -535,19 +546,19 @@ system.ruby.network.routers2.throttle0.msg_bytes.Request_Control::1 9464 system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Data::2 13968 system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::1 1552 system.ruby.network.routers2.throttle0.msg_bytes.Unblock_Control::2 9464 -system.ruby.network.routers2.throttle1.link_utilization 4.978508 +system.ruby.network.routers2.throttle1.link_utilization 4.674940 system.ruby.network.routers2.throttle1.msg_count.Response_Data::2 1183 system.ruby.network.routers2.throttle1.msg_count.Writeback_Control::1 194 system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::2 85176 system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Control::1 1552 -system.ruby.network.routers3.throttle0.link_utilization 6.499476 +system.ruby.network.routers3.throttle0.link_utilization 6.103167 system.ruby.network.routers3.throttle0.msg_count.Response_Data::2 1183 system.ruby.network.routers3.throttle0.msg_count.ResponseL2hit_Data::2 239 system.ruby.network.routers3.throttle0.msg_count.Writeback_Control::0 1355 system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::2 85176 system.ruby.network.routers3.throttle0.msg_bytes.ResponseL2hit_Data::2 17208 system.ruby.network.routers3.throttle0.msg_bytes.Writeback_Control::0 10840 -system.ruby.network.routers3.throttle1.link_utilization 12.338122 +system.ruby.network.routers3.throttle1.link_utilization 11.585797 system.ruby.network.routers3.throttle1.msg_count.Request_Control::0 1422 system.ruby.network.routers3.throttle1.msg_count.Response_Data::2 1183 system.ruby.network.routers3.throttle1.msg_count.Writeback_Data::2 1309 @@ -560,7 +571,7 @@ system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::2 94248 system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::0 10840 system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::1 1552 system.ruby.network.routers3.throttle1.msg_bytes.Unblock_Control::2 11744 -system.ruby.network.routers3.throttle2.link_utilization 1.977443 +system.ruby.network.routers3.throttle2.link_utilization 1.856867 system.ruby.network.routers3.throttle2.msg_count.Request_Control::1 1183 system.ruby.network.routers3.throttle2.msg_count.Writeback_Data::2 194 system.ruby.network.routers3.throttle2.msg_count.Writeback_Control::1 194 @@ -569,13 +580,13 @@ system.ruby.network.routers3.throttle2.msg_bytes.Request_Control::1 9464 system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Data::2 13968 system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Control::1 1552 system.ruby.network.routers3.throttle2.msg_bytes.Unblock_Control::2 9464 -system.ruby.LD.latency_hist_seqr::bucket_size 32 -system.ruby.LD.latency_hist_seqr::max_bucket 319 +system.ruby.LD.latency_hist_seqr::bucket_size 64 +system.ruby.LD.latency_hist_seqr::max_bucket 639 system.ruby.LD.latency_hist_seqr::samples 1185 -system.ruby.LD.latency_hist_seqr::mean 27.428692 -system.ruby.LD.latency_hist_seqr::gmean 5.747000 -system.ruby.LD.latency_hist_seqr::stdev 36.091782 -system.ruby.LD.latency_hist_seqr | 775 65.40% 65.40% | 87 7.34% 72.74% | 279 23.54% 96.29% | 40 3.38% 99.66% | 1 0.08% 99.75% | 1 0.08% 99.83% | 0 0.00% 99.83% | 0 0.00% 99.83% | 1 0.08% 99.92% | 1 0.08% 100.00% +system.ruby.LD.latency_hist_seqr::mean 29.289451 +system.ruby.LD.latency_hist_seqr::gmean 5.875383 +system.ruby.LD.latency_hist_seqr::stdev 39.627102 +system.ruby.LD.latency_hist_seqr | 857 72.32% 72.32% | 323 27.26% 99.58% | 2 0.17% 99.75% | 0 0.00% 99.75% | 1 0.08% 99.83% | 2 0.17% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.latency_hist_seqr::total 1185 system.ruby.LD.hit_latency_hist_seqr::bucket_size 1 system.ruby.LD.hit_latency_hist_seqr::max_bucket 9 @@ -584,21 +595,21 @@ system.ruby.LD.hit_latency_hist_seqr::mean 1 system.ruby.LD.hit_latency_hist_seqr::gmean 1 system.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 659 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.hit_latency_hist_seqr::total 659 -system.ruby.LD.miss_latency_hist_seqr::bucket_size 32 -system.ruby.LD.miss_latency_hist_seqr::max_bucket 319 +system.ruby.LD.miss_latency_hist_seqr::bucket_size 64 +system.ruby.LD.miss_latency_hist_seqr::max_bucket 639 system.ruby.LD.miss_latency_hist_seqr::samples 526 -system.ruby.LD.miss_latency_hist_seqr::mean 60.539924 -system.ruby.LD.miss_latency_hist_seqr::gmean 51.393520 -system.ruby.LD.miss_latency_hist_seqr::stdev 31.024435 -system.ruby.LD.miss_latency_hist_seqr | 116 22.05% 22.05% | 87 16.54% 38.59% | 279 53.04% 91.63% | 40 7.60% 99.24% | 1 0.19% 99.43% | 1 0.19% 99.62% | 0 0.00% 99.62% | 0 0.00% 99.62% | 1 0.19% 99.81% | 1 0.19% 100.00% +system.ruby.LD.miss_latency_hist_seqr::mean 64.731939 +system.ruby.LD.miss_latency_hist_seqr::gmean 54.016248 +system.ruby.LD.miss_latency_hist_seqr::stdev 35.753260 +system.ruby.LD.miss_latency_hist_seqr | 198 37.64% 37.64% | 323 61.41% 99.05% | 2 0.38% 99.43% | 0 0.00% 99.43% | 1 0.19% 99.62% | 2 0.38% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.miss_latency_hist_seqr::total 526 system.ruby.ST.latency_hist_seqr::bucket_size 64 system.ruby.ST.latency_hist_seqr::max_bucket 639 system.ruby.ST.latency_hist_seqr::samples 865 -system.ruby.ST.latency_hist_seqr::mean 17.057803 -system.ruby.ST.latency_hist_seqr::gmean 3.071194 -system.ruby.ST.latency_hist_seqr::stdev 31.094076 -system.ruby.ST.latency_hist_seqr | 753 87.05% 87.05% | 110 12.72% 99.77% | 0 0.00% 99.77% | 0 0.00% 99.77% | 1 0.12% 99.88% | 1 0.12% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.latency_hist_seqr::mean 17.729480 +system.ruby.ST.latency_hist_seqr::gmean 3.104775 +system.ruby.ST.latency_hist_seqr::stdev 31.273004 +system.ruby.ST.latency_hist_seqr | 749 86.59% 86.59% | 115 13.29% 99.88% | 0 0.00% 99.88% | 0 0.00% 99.88% | 0 0.00% 99.88% | 1 0.12% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ST.latency_hist_seqr::total 865 system.ruby.ST.hit_latency_hist_seqr::bucket_size 1 system.ruby.ST.hit_latency_hist_seqr::max_bucket 9 @@ -610,18 +621,18 @@ system.ruby.ST.hit_latency_hist_seqr::total 615 system.ruby.ST.miss_latency_hist_seqr::bucket_size 64 system.ruby.ST.miss_latency_hist_seqr::max_bucket 639 system.ruby.ST.miss_latency_hist_seqr::samples 250 -system.ruby.ST.miss_latency_hist_seqr::mean 56.560000 -system.ruby.ST.miss_latency_hist_seqr::gmean 48.538116 -system.ruby.ST.miss_latency_hist_seqr::stdev 33.930333 -system.ruby.ST.miss_latency_hist_seqr | 138 55.20% 55.20% | 110 44.00% 99.20% | 0 0.00% 99.20% | 0 0.00% 99.20% | 1 0.40% 99.60% | 1 0.40% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.miss_latency_hist_seqr::mean 58.884000 +system.ruby.ST.miss_latency_hist_seqr::gmean 50.399294 +system.ruby.ST.miss_latency_hist_seqr::stdev 31.651062 +system.ruby.ST.miss_latency_hist_seqr | 134 53.60% 53.60% | 115 46.00% 99.60% | 0 0.00% 99.60% | 0 0.00% 99.60% | 0 0.00% 99.60% | 1 0.40% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ST.miss_latency_hist_seqr::total 250 system.ruby.IFETCH.latency_hist_seqr::bucket_size 64 system.ruby.IFETCH.latency_hist_seqr::max_bucket 639 system.ruby.IFETCH.latency_hist_seqr::samples 6413 -system.ruby.IFETCH.latency_hist_seqr::mean 8.288944 -system.ruby.IFETCH.latency_hist_seqr::gmean 1.525778 -system.ruby.IFETCH.latency_hist_seqr::stdev 24.342417 -system.ruby.IFETCH.latency_hist_seqr | 5838 91.03% 91.03% | 566 8.83% 99.86% | 0 0.00% 99.86% | 0 0.00% 99.86% | 6 0.09% 99.95% | 3 0.05% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.latency_hist_seqr::mean 8.956962 +system.ruby.IFETCH.latency_hist_seqr::gmean 1.536905 +system.ruby.IFETCH.latency_hist_seqr::stdev 27.408738 +system.ruby.IFETCH.latency_hist_seqr | 5838 91.03% 91.03% | 563 8.78% 99.81% | 1 0.02% 99.83% | 0 0.00% 99.83% | 5 0.08% 99.91% | 5 0.08% 99.98% | 0 0.00% 99.98% | 0 0.00% 99.98% | 0 0.00% 99.98% | 1 0.02% 100.00% system.ruby.IFETCH.latency_hist_seqr::total 6413 system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 1 system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 9 @@ -633,10 +644,10 @@ system.ruby.IFETCH.hit_latency_hist_seqr::total 5767 system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 64 system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 639 system.ruby.IFETCH.miss_latency_hist_seqr::samples 646 -system.ruby.IFETCH.miss_latency_hist_seqr::mean 73.359133 -system.ruby.IFETCH.miss_latency_hist_seqr::gmean 66.307554 -system.ruby.IFETCH.miss_latency_hist_seqr::stdev 34.276818 -system.ruby.IFETCH.miss_latency_hist_seqr | 71 10.99% 10.99% | 566 87.62% 98.61% | 0 0.00% 98.61% | 0 0.00% 98.61% | 6 0.93% 99.54% | 3 0.46% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.miss_latency_hist_seqr::mean 79.990712 +system.ruby.IFETCH.miss_latency_hist_seqr::gmean 71.267502 +system.ruby.IFETCH.miss_latency_hist_seqr::stdev 42.993310 +system.ruby.IFETCH.miss_latency_hist_seqr | 71 10.99% 10.99% | 563 87.15% 98.14% | 1 0.15% 98.30% | 0 0.00% 98.30% | 5 0.77% 99.07% | 5 0.77% 99.85% | 0 0.00% 99.85% | 0 0.00% 99.85% | 0 0.00% 99.85% | 1 0.15% 100.00% system.ruby.IFETCH.miss_latency_hist_seqr::total 646 system.ruby.Directory_Controller.GETX 198 0.00% 0.00% system.ruby.Directory_Controller.GETS 985 0.00% 0.00% diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini index 072c6d45b..c3c3a350f 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini @@ -14,6 +14,7 @@ children=clk_domain cpu dvfs_handler mem_ctrls ruby sys_port_proxy voltage_domai boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 exit_on_work_items=false init_param=0 @@ -22,11 +23,15 @@ kernel_addr_check=true load_addr_mask=1099511627775 load_offset=0 mem_mode=timing -mem_ranges=0:268435455 +mem_ranges=0:268435455:0:0:0:0 memories=system.mem_ctrls mmap_using_noreserve=false multi_thread=false num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null readfile= symbolfile= thermal_components= @@ -55,6 +60,7 @@ branchPred=Null checker=Null clk_domain=system.cpu.clk_domain cpu_id=0 +default_p_state=UNDEFINED do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true @@ -70,6 +76,10 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null profile=0 progress_interval=0 simpoint_start_insts= @@ -122,7 +132,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/hello/bin/alpha/linux/hello +executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin kvmInSE=false @@ -145,27 +155,27 @@ transition_latency=100000 [system.mem_ctrls] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -177,6 +187,7 @@ burst_length=8 channels=1 clk_domain=system.clk_domain conf_table_reported=true +default_p_state=UNDEFINED device_bus_width=8 device_rowbuffer_size=1024 device_size=536870912 @@ -184,12 +195,17 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 page_policy=open_adaptive -range=0:268435455 +power_model=Null +range=0:268435455:5:19:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10 @@ -211,9 +227,9 @@ tRTW=3 tWR=15 tWTR=8 tXAW=30 -tXP=0 +tXP=6 tXPDLL=0 -tXS=0 +tXS=270 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 @@ -227,12 +243,17 @@ access_backing_store=false all_instructions=false block_size_bytes=64 clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED eventq_index=0 hot_lines=false memory_size_bits=48 num_of_sequencers=1 number_of_virtual_networks=6 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 phys_mem=Null +power_model=Null randomization=false [system.ruby.clk_domain] @@ -249,6 +270,7 @@ children=directory dmaRequestToDir dmaResponseFromDir persistentFromDir persiste buffer_size=0 clk_domain=system.ruby.clk_domain cluster_id=0 +default_p_state=UNDEFINED directory=system.ruby.dir_cntrl0.directory directory_latency=5 distributed_persistent=true @@ -258,8 +280,12 @@ eventq_index=0 fixed_timeout_latency=100 l2_select_num_bits=0 number_of_TBEs=256 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 persistentFromDir=system.ruby.dir_cntrl0.persistentFromDir persistentToDir=system.ruby.dir_cntrl0.persistentToDir +power_model=Null recycle_latency=10 reissue_wakeup_latency=10 requestFromDir=system.ruby.dir_cntrl0.requestFromDir @@ -361,6 +387,7 @@ N_tokens=2 buffer_size=0 clk_domain=system.cpu.clk_domain cluster_id=0 +default_p_state=UNDEFINED dynamic_timeout_enabled=true eventq_index=0 fixed_timeout_latency=300 @@ -370,8 +397,12 @@ l2_select_num_bits=0 mandatoryQueue=system.ruby.l1_cntrl0.mandatoryQueue no_mig_atomic=true number_of_TBEs=256 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 persistentFromL1Cache=system.ruby.l1_cntrl0.persistentFromL1Cache persistentToL1Cache=system.ruby.l1_cntrl0.persistentToL1Cache +power_model=Null recycle_latency=10 reissue_wakeup_latency=10 requestFromL1Cache=system.ruby.l1_cntrl0.requestFromL1Cache @@ -497,17 +528,22 @@ coreid=99 dcache=system.ruby.l1_cntrl0.L1Dcache dcache_hit_latency=1 deadlock_threshold=500000 +default_p_state=UNDEFINED eventq_index=0 +garnet_standalone=false icache=system.ruby.l1_cntrl0.L1Icache icache_hit_latency=1 is_cpu_sequencer=true max_outstanding_requests=16 no_retry_on_stall=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null ruby_system=system.ruby support_data_reqs=true support_inst_reqs=true system=system -using_network_tester=false using_ruby_tester=false version=0 slave=system.cpu.icache_port system.cpu.dcache_port @@ -524,12 +560,17 @@ N_tokens=2 buffer_size=0 clk_domain=system.ruby.clk_domain cluster_id=0 +default_p_state=UNDEFINED eventq_index=0 filtering_enabled=true l2_request_latency=5 l2_response_latency=5 number_of_TBEs=256 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 persistentToL2Cache=system.ruby.l2_cntrl0.persistentToL2Cache +power_model=Null recycle_latency=10 responseFromL2Cache=system.ruby.l2_cntrl0.responseFromL2Cache responseToL2Cache=system.ruby.l2_cntrl0.responseToL2Cache @@ -626,18 +667,23 @@ eventq_index=0 [system.ruby.network] type=SimpleNetwork -children=ext_links0 ext_links1 ext_links2 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_link_buffers20 int_link_buffers21 int_link_buffers22 int_link_buffers23 int_link_buffers24 int_link_buffers25 int_link_buffers26 int_link_buffers27 int_link_buffers28 int_link_buffers29 int_link_buffers30 int_link_buffers31 int_link_buffers32 int_link_buffers33 int_link_buffers34 int_link_buffers35 int_links0 int_links1 int_links2 routers0 routers1 routers2 routers3 +children=ext_links0 ext_links1 ext_links2 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_link_buffers20 int_link_buffers21 int_link_buffers22 int_link_buffers23 int_link_buffers24 int_link_buffers25 int_link_buffers26 int_link_buffers27 int_link_buffers28 int_link_buffers29 int_link_buffers30 int_link_buffers31 int_link_buffers32 int_link_buffers33 int_link_buffers34 int_link_buffers35 int_link_buffers36 int_link_buffers37 int_link_buffers38 int_link_buffers39 int_link_buffers40 int_link_buffers41 int_link_buffers42 int_link_buffers43 int_link_buffers44 int_link_buffers45 int_link_buffers46 int_link_buffers47 int_link_buffers48 int_link_buffers49 int_link_buffers50 int_link_buffers51 int_link_buffers52 int_link_buffers53 int_link_buffers54 int_link_buffers55 int_link_buffers56 int_link_buffers57 int_link_buffers58 int_link_buffers59 int_link_buffers60 int_link_buffers61 int_link_buffers62 int_link_buffers63 int_link_buffers64 int_link_buffers65 int_link_buffers66 int_link_buffers67 int_link_buffers68 int_link_buffers69 int_link_buffers70 int_link_buffers71 int_links0 int_links1 int_links2 int_links3 int_links4 int_links5 routers0 routers1 routers2 routers3 adaptive_routing=false buffer_size=0 clk_domain=system.ruby.clk_domain control_msg_size=8 +default_p_state=UNDEFINED endpoint_bandwidth=1000 eventq_index=0 ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1 system.ruby.network.ext_links2 -int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19 system.ruby.network.int_link_buffers20 system.ruby.network.int_link_buffers21 system.ruby.network.int_link_buffers22 system.ruby.network.int_link_buffers23 system.ruby.network.int_link_buffers24 system.ruby.network.int_link_buffers25 system.ruby.network.int_link_buffers26 system.ruby.network.int_link_buffers27 system.ruby.network.int_link_buffers28 system.ruby.network.int_link_buffers29 system.ruby.network.int_link_buffers30 system.ruby.network.int_link_buffers31 system.ruby.network.int_link_buffers32 system.ruby.network.int_link_buffers33 system.ruby.network.int_link_buffers34 system.ruby.network.int_link_buffers35 -int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2 +int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19 system.ruby.network.int_link_buffers20 system.ruby.network.int_link_buffers21 system.ruby.network.int_link_buffers22 system.ruby.network.int_link_buffers23 system.ruby.network.int_link_buffers24 system.ruby.network.int_link_buffers25 system.ruby.network.int_link_buffers26 system.ruby.network.int_link_buffers27 system.ruby.network.int_link_buffers28 system.ruby.network.int_link_buffers29 system.ruby.network.int_link_buffers30 system.ruby.network.int_link_buffers31 system.ruby.network.int_link_buffers32 system.ruby.network.int_link_buffers33 system.ruby.network.int_link_buffers34 system.ruby.network.int_link_buffers35 system.ruby.network.int_link_buffers36 system.ruby.network.int_link_buffers37 system.ruby.network.int_link_buffers38 system.ruby.network.int_link_buffers39 system.ruby.network.int_link_buffers40 system.ruby.network.int_link_buffers41 system.ruby.network.int_link_buffers42 system.ruby.network.int_link_buffers43 system.ruby.network.int_link_buffers44 system.ruby.network.int_link_buffers45 system.ruby.network.int_link_buffers46 system.ruby.network.int_link_buffers47 system.ruby.network.int_link_buffers48 system.ruby.network.int_link_buffers49 system.ruby.network.int_link_buffers50 system.ruby.network.int_link_buffers51 system.ruby.network.int_link_buffers52 system.ruby.network.int_link_buffers53 system.ruby.network.int_link_buffers54 system.ruby.network.int_link_buffers55 system.ruby.network.int_link_buffers56 system.ruby.network.int_link_buffers57 system.ruby.network.int_link_buffers58 system.ruby.network.int_link_buffers59 system.ruby.network.int_link_buffers60 system.ruby.network.int_link_buffers61 system.ruby.network.int_link_buffers62 system.ruby.network.int_link_buffers63 system.ruby.network.int_link_buffers64 system.ruby.network.int_link_buffers65 system.ruby.network.int_link_buffers66 system.ruby.network.int_link_buffers67 system.ruby.network.int_link_buffers68 system.ruby.network.int_link_buffers69 system.ruby.network.int_link_buffers70 system.ruby.network.int_link_buffers71 +int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2 system.ruby.network.int_links3 system.ruby.network.int_links4 system.ruby.network.int_links5 netifs= number_of_virtual_networks=6 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null routers=system.ruby.network.routers0 system.ruby.network.routers1 system.ruby.network.routers2 system.ruby.network.routers3 ruby_system=system.ruby topology=Crossbar @@ -926,42 +972,342 @@ eventq_index=0 ordered=true randomization=false +[system.ruby.network.int_link_buffers36] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers37] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers38] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers39] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers40] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers41] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers42] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers43] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers44] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers45] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers46] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers47] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers48] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers49] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers50] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers51] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers52] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers53] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers54] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers55] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers56] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers57] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers58] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers59] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers60] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers61] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers62] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers63] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers64] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers65] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers66] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers67] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers68] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers69] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers70] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers71] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + [system.ruby.network.int_links0] type=SimpleIntLink bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers3 eventq_index=0 latency=1 link_id=3 -node_a=system.ruby.network.routers0 -node_b=system.ruby.network.routers3 +src_node=system.ruby.network.routers0 +src_outport= weight=1 [system.ruby.network.int_links1] type=SimpleIntLink bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers3 eventq_index=0 latency=1 link_id=4 -node_a=system.ruby.network.routers1 -node_b=system.ruby.network.routers3 +src_node=system.ruby.network.routers1 +src_outport= weight=1 [system.ruby.network.int_links2] type=SimpleIntLink bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers3 eventq_index=0 latency=1 link_id=5 -node_a=system.ruby.network.routers2 -node_b=system.ruby.network.routers3 +src_node=system.ruby.network.routers2 +src_outport= +weight=1 + +[system.ruby.network.int_links3] +type=SimpleIntLink +bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers0 +eventq_index=0 +latency=1 +link_id=6 +src_node=system.ruby.network.routers3 +src_outport= +weight=1 + +[system.ruby.network.int_links4] +type=SimpleIntLink +bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers1 +eventq_index=0 +latency=1 +link_id=7 +src_node=system.ruby.network.routers3 +src_outport= +weight=1 + +[system.ruby.network.int_links5] +type=SimpleIntLink +bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers2 +eventq_index=0 +latency=1 +link_id=8 +src_node=system.ruby.network.routers3 +src_outport= weight=1 [system.ruby.network.routers0] type=Switch children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17 port_buffers18 port_buffers19 port_buffers20 port_buffers21 port_buffers22 port_buffers23 clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED eventq_index=0 +latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 port_buffers=system.ruby.network.routers0.port_buffers00 system.ruby.network.routers0.port_buffers01 system.ruby.network.routers0.port_buffers02 system.ruby.network.routers0.port_buffers03 system.ruby.network.routers0.port_buffers04 system.ruby.network.routers0.port_buffers05 system.ruby.network.routers0.port_buffers06 system.ruby.network.routers0.port_buffers07 system.ruby.network.routers0.port_buffers08 system.ruby.network.routers0.port_buffers09 system.ruby.network.routers0.port_buffers10 system.ruby.network.routers0.port_buffers11 system.ruby.network.routers0.port_buffers12 system.ruby.network.routers0.port_buffers13 system.ruby.network.routers0.port_buffers14 system.ruby.network.routers0.port_buffers15 system.ruby.network.routers0.port_buffers16 system.ruby.network.routers0.port_buffers17 system.ruby.network.routers0.port_buffers18 system.ruby.network.routers0.port_buffers19 system.ruby.network.routers0.port_buffers20 system.ruby.network.routers0.port_buffers21 system.ruby.network.routers0.port_buffers22 system.ruby.network.routers0.port_buffers23 +power_model=Null router_id=0 virt_nets=6 @@ -1137,8 +1483,14 @@ randomization=false type=Switch children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17 port_buffers18 port_buffers19 port_buffers20 port_buffers21 port_buffers22 port_buffers23 clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED eventq_index=0 +latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 port_buffers=system.ruby.network.routers1.port_buffers00 system.ruby.network.routers1.port_buffers01 system.ruby.network.routers1.port_buffers02 system.ruby.network.routers1.port_buffers03 system.ruby.network.routers1.port_buffers04 system.ruby.network.routers1.port_buffers05 system.ruby.network.routers1.port_buffers06 system.ruby.network.routers1.port_buffers07 system.ruby.network.routers1.port_buffers08 system.ruby.network.routers1.port_buffers09 system.ruby.network.routers1.port_buffers10 system.ruby.network.routers1.port_buffers11 system.ruby.network.routers1.port_buffers12 system.ruby.network.routers1.port_buffers13 system.ruby.network.routers1.port_buffers14 system.ruby.network.routers1.port_buffers15 system.ruby.network.routers1.port_buffers16 system.ruby.network.routers1.port_buffers17 system.ruby.network.routers1.port_buffers18 system.ruby.network.routers1.port_buffers19 system.ruby.network.routers1.port_buffers20 system.ruby.network.routers1.port_buffers21 system.ruby.network.routers1.port_buffers22 system.ruby.network.routers1.port_buffers23 +power_model=Null router_id=1 virt_nets=6 @@ -1314,8 +1666,14 @@ randomization=false type=Switch children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17 port_buffers18 port_buffers19 port_buffers20 port_buffers21 port_buffers22 port_buffers23 clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED eventq_index=0 +latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 port_buffers=system.ruby.network.routers2.port_buffers00 system.ruby.network.routers2.port_buffers01 system.ruby.network.routers2.port_buffers02 system.ruby.network.routers2.port_buffers03 system.ruby.network.routers2.port_buffers04 system.ruby.network.routers2.port_buffers05 system.ruby.network.routers2.port_buffers06 system.ruby.network.routers2.port_buffers07 system.ruby.network.routers2.port_buffers08 system.ruby.network.routers2.port_buffers09 system.ruby.network.routers2.port_buffers10 system.ruby.network.routers2.port_buffers11 system.ruby.network.routers2.port_buffers12 system.ruby.network.routers2.port_buffers13 system.ruby.network.routers2.port_buffers14 system.ruby.network.routers2.port_buffers15 system.ruby.network.routers2.port_buffers16 system.ruby.network.routers2.port_buffers17 system.ruby.network.routers2.port_buffers18 system.ruby.network.routers2.port_buffers19 system.ruby.network.routers2.port_buffers20 system.ruby.network.routers2.port_buffers21 system.ruby.network.routers2.port_buffers22 system.ruby.network.routers2.port_buffers23 +power_model=Null router_id=2 virt_nets=6 @@ -1491,8 +1849,14 @@ randomization=false type=Switch children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17 port_buffers18 port_buffers19 port_buffers20 port_buffers21 port_buffers22 port_buffers23 port_buffers24 port_buffers25 port_buffers26 port_buffers27 port_buffers28 port_buffers29 port_buffers30 port_buffers31 port_buffers32 port_buffers33 port_buffers34 port_buffers35 clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED eventq_index=0 +latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 port_buffers=system.ruby.network.routers3.port_buffers00 system.ruby.network.routers3.port_buffers01 system.ruby.network.routers3.port_buffers02 system.ruby.network.routers3.port_buffers03 system.ruby.network.routers3.port_buffers04 system.ruby.network.routers3.port_buffers05 system.ruby.network.routers3.port_buffers06 system.ruby.network.routers3.port_buffers07 system.ruby.network.routers3.port_buffers08 system.ruby.network.routers3.port_buffers09 system.ruby.network.routers3.port_buffers10 system.ruby.network.routers3.port_buffers11 system.ruby.network.routers3.port_buffers12 system.ruby.network.routers3.port_buffers13 system.ruby.network.routers3.port_buffers14 system.ruby.network.routers3.port_buffers15 system.ruby.network.routers3.port_buffers16 system.ruby.network.routers3.port_buffers17 system.ruby.network.routers3.port_buffers18 system.ruby.network.routers3.port_buffers19 system.ruby.network.routers3.port_buffers20 system.ruby.network.routers3.port_buffers21 system.ruby.network.routers3.port_buffers22 system.ruby.network.routers3.port_buffers23 system.ruby.network.routers3.port_buffers24 system.ruby.network.routers3.port_buffers25 system.ruby.network.routers3.port_buffers26 system.ruby.network.routers3.port_buffers27 system.ruby.network.routers3.port_buffers28 system.ruby.network.routers3.port_buffers29 system.ruby.network.routers3.port_buffers30 system.ruby.network.routers3.port_buffers31 system.ruby.network.routers3.port_buffers32 system.ruby.network.routers3.port_buffers33 system.ruby.network.routers3.port_buffers34 system.ruby.network.routers3.port_buffers35 +power_model=Null router_id=3 virt_nets=6 @@ -1751,9 +2115,14 @@ randomization=false [system.sys_port_proxy] type=RubyPortProxy clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 is_cpu_sequencer=true no_retry_on_stall=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null ruby_system=system.ruby support_data_reqs=true support_inst_reqs=true diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simerr b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simerr index ccfdd3697..f6f6f15a5 100755 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simerr +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simerr @@ -4,8 +4,7 @@ warn: rounding error > tolerance 1.250000 rounded to 1 warn: rounding error > tolerance 1.250000 rounded to 1 -warn: rounding error > tolerance - 1.250000 rounded to 1 warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes) warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files! diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout index f535b9682..57e41dbee 100755 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout @@ -3,13 +3,13 @@ Redirecting stderr to build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/al gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 14 2016 22:02:54 -gem5 started Mar 14 2016 22:04:07 -gem5 executing on phenom, pid 29513 -command line: build/ALPHA_MOESI_CMP_token/gem5.opt -d build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token +gem5 compiled Oct 13 2016 20:33:48 +gem5 started Oct 13 2016 20:34:16 +gem5 executing on e108600-lin, pid 27525 +command line: /work/curdun01/gem5-external.hg/build/ALPHA_MOESI_CMP_token/gem5.opt -d build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 108253 because target called exit() +Exiting @ tick 113952 because target called exit() diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt index e5f292184..b89069f53 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000108 # Number of seconds simulated -sim_ticks 108253 # Number of ticks simulated -final_tick 108253 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000114 # Number of seconds simulated +sim_ticks 113952 # Number of ticks simulated +final_tick 113952 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 94410 # Simulator instruction rate (inst/s) -host_op_rate 94397 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1595747 # Simulator tick rate (ticks/s) -host_mem_usage 455808 # Number of bytes of host memory used -host_seconds 0.07 # Real time elapsed on the host +host_inst_rate 64476 # Simulator instruction rate (inst/s) +host_op_rate 64460 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1146955 # Simulator tick rate (ticks/s) +host_mem_usage 412808 # Number of bytes of host memory used +host_seconds 0.10 # Real time elapsed on the host sim_insts 6403 # Number of instructions simulated sim_ops 6403 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks -system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 108253 # Cumulative time (in ticks) in various power states +system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 113952 # Cumulative time (in ticks) in various power states system.mem_ctrls.bytes_read::ruby.dir_cntrl0 75456 # Number of bytes read from this memory system.mem_ctrls.bytes_read::total 75456 # Number of bytes read from this memory system.mem_ctrls.bytes_written::ruby.dir_cntrl0 14656 # Number of bytes written to this memory @@ -22,59 +22,59 @@ system.mem_ctrls.num_reads::ruby.dir_cntrl0 1179 # system.mem_ctrls.num_reads::total 1179 # Number of read requests responded to by this memory system.mem_ctrls.num_writes::ruby.dir_cntrl0 229 # Number of write requests responded to by this memory system.mem_ctrls.num_writes::total 229 # Number of write requests responded to by this memory -system.mem_ctrls.bw_read::ruby.dir_cntrl0 697033800 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_read::total 697033800 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::ruby.dir_cntrl0 135386548 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::total 135386548 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_total::ruby.dir_cntrl0 832420349 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.bw_total::total 832420349 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_read::ruby.dir_cntrl0 662173547 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 662173547 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::ruby.dir_cntrl0 128615557 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::total 128615557 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::ruby.dir_cntrl0 790789104 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 790789104 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrls.readReqs 1179 # Number of read requests accepted system.mem_ctrls.writeReqs 229 # Number of write requests accepted system.mem_ctrls.readBursts 1179 # Number of DRAM read bursts, including those serviced by the write queue system.mem_ctrls.writeBursts 229 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrls.bytesReadDRAM 65088 # Total number of bytes read from DRAM -system.mem_ctrls.bytesReadWrQ 10368 # Total number of bytes read from write queue -system.mem_ctrls.bytesWritten 6144 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadDRAM 64256 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 11200 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 5120 # Total number of bytes written to DRAM system.mem_ctrls.bytesReadSys 75456 # Total read bytes from the system interface side system.mem_ctrls.bytesWrittenSys 14656 # Total written bytes from the system interface side -system.mem_ctrls.servicedByWrQ 162 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrls.mergedWrBursts 112 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.servicedByWrQ 175 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 117 # Number of DRAM write bursts merged with an existing one system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.mem_ctrls.perBankRdBursts::0 86 # Per bank write bursts system.mem_ctrls.perBankRdBursts::1 52 # Per bank write bursts system.mem_ctrls.perBankRdBursts::2 82 # Per bank write bursts system.mem_ctrls.perBankRdBursts::3 77 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::4 95 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::5 19 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 92 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 18 # Per bank write bursts system.mem_ctrls.perBankRdBursts::6 1 # Per bank write bursts system.mem_ctrls.perBankRdBursts::7 3 # Per bank write bursts system.mem_ctrls.perBankRdBursts::8 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::9 1 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::10 59 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 51 # Per bank write bursts system.mem_ctrls.perBankRdBursts::11 53 # Per bank write bursts system.mem_ctrls.perBankRdBursts::12 22 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::13 361 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 360 # Per bank write bursts system.mem_ctrls.perBankRdBursts::14 61 # Per bank write bursts system.mem_ctrls.perBankRdBursts::15 45 # Per bank write bursts system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::4 23 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::5 7 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 20 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 6 # Per bank write bursts system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::10 5 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 2 # Per bank write bursts system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::13 18 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::14 43 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 15 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 37 # Per bank write bursts system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrls.totGap 108170 # Total gap between requests +system.mem_ctrls.totGap 113863 # Total gap between requests system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) @@ -89,7 +89,7 @@ system.mem_ctrls.writePktSize::3 0 # Wr system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::6 229 # Write request sizes (log2) -system.mem_ctrls.rdQLenPdf::0 1017 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::0 1004 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see @@ -138,10 +138,10 @@ system.mem_ctrls.wrQLenPdf::13 1 # Wh system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::15 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::16 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::17 7 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::18 7 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::19 7 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::20 7 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 6 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 6 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 6 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 6 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::21 6 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::22 6 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::23 6 # What write queue length does an incoming req see @@ -153,7 +153,7 @@ system.mem_ctrls.wrQLenPdf::28 6 # Wh system.mem_ctrls.wrQLenPdf::29 6 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::30 6 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::31 6 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::32 6 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::32 5 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see @@ -185,87 +185,96 @@ system.mem_ctrls.wrQLenPdf::60 0 # Wh system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrls.bytesPerActivate::samples 203 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::mean 338.916256 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::gmean 206.604664 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::stdev 325.225174 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::0-127 65 32.02% 32.02% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::128-255 46 22.66% 54.68% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::256-383 21 10.34% 65.02% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::384-511 11 5.42% 70.44% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::512-639 17 8.37% 78.82% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::640-767 10 4.93% 83.74% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::768-895 8 3.94% 87.68% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::896-1023 4 1.97% 89.66% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::1024-1151 21 10.34% 100.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::total 203 # Bytes accessed per row activation -system.mem_ctrls.rdPerTurnAround::samples 6 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::mean 156.500000 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::gmean 117.084065 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::stdev 90.391924 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::16-31 1 16.67% 16.67% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::80-95 1 16.67% 33.33% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::160-175 1 16.67% 50.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::192-207 1 16.67% 66.67% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::208-223 1 16.67% 83.33% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::256-271 1 16.67% 100.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::total 6 # Reads before turning the bus around for writes -system.mem_ctrls.wrPerTurnAround::samples 6 # Writes before turning the bus around for reads +system.mem_ctrls.bytesPerActivate::samples 201 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 338.149254 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 209.301438 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 329.237418 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 56 27.86% 27.86% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 54 26.87% 54.73% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 27 13.43% 68.16% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 9 4.48% 72.64% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 15 7.46% 80.10% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 6 2.99% 83.08% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 6 2.99% 86.07% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 4 1.99% 88.06% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 24 11.94% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 201 # Bytes accessed per row activation +system.mem_ctrls.rdPerTurnAround::samples 5 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::mean 138 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::gmean 99.720637 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::stdev 86.905121 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::16-23 1 20.00% 20.00% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::80-87 1 20.00% 40.00% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::160-167 1 20.00% 60.00% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::208-215 1 20.00% 80.00% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::216-223 1 20.00% 100.00% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::total 5 # Reads before turning the bus around for writes +system.mem_ctrls.wrPerTurnAround::samples 5 # Writes before turning the bus around for reads system.mem_ctrls.wrPerTurnAround::mean 16 # Writes before turning the bus around for reads system.mem_ctrls.wrPerTurnAround::gmean 16.000000 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::16 6 100.00% 100.00% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::total 6 # Writes before turning the bus around for reads -system.mem_ctrls.totQLat 7213 # Total ticks spent queuing -system.mem_ctrls.totMemAccLat 26536 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrls.totBusLat 5085 # Total ticks spent in databus transfers -system.mem_ctrls.avgQLat 7.09 # Average queueing delay per DRAM burst +system.mem_ctrls.wrPerTurnAround::16 5 100.00% 100.00% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::total 5 # Writes before turning the bus around for reads +system.mem_ctrls.totQLat 13296 # Total ticks spent queuing +system.mem_ctrls.totMemAccLat 32372 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.totBusLat 5020 # Total ticks spent in databus transfers +system.mem_ctrls.avgQLat 13.24 # Average queueing delay per DRAM burst system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst -system.mem_ctrls.avgMemAccLat 26.09 # Average memory access latency per DRAM burst -system.mem_ctrls.avgRdBW 601.26 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrls.avgWrBW 56.76 # Average achieved write bandwidth in MiByte/s -system.mem_ctrls.avgRdBWSys 697.03 # Average system read bandwidth in MiByte/s -system.mem_ctrls.avgWrBWSys 135.39 # Average system write bandwidth in MiByte/s +system.mem_ctrls.avgMemAccLat 32.24 # Average memory access latency per DRAM burst +system.mem_ctrls.avgRdBW 563.89 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 44.93 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 662.17 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 128.62 # Average system write bandwidth in MiByte/s system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrls.busUtil 5.14 # Data bus utilization in percentage -system.mem_ctrls.busUtilRead 4.70 # Data bus utilization in percentage for reads -system.mem_ctrls.busUtilWrite 0.44 # Data bus utilization in percentage for writes +system.mem_ctrls.busUtil 4.76 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 4.41 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 0.35 # Data bus utilization in percentage for writes system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing -system.mem_ctrls.avgWrQLen 23.01 # Average write queue length when enqueuing -system.mem_ctrls.readRowHits 816 # Number of row buffer hits during reads -system.mem_ctrls.writeRowHits 88 # Number of row buffer hits during writes -system.mem_ctrls.readRowHitRate 80.24 # Row buffer hit rate for reads -system.mem_ctrls.writeRowHitRate 75.21 # Row buffer hit rate for writes -system.mem_ctrls.avgGap 76.83 # Average gap between requests -system.mem_ctrls.pageHitRate 79.72 # Row buffer hit rate, read and write combined -system.mem_ctrls_0.actEnergy 521640 # Energy for activate commands per rank (pJ) -system.mem_ctrls_0.preEnergy 289800 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_0.readEnergy 5104320 # Energy for read commands per rank (pJ) -system.mem_ctrls_0.writeEnergy 311040 # Energy for write commands per rank (pJ) -system.mem_ctrls_0.refreshEnergy 6611280 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_0.actBackEnergy 57840408 # Energy for active background per rank (pJ) -system.mem_ctrls_0.preBackEnergy 10149600 # Energy for precharge background per rank (pJ) -system.mem_ctrls_0.totalEnergy 80828088 # Total energy per rank (pJ) -system.mem_ctrls_0.averagePower 796.508485 # Core power per rank (mW) -system.mem_ctrls_0.memoryStateTime::IDLE 21689 # Time in different power states -system.mem_ctrls_0.memoryStateTime::REF 3380 # Time in different power states -system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT 81532 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrls_1.actEnergy 945000 # Energy for activate commands per rank (pJ) -system.mem_ctrls_1.preEnergy 525000 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_1.readEnergy 6764160 # Energy for read commands per rank (pJ) -system.mem_ctrls_1.writeEnergy 684288 # Energy for write commands per rank (pJ) -system.mem_ctrls_1.refreshEnergy 6611280 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_1.actBackEnergy 67474548 # Energy for active background per rank (pJ) -system.mem_ctrls_1.preBackEnergy 1707000 # Energy for precharge background per rank (pJ) -system.mem_ctrls_1.totalEnergy 84711276 # Total energy per rank (pJ) -system.mem_ctrls_1.averagePower 834.659638 # Core power per rank (mW) -system.mem_ctrls_1.memoryStateTime::IDLE 2397 # Time in different power states -system.mem_ctrls_1.memoryStateTime::REF 3380 # Time in different power states -system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT 95729 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 108253 # Cumulative time (in ticks) in various power states +system.mem_ctrls.avgWrQLen 22.60 # Average write queue length when enqueuing +system.mem_ctrls.readRowHits 806 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 73 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 80.28 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate 65.18 # Row buffer hit rate for writes +system.mem_ctrls.avgGap 80.87 # Average gap between requests +system.mem_ctrls.pageHitRate 78.76 # Row buffer hit rate, read and write combined +system.mem_ctrls_0.actEnergy 471240 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 255024 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 4695264 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 217152 # Energy for write commands per rank (pJ) +system.mem_ctrls_0.refreshEnergy 9219600.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 7578264 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 292992 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.actPowerDownEnergy 33706152 # Energy for active power-down per rank (pJ) +system.mem_ctrls_0.prePowerDownEnergy 7106688 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls_0.selfRefreshEnergy 1604640 # Energy for self refresh per rank (pJ) +system.mem_ctrls_0.totalEnergy 65147016 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 570.509199 # Core power per rank (mW) +system.mem_ctrls_0.totalIdleTime 96809 # Total Idle time Per DRAM Rank +system.mem_ctrls_0.memoryStateTime::IDLE 351 # Time in different power states +system.mem_ctrls_0.memoryStateTime::REF 3653 # Time in different power states +system.mem_ctrls_0.memoryStateTime::SREF 4385 # Time in different power states +system.mem_ctrls_0.memoryStateTime::PRE_PDN 18507 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 13139 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT_PDN 73917 # Time in different power states +system.mem_ctrls_1.actEnergy 992460 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 521640 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 6774432 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 451008 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.refreshEnergy 8604960.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 10831824 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 319872 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.actPowerDownEnergy 39423936 # Energy for active power-down per rank (pJ) +system.mem_ctrls_1.prePowerDownEnergy 1117056 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls_1.totalEnergy 69037188 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 605.844461 # Core power per rank (mW) +system.mem_ctrls_1.totalIdleTime 89154 # Total Idle time Per DRAM Rank +system.mem_ctrls_1.memoryStateTime::IDLE 259 # Time in different power states +system.mem_ctrls_1.memoryStateTime::REF 3640 # Time in different power states +system.mem_ctrls_1.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls_1.memoryStateTime::PRE_PDN 2909 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 20688 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT_PDN 86456 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 113952 # Cumulative time (in ticks) in various power states system.cpu.clk_domain.clock 1 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -300,8 +309,8 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 108253 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 108253 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 113952 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 113952 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 6403 # Number of instructions committed @@ -320,7 +329,7 @@ system.cpu.num_mem_refs 2060 # nu system.cpu.num_load_insts 1192 # Number of load instructions system.cpu.num_store_insts 868 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 108253 # Number of busy cycles +system.cpu.num_busy_cycles 113952 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 1056 # Number of branches fetched @@ -360,7 +369,7 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 6413 # Class of executed instruction system.ruby.clk_domain.clock 1 # Clock period in ticks -system.ruby.pwrStateResidencyTicks::UNDEFINED 108253 # Cumulative time (in ticks) in various power states +system.ruby.pwrStateResidencyTicks::UNDEFINED 113952 # Cumulative time (in ticks) in various power states system.ruby.outstanding_req_hist_seqr::bucket_size 1 system.ruby.outstanding_req_hist_seqr::max_bucket 9 system.ruby.outstanding_req_hist_seqr::samples 8464 @@ -371,86 +380,86 @@ system.ruby.outstanding_req_hist_seqr::total 8464 system.ruby.latency_hist_seqr::bucket_size 64 system.ruby.latency_hist_seqr::max_bucket 639 system.ruby.latency_hist_seqr::samples 8463 -system.ruby.latency_hist_seqr::mean 11.791327 -system.ruby.latency_hist_seqr::gmean 1.956562 -system.ruby.latency_hist_seqr::stdev 27.556143 -system.ruby.latency_hist_seqr | 7446 87.98% 87.98% | 996 11.77% 99.75% | 8 0.09% 99.85% | 4 0.05% 99.89% | 5 0.06% 99.95% | 4 0.05% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.latency_hist_seqr::mean 12.464729 +system.ruby.latency_hist_seqr::gmean 1.971984 +system.ruby.latency_hist_seqr::stdev 29.823065 +system.ruby.latency_hist_seqr | 7459 88.14% 88.14% | 983 11.62% 99.75% | 7 0.08% 99.83% | 3 0.04% 99.87% | 5 0.06% 99.93% | 5 0.06% 99.99% | 0 0.00% 99.99% | 0 0.00% 99.99% | 0 0.00% 99.99% | 1 0.01% 100.00% system.ruby.latency_hist_seqr::total 8463 system.ruby.hit_latency_hist_seqr::bucket_size 8 system.ruby.hit_latency_hist_seqr::max_bucket 79 system.ruby.hit_latency_hist_seqr::samples 7284 -system.ruby.hit_latency_hist_seqr::mean 1.635502 -system.ruby.hit_latency_hist_seqr::gmean 1.092626 -system.ruby.hit_latency_hist_seqr::stdev 3.754063 +system.ruby.hit_latency_hist_seqr::mean 1.636052 +system.ruby.hit_latency_hist_seqr::gmean 1.092653 +system.ruby.hit_latency_hist_seqr::stdev 3.757041 system.ruby.hit_latency_hist_seqr | 7080 97.20% 97.20% | 0 0.00% 97.20% | 21 0.29% 97.49% | 182 2.50% 99.99% | 0 0.00% 99.99% | 1 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.hit_latency_hist_seqr::total 7284 system.ruby.miss_latency_hist_seqr::bucket_size 64 system.ruby.miss_latency_hist_seqr::max_bucket 639 system.ruby.miss_latency_hist_seqr::samples 1179 -system.ruby.miss_latency_hist_seqr::mean 74.535199 -system.ruby.miss_latency_hist_seqr::gmean 71.564149 -system.ruby.miss_latency_hist_seqr::stdev 28.099799 -system.ruby.miss_latency_hist_seqr | 162 13.74% 13.74% | 996 84.48% 98.22% | 8 0.68% 98.90% | 4 0.34% 99.24% | 5 0.42% 99.66% | 4 0.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.miss_latency_hist_seqr::mean 79.365564 +system.ruby.miss_latency_hist_seqr::gmean 75.701428 +system.ruby.miss_latency_hist_seqr::stdev 33.123085 +system.ruby.miss_latency_hist_seqr | 175 14.84% 14.84% | 983 83.38% 98.22% | 7 0.59% 98.81% | 3 0.25% 99.07% | 5 0.42% 99.49% | 5 0.42% 99.92% | 0 0.00% 99.92% | 0 0.00% 99.92% | 0 0.00% 99.92% | 1 0.08% 100.00% system.ruby.miss_latency_hist_seqr::total 1179 system.ruby.Directory.incomplete_times_seqr 1178 -system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 108253 # Cumulative time (in ticks) in various power states +system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 113952 # Cumulative time (in ticks) in various power states system.ruby.l1_cntrl0.L1Dcache.demand_hits 1313 # Number of cache demand hits system.ruby.l1_cntrl0.L1Dcache.demand_misses 737 # Number of cache demand misses system.ruby.l1_cntrl0.L1Dcache.demand_accesses 2050 # Number of cache demand accesses system.ruby.l1_cntrl0.L1Icache.demand_hits 5767 # Number of cache demand hits system.ruby.l1_cntrl0.L1Icache.demand_misses 646 # Number of cache demand misses system.ruby.l1_cntrl0.L1Icache.demand_accesses 6413 # Number of cache demand accesses -system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 108253 # Cumulative time (in ticks) in various power states -system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 108253 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 113952 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 113952 # Cumulative time (in ticks) in various power states system.ruby.l2_cntrl0.L2cache.demand_hits 187 # Number of cache demand hits system.ruby.l2_cntrl0.L2cache.demand_misses 1196 # Number of cache demand misses system.ruby.l2_cntrl0.L2cache.demand_accesses 1383 # Number of cache demand accesses -system.ruby.l2_cntrl0.pwrStateResidencyTicks::UNDEFINED 108253 # Cumulative time (in ticks) in various power states +system.ruby.l2_cntrl0.pwrStateResidencyTicks::UNDEFINED 113952 # Cumulative time (in ticks) in various power states system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 108253 # Cumulative time (in ticks) in various power states -system.ruby.network.routers0.percent_links_utilized 6.022466 +system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 113952 # Cumulative time (in ticks) in various power states +system.ruby.network.routers0.percent_links_utilized 5.719513 system.ruby.network.routers0.msg_count.Request_Control::1 1383 system.ruby.network.routers0.msg_count.Response_Data::4 1179 system.ruby.network.routers0.msg_count.ResponseL2hit_Data::4 204 system.ruby.network.routers0.msg_count.Response_Control::4 1 system.ruby.network.routers0.msg_count.Writeback_Data::4 1355 -system.ruby.network.routers0.msg_count.Persistent_Control::3 52 +system.ruby.network.routers0.msg_count.Persistent_Control::3 44 system.ruby.network.routers0.msg_bytes.Request_Control::1 11064 system.ruby.network.routers0.msg_bytes.Response_Data::4 84888 system.ruby.network.routers0.msg_bytes.ResponseL2hit_Data::4 14688 system.ruby.network.routers0.msg_bytes.Response_Control::4 8 system.ruby.network.routers0.msg_bytes.Writeback_Data::4 97560 -system.ruby.network.routers0.msg_bytes.Persistent_Control::3 416 -system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 108253 # Cumulative time (in ticks) in various power states -system.ruby.network.routers1.percent_links_utilized 4.541676 +system.ruby.network.routers0.msg_bytes.Persistent_Control::3 352 +system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 113952 # Cumulative time (in ticks) in various power states +system.ruby.network.routers1.percent_links_utilized 4.313658 system.ruby.network.routers1.msg_count.Request_Control::1 1383 system.ruby.network.routers1.msg_count.Request_Control::2 1196 system.ruby.network.routers1.msg_count.ResponseL2hit_Data::4 204 system.ruby.network.routers1.msg_count.Response_Control::4 1 system.ruby.network.routers1.msg_count.Writeback_Data::4 1584 system.ruby.network.routers1.msg_count.Writeback_Control::4 968 -system.ruby.network.routers1.msg_count.Persistent_Control::3 26 +system.ruby.network.routers1.msg_count.Persistent_Control::3 22 system.ruby.network.routers1.msg_bytes.Request_Control::1 11064 system.ruby.network.routers1.msg_bytes.Request_Control::2 9568 system.ruby.network.routers1.msg_bytes.ResponseL2hit_Data::4 14688 system.ruby.network.routers1.msg_bytes.Response_Control::4 8 system.ruby.network.routers1.msg_bytes.Writeback_Data::4 114048 system.ruby.network.routers1.msg_bytes.Writeback_Control::4 7744 -system.ruby.network.routers1.msg_bytes.Persistent_Control::3 208 -system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 108253 # Cumulative time (in ticks) in various power states -system.ruby.network.routers2.percent_links_utilized 3.432237 +system.ruby.network.routers1.msg_bytes.Persistent_Control::3 176 +system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 113952 # Cumulative time (in ticks) in various power states +system.ruby.network.routers2.percent_links_utilized 3.259706 system.ruby.network.routers2.msg_count.Request_Control::2 1196 system.ruby.network.routers2.msg_count.Response_Data::4 1179 system.ruby.network.routers2.msg_count.Writeback_Data::4 229 system.ruby.network.routers2.msg_count.Writeback_Control::4 968 -system.ruby.network.routers2.msg_count.Persistent_Control::3 26 +system.ruby.network.routers2.msg_count.Persistent_Control::3 22 system.ruby.network.routers2.msg_bytes.Request_Control::2 9568 system.ruby.network.routers2.msg_bytes.Response_Data::4 84888 system.ruby.network.routers2.msg_bytes.Writeback_Data::4 16488 system.ruby.network.routers2.msg_bytes.Writeback_Control::4 7744 -system.ruby.network.routers2.msg_bytes.Persistent_Control::3 208 -system.ruby.network.routers3.pwrStateResidencyTicks::UNDEFINED 108253 # Cumulative time (in ticks) in various power states -system.ruby.network.routers3.percent_links_utilized 4.665460 +system.ruby.network.routers2.msg_bytes.Persistent_Control::3 176 +system.ruby.network.routers3.pwrStateResidencyTicks::UNDEFINED 113952 # Cumulative time (in ticks) in various power states +system.ruby.network.routers3.percent_links_utilized 4.430959 system.ruby.network.routers3.msg_count.Request_Control::1 1383 system.ruby.network.routers3.msg_count.Request_Control::2 1196 system.ruby.network.routers3.msg_count.Response_Data::4 1179 @@ -458,7 +467,7 @@ system.ruby.network.routers3.msg_count.ResponseL2hit_Data::4 204 system.ruby.network.routers3.msg_count.Response_Control::4 1 system.ruby.network.routers3.msg_count.Writeback_Data::4 1584 system.ruby.network.routers3.msg_count.Writeback_Control::4 968 -system.ruby.network.routers3.msg_count.Persistent_Control::3 52 +system.ruby.network.routers3.msg_count.Persistent_Control::3 44 system.ruby.network.routers3.msg_bytes.Request_Control::1 11064 system.ruby.network.routers3.msg_bytes.Request_Control::2 9568 system.ruby.network.routers3.msg_bytes.Response_Data::4 84888 @@ -466,47 +475,47 @@ system.ruby.network.routers3.msg_bytes.ResponseL2hit_Data::4 14688 system.ruby.network.routers3.msg_bytes.Response_Control::4 8 system.ruby.network.routers3.msg_bytes.Writeback_Data::4 114048 system.ruby.network.routers3.msg_bytes.Writeback_Control::4 7744 -system.ruby.network.routers3.msg_bytes.Persistent_Control::3 416 -system.ruby.network.pwrStateResidencyTicks::UNDEFINED 108253 # Cumulative time (in ticks) in various power states +system.ruby.network.routers3.msg_bytes.Persistent_Control::3 352 +system.ruby.network.pwrStateResidencyTicks::UNDEFINED 113952 # Cumulative time (in ticks) in various power states system.ruby.network.msg_count.Request_Control 7737 system.ruby.network.msg_count.Response_Data 3537 system.ruby.network.msg_count.ResponseL2hit_Data 612 system.ruby.network.msg_count.Response_Control 3 system.ruby.network.msg_count.Writeback_Data 4752 system.ruby.network.msg_count.Writeback_Control 2904 -system.ruby.network.msg_count.Persistent_Control 156 +system.ruby.network.msg_count.Persistent_Control 132 system.ruby.network.msg_byte.Request_Control 61896 system.ruby.network.msg_byte.Response_Data 254664 system.ruby.network.msg_byte.ResponseL2hit_Data 44064 system.ruby.network.msg_byte.Response_Control 24 system.ruby.network.msg_byte.Writeback_Data 342144 system.ruby.network.msg_byte.Writeback_Control 23232 -system.ruby.network.msg_byte.Persistent_Control 1248 -system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 108253 # Cumulative time (in ticks) in various power states -system.ruby.network.routers0.throttle0.link_utilization 5.761503 +system.ruby.network.msg_byte.Persistent_Control 1056 +system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 113952 # Cumulative time (in ticks) in various power states +system.ruby.network.routers0.throttle0.link_utilization 5.471602 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1179 system.ruby.network.routers0.throttle0.msg_count.ResponseL2hit_Data::4 204 system.ruby.network.routers0.throttle0.msg_count.Response_Control::4 1 -system.ruby.network.routers0.throttle0.msg_count.Persistent_Control::3 26 +system.ruby.network.routers0.throttle0.msg_count.Persistent_Control::3 22 system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 84888 system.ruby.network.routers0.throttle0.msg_bytes.ResponseL2hit_Data::4 14688 system.ruby.network.routers0.throttle0.msg_bytes.Response_Control::4 8 -system.ruby.network.routers0.throttle0.msg_bytes.Persistent_Control::3 208 -system.ruby.network.routers0.throttle1.link_utilization 6.283429 +system.ruby.network.routers0.throttle0.msg_bytes.Persistent_Control::3 176 +system.ruby.network.routers0.throttle1.link_utilization 5.967425 system.ruby.network.routers0.throttle1.msg_count.Request_Control::1 1383 system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::4 1355 -system.ruby.network.routers0.throttle1.msg_count.Persistent_Control::3 26 +system.ruby.network.routers0.throttle1.msg_count.Persistent_Control::3 22 system.ruby.network.routers0.throttle1.msg_bytes.Request_Control::1 11064 system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::4 97560 -system.ruby.network.routers0.throttle1.msg_bytes.Persistent_Control::3 208 -system.ruby.network.routers1.throttle0.link_utilization 6.283429 +system.ruby.network.routers0.throttle1.msg_bytes.Persistent_Control::3 176 +system.ruby.network.routers1.throttle0.link_utilization 5.967425 system.ruby.network.routers1.throttle0.msg_count.Request_Control::1 1383 system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::4 1355 -system.ruby.network.routers1.throttle0.msg_count.Persistent_Control::3 26 +system.ruby.network.routers1.throttle0.msg_count.Persistent_Control::3 22 system.ruby.network.routers1.throttle0.msg_bytes.Request_Control::1 11064 system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::4 97560 -system.ruby.network.routers1.throttle0.msg_bytes.Persistent_Control::3 208 -system.ruby.network.routers1.throttle1.link_utilization 2.799922 +system.ruby.network.routers1.throttle0.msg_bytes.Persistent_Control::3 176 +system.ruby.network.routers1.throttle1.link_utilization 2.659892 system.ruby.network.routers1.throttle1.msg_count.Request_Control::2 1196 system.ruby.network.routers1.throttle1.msg_count.ResponseL2hit_Data::4 204 system.ruby.network.routers1.throttle1.msg_count.Response_Control::4 1 @@ -517,96 +526,96 @@ system.ruby.network.routers1.throttle1.msg_bytes.ResponseL2hit_Data::4 14 system.ruby.network.routers1.throttle1.msg_bytes.Response_Control::4 8 system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Data::4 16488 system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::4 7744 -system.ruby.network.routers2.throttle0.link_utilization 1.963456 +system.ruby.network.routers2.throttle0.link_utilization 1.863504 system.ruby.network.routers2.throttle0.msg_count.Request_Control::2 1196 system.ruby.network.routers2.throttle0.msg_count.Writeback_Data::4 229 system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::4 968 -system.ruby.network.routers2.throttle0.msg_count.Persistent_Control::3 26 +system.ruby.network.routers2.throttle0.msg_count.Persistent_Control::3 22 system.ruby.network.routers2.throttle0.msg_bytes.Request_Control::2 9568 system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Data::4 16488 system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::4 7744 -system.ruby.network.routers2.throttle0.msg_bytes.Persistent_Control::3 208 -system.ruby.network.routers2.throttle1.link_utilization 4.901019 +system.ruby.network.routers2.throttle0.msg_bytes.Persistent_Control::3 176 +system.ruby.network.routers2.throttle1.link_utilization 4.655908 system.ruby.network.routers2.throttle1.msg_count.Response_Data::4 1179 system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::4 84888 -system.ruby.network.routers3.throttle0.link_utilization 5.749494 +system.ruby.network.routers3.throttle0.link_utilization 5.461949 system.ruby.network.routers3.throttle0.msg_count.Response_Data::4 1179 system.ruby.network.routers3.throttle0.msg_count.ResponseL2hit_Data::4 204 system.ruby.network.routers3.throttle0.msg_count.Response_Control::4 1 system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::4 84888 system.ruby.network.routers3.throttle0.msg_bytes.ResponseL2hit_Data::4 14688 system.ruby.network.routers3.throttle0.msg_bytes.Response_Control::4 8 -system.ruby.network.routers3.throttle1.link_utilization 6.283429 +system.ruby.network.routers3.throttle1.link_utilization 5.967425 system.ruby.network.routers3.throttle1.msg_count.Request_Control::1 1383 system.ruby.network.routers3.throttle1.msg_count.Writeback_Data::4 1355 -system.ruby.network.routers3.throttle1.msg_count.Persistent_Control::3 26 +system.ruby.network.routers3.throttle1.msg_count.Persistent_Control::3 22 system.ruby.network.routers3.throttle1.msg_bytes.Request_Control::1 11064 system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::4 97560 -system.ruby.network.routers3.throttle1.msg_bytes.Persistent_Control::3 208 -system.ruby.network.routers3.throttle2.link_utilization 1.963456 +system.ruby.network.routers3.throttle1.msg_bytes.Persistent_Control::3 176 +system.ruby.network.routers3.throttle2.link_utilization 1.863504 system.ruby.network.routers3.throttle2.msg_count.Request_Control::2 1196 system.ruby.network.routers3.throttle2.msg_count.Writeback_Data::4 229 system.ruby.network.routers3.throttle2.msg_count.Writeback_Control::4 968 -system.ruby.network.routers3.throttle2.msg_count.Persistent_Control::3 26 +system.ruby.network.routers3.throttle2.msg_count.Persistent_Control::3 22 system.ruby.network.routers3.throttle2.msg_bytes.Request_Control::2 9568 system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Data::4 16488 system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Control::4 7744 -system.ruby.network.routers3.throttle2.msg_bytes.Persistent_Control::3 208 +system.ruby.network.routers3.throttle2.msg_bytes.Persistent_Control::3 176 system.ruby.LD.latency_hist_seqr::bucket_size 64 system.ruby.LD.latency_hist_seqr::max_bucket 639 system.ruby.LD.latency_hist_seqr::samples 1185 -system.ruby.LD.latency_hist_seqr::mean 28.779747 -system.ruby.LD.latency_hist_seqr::gmean 6.012520 -system.ruby.LD.latency_hist_seqr::stdev 37.360727 -system.ruby.LD.latency_hist_seqr | 843 71.14% 71.14% | 337 28.44% 99.58% | 2 0.17% 99.75% | 0 0.00% 99.75% | 2 0.17% 99.92% | 1 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.latency_hist_seqr::mean 29.824473 +system.ruby.LD.latency_hist_seqr::gmean 6.089961 +system.ruby.LD.latency_hist_seqr::stdev 38.602832 +system.ruby.LD.latency_hist_seqr | 854 72.07% 72.07% | 327 27.59% 99.66% | 2 0.17% 99.83% | 0 0.00% 99.83% | 0 0.00% 99.83% | 2 0.17% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.latency_hist_seqr::total 1185 system.ruby.LD.hit_latency_hist_seqr::bucket_size 4 system.ruby.LD.hit_latency_hist_seqr::max_bucket 39 system.ruby.LD.hit_latency_hist_seqr::samples 759 -system.ruby.LD.hit_latency_hist_seqr::mean 4.030303 -system.ruby.LD.hit_latency_hist_seqr::gmean 1.520008 -system.ruby.LD.hit_latency_hist_seqr::stdev 7.784219 -system.ruby.LD.hit_latency_hist_seqr | 659 86.82% 86.82% | 0 0.00% 86.82% | 0 0.00% 86.82% | 0 0.00% 86.82% | 0 0.00% 86.82% | 0 0.00% 86.82% | 100 13.18% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.hit_latency_hist_seqr::mean 4.025033 +system.ruby.LD.hit_latency_hist_seqr::gmean 1.519643 +system.ruby.LD.hit_latency_hist_seqr::stdev 7.772026 +system.ruby.LD.hit_latency_hist_seqr | 659 86.82% 86.82% | 0 0.00% 86.82% | 0 0.00% 86.82% | 0 0.00% 86.82% | 0 0.00% 86.82% | 1 0.13% 86.96% | 99 13.04% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.hit_latency_hist_seqr::total 759 system.ruby.LD.miss_latency_hist_seqr::bucket_size 64 system.ruby.LD.miss_latency_hist_seqr::max_bucket 639 system.ruby.LD.miss_latency_hist_seqr::samples 426 -system.ruby.LD.miss_latency_hist_seqr::mean 72.875587 -system.ruby.LD.miss_latency_hist_seqr::gmean 69.678801 -system.ruby.LD.miss_latency_hist_seqr::stdev 27.158723 -system.ruby.LD.miss_latency_hist_seqr | 84 19.72% 19.72% | 337 79.11% 98.83% | 2 0.47% 99.30% | 0 0.00% 99.30% | 2 0.47% 99.77% | 1 0.23% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.miss_latency_hist_seqr::mean 75.791080 +system.ruby.LD.miss_latency_hist_seqr::gmean 72.234894 +system.ruby.LD.miss_latency_hist_seqr::stdev 27.150058 +system.ruby.LD.miss_latency_hist_seqr | 95 22.30% 22.30% | 327 76.76% 99.06% | 2 0.47% 99.53% | 0 0.00% 99.53% | 0 0.00% 99.53% | 2 0.47% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.miss_latency_hist_seqr::total 426 system.ruby.ST.latency_hist_seqr::bucket_size 32 system.ruby.ST.latency_hist_seqr::max_bucket 319 system.ruby.ST.latency_hist_seqr::samples 865 -system.ruby.ST.latency_hist_seqr::mean 13.996532 -system.ruby.ST.latency_hist_seqr::gmean 2.581393 -system.ruby.ST.latency_hist_seqr::stdev 26.004028 -system.ruby.ST.latency_hist_seqr | 697 80.58% 80.58% | 78 9.02% 89.60% | 85 9.83% 99.42% | 3 0.35% 99.77% | 0 0.00% 99.77% | 1 0.12% 99.88% | 1 0.12% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.latency_hist_seqr::mean 14.804624 +system.ruby.ST.latency_hist_seqr::gmean 2.602855 +system.ruby.ST.latency_hist_seqr::stdev 29.163214 +system.ruby.ST.latency_hist_seqr | 697 80.58% 80.58% | 80 9.25% 89.83% | 83 9.60% 99.42% | 2 0.23% 99.65% | 0 0.00% 99.65% | 1 0.12% 99.77% | 0 0.00% 99.77% | 1 0.12% 99.88% | 0 0.00% 99.88% | 1 0.12% 100.00% system.ruby.ST.latency_hist_seqr::total 865 system.ruby.ST.hit_latency_hist_seqr::bucket_size 4 system.ruby.ST.hit_latency_hist_seqr::max_bucket 39 system.ruby.ST.hit_latency_hist_seqr::samples 697 -system.ruby.ST.hit_latency_hist_seqr::mean 2.305595 -system.ruby.ST.hit_latency_hist_seqr::gmean 1.210352 -system.ruby.ST.hit_latency_hist_seqr::stdev 5.118132 -system.ruby.ST.hit_latency_hist_seqr | 654 93.83% 93.83% | 0 0.00% 93.83% | 0 0.00% 93.83% | 0 0.00% 93.83% | 0 0.00% 93.83% | 21 3.01% 96.84% | 22 3.16% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.hit_latency_hist_seqr::mean 2.317073 +system.ruby.ST.hit_latency_hist_seqr::gmean 1.210984 +system.ruby.ST.hit_latency_hist_seqr::stdev 5.162159 +system.ruby.ST.hit_latency_hist_seqr | 654 93.83% 93.83% | 0 0.00% 93.83% | 0 0.00% 93.83% | 0 0.00% 93.83% | 0 0.00% 93.83% | 20 2.87% 96.70% | 23 3.30% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ST.hit_latency_hist_seqr::total 697 system.ruby.ST.miss_latency_hist_seqr::bucket_size 32 system.ruby.ST.miss_latency_hist_seqr::max_bucket 319 system.ruby.ST.miss_latency_hist_seqr::samples 168 -system.ruby.ST.miss_latency_hist_seqr::mean 62.500000 -system.ruby.ST.miss_latency_hist_seqr::gmean 59.782556 -system.ruby.ST.miss_latency_hist_seqr::stdev 21.264516 -system.ruby.ST.miss_latency_hist_seqr | 0 0.00% 0.00% | 78 46.43% 46.43% | 85 50.60% 97.02% | 3 1.79% 98.81% | 0 0.00% 98.81% | 1 0.60% 99.40% | 1 0.60% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.miss_latency_hist_seqr::mean 66.613095 +system.ruby.ST.miss_latency_hist_seqr::gmean 62.251080 +system.ruby.ST.miss_latency_hist_seqr::stdev 30.627944 +system.ruby.ST.miss_latency_hist_seqr | 0 0.00% 0.00% | 80 47.62% 47.62% | 83 49.40% 97.02% | 2 1.19% 98.21% | 0 0.00% 98.21% | 1 0.60% 98.81% | 0 0.00% 98.81% | 1 0.60% 99.40% | 0 0.00% 99.40% | 1 0.60% 100.00% system.ruby.ST.miss_latency_hist_seqr::total 168 system.ruby.IFETCH.latency_hist_seqr::bucket_size 64 system.ruby.IFETCH.latency_hist_seqr::max_bucket 639 system.ruby.IFETCH.latency_hist_seqr::samples 6413 -system.ruby.IFETCH.latency_hist_seqr::mean 8.354748 -system.ruby.IFETCH.latency_hist_seqr::gmean 1.531676 -system.ruby.IFETCH.latency_hist_seqr::stdev 24.237273 -system.ruby.IFETCH.latency_hist_seqr | 5828 90.88% 90.88% | 571 8.90% 99.78% | 5 0.08% 99.86% | 3 0.05% 99.91% | 3 0.05% 99.95% | 3 0.05% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.latency_hist_seqr::mean 8.941369 +system.ruby.IFETCH.latency_hist_seqr::gmean 1.542249 +system.ruby.IFETCH.latency_hist_seqr::stdev 26.742382 +system.ruby.IFETCH.latency_hist_seqr | 5828 90.88% 90.88% | 571 8.90% 99.78% | 4 0.06% 99.84% | 2 0.03% 99.88% | 4 0.06% 99.94% | 3 0.05% 99.98% | 0 0.00% 99.98% | 0 0.00% 99.98% | 0 0.00% 99.98% | 1 0.02% 100.00% system.ruby.IFETCH.latency_hist_seqr::total 6413 system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 8 system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 79 @@ -619,10 +628,10 @@ system.ruby.IFETCH.hit_latency_hist_seqr::total 5828 system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 64 system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 639 system.ruby.IFETCH.miss_latency_hist_seqr::samples 585 -system.ruby.IFETCH.miss_latency_hist_seqr::mean 79.200000 -system.ruby.IFETCH.miss_latency_hist_seqr::gmean 76.837583 -system.ruby.IFETCH.miss_latency_hist_seqr::stdev 29.345532 -system.ruby.IFETCH.miss_latency_hist_seqr | 0 0.00% 0.00% | 571 97.61% 97.61% | 5 0.85% 98.46% | 3 0.51% 98.97% | 3 0.51% 99.49% | 3 0.51% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.miss_latency_hist_seqr::mean 85.630769 +system.ruby.IFETCH.miss_latency_hist_seqr::gmean 82.856413 +system.ruby.IFETCH.miss_latency_hist_seqr::stdev 36.234733 +system.ruby.IFETCH.miss_latency_hist_seqr | 0 0.00% 0.00% | 571 97.61% 97.61% | 4 0.68% 98.29% | 2 0.34% 98.63% | 4 0.68% 99.32% | 3 0.51% 99.83% | 0 0.00% 99.83% | 0 0.00% 99.83% | 0 0.00% 99.83% | 1 0.17% 100.00% system.ruby.IFETCH.miss_latency_hist_seqr::total 585 system.ruby.L1Cache.hit_mach_latency_hist_seqr::bucket_size 1 system.ruby.L1Cache.hit_mach_latency_hist_seqr::max_bucket 9 @@ -634,18 +643,18 @@ system.ruby.L1Cache.hit_mach_latency_hist_seqr::total 7080 system.ruby.L2Cache.hit_mach_latency_hist_seqr::bucket_size 8 system.ruby.L2Cache.hit_mach_latency_hist_seqr::max_bucket 79 system.ruby.L2Cache.hit_mach_latency_hist_seqr::samples 204 -system.ruby.L2Cache.hit_mach_latency_hist_seqr::mean 23.691176 -system.ruby.L2Cache.hit_mach_latency_hist_seqr::gmean 23.640301 -system.ruby.L2Cache.hit_mach_latency_hist_seqr::stdev 1.636324 +system.ruby.L2Cache.hit_mach_latency_hist_seqr::mean 23.710784 +system.ruby.L2Cache.hit_mach_latency_hist_seqr::gmean 23.661395 +system.ruby.L2Cache.hit_mach_latency_hist_seqr::stdev 1.615711 system.ruby.L2Cache.hit_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 21 10.29% 10.29% | 182 89.22% 99.51% | 0 0.00% 99.51% | 1 0.49% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.L2Cache.hit_mach_latency_hist_seqr::total 204 system.ruby.Directory.miss_mach_latency_hist_seqr::bucket_size 64 system.ruby.Directory.miss_mach_latency_hist_seqr::max_bucket 639 system.ruby.Directory.miss_mach_latency_hist_seqr::samples 1179 -system.ruby.Directory.miss_mach_latency_hist_seqr::mean 74.535199 -system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 71.564149 -system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 28.099799 -system.ruby.Directory.miss_mach_latency_hist_seqr | 162 13.74% 13.74% | 996 84.48% 98.22% | 8 0.68% 98.90% | 4 0.34% 99.24% | 5 0.42% 99.66% | 4 0.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_mach_latency_hist_seqr::mean 79.365564 +system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 75.701428 +system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 33.123085 +system.ruby.Directory.miss_mach_latency_hist_seqr | 175 14.84% 14.84% | 983 83.38% 98.22% | 7 0.59% 98.81% | 3 0.25% 99.07% | 5 0.42% 99.49% | 5 0.42% 99.92% | 0 0.00% 99.92% | 0 0.00% 99.92% | 0 0.00% 99.92% | 1 0.08% 100.00% system.ruby.Directory.miss_mach_latency_hist_seqr::total 1179 system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::bucket_size 1 system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::max_bucket 9 @@ -683,17 +692,18 @@ system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::total 659 system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::bucket_size 4 system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::max_bucket 39 system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::samples 100 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::mean 24 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::gmean 24.000000 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 100 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::mean 23.960000 +system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::gmean 23.956283 +system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::stdev 0.400000 +system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 1.00% 1.00% | 99 99.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::total 100 system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples 426 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 72.875587 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 69.678801 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 27.158723 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 84 19.72% 19.72% | 337 79.11% 98.83% | 2 0.47% 99.30% | 0 0.00% 99.30% | 2 0.47% 99.77% | 1 0.23% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 75.791080 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 72.234894 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 27.150058 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 95 22.30% 22.30% | 327 76.76% 99.06% | 2 0.47% 99.53% | 0 0.00% 99.53% | 0 0.00% 99.53% | 2 0.47% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total 426 system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::bucket_size 1 system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::max_bucket 9 @@ -705,18 +715,18 @@ system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::total 654 system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::bucket_size 4 system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::max_bucket 39 system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::samples 43 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::mean 22.162791 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::gmean 22.076919 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::stdev 1.963115 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 21 48.84% 48.84% | 22 51.16% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::mean 22.348837 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::gmean 22.264733 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::stdev 1.938135 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 20 46.51% 46.51% | 23 53.49% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::total 43 system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size 32 system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket 319 system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::samples 168 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 62.500000 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 59.782556 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 21.264516 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 78 46.43% 46.43% | 85 50.60% 97.02% | 3 1.79% 98.81% | 0 0.00% 98.81% | 1 0.60% 99.40% | 1 0.60% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 66.613095 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 62.251080 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 30.627944 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 80 47.62% 47.62% | 83 49.40% 97.02% | 2 1.19% 98.21% | 0 0.00% 98.21% | 1 0.60% 98.81% | 0 0.00% 98.81% | 1 0.60% 99.40% | 0 0.00% 99.40% | 1 0.60% 100.00% system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total 168 system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::bucket_size 1 system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::max_bucket 9 @@ -736,15 +746,15 @@ system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::total 61 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::samples 585 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 79.200000 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 76.837583 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 29.345532 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 571 97.61% 97.61% | 5 0.85% 98.46% | 3 0.51% 98.97% | 3 0.51% 99.49% | 3 0.51% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 85.630769 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 82.856413 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 36.234733 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 571 97.61% 97.61% | 4 0.68% 98.29% | 2 0.34% 98.63% | 4 0.68% 99.32% | 3 0.51% 99.83% | 0 0.00% 99.83% | 0 0.00% 99.83% | 0 0.00% 99.83% | 1 0.17% 100.00% system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::total 585 system.ruby.Directory_Controller.GETX 208 0.00% 0.00% system.ruby.Directory_Controller.GETS 1017 0.00% 0.00% -system.ruby.Directory_Controller.Lockdown 13 0.00% 0.00% -system.ruby.Directory_Controller.Unlockdown 13 0.00% 0.00% +system.ruby.Directory_Controller.Lockdown 11 0.00% 0.00% +system.ruby.Directory_Controller.Unlockdown 11 0.00% 0.00% system.ruby.Directory_Controller.Data_Owner 9 0.00% 0.00% system.ruby.Directory_Controller.Data_All_Tokens 220 0.00% 0.00% system.ruby.Directory_Controller.Ack_Owner 29 0.00% 0.00% @@ -756,12 +766,11 @@ system.ruby.Directory_Controller.O.GETX 168 0.00% 0.00% system.ruby.Directory_Controller.O.GETS 1011 0.00% 0.00% system.ruby.Directory_Controller.O.Ack_All_Tokens 34 0.00% 0.00% system.ruby.Directory_Controller.NO.GETX 17 0.00% 0.00% -system.ruby.Directory_Controller.NO.Lockdown 2 0.00% 0.00% system.ruby.Directory_Controller.NO.Data_Owner 9 0.00% 0.00% system.ruby.Directory_Controller.NO.Data_All_Tokens 220 0.00% 0.00% system.ruby.Directory_Controller.NO.Ack_Owner 29 0.00% 0.00% system.ruby.Directory_Controller.NO.Ack_Owner_All_Tokens 905 0.00% 0.00% -system.ruby.Directory_Controller.L.Unlockdown 13 0.00% 0.00% +system.ruby.Directory_Controller.L.Unlockdown 11 0.00% 0.00% system.ruby.Directory_Controller.O_W.GETX 23 0.00% 0.00% system.ruby.Directory_Controller.O_W.GETS 6 0.00% 0.00% system.ruby.Directory_Controller.O_W.Memory_Ack 229 0.00% 0.00% @@ -775,8 +784,8 @@ system.ruby.L1Cache_Controller.L1_Replacement 1368 0.00% 0.00% system.ruby.L1Cache_Controller.Data_Shared 161 0.00% 0.00% system.ruby.L1Cache_Controller.Data_All_Tokens 1222 0.00% 0.00% system.ruby.L1Cache_Controller.Ack 1 0.00% 0.00% -system.ruby.L1Cache_Controller.Own_Lock_or_Unlock 26 0.00% 0.00% -system.ruby.L1Cache_Controller.Request_Timeout 13 0.00% 0.00% +system.ruby.L1Cache_Controller.Own_Lock_or_Unlock 22 0.00% 0.00% +system.ruby.L1Cache_Controller.Request_Timeout 11 0.00% 0.00% system.ruby.L1Cache_Controller.Use_TimeoutNoStarvers 1221 0.00% 0.00% system.ruby.L1Cache_Controller.NP.Load 526 0.00% 0.00% system.ruby.L1Cache_Controller.NP.Ifetch 646 0.00% 0.00% @@ -786,15 +795,15 @@ system.ruby.L1Cache_Controller.S.Ifetch 331 0.00% 0.00% system.ruby.L1Cache_Controller.S.Store 20 0.00% 0.00% system.ruby.L1Cache_Controller.S.L1_Replacement 141 0.00% 0.00% system.ruby.L1Cache_Controller.M.Load 181 0.00% 0.00% -system.ruby.L1Cache_Controller.M.Ifetch 3194 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Ifetch 3196 0.00% 0.00% system.ruby.L1Cache_Controller.M.Store 33 0.00% 0.00% system.ruby.L1Cache_Controller.M.L1_Replacement 946 0.00% 0.00% -system.ruby.L1Cache_Controller.M.Own_Lock_or_Unlock 13 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Own_Lock_or_Unlock 11 0.00% 0.00% system.ruby.L1Cache_Controller.MM.Load 218 0.00% 0.00% system.ruby.L1Cache_Controller.MM.Store 265 0.00% 0.00% system.ruby.L1Cache_Controller.MM.L1_Replacement 268 0.00% 0.00% system.ruby.L1Cache_Controller.M_W.Load 84 0.00% 0.00% -system.ruby.L1Cache_Controller.M_W.Ifetch 2242 0.00% 0.00% +system.ruby.L1Cache_Controller.M_W.Ifetch 2240 0.00% 0.00% system.ruby.L1Cache_Controller.M_W.Store 25 0.00% 0.00% system.ruby.L1Cache_Controller.M_W.L1_Replacement 9 0.00% 0.00% system.ruby.L1Cache_Controller.M_W.Use_TimeoutNoStarvers 985 0.00% 0.00% @@ -807,21 +816,21 @@ system.ruby.L1Cache_Controller.IM.Ack 1 0.00% 0.00% system.ruby.L1Cache_Controller.SM.Data_All_Tokens 20 0.00% 0.00% system.ruby.L1Cache_Controller.IS.Data_Shared 161 0.00% 0.00% system.ruby.L1Cache_Controller.IS.Data_All_Tokens 1011 0.00% 0.00% -system.ruby.L1Cache_Controller.IS.Own_Lock_or_Unlock 13 0.00% 0.00% -system.ruby.L1Cache_Controller.IS.Request_Timeout 13 0.00% 0.00% +system.ruby.L1Cache_Controller.IS.Own_Lock_or_Unlock 11 0.00% 0.00% +system.ruby.L1Cache_Controller.IS.Request_Timeout 11 0.00% 0.00% system.ruby.L2Cache_Controller.L1_GETS 1123 0.00% 0.00% system.ruby.L2Cache_Controller.L1_GETS_Last_Token 49 0.00% 0.00% system.ruby.L2Cache_Controller.L1_GETX 211 0.00% 0.00% system.ruby.L2Cache_Controller.L2_Replacement 1266 0.00% 0.00% system.ruby.L2Cache_Controller.Writeback_Shared_Data 84 0.00% 0.00% system.ruby.L2Cache_Controller.Writeback_All_Tokens 1271 0.00% 0.00% -system.ruby.L2Cache_Controller.Persistent_GETS 13 0.00% 0.00% -system.ruby.L2Cache_Controller.Own_Lock_or_Unlock 13 0.00% 0.00% +system.ruby.L2Cache_Controller.Persistent_GETS 11 0.00% 0.00% +system.ruby.L2Cache_Controller.Own_Lock_or_Unlock 11 0.00% 0.00% system.ruby.L2Cache_Controller.NP.L1_GETS 1011 0.00% 0.00% system.ruby.L2Cache_Controller.NP.L1_GETX 166 0.00% 0.00% system.ruby.L2Cache_Controller.NP.Writeback_Shared_Data 81 0.00% 0.00% system.ruby.L2Cache_Controller.NP.Writeback_All_Tokens 1193 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.Own_Lock_or_Unlock 13 0.00% 0.00% +system.ruby.L2Cache_Controller.NP.Own_Lock_or_Unlock 11 0.00% 0.00% system.ruby.L2Cache_Controller.I.L1_GETX 1 0.00% 0.00% system.ruby.L2Cache_Controller.I.L2_Replacement 69 0.00% 0.00% system.ruby.L2Cache_Controller.I.Writeback_Shared_Data 3 0.00% 0.00% @@ -835,6 +844,6 @@ system.ruby.L2Cache_Controller.O.Writeback_All_Tokens 57 0.00% system.ruby.L2Cache_Controller.M.L1_GETS 112 0.00% 0.00% system.ruby.L2Cache_Controller.M.L1_GETX 26 0.00% 0.00% system.ruby.L2Cache_Controller.M.L2_Replacement 1125 0.00% 0.00% -system.ruby.L2Cache_Controller.I_L.Persistent_GETS 13 0.00% 0.00% +system.ruby.L2Cache_Controller.I_L.Persistent_GETS 11 0.00% 0.00% ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini index 2fd013908..293c2e7fd 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini @@ -14,6 +14,7 @@ children=clk_domain cpu dvfs_handler mem_ctrls ruby sys_port_proxy voltage_domai boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 exit_on_work_items=false init_param=0 @@ -22,11 +23,15 @@ kernel_addr_check=true load_addr_mask=1099511627775 load_offset=0 mem_mode=timing -mem_ranges=0:268435455 +mem_ranges=0:268435455:0:0:0:0 memories=system.mem_ctrls mmap_using_noreserve=false multi_thread=false num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null readfile= symbolfile= thermal_components= @@ -55,6 +60,7 @@ branchPred=Null checker=Null clk_domain=system.cpu.clk_domain cpu_id=0 +default_p_state=UNDEFINED do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true @@ -70,6 +76,10 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null profile=0 progress_interval=0 simpoint_start_insts= @@ -122,7 +132,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/hello/bin/alpha/linux/hello +executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin kvmInSE=false @@ -145,27 +155,27 @@ transition_latency=100000 [system.mem_ctrls] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -177,6 +187,7 @@ burst_length=8 channels=1 clk_domain=system.clk_domain conf_table_reported=true +default_p_state=UNDEFINED device_bus_width=8 device_rowbuffer_size=1024 device_size=536870912 @@ -184,12 +195,17 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 page_policy=open_adaptive -range=0:268435455 +power_model=Null +range=0:268435455:5:19:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10 @@ -211,9 +227,9 @@ tRTW=3 tWR=15 tWTR=8 tXAW=30 -tXP=0 +tXP=6 tXPDLL=0 -tXS=0 +tXS=270 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 @@ -227,12 +243,17 @@ access_backing_store=false all_instructions=false block_size_bytes=64 clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED eventq_index=0 hot_lines=false memory_size_bits=48 num_of_sequencers=1 number_of_virtual_networks=6 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 phys_mem=Null +power_model=Null randomization=false [system.ruby.clk_domain] @@ -249,6 +270,7 @@ children=directory dmaRequestToDir dmaResponseFromDir forwardFromDir probeFilter buffer_size=0 clk_domain=system.ruby.clk_domain cluster_id=0 +default_p_state=UNDEFINED directory=system.ruby.dir_cntrl0.directory dmaRequestToDir=system.ruby.dir_cntrl0.dmaRequestToDir dmaResponseFromDir=system.ruby.dir_cntrl0.dmaResponseFromDir @@ -257,6 +279,10 @@ forwardFromDir=system.ruby.dir_cntrl0.forwardFromDir from_memory_controller_latency=2 full_bit_dir_enabled=false number_of_TBEs=256 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null probeFilter=system.ruby.dir_cntrl0.probeFilter probe_filter_enabled=false recycle_latency=10 @@ -384,6 +410,7 @@ buffer_size=0 cache_response_latency=10 clk_domain=system.cpu.clk_domain cluster_id=0 +default_p_state=UNDEFINED eventq_index=0 forwardToCache=system.ruby.l1_cntrl0.forwardToCache issue_latency=2 @@ -391,6 +418,10 @@ l2_cache_hit_latency=10 mandatoryQueue=system.ruby.l1_cntrl0.mandatoryQueue no_mig_atomic=true number_of_TBEs=256 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null recycle_latency=10 requestFromCache=system.ruby.l1_cntrl0.requestFromCache responseFromCache=system.ruby.l1_cntrl0.responseFromCache @@ -522,17 +553,22 @@ coreid=99 dcache=system.ruby.l1_cntrl0.L1Dcache dcache_hit_latency=1 deadlock_threshold=500000 +default_p_state=UNDEFINED eventq_index=0 +garnet_standalone=false icache=system.ruby.l1_cntrl0.L1Icache icache_hit_latency=1 is_cpu_sequencer=true max_outstanding_requests=16 no_retry_on_stall=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null ruby_system=system.ruby support_data_reqs=true support_inst_reqs=true system=system -using_network_tester=false using_ruby_tester=false version=0 slave=system.cpu.icache_port system.cpu.dcache_port @@ -560,18 +596,23 @@ eventq_index=0 [system.ruby.network] type=SimpleNetwork -children=ext_links0 ext_links1 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_link_buffers20 int_link_buffers21 int_link_buffers22 int_link_buffers23 int_links0 int_links1 routers0 routers1 routers2 +children=ext_links0 ext_links1 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_link_buffers20 int_link_buffers21 int_link_buffers22 int_link_buffers23 int_link_buffers24 int_link_buffers25 int_link_buffers26 int_link_buffers27 int_link_buffers28 int_link_buffers29 int_link_buffers30 int_link_buffers31 int_link_buffers32 int_link_buffers33 int_link_buffers34 int_link_buffers35 int_link_buffers36 int_link_buffers37 int_link_buffers38 int_link_buffers39 int_link_buffers40 int_link_buffers41 int_link_buffers42 int_link_buffers43 int_link_buffers44 int_link_buffers45 int_link_buffers46 int_link_buffers47 int_links0 int_links1 int_links2 int_links3 routers0 routers1 routers2 adaptive_routing=false buffer_size=0 clk_domain=system.ruby.clk_domain control_msg_size=8 +default_p_state=UNDEFINED endpoint_bandwidth=1000 eventq_index=0 ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1 -int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19 system.ruby.network.int_link_buffers20 system.ruby.network.int_link_buffers21 system.ruby.network.int_link_buffers22 system.ruby.network.int_link_buffers23 -int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 +int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19 system.ruby.network.int_link_buffers20 system.ruby.network.int_link_buffers21 system.ruby.network.int_link_buffers22 system.ruby.network.int_link_buffers23 system.ruby.network.int_link_buffers24 system.ruby.network.int_link_buffers25 system.ruby.network.int_link_buffers26 system.ruby.network.int_link_buffers27 system.ruby.network.int_link_buffers28 system.ruby.network.int_link_buffers29 system.ruby.network.int_link_buffers30 system.ruby.network.int_link_buffers31 system.ruby.network.int_link_buffers32 system.ruby.network.int_link_buffers33 system.ruby.network.int_link_buffers34 system.ruby.network.int_link_buffers35 system.ruby.network.int_link_buffers36 system.ruby.network.int_link_buffers37 system.ruby.network.int_link_buffers38 system.ruby.network.int_link_buffers39 system.ruby.network.int_link_buffers40 system.ruby.network.int_link_buffers41 system.ruby.network.int_link_buffers42 system.ruby.network.int_link_buffers43 system.ruby.network.int_link_buffers44 system.ruby.network.int_link_buffers45 system.ruby.network.int_link_buffers46 system.ruby.network.int_link_buffers47 +int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2 system.ruby.network.int_links3 netifs= number_of_virtual_networks=6 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null routers=system.ruby.network.routers0 system.ruby.network.routers1 system.ruby.network.routers2 ruby_system=system.ruby topology=Crossbar @@ -766,32 +807,234 @@ eventq_index=0 ordered=true randomization=false +[system.ruby.network.int_link_buffers24] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers25] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers26] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers27] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers28] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers29] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers30] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers31] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers32] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers33] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers34] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers35] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers36] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers37] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers38] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers39] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers40] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers41] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers42] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers43] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers44] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers45] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers46] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers47] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + [system.ruby.network.int_links0] type=SimpleIntLink bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers2 eventq_index=0 latency=1 link_id=2 -node_a=system.ruby.network.routers0 -node_b=system.ruby.network.routers2 +src_node=system.ruby.network.routers0 +src_outport= weight=1 [system.ruby.network.int_links1] type=SimpleIntLink bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers2 eventq_index=0 latency=1 link_id=3 -node_a=system.ruby.network.routers1 -node_b=system.ruby.network.routers2 +src_node=system.ruby.network.routers1 +src_outport= +weight=1 + +[system.ruby.network.int_links2] +type=SimpleIntLink +bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers0 +eventq_index=0 +latency=1 +link_id=4 +src_node=system.ruby.network.routers2 +src_outport= +weight=1 + +[system.ruby.network.int_links3] +type=SimpleIntLink +bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers1 +eventq_index=0 +latency=1 +link_id=5 +src_node=system.ruby.network.routers2 +src_outport= weight=1 [system.ruby.network.routers0] type=Switch children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17 clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED eventq_index=0 +latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 port_buffers=system.ruby.network.routers0.port_buffers00 system.ruby.network.routers0.port_buffers01 system.ruby.network.routers0.port_buffers02 system.ruby.network.routers0.port_buffers03 system.ruby.network.routers0.port_buffers04 system.ruby.network.routers0.port_buffers05 system.ruby.network.routers0.port_buffers06 system.ruby.network.routers0.port_buffers07 system.ruby.network.routers0.port_buffers08 system.ruby.network.routers0.port_buffers09 system.ruby.network.routers0.port_buffers10 system.ruby.network.routers0.port_buffers11 system.ruby.network.routers0.port_buffers12 system.ruby.network.routers0.port_buffers13 system.ruby.network.routers0.port_buffers14 system.ruby.network.routers0.port_buffers15 system.ruby.network.routers0.port_buffers16 system.ruby.network.routers0.port_buffers17 +power_model=Null router_id=0 virt_nets=6 @@ -925,8 +1168,14 @@ randomization=false type=Switch children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17 clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED eventq_index=0 +latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 port_buffers=system.ruby.network.routers1.port_buffers00 system.ruby.network.routers1.port_buffers01 system.ruby.network.routers1.port_buffers02 system.ruby.network.routers1.port_buffers03 system.ruby.network.routers1.port_buffers04 system.ruby.network.routers1.port_buffers05 system.ruby.network.routers1.port_buffers06 system.ruby.network.routers1.port_buffers07 system.ruby.network.routers1.port_buffers08 system.ruby.network.routers1.port_buffers09 system.ruby.network.routers1.port_buffers10 system.ruby.network.routers1.port_buffers11 system.ruby.network.routers1.port_buffers12 system.ruby.network.routers1.port_buffers13 system.ruby.network.routers1.port_buffers14 system.ruby.network.routers1.port_buffers15 system.ruby.network.routers1.port_buffers16 system.ruby.network.routers1.port_buffers17 +power_model=Null router_id=1 virt_nets=6 @@ -1060,8 +1309,14 @@ randomization=false type=Switch children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17 port_buffers18 port_buffers19 port_buffers20 port_buffers21 port_buffers22 port_buffers23 clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED eventq_index=0 +latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 port_buffers=system.ruby.network.routers2.port_buffers00 system.ruby.network.routers2.port_buffers01 system.ruby.network.routers2.port_buffers02 system.ruby.network.routers2.port_buffers03 system.ruby.network.routers2.port_buffers04 system.ruby.network.routers2.port_buffers05 system.ruby.network.routers2.port_buffers06 system.ruby.network.routers2.port_buffers07 system.ruby.network.routers2.port_buffers08 system.ruby.network.routers2.port_buffers09 system.ruby.network.routers2.port_buffers10 system.ruby.network.routers2.port_buffers11 system.ruby.network.routers2.port_buffers12 system.ruby.network.routers2.port_buffers13 system.ruby.network.routers2.port_buffers14 system.ruby.network.routers2.port_buffers15 system.ruby.network.routers2.port_buffers16 system.ruby.network.routers2.port_buffers17 system.ruby.network.routers2.port_buffers18 system.ruby.network.routers2.port_buffers19 system.ruby.network.routers2.port_buffers20 system.ruby.network.routers2.port_buffers21 system.ruby.network.routers2.port_buffers22 system.ruby.network.routers2.port_buffers23 +power_model=Null router_id=2 virt_nets=6 @@ -1236,9 +1491,14 @@ randomization=false [system.sys_port_proxy] type=RubyPortProxy clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 is_cpu_sequencer=true no_retry_on_stall=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null ruby_system=system.ruby support_data_reqs=true support_inst_reqs=true diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simerr b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simerr index ccfdd3697..f6f6f15a5 100755 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simerr +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simerr @@ -4,8 +4,7 @@ warn: rounding error > tolerance 1.250000 rounded to 1 warn: rounding error > tolerance 1.250000 rounded to 1 -warn: rounding error > tolerance - 1.250000 rounded to 1 warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes) warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files! diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout index 2d739759e..df46cff97 100755 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout @@ -3,13 +3,13 @@ Redirecting stderr to build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 14 2016 21:55:52 -gem5 started Mar 14 2016 21:57:33 -gem5 executing on phenom, pid 28167 -command line: build/ALPHA_MOESI_hammer/gem5.opt -d build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer +gem5 compiled Oct 13 2016 20:24:36 +gem5 started Oct 13 2016 20:24:58 +gem5 executing on e108600-lin, pid 38872 +command line: /work/curdun01/gem5-external.hg/build/ALPHA_MOESI_hammer/gem5.opt -d build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 86770 because target called exit() +Exiting @ tick 93323 because target called exit() diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt index 9d52394d3..56d6a64b0 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000087 # Number of seconds simulated -sim_ticks 86770 # Number of ticks simulated -final_tick 86770 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000093 # Number of seconds simulated +sim_ticks 93323 # Number of ticks simulated +final_tick 93323 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 95809 # Simulator instruction rate (inst/s) -host_op_rate 95795 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1297998 # Simulator tick rate (ticks/s) -host_mem_usage 453692 # Number of bytes of host memory used -host_seconds 0.07 # Real time elapsed on the host +host_inst_rate 48908 # Simulator instruction rate (inst/s) +host_op_rate 48899 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 712591 # Simulator tick rate (ticks/s) +host_mem_usage 412484 # Number of bytes of host memory used +host_seconds 0.13 # Real time elapsed on the host sim_insts 6403 # Number of instructions simulated sim_ops 6403 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks -system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 86770 # Cumulative time (in ticks) in various power states +system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 93323 # Cumulative time (in ticks) in various power states system.mem_ctrls.bytes_read::ruby.dir_cntrl0 74240 # Number of bytes read from this memory system.mem_ctrls.bytes_read::total 74240 # Number of bytes read from this memory system.mem_ctrls.bytes_written::ruby.dir_cntrl0 14080 # Number of bytes written to this memory @@ -22,29 +22,29 @@ system.mem_ctrls.num_reads::ruby.dir_cntrl0 1160 # system.mem_ctrls.num_reads::total 1160 # Number of read requests responded to by this memory system.mem_ctrls.num_writes::ruby.dir_cntrl0 220 # Number of write requests responded to by this memory system.mem_ctrls.num_writes::total 220 # Number of write requests responded to by this memory -system.mem_ctrls.bw_read::ruby.dir_cntrl0 855595252 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_read::total 855595252 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::ruby.dir_cntrl0 162268065 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::total 162268065 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_total::ruby.dir_cntrl0 1017863317 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.bw_total::total 1017863317 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_read::ruby.dir_cntrl0 795516646 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 795516646 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::ruby.dir_cntrl0 150873847 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::total 150873847 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::ruby.dir_cntrl0 946390493 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 946390493 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrls.readReqs 1160 # Number of read requests accepted system.mem_ctrls.writeReqs 220 # Number of write requests accepted system.mem_ctrls.readBursts 1160 # Number of DRAM read bursts, including those serviced by the write queue system.mem_ctrls.writeBursts 220 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrls.bytesReadDRAM 63744 # Total number of bytes read from DRAM -system.mem_ctrls.bytesReadWrQ 10496 # Total number of bytes read from write queue -system.mem_ctrls.bytesWritten 5504 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadDRAM 63488 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 10752 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 5248 # Total number of bytes written to DRAM system.mem_ctrls.bytesReadSys 74240 # Total read bytes from the system interface side system.mem_ctrls.bytesWrittenSys 14080 # Total written bytes from the system interface side -system.mem_ctrls.servicedByWrQ 164 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.servicedByWrQ 168 # Number of DRAM read bursts serviced by the write queue system.mem_ctrls.mergedWrBursts 109 # Number of DRAM write bursts merged with an existing one system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.mem_ctrls.perBankRdBursts::0 86 # Per bank write bursts system.mem_ctrls.perBankRdBursts::1 52 # Per bank write bursts system.mem_ctrls.perBankRdBursts::2 82 # Per bank write bursts system.mem_ctrls.perBankRdBursts::3 77 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::4 93 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 90 # Per bank write bursts system.mem_ctrls.perBankRdBursts::5 18 # Per bank write bursts system.mem_ctrls.perBankRdBursts::6 1 # Per bank write bursts system.mem_ctrls.perBankRdBursts::7 3 # Per bank write bursts @@ -54,13 +54,13 @@ system.mem_ctrls.perBankRdBursts::10 54 # Pe system.mem_ctrls.perBankRdBursts::11 47 # Per bank write bursts system.mem_ctrls.perBankRdBursts::12 22 # Per bank write bursts system.mem_ctrls.perBankRdBursts::13 358 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::14 61 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 60 # Per bank write bursts system.mem_ctrls.perBankRdBursts::15 41 # Per bank write bursts system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::4 19 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 17 # Per bank write bursts system.mem_ctrls.perBankWrBursts::5 6 # Per bank write bursts system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts @@ -69,12 +69,12 @@ system.mem_ctrls.perBankWrBursts::9 0 # Pe system.mem_ctrls.perBankWrBursts::10 2 # Per bank write bursts system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::13 17 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 15 # Per bank write bursts system.mem_ctrls.perBankWrBursts::14 42 # Per bank write bursts system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrls.totGap 86698 # Total gap between requests +system.mem_ctrls.totGap 93245 # Total gap between requests system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) @@ -89,7 +89,7 @@ system.mem_ctrls.writePktSize::3 0 # Wr system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::6 220 # Write request sizes (log2) -system.mem_ctrls.rdQLenPdf::0 996 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::0 992 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see @@ -136,8 +136,8 @@ system.mem_ctrls.wrQLenPdf::11 1 # Wh system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::15 4 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::16 4 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 2 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 2 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::17 6 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::18 6 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::19 6 # What write queue length does an incoming req see @@ -146,10 +146,10 @@ system.mem_ctrls.wrQLenPdf::21 6 # Wh system.mem_ctrls.wrQLenPdf::22 6 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::23 6 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::24 6 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::25 5 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::26 5 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::27 5 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::28 5 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 6 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 6 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 6 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::28 6 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::29 5 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::30 5 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::31 5 # What write queue length does an incoming req see @@ -185,87 +185,98 @@ system.mem_ctrls.wrQLenPdf::60 0 # Wh system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrls.bytesPerActivate::samples 191 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::mean 358.869110 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::gmean 215.937059 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::stdev 347.377875 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::0-127 57 29.84% 29.84% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::128-255 46 24.08% 53.93% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::256-383 20 10.47% 64.40% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::384-511 14 7.33% 71.73% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::512-639 10 5.24% 76.96% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::640-767 4 2.09% 79.06% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::768-895 7 3.66% 82.72% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::896-1023 8 4.19% 86.91% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::1024-1151 25 13.09% 100.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::total 191 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::samples 185 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 364.627027 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 225.304848 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 344.102671 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 47 25.41% 25.41% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 51 27.57% 52.97% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 22 11.89% 64.86% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 11 5.95% 70.81% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 10 5.41% 76.22% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 6 3.24% 79.46% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 6 3.24% 82.70% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 9 4.86% 87.57% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 23 12.43% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 185 # Bytes accessed per row activation system.mem_ctrls.rdPerTurnAround::samples 5 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::mean 143.400000 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::gmean 107.861440 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::stdev 83.476344 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::mean 135.600000 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::gmean 103.520831 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::stdev 76.774345 # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::16-23 1 20.00% 20.00% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::120-127 1 20.00% 40.00% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::128-135 1 20.00% 60.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::216-223 2 40.00% 100.00% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::184-191 1 20.00% 80.00% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::216-223 1 20.00% 100.00% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::total 5 # Reads before turning the bus around for writes system.mem_ctrls.wrPerTurnAround::samples 5 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::mean 17.200000 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::gmean 17.171629 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::stdev 1.095445 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::16 2 40.00% 40.00% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::18 3 60.00% 100.00% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::mean 16.400000 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::gmean 16.381380 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::stdev 0.894427 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::16 4 80.00% 80.00% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::18 1 20.00% 100.00% # Writes before turning the bus around for reads system.mem_ctrls.wrPerTurnAround::total 5 # Writes before turning the bus around for reads -system.mem_ctrls.totQLat 6142 # Total ticks spent queuing -system.mem_ctrls.totMemAccLat 25066 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrls.totBusLat 4980 # Total ticks spent in databus transfers -system.mem_ctrls.avgQLat 6.17 # Average queueing delay per DRAM burst +system.mem_ctrls.totQLat 12811 # Total ticks spent queuing +system.mem_ctrls.totMemAccLat 31659 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.totBusLat 4960 # Total ticks spent in databus transfers +system.mem_ctrls.avgQLat 12.91 # Average queueing delay per DRAM burst system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst -system.mem_ctrls.avgMemAccLat 25.17 # Average memory access latency per DRAM burst -system.mem_ctrls.avgRdBW 734.63 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrls.avgWrBW 63.43 # Average achieved write bandwidth in MiByte/s -system.mem_ctrls.avgRdBWSys 855.60 # Average system read bandwidth in MiByte/s -system.mem_ctrls.avgWrBWSys 162.27 # Average system write bandwidth in MiByte/s +system.mem_ctrls.avgMemAccLat 31.91 # Average memory access latency per DRAM burst +system.mem_ctrls.avgRdBW 680.30 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 56.23 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 795.52 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 150.87 # Average system write bandwidth in MiByte/s system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrls.busUtil 6.23 # Data bus utilization in percentage -system.mem_ctrls.busUtilRead 5.74 # Data bus utilization in percentage for reads -system.mem_ctrls.busUtilWrite 0.50 # Data bus utilization in percentage for writes +system.mem_ctrls.busUtil 5.75 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 5.31 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 0.44 # Data bus utilization in percentage for writes system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing -system.mem_ctrls.avgWrQLen 20.55 # Average write queue length when enqueuing -system.mem_ctrls.readRowHits 808 # Number of row buffer hits during reads +system.mem_ctrls.avgWrQLen 22.62 # Average write queue length when enqueuing +system.mem_ctrls.readRowHits 805 # Number of row buffer hits during reads system.mem_ctrls.writeRowHits 78 # Number of row buffer hits during writes -system.mem_ctrls.readRowHitRate 81.12 # Row buffer hit rate for reads +system.mem_ctrls.readRowHitRate 81.15 # Row buffer hit rate for reads system.mem_ctrls.writeRowHitRate 70.27 # Row buffer hit rate for writes -system.mem_ctrls.avgGap 62.82 # Average gap between requests -system.mem_ctrls.pageHitRate 80.04 # Row buffer hit rate, read and write combined -system.mem_ctrls_0.actEnergy 476280 # Energy for activate commands per rank (pJ) -system.mem_ctrls_0.preEnergy 264600 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_0.readEnergy 5091840 # Energy for read commands per rank (pJ) -system.mem_ctrls_0.writeEnergy 259200 # Energy for write commands per rank (pJ) -system.mem_ctrls_0.refreshEnergy 5594160 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_0.actBackEnergy 50178924 # Energy for active background per rank (pJ) -system.mem_ctrls_0.preBackEnergy 7527000 # Energy for precharge background per rank (pJ) -system.mem_ctrls_0.totalEnergy 69392004 # Total energy per rank (pJ) -system.mem_ctrls_0.averagePower 807.766675 # Core power per rank (mW) -system.mem_ctrls_0.memoryStateTime::IDLE 12759 # Time in different power states -system.mem_ctrls_0.memoryStateTime::REF 2860 # Time in different power states -system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT 70795 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrls_1.actEnergy 967680 # Energy for activate commands per rank (pJ) -system.mem_ctrls_1.preEnergy 537600 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_1.readEnergy 7200960 # Energy for read commands per rank (pJ) -system.mem_ctrls_1.writeEnergy 632448 # Energy for write commands per rank (pJ) -system.mem_ctrls_1.refreshEnergy 5594160 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_1.actBackEnergy 57849984 # Energy for active background per rank (pJ) -system.mem_ctrls_1.preBackEnergy 798000 # Energy for precharge background per rank (pJ) -system.mem_ctrls_1.totalEnergy 73580832 # Total energy per rank (pJ) -system.mem_ctrls_1.averagePower 856.527274 # Core power per rank (mW) -system.mem_ctrls_1.memoryStateTime::IDLE 910 # Time in different power states +system.mem_ctrls.avgGap 67.57 # Average gap between requests +system.mem_ctrls.pageHitRate 80.05 # Row buffer hit rate, read and write combined +system.mem_ctrls_0.actEnergy 449820 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 235704 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 4672416 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 192096 # Energy for write commands per rank (pJ) +system.mem_ctrls_0.refreshEnergy 7375680.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 7678128 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 246528 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.actPowerDownEnergy 28111488 # Energy for active power-down per rank (pJ) +system.mem_ctrls_0.prePowerDownEnergy 4554240 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls_0.selfRefreshEnergy 1112640 # Energy for self refresh per rank (pJ) +system.mem_ctrls_0.totalEnergy 54628740 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 585.372738 # Core power per rank (mW) +system.mem_ctrls_0.totalIdleTime 75800 # Total Idle time Per DRAM Rank +system.mem_ctrls_0.memoryStateTime::IDLE 328 # Time in different power states +system.mem_ctrls_0.memoryStateTime::REF 3126 # Time in different power states +system.mem_ctrls_0.memoryStateTime::SREF 2335 # Time in different power states +system.mem_ctrls_0.memoryStateTime::PRE_PDN 11860 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 14026 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT_PDN 61648 # Time in different power states +system.mem_ctrls_1.actEnergy 913920 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 479136 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 6660192 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 492768 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.refreshEnergy 6761040.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 10312440 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 226560 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.actPowerDownEnergy 31424328 # Energy for active power-down per rank (pJ) +system.mem_ctrls_1.prePowerDownEnergy 462720 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls_1.totalEnergy 57733104 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 618.637463 # Core power per rank (mW) +system.mem_ctrls_1.totalIdleTime 69937 # Total Idle time Per DRAM Rank +system.mem_ctrls_1.memoryStateTime::IDLE 212 # Time in different power states system.mem_ctrls_1.memoryStateTime::REF 2860 # Time in different power states -system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT 82150 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 86770 # Cumulative time (in ticks) in various power states +system.mem_ctrls_1.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls_1.memoryStateTime::PRE_PDN 1205 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 20133 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT_PDN 68913 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 93323 # Cumulative time (in ticks) in various power states system.cpu.clk_domain.clock 1 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -300,8 +311,8 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 86770 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 86770 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 93323 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 93323 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 6403 # Number of instructions committed @@ -320,7 +331,7 @@ system.cpu.num_mem_refs 2060 # nu system.cpu.num_load_insts 1192 # Number of load instructions system.cpu.num_store_insts 868 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 86770 # Number of busy cycles +system.cpu.num_busy_cycles 93323 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 1056 # Number of branches fetched @@ -360,7 +371,7 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 6413 # Class of executed instruction system.ruby.clk_domain.clock 1 # Clock period in ticks -system.ruby.pwrStateResidencyTicks::UNDEFINED 86770 # Cumulative time (in ticks) in various power states +system.ruby.pwrStateResidencyTicks::UNDEFINED 93323 # Cumulative time (in ticks) in various power states system.ruby.outstanding_req_hist_seqr::bucket_size 1 system.ruby.outstanding_req_hist_seqr::max_bucket 9 system.ruby.outstanding_req_hist_seqr::samples 8464 @@ -371,10 +382,10 @@ system.ruby.outstanding_req_hist_seqr::total 8464 system.ruby.latency_hist_seqr::bucket_size 64 system.ruby.latency_hist_seqr::max_bucket 639 system.ruby.latency_hist_seqr::samples 8463 -system.ruby.latency_hist_seqr::mean 9.252865 -system.ruby.latency_hist_seqr::gmean 1.840314 -system.ruby.latency_hist_seqr::stdev 22.282539 -system.ruby.latency_hist_seqr | 8231 97.26% 97.26% | 222 2.62% 99.88% | 0 0.00% 99.88% | 1 0.01% 99.89% | 7 0.08% 99.98% | 2 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.latency_hist_seqr::mean 10.027177 +system.ruby.latency_hist_seqr::gmean 1.860537 +system.ruby.latency_hist_seqr::stdev 25.112208 +system.ruby.latency_hist_seqr | 8219 97.12% 97.12% | 231 2.73% 99.85% | 1 0.01% 99.86% | 1 0.01% 99.87% | 5 0.06% 99.93% | 5 0.06% 99.99% | 0 0.00% 99.99% | 0 0.00% 99.99% | 0 0.00% 99.99% | 1 0.01% 100.00% system.ruby.latency_hist_seqr::total 8463 system.ruby.hit_latency_hist_seqr::bucket_size 2 system.ruby.hit_latency_hist_seqr::max_bucket 19 @@ -387,16 +398,16 @@ system.ruby.hit_latency_hist_seqr::total 7303 system.ruby.miss_latency_hist_seqr::bucket_size 64 system.ruby.miss_latency_hist_seqr::max_bucket 639 system.ruby.miss_latency_hist_seqr::samples 1160 -system.ruby.miss_latency_hist_seqr::mean 59.460345 -system.ruby.miss_latency_hist_seqr::gmean 56.276317 -system.ruby.miss_latency_hist_seqr::stdev 26.160126 -system.ruby.miss_latency_hist_seqr | 928 80.00% 80.00% | 222 19.14% 99.14% | 0 0.00% 99.14% | 1 0.09% 99.22% | 7 0.60% 99.83% | 2 0.17% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.miss_latency_hist_seqr::mean 65.109483 +system.ruby.miss_latency_hist_seqr::gmean 60.947221 +system.ruby.miss_latency_hist_seqr::stdev 32.683425 +system.ruby.miss_latency_hist_seqr | 916 78.97% 78.97% | 231 19.91% 98.88% | 1 0.09% 98.97% | 1 0.09% 99.05% | 5 0.43% 99.48% | 5 0.43% 99.91% | 0 0.00% 99.91% | 0 0.00% 99.91% | 0 0.00% 99.91% | 1 0.09% 100.00% system.ruby.miss_latency_hist_seqr::total 1160 system.ruby.Directory.incomplete_times_seqr 1159 system.ruby.dir_cntrl0.probeFilter.demand_hits 0 # Number of cache demand hits system.ruby.dir_cntrl0.probeFilter.demand_misses 0 # Number of cache demand misses system.ruby.dir_cntrl0.probeFilter.demand_accesses 0 # Number of cache demand accesses -system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 86770 # Cumulative time (in ticks) in various power states +system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 93323 # Cumulative time (in ticks) in various power states system.ruby.l1_cntrl0.L1Dcache.demand_hits 1333 # Number of cache demand hits system.ruby.l1_cntrl0.L1Dcache.demand_misses 717 # Number of cache demand misses system.ruby.l1_cntrl0.L1Dcache.demand_accesses 2050 # Number of cache demand accesses @@ -406,12 +417,12 @@ system.ruby.l1_cntrl0.L1Icache.demand_accesses 6413 system.ruby.l1_cntrl0.L2cache.demand_hits 203 # Number of cache demand hits system.ruby.l1_cntrl0.L2cache.demand_misses 1160 # Number of cache demand misses system.ruby.l1_cntrl0.L2cache.demand_accesses 1363 # Number of cache demand accesses -system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 86770 # Cumulative time (in ticks) in various power states -system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 86770 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 93323 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 93323 # Cumulative time (in ticks) in various power states system.ruby.l1_cntrl0.fully_busy_cycles 7 # cycles for which number of transistions == max transitions system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 86770 # Cumulative time (in ticks) in various power states -system.ruby.network.routers0.percent_links_utilized 5.172295 +system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 93323 # Cumulative time (in ticks) in various power states +system.ruby.network.routers0.percent_links_utilized 4.809104 system.ruby.network.routers0.msg_count.Request_Control::2 1160 system.ruby.network.routers0.msg_count.Response_Data::4 1160 system.ruby.network.routers0.msg_count.Writeback_Data::5 220 @@ -426,8 +437,8 @@ system.ruby.network.routers0.msg_bytes.Writeback_Control::2 9152 system.ruby.network.routers0.msg_bytes.Writeback_Control::3 9152 system.ruby.network.routers0.msg_bytes.Writeback_Control::5 7392 system.ruby.network.routers0.msg_bytes.Unblock_Control::5 9280 -system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 86770 # Cumulative time (in ticks) in various power states -system.ruby.network.routers1.percent_links_utilized 5.172006 +system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 93323 # Cumulative time (in ticks) in various power states +system.ruby.network.routers1.percent_links_utilized 4.808836 system.ruby.network.routers1.msg_count.Request_Control::2 1160 system.ruby.network.routers1.msg_count.Response_Data::4 1160 system.ruby.network.routers1.msg_count.Writeback_Data::5 220 @@ -442,8 +453,8 @@ system.ruby.network.routers1.msg_bytes.Writeback_Control::2 9152 system.ruby.network.routers1.msg_bytes.Writeback_Control::3 9152 system.ruby.network.routers1.msg_bytes.Writeback_Control::5 7392 system.ruby.network.routers1.msg_bytes.Unblock_Control::5 9272 -system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 86770 # Cumulative time (in ticks) in various power states -system.ruby.network.routers2.percent_links_utilized 5.172295 +system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 93323 # Cumulative time (in ticks) in various power states +system.ruby.network.routers2.percent_links_utilized 4.809104 system.ruby.network.routers2.msg_count.Request_Control::2 1160 system.ruby.network.routers2.msg_count.Response_Data::4 1160 system.ruby.network.routers2.msg_count.Writeback_Data::5 220 @@ -458,7 +469,7 @@ system.ruby.network.routers2.msg_bytes.Writeback_Control::2 9152 system.ruby.network.routers2.msg_bytes.Writeback_Control::3 9152 system.ruby.network.routers2.msg_bytes.Writeback_Control::5 7392 system.ruby.network.routers2.msg_bytes.Unblock_Control::5 9280 -system.ruby.network.pwrStateResidencyTicks::UNDEFINED 86770 # Cumulative time (in ticks) in various power states +system.ruby.network.pwrStateResidencyTicks::UNDEFINED 93323 # Cumulative time (in ticks) in various power states system.ruby.network.msg_count.Request_Control 3480 system.ruby.network.msg_count.Response_Data 3480 system.ruby.network.msg_count.Writeback_Data 660 @@ -469,13 +480,13 @@ system.ruby.network.msg_byte.Response_Data 250560 system.ruby.network.msg_byte.Writeback_Data 47520 system.ruby.network.msg_byte.Writeback_Control 77088 system.ruby.network.msg_byte.Unblock_Control 27832 -system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 86770 # Cumulative time (in ticks) in various power states -system.ruby.network.routers0.throttle0.link_utilization 6.675118 +system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 93323 # Cumulative time (in ticks) in various power states +system.ruby.network.routers0.throttle0.link_utilization 6.206401 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1160 system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 1144 system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 83520 system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 9152 -system.ruby.network.routers0.throttle1.link_utilization 3.669471 +system.ruby.network.routers0.throttle1.link_utilization 3.411806 system.ruby.network.routers0.throttle1.msg_count.Request_Control::2 1160 system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::5 220 system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::2 1144 @@ -486,7 +497,7 @@ system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::5 15840 system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::2 9152 system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::5 7392 system.ruby.network.routers0.throttle1.msg_bytes.Unblock_Control::5 9280 -system.ruby.network.routers1.throttle0.link_utilization 3.668895 +system.ruby.network.routers1.throttle0.link_utilization 3.411271 system.ruby.network.routers1.throttle0.msg_count.Request_Control::2 1160 system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::5 220 system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::2 1144 @@ -497,17 +508,17 @@ system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::5 15840 system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::2 9152 system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::5 7392 system.ruby.network.routers1.throttle0.msg_bytes.Unblock_Control::5 9272 -system.ruby.network.routers1.throttle1.link_utilization 6.675118 +system.ruby.network.routers1.throttle1.link_utilization 6.206401 system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 1160 system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 1144 system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 83520 system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 9152 -system.ruby.network.routers2.throttle0.link_utilization 6.675118 +system.ruby.network.routers2.throttle0.link_utilization 6.206401 system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 1160 system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 1144 system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 83520 system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 9152 -system.ruby.network.routers2.throttle1.link_utilization 3.669471 +system.ruby.network.routers2.throttle1.link_utilization 3.411806 system.ruby.network.routers2.throttle1.msg_count.Request_Control::2 1160 system.ruby.network.routers2.throttle1.msg_count.Writeback_Data::5 220 system.ruby.network.routers2.throttle1.msg_count.Writeback_Control::2 1144 @@ -518,13 +529,13 @@ system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Data::5 15840 system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Control::2 9152 system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Control::5 7392 system.ruby.network.routers2.throttle1.msg_bytes.Unblock_Control::5 9280 -system.ruby.LD.latency_hist_seqr::bucket_size 32 -system.ruby.LD.latency_hist_seqr::max_bucket 319 +system.ruby.LD.latency_hist_seqr::bucket_size 64 +system.ruby.LD.latency_hist_seqr::max_bucket 639 system.ruby.LD.latency_hist_seqr::samples 1185 -system.ruby.LD.latency_hist_seqr::mean 21.677637 -system.ruby.LD.latency_hist_seqr::gmean 5.060853 -system.ruby.LD.latency_hist_seqr::stdev 30.245768 -system.ruby.LD.latency_hist_seqr | 853 71.98% 71.98% | 244 20.59% 92.57% | 84 7.09% 99.66% | 1 0.08% 99.75% | 0 0.00% 99.75% | 0 0.00% 99.75% | 0 0.00% 99.75% | 0 0.00% 99.75% | 1 0.08% 99.83% | 2 0.17% 100.00% +system.ruby.LD.latency_hist_seqr::mean 23.222785 +system.ruby.LD.latency_hist_seqr::gmean 5.170883 +system.ruby.LD.latency_hist_seqr::stdev 33.395677 +system.ruby.LD.latency_hist_seqr | 1100 92.83% 92.83% | 82 6.92% 99.75% | 0 0.00% 99.75% | 0 0.00% 99.75% | 0 0.00% 99.75% | 3 0.25% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.latency_hist_seqr::total 1185 system.ruby.LD.hit_latency_hist_seqr::bucket_size 2 system.ruby.LD.hit_latency_hist_seqr::max_bucket 19 @@ -534,21 +545,21 @@ system.ruby.LD.hit_latency_hist_seqr::gmean 1.390347 system.ruby.LD.hit_latency_hist_seqr::stdev 3.445311 system.ruby.LD.hit_latency_hist_seqr | 659 86.26% 86.26% | 0 0.00% 86.26% | 0 0.00% 86.26% | 0 0.00% 86.26% | 0 0.00% 86.26% | 105 13.74% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.hit_latency_hist_seqr::total 764 -system.ruby.LD.miss_latency_hist_seqr::bucket_size 32 -system.ruby.LD.miss_latency_hist_seqr::max_bucket 319 +system.ruby.LD.miss_latency_hist_seqr::bucket_size 64 +system.ruby.LD.miss_latency_hist_seqr::max_bucket 639 system.ruby.LD.miss_latency_hist_seqr::samples 421 -system.ruby.LD.miss_latency_hist_seqr::mean 56.707838 -system.ruby.LD.miss_latency_hist_seqr::gmean 52.779793 -system.ruby.LD.miss_latency_hist_seqr::stdev 25.484779 -system.ruby.LD.miss_latency_hist_seqr | 89 21.14% 21.14% | 244 57.96% 79.10% | 84 19.95% 99.05% | 1 0.24% 99.29% | 0 0.00% 99.29% | 0 0.00% 99.29% | 0 0.00% 99.29% | 0 0.00% 99.29% | 1 0.24% 99.52% | 2 0.48% 100.00% +system.ruby.LD.miss_latency_hist_seqr::mean 61.057007 +system.ruby.LD.miss_latency_hist_seqr::gmean 56.073786 +system.ruby.LD.miss_latency_hist_seqr::stdev 29.948950 +system.ruby.LD.miss_latency_hist_seqr | 336 79.81% 79.81% | 82 19.48% 99.29% | 0 0.00% 99.29% | 0 0.00% 99.29% | 0 0.00% 99.29% | 3 0.71% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.miss_latency_hist_seqr::total 421 system.ruby.ST.latency_hist_seqr::bucket_size 16 system.ruby.ST.latency_hist_seqr::max_bucket 159 system.ruby.ST.latency_hist_seqr::samples 865 -system.ruby.ST.latency_hist_seqr::mean 10.558382 -system.ruby.ST.latency_hist_seqr::gmean 2.225841 -system.ruby.ST.latency_hist_seqr::stdev 20.458667 -system.ruby.ST.latency_hist_seqr | 707 81.73% 81.73% | 45 5.20% 86.94% | 0 0.00% 86.94% | 76 8.79% 95.72% | 33 3.82% 99.54% | 4 0.46% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.latency_hist_seqr::mean 11.254335 +system.ruby.ST.latency_hist_seqr::gmean 2.251088 +system.ruby.ST.latency_hist_seqr::stdev 22.172254 +system.ruby.ST.latency_hist_seqr | 707 81.73% 81.73% | 44 5.09% 86.82% | 0 0.00% 86.82% | 73 8.44% 95.26% | 36 4.16% 99.42% | 4 0.46% 99.88% | 1 0.12% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ST.latency_hist_seqr::total 865 system.ruby.ST.hit_latency_hist_seqr::bucket_size 2 system.ruby.ST.hit_latency_hist_seqr::max_bucket 19 @@ -561,18 +572,18 @@ system.ruby.ST.hit_latency_hist_seqr::total 707 system.ruby.ST.miss_latency_hist_seqr::bucket_size 16 system.ruby.ST.miss_latency_hist_seqr::max_bucket 159 system.ruby.ST.miss_latency_hist_seqr::samples 158 -system.ruby.ST.miss_latency_hist_seqr::mean 51.240506 -system.ruby.ST.miss_latency_hist_seqr::gmean 48.407659 -system.ruby.ST.miss_latency_hist_seqr::stdev 15.670342 -system.ruby.ST.miss_latency_hist_seqr | 0 0.00% 0.00% | 45 28.48% 28.48% | 0 0.00% 28.48% | 76 48.10% 76.58% | 33 20.89% 97.47% | 4 2.53% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.miss_latency_hist_seqr::mean 55.050633 +system.ruby.ST.miss_latency_hist_seqr::gmean 51.490981 +system.ruby.ST.miss_latency_hist_seqr::stdev 17.990372 +system.ruby.ST.miss_latency_hist_seqr | 0 0.00% 0.00% | 44 27.85% 27.85% | 0 0.00% 27.85% | 73 46.20% 74.05% | 36 22.78% 96.84% | 4 2.53% 99.37% | 1 0.63% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ST.miss_latency_hist_seqr::total 158 system.ruby.IFETCH.latency_hist_seqr::bucket_size 64 system.ruby.IFETCH.latency_hist_seqr::max_bucket 639 system.ruby.IFETCH.latency_hist_seqr::samples 6413 -system.ruby.IFETCH.latency_hist_seqr::mean 6.780914 -system.ruby.IFETCH.latency_hist_seqr::gmean 1.487888 -system.ruby.IFETCH.latency_hist_seqr::stdev 19.876102 -system.ruby.IFETCH.latency_hist_seqr | 6306 98.33% 98.33% | 100 1.56% 99.89% | 0 0.00% 99.89% | 1 0.02% 99.91% | 4 0.06% 99.97% | 2 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.latency_hist_seqr::mean 7.423359 +system.ruby.IFETCH.latency_hist_seqr::gmean 1.501230 +system.ruby.IFETCH.latency_hist_seqr::stdev 22.823134 +system.ruby.IFETCH.latency_hist_seqr | 6295 98.16% 98.16% | 108 1.68% 99.84% | 1 0.02% 99.86% | 1 0.02% 99.88% | 5 0.08% 99.95% | 2 0.03% 99.98% | 0 0.00% 99.98% | 0 0.00% 99.98% | 0 0.00% 99.98% | 1 0.02% 100.00% system.ruby.IFETCH.latency_hist_seqr::total 6413 system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 2 system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 19 @@ -585,10 +596,10 @@ system.ruby.IFETCH.hit_latency_hist_seqr::total 5832 system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 64 system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 639 system.ruby.IFETCH.miss_latency_hist_seqr::samples 581 -system.ruby.IFETCH.miss_latency_hist_seqr::mean 63.690189 -system.ruby.IFETCH.miss_latency_hist_seqr::gmean 61.418649 -system.ruby.IFETCH.miss_latency_hist_seqr::stdev 28.087678 -system.ruby.IFETCH.miss_latency_hist_seqr | 474 81.58% 81.58% | 100 17.21% 98.80% | 0 0.00% 98.80% | 1 0.17% 98.97% | 4 0.69% 99.66% | 2 0.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.miss_latency_hist_seqr::mean 70.781411 +system.ruby.IFETCH.miss_latency_hist_seqr::gmean 67.778682 +system.ruby.IFETCH.miss_latency_hist_seqr::stdev 36.410761 +system.ruby.IFETCH.miss_latency_hist_seqr | 463 79.69% 79.69% | 108 18.59% 98.28% | 1 0.17% 98.45% | 1 0.17% 98.62% | 5 0.86% 99.48% | 2 0.34% 99.83% | 0 0.00% 99.83% | 0 0.00% 99.83% | 0 0.00% 99.83% | 1 0.17% 100.00% system.ruby.IFETCH.miss_latency_hist_seqr::total 581 system.ruby.L1Cache.hit_mach_latency_hist_seqr::bucket_size 1 system.ruby.L1Cache.hit_mach_latency_hist_seqr::max_bucket 9 @@ -607,10 +618,10 @@ system.ruby.L2Cache.hit_mach_latency_hist_seqr::total 203 system.ruby.Directory.miss_mach_latency_hist_seqr::bucket_size 64 system.ruby.Directory.miss_mach_latency_hist_seqr::max_bucket 639 system.ruby.Directory.miss_mach_latency_hist_seqr::samples 1160 -system.ruby.Directory.miss_mach_latency_hist_seqr::mean 59.460345 -system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 56.276317 -system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 26.160126 -system.ruby.Directory.miss_mach_latency_hist_seqr | 928 80.00% 80.00% | 222 19.14% 99.14% | 0 0.00% 99.14% | 1 0.09% 99.22% | 7 0.60% 99.83% | 2 0.17% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_mach_latency_hist_seqr::mean 65.109483 +system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 60.947221 +system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 32.683425 +system.ruby.Directory.miss_mach_latency_hist_seqr | 916 78.97% 78.97% | 231 19.91% 98.88% | 1 0.09% 98.97% | 1 0.09% 99.05% | 5 0.43% 99.48% | 5 0.43% 99.91% | 0 0.00% 99.91% | 0 0.00% 99.91% | 0 0.00% 99.91% | 1 0.09% 100.00% system.ruby.Directory.miss_mach_latency_hist_seqr::total 1160 system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::bucket_size 1 system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::max_bucket 9 @@ -652,13 +663,13 @@ system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::mean 11 system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::gmean 11.000000 system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 105 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::total 105 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size 32 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket 319 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples 421 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 56.707838 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 52.779793 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 25.484779 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 89 21.14% 21.14% | 244 57.96% 79.10% | 84 19.95% 99.05% | 1 0.24% 99.29% | 0 0.00% 99.29% | 0 0.00% 99.29% | 0 0.00% 99.29% | 0 0.00% 99.29% | 1 0.24% 99.52% | 2 0.48% 100.00% +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 61.057007 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 56.073786 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 29.948950 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 336 79.81% 79.81% | 82 19.48% 99.29% | 0 0.00% 99.29% | 0 0.00% 99.29% | 0 0.00% 99.29% | 3 0.71% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total 421 system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::bucket_size 1 system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::max_bucket 9 @@ -677,10 +688,10 @@ system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::total 33 system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size 16 system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket 159 system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::samples 158 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 51.240506 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 48.407659 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 15.670342 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 45 28.48% 28.48% | 0 0.00% 28.48% | 76 48.10% 76.58% | 33 20.89% 97.47% | 4 2.53% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 55.050633 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 51.490981 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 17.990372 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 44 27.85% 27.85% | 0 0.00% 27.85% | 73 46.20% 74.05% | 36 22.78% 96.84% | 4 2.53% 99.37% | 1 0.63% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total 158 system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::bucket_size 1 system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::max_bucket 9 @@ -699,10 +710,10 @@ system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::total 65 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::samples 581 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 63.690189 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 61.418649 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 28.087678 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 474 81.58% 81.58% | 100 17.21% 98.80% | 0 0.00% 98.80% | 1 0.17% 98.97% | 4 0.69% 99.66% | 2 0.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 70.781411 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 67.778682 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 36.410761 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 463 79.69% 79.69% | 108 18.59% 98.28% | 1 0.17% 98.45% | 1 0.17% 98.62% | 5 0.86% 99.48% | 2 0.34% 99.83% | 0 0.00% 99.83% | 0 0.00% 99.83% | 0 0.00% 99.83% | 1 0.17% 100.00% system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::total 581 system.ruby.Directory_Controller.GETX 185 0.00% 0.00% system.ruby.Directory_Controller.GETS 1021 0.00% 0.00% diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini index 2d08f440e..6b91b5d29 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini @@ -14,6 +14,7 @@ children=clk_domain cpu dvfs_handler mem_ctrls ruby sys_port_proxy voltage_domai boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 exit_on_work_items=false init_param=0 @@ -22,11 +23,15 @@ kernel_addr_check=true load_addr_mask=1099511627775 load_offset=0 mem_mode=timing -mem_ranges=0:268435455 +mem_ranges=0:268435455:0:0:0:0 memories=system.mem_ctrls mmap_using_noreserve=false multi_thread=false num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null readfile= symbolfile= thermal_components= @@ -55,6 +60,7 @@ branchPred=Null checker=Null clk_domain=system.cpu.clk_domain cpu_id=0 +default_p_state=UNDEFINED do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true @@ -70,6 +76,10 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null profile=0 progress_interval=0 simpoint_start_insts= @@ -122,7 +132,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/hello/bin/alpha/linux/hello +executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin kvmInSE=false @@ -145,27 +155,27 @@ transition_latency=100000 [system.mem_ctrls] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -177,6 +187,7 @@ burst_length=8 channels=1 clk_domain=system.clk_domain conf_table_reported=true +default_p_state=UNDEFINED device_bus_width=8 device_rowbuffer_size=1024 device_size=536870912 @@ -184,12 +195,17 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 page_policy=open_adaptive -range=0:268435455 +power_model=Null +range=0:268435455:5:19:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10 @@ -211,9 +227,9 @@ tRTW=3 tWR=15 tWTR=8 tXAW=30 -tXP=0 +tXP=6 tXPDLL=0 -tXS=0 +tXS=270 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 @@ -227,12 +243,17 @@ access_backing_store=false all_instructions=false block_size_bytes=64 clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED eventq_index=0 hot_lines=false memory_size_bits=48 num_of_sequencers=1 number_of_virtual_networks=5 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 phys_mem=Null +power_model=Null randomization=false [system.ruby.clk_domain] @@ -249,6 +270,7 @@ children=directory dmaRequestToDir dmaResponseFromDir forwardFromDir requestToDi buffer_size=0 clk_domain=system.ruby.clk_domain cluster_id=0 +default_p_state=UNDEFINED directory=system.ruby.dir_cntrl0.directory directory_latency=12 dmaRequestToDir=system.ruby.dir_cntrl0.dmaRequestToDir @@ -256,6 +278,10 @@ dmaResponseFromDir=system.ruby.dir_cntrl0.dmaResponseFromDir eventq_index=0 forwardFromDir=system.ruby.dir_cntrl0.forwardFromDir number_of_TBEs=256 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null recycle_latency=10 requestToDir=system.ruby.dir_cntrl0.requestToDir responseFromDir=system.ruby.dir_cntrl0.responseFromDir @@ -329,11 +355,16 @@ cacheMemory=system.ruby.l1_cntrl0.cacheMemory cache_response_latency=12 clk_domain=system.cpu.clk_domain cluster_id=0 +default_p_state=UNDEFINED eventq_index=0 forwardToCache=system.ruby.l1_cntrl0.forwardToCache issue_latency=2 mandatoryQueue=system.ruby.l1_cntrl0.mandatoryQueue number_of_TBEs=256 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null recycle_latency=10 requestFromCache=system.ruby.l1_cntrl0.requestFromCache responseFromCache=system.ruby.l1_cntrl0.responseFromCache @@ -415,17 +446,22 @@ coreid=99 dcache=system.ruby.l1_cntrl0.cacheMemory dcache_hit_latency=1 deadlock_threshold=500000 +default_p_state=UNDEFINED eventq_index=0 +garnet_standalone=false icache=system.ruby.l1_cntrl0.cacheMemory icache_hit_latency=1 is_cpu_sequencer=true max_outstanding_requests=16 no_retry_on_stall=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null ruby_system=system.ruby support_data_reqs=true support_inst_reqs=true system=system -using_network_tester=false using_ruby_tester=false version=0 slave=system.cpu.icache_port system.cpu.dcache_port @@ -438,18 +474,23 @@ eventq_index=0 [system.ruby.network] type=SimpleNetwork -children=ext_links0 ext_links1 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_links0 int_links1 routers0 routers1 routers2 +children=ext_links0 ext_links1 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_link_buffers20 int_link_buffers21 int_link_buffers22 int_link_buffers23 int_link_buffers24 int_link_buffers25 int_link_buffers26 int_link_buffers27 int_link_buffers28 int_link_buffers29 int_link_buffers30 int_link_buffers31 int_link_buffers32 int_link_buffers33 int_link_buffers34 int_link_buffers35 int_link_buffers36 int_link_buffers37 int_link_buffers38 int_link_buffers39 int_links0 int_links1 int_links2 int_links3 routers0 routers1 routers2 adaptive_routing=false buffer_size=0 clk_domain=system.ruby.clk_domain control_msg_size=8 +default_p_state=UNDEFINED endpoint_bandwidth=1000 eventq_index=0 ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1 -int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19 -int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 +int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19 system.ruby.network.int_link_buffers20 system.ruby.network.int_link_buffers21 system.ruby.network.int_link_buffers22 system.ruby.network.int_link_buffers23 system.ruby.network.int_link_buffers24 system.ruby.network.int_link_buffers25 system.ruby.network.int_link_buffers26 system.ruby.network.int_link_buffers27 system.ruby.network.int_link_buffers28 system.ruby.network.int_link_buffers29 system.ruby.network.int_link_buffers30 system.ruby.network.int_link_buffers31 system.ruby.network.int_link_buffers32 system.ruby.network.int_link_buffers33 system.ruby.network.int_link_buffers34 system.ruby.network.int_link_buffers35 system.ruby.network.int_link_buffers36 system.ruby.network.int_link_buffers37 system.ruby.network.int_link_buffers38 system.ruby.network.int_link_buffers39 +int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2 system.ruby.network.int_links3 netifs= number_of_virtual_networks=5 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null routers=system.ruby.network.routers0 system.ruby.network.routers1 system.ruby.network.routers2 ruby_system=system.ruby topology=Crossbar @@ -616,32 +657,206 @@ eventq_index=0 ordered=true randomization=false +[system.ruby.network.int_link_buffers20] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers21] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers22] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers23] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers24] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers25] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers26] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers27] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers28] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers29] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers30] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers31] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers32] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers33] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers34] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers35] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers36] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers37] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers38] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers39] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + [system.ruby.network.int_links0] type=SimpleIntLink bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers2 eventq_index=0 latency=1 link_id=2 -node_a=system.ruby.network.routers0 -node_b=system.ruby.network.routers2 +src_node=system.ruby.network.routers0 +src_outport= weight=1 [system.ruby.network.int_links1] type=SimpleIntLink bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers2 eventq_index=0 latency=1 link_id=3 -node_a=system.ruby.network.routers1 -node_b=system.ruby.network.routers2 +src_node=system.ruby.network.routers1 +src_outport= +weight=1 + +[system.ruby.network.int_links2] +type=SimpleIntLink +bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers0 +eventq_index=0 +latency=1 +link_id=4 +src_node=system.ruby.network.routers2 +src_outport= +weight=1 + +[system.ruby.network.int_links3] +type=SimpleIntLink +bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers1 +eventq_index=0 +latency=1 +link_id=5 +src_node=system.ruby.network.routers2 +src_outport= weight=1 [system.ruby.network.routers0] type=Switch children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED eventq_index=0 +latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 port_buffers=system.ruby.network.routers0.port_buffers00 system.ruby.network.routers0.port_buffers01 system.ruby.network.routers0.port_buffers02 system.ruby.network.routers0.port_buffers03 system.ruby.network.routers0.port_buffers04 system.ruby.network.routers0.port_buffers05 system.ruby.network.routers0.port_buffers06 system.ruby.network.routers0.port_buffers07 system.ruby.network.routers0.port_buffers08 system.ruby.network.routers0.port_buffers09 system.ruby.network.routers0.port_buffers10 system.ruby.network.routers0.port_buffers11 system.ruby.network.routers0.port_buffers12 system.ruby.network.routers0.port_buffers13 system.ruby.network.routers0.port_buffers14 +power_model=Null router_id=0 virt_nets=5 @@ -754,8 +969,14 @@ randomization=false type=Switch children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED eventq_index=0 +latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 port_buffers=system.ruby.network.routers1.port_buffers00 system.ruby.network.routers1.port_buffers01 system.ruby.network.routers1.port_buffers02 system.ruby.network.routers1.port_buffers03 system.ruby.network.routers1.port_buffers04 system.ruby.network.routers1.port_buffers05 system.ruby.network.routers1.port_buffers06 system.ruby.network.routers1.port_buffers07 system.ruby.network.routers1.port_buffers08 system.ruby.network.routers1.port_buffers09 system.ruby.network.routers1.port_buffers10 system.ruby.network.routers1.port_buffers11 system.ruby.network.routers1.port_buffers12 system.ruby.network.routers1.port_buffers13 system.ruby.network.routers1.port_buffers14 +power_model=Null router_id=1 virt_nets=5 @@ -868,8 +1089,14 @@ randomization=false type=Switch children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17 port_buffers18 port_buffers19 clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED eventq_index=0 +latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 port_buffers=system.ruby.network.routers2.port_buffers00 system.ruby.network.routers2.port_buffers01 system.ruby.network.routers2.port_buffers02 system.ruby.network.routers2.port_buffers03 system.ruby.network.routers2.port_buffers04 system.ruby.network.routers2.port_buffers05 system.ruby.network.routers2.port_buffers06 system.ruby.network.routers2.port_buffers07 system.ruby.network.routers2.port_buffers08 system.ruby.network.routers2.port_buffers09 system.ruby.network.routers2.port_buffers10 system.ruby.network.routers2.port_buffers11 system.ruby.network.routers2.port_buffers12 system.ruby.network.routers2.port_buffers13 system.ruby.network.routers2.port_buffers14 system.ruby.network.routers2.port_buffers15 system.ruby.network.routers2.port_buffers16 system.ruby.network.routers2.port_buffers17 system.ruby.network.routers2.port_buffers18 system.ruby.network.routers2.port_buffers19 +power_model=Null router_id=2 virt_nets=5 @@ -1016,9 +1243,14 @@ randomization=false [system.sys_port_proxy] type=RubyPortProxy clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 is_cpu_sequencer=true no_retry_on_stall=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null ruby_system=system.ruby support_data_reqs=true support_inst_reqs=true diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simerr b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simerr index ccfdd3697..f6f6f15a5 100755 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simerr +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simerr @@ -4,8 +4,7 @@ warn: rounding error > tolerance 1.250000 rounded to 1 warn: rounding error > tolerance 1.250000 rounded to 1 -warn: rounding error > tolerance - 1.250000 rounded to 1 warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes) warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files! diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simout b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simout index 9c35f4885..89adb8b85 100755 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simout +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simout @@ -3,13 +3,13 @@ Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 14 2016 21:54:46 -gem5 started Mar 14 2016 21:55:58 -gem5 executing on phenom, pid 28070 -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby +gem5 compiled Oct 11 2016 00:00:58 +gem5 started Oct 13 2016 20:19:45 +gem5 executing on e108600-lin, pid 28066 +command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/alpha/linux/simple-timing-ruby Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 107065 because target called exit() +Exiting @ tick 112490 because target called exit() diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt index a33abfe97..06dea8ad2 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000107 # Number of seconds simulated -sim_ticks 107065 # Number of ticks simulated -final_tick 107065 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000112 # Number of seconds simulated +sim_ticks 112490 # Number of ticks simulated +final_tick 112490 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 58028 # Simulator instruction rate (inst/s) -host_op_rate 58023 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 970128 # Simulator tick rate (ticks/s) -host_mem_usage 456600 # Number of bytes of host memory used -host_seconds 0.11 # Real time elapsed on the host +host_inst_rate 94486 # Simulator instruction rate (inst/s) +host_op_rate 94411 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1658372 # Simulator tick rate (ticks/s) +host_mem_usage 414356 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host sim_insts 6403 # Number of instructions simulated sim_ops 6403 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks -system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 107065 # Cumulative time (in ticks) in various power states +system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 112490 # Cumulative time (in ticks) in various power states system.mem_ctrls.bytes_read::ruby.dir_cntrl0 110784 # Number of bytes read from this memory system.mem_ctrls.bytes_read::total 110784 # Number of bytes read from this memory system.mem_ctrls.bytes_written::ruby.dir_cntrl0 110528 # Number of bytes written to this memory @@ -22,59 +22,59 @@ system.mem_ctrls.num_reads::ruby.dir_cntrl0 1731 # system.mem_ctrls.num_reads::total 1731 # Number of read requests responded to by this memory system.mem_ctrls.num_writes::ruby.dir_cntrl0 1727 # Number of write requests responded to by this memory system.mem_ctrls.num_writes::total 1727 # Number of write requests responded to by this memory -system.mem_ctrls.bw_read::ruby.dir_cntrl0 1034735908 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_read::total 1034735908 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::ruby.dir_cntrl0 1032344837 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::total 1032344837 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_total::ruby.dir_cntrl0 2067080745 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.bw_total::total 2067080745 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_read::ruby.dir_cntrl0 984834207 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 984834207 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::ruby.dir_cntrl0 982558450 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::total 982558450 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::ruby.dir_cntrl0 1967392657 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 1967392657 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrls.readReqs 1731 # Number of read requests accepted system.mem_ctrls.writeReqs 1727 # Number of write requests accepted system.mem_ctrls.readBursts 1731 # Number of DRAM read bursts, including those serviced by the write queue system.mem_ctrls.writeBursts 1727 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrls.bytesReadDRAM 56512 # Total number of bytes read from DRAM -system.mem_ctrls.bytesReadWrQ 54272 # Total number of bytes read from write queue -system.mem_ctrls.bytesWritten 57856 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadDRAM 56704 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 54080 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 57088 # Total number of bytes written to DRAM system.mem_ctrls.bytesReadSys 110784 # Total read bytes from the system interface side system.mem_ctrls.bytesWrittenSys 110528 # Total written bytes from the system interface side -system.mem_ctrls.servicedByWrQ 848 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrls.mergedWrBursts 792 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.servicedByWrQ 845 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 803 # Number of DRAM write bursts merged with an existing one system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.mem_ctrls.perBankRdBursts::0 85 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::1 47 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::2 74 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::3 68 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::4 112 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::0 83 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 50 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 70 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 63 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 108 # Per bank write bursts system.mem_ctrls.perBankRdBursts::5 23 # Per bank write bursts system.mem_ctrls.perBankRdBursts::6 1 # Per bank write bursts system.mem_ctrls.perBankRdBursts::7 3 # Per bank write bursts system.mem_ctrls.perBankRdBursts::8 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::9 1 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::10 49 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::11 33 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::12 17 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::13 263 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::14 79 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::15 28 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::0 83 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::1 47 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::2 80 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::3 68 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::4 133 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::5 25 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 55 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 36 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::12 18 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 270 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 81 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::15 24 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 82 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 51 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 73 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 60 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 126 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 27 # Per bank write bursts system.mem_ctrls.perBankWrBursts::6 1 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::7 4 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 3 # Per bank write bursts system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::9 1 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::10 46 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::11 28 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::12 11 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 50 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::11 33 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::12 12 # Per bank write bursts system.mem_ctrls.perBankWrBursts::13 268 # Per bank write bursts system.mem_ctrls.perBankWrBursts::14 81 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::15 28 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::15 24 # Per bank write bursts system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrls.totGap 106993 # Total gap between requests +system.mem_ctrls.totGap 112412 # Total gap between requests system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) @@ -89,7 +89,7 @@ system.mem_ctrls.writePktSize::3 0 # Wr system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::6 1727 # Write request sizes (log2) -system.mem_ctrls.rdQLenPdf::0 883 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::0 886 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see @@ -136,15 +136,15 @@ system.mem_ctrls.wrQLenPdf::11 1 # Wh system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::15 9 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::16 10 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::17 50 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 6 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 6 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 51 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::18 57 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::19 60 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::20 61 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::21 57 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::22 56 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::23 57 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 57 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 56 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 60 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 57 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 56 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::24 56 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::25 56 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::26 56 # What write queue length does an incoming req see @@ -152,9 +152,9 @@ system.mem_ctrls.wrQLenPdf::27 56 # Wh system.mem_ctrls.wrQLenPdf::28 56 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::29 56 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::30 56 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::31 55 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 56 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::32 55 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::33 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see @@ -185,90 +185,100 @@ system.mem_ctrls.wrQLenPdf::60 0 # Wh system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrls.bytesPerActivate::samples 275 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::mean 406.341818 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::gmean 258.682678 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::stdev 357.059585 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::0-127 55 20.00% 20.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::128-255 74 26.91% 46.91% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::256-383 37 13.45% 60.36% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::384-511 16 5.82% 66.18% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::512-639 18 6.55% 72.73% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::640-767 12 4.36% 77.09% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::768-895 8 2.91% 80.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::896-1023 6 2.18% 82.18% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::1024-1151 49 17.82% 100.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::total 275 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::samples 264 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 424 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 260.079273 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 372.426347 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 66 25.00% 25.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 58 21.97% 46.97% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 27 10.23% 57.20% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 16 6.06% 63.26% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 17 6.44% 69.70% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 8 3.03% 72.73% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 12 4.55% 77.27% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 10 3.79% 81.06% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 50 18.94% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 264 # Bytes accessed per row activation system.mem_ctrls.rdPerTurnAround::samples 55 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::mean 15.781818 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::gmean 15.596648 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::stdev 2.973282 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::12-13 4 7.27% 7.27% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::14-15 25 45.45% 52.73% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::16-17 21 38.18% 90.91% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::mean 15.818182 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::gmean 15.638991 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::stdev 2.938196 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::12-13 3 5.45% 5.45% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::14-15 24 43.64% 49.09% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::16-17 23 41.82% 90.91% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::18-19 4 7.27% 98.18% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::34-35 1 1.82% 100.00% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::total 55 # Reads before turning the bus around for writes system.mem_ctrls.wrPerTurnAround::samples 55 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::mean 16.436364 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::gmean 16.408895 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::stdev 0.995613 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::16 45 81.82% 81.82% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::17 2 3.64% 85.45% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::18 2 3.64% 89.09% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::19 6 10.91% 100.00% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::mean 16.218182 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::gmean 16.206001 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::stdev 0.658025 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::16 49 89.09% 89.09% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::17 1 1.82% 90.91% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::18 4 7.27% 98.18% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::19 1 1.82% 100.00% # Writes before turning the bus around for reads system.mem_ctrls.wrPerTurnAround::total 55 # Writes before turning the bus around for reads -system.mem_ctrls.totQLat 10887 # Total ticks spent queuing -system.mem_ctrls.totMemAccLat 27664 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrls.totBusLat 4415 # Total ticks spent in databus transfers -system.mem_ctrls.avgQLat 12.33 # Average queueing delay per DRAM burst +system.mem_ctrls.totQLat 16225 # Total ticks spent queuing +system.mem_ctrls.totMemAccLat 33059 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.totBusLat 4430 # Total ticks spent in databus transfers +system.mem_ctrls.avgQLat 18.31 # Average queueing delay per DRAM burst system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst -system.mem_ctrls.avgMemAccLat 31.33 # Average memory access latency per DRAM burst -system.mem_ctrls.avgRdBW 527.83 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrls.avgWrBW 540.38 # Average achieved write bandwidth in MiByte/s -system.mem_ctrls.avgRdBWSys 1034.74 # Average system read bandwidth in MiByte/s -system.mem_ctrls.avgWrBWSys 1032.34 # Average system write bandwidth in MiByte/s +system.mem_ctrls.avgMemAccLat 37.31 # Average memory access latency per DRAM burst +system.mem_ctrls.avgRdBW 504.08 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 507.49 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 984.83 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 982.56 # Average system write bandwidth in MiByte/s system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrls.busUtil 8.35 # Data bus utilization in percentage -system.mem_ctrls.busUtilRead 4.12 # Data bus utilization in percentage for reads -system.mem_ctrls.busUtilWrite 4.22 # Data bus utilization in percentage for writes +system.mem_ctrls.busUtil 7.90 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 3.94 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 3.96 # Data bus utilization in percentage for writes system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing -system.mem_ctrls.avgWrQLen 26.13 # Average write queue length when enqueuing -system.mem_ctrls.readRowHits 670 # Number of row buffer hits during reads -system.mem_ctrls.writeRowHits 835 # Number of row buffer hits during writes -system.mem_ctrls.readRowHitRate 75.88 # Row buffer hit rate for reads -system.mem_ctrls.writeRowHitRate 89.30 # Row buffer hit rate for writes -system.mem_ctrls.avgGap 30.94 # Average gap between requests -system.mem_ctrls.pageHitRate 82.78 # Row buffer hit rate, read and write combined -system.mem_ctrls_0.actEnergy 876960 # Energy for activate commands per rank (pJ) -system.mem_ctrls_0.preEnergy 487200 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_0.readEnergy 4992000 # Energy for read commands per rank (pJ) -system.mem_ctrls_0.writeEnergy 4489344 # Energy for write commands per rank (pJ) -system.mem_ctrls_0.refreshEnergy 6611280 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_0.actBackEnergy 63943740 # Energy for active background per rank (pJ) -system.mem_ctrls_0.preBackEnergy 4795800 # Energy for precharge background per rank (pJ) -system.mem_ctrls_0.totalEnergy 86196324 # Total energy per rank (pJ) -system.mem_ctrls_0.averagePower 849.408975 # Core power per rank (mW) -system.mem_ctrls_0.memoryStateTime::IDLE 8418 # Time in different power states -system.mem_ctrls_0.memoryStateTime::REF 3380 # Time in different power states -system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT 90483 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrls_1.actEnergy 1156680 # Energy for activate commands per rank (pJ) -system.mem_ctrls_1.preEnergy 642600 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_1.readEnergy 5366400 # Energy for read commands per rank (pJ) -system.mem_ctrls_1.writeEnergy 4385664 # Energy for write commands per rank (pJ) -system.mem_ctrls_1.refreshEnergy 6611280 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_1.actBackEnergy 65375352 # Energy for active background per rank (pJ) -system.mem_ctrls_1.preBackEnergy 3540000 # Energy for precharge background per rank (pJ) -system.mem_ctrls_1.totalEnergy 87077976 # Total energy per rank (pJ) -system.mem_ctrls_1.averagePower 858.097085 # Core power per rank (mW) -system.mem_ctrls_1.memoryStateTime::IDLE 5471 # Time in different power states -system.mem_ctrls_1.memoryStateTime::REF 3380 # Time in different power states -system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT 92641 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 107065 # Cumulative time (in ticks) in various power states +system.mem_ctrls.avgWrQLen 26.10 # Average write queue length when enqueuing +system.mem_ctrls.readRowHits 674 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 833 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 76.07 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate 90.15 # Row buffer hit rate for writes +system.mem_ctrls.avgGap 32.51 # Average gap between requests +system.mem_ctrls.pageHitRate 83.26 # Row buffer hit rate, read and write combined +system.mem_ctrls_0.actEnergy 735420 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 386400 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 4581024 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 3532896 # Energy for write commands per rank (pJ) +system.mem_ctrls_0.refreshEnergy 8604960.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 13923048 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 195072 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.actPowerDownEnergy 30921360 # Energy for active power-down per rank (pJ) +system.mem_ctrls_0.prePowerDownEnergy 5237376 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls_0.totalEnergy 68117556 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 605.543213 # Core power per rank (mW) +system.mem_ctrls_0.totalIdleTime 81406 # Total Idle time Per DRAM Rank +system.mem_ctrls_0.memoryStateTime::IDLE 88 # Time in different power states +system.mem_ctrls_0.memoryStateTime::REF 3640 # Time in different power states +system.mem_ctrls_0.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls_0.memoryStateTime::PRE_PDN 13639 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 27313 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT_PDN 67810 # Time in different power states +system.mem_ctrls_1.actEnergy 1199520 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 633696 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 5540640 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 3917088 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.refreshEnergy 8604960.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 12524952 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 314880 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.actPowerDownEnergy 33139344 # Energy for active power-down per rank (pJ) +system.mem_ctrls_1.prePowerDownEnergy 4427136 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls_1.totalEnergy 70302216 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 624.964139 # Core power per rank (mW) +system.mem_ctrls_1.totalIdleTime 83983 # Total Idle time Per DRAM Rank +system.mem_ctrls_1.memoryStateTime::IDLE 260 # Time in different power states +system.mem_ctrls_1.memoryStateTime::REF 3640 # Time in different power states +system.mem_ctrls_1.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls_1.memoryStateTime::PRE_PDN 11529 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 24387 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT_PDN 72674 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 112490 # Cumulative time (in ticks) in various power states system.cpu.clk_domain.clock 1 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -303,8 +313,8 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 107065 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 107065 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 112490 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 112490 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 6403 # Number of instructions committed @@ -323,7 +333,7 @@ system.cpu.num_mem_refs 2060 # nu system.cpu.num_load_insts 1192 # Number of load instructions system.cpu.num_store_insts 868 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 107065 # Number of busy cycles +system.cpu.num_busy_cycles 112490 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 1056 # Number of branches fetched @@ -363,7 +373,7 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 6413 # Class of executed instruction system.ruby.clk_domain.clock 1 # Clock period in ticks -system.ruby.pwrStateResidencyTicks::UNDEFINED 107065 # Cumulative time (in ticks) in various power states +system.ruby.pwrStateResidencyTicks::UNDEFINED 112490 # Cumulative time (in ticks) in various power states system.ruby.delayHist::bucket_size 1 # delay histogram for all message system.ruby.delayHist::max_bucket 9 # delay histogram for all message system.ruby.delayHist::samples 3458 # delay histogram for all message @@ -379,10 +389,10 @@ system.ruby.outstanding_req_hist_seqr::total 8464 system.ruby.latency_hist_seqr::bucket_size 64 system.ruby.latency_hist_seqr::max_bucket 639 system.ruby.latency_hist_seqr::samples 8463 -system.ruby.latency_hist_seqr::mean 11.650951 -system.ruby.latency_hist_seqr::gmean 2.202191 -system.ruby.latency_hist_seqr::stdev 25.742711 -system.ruby.latency_hist_seqr | 8220 97.13% 97.13% | 190 2.25% 99.37% | 41 0.48% 99.86% | 1 0.01% 99.87% | 6 0.07% 99.94% | 4 0.05% 99.99% | 1 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.latency_hist_seqr::mean 12.291977 +system.ruby.latency_hist_seqr::gmean 2.221869 +system.ruby.latency_hist_seqr::stdev 27.407806 +system.ruby.latency_hist_seqr | 7608 89.90% 89.90% | 798 9.43% 99.33% | 40 0.47% 99.80% | 5 0.06% 99.86% | 6 0.07% 99.93% | 6 0.07% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.latency_hist_seqr::total 8463 system.ruby.hit_latency_hist_seqr::bucket_size 1 system.ruby.hit_latency_hist_seqr::max_bucket 9 @@ -394,21 +404,21 @@ system.ruby.hit_latency_hist_seqr::total 6732 system.ruby.miss_latency_hist_seqr::bucket_size 64 system.ruby.miss_latency_hist_seqr::max_bucket 639 system.ruby.miss_latency_hist_seqr::samples 1731 -system.ruby.miss_latency_hist_seqr::mean 53.073368 -system.ruby.miss_latency_hist_seqr::gmean 47.451096 -system.ruby.miss_latency_hist_seqr::stdev 32.911544 -system.ruby.miss_latency_hist_seqr | 1488 85.96% 85.96% | 190 10.98% 96.94% | 41 2.37% 99.31% | 1 0.06% 99.36% | 6 0.35% 99.71% | 4 0.23% 99.94% | 1 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.miss_latency_hist_seqr::mean 56.207395 +system.ruby.miss_latency_hist_seqr::gmean 49.560362 +system.ruby.miss_latency_hist_seqr::stdev 35.333412 +system.ruby.miss_latency_hist_seqr | 876 50.61% 50.61% | 798 46.10% 96.71% | 40 2.31% 99.02% | 5 0.29% 99.31% | 6 0.35% 99.65% | 6 0.35% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.miss_latency_hist_seqr::total 1731 system.ruby.Directory.incomplete_times_seqr 1730 -system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 107065 # Cumulative time (in ticks) in various power states +system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 112490 # Cumulative time (in ticks) in various power states system.ruby.l1_cntrl0.cacheMemory.demand_hits 6732 # Number of cache demand hits system.ruby.l1_cntrl0.cacheMemory.demand_misses 1731 # Number of cache demand misses system.ruby.l1_cntrl0.cacheMemory.demand_accesses 8463 # Number of cache demand accesses -system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 107065 # Cumulative time (in ticks) in various power states -system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 107065 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 112490 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 112490 # Cumulative time (in ticks) in various power states system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 107065 # Cumulative time (in ticks) in various power states -system.ruby.network.routers0.percent_links_utilized 8.074534 +system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 112490 # Cumulative time (in ticks) in various power states +system.ruby.network.routers0.percent_links_utilized 7.685128 system.ruby.network.routers0.msg_count.Control::2 1731 system.ruby.network.routers0.msg_count.Data::2 1727 system.ruby.network.routers0.msg_count.Response_Data::4 1731 @@ -417,8 +427,8 @@ system.ruby.network.routers0.msg_bytes.Control::2 13848 system.ruby.network.routers0.msg_bytes.Data::2 124344 system.ruby.network.routers0.msg_bytes.Response_Data::4 124632 system.ruby.network.routers0.msg_bytes.Writeback_Control::3 13816 -system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 107065 # Cumulative time (in ticks) in various power states -system.ruby.network.routers1.percent_links_utilized 8.074534 +system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 112490 # Cumulative time (in ticks) in various power states +system.ruby.network.routers1.percent_links_utilized 7.685128 system.ruby.network.routers1.msg_count.Control::2 1731 system.ruby.network.routers1.msg_count.Data::2 1727 system.ruby.network.routers1.msg_count.Response_Data::4 1731 @@ -427,8 +437,8 @@ system.ruby.network.routers1.msg_bytes.Control::2 13848 system.ruby.network.routers1.msg_bytes.Data::2 124344 system.ruby.network.routers1.msg_bytes.Response_Data::4 124632 system.ruby.network.routers1.msg_bytes.Writeback_Control::3 13816 -system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 107065 # Cumulative time (in ticks) in various power states -system.ruby.network.routers2.percent_links_utilized 8.074534 +system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 112490 # Cumulative time (in ticks) in various power states +system.ruby.network.routers2.percent_links_utilized 7.685128 system.ruby.network.routers2.msg_count.Control::2 1731 system.ruby.network.routers2.msg_count.Data::2 1727 system.ruby.network.routers2.msg_count.Response_Data::4 1731 @@ -437,7 +447,7 @@ system.ruby.network.routers2.msg_bytes.Control::2 13848 system.ruby.network.routers2.msg_bytes.Data::2 124344 system.ruby.network.routers2.msg_bytes.Response_Data::4 124632 system.ruby.network.routers2.msg_bytes.Writeback_Control::3 13816 -system.ruby.network.pwrStateResidencyTicks::UNDEFINED 107065 # Cumulative time (in ticks) in various power states +system.ruby.network.pwrStateResidencyTicks::UNDEFINED 112490 # Cumulative time (in ticks) in various power states system.ruby.network.msg_count.Control 5193 system.ruby.network.msg_count.Data 5181 system.ruby.network.msg_count.Response_Data 5193 @@ -446,33 +456,33 @@ system.ruby.network.msg_byte.Control 41544 system.ruby.network.msg_byte.Data 373032 system.ruby.network.msg_byte.Response_Data 373896 system.ruby.network.msg_byte.Writeback_Control 41448 -system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 107065 # Cumulative time (in ticks) in various power states -system.ruby.network.routers0.throttle0.link_utilization 8.082006 +system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 112490 # Cumulative time (in ticks) in various power states +system.ruby.network.routers0.throttle0.link_utilization 7.692239 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1731 system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 1727 system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 124632 system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 13816 -system.ruby.network.routers0.throttle1.link_utilization 8.067062 +system.ruby.network.routers0.throttle1.link_utilization 7.678016 system.ruby.network.routers0.throttle1.msg_count.Control::2 1731 system.ruby.network.routers0.throttle1.msg_count.Data::2 1727 system.ruby.network.routers0.throttle1.msg_bytes.Control::2 13848 system.ruby.network.routers0.throttle1.msg_bytes.Data::2 124344 -system.ruby.network.routers1.throttle0.link_utilization 8.067062 +system.ruby.network.routers1.throttle0.link_utilization 7.678016 system.ruby.network.routers1.throttle0.msg_count.Control::2 1731 system.ruby.network.routers1.throttle0.msg_count.Data::2 1727 system.ruby.network.routers1.throttle0.msg_bytes.Control::2 13848 system.ruby.network.routers1.throttle0.msg_bytes.Data::2 124344 -system.ruby.network.routers1.throttle1.link_utilization 8.082006 +system.ruby.network.routers1.throttle1.link_utilization 7.692239 system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 1731 system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 1727 system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 124632 system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 13816 -system.ruby.network.routers2.throttle0.link_utilization 8.082006 +system.ruby.network.routers2.throttle0.link_utilization 7.692239 system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 1731 system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 1727 system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 124632 system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 13816 -system.ruby.network.routers2.throttle1.link_utilization 8.067062 +system.ruby.network.routers2.throttle1.link_utilization 7.678016 system.ruby.network.routers2.throttle1.msg_count.Control::2 1731 system.ruby.network.routers2.throttle1.msg_count.Data::2 1727 system.ruby.network.routers2.throttle1.msg_bytes.Control::2 13848 @@ -490,10 +500,10 @@ system.ruby.delayVCHist.vnet_2::total 1727 # de system.ruby.LD.latency_hist_seqr::bucket_size 64 system.ruby.LD.latency_hist_seqr::max_bucket 639 system.ruby.LD.latency_hist_seqr::samples 1185 -system.ruby.LD.latency_hist_seqr::mean 31.532489 -system.ruby.LD.latency_hist_seqr::gmean 10.421226 -system.ruby.LD.latency_hist_seqr::stdev 34.906160 -system.ruby.LD.latency_hist_seqr | 1091 92.07% 92.07% | 75 6.33% 98.40% | 15 1.27% 99.66% | 0 0.00% 99.66% | 2 0.17% 99.83% | 1 0.08% 99.92% | 1 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.latency_hist_seqr::mean 33.356118 +system.ruby.LD.latency_hist_seqr::gmean 10.708915 +system.ruby.LD.latency_hist_seqr::stdev 36.387225 +system.ruby.LD.latency_hist_seqr | 862 72.74% 72.74% | 301 25.40% 98.14% | 16 1.35% 99.49% | 3 0.25% 99.75% | 1 0.08% 99.83% | 2 0.17% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.latency_hist_seqr::total 1185 system.ruby.LD.hit_latency_hist_seqr::bucket_size 1 system.ruby.LD.hit_latency_hist_seqr::max_bucket 9 @@ -505,18 +515,18 @@ system.ruby.LD.hit_latency_hist_seqr::total 457 system.ruby.LD.miss_latency_hist_seqr::bucket_size 64 system.ruby.LD.miss_latency_hist_seqr::max_bucket 639 system.ruby.LD.miss_latency_hist_seqr::samples 728 -system.ruby.LD.miss_latency_hist_seqr::mean 50.699176 -system.ruby.LD.miss_latency_hist_seqr::gmean 45.385232 -system.ruby.LD.miss_latency_hist_seqr::stdev 32.101179 -system.ruby.LD.miss_latency_hist_seqr | 634 87.09% 87.09% | 75 10.30% 97.39% | 15 2.06% 99.45% | 0 0.00% 99.45% | 2 0.27% 99.73% | 1 0.14% 99.86% | 1 0.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.miss_latency_hist_seqr::mean 53.667582 +system.ruby.LD.miss_latency_hist_seqr::gmean 47.442261 +system.ruby.LD.miss_latency_hist_seqr::stdev 32.940895 +system.ruby.LD.miss_latency_hist_seqr | 405 55.63% 55.63% | 301 41.35% 96.98% | 16 2.20% 99.18% | 3 0.41% 99.59% | 1 0.14% 99.73% | 2 0.27% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.miss_latency_hist_seqr::total 728 system.ruby.ST.latency_hist_seqr::bucket_size 32 system.ruby.ST.latency_hist_seqr::max_bucket 319 system.ruby.ST.latency_hist_seqr::samples 865 -system.ruby.ST.latency_hist_seqr::mean 16.426590 -system.ruby.ST.latency_hist_seqr::gmean 3.318487 -system.ruby.ST.latency_hist_seqr::stdev 28.264983 -system.ruby.ST.latency_hist_seqr | 592 68.44% 68.44% | 242 27.98% 96.42% | 21 2.43% 98.84% | 1 0.12% 98.96% | 4 0.46% 99.42% | 4 0.46% 99.88% | 0 0.00% 99.88% | 0 0.00% 99.88% | 0 0.00% 99.88% | 1 0.12% 100.00% +system.ruby.ST.latency_hist_seqr::mean 17.479769 +system.ruby.ST.latency_hist_seqr::gmean 3.361529 +system.ruby.ST.latency_hist_seqr::stdev 31.340829 +system.ruby.ST.latency_hist_seqr | 592 68.44% 68.44% | 160 18.50% 86.94% | 102 11.79% 98.73% | 0 0.00% 98.73% | 4 0.46% 99.19% | 4 0.46% 99.65% | 1 0.12% 99.77% | 0 0.00% 99.77% | 1 0.12% 99.88% | 1 0.12% 100.00% system.ruby.ST.latency_hist_seqr::total 865 system.ruby.ST.hit_latency_hist_seqr::bucket_size 1 system.ruby.ST.hit_latency_hist_seqr::max_bucket 9 @@ -528,18 +538,18 @@ system.ruby.ST.hit_latency_hist_seqr::total 592 system.ruby.ST.miss_latency_hist_seqr::bucket_size 32 system.ruby.ST.miss_latency_hist_seqr::max_bucket 319 system.ruby.ST.miss_latency_hist_seqr::samples 273 -system.ruby.ST.miss_latency_hist_seqr::mean 49.879121 -system.ruby.ST.miss_latency_hist_seqr::gmean 44.729882 -system.ruby.ST.miss_latency_hist_seqr::stdev 29.942777 -system.ruby.ST.miss_latency_hist_seqr | 0 0.00% 0.00% | 242 88.64% 88.64% | 21 7.69% 96.34% | 1 0.37% 96.70% | 4 1.47% 98.17% | 4 1.47% 99.63% | 0 0.00% 99.63% | 0 0.00% 99.63% | 0 0.00% 99.63% | 1 0.37% 100.00% +system.ruby.ST.miss_latency_hist_seqr::mean 53.216117 +system.ruby.ST.miss_latency_hist_seqr::gmean 46.594106 +system.ruby.ST.miss_latency_hist_seqr::stdev 35.315815 +system.ruby.ST.miss_latency_hist_seqr | 0 0.00% 0.00% | 160 58.61% 58.61% | 102 37.36% 95.97% | 0 0.00% 95.97% | 4 1.47% 97.44% | 4 1.47% 98.90% | 1 0.37% 99.27% | 0 0.00% 99.27% | 1 0.37% 99.63% | 1 0.37% 100.00% system.ruby.ST.miss_latency_hist_seqr::total 273 system.ruby.IFETCH.latency_hist_seqr::bucket_size 64 system.ruby.IFETCH.latency_hist_seqr::max_bucket 639 system.ruby.IFETCH.latency_hist_seqr::samples 6413 -system.ruby.IFETCH.latency_hist_seqr::mean 7.333073 -system.ruby.IFETCH.latency_hist_seqr::gmean 1.563492 -system.ruby.IFETCH.latency_hist_seqr::stdev 21.145733 -system.ruby.IFETCH.latency_hist_seqr | 6295 98.16% 98.16% | 93 1.45% 99.61% | 18 0.28% 99.89% | 1 0.02% 99.91% | 3 0.05% 99.95% | 3 0.05% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.latency_hist_seqr::mean 7.699984 +system.ruby.IFETCH.latency_hist_seqr::gmean 1.571280 +system.ruby.IFETCH.latency_hist_seqr::stdev 22.534194 +system.ruby.IFETCH.latency_hist_seqr | 5994 93.47% 93.47% | 395 6.16% 99.63% | 16 0.25% 99.88% | 1 0.02% 99.89% | 3 0.05% 99.94% | 4 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.latency_hist_seqr::total 6413 system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 1 system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 9 @@ -551,18 +561,18 @@ system.ruby.IFETCH.hit_latency_hist_seqr::total 5683 system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 64 system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 639 system.ruby.IFETCH.miss_latency_hist_seqr::samples 730 -system.ruby.IFETCH.miss_latency_hist_seqr::mean 56.635616 -system.ruby.IFETCH.miss_latency_hist_seqr::gmean 50.712708 -system.ruby.IFETCH.miss_latency_hist_seqr::stdev 34.440483 -system.ruby.IFETCH.miss_latency_hist_seqr | 612 83.84% 83.84% | 93 12.74% 96.58% | 18 2.47% 99.04% | 1 0.14% 99.18% | 3 0.41% 99.59% | 3 0.41% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.miss_latency_hist_seqr::mean 59.858904 +system.ruby.IFETCH.miss_latency_hist_seqr::gmean 52.975537 +system.ruby.IFETCH.miss_latency_hist_seqr::stdev 37.310775 +system.ruby.IFETCH.miss_latency_hist_seqr | 311 42.60% 42.60% | 395 54.11% 96.71% | 16 2.19% 98.90% | 1 0.14% 99.04% | 3 0.41% 99.45% | 4 0.55% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.miss_latency_hist_seqr::total 730 system.ruby.Directory.miss_mach_latency_hist_seqr::bucket_size 64 system.ruby.Directory.miss_mach_latency_hist_seqr::max_bucket 639 system.ruby.Directory.miss_mach_latency_hist_seqr::samples 1731 -system.ruby.Directory.miss_mach_latency_hist_seqr::mean 53.073368 -system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 47.451096 -system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 32.911544 -system.ruby.Directory.miss_mach_latency_hist_seqr | 1488 85.96% 85.96% | 190 10.98% 96.94% | 41 2.37% 99.31% | 1 0.06% 99.36% | 6 0.35% 99.71% | 4 0.23% 99.94% | 1 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_mach_latency_hist_seqr::mean 56.207395 +system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 49.560362 +system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 35.333412 +system.ruby.Directory.miss_mach_latency_hist_seqr | 876 50.61% 50.61% | 798 46.10% 96.71% | 40 2.31% 99.02% | 5 0.29% 99.31% | 6 0.35% 99.65% | 6 0.35% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.Directory.miss_mach_latency_hist_seqr::total 1731 system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::bucket_size 1 system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::max_bucket 9 @@ -593,26 +603,26 @@ system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::total system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples 728 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 50.699176 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 45.385232 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 32.101179 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 634 87.09% 87.09% | 75 10.30% 97.39% | 15 2.06% 99.45% | 0 0.00% 99.45% | 2 0.27% 99.73% | 1 0.14% 99.86% | 1 0.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 53.667582 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 47.442261 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 32.940895 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 405 55.63% 55.63% | 301 41.35% 96.98% | 16 2.20% 99.18% | 3 0.41% 99.59% | 1 0.14% 99.73% | 2 0.27% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total 728 system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size 32 system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket 319 system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::samples 273 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 49.879121 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 44.729882 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 29.942777 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 242 88.64% 88.64% | 21 7.69% 96.34% | 1 0.37% 96.70% | 4 1.47% 98.17% | 4 1.47% 99.63% | 0 0.00% 99.63% | 0 0.00% 99.63% | 0 0.00% 99.63% | 1 0.37% 100.00% +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 53.216117 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 46.594106 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 35.315815 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 160 58.61% 58.61% | 102 37.36% 95.97% | 0 0.00% 95.97% | 4 1.47% 97.44% | 4 1.47% 98.90% | 1 0.37% 99.27% | 0 0.00% 99.27% | 1 0.37% 99.63% | 1 0.37% 100.00% system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total 273 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::samples 730 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 56.635616 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 50.712708 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 34.440483 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 612 83.84% 83.84% | 93 12.74% 96.58% | 18 2.47% 99.04% | 1 0.14% 99.18% | 3 0.41% 99.59% | 3 0.41% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 59.858904 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 52.975537 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 37.310775 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 311 42.60% 42.60% | 395 54.11% 96.71% | 16 2.19% 98.90% | 1 0.14% 99.04% | 3 0.41% 99.45% | 4 0.55% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::total 730 system.ruby.Directory_Controller.GETX 1731 0.00% 0.00% system.ruby.Directory_Controller.PUTX 1727 0.00% 0.00% diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/config.ini index ccd9350bc..220cfeeae 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/config.ini @@ -149,7 +149,7 @@ useIndirect=true [system.cpu.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -583,7 +583,7 @@ opClass=InstPrefetch [system.cpu.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -643,7 +643,7 @@ size=48 [system.cpu.l2cache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -760,6 +760,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -771,7 +772,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -779,29 +780,36 @@ width=16 master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -821,6 +829,7 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 @@ -830,7 +839,7 @@ p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 page_policy=open_adaptive power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 @@ -852,9 +861,9 @@ tRTW=2500 tWR=15000 tWTR=7500 tXAW=30000 -tXP=0 +tXP=6000 tXPDLL=0 -tXS=0 +tXS=270000 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/simout b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/simout index 115f46689..fff19a530 100755 --- a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/simout +++ b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/simout @@ -3,13 +3,13 @@ Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/minor- gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 19 2016 12:23:51 -gem5 started Jul 19 2016 12:24:24 -gem5 executing on e108600-lin, pid 39579 +gem5 compiled Oct 11 2016 00:00:58 +gem5 started Oct 13 2016 20:19:45 +gem5 executing on e108600-lin, pid 28071 command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/minor-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/alpha/tru64/minor-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 20329000 because target called exit() +Exiting @ tick 22083000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt index 95775a988..a6e87b576 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000021 # Number of seconds simulated -sim_ticks 20616000 # Number of ticks simulated -final_tick 20616000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000022 # Number of seconds simulated +sim_ticks 22083000 # Number of ticks simulated +final_tick 22083000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 91304 # Simulator instruction rate (inst/s) -host_op_rate 91266 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 727585147 # Simulator tick rate (ticks/s) -host_mem_usage 252076 # Number of bytes of host memory used -host_seconds 0.03 # Real time elapsed on the host +host_inst_rate 143746 # Simulator instruction rate (inst/s) +host_op_rate 143654 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1226490189 # Simulator tick rate (ticks/s) +host_mem_usage 251004 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host sim_insts 2585 # Number of instructions simulated sim_ops 2585 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 20616000 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 22083000 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 14400 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 5440 # Number of bytes read from this memory system.physmem.bytes_read::total 19840 # Number of bytes read from this memory @@ -22,14 +22,14 @@ system.physmem.bytes_inst_read::total 14400 # Nu system.physmem.num_reads::cpu.inst 225 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 85 # Number of read requests responded to by this memory system.physmem.num_reads::total 310 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 698486612 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 263872720 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 962359333 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 698486612 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 698486612 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 698486612 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 263872720 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 962359333 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 652085314 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 246343341 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 898428656 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 652085314 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 652085314 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 652085314 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 246343341 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 898428656 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 310 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 310 # Number of DRAM read bursts, including those serviced by the write queue @@ -76,7 +76,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 20527500 # Total gap between requests +system.physmem.totGap 21988500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -91,8 +91,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 246 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 61 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 245 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 62 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -188,77 +188,87 @@ system.physmem.wrQLenPdf::61 0 # Wh system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 41 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 424.585366 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 277.937119 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 331.553388 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 429.268293 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 281.212133 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 334.776868 # Bytes accessed per row activation system.physmem.bytesPerActivate::0-127 10 24.39% 24.39% # Bytes accessed per row activation system.physmem.bytesPerActivate::128-255 6 14.63% 39.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5 12.20% 51.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2 4.88% 56.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 6 14.63% 70.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2 4.88% 75.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 4 9.76% 85.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 3 7.32% 92.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6 14.63% 53.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2 4.88% 58.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3 7.32% 65.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2 4.88% 70.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 7 17.07% 87.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2 4.88% 92.68% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 3 7.32% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 41 # Bytes accessed per row activation -system.physmem.totQLat 1590750 # Total ticks spent queuing -system.physmem.totMemAccLat 7403250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 3615250 # Total ticks spent queuing +system.physmem.totMemAccLat 9427750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 1550000 # Total ticks spent in databus transfers -system.physmem.avgQLat 5131.45 # Average queueing delay per DRAM burst +system.physmem.avgQLat 11662.10 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 23881.45 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 962.36 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 30412.10 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 898.43 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 962.36 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 898.43 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 7.52 # Data bus utilization in percentage -system.physmem.busUtilRead 7.52 # Data bus utilization in percentage for reads +system.physmem.busUtil 7.02 # Data bus utilization in percentage +system.physmem.busUtilRead 7.02 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.24 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.26 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing system.physmem.readRowHits 260 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 83.87 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 66217.74 # Average gap between requests +system.physmem.avgGap 70930.65 # Average gap between requests system.physmem.pageHitRate 83.87 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 83160 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 45375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 787800 # Energy for read commands per rank (pJ) +system.physmem_0.actEnergy 114240 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 45540 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 885360 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 10790100 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 34500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 12758055 # Total energy per rank (pJ) -system.physmem_0.averagePower 805.814306 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 727750 # Time in different power states +system.physmem_0.refreshEnergy 1229280.000000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1636470 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 32160 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 7529700 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 729120 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 12201870 # Total energy per rank (pJ) +system.physmem_0.averagePower 552.527084 # Core power per rank (mW) +system.physmem_0.totalIdleTime 18356500 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 27500 # Time in different power states system.physmem_0.memoryStateTime::REF 520000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 15310750 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 189000 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 103125 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1162200 # Energy for read commands per rank (pJ) +system.physmem_0.memoryStateTime::SREF 0 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 1898500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 3124750 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 16512250 # Time in different power states +system.physmem_1.actEnergy 242760 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 110055 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1328040 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 10417320 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 361500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 13250265 # Total energy per rank (pJ) -system.physmem_1.averagePower 836.902890 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 560000 # Time in different power states +system.physmem_1.refreshEnergy 1229280.000000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 2565570 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 217440 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 7221900 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 20640 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 12935685 # Total energy per rank (pJ) +system.physmem_1.averagePower 585.755816 # Core power per rank (mW) +system.physmem_1.totalIdleTime 15168500 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 498000 # Time in different power states system.physmem_1.memoryStateTime::REF 520000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 14766250 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 20616000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 794 # Number of BP lookups -system.cpu.branchPred.condPredicted 394 # Number of conditional branches predicted +system.physmem_1.memoryStateTime::SREF 0 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 53000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 5182750 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 15829250 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 22083000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 793 # Number of BP lookups +system.cpu.branchPred.condPredicted 395 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 170 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 562 # Number of BTB lookups +system.cpu.branchPred.BTBLookups 561 # Number of BTB lookups system.cpu.branchPred.BTBHits 54 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 9.608541 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 9.625668 # BTB Hit Percentage system.cpu.branchPred.usedRAS 144 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 2 # Number of incorrect RAS predictions. system.cpu.branchPred.indirectLookups 83 # Number of indirect predictor lookups. @@ -282,10 +292,10 @@ system.cpu.dtb.data_hits 813 # DT system.cpu.dtb.data_misses 12 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations system.cpu.dtb.data_accesses 825 # DTB accesses -system.cpu.itb.fetch_hits 979 # ITB hits +system.cpu.itb.fetch_hits 980 # ITB hits system.cpu.itb.fetch_misses 13 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 992 # ITB accesses +system.cpu.itb.fetch_accesses 993 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -299,16 +309,16 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 20616000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 41232 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 22083000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 44166 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 2585 # Number of instructions committed system.cpu.committedOps 2585 # Number of ops (including micro ops) committed system.cpu.discardedOps 573 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 15.950484 # CPI: cycles per instruction -system.cpu.ipc 0.062694 # IPC: instructions per cycle +system.cpu.cpi 17.085493 # CPI: cycles per instruction +system.cpu.ipc 0.058529 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 189 7.31% 7.31% # Class of committed instruction system.cpu.op_class_0::IntAlu 1678 64.91% 72.22% # Class of committed instruction system.cpu.op_class_0::IntMult 1 0.04% 72.26% # Class of committed instruction @@ -344,25 +354,25 @@ system.cpu.op_class_0::MemWrite 298 11.53% 100.00% # Cl system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 2585 # Class of committed instruction -system.cpu.tickCycles 5423 # Number of cycles that the object actually ticked -system.cpu.idleCycles 35809 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 20616000 # Cumulative time (in ticks) in various power states +system.cpu.tickCycles 5429 # Number of cycles that the object actually ticked +system.cpu.idleCycles 38737 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 22083000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 48.342284 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 48.291787 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 692 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 85 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 8.141176 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 48.342284 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.011802 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.011802 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 48.291787 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.011790 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.011790 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 85 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 33 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 52 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 54 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.020752 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 1673 # Number of tag accesses system.cpu.dcache.tags.data_accesses 1673 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 20616000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 22083000 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 441 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 441 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 251 # number of WriteReq hits @@ -379,14 +389,14 @@ system.cpu.dcache.demand_misses::cpu.data 102 # n system.cpu.dcache.demand_misses::total 102 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 102 # number of overall misses system.cpu.dcache.overall_misses::total 102 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4617500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4617500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 3301000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 3301000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 7918500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 7918500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 7918500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 7918500 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5143500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5143500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 3553000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 3553000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 8696500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 8696500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 8696500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 8696500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 500 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 500 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 294 # number of WriteReq accesses(hits+misses) @@ -403,14 +413,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.128463 system.cpu.dcache.demand_miss_rate::total 0.128463 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.128463 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.128463 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 78262.711864 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 78262.711864 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76767.441860 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 76767.441860 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 77632.352941 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 77632.352941 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 77632.352941 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 77632.352941 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 87177.966102 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 87177.966102 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 82627.906977 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 82627.906977 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 85259.803922 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 85259.803922 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 85259.803922 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 85259.803922 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -433,14 +443,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 85 system.cpu.dcache.demand_mshr_misses::total 85 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 85 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4487000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4487000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2044500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2044500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6531500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6531500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6531500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6531500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5007000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5007000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2203500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2203500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7210500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7210500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7210500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7210500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.116000 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.116000 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.091837 # mshr miss rate for WriteReq accesses @@ -449,67 +459,67 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.107053 system.cpu.dcache.demand_mshr_miss_rate::total 0.107053 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.107053 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.107053 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77362.068966 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77362.068966 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75722.222222 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75722.222222 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76841.176471 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 76841.176471 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76841.176471 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 76841.176471 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 20616000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 86327.586207 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 86327.586207 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 81611.111111 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 81611.111111 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 84829.411765 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 84829.411765 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 84829.411765 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 84829.411765 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 22083000 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 119.307121 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 754 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 118.973491 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 755 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 225 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 3.351111 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 3.355556 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 119.307121 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.058255 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.058255 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 118.973491 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.058093 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.058093 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 225 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 98 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 127 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 90 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 135 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.109863 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 2183 # Number of tag accesses -system.cpu.icache.tags.data_accesses 2183 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 20616000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 754 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 754 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 754 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 754 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 754 # number of overall hits -system.cpu.icache.overall_hits::total 754 # number of overall hits +system.cpu.icache.tags.tag_accesses 2185 # Number of tag accesses +system.cpu.icache.tags.data_accesses 2185 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 22083000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 755 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 755 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 755 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 755 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 755 # number of overall hits +system.cpu.icache.overall_hits::total 755 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 225 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 225 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 225 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 225 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 225 # number of overall misses system.cpu.icache.overall_misses::total 225 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 17383000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 17383000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 17383000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 17383000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 17383000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 17383000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 979 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 979 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 979 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 979 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 979 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 979 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.229826 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.229826 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.229826 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.229826 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.229826 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.229826 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77257.777778 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 77257.777778 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 77257.777778 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 77257.777778 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 77257.777778 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 77257.777778 # average overall miss latency +system.cpu.icache.ReadReq_miss_latency::cpu.inst 18729500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 18729500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 18729500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 18729500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 18729500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 18729500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 980 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 980 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 980 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 980 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 980 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 980 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.229592 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.229592 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.229592 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.229592 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.229592 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.229592 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 83242.222222 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 83242.222222 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 83242.222222 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 83242.222222 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 83242.222222 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 83242.222222 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -522,43 +532,43 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 225 system.cpu.icache.demand_mshr_misses::total 225 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 225 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 225 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17158000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 17158000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17158000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 17158000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17158000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 17158000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.229826 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.229826 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.229826 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.229826 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.229826 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.229826 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 76257.777778 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 76257.777778 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76257.777778 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 76257.777778 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76257.777778 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 76257.777778 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 20616000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 18504500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 18504500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 18504500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 18504500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 18504500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 18504500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.229592 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.229592 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.229592 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.229592 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.229592 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.229592 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 82242.222222 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 82242.222222 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 82242.222222 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 82242.222222 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 82242.222222 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 82242.222222 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 22083000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 167.807293 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 167.412677 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 310 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 119.421716 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 48.385576 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003644 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.001477 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.005121 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 119.080474 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 48.332203 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003634 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.001475 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.005109 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 310 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 130 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 180 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 121 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 189 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.009460 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 2790 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 2790 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 20616000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 22083000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.ReadExReq_misses::cpu.data 27 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 27 # number of ReadExReq misses system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 225 # number of ReadCleanReq misses @@ -571,18 +581,18 @@ system.cpu.l2cache.demand_misses::total 310 # nu system.cpu.l2cache.overall_misses::cpu.inst 225 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 85 # number of overall misses system.cpu.l2cache.overall_misses::total 310 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2004000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 2004000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 16820500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 16820500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4399000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 4399000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 16820500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 6403000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 23223500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 16820500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 6403000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 23223500 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2163000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 2163000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 18167000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 18167000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4919000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 4919000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 18167000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7082000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 25249000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 18167000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7082000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 25249000 # number of overall miss cycles system.cpu.l2cache.ReadExReq_accesses::cpu.data 27 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 27 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 225 # number of ReadCleanReq accesses(hits+misses) @@ -607,18 +617,18 @@ system.cpu.l2cache.demand_miss_rate::total 1 # system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74222.222222 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74222.222222 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74757.777778 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74757.777778 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 75844.827586 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 75844.827586 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74757.777778 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75329.411765 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 74914.516129 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74757.777778 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75329.411765 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 74914.516129 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80111.111111 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80111.111111 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 80742.222222 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 80742.222222 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 84810.344828 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 84810.344828 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80742.222222 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 83317.647059 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 81448.387097 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80742.222222 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83317.647059 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 81448.387097 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -637,18 +647,18 @@ system.cpu.l2cache.demand_mshr_misses::total 310 system.cpu.l2cache.overall_mshr_misses::cpu.inst 225 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 310 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1734000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1734000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 14570500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 14570500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 3819000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 3819000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 14570500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5553000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 20123500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 14570500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5553000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 20123500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1893000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1893000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 15917000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 15917000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4339000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4339000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 15917000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6232000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 22149000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 15917000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6232000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 22149000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses @@ -661,25 +671,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 1 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64222.222222 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64222.222222 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64757.777778 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64757.777778 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 65844.827586 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 65844.827586 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64757.777778 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65329.411765 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64914.516129 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64757.777778 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65329.411765 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64914.516129 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70111.111111 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70111.111111 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70742.222222 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70742.222222 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 74810.344828 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 74810.344828 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70742.222222 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73317.647059 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71448.387097 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70742.222222 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73317.647059 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71448.387097 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 310 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 20616000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 22083000 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 283 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 27 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 27 # Transaction distribution @@ -705,9 +715,9 @@ system.cpu.toL2Bus.snoop_fanout::min_value 0 # system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 310 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 155000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%) +system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 337500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 1.6 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.utilization 1.5 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 127500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.6 # Layer utilization (%) system.membus.snoop_filter.tot_requests 310 # Total number of requests made to the snoop filter. @@ -716,7 +726,7 @@ system.membus.snoop_filter.hit_multi_requests 0 system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 20616000 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 22083000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 283 # Transaction distribution system.membus.trans_dist::ReadExReq 27 # Transaction distribution system.membus.trans_dist::ReadExResp 27 # Transaction distribution @@ -737,9 +747,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 310 # Request fanout histogram -system.membus.reqLayer0.occupancy 363000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.8 # Layer utilization (%) +system.membus.reqLayer0.occupancy 362500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.6 # Layer utilization (%) system.membus.respLayer1.occupancy 1648750 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 8.0 # Layer utilization (%) +system.membus.respLayer1.utilization 7.5 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini index 39c72e110..ff6825b17 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini @@ -173,7 +173,7 @@ useIndirect=true [system.cpu.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -531,7 +531,7 @@ pipelined=false [system.cpu.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -591,7 +591,7 @@ size=48 [system.cpu.l2cache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -708,6 +708,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -719,7 +720,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -727,29 +728,36 @@ width=16 master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -769,6 +777,7 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 @@ -778,7 +787,7 @@ p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 page_policy=open_adaptive power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 @@ -800,9 +809,9 @@ tRTW=2500 tWR=15000 tWTR=7500 tXAW=30000 -tXP=0 +tXP=6000 tXPDLL=0 -tXS=0 +tXS=270000 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout index 5515360ee..35f169b23 100755 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout @@ -3,13 +3,13 @@ Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/o3-tim gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 19 2016 12:23:51 -gem5 started Jul 19 2016 12:24:24 -gem5 executing on e108600-lin, pid 39577 +gem5 compiled Oct 11 2016 00:00:58 +gem5 started Oct 13 2016 20:19:49 +gem5 executing on e108600-lin, pid 28097 command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 12409500 because target called exit() +Exiting @ tick 13358500 because target called exit() diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt index cdae5e837..cecea8f6e 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000013 # Number of seconds simulated -sim_ticks 12542500 # Number of ticks simulated -final_tick 12542500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 13358500 # Number of ticks simulated +final_tick 13358500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 60996 # Simulator instruction rate (inst/s) -host_op_rate 60977 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 320317516 # Simulator tick rate (ticks/s) -host_mem_usage 253100 # Number of bytes of host memory used -host_seconds 0.04 # Real time elapsed on the host +host_inst_rate 53089 # Simulator instruction rate (inst/s) +host_op_rate 53060 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 296795260 # Simulator tick rate (ticks/s) +host_mem_usage 251260 # Number of bytes of host memory used +host_seconds 0.05 # Real time elapsed on the host sim_insts 2387 # Number of instructions simulated sim_ops 2387 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 12542500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 13358500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 11968 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 5440 # Number of bytes read from this memory system.physmem.bytes_read::total 17408 # Number of bytes read from this memory @@ -22,14 +22,14 @@ system.physmem.bytes_inst_read::total 11968 # Nu system.physmem.num_reads::cpu.inst 187 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 85 # Number of read requests responded to by this memory system.physmem.num_reads::total 272 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 954195735 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 433725334 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1387921068 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 954195735 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 954195735 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 954195735 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 433725334 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1387921068 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 895908972 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 407231351 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1303140323 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 895908972 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 895908972 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 895908972 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 407231351 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1303140323 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 272 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 272 # Number of DRAM read bursts, including those serviced by the write queue @@ -76,7 +76,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 12445000 # Total gap between requests +system.physmem.totGap 13255000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -91,10 +91,10 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 157 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 155 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 80 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 29 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 28 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 8 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -188,81 +188,91 @@ system.physmem.wrQLenPdf::61 0 # Wh system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 36 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 394.666667 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 235.952583 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 357.320824 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 384 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 235.532687 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 344.140835 # Bytes accessed per row activation system.physmem.bytesPerActivate::0-127 12 33.33% 33.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 5 13.89% 47.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 3 8.33% 55.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3 8.33% 63.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3 8.33% 72.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2 5.56% 77.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 2 5.56% 83.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 4 11.11% 44.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4 11.11% 55.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 6 16.67% 72.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2 5.56% 77.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1 2.78% 80.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1 2.78% 83.33% # Bytes accessed per row activation system.physmem.bytesPerActivate::896-1023 1 2.78% 86.11% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 5 13.89% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 36 # Bytes accessed per row activation -system.physmem.totQLat 1866000 # Total ticks spent queuing -system.physmem.totMemAccLat 6966000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 3364250 # Total ticks spent queuing +system.physmem.totMemAccLat 8464250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 1360000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6860.29 # Average queueing delay per DRAM burst +system.physmem.avgQLat 12368.57 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25610.29 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1387.92 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 31118.57 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1303.14 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1387.92 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1303.14 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 10.84 # Data bus utilization in percentage -system.physmem.busUtilRead 10.84 # Data bus utilization in percentage for reads +system.physmem.busUtil 10.18 # Data bus utilization in percentage +system.physmem.busUtilRead 10.18 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.70 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.73 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 226 # Number of row buffer hits during reads +system.physmem.readRowHits 224 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.09 # Row buffer hit rate for reads +system.physmem.readRowHitRate 82.35 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 45753.68 # Average gap between requests -system.physmem.pageHitRate 83.09 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 68040 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 37125 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 585000 # Energy for read commands per rank (pJ) +system.physmem.avgGap 48731.62 # Average gap between requests +system.physmem.pageHitRate 82.35 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 99960 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 37950 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 756840 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 508560 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 5478840 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 21750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 6699315 # Total energy per rank (pJ) -system.physmem_0.averagePower 832.600901 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 22500 # Time in different power states +system.physmem_0.refreshEnergy 614640.000000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1355460 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 21600 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 4583370 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 107040 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 7576860 # Total energy per rank (pJ) +system.physmem_0.averagePower 567.183307 # Core power per rank (mW) +system.physmem_0.totalIdleTime 10278500 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 28500 # Time in different power states system.physmem_0.memoryStateTime::REF 260000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 7777500 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 128520 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 70125 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 787800 # Energy for read commands per rank (pJ) +system.physmem_0.memoryStateTime::SREF 0 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 279000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 2735250 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 10055750 # Time in different power states +system.physmem_1.actEnergy 242760 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 98670 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1185240 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 508560 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 5198400 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 267750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 6961155 # Total energy per rank (pJ) -system.physmem_1.averagePower 865.142768 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 432500 # Time in different power states +system.physmem_1.refreshEnergy 614640.000000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1822290 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 183840 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 4050420 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 480 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 8198340 # Total energy per rank (pJ) +system.physmem_1.averagePower 613.705624 # Core power per rank (mW) +system.physmem_1.totalIdleTime 8246250 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 450500 # Time in different power states system.physmem_1.memoryStateTime::REF 260000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 7367500 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 12542500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 1001 # Number of BP lookups -system.cpu.branchPred.condPredicted 492 # Number of conditional branches predicted +system.physmem_1.memoryStateTime::SREF 0 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 1250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 3767500 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 8879250 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 13358500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 994 # Number of BP lookups +system.cpu.branchPred.condPredicted 488 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 213 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 687 # Number of BTB lookups -system.cpu.branchPred.BTBHits 176 # Number of BTB hits +system.cpu.branchPred.BTBLookups 684 # Number of BTB lookups +system.cpu.branchPred.BTBHits 175 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 25.618632 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 220 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 25.584795 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 218 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 18 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 100 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 3 # Number of indirect target hits. +system.cpu.branchPred.indirectLookups 99 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 2 # Number of indirect target hits. system.cpu.branchPred.indirectMisses 97 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 33 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks @@ -270,22 +280,22 @@ system.cpu.dtb.fetch_hits 0 # IT system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 712 # DTB read hits -system.cpu.dtb.read_misses 13 # DTB read misses +system.cpu.dtb.read_hits 705 # DTB read hits +system.cpu.dtb.read_misses 10 # DTB read misses system.cpu.dtb.read_acv 1 # DTB read access violations -system.cpu.dtb.read_accesses 725 # DTB read accesses +system.cpu.dtb.read_accesses 715 # DTB read accesses system.cpu.dtb.write_hits 349 # DTB write hits -system.cpu.dtb.write_misses 17 # DTB write misses +system.cpu.dtb.write_misses 16 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 366 # DTB write accesses -system.cpu.dtb.data_hits 1061 # DTB hits -system.cpu.dtb.data_misses 30 # DTB misses +system.cpu.dtb.write_accesses 365 # DTB write accesses +system.cpu.dtb.data_hits 1054 # DTB hits +system.cpu.dtb.data_misses 26 # DTB misses system.cpu.dtb.data_acv 1 # DTB access violations -system.cpu.dtb.data_accesses 1091 # DTB accesses -system.cpu.itb.fetch_hits 877 # ITB hits +system.cpu.dtb.data_accesses 1080 # DTB accesses +system.cpu.itb.fetch_hits 872 # ITB hits system.cpu.itb.fetch_misses 32 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 909 # ITB accesses +system.cpu.itb.fetch_accesses 904 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -299,193 +309,193 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 12542500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 25086 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 13358500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 26718 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 4377 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 6059 # Number of instructions fetch has processed -system.cpu.fetch.Branches 1001 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 399 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 1174 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.icacheStallCycles 4379 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 6026 # Number of instructions fetch has processed +system.cpu.fetch.Branches 994 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 395 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 1172 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 472 # Number of cycles fetch has spent squashing system.cpu.fetch.MiscStallCycles 18 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1154 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingTrapStallCycles 1202 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 11 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 877 # Number of cache lines fetched +system.cpu.fetch.CacheLines 872 # Number of cache lines fetched system.cpu.fetch.IcacheSquashes 147 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 6970 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.869297 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.271813 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 7018 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.858649 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.260497 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 5938 85.19% 85.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 27 0.39% 85.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 100 1.43% 87.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 87 1.25% 88.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 141 2.02% 90.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 81 1.16% 91.45% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 45 0.65% 92.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 76 1.09% 93.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 475 6.81% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 5993 85.39% 85.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 27 0.38% 85.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 97 1.38% 87.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 87 1.24% 88.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 140 1.99% 90.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 81 1.15% 91.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 45 0.64% 92.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 75 1.07% 93.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 473 6.74% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 6970 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.039903 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.241529 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 5221 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 627 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 919 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 40 # Number of cycles decode is unblocking +system.cpu.fetch.rateDist::total 7018 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.037203 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.225541 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 5261 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 642 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 913 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 39 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 163 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 145 # Number of times decode resolved a branch +system.cpu.decode.BranchResolved 144 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 75 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 5274 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 5228 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 263 # Number of squashed instructions handled by decode system.cpu.rename.SquashCycles 163 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 5296 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 329 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 290 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 881 # Number of cycles rename is running +system.cpu.rename.IdleCycles 5336 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 333 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 302 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 873 # Number of cycles rename is running system.cpu.rename.UnblockCycles 11 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 5069 # Number of instructions processed by rename +system.cpu.rename.RenamedInsts 5015 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 1 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 2 # Number of times rename has blocked due to IQ full -system.cpu.rename.RenamedOperands 3638 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 5669 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 5662 # Number of integer rename lookups +system.cpu.rename.RenamedOperands 3598 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 5603 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 5596 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 6 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1768 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 1870 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 1830 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 8 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 6 # count of temporary serializing insts renamed system.cpu.rename.skidInsts 62 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 846 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 428 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. +system.cpu.memDep0.insertedLoads 838 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 424 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 0 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 4387 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 4336 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 6 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 3758 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 28 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 2005 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1025 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 3724 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 19 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 1954 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 987 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 6970 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.539168 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.278867 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 7018 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.530636 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.266302 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 5524 79.25% 79.25% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 467 6.70% 85.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 343 4.92% 90.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 254 3.64% 94.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 193 2.77% 97.29% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 103 1.48% 98.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 56 0.80% 99.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 20 0.29% 99.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 10 0.14% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 5580 79.51% 79.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 466 6.64% 86.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 341 4.86% 91.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 254 3.62% 94.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 190 2.71% 97.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 104 1.48% 98.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 55 0.78% 99.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 20 0.28% 99.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 8 0.11% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 6970 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 7018 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 6 9.84% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 31 50.82% 60.66% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 24 39.34% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 6 10.00% 10.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 10.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 10.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 10.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 10.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 10.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 10.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 10.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 10.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 10.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 10.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 10.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 10.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 10.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 10.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 10.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 10.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 10.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 10.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 10.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 10.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 10.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 10.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 10.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 10.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 10.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 10.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 10.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 30 50.00% 60.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 24 40.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 2627 69.90% 69.90% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.03% 69.93% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 69.93% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 69.93% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 69.93% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 69.93% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 69.93% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 69.93% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 69.93% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 69.93% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 69.93% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 69.93% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 69.93% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 69.93% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 69.93% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 69.93% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 69.93% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 69.93% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.93% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 69.93% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 69.93% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.93% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 69.93% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 69.93% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.93% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 69.93% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 69.93% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.93% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.93% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 757 20.14% 90.07% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 373 9.93% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 2606 69.98% 69.98% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.03% 70.01% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.01% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.01% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.01% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.01% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.01% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.01% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 70.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 70.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 70.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 70.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.01% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 745 20.01% 90.01% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 372 9.99% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 3758 # Type of FU issued -system.cpu.iq.rate 0.149805 # Inst issue rate -system.cpu.iq.fu_busy_cnt 61 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.016232 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 14562 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 6395 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 3419 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 3724 # Type of FU issued +system.cpu.iq.rate 0.139382 # Inst issue rate +system.cpu.iq.fu_busy_cnt 60 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.016112 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 14532 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 6293 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 3394 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 13 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 6 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 6 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 3812 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 3777 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 7 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 33 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 32 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 431 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 423 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 4 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 134 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 130 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 56 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 42 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewSquashCycles 163 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 299 # Number of cycles IEW is blocking +system.cpu.iew.iewBlockCycles 304 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 3 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 4700 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispatchedInsts 4648 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 46 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 846 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 428 # Number of dispatched store instructions +system.cpu.iew.iewDispLoadInsts 838 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 424 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 6 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall @@ -493,41 +503,41 @@ system.cpu.iew.memOrderViolationEvents 4 # Nu system.cpu.iew.predictedTakenIncorrect 33 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 132 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 165 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 3634 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 727 # Number of load instructions executed +system.cpu.iew.iewExecutedInsts 3600 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 717 # Number of load instructions executed system.cpu.iew.iewExecSquashedInsts 124 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 307 # number of nop insts executed -system.cpu.iew.exec_refs 1093 # number of memory reference insts executed -system.cpu.iew.exec_branches 599 # Number of branches executed -system.cpu.iew.exec_stores 366 # Number of stores executed -system.cpu.iew.exec_rate 0.144862 # Inst execution rate -system.cpu.iew.wb_sent 3483 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 3425 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1633 # num instructions producing a value -system.cpu.iew.wb_consumers 2097 # num instructions consuming a value -system.cpu.iew.wb_rate 0.136530 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.778732 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 2122 # The number of squashed insts skipped by commit +system.cpu.iew.exec_nop 306 # number of nop insts executed +system.cpu.iew.exec_refs 1082 # number of memory reference insts executed +system.cpu.iew.exec_branches 595 # Number of branches executed +system.cpu.iew.exec_stores 365 # Number of stores executed +system.cpu.iew.exec_rate 0.134741 # Inst execution rate +system.cpu.iew.wb_sent 3453 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 3400 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1619 # num instructions producing a value +system.cpu.iew.wb_consumers 2076 # num instructions consuming a value +system.cpu.iew.wb_rate 0.127255 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.779865 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 2070 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 140 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 6555 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.392982 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.248476 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 6610 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.389713 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.245121 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 5684 86.71% 86.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 198 3.02% 89.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 318 4.85% 94.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 118 1.80% 96.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 63 0.96% 97.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 53 0.81% 98.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 37 0.56% 98.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 23 0.35% 99.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 61 0.93% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 5740 86.84% 86.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 197 2.98% 89.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 319 4.83% 94.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 117 1.77% 96.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 63 0.95% 97.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 53 0.80% 98.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 36 0.54% 98.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 23 0.35% 99.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 62 0.94% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 6555 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 6610 # Number of insts commited each cycle system.cpu.commit.committedInsts 2576 # Number of instructions committed system.cpu.commit.committedOps 2576 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -573,47 +583,47 @@ system.cpu.commit.op_class_0::MemWrite 294 11.41% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 2576 # Class of committed instruction -system.cpu.commit.bw_lim_events 61 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 10945 # The number of ROB reads -system.cpu.rob.rob_writes 9815 # The number of ROB writes +system.cpu.commit.bw_lim_events 62 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 10947 # The number of ROB reads +system.cpu.rob.rob_writes 9704 # The number of ROB writes system.cpu.timesIdled 154 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 18116 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 19700 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 2387 # Number of Instructions Simulated system.cpu.committedOps 2387 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 10.509426 # CPI: Cycles Per Instruction -system.cpu.cpi_total 10.509426 # CPI: Total CPI of All Threads -system.cpu.ipc 0.095153 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.095153 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 4383 # number of integer regfile reads -system.cpu.int_regfile_writes 2640 # number of integer regfile writes +system.cpu.cpi 11.193129 # CPI: Cycles Per Instruction +system.cpu.cpi_total 11.193129 # CPI: Total CPI of All Threads +system.cpu.ipc 0.089341 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.089341 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 4344 # number of integer regfile reads +system.cpu.int_regfile_writes 2618 # number of integer regfile writes system.cpu.fp_regfile_reads 6 # number of floating regfile reads system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 12542500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 13358500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 45.419736 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 735 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 45.378002 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 743 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 85 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 8.647059 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 8.741176 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 45.419736 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.011089 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.011089 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 45.378002 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.011079 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.011079 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 85 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 24 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.020752 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1919 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1919 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 12542500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 522 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 522 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 1935 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1935 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 13358500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 530 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 530 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 213 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 213 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 735 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 735 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 735 # number of overall hits -system.cpu.dcache.overall_hits::total 735 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 743 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 743 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 743 # number of overall hits +system.cpu.dcache.overall_hits::total 743 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 101 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 101 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 81 # number of WriteReq misses @@ -622,43 +632,43 @@ system.cpu.dcache.demand_misses::cpu.data 182 # n system.cpu.dcache.demand_misses::total 182 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 182 # number of overall misses system.cpu.dcache.overall_misses::total 182 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 6754500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 6754500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 5744000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 5744000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 12498500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 12498500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 12498500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 12498500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 623 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 623 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_latency::cpu.data 7124500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 7124500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 6134000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 6134000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 13258500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 13258500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 13258500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 13258500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 631 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 631 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 294 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 294 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 917 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 917 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 917 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 917 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.162119 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.162119 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 925 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 925 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 925 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 925 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.160063 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.160063 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.275510 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.275510 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.198473 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.198473 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.198473 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.198473 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66876.237624 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 66876.237624 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70913.580247 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 70913.580247 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 68673.076923 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 68673.076923 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 68673.076923 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 68673.076923 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 260 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.196757 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.196757 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.196757 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.196757 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 70539.603960 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 70539.603960 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75728.395062 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 75728.395062 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 72848.901099 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 72848.901099 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 72848.901099 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 72848.901099 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 269 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 6 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 4 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 43.333333 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 67.250000 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.ReadReq_mshr_hits::cpu.data 40 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 40 # number of ReadReq MSHR hits @@ -676,138 +686,138 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 85 system.cpu.dcache.demand_mshr_misses::total 85 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 85 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4858000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4858000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1875000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1875000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6733000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6733000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6733000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6733000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.097913 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.097913 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5157500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5157500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2004000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2004000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7161500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7161500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7161500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7161500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.096672 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.096672 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081633 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.081633 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.092694 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.092694 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.092694 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.092694 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 79639.344262 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 79639.344262 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78125 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78125 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 79211.764706 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 79211.764706 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 79211.764706 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 79211.764706 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 12542500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091892 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.091892 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091892 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.091892 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 84549.180328 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 84549.180328 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 83500 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 83500 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 84252.941176 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 84252.941176 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 84252.941176 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 84252.941176 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 13358500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 90.302659 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 624 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 89.996713 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 618 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 187 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 3.336898 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 3.304813 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 90.302659 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.044093 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.044093 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 89.996713 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.043944 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.043944 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 187 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 156 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 31 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 150 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 37 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.091309 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 1941 # Number of tag accesses -system.cpu.icache.tags.data_accesses 1941 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 12542500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 624 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 624 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 624 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 624 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 624 # number of overall hits -system.cpu.icache.overall_hits::total 624 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 253 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 253 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 253 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 253 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 253 # number of overall misses -system.cpu.icache.overall_misses::total 253 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 19081499 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 19081499 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 19081499 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 19081499 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 19081499 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 19081499 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 877 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 877 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 877 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 877 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 877 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 877 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.288483 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.288483 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.288483 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.288483 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.288483 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.288483 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75420.944664 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 75420.944664 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 75420.944664 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 75420.944664 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 75420.944664 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 75420.944664 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 127 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 1931 # Number of tag accesses +system.cpu.icache.tags.data_accesses 1931 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 13358500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 618 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 618 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 618 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 618 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 618 # number of overall hits +system.cpu.icache.overall_hits::total 618 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 254 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 254 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 254 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 254 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 254 # number of overall misses +system.cpu.icache.overall_misses::total 254 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 20808999 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 20808999 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 20808999 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 20808999 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 20808999 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 20808999 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 872 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 872 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 872 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 872 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 872 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 872 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.291284 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.291284 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.291284 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.291284 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.291284 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.291284 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 81925.192913 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 81925.192913 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 81925.192913 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 81925.192913 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 81925.192913 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 81925.192913 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 131 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 63.500000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 65.500000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 66 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 66 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 66 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 66 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 66 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 66 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 67 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 67 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 67 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 67 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 67 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 67 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 187 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 187 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 187 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 187 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 187 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 187 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14560999 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 14560999 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14560999 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 14560999 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14560999 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 14560999 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.213227 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.213227 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.213227 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.213227 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.213227 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.213227 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 77866.304813 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 77866.304813 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 77866.304813 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 77866.304813 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 77866.304813 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 77866.304813 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 12542500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15635499 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 15635499 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15635499 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 15635499 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15635499 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 15635499 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.214450 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.214450 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.214450 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.214450 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.214450 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.214450 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 83612.294118 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 83612.294118 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 83612.294118 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 83612.294118 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 83612.294118 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 83612.294118 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 13358500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 135.950101 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 135.588512 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 272 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 90.459206 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 45.490894 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002761 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.001388 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.004149 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 90.143699 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 45.444813 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002751 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.001387 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.004138 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 272 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 217 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 55 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 207 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 65 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.008301 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 2448 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 2448 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 12542500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 13358500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.ReadExReq_misses::cpu.data 24 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 24 # number of ReadExReq misses system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 187 # number of ReadCleanReq misses @@ -820,18 +830,18 @@ system.cpu.l2cache.demand_misses::total 272 # nu system.cpu.l2cache.overall_misses::cpu.inst 187 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 85 # number of overall misses system.cpu.l2cache.overall_misses::total 272 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1837500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1837500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 14279500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 14279500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4766500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 4766500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 14279500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 6604000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 20883500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 14279500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 6604000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 20883500 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1966500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1966500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 15354000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 15354000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 5066000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 5066000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 15354000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7032500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 22386500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 15354000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7032500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 22386500 # number of overall miss cycles system.cpu.l2cache.ReadExReq_accesses::cpu.data 24 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 24 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 187 # number of ReadCleanReq accesses(hits+misses) @@ -856,18 +866,18 @@ system.cpu.l2cache.demand_miss_rate::total 1 # system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76562.500000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76562.500000 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76360.962567 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76360.962567 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 78139.344262 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 78139.344262 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76360.962567 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77694.117647 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 76777.573529 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76360.962567 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77694.117647 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 76777.573529 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81937.500000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81937.500000 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82106.951872 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82106.951872 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83049.180328 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83049.180328 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82106.951872 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 82735.294118 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 82303.308824 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82106.951872 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 82735.294118 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 82303.308824 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -886,18 +896,18 @@ system.cpu.l2cache.demand_mshr_misses::total 272 system.cpu.l2cache.overall_mshr_misses::cpu.inst 187 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 272 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1597500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1597500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 12409500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 12409500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4156500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4156500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12409500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5754000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 18163500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12409500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5754000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 18163500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1726500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1726500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 13484000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 13484000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4456000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4456000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 13484000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6182500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 19666500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 13484000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6182500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 19666500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses @@ -910,25 +920,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 1 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66562.500000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66562.500000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66360.962567 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66360.962567 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 68139.344262 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 68139.344262 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66360.962567 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67694.117647 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66777.573529 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66360.962567 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67694.117647 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66777.573529 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71937.500000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71937.500000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72106.951872 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72106.951872 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73049.180328 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73049.180328 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72106.951872 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72735.294118 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72303.308824 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72106.951872 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72735.294118 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72303.308824 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 272 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 12542500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 13358500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 248 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 24 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 24 # Transaction distribution @@ -954,9 +964,9 @@ system.cpu.toL2Bus.snoop_fanout::min_value 0 # system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 272 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 136000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) +system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 280500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.2 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.utilization 2.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 127500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) system.membus.snoop_filter.tot_requests 272 # Total number of requests made to the snoop filter. @@ -965,7 +975,7 @@ system.membus.snoop_filter.hit_multi_requests 0 system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 12542500 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 13358500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 248 # Transaction distribution system.membus.trans_dist::ReadExReq 24 # Transaction distribution system.membus.trans_dist::ReadExResp 24 # Transaction distribution @@ -987,8 +997,8 @@ system.membus.snoop_fanout::min_value 0 # Re system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 272 # Request fanout histogram system.membus.reqLayer0.occupancy 337500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 1440000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 11.5 # Layer utilization (%) +system.membus.reqLayer0.utilization 2.5 # Layer utilization (%) +system.membus.respLayer1.occupancy 1437500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 10.8 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/config.ini index 214f11946..41209dc7f 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/config.ini @@ -14,6 +14,7 @@ children=clk_domain cpu dvfs_handler mem_ctrls ruby sys_port_proxy voltage_domai boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 exit_on_work_items=false init_param=0 @@ -22,11 +23,15 @@ kernel_addr_check=true load_addr_mask=1099511627775 load_offset=0 mem_mode=timing -mem_ranges=0:268435455 +mem_ranges=0:268435455:0:0:0:0 memories=system.mem_ctrls mmap_using_noreserve=false multi_thread=false num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null readfile= symbolfile= thermal_components= @@ -55,6 +60,7 @@ branchPred=Null checker=Null clk_domain=system.cpu.clk_domain cpu_id=0 +default_p_state=UNDEFINED do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true @@ -70,6 +76,10 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null profile=0 progress_interval=0 simpoint_start_insts= @@ -122,7 +132,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello +executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/alpha/tru64/hello gid=100 input=cin kvmInSE=false @@ -145,27 +155,27 @@ transition_latency=100000 [system.mem_ctrls] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -177,6 +187,7 @@ burst_length=8 channels=1 clk_domain=system.clk_domain conf_table_reported=true +default_p_state=UNDEFINED device_bus_width=8 device_rowbuffer_size=1024 device_size=536870912 @@ -184,12 +195,17 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 page_policy=open_adaptive -range=0:268435455 +power_model=Null +range=0:268435455:5:19:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10 @@ -211,9 +227,9 @@ tRTW=3 tWR=15 tWTR=8 tXAW=30 -tXP=0 +tXP=6 tXPDLL=0 -tXS=0 +tXS=270 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 @@ -227,12 +243,17 @@ access_backing_store=false all_instructions=false block_size_bytes=64 clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED eventq_index=0 hot_lines=false memory_size_bits=48 num_of_sequencers=1 number_of_virtual_networks=3 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 phys_mem=Null +power_model=Null randomization=false [system.ruby.clk_domain] @@ -249,10 +270,15 @@ children=directory requestToDir responseFromDir responseFromMemory responseToDir buffer_size=0 clk_domain=system.ruby.clk_domain cluster_id=0 +default_p_state=UNDEFINED directory=system.ruby.dir_cntrl0.directory directory_latency=6 eventq_index=0 number_of_TBEs=256 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null recycle_latency=10 requestToDir=system.ruby.dir_cntrl0.requestToDir responseFromDir=system.ruby.dir_cntrl0.responseFromDir @@ -311,6 +337,7 @@ L1Icache=system.ruby.l1_cntrl0.L1Icache buffer_size=0 clk_domain=system.cpu.clk_domain cluster_id=0 +default_p_state=UNDEFINED enable_prefetch=false eventq_index=0 l1_request_latency=2 @@ -319,6 +346,10 @@ l2_select_num_bits=0 mandatoryQueue=system.ruby.l1_cntrl0.mandatoryQueue number_of_TBEs=256 optionalQueue=system.ruby.l1_cntrl0.optionalQueue +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null prefetcher=system.ruby.l1_cntrl0.prefetcher recycle_latency=10 requestFromL1Cache=system.ruby.l1_cntrl0.requestFromL1Cache @@ -447,17 +478,22 @@ coreid=99 dcache=system.ruby.l1_cntrl0.L1Dcache dcache_hit_latency=1 deadlock_threshold=500000 +default_p_state=UNDEFINED eventq_index=0 +garnet_standalone=false icache=system.ruby.l1_cntrl0.L1Icache icache_hit_latency=1 is_cpu_sequencer=true max_outstanding_requests=16 no_retry_on_stall=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null ruby_system=system.ruby support_data_reqs=true support_inst_reqs=true system=system -using_network_tester=false using_ruby_tester=false version=0 slave=system.cpu.icache_port system.cpu.dcache_port @@ -480,10 +516,15 @@ L2cache=system.ruby.l2_cntrl0.L2cache buffer_size=0 clk_domain=system.ruby.clk_domain cluster_id=0 +default_p_state=UNDEFINED eventq_index=0 l2_request_latency=2 l2_response_latency=2 number_of_TBEs=256 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null recycle_latency=10 responseFromL2Cache=system.ruby.l2_cntrl0.responseFromL2Cache responseToL2Cache=system.ruby.l2_cntrl0.responseToL2Cache @@ -574,18 +615,23 @@ eventq_index=0 [system.ruby.network] type=SimpleNetwork -children=ext_links0 ext_links1 ext_links2 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_links0 int_links1 int_links2 routers0 routers1 routers2 routers3 +children=ext_links0 ext_links1 ext_links2 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_link_buffers20 int_link_buffers21 int_link_buffers22 int_link_buffers23 int_link_buffers24 int_link_buffers25 int_link_buffers26 int_link_buffers27 int_link_buffers28 int_link_buffers29 int_link_buffers30 int_link_buffers31 int_link_buffers32 int_link_buffers33 int_link_buffers34 int_link_buffers35 int_links0 int_links1 int_links2 int_links3 int_links4 int_links5 routers0 routers1 routers2 routers3 adaptive_routing=false buffer_size=0 clk_domain=system.ruby.clk_domain control_msg_size=8 +default_p_state=UNDEFINED endpoint_bandwidth=1000 eventq_index=0 ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1 system.ruby.network.ext_links2 -int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 -int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2 +int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19 system.ruby.network.int_link_buffers20 system.ruby.network.int_link_buffers21 system.ruby.network.int_link_buffers22 system.ruby.network.int_link_buffers23 system.ruby.network.int_link_buffers24 system.ruby.network.int_link_buffers25 system.ruby.network.int_link_buffers26 system.ruby.network.int_link_buffers27 system.ruby.network.int_link_buffers28 system.ruby.network.int_link_buffers29 system.ruby.network.int_link_buffers30 system.ruby.network.int_link_buffers31 system.ruby.network.int_link_buffers32 system.ruby.network.int_link_buffers33 system.ruby.network.int_link_buffers34 system.ruby.network.int_link_buffers35 +int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2 system.ruby.network.int_links3 system.ruby.network.int_links4 system.ruby.network.int_links5 netifs= number_of_virtual_networks=3 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null routers=system.ruby.network.routers0 system.ruby.network.routers1 system.ruby.network.routers2 system.ruby.network.routers3 ruby_system=system.ruby topology=Crossbar @@ -748,42 +794,216 @@ eventq_index=0 ordered=true randomization=false +[system.ruby.network.int_link_buffers18] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers19] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers20] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers21] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers22] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers23] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers24] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers25] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers26] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers27] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers28] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers29] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers30] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers31] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers32] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers33] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers34] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers35] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + [system.ruby.network.int_links0] type=SimpleIntLink bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers3 eventq_index=0 latency=1 link_id=3 -node_a=system.ruby.network.routers0 -node_b=system.ruby.network.routers3 +src_node=system.ruby.network.routers0 +src_outport= weight=1 [system.ruby.network.int_links1] type=SimpleIntLink bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers3 eventq_index=0 latency=1 link_id=4 -node_a=system.ruby.network.routers1 -node_b=system.ruby.network.routers3 +src_node=system.ruby.network.routers1 +src_outport= weight=1 [system.ruby.network.int_links2] type=SimpleIntLink bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers3 eventq_index=0 latency=1 link_id=5 -node_a=system.ruby.network.routers2 -node_b=system.ruby.network.routers3 +src_node=system.ruby.network.routers2 +src_outport= +weight=1 + +[system.ruby.network.int_links3] +type=SimpleIntLink +bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers0 +eventq_index=0 +latency=1 +link_id=6 +src_node=system.ruby.network.routers3 +src_outport= +weight=1 + +[system.ruby.network.int_links4] +type=SimpleIntLink +bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers1 +eventq_index=0 +latency=1 +link_id=7 +src_node=system.ruby.network.routers3 +src_outport= +weight=1 + +[system.ruby.network.int_links5] +type=SimpleIntLink +bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers2 +eventq_index=0 +latency=1 +link_id=8 +src_node=system.ruby.network.routers3 +src_outport= weight=1 [system.ruby.network.routers0] type=Switch children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED eventq_index=0 +latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 port_buffers=system.ruby.network.routers0.port_buffers00 system.ruby.network.routers0.port_buffers01 system.ruby.network.routers0.port_buffers02 system.ruby.network.routers0.port_buffers03 system.ruby.network.routers0.port_buffers04 system.ruby.network.routers0.port_buffers05 system.ruby.network.routers0.port_buffers06 system.ruby.network.routers0.port_buffers07 system.ruby.network.routers0.port_buffers08 system.ruby.network.routers0.port_buffers09 system.ruby.network.routers0.port_buffers10 system.ruby.network.routers0.port_buffers11 +power_model=Null router_id=0 virt_nets=3 @@ -875,8 +1095,14 @@ randomization=false type=Switch children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED eventq_index=0 +latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 port_buffers=system.ruby.network.routers1.port_buffers00 system.ruby.network.routers1.port_buffers01 system.ruby.network.routers1.port_buffers02 system.ruby.network.routers1.port_buffers03 system.ruby.network.routers1.port_buffers04 system.ruby.network.routers1.port_buffers05 system.ruby.network.routers1.port_buffers06 system.ruby.network.routers1.port_buffers07 system.ruby.network.routers1.port_buffers08 system.ruby.network.routers1.port_buffers09 system.ruby.network.routers1.port_buffers10 system.ruby.network.routers1.port_buffers11 +power_model=Null router_id=1 virt_nets=3 @@ -968,8 +1194,14 @@ randomization=false type=Switch children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED eventq_index=0 +latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 port_buffers=system.ruby.network.routers2.port_buffers00 system.ruby.network.routers2.port_buffers01 system.ruby.network.routers2.port_buffers02 system.ruby.network.routers2.port_buffers03 system.ruby.network.routers2.port_buffers04 system.ruby.network.routers2.port_buffers05 system.ruby.network.routers2.port_buffers06 system.ruby.network.routers2.port_buffers07 system.ruby.network.routers2.port_buffers08 system.ruby.network.routers2.port_buffers09 system.ruby.network.routers2.port_buffers10 system.ruby.network.routers2.port_buffers11 +power_model=Null router_id=2 virt_nets=3 @@ -1061,8 +1293,14 @@ randomization=false type=Switch children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17 clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED eventq_index=0 +latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 port_buffers=system.ruby.network.routers3.port_buffers00 system.ruby.network.routers3.port_buffers01 system.ruby.network.routers3.port_buffers02 system.ruby.network.routers3.port_buffers03 system.ruby.network.routers3.port_buffers04 system.ruby.network.routers3.port_buffers05 system.ruby.network.routers3.port_buffers06 system.ruby.network.routers3.port_buffers07 system.ruby.network.routers3.port_buffers08 system.ruby.network.routers3.port_buffers09 system.ruby.network.routers3.port_buffers10 system.ruby.network.routers3.port_buffers11 system.ruby.network.routers3.port_buffers12 system.ruby.network.routers3.port_buffers13 system.ruby.network.routers3.port_buffers14 system.ruby.network.routers3.port_buffers15 system.ruby.network.routers3.port_buffers16 system.ruby.network.routers3.port_buffers17 +power_model=Null router_id=3 virt_nets=3 @@ -1195,9 +1433,14 @@ randomization=false [system.sys_port_proxy] type=RubyPortProxy clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 is_cpu_sequencer=true no_retry_on_stall=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null ruby_system=system.ruby support_data_reqs=true support_inst_reqs=true diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/simerr b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/simerr index 1c18978fa..63982fce4 100755 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/simerr +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/simerr @@ -4,9 +4,8 @@ warn: rounding error > tolerance 1.250000 rounded to 1 warn: rounding error > tolerance 1.250000 rounded to 1 -warn: rounding error > tolerance - 1.250000 rounded to 1 warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes) warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files! warn: ignoring syscall sigprocmask(1, ...) diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/simout index 321d1816d..fcadeb2be 100755 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/simout +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/simout @@ -1,13 +1,15 @@ +Redirecting stdout to build/ALPHA_MESI_Two_Level/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MESI_Two_Level/simout +Redirecting stderr to build/ALPHA_MESI_Two_Level/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MESI_Two_Level/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 21 2016 14:01:33 -gem5 started Jan 21 2016 14:02:10 -gem5 executing on zizzer, pid 44711 -command line: build/ALPHA_MESI_Two_Level/gem5.opt -d build/ALPHA_MESI_Two_Level/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MESI_Two_Level -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ALPHA_MESI_Two_Level/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MESI_Two_Level +gem5 compiled Oct 13 2016 20:28:06 +gem5 started Oct 13 2016 20:28:32 +gem5 executing on e108600-lin, pid 8237 +command line: /work/curdun01/gem5-external.hg/build/ALPHA_MESI_Two_Level/gem5.opt -d build/ALPHA_MESI_Two_Level/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MESI_Two_Level -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/alpha/tru64/simple-timing-ruby-MESI_Two_Level Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 45733 because target called exit() +Exiting @ tick 48659 because target called exit() diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/stats.txt index 5ca935512..d4dee56c3 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000046 # Number of seconds simulated -sim_ticks 45733 # Number of ticks simulated -final_tick 45733 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000049 # Number of seconds simulated +sim_ticks 48659 # Number of ticks simulated +final_tick 48659 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 61876 # Simulator instruction rate (inst/s) -host_op_rate 61863 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1097622 # Simulator tick rate (ticks/s) -host_mem_usage 452416 # Number of bytes of host memory used -host_seconds 0.04 # Real time elapsed on the host +host_inst_rate 43978 # Simulator instruction rate (inst/s) +host_op_rate 43962 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 829814 # Simulator tick rate (ticks/s) +host_mem_usage 410700 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks -system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 45733 # Cumulative time (in ticks) in various power states +system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 48659 # Cumulative time (in ticks) in various power states system.mem_ctrls.bytes_read::ruby.dir_cntrl0 35008 # Number of bytes read from this memory system.mem_ctrls.bytes_read::total 35008 # Number of bytes read from this memory system.mem_ctrls.bytes_written::ruby.dir_cntrl0 6592 # Number of bytes written to this memory @@ -22,12 +22,12 @@ system.mem_ctrls.num_reads::ruby.dir_cntrl0 547 # system.mem_ctrls.num_reads::total 547 # Number of read requests responded to by this memory system.mem_ctrls.num_writes::ruby.dir_cntrl0 103 # Number of write requests responded to by this memory system.mem_ctrls.num_writes::total 103 # Number of write requests responded to by this memory -system.mem_ctrls.bw_read::ruby.dir_cntrl0 765486629 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_read::total 765486629 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::ruby.dir_cntrl0 144140992 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::total 144140992 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_total::ruby.dir_cntrl0 909627621 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.bw_total::total 909627621 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_read::ruby.dir_cntrl0 719455805 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 719455805 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::ruby.dir_cntrl0 135473396 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::total 135473396 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::ruby.dir_cntrl0 854929201 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 854929201 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrls.readReqs 547 # Number of read requests accepted system.mem_ctrls.writeReqs 103 # Number of write requests accepted system.mem_ctrls.readBursts 547 # Number of DRAM read bursts, including those serviced by the write queue @@ -74,7 +74,7 @@ system.mem_ctrls.perBankWrBursts::14 0 # Pe system.mem_ctrls.perBankWrBursts::15 1 # Per bank write bursts system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrls.totGap 45654 # Total gap between requests +system.mem_ctrls.totGap 48574 # Total gap between requests system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) @@ -185,20 +185,20 @@ system.mem_ctrls.wrQLenPdf::60 0 # Wh system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrls.bytesPerActivate::samples 74 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::mean 358.054054 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::gmean 233.275053 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::stdev 307.922241 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::0-127 18 24.32% 24.32% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::128-255 18 24.32% 48.65% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::256-383 8 10.81% 59.46% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::384-511 4 5.41% 64.86% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::512-639 9 12.16% 77.03% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::640-767 7 9.46% 86.49% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::768-895 3 4.05% 90.54% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::896-1023 1 1.35% 91.89% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::1024-1151 6 8.11% 100.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::total 74 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::samples 83 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 339.277108 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 221.785975 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 292.728223 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 23 27.71% 27.71% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 19 22.89% 50.60% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 6 7.23% 57.83% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 10 12.05% 69.88% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 11 13.25% 83.13% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 4 4.82% 87.95% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 3 3.61% 91.57% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 3 3.61% 95.18% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 4 4.82% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 83 # Bytes accessed per row activation system.mem_ctrls.rdPerTurnAround::samples 1 # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::mean 268 # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::gmean 268.000000 # Reads before turning the bus around for writes @@ -211,57 +211,67 @@ system.mem_ctrls.wrPerTurnAround::gmean 16.000000 # Wr system.mem_ctrls.wrPerTurnAround::stdev nan # Writes before turning the bus around for reads system.mem_ctrls.wrPerTurnAround::16 1 100.00% 100.00% # Writes before turning the bus around for reads system.mem_ctrls.wrPerTurnAround::total 1 # Writes before turning the bus around for reads -system.mem_ctrls.totQLat 2733 # Total ticks spent queuing -system.mem_ctrls.totMemAccLat 11055 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.totQLat 5659 # Total ticks spent queuing +system.mem_ctrls.totMemAccLat 13981 # Total ticks spent from burst creation until serviced by the DRAM system.mem_ctrls.totBusLat 2190 # Total ticks spent in databus transfers -system.mem_ctrls.avgQLat 6.24 # Average queueing delay per DRAM burst +system.mem_ctrls.avgQLat 12.92 # Average queueing delay per DRAM burst system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst -system.mem_ctrls.avgMemAccLat 25.24 # Average memory access latency per DRAM burst -system.mem_ctrls.avgRdBW 612.95 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrls.avgWrBW 22.39 # Average achieved write bandwidth in MiByte/s -system.mem_ctrls.avgRdBWSys 765.49 # Average system read bandwidth in MiByte/s -system.mem_ctrls.avgWrBWSys 144.14 # Average system write bandwidth in MiByte/s +system.mem_ctrls.avgMemAccLat 31.92 # Average memory access latency per DRAM burst +system.mem_ctrls.avgRdBW 576.09 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 21.04 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 719.46 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 135.47 # Average system write bandwidth in MiByte/s system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrls.busUtil 4.96 # Data bus utilization in percentage -system.mem_ctrls.busUtilRead 4.79 # Data bus utilization in percentage for reads -system.mem_ctrls.busUtilWrite 0.17 # Data bus utilization in percentage for writes +system.mem_ctrls.busUtil 4.67 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 4.50 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 0.16 # Data bus utilization in percentage for writes system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing system.mem_ctrls.avgWrQLen 22.48 # Average write queue length when enqueuing -system.mem_ctrls.readRowHits 356 # Number of row buffer hits during reads +system.mem_ctrls.readRowHits 349 # Number of row buffer hits during reads system.mem_ctrls.writeRowHits 15 # Number of row buffer hits during writes -system.mem_ctrls.readRowHitRate 81.28 # Row buffer hit rate for reads +system.mem_ctrls.readRowHitRate 79.68 # Row buffer hit rate for reads system.mem_ctrls.writeRowHitRate 32.61 # Row buffer hit rate for writes -system.mem_ctrls.avgGap 70.24 # Average gap between requests -system.mem_ctrls.pageHitRate 76.65 # Row buffer hit rate, read and write combined -system.mem_ctrls_0.actEnergy 143640 # Energy for activate commands per rank (pJ) -system.mem_ctrls_0.preEnergy 79800 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_0.readEnergy 1797120 # Energy for read commands per rank (pJ) +system.mem_ctrls.avgGap 74.73 # Average gap between requests +system.mem_ctrls.pageHitRate 75.21 # Row buffer hit rate, read and write combined +system.mem_ctrls_0.actEnergy 199920 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 92736 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 2124864 # Energy for read commands per rank (pJ) system.mem_ctrls_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.mem_ctrls_0.refreshEnergy 2542800 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_0.actBackEnergy 26498844 # Energy for active background per rank (pJ) -system.mem_ctrls_0.preBackEnergy 269400 # Energy for precharge background per rank (pJ) -system.mem_ctrls_0.totalEnergy 31331604 # Total energy per rank (pJ) -system.mem_ctrls_0.averagePower 799.479561 # Core power per rank (mW) -system.mem_ctrls_0.memoryStateTime::IDLE 528 # Time in different power states -system.mem_ctrls_0.memoryStateTime::REF 1300 # Time in different power states -system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT 37581 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrls_1.actEnergy 362880 # Energy for activate commands per rank (pJ) -system.mem_ctrls_1.preEnergy 201600 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_1.readEnergy 2882880 # Energy for read commands per rank (pJ) -system.mem_ctrls_1.writeEnergy 165888 # Energy for write commands per rank (pJ) -system.mem_ctrls_1.refreshEnergy 2542800 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_1.actBackEnergy 26204040 # Energy for active background per rank (pJ) -system.mem_ctrls_1.preBackEnergy 528000 # Energy for precharge background per rank (pJ) -system.mem_ctrls_1.totalEnergy 32888088 # Total energy per rank (pJ) -system.mem_ctrls_1.averagePower 839.195917 # Core power per rank (mW) -system.mem_ctrls_1.memoryStateTime::IDLE 754 # Time in different power states -system.mem_ctrls_1.memoryStateTime::REF 1300 # Time in different power states -system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT 37150 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 45733 # Cumulative time (in ticks) in various power states +system.mem_ctrls_0.refreshEnergy 3687840.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 3071616 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 85248 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.actPowerDownEnergy 18833256 # Energy for active power-down per rank (pJ) +system.mem_ctrls_0.prePowerDownEnergy 153600 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls_0.totalEnergy 28249080 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 580.552005 # Core power per rank (mW) +system.mem_ctrls_0.totalIdleTime 41659 # Total Idle time Per DRAM Rank +system.mem_ctrls_0.memoryStateTime::IDLE 54 # Time in different power states +system.mem_ctrls_0.memoryStateTime::REF 1560 # Time in different power states +system.mem_ctrls_0.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls_0.memoryStateTime::PRE_PDN 400 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 5344 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT_PDN 41301 # Time in different power states +system.mem_ctrls_1.actEnergy 442680 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 227976 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 2878848 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 133632 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.refreshEnergy 3687840.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 4289136 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 272256 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.actPowerDownEnergy 17021568 # Energy for active power-down per rank (pJ) +system.mem_ctrls_1.prePowerDownEnergy 466944 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls_1.totalEnergy 29420880 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 604.633881 # Core power per rank (mW) +system.mem_ctrls_1.totalIdleTime 37647 # Total Idle time Per DRAM Rank +system.mem_ctrls_1.memoryStateTime::IDLE 541 # Time in different power states +system.mem_ctrls_1.memoryStateTime::REF 1560 # Time in different power states +system.mem_ctrls_1.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls_1.memoryStateTime::PRE_PDN 1216 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 8014 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT_PDN 37328 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 48659 # Cumulative time (in ticks) in various power states system.cpu.clk_domain.clock 1 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -296,8 +306,8 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 45733 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 45733 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 48659 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 48659 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 2577 # Number of instructions committed @@ -316,7 +326,7 @@ system.cpu.num_mem_refs 717 # nu system.cpu.num_load_insts 419 # Number of load instructions system.cpu.num_store_insts 298 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 45733 # Number of busy cycles +system.cpu.num_busy_cycles 48659 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 396 # Number of branches fetched @@ -356,7 +366,7 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 2585 # Class of executed instruction system.ruby.clk_domain.clock 1 # Clock period in ticks -system.ruby.pwrStateResidencyTicks::UNDEFINED 45733 # Cumulative time (in ticks) in various power states +system.ruby.pwrStateResidencyTicks::UNDEFINED 48659 # Cumulative time (in ticks) in various power states system.ruby.delayHist::bucket_size 1 # delay histogram for all message system.ruby.delayHist::max_bucket 9 # delay histogram for all message system.ruby.delayHist::samples 3612 # delay histogram for all message @@ -374,10 +384,10 @@ system.ruby.outstanding_req_hist_seqr::total 3295 system.ruby.latency_hist_seqr::bucket_size 64 system.ruby.latency_hist_seqr::max_bucket 639 system.ruby.latency_hist_seqr::samples 3294 -system.ruby.latency_hist_seqr::mean 12.883728 -system.ruby.latency_hist_seqr::gmean 2.062291 -system.ruby.latency_hist_seqr::stdev 28.863704 -system.ruby.latency_hist_seqr | 2856 86.70% 86.70% | 432 13.11% 99.82% | 1 0.03% 99.85% | 0 0.00% 99.85% | 1 0.03% 99.88% | 4 0.12% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.latency_hist_seqr::mean 13.772010 +system.ruby.latency_hist_seqr::gmean 2.084389 +system.ruby.latency_hist_seqr::stdev 31.264017 +system.ruby.latency_hist_seqr | 2856 86.70% 86.70% | 431 13.08% 99.79% | 1 0.03% 99.82% | 0 0.00% 99.82% | 2 0.06% 99.88% | 4 0.12% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.latency_hist_seqr::total 3294 system.ruby.hit_latency_hist_seqr::bucket_size 1 system.ruby.hit_latency_hist_seqr::max_bucket 9 @@ -389,12 +399,12 @@ system.ruby.hit_latency_hist_seqr::total 2722 system.ruby.miss_latency_hist_seqr::bucket_size 64 system.ruby.miss_latency_hist_seqr::max_bucket 639 system.ruby.miss_latency_hist_seqr::samples 572 -system.ruby.miss_latency_hist_seqr::mean 69.435315 -system.ruby.miss_latency_hist_seqr::gmean 64.604000 -system.ruby.miss_latency_hist_seqr::stdev 30.458568 -system.ruby.miss_latency_hist_seqr | 134 23.43% 23.43% | 432 75.52% 98.95% | 1 0.17% 99.13% | 0 0.00% 99.13% | 1 0.17% 99.30% | 4 0.70% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.miss_latency_hist_seqr::mean 74.550699 +system.ruby.miss_latency_hist_seqr::gmean 68.693513 +system.ruby.miss_latency_hist_seqr::stdev 34.041428 +system.ruby.miss_latency_hist_seqr | 134 23.43% 23.43% | 431 75.35% 98.78% | 1 0.17% 98.95% | 0 0.00% 98.95% | 2 0.35% 99.30% | 4 0.70% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.miss_latency_hist_seqr::total 572 -system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 45733 # Cumulative time (in ticks) in various power states +system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 48659 # Cumulative time (in ticks) in various power states system.ruby.l1_cntrl0.L1Dcache.demand_hits 437 # Number of cache demand hits system.ruby.l1_cntrl0.L1Dcache.demand_misses 272 # Number of cache demand misses system.ruby.l1_cntrl0.L1Dcache.demand_accesses 709 # Number of cache demand accesses @@ -410,15 +420,15 @@ system.ruby.l1_cntrl0.prefetcher.hits 0 # nu system.ruby.l1_cntrl0.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched system.ruby.l1_cntrl0.prefetcher.pages_crossed 0 # number of prefetches across pages system.ruby.l1_cntrl0.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed -system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 45733 # Cumulative time (in ticks) in various power states -system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 45733 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 48659 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 48659 # Cumulative time (in ticks) in various power states system.ruby.l2_cntrl0.L2cache.demand_hits 25 # Number of cache demand hits system.ruby.l2_cntrl0.L2cache.demand_misses 547 # Number of cache demand misses system.ruby.l2_cntrl0.L2cache.demand_accesses 572 # Number of cache demand accesses -system.ruby.l2_cntrl0.pwrStateResidencyTicks::UNDEFINED 45733 # Cumulative time (in ticks) in various power states +system.ruby.l2_cntrl0.pwrStateResidencyTicks::UNDEFINED 48659 # Cumulative time (in ticks) in various power states system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 45733 # Cumulative time (in ticks) in various power states -system.ruby.network.routers0.percent_links_utilized 4.350250 +system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 48659 # Cumulative time (in ticks) in various power states +system.ruby.network.routers0.percent_links_utilized 4.088658 system.ruby.network.routers0.msg_count.Control::0 572 system.ruby.network.routers0.msg_count.Request_Control::2 431 system.ruby.network.routers0.msg_count.Response_Data::1 572 @@ -435,8 +445,8 @@ system.ruby.network.routers0.msg_bytes.Response_Control::2 2176 system.ruby.network.routers0.msg_bytes.Writeback_Data::0 3240 system.ruby.network.routers0.msg_bytes.Writeback_Data::1 4464 system.ruby.network.routers0.msg_bytes.Writeback_Control::0 632 -system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 45733 # Cumulative time (in ticks) in various power states -system.ruby.network.routers1.percent_links_utilized 8.380163 +system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 48659 # Cumulative time (in ticks) in various power states +system.ruby.network.routers1.percent_links_utilized 7.876241 system.ruby.network.routers1.msg_count.Control::0 1119 system.ruby.network.routers1.msg_count.Request_Control::2 431 system.ruby.network.routers1.msg_count.Response_Data::1 1222 @@ -453,16 +463,16 @@ system.ruby.network.routers1.msg_bytes.Response_Control::2 2176 system.ruby.network.routers1.msg_bytes.Writeback_Data::0 3240 system.ruby.network.routers1.msg_bytes.Writeback_Data::1 4464 system.ruby.network.routers1.msg_bytes.Writeback_Control::0 632 -system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 45733 # Cumulative time (in ticks) in various power states -system.ruby.network.routers2.percent_links_utilized 4.029913 +system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 48659 # Cumulative time (in ticks) in various power states +system.ruby.network.routers2.percent_links_utilized 3.787583 system.ruby.network.routers2.msg_count.Control::0 547 system.ruby.network.routers2.msg_count.Response_Data::1 650 system.ruby.network.routers2.msg_count.Response_Control::1 975 system.ruby.network.routers2.msg_bytes.Control::0 4376 system.ruby.network.routers2.msg_bytes.Response_Data::1 46800 system.ruby.network.routers2.msg_bytes.Response_Control::1 7800 -system.ruby.network.routers3.pwrStateResidencyTicks::UNDEFINED 45733 # Cumulative time (in ticks) in various power states -system.ruby.network.routers3.percent_links_utilized 5.586775 +system.ruby.network.routers3.pwrStateResidencyTicks::UNDEFINED 48659 # Cumulative time (in ticks) in various power states +system.ruby.network.routers3.percent_links_utilized 5.250827 system.ruby.network.routers3.msg_count.Control::0 1119 system.ruby.network.routers3.msg_count.Request_Control::2 431 system.ruby.network.routers3.msg_count.Response_Data::1 1222 @@ -479,7 +489,7 @@ system.ruby.network.routers3.msg_bytes.Response_Control::2 2176 system.ruby.network.routers3.msg_bytes.Writeback_Data::0 3240 system.ruby.network.routers3.msg_bytes.Writeback_Data::1 4464 system.ruby.network.routers3.msg_bytes.Writeback_Control::0 632 -system.ruby.network.pwrStateResidencyTicks::UNDEFINED 45733 # Cumulative time (in ticks) in various power states +system.ruby.network.pwrStateResidencyTicks::UNDEFINED 48659 # Cumulative time (in ticks) in various power states system.ruby.network.msg_count.Control 3357 system.ruby.network.msg_count.Request_Control 1293 system.ruby.network.msg_count.Response_Data 3666 @@ -492,15 +502,15 @@ system.ruby.network.msg_byte.Response_Data 263952 system.ruby.network.msg_byte.Response_Control 41760 system.ruby.network.msg_byte.Writeback_Data 23112 system.ruby.network.msg_byte.Writeback_Control 1896 -system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 45733 # Cumulative time (in ticks) in various power states -system.ruby.network.routers0.throttle0.link_utilization 6.235104 +system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 48659 # Cumulative time (in ticks) in various power states +system.ruby.network.routers0.throttle0.link_utilization 5.860170 system.ruby.network.routers0.throttle0.msg_count.Request_Control::2 431 system.ruby.network.routers0.throttle0.msg_count.Response_Data::1 572 system.ruby.network.routers0.throttle0.msg_count.Response_Control::1 124 system.ruby.network.routers0.throttle0.msg_bytes.Request_Control::2 3448 system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::1 41184 system.ruby.network.routers0.throttle0.msg_bytes.Response_Control::1 992 -system.ruby.network.routers0.throttle1.link_utilization 2.465397 +system.ruby.network.routers0.throttle1.link_utilization 2.317146 system.ruby.network.routers0.throttle1.msg_count.Control::0 572 system.ruby.network.routers0.throttle1.msg_count.Response_Control::1 369 system.ruby.network.routers0.throttle1.msg_count.Response_Control::2 272 @@ -513,7 +523,7 @@ system.ruby.network.routers0.throttle1.msg_bytes.Response_Control::2 217 system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::0 3240 system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::1 4464 system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::0 632 -system.ruby.network.routers1.throttle0.link_utilization 8.437015 +system.ruby.network.routers1.throttle0.link_utilization 7.929674 system.ruby.network.routers1.throttle0.msg_count.Control::0 572 system.ruby.network.routers1.throttle0.msg_count.Response_Data::1 547 system.ruby.network.routers1.throttle0.msg_count.Response_Control::1 908 @@ -528,7 +538,7 @@ system.ruby.network.routers1.throttle0.msg_bytes.Response_Control::2 217 system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::0 3240 system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::1 4464 system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::0 632 -system.ruby.network.routers1.throttle1.link_utilization 8.323311 +system.ruby.network.routers1.throttle1.link_utilization 7.822808 system.ruby.network.routers1.throttle1.msg_count.Control::0 547 system.ruby.network.routers1.throttle1.msg_count.Request_Control::2 431 system.ruby.network.routers1.throttle1.msg_count.Response_Data::1 675 @@ -537,26 +547,26 @@ system.ruby.network.routers1.throttle1.msg_bytes.Control::0 4376 system.ruby.network.routers1.throttle1.msg_bytes.Request_Control::2 3448 system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::1 48600 system.ruby.network.routers1.throttle1.msg_bytes.Response_Control::1 4480 -system.ruby.network.routers2.throttle0.link_utilization 2.088208 +system.ruby.network.routers2.throttle0.link_utilization 1.962638 system.ruby.network.routers2.throttle0.msg_count.Control::0 547 system.ruby.network.routers2.throttle0.msg_count.Response_Data::1 103 system.ruby.network.routers2.throttle0.msg_count.Response_Control::1 436 system.ruby.network.routers2.throttle0.msg_bytes.Control::0 4376 system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::1 7416 system.ruby.network.routers2.throttle0.msg_bytes.Response_Control::1 3488 -system.ruby.network.routers2.throttle1.link_utilization 5.971618 +system.ruby.network.routers2.throttle1.link_utilization 5.612528 system.ruby.network.routers2.throttle1.msg_count.Response_Data::1 547 system.ruby.network.routers2.throttle1.msg_count.Response_Control::1 539 system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::1 39384 system.ruby.network.routers2.throttle1.msg_bytes.Response_Control::1 4312 -system.ruby.network.routers3.throttle0.link_utilization 6.235104 +system.ruby.network.routers3.throttle0.link_utilization 5.860170 system.ruby.network.routers3.throttle0.msg_count.Request_Control::2 431 system.ruby.network.routers3.throttle0.msg_count.Response_Data::1 572 system.ruby.network.routers3.throttle0.msg_count.Response_Control::1 124 system.ruby.network.routers3.throttle0.msg_bytes.Request_Control::2 3448 system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::1 41184 system.ruby.network.routers3.throttle0.msg_bytes.Response_Control::1 992 -system.ruby.network.routers3.throttle1.link_utilization 8.437015 +system.ruby.network.routers3.throttle1.link_utilization 7.929674 system.ruby.network.routers3.throttle1.msg_count.Control::0 572 system.ruby.network.routers3.throttle1.msg_count.Response_Data::1 547 system.ruby.network.routers3.throttle1.msg_count.Response_Control::1 908 @@ -571,7 +581,7 @@ system.ruby.network.routers3.throttle1.msg_bytes.Response_Control::2 217 system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::0 3240 system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::1 4464 system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::0 632 -system.ruby.network.routers3.throttle2.link_utilization 2.088208 +system.ruby.network.routers3.throttle2.link_utilization 1.962638 system.ruby.network.routers3.throttle2.msg_count.Control::0 547 system.ruby.network.routers3.throttle2.msg_count.Response_Data::1 103 system.ruby.network.routers3.throttle2.msg_count.Response_Control::1 436 @@ -597,13 +607,13 @@ system.ruby.delayVCHist.vnet_2::max_bucket 9 # system.ruby.delayVCHist.vnet_2::samples 431 # delay histogram for vnet_2 system.ruby.delayVCHist.vnet_2 | 431 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 system.ruby.delayVCHist.vnet_2::total 431 # delay histogram for vnet_2 -system.ruby.LD.latency_hist_seqr::bucket_size 32 -system.ruby.LD.latency_hist_seqr::max_bucket 319 +system.ruby.LD.latency_hist_seqr::bucket_size 64 +system.ruby.LD.latency_hist_seqr::max_bucket 639 system.ruby.LD.latency_hist_seqr::samples 415 -system.ruby.LD.latency_hist_seqr::mean 31.356627 -system.ruby.LD.latency_hist_seqr::gmean 7.342788 -system.ruby.LD.latency_hist_seqr::stdev 35.995277 -system.ruby.LD.latency_hist_seqr | 223 53.73% 53.73% | 75 18.07% 71.81% | 106 25.54% 97.35% | 10 2.41% 99.76% | 0 0.00% 99.76% | 0 0.00% 99.76% | 0 0.00% 99.76% | 0 0.00% 99.76% | 0 0.00% 99.76% | 1 0.24% 100.00% +system.ruby.LD.latency_hist_seqr::mean 33.824096 +system.ruby.LD.latency_hist_seqr::gmean 7.531942 +system.ruby.LD.latency_hist_seqr::stdev 41.807535 +system.ruby.LD.latency_hist_seqr | 298 71.81% 71.81% | 115 27.71% 99.52% | 0 0.00% 99.52% | 0 0.00% 99.52% | 0 0.00% 99.52% | 2 0.48% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.latency_hist_seqr::total 415 system.ruby.LD.hit_latency_hist_seqr::bucket_size 1 system.ruby.LD.hit_latency_hist_seqr::max_bucket 9 @@ -612,21 +622,21 @@ system.ruby.LD.hit_latency_hist_seqr::mean 1 system.ruby.LD.hit_latency_hist_seqr::gmean 1 system.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 211 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.hit_latency_hist_seqr::total 211 -system.ruby.LD.miss_latency_hist_seqr::bucket_size 32 -system.ruby.LD.miss_latency_hist_seqr::max_bucket 319 +system.ruby.LD.miss_latency_hist_seqr::bucket_size 64 +system.ruby.LD.miss_latency_hist_seqr::max_bucket 639 system.ruby.LD.miss_latency_hist_seqr::samples 204 -system.ruby.LD.miss_latency_hist_seqr::mean 62.754902 -system.ruby.LD.miss_latency_hist_seqr::gmean 57.734169 -system.ruby.LD.miss_latency_hist_seqr::stdev 26.340677 -system.ruby.LD.miss_latency_hist_seqr | 12 5.88% 5.88% | 75 36.76% 42.65% | 106 51.96% 94.61% | 10 4.90% 99.51% | 0 0.00% 99.51% | 0 0.00% 99.51% | 0 0.00% 99.51% | 0 0.00% 99.51% | 0 0.00% 99.51% | 1 0.49% 100.00% +system.ruby.LD.miss_latency_hist_seqr::mean 67.774510 +system.ruby.LD.miss_latency_hist_seqr::gmean 60.800044 +system.ruby.LD.miss_latency_hist_seqr::stdev 35.866860 +system.ruby.LD.miss_latency_hist_seqr | 87 42.65% 42.65% | 115 56.37% 99.02% | 0 0.00% 99.02% | 0 0.00% 99.02% | 0 0.00% 99.02% | 2 0.98% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.miss_latency_hist_seqr::total 204 -system.ruby.ST.latency_hist_seqr::bucket_size 64 -system.ruby.ST.latency_hist_seqr::max_bucket 639 +system.ruby.ST.latency_hist_seqr::bucket_size 16 +system.ruby.ST.latency_hist_seqr::max_bucket 159 system.ruby.ST.latency_hist_seqr::samples 294 -system.ruby.ST.latency_hist_seqr::mean 14.789116 -system.ruby.ST.latency_hist_seqr::gmean 2.517478 -system.ruby.ST.latency_hist_seqr::stdev 31.573573 -system.ruby.ST.latency_hist_seqr | 264 89.80% 89.80% | 29 9.86% 99.66% | 0 0.00% 99.66% | 0 0.00% 99.66% | 0 0.00% 99.66% | 1 0.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.latency_hist_seqr::mean 14.469388 +system.ruby.ST.latency_hist_seqr::gmean 2.523301 +system.ruby.ST.latency_hist_seqr::stdev 26.779037 +system.ruby.ST.latency_hist_seqr | 226 76.87% 76.87% | 4 1.36% 78.23% | 33 11.22% 89.46% | 1 0.34% 89.80% | 14 4.76% 94.56% | 14 4.76% 99.32% | 2 0.68% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ST.latency_hist_seqr::total 294 system.ruby.ST.hit_latency_hist_seqr::bucket_size 1 system.ruby.ST.hit_latency_hist_seqr::max_bucket 9 @@ -635,21 +645,21 @@ system.ruby.ST.hit_latency_hist_seqr::mean 1 system.ruby.ST.hit_latency_hist_seqr::gmean 1 system.ruby.ST.hit_latency_hist_seqr | 0 0.00% 0.00% | 226 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ST.hit_latency_hist_seqr::total 226 -system.ruby.ST.miss_latency_hist_seqr::bucket_size 64 -system.ruby.ST.miss_latency_hist_seqr::max_bucket 639 +system.ruby.ST.miss_latency_hist_seqr::bucket_size 16 +system.ruby.ST.miss_latency_hist_seqr::max_bucket 159 system.ruby.ST.miss_latency_hist_seqr::samples 68 -system.ruby.ST.miss_latency_hist_seqr::mean 60.617647 -system.ruby.ST.miss_latency_hist_seqr::gmean 54.148546 -system.ruby.ST.miss_latency_hist_seqr::stdev 39.831747 -system.ruby.ST.miss_latency_hist_seqr | 38 55.88% 55.88% | 29 42.65% 98.53% | 0 0.00% 98.53% | 0 0.00% 98.53% | 0 0.00% 98.53% | 1 1.47% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.miss_latency_hist_seqr::mean 59.235294 +system.ruby.ST.miss_latency_hist_seqr::gmean 54.692111 +system.ruby.ST.miss_latency_hist_seqr::stdev 22.140068 +system.ruby.ST.miss_latency_hist_seqr | 0 0.00% 0.00% | 4 5.88% 5.88% | 33 48.53% 54.41% | 1 1.47% 55.88% | 14 20.59% 76.47% | 14 20.59% 97.06% | 2 2.94% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ST.miss_latency_hist_seqr::total 68 system.ruby.IFETCH.latency_hist_seqr::bucket_size 64 system.ruby.IFETCH.latency_hist_seqr::max_bucket 639 system.ruby.IFETCH.latency_hist_seqr::samples 2585 -system.ruby.IFETCH.latency_hist_seqr::mean 9.701354 -system.ruby.IFETCH.latency_hist_seqr::gmean 1.644214 -system.ruby.IFETCH.latency_hist_seqr::stdev 25.994801 -system.ruby.IFETCH.latency_hist_seqr | 2294 88.74% 88.74% | 287 11.10% 99.85% | 1 0.04% 99.88% | 0 0.00% 99.88% | 0 0.00% 99.88% | 3 0.12% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.latency_hist_seqr::mean 10.473501 +system.ruby.IFETCH.latency_hist_seqr::gmean 1.659469 +system.ruby.IFETCH.latency_hist_seqr::stdev 28.438724 +system.ruby.IFETCH.latency_hist_seqr | 2294 88.74% 88.74% | 286 11.06% 99.81% | 1 0.04% 99.85% | 0 0.00% 99.85% | 2 0.08% 99.92% | 2 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.latency_hist_seqr::total 2585 system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 1 system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 9 @@ -661,10 +671,10 @@ system.ruby.IFETCH.hit_latency_hist_seqr::total 2285 system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 64 system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 639 system.ruby.IFETCH.miss_latency_hist_seqr::samples 300 -system.ruby.IFETCH.miss_latency_hist_seqr::mean 75.976667 -system.ruby.IFETCH.miss_latency_hist_seqr::gmean 72.583942 -system.ruby.IFETCH.miss_latency_hist_seqr::stdev 29.223784 -system.ruby.IFETCH.miss_latency_hist_seqr | 9 3.00% 3.00% | 287 95.67% 98.67% | 1 0.33% 99.00% | 0 0.00% 99.00% | 0 0.00% 99.00% | 3 1.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.miss_latency_hist_seqr::mean 82.630000 +system.ruby.IFETCH.miss_latency_hist_seqr::gmean 78.596235 +system.ruby.IFETCH.miss_latency_hist_seqr::stdev 32.857141 +system.ruby.IFETCH.miss_latency_hist_seqr | 9 3.00% 3.00% | 286 95.33% 98.33% | 1 0.33% 98.67% | 0 0.00% 98.67% | 2 0.67% 99.33% | 2 0.67% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.miss_latency_hist_seqr::total 300 system.ruby.Directory_Controller.Fetch 547 0.00% 0.00% system.ruby.Directory_Controller.Data 103 0.00% 0.00% diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini index 2ad2eb8ea..70212c16a 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini @@ -14,6 +14,7 @@ children=clk_domain cpu dvfs_handler mem_ctrls ruby sys_port_proxy voltage_domai boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 exit_on_work_items=false init_param=0 @@ -22,11 +23,15 @@ kernel_addr_check=true load_addr_mask=1099511627775 load_offset=0 mem_mode=timing -mem_ranges=0:268435455 +mem_ranges=0:268435455:0:0:0:0 memories=system.mem_ctrls mmap_using_noreserve=false multi_thread=false num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null readfile= symbolfile= thermal_components= @@ -55,6 +60,7 @@ branchPred=Null checker=Null clk_domain=system.cpu.clk_domain cpu_id=0 +default_p_state=UNDEFINED do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true @@ -70,6 +76,10 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null profile=0 progress_interval=0 simpoint_start_insts= @@ -122,7 +132,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello +executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/alpha/tru64/hello gid=100 input=cin kvmInSE=false @@ -145,27 +155,27 @@ transition_latency=100000 [system.mem_ctrls] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -177,6 +187,7 @@ burst_length=8 channels=1 clk_domain=system.clk_domain conf_table_reported=true +default_p_state=UNDEFINED device_bus_width=8 device_rowbuffer_size=1024 device_size=536870912 @@ -184,12 +195,17 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 page_policy=open_adaptive -range=0:268435455 +power_model=Null +range=0:268435455:5:19:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10 @@ -211,9 +227,9 @@ tRTW=3 tWR=15 tWTR=8 tXAW=30 -tXP=0 +tXP=6 tXPDLL=0 -tXS=0 +tXS=270 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 @@ -227,12 +243,17 @@ access_backing_store=false all_instructions=false block_size_bytes=64 clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED eventq_index=0 hot_lines=false memory_size_bits=48 num_of_sequencers=1 number_of_virtual_networks=3 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 phys_mem=Null +power_model=Null randomization=false [system.ruby.clk_domain] @@ -249,11 +270,16 @@ children=directory forwardFromDir requestToDir responseFromDir responseFromMemor buffer_size=0 clk_domain=system.ruby.clk_domain cluster_id=0 +default_p_state=UNDEFINED directory=system.ruby.dir_cntrl0.directory directory_latency=6 eventq_index=0 forwardFromDir=system.ruby.dir_cntrl0.forwardFromDir number_of_TBEs=256 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null recycle_latency=10 requestToDir=system.ruby.dir_cntrl0.requestToDir responseFromDir=system.ruby.dir_cntrl0.responseFromDir @@ -320,10 +346,15 @@ L1Icache=system.ruby.l1_cntrl0.L1Icache buffer_size=0 clk_domain=system.cpu.clk_domain cluster_id=0 +default_p_state=UNDEFINED eventq_index=0 l2_select_num_bits=0 mandatoryQueue=system.ruby.l1_cntrl0.mandatoryQueue number_of_TBEs=256 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null recycle_latency=10 requestFromL1Cache=system.ruby.l1_cntrl0.requestFromL1Cache requestToL1Cache=system.ruby.l1_cntrl0.requestToL1Cache @@ -433,17 +464,22 @@ coreid=99 dcache=system.ruby.l1_cntrl0.L1Dcache dcache_hit_latency=1 deadlock_threshold=500000 +default_p_state=UNDEFINED eventq_index=0 +garnet_standalone=false icache=system.ruby.l1_cntrl0.L1Icache icache_hit_latency=1 is_cpu_sequencer=true max_outstanding_requests=16 no_retry_on_stall=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null ruby_system=system.ruby support_data_reqs=true support_inst_reqs=true system=system -using_network_tester=false using_ruby_tester=false version=0 slave=system.cpu.icache_port system.cpu.dcache_port @@ -466,8 +502,13 @@ L2cache=system.ruby.l2_cntrl0.L2cache buffer_size=0 clk_domain=system.ruby.clk_domain cluster_id=0 +default_p_state=UNDEFINED eventq_index=0 number_of_TBEs=256 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null recycle_latency=10 request_latency=2 responseFromL2Cache=system.ruby.l2_cntrl0.responseFromL2Cache @@ -566,18 +607,23 @@ eventq_index=0 [system.ruby.network] type=SimpleNetwork -children=ext_links0 ext_links1 ext_links2 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_links0 int_links1 int_links2 routers0 routers1 routers2 routers3 +children=ext_links0 ext_links1 ext_links2 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_link_buffers20 int_link_buffers21 int_link_buffers22 int_link_buffers23 int_link_buffers24 int_link_buffers25 int_link_buffers26 int_link_buffers27 int_link_buffers28 int_link_buffers29 int_link_buffers30 int_link_buffers31 int_link_buffers32 int_link_buffers33 int_link_buffers34 int_link_buffers35 int_links0 int_links1 int_links2 int_links3 int_links4 int_links5 routers0 routers1 routers2 routers3 adaptive_routing=false buffer_size=0 clk_domain=system.ruby.clk_domain control_msg_size=8 +default_p_state=UNDEFINED endpoint_bandwidth=1000 eventq_index=0 ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1 system.ruby.network.ext_links2 -int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 -int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2 +int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19 system.ruby.network.int_link_buffers20 system.ruby.network.int_link_buffers21 system.ruby.network.int_link_buffers22 system.ruby.network.int_link_buffers23 system.ruby.network.int_link_buffers24 system.ruby.network.int_link_buffers25 system.ruby.network.int_link_buffers26 system.ruby.network.int_link_buffers27 system.ruby.network.int_link_buffers28 system.ruby.network.int_link_buffers29 system.ruby.network.int_link_buffers30 system.ruby.network.int_link_buffers31 system.ruby.network.int_link_buffers32 system.ruby.network.int_link_buffers33 system.ruby.network.int_link_buffers34 system.ruby.network.int_link_buffers35 +int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2 system.ruby.network.int_links3 system.ruby.network.int_links4 system.ruby.network.int_links5 netifs= number_of_virtual_networks=3 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null routers=system.ruby.network.routers0 system.ruby.network.routers1 system.ruby.network.routers2 system.ruby.network.routers3 ruby_system=system.ruby topology=Crossbar @@ -740,42 +786,216 @@ eventq_index=0 ordered=true randomization=false +[system.ruby.network.int_link_buffers18] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers19] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers20] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers21] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers22] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers23] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers24] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers25] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers26] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers27] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers28] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers29] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers30] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers31] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers32] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers33] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers34] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers35] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + [system.ruby.network.int_links0] type=SimpleIntLink bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers3 eventq_index=0 latency=1 link_id=3 -node_a=system.ruby.network.routers0 -node_b=system.ruby.network.routers3 +src_node=system.ruby.network.routers0 +src_outport= weight=1 [system.ruby.network.int_links1] type=SimpleIntLink bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers3 eventq_index=0 latency=1 link_id=4 -node_a=system.ruby.network.routers1 -node_b=system.ruby.network.routers3 +src_node=system.ruby.network.routers1 +src_outport= weight=1 [system.ruby.network.int_links2] type=SimpleIntLink bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers3 eventq_index=0 latency=1 link_id=5 -node_a=system.ruby.network.routers2 -node_b=system.ruby.network.routers3 +src_node=system.ruby.network.routers2 +src_outport= +weight=1 + +[system.ruby.network.int_links3] +type=SimpleIntLink +bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers0 +eventq_index=0 +latency=1 +link_id=6 +src_node=system.ruby.network.routers3 +src_outport= +weight=1 + +[system.ruby.network.int_links4] +type=SimpleIntLink +bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers1 +eventq_index=0 +latency=1 +link_id=7 +src_node=system.ruby.network.routers3 +src_outport= +weight=1 + +[system.ruby.network.int_links5] +type=SimpleIntLink +bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers2 +eventq_index=0 +latency=1 +link_id=8 +src_node=system.ruby.network.routers3 +src_outport= weight=1 [system.ruby.network.routers0] type=Switch children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED eventq_index=0 +latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 port_buffers=system.ruby.network.routers0.port_buffers00 system.ruby.network.routers0.port_buffers01 system.ruby.network.routers0.port_buffers02 system.ruby.network.routers0.port_buffers03 system.ruby.network.routers0.port_buffers04 system.ruby.network.routers0.port_buffers05 system.ruby.network.routers0.port_buffers06 system.ruby.network.routers0.port_buffers07 system.ruby.network.routers0.port_buffers08 system.ruby.network.routers0.port_buffers09 system.ruby.network.routers0.port_buffers10 system.ruby.network.routers0.port_buffers11 +power_model=Null router_id=0 virt_nets=3 @@ -867,8 +1087,14 @@ randomization=false type=Switch children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED eventq_index=0 +latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 port_buffers=system.ruby.network.routers1.port_buffers00 system.ruby.network.routers1.port_buffers01 system.ruby.network.routers1.port_buffers02 system.ruby.network.routers1.port_buffers03 system.ruby.network.routers1.port_buffers04 system.ruby.network.routers1.port_buffers05 system.ruby.network.routers1.port_buffers06 system.ruby.network.routers1.port_buffers07 system.ruby.network.routers1.port_buffers08 system.ruby.network.routers1.port_buffers09 system.ruby.network.routers1.port_buffers10 system.ruby.network.routers1.port_buffers11 +power_model=Null router_id=1 virt_nets=3 @@ -960,8 +1186,14 @@ randomization=false type=Switch children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED eventq_index=0 +latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 port_buffers=system.ruby.network.routers2.port_buffers00 system.ruby.network.routers2.port_buffers01 system.ruby.network.routers2.port_buffers02 system.ruby.network.routers2.port_buffers03 system.ruby.network.routers2.port_buffers04 system.ruby.network.routers2.port_buffers05 system.ruby.network.routers2.port_buffers06 system.ruby.network.routers2.port_buffers07 system.ruby.network.routers2.port_buffers08 system.ruby.network.routers2.port_buffers09 system.ruby.network.routers2.port_buffers10 system.ruby.network.routers2.port_buffers11 +power_model=Null router_id=2 virt_nets=3 @@ -1053,8 +1285,14 @@ randomization=false type=Switch children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17 clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED eventq_index=0 +latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 port_buffers=system.ruby.network.routers3.port_buffers00 system.ruby.network.routers3.port_buffers01 system.ruby.network.routers3.port_buffers02 system.ruby.network.routers3.port_buffers03 system.ruby.network.routers3.port_buffers04 system.ruby.network.routers3.port_buffers05 system.ruby.network.routers3.port_buffers06 system.ruby.network.routers3.port_buffers07 system.ruby.network.routers3.port_buffers08 system.ruby.network.routers3.port_buffers09 system.ruby.network.routers3.port_buffers10 system.ruby.network.routers3.port_buffers11 system.ruby.network.routers3.port_buffers12 system.ruby.network.routers3.port_buffers13 system.ruby.network.routers3.port_buffers14 system.ruby.network.routers3.port_buffers15 system.ruby.network.routers3.port_buffers16 system.ruby.network.routers3.port_buffers17 +power_model=Null router_id=3 virt_nets=3 @@ -1187,9 +1425,14 @@ randomization=false [system.sys_port_proxy] type=RubyPortProxy clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 is_cpu_sequencer=true no_retry_on_stall=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null ruby_system=system.ruby support_data_reqs=true support_inst_reqs=true diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simerr b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simerr index 1c18978fa..63982fce4 100755 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simerr +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simerr @@ -4,9 +4,8 @@ warn: rounding error > tolerance 1.250000 rounded to 1 warn: rounding error > tolerance 1.250000 rounded to 1 -warn: rounding error > tolerance - 1.250000 rounded to 1 warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes) warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files! warn: ignoring syscall sigprocmask(1, ...) diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout index 28c1f1cb8..42fdb4cc6 100755 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout @@ -1,13 +1,15 @@ +Redirecting stdout to build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout +Redirecting stderr to build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 21 2016 14:06:59 -gem5 started Jan 21 2016 14:07:35 -gem5 executing on zizzer, pid 50069 -command line: build/ALPHA_MOESI_CMP_directory/gem5.opt -d build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory +gem5 compiled Oct 13 2016 20:30:58 +gem5 started Oct 13 2016 20:31:25 +gem5 executing on e108600-lin, pid 17791 +command line: /work/curdun01/gem5-external.hg/build/ALPHA_MOESI_CMP_directory/gem5.opt -d build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 41712 because target called exit() +Exiting @ tick 44230 because target called exit() diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt index 1d68008a1..9bed4b569 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000042 # Number of seconds simulated -sim_ticks 41712 # Number of ticks simulated -final_tick 41712 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000044 # Number of seconds simulated +sim_ticks 44230 # Number of ticks simulated +final_tick 44230 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 62826 # Simulator instruction rate (inst/s) -host_op_rate 62813 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1016484 # Simulator tick rate (ticks/s) -host_mem_usage 457644 # Number of bytes of host memory used -host_seconds 0.04 # Real time elapsed on the host +host_inst_rate 44627 # Simulator instruction rate (inst/s) +host_op_rate 44610 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 765394 # Simulator tick rate (ticks/s) +host_mem_usage 414624 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks -system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 41712 # Cumulative time (in ticks) in various power states +system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 44230 # Cumulative time (in ticks) in various power states system.mem_ctrls.bytes_read::ruby.dir_cntrl0 29696 # Number of bytes read from this memory system.mem_ctrls.bytes_read::total 29696 # Number of bytes read from this memory system.mem_ctrls.bytes_written::ruby.dir_cntrl0 4992 # Number of bytes written to this memory @@ -22,12 +22,12 @@ system.mem_ctrls.num_reads::ruby.dir_cntrl0 464 # system.mem_ctrls.num_reads::total 464 # Number of read requests responded to by this memory system.mem_ctrls.num_writes::ruby.dir_cntrl0 78 # Number of write requests responded to by this memory system.mem_ctrls.num_writes::total 78 # Number of write requests responded to by this memory -system.mem_ctrls.bw_read::ruby.dir_cntrl0 711929421 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_read::total 711929421 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::ruby.dir_cntrl0 119677791 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::total 119677791 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_total::ruby.dir_cntrl0 831607211 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.bw_total::total 831607211 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_read::ruby.dir_cntrl0 671399503 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 671399503 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::ruby.dir_cntrl0 112864572 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::total 112864572 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::ruby.dir_cntrl0 784264074 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 784264074 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrls.readReqs 464 # Number of read requests accepted system.mem_ctrls.writeReqs 78 # Number of write requests accepted system.mem_ctrls.readBursts 464 # Number of DRAM read bursts, including those serviced by the write queue @@ -74,7 +74,7 @@ system.mem_ctrls.perBankWrBursts::14 0 # Pe system.mem_ctrls.perBankWrBursts::15 1 # Per bank write bursts system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrls.totGap 41632 # Total gap between requests +system.mem_ctrls.totGap 44144 # Total gap between requests system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) @@ -185,20 +185,20 @@ system.mem_ctrls.wrQLenPdf::60 0 # Wh system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrls.bytesPerActivate::samples 72 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::mean 336 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::gmean 226.772547 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::stdev 284.954160 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::0-127 17 23.61% 23.61% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::128-255 17 23.61% 47.22% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::256-383 12 16.67% 63.89% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::384-511 5 6.94% 70.83% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::512-639 7 9.72% 80.56% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::640-767 6 8.33% 88.89% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::768-895 2 2.78% 91.67% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::896-1023 3 4.17% 95.83% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::1024-1151 3 4.17% 100.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::total 72 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::samples 75 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 308.906667 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 203.362375 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 281.413861 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 21 28.00% 28.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 20 26.67% 54.67% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 8 10.67% 65.33% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 8 10.67% 76.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 6 8.00% 84.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 3 4.00% 88.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 4 5.33% 93.33% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 1 1.33% 94.67% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 4 5.33% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 75 # Bytes accessed per row activation system.mem_ctrls.rdPerTurnAround::samples 1 # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::mean 248 # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::gmean 248.000000 # Reads before turning the bus around for writes @@ -211,57 +211,67 @@ system.mem_ctrls.wrPerTurnAround::gmean 16.000000 # Wr system.mem_ctrls.wrPerTurnAround::stdev nan # Writes before turning the bus around for reads system.mem_ctrls.wrPerTurnAround::16 1 100.00% 100.00% # Writes before turning the bus around for reads system.mem_ctrls.wrPerTurnAround::total 1 # Writes before turning the bus around for reads -system.mem_ctrls.totQLat 2393 # Total ticks spent queuing -system.mem_ctrls.totMemAccLat 9689 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.totQLat 4911 # Total ticks spent queuing +system.mem_ctrls.totMemAccLat 12207 # Total ticks spent from burst creation until serviced by the DRAM system.mem_ctrls.totBusLat 1920 # Total ticks spent in databus transfers -system.mem_ctrls.avgQLat 6.23 # Average queueing delay per DRAM burst +system.mem_ctrls.avgQLat 12.79 # Average queueing delay per DRAM burst system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst -system.mem_ctrls.avgMemAccLat 25.23 # Average memory access latency per DRAM burst -system.mem_ctrls.avgRdBW 589.18 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrls.avgWrBW 24.55 # Average achieved write bandwidth in MiByte/s -system.mem_ctrls.avgRdBWSys 711.93 # Average system read bandwidth in MiByte/s -system.mem_ctrls.avgWrBWSys 119.68 # Average system write bandwidth in MiByte/s +system.mem_ctrls.avgMemAccLat 31.79 # Average memory access latency per DRAM burst +system.mem_ctrls.avgRdBW 555.64 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 23.15 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 671.40 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 112.86 # Average system write bandwidth in MiByte/s system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrls.busUtil 4.79 # Data bus utilization in percentage -system.mem_ctrls.busUtilRead 4.60 # Data bus utilization in percentage for reads -system.mem_ctrls.busUtilWrite 0.19 # Data bus utilization in percentage for writes +system.mem_ctrls.busUtil 4.52 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 4.34 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 0.18 # Data bus utilization in percentage for writes system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing -system.mem_ctrls.avgWrQLen 21.63 # Average write queue length when enqueuing -system.mem_ctrls.readRowHits 305 # Number of row buffer hits during reads +system.mem_ctrls.avgWrQLen 21.61 # Average write queue length when enqueuing +system.mem_ctrls.readRowHits 302 # Number of row buffer hits during reads system.mem_ctrls.writeRowHits 15 # Number of row buffer hits during writes -system.mem_ctrls.readRowHitRate 79.43 # Row buffer hit rate for reads +system.mem_ctrls.readRowHitRate 78.65 # Row buffer hit rate for reads system.mem_ctrls.writeRowHitRate 32.61 # Row buffer hit rate for writes -system.mem_ctrls.avgGap 76.81 # Average gap between requests -system.mem_ctrls.pageHitRate 74.42 # Row buffer hit rate, read and write combined -system.mem_ctrls_0.actEnergy 158760 # Energy for activate commands per rank (pJ) -system.mem_ctrls_0.preEnergy 88200 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_0.readEnergy 1809600 # Energy for read commands per rank (pJ) +system.mem_ctrls.avgGap 81.45 # Average gap between requests +system.mem_ctrls.pageHitRate 73.72 # Row buffer hit rate, read and write combined +system.mem_ctrls_0.actEnergy 178500 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 81144 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 1793568 # Energy for read commands per rank (pJ) system.mem_ctrls_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.mem_ctrls_0.refreshEnergy 2542800 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_0.actBackEnergy 24398280 # Energy for active background per rank (pJ) -system.mem_ctrls_0.preBackEnergy 2114400 # Energy for precharge background per rank (pJ) -system.mem_ctrls_0.totalEnergy 31112040 # Total energy per rank (pJ) -system.mem_ctrls_0.averagePower 793.795989 # Core power per rank (mW) -system.mem_ctrls_0.memoryStateTime::IDLE 3488 # Time in different power states +system.mem_ctrls_0.refreshEnergy 3073200.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 2736456 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 72192 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.actPowerDownEnergy 16199400 # Energy for active power-down per rank (pJ) +system.mem_ctrls_0.prePowerDownEnergy 966144 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls_0.totalEnergy 25100604 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 567.501786 # Core power per rank (mW) +system.mem_ctrls_0.totalIdleTime 37998 # Total Idle time Per DRAM Rank +system.mem_ctrls_0.memoryStateTime::IDLE 48 # Time in different power states system.mem_ctrls_0.memoryStateTime::REF 1300 # Time in different power states -system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT 34510 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrls_1.actEnergy 385560 # Energy for activate commands per rank (pJ) -system.mem_ctrls_1.preEnergy 214200 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_1.readEnergy 2708160 # Energy for read commands per rank (pJ) -system.mem_ctrls_1.writeEnergy 165888 # Energy for write commands per rank (pJ) -system.mem_ctrls_1.refreshEnergy 2542800 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_1.actBackEnergy 26293644 # Energy for active background per rank (pJ) -system.mem_ctrls_1.preBackEnergy 449400 # Energy for precharge background per rank (pJ) -system.mem_ctrls_1.totalEnergy 32759652 # Total energy per rank (pJ) -system.mem_ctrls_1.averagePower 835.918653 # Core power per rank (mW) -system.mem_ctrls_1.memoryStateTime::IDLE 623 # Time in different power states +system.mem_ctrls_0.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls_0.memoryStateTime::PRE_PDN 2516 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 4841 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT_PDN 35525 # Time in different power states +system.mem_ctrls_1.actEnergy 414120 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 208656 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 2593248 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 133632 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.refreshEnergy 3073200.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 3830856 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 258048 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.actPowerDownEnergy 15964560 # Energy for active power-down per rank (pJ) +system.mem_ctrls_1.prePowerDownEnergy 56448 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls_1.totalEnergy 26532768 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 599.881709 # Core power per rank (mW) +system.mem_ctrls_1.totalIdleTime 34371 # Total Idle time Per DRAM Rank +system.mem_ctrls_1.memoryStateTime::IDLE 532 # Time in different power states system.mem_ctrls_1.memoryStateTime::REF 1300 # Time in different power states -system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT 37281 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 41712 # Cumulative time (in ticks) in various power states +system.mem_ctrls_1.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls_1.memoryStateTime::PRE_PDN 147 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 7241 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT_PDN 35010 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 44230 # Cumulative time (in ticks) in various power states system.cpu.clk_domain.clock 1 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -296,8 +306,8 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 41712 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 41712 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 44230 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 44230 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 2577 # Number of instructions committed @@ -316,7 +326,7 @@ system.cpu.num_mem_refs 717 # nu system.cpu.num_load_insts 419 # Number of load instructions system.cpu.num_store_insts 298 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 41712 # Number of busy cycles +system.cpu.num_busy_cycles 44230 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 396 # Number of branches fetched @@ -356,7 +366,7 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 2585 # Class of executed instruction system.ruby.clk_domain.clock 1 # Clock period in ticks -system.ruby.pwrStateResidencyTicks::UNDEFINED 41712 # Cumulative time (in ticks) in various power states +system.ruby.pwrStateResidencyTicks::UNDEFINED 44230 # Cumulative time (in ticks) in various power states system.ruby.outstanding_req_hist_seqr::bucket_size 1 system.ruby.outstanding_req_hist_seqr::max_bucket 9 system.ruby.outstanding_req_hist_seqr::samples 3295 @@ -364,13 +374,13 @@ system.ruby.outstanding_req_hist_seqr::mean 1 system.ruby.outstanding_req_hist_seqr::gmean 1 system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 3295 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.outstanding_req_hist_seqr::total 3295 -system.ruby.latency_hist_seqr::bucket_size 32 -system.ruby.latency_hist_seqr::max_bucket 319 +system.ruby.latency_hist_seqr::bucket_size 64 +system.ruby.latency_hist_seqr::max_bucket 639 system.ruby.latency_hist_seqr::samples 3294 -system.ruby.latency_hist_seqr::mean 11.663024 -system.ruby.latency_hist_seqr::gmean 1.954156 -system.ruby.latency_hist_seqr::stdev 27.142816 -system.ruby.latency_hist_seqr | 2830 85.91% 85.91% | 80 2.43% 88.34% | 359 10.90% 99.24% | 18 0.55% 99.79% | 2 0.06% 99.85% | 0 0.00% 99.85% | 1 0.03% 99.88% | 0 0.00% 99.88% | 1 0.03% 99.91% | 3 0.09% 100.00% +system.ruby.latency_hist_seqr::mean 12.427444 +system.ruby.latency_hist_seqr::gmean 1.971908 +system.ruby.latency_hist_seqr::stdev 29.452789 +system.ruby.latency_hist_seqr | 2910 88.34% 88.34% | 377 11.45% 99.79% | 2 0.06% 99.85% | 0 0.00% 99.85% | 3 0.09% 99.94% | 2 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.latency_hist_seqr::total 3294 system.ruby.hit_latency_hist_seqr::bucket_size 1 system.ruby.hit_latency_hist_seqr::max_bucket 9 @@ -379,30 +389,30 @@ system.ruby.hit_latency_hist_seqr::mean 1 system.ruby.hit_latency_hist_seqr::gmean 1 system.ruby.hit_latency_hist_seqr | 0 0.00% 0.00% | 2750 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.hit_latency_hist_seqr::total 2750 -system.ruby.miss_latency_hist_seqr::bucket_size 32 -system.ruby.miss_latency_hist_seqr::max_bucket 319 +system.ruby.miss_latency_hist_seqr::bucket_size 64 +system.ruby.miss_latency_hist_seqr::max_bucket 639 system.ruby.miss_latency_hist_seqr::samples 544 -system.ruby.miss_latency_hist_seqr::mean 65.566176 -system.ruby.miss_latency_hist_seqr::gmean 57.783054 -system.ruby.miss_latency_hist_seqr::stdev 31.323348 -system.ruby.miss_latency_hist_seqr | 80 14.71% 14.71% | 80 14.71% 29.41% | 359 65.99% 95.40% | 18 3.31% 98.71% | 2 0.37% 99.08% | 0 0.00% 99.08% | 1 0.18% 99.26% | 0 0.00% 99.26% | 1 0.18% 99.45% | 3 0.55% 100.00% +system.ruby.miss_latency_hist_seqr::mean 70.194853 +system.ruby.miss_latency_hist_seqr::gmean 61.035379 +system.ruby.miss_latency_hist_seqr::stdev 35.442152 +system.ruby.miss_latency_hist_seqr | 160 29.41% 29.41% | 377 69.30% 98.71% | 2 0.37% 99.08% | 0 0.00% 99.08% | 3 0.55% 99.63% | 2 0.37% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.miss_latency_hist_seqr::total 544 -system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 41712 # Cumulative time (in ticks) in various power states +system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 44230 # Cumulative time (in ticks) in various power states system.ruby.l1_cntrl0.L1Dcache.demand_hits 435 # Number of cache demand hits system.ruby.l1_cntrl0.L1Dcache.demand_misses 274 # Number of cache demand misses system.ruby.l1_cntrl0.L1Dcache.demand_accesses 709 # Number of cache demand accesses system.ruby.l1_cntrl0.L1Icache.demand_hits 2315 # Number of cache demand hits system.ruby.l1_cntrl0.L1Icache.demand_misses 270 # Number of cache demand misses system.ruby.l1_cntrl0.L1Icache.demand_accesses 2585 # Number of cache demand accesses -system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 41712 # Cumulative time (in ticks) in various power states -system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 41712 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 44230 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 44230 # Cumulative time (in ticks) in various power states system.ruby.l2_cntrl0.L2cache.demand_hits 80 # Number of cache demand hits system.ruby.l2_cntrl0.L2cache.demand_misses 464 # Number of cache demand misses system.ruby.l2_cntrl0.L2cache.demand_accesses 544 # Number of cache demand accesses -system.ruby.l2_cntrl0.pwrStateResidencyTicks::UNDEFINED 41712 # Cumulative time (in ticks) in various power states +system.ruby.l2_cntrl0.pwrStateResidencyTicks::UNDEFINED 44230 # Cumulative time (in ticks) in various power states system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 41712 # Cumulative time (in ticks) in various power states -system.ruby.network.routers0.percent_links_utilized 6.800201 +system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 44230 # Cumulative time (in ticks) in various power states +system.ruby.network.routers0.percent_links_utilized 6.413068 system.ruby.network.routers0.msg_count.Request_Control::0 544 system.ruby.network.routers0.msg_count.Response_Data::2 464 system.ruby.network.routers0.msg_count.ResponseL2hit_Data::2 80 @@ -415,8 +425,8 @@ system.ruby.network.routers0.msg_bytes.ResponseL2hit_Data::2 5760 system.ruby.network.routers0.msg_bytes.Writeback_Data::2 34704 system.ruby.network.routers0.msg_bytes.Writeback_Control::0 8032 system.ruby.network.routers0.msg_bytes.Unblock_Control::2 4512 -system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 41712 # Cumulative time (in ticks) in various power states -system.ruby.network.routers1.percent_links_utilized 10.372914 +system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 44230 # Cumulative time (in ticks) in various power states +system.ruby.network.routers1.percent_links_utilized 9.782388 system.ruby.network.routers1.msg_count.Request_Control::0 544 system.ruby.network.routers1.msg_count.Request_Control::1 464 system.ruby.network.routers1.msg_count.Response_Data::2 928 @@ -433,8 +443,8 @@ system.ruby.network.routers1.msg_bytes.Writeback_Data::2 40320 system.ruby.network.routers1.msg_bytes.Writeback_Control::0 8032 system.ruby.network.routers1.msg_bytes.Writeback_Control::1 1248 system.ruby.network.routers1.msg_bytes.Unblock_Control::2 8216 -system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 41712 # Cumulative time (in ticks) in various power states -system.ruby.network.routers2.percent_links_utilized 3.572713 +system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 44230 # Cumulative time (in ticks) in various power states +system.ruby.network.routers2.percent_links_utilized 3.369319 system.ruby.network.routers2.msg_count.Request_Control::1 464 system.ruby.network.routers2.msg_count.Response_Data::2 464 system.ruby.network.routers2.msg_count.Writeback_Data::2 78 @@ -445,8 +455,8 @@ system.ruby.network.routers2.msg_bytes.Response_Data::2 33408 system.ruby.network.routers2.msg_bytes.Writeback_Data::2 5616 system.ruby.network.routers2.msg_bytes.Writeback_Control::1 1248 system.ruby.network.routers2.msg_bytes.Unblock_Control::2 3704 -system.ruby.network.routers3.pwrStateResidencyTicks::UNDEFINED 41712 # Cumulative time (in ticks) in various power states -system.ruby.network.routers3.percent_links_utilized 6.915276 +system.ruby.network.routers3.pwrStateResidencyTicks::UNDEFINED 44230 # Cumulative time (in ticks) in various power states +system.ruby.network.routers3.percent_links_utilized 6.521592 system.ruby.network.routers3.msg_count.Request_Control::0 544 system.ruby.network.routers3.msg_count.Request_Control::1 464 system.ruby.network.routers3.msg_count.Response_Data::2 928 @@ -463,7 +473,7 @@ system.ruby.network.routers3.msg_bytes.Writeback_Data::2 40320 system.ruby.network.routers3.msg_bytes.Writeback_Control::0 8032 system.ruby.network.routers3.msg_bytes.Writeback_Control::1 1248 system.ruby.network.routers3.msg_bytes.Unblock_Control::2 8216 -system.ruby.network.pwrStateResidencyTicks::UNDEFINED 41712 # Cumulative time (in ticks) in various power states +system.ruby.network.pwrStateResidencyTicks::UNDEFINED 44230 # Cumulative time (in ticks) in various power states system.ruby.network.msg_count.Request_Control 3024 system.ruby.network.msg_count.Response_Data 2784 system.ruby.network.msg_count.ResponseL2hit_Data 240 @@ -476,15 +486,15 @@ system.ruby.network.msg_byte.ResponseL2hit_Data 17280 system.ruby.network.msg_byte.Writeback_Data 120960 system.ruby.network.msg_byte.Writeback_Control 27840 system.ruby.network.msg_byte.Unblock_Control 24648 -system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 41712 # Cumulative time (in ticks) in various power states -system.ruby.network.routers0.throttle0.link_utilization 6.470560 +system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 44230 # Cumulative time (in ticks) in various power states +system.ruby.network.routers0.throttle0.link_utilization 6.102193 system.ruby.network.routers0.throttle0.msg_count.Response_Data::2 464 system.ruby.network.routers0.throttle0.msg_count.ResponseL2hit_Data::2 80 system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::0 502 system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::2 33408 system.ruby.network.routers0.throttle0.msg_bytes.ResponseL2hit_Data::2 5760 system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::0 4016 -system.ruby.network.routers0.throttle1.link_utilization 7.129843 +system.ruby.network.routers0.throttle1.link_utilization 6.723943 system.ruby.network.routers0.throttle1.msg_count.Request_Control::0 544 system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::2 482 system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::0 502 @@ -493,7 +503,7 @@ system.ruby.network.routers0.throttle1.msg_bytes.Request_Control::0 4352 system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::2 34704 system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::0 4016 system.ruby.network.routers0.throttle1.msg_bytes.Unblock_Control::2 4512 -system.ruby.network.routers1.throttle0.link_utilization 12.229095 +system.ruby.network.routers1.throttle0.link_utilization 11.532896 system.ruby.network.routers1.throttle0.msg_count.Request_Control::0 544 system.ruby.network.routers1.throttle0.msg_count.Response_Data::2 464 system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::2 482 @@ -506,7 +516,7 @@ system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::2 34704 system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::0 4016 system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::1 624 system.ruby.network.routers1.throttle0.msg_bytes.Unblock_Control::2 4512 -system.ruby.network.routers1.throttle1.link_utilization 8.516734 +system.ruby.network.routers1.throttle1.link_utilization 8.031879 system.ruby.network.routers1.throttle1.msg_count.Request_Control::1 464 system.ruby.network.routers1.throttle1.msg_count.Response_Data::2 464 system.ruby.network.routers1.throttle1.msg_count.ResponseL2hit_Data::2 80 @@ -521,7 +531,7 @@ system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Data::2 5616 system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::0 4016 system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::1 624 system.ruby.network.routers1.throttle1.msg_bytes.Unblock_Control::2 3704 -system.ruby.network.routers2.throttle0.link_utilization 2.046174 +system.ruby.network.routers2.throttle0.link_utilization 1.929686 system.ruby.network.routers2.throttle0.msg_count.Request_Control::1 464 system.ruby.network.routers2.throttle0.msg_count.Writeback_Data::2 78 system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::1 78 @@ -530,19 +540,19 @@ system.ruby.network.routers2.throttle0.msg_bytes.Request_Control::1 3712 system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Data::2 5616 system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::1 624 system.ruby.network.routers2.throttle0.msg_bytes.Unblock_Control::2 3704 -system.ruby.network.routers2.throttle1.link_utilization 5.099252 +system.ruby.network.routers2.throttle1.link_utilization 4.808953 system.ruby.network.routers2.throttle1.msg_count.Response_Data::2 464 system.ruby.network.routers2.throttle1.msg_count.Writeback_Control::1 78 system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::2 33408 system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Control::1 624 -system.ruby.network.routers3.throttle0.link_utilization 6.470560 +system.ruby.network.routers3.throttle0.link_utilization 6.102193 system.ruby.network.routers3.throttle0.msg_count.Response_Data::2 464 system.ruby.network.routers3.throttle0.msg_count.ResponseL2hit_Data::2 80 system.ruby.network.routers3.throttle0.msg_count.Writeback_Control::0 502 system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::2 33408 system.ruby.network.routers3.throttle0.msg_bytes.ResponseL2hit_Data::2 5760 system.ruby.network.routers3.throttle0.msg_bytes.Writeback_Control::0 4016 -system.ruby.network.routers3.throttle1.link_utilization 12.229095 +system.ruby.network.routers3.throttle1.link_utilization 11.532896 system.ruby.network.routers3.throttle1.msg_count.Request_Control::0 544 system.ruby.network.routers3.throttle1.msg_count.Response_Data::2 464 system.ruby.network.routers3.throttle1.msg_count.Writeback_Data::2 482 @@ -555,7 +565,7 @@ system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::2 34704 system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::0 4016 system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::1 624 system.ruby.network.routers3.throttle1.msg_bytes.Unblock_Control::2 4512 -system.ruby.network.routers3.throttle2.link_utilization 2.046174 +system.ruby.network.routers3.throttle2.link_utilization 1.929686 system.ruby.network.routers3.throttle2.msg_count.Request_Control::1 464 system.ruby.network.routers3.throttle2.msg_count.Writeback_Data::2 78 system.ruby.network.routers3.throttle2.msg_count.Writeback_Control::1 78 @@ -564,13 +574,13 @@ system.ruby.network.routers3.throttle2.msg_bytes.Request_Control::1 3712 system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Data::2 5616 system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Control::1 624 system.ruby.network.routers3.throttle2.msg_bytes.Unblock_Control::2 3704 -system.ruby.LD.latency_hist_seqr::bucket_size 32 -system.ruby.LD.latency_hist_seqr::max_bucket 319 +system.ruby.LD.latency_hist_seqr::bucket_size 64 +system.ruby.LD.latency_hist_seqr::max_bucket 639 system.ruby.LD.latency_hist_seqr::samples 415 -system.ruby.LD.latency_hist_seqr::mean 25.657831 -system.ruby.LD.latency_hist_seqr::gmean 5.487426 -system.ruby.LD.latency_hist_seqr::stdev 34.035908 -system.ruby.LD.latency_hist_seqr | 275 66.27% 66.27% | 45 10.84% 77.11% | 85 20.48% 97.59% | 8 1.93% 99.52% | 1 0.24% 99.76% | 0 0.00% 99.76% | 1 0.24% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.latency_hist_seqr::mean 27.790361 +system.ruby.LD.latency_hist_seqr::gmean 5.600782 +system.ruby.LD.latency_hist_seqr::stdev 40.269706 +system.ruby.LD.latency_hist_seqr | 320 77.11% 77.11% | 92 22.17% 99.28% | 1 0.24% 99.52% | 0 0.00% 99.52% | 1 0.24% 99.76% | 1 0.24% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.latency_hist_seqr::total 415 system.ruby.LD.hit_latency_hist_seqr::bucket_size 1 system.ruby.LD.hit_latency_hist_seqr::max_bucket 9 @@ -579,21 +589,21 @@ system.ruby.LD.hit_latency_hist_seqr::mean 1 system.ruby.LD.hit_latency_hist_seqr::gmean 1 system.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 233 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.hit_latency_hist_seqr::total 233 -system.ruby.LD.miss_latency_hist_seqr::bucket_size 32 -system.ruby.LD.miss_latency_hist_seqr::max_bucket 319 +system.ruby.LD.miss_latency_hist_seqr::bucket_size 64 +system.ruby.LD.miss_latency_hist_seqr::max_bucket 639 system.ruby.LD.miss_latency_hist_seqr::samples 182 -system.ruby.LD.miss_latency_hist_seqr::mean 57.225275 -system.ruby.LD.miss_latency_hist_seqr::gmean 48.520263 -system.ruby.LD.miss_latency_hist_seqr::stdev 29.410954 -system.ruby.LD.miss_latency_hist_seqr | 42 23.08% 23.08% | 45 24.73% 47.80% | 85 46.70% 94.51% | 8 4.40% 98.90% | 1 0.55% 99.45% | 0 0.00% 99.45% | 1 0.55% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.miss_latency_hist_seqr::mean 62.087912 +system.ruby.LD.miss_latency_hist_seqr::gmean 50.836003 +system.ruby.LD.miss_latency_hist_seqr::stdev 40.030554 +system.ruby.LD.miss_latency_hist_seqr | 87 47.80% 47.80% | 92 50.55% 98.35% | 1 0.55% 98.90% | 0 0.00% 98.90% | 1 0.55% 99.45% | 1 0.55% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.miss_latency_hist_seqr::total 182 system.ruby.ST.latency_hist_seqr::bucket_size 16 system.ruby.ST.latency_hist_seqr::max_bucket 159 system.ruby.ST.latency_hist_seqr::samples 294 -system.ruby.ST.latency_hist_seqr::mean 18.809524 -system.ruby.ST.latency_hist_seqr::gmean 3.456048 -system.ruby.ST.latency_hist_seqr::stdev 29.072895 -system.ruby.ST.latency_hist_seqr | 202 68.71% 68.71% | 12 4.08% 72.79% | 34 11.56% 84.35% | 1 0.34% 84.69% | 38 12.93% 97.62% | 6 2.04% 99.66% | 1 0.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.latency_hist_seqr::mean 19.755102 +system.ruby.ST.latency_hist_seqr::gmean 3.497030 +system.ruby.ST.latency_hist_seqr::stdev 31.010753 +system.ruby.ST.latency_hist_seqr | 202 68.71% 68.71% | 12 4.08% 72.79% | 34 11.56% 84.35% | 1 0.34% 84.69% | 0 0.00% 84.69% | 44 14.97% 99.66% | 1 0.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ST.latency_hist_seqr::total 294 system.ruby.ST.hit_latency_hist_seqr::bucket_size 1 system.ruby.ST.hit_latency_hist_seqr::max_bucket 9 @@ -605,18 +615,18 @@ system.ruby.ST.hit_latency_hist_seqr::total 202 system.ruby.ST.miss_latency_hist_seqr::bucket_size 16 system.ruby.ST.miss_latency_hist_seqr::max_bucket 159 system.ruby.ST.miss_latency_hist_seqr::samples 92 -system.ruby.ST.miss_latency_hist_seqr::mean 57.913043 -system.ruby.ST.miss_latency_hist_seqr::gmean 52.615480 -system.ruby.ST.miss_latency_hist_seqr::stdev 21.714254 -system.ruby.ST.miss_latency_hist_seqr | 0 0.00% 0.00% | 12 13.04% 13.04% | 34 36.96% 50.00% | 1 1.09% 51.09% | 38 41.30% 92.39% | 6 6.52% 98.91% | 1 1.09% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.miss_latency_hist_seqr::mean 60.934783 +system.ruby.ST.miss_latency_hist_seqr::gmean 54.635401 +system.ruby.ST.miss_latency_hist_seqr::stdev 24.518127 +system.ruby.ST.miss_latency_hist_seqr | 0 0.00% 0.00% | 12 13.04% 13.04% | 34 36.96% 50.00% | 1 1.09% 51.09% | 0 0.00% 51.09% | 44 47.83% 98.91% | 1 1.09% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ST.miss_latency_hist_seqr::total 92 -system.ruby.IFETCH.latency_hist_seqr::bucket_size 32 -system.ruby.IFETCH.latency_hist_seqr::max_bucket 319 +system.ruby.IFETCH.latency_hist_seqr::bucket_size 64 +system.ruby.IFETCH.latency_hist_seqr::max_bucket 639 system.ruby.IFETCH.latency_hist_seqr::samples 2585 -system.ruby.IFETCH.latency_hist_seqr::mean 8.603482 -system.ruby.IFETCH.latency_hist_seqr::gmean 1.551701 -system.ruby.IFETCH.latency_hist_seqr::stdev 24.714457 -system.ruby.IFETCH.latency_hist_seqr | 2341 90.56% 90.56% | 0 0.00% 90.56% | 230 8.90% 99.46% | 9 0.35% 99.81% | 1 0.04% 99.85% | 0 0.00% 99.85% | 0 0.00% 99.85% | 0 0.00% 99.85% | 1 0.04% 99.88% | 3 0.12% 100.00% +system.ruby.IFETCH.latency_hist_seqr::mean 9.127660 +system.ruby.IFETCH.latency_hist_seqr::gmean 1.562445 +system.ruby.IFETCH.latency_hist_seqr::stdev 26.109704 +system.ruby.IFETCH.latency_hist_seqr | 2341 90.56% 90.56% | 240 9.28% 99.85% | 1 0.04% 99.88% | 0 0.00% 99.88% | 2 0.08% 99.96% | 1 0.04% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.latency_hist_seqr::total 2585 system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 1 system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 9 @@ -625,13 +635,13 @@ system.ruby.IFETCH.hit_latency_hist_seqr::mean 1 system.ruby.IFETCH.hit_latency_hist_seqr::gmean 1 system.ruby.IFETCH.hit_latency_hist_seqr | 0 0.00% 0.00% | 2315 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.hit_latency_hist_seqr::total 2315 -system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 32 -system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 319 +system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 64 +system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 639 system.ruby.IFETCH.miss_latency_hist_seqr::samples 270 -system.ruby.IFETCH.miss_latency_hist_seqr::mean 73.796296 -system.ruby.IFETCH.miss_latency_hist_seqr::gmean 67.113694 -system.ruby.IFETCH.miss_latency_hist_seqr::stdev 33.225253 -system.ruby.IFETCH.miss_latency_hist_seqr | 26 9.63% 9.63% | 0 0.00% 9.63% | 230 85.19% 94.81% | 9 3.33% 98.15% | 1 0.37% 98.52% | 0 0.00% 98.52% | 0 0.00% 98.52% | 0 0.00% 98.52% | 1 0.37% 98.89% | 3 1.11% 100.00% +system.ruby.IFETCH.miss_latency_hist_seqr::mean 78.814815 +system.ruby.IFETCH.miss_latency_hist_seqr::gmean 71.697206 +system.ruby.IFETCH.miss_latency_hist_seqr::stdev 33.251813 +system.ruby.IFETCH.miss_latency_hist_seqr | 26 9.63% 9.63% | 240 88.89% 98.52% | 1 0.37% 98.89% | 0 0.00% 98.89% | 2 0.74% 99.63% | 1 0.37% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.miss_latency_hist_seqr::total 270 system.ruby.Directory_Controller.GETX 80 0.00% 0.00% system.ruby.Directory_Controller.GETS 384 0.00% 0.00% diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini index c78531ccf..cf25b799b 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini @@ -14,6 +14,7 @@ children=clk_domain cpu dvfs_handler mem_ctrls ruby sys_port_proxy voltage_domai boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 exit_on_work_items=false init_param=0 @@ -22,11 +23,15 @@ kernel_addr_check=true load_addr_mask=1099511627775 load_offset=0 mem_mode=timing -mem_ranges=0:268435455 +mem_ranges=0:268435455:0:0:0:0 memories=system.mem_ctrls mmap_using_noreserve=false multi_thread=false num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null readfile= symbolfile= thermal_components= @@ -55,6 +60,7 @@ branchPred=Null checker=Null clk_domain=system.cpu.clk_domain cpu_id=0 +default_p_state=UNDEFINED do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true @@ -70,6 +76,10 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null profile=0 progress_interval=0 simpoint_start_insts= @@ -122,7 +132,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello +executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/alpha/tru64/hello gid=100 input=cin kvmInSE=false @@ -145,27 +155,27 @@ transition_latency=100000 [system.mem_ctrls] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -177,6 +187,7 @@ burst_length=8 channels=1 clk_domain=system.clk_domain conf_table_reported=true +default_p_state=UNDEFINED device_bus_width=8 device_rowbuffer_size=1024 device_size=536870912 @@ -184,12 +195,17 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 page_policy=open_adaptive -range=0:268435455 +power_model=Null +range=0:268435455:5:19:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10 @@ -211,9 +227,9 @@ tRTW=3 tWR=15 tWTR=8 tXAW=30 -tXP=0 +tXP=6 tXPDLL=0 -tXS=0 +tXS=270 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 @@ -227,12 +243,17 @@ access_backing_store=false all_instructions=false block_size_bytes=64 clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED eventq_index=0 hot_lines=false memory_size_bits=48 num_of_sequencers=1 number_of_virtual_networks=6 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 phys_mem=Null +power_model=Null randomization=false [system.ruby.clk_domain] @@ -249,6 +270,7 @@ children=directory dmaRequestToDir dmaResponseFromDir persistentFromDir persiste buffer_size=0 clk_domain=system.ruby.clk_domain cluster_id=0 +default_p_state=UNDEFINED directory=system.ruby.dir_cntrl0.directory directory_latency=5 distributed_persistent=true @@ -258,8 +280,12 @@ eventq_index=0 fixed_timeout_latency=100 l2_select_num_bits=0 number_of_TBEs=256 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 persistentFromDir=system.ruby.dir_cntrl0.persistentFromDir persistentToDir=system.ruby.dir_cntrl0.persistentToDir +power_model=Null recycle_latency=10 reissue_wakeup_latency=10 requestFromDir=system.ruby.dir_cntrl0.requestFromDir @@ -361,6 +387,7 @@ N_tokens=2 buffer_size=0 clk_domain=system.cpu.clk_domain cluster_id=0 +default_p_state=UNDEFINED dynamic_timeout_enabled=true eventq_index=0 fixed_timeout_latency=300 @@ -370,8 +397,12 @@ l2_select_num_bits=0 mandatoryQueue=system.ruby.l1_cntrl0.mandatoryQueue no_mig_atomic=true number_of_TBEs=256 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 persistentFromL1Cache=system.ruby.l1_cntrl0.persistentFromL1Cache persistentToL1Cache=system.ruby.l1_cntrl0.persistentToL1Cache +power_model=Null recycle_latency=10 reissue_wakeup_latency=10 requestFromL1Cache=system.ruby.l1_cntrl0.requestFromL1Cache @@ -497,17 +528,22 @@ coreid=99 dcache=system.ruby.l1_cntrl0.L1Dcache dcache_hit_latency=1 deadlock_threshold=500000 +default_p_state=UNDEFINED eventq_index=0 +garnet_standalone=false icache=system.ruby.l1_cntrl0.L1Icache icache_hit_latency=1 is_cpu_sequencer=true max_outstanding_requests=16 no_retry_on_stall=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null ruby_system=system.ruby support_data_reqs=true support_inst_reqs=true system=system -using_network_tester=false using_ruby_tester=false version=0 slave=system.cpu.icache_port system.cpu.dcache_port @@ -524,12 +560,17 @@ N_tokens=2 buffer_size=0 clk_domain=system.ruby.clk_domain cluster_id=0 +default_p_state=UNDEFINED eventq_index=0 filtering_enabled=true l2_request_latency=5 l2_response_latency=5 number_of_TBEs=256 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 persistentToL2Cache=system.ruby.l2_cntrl0.persistentToL2Cache +power_model=Null recycle_latency=10 responseFromL2Cache=system.ruby.l2_cntrl0.responseFromL2Cache responseToL2Cache=system.ruby.l2_cntrl0.responseToL2Cache @@ -626,18 +667,23 @@ eventq_index=0 [system.ruby.network] type=SimpleNetwork -children=ext_links0 ext_links1 ext_links2 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_link_buffers20 int_link_buffers21 int_link_buffers22 int_link_buffers23 int_link_buffers24 int_link_buffers25 int_link_buffers26 int_link_buffers27 int_link_buffers28 int_link_buffers29 int_link_buffers30 int_link_buffers31 int_link_buffers32 int_link_buffers33 int_link_buffers34 int_link_buffers35 int_links0 int_links1 int_links2 routers0 routers1 routers2 routers3 +children=ext_links0 ext_links1 ext_links2 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_link_buffers20 int_link_buffers21 int_link_buffers22 int_link_buffers23 int_link_buffers24 int_link_buffers25 int_link_buffers26 int_link_buffers27 int_link_buffers28 int_link_buffers29 int_link_buffers30 int_link_buffers31 int_link_buffers32 int_link_buffers33 int_link_buffers34 int_link_buffers35 int_link_buffers36 int_link_buffers37 int_link_buffers38 int_link_buffers39 int_link_buffers40 int_link_buffers41 int_link_buffers42 int_link_buffers43 int_link_buffers44 int_link_buffers45 int_link_buffers46 int_link_buffers47 int_link_buffers48 int_link_buffers49 int_link_buffers50 int_link_buffers51 int_link_buffers52 int_link_buffers53 int_link_buffers54 int_link_buffers55 int_link_buffers56 int_link_buffers57 int_link_buffers58 int_link_buffers59 int_link_buffers60 int_link_buffers61 int_link_buffers62 int_link_buffers63 int_link_buffers64 int_link_buffers65 int_link_buffers66 int_link_buffers67 int_link_buffers68 int_link_buffers69 int_link_buffers70 int_link_buffers71 int_links0 int_links1 int_links2 int_links3 int_links4 int_links5 routers0 routers1 routers2 routers3 adaptive_routing=false buffer_size=0 clk_domain=system.ruby.clk_domain control_msg_size=8 +default_p_state=UNDEFINED endpoint_bandwidth=1000 eventq_index=0 ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1 system.ruby.network.ext_links2 -int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19 system.ruby.network.int_link_buffers20 system.ruby.network.int_link_buffers21 system.ruby.network.int_link_buffers22 system.ruby.network.int_link_buffers23 system.ruby.network.int_link_buffers24 system.ruby.network.int_link_buffers25 system.ruby.network.int_link_buffers26 system.ruby.network.int_link_buffers27 system.ruby.network.int_link_buffers28 system.ruby.network.int_link_buffers29 system.ruby.network.int_link_buffers30 system.ruby.network.int_link_buffers31 system.ruby.network.int_link_buffers32 system.ruby.network.int_link_buffers33 system.ruby.network.int_link_buffers34 system.ruby.network.int_link_buffers35 -int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2 +int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19 system.ruby.network.int_link_buffers20 system.ruby.network.int_link_buffers21 system.ruby.network.int_link_buffers22 system.ruby.network.int_link_buffers23 system.ruby.network.int_link_buffers24 system.ruby.network.int_link_buffers25 system.ruby.network.int_link_buffers26 system.ruby.network.int_link_buffers27 system.ruby.network.int_link_buffers28 system.ruby.network.int_link_buffers29 system.ruby.network.int_link_buffers30 system.ruby.network.int_link_buffers31 system.ruby.network.int_link_buffers32 system.ruby.network.int_link_buffers33 system.ruby.network.int_link_buffers34 system.ruby.network.int_link_buffers35 system.ruby.network.int_link_buffers36 system.ruby.network.int_link_buffers37 system.ruby.network.int_link_buffers38 system.ruby.network.int_link_buffers39 system.ruby.network.int_link_buffers40 system.ruby.network.int_link_buffers41 system.ruby.network.int_link_buffers42 system.ruby.network.int_link_buffers43 system.ruby.network.int_link_buffers44 system.ruby.network.int_link_buffers45 system.ruby.network.int_link_buffers46 system.ruby.network.int_link_buffers47 system.ruby.network.int_link_buffers48 system.ruby.network.int_link_buffers49 system.ruby.network.int_link_buffers50 system.ruby.network.int_link_buffers51 system.ruby.network.int_link_buffers52 system.ruby.network.int_link_buffers53 system.ruby.network.int_link_buffers54 system.ruby.network.int_link_buffers55 system.ruby.network.int_link_buffers56 system.ruby.network.int_link_buffers57 system.ruby.network.int_link_buffers58 system.ruby.network.int_link_buffers59 system.ruby.network.int_link_buffers60 system.ruby.network.int_link_buffers61 system.ruby.network.int_link_buffers62 system.ruby.network.int_link_buffers63 system.ruby.network.int_link_buffers64 system.ruby.network.int_link_buffers65 system.ruby.network.int_link_buffers66 system.ruby.network.int_link_buffers67 system.ruby.network.int_link_buffers68 system.ruby.network.int_link_buffers69 system.ruby.network.int_link_buffers70 system.ruby.network.int_link_buffers71 +int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2 system.ruby.network.int_links3 system.ruby.network.int_links4 system.ruby.network.int_links5 netifs= number_of_virtual_networks=6 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null routers=system.ruby.network.routers0 system.ruby.network.routers1 system.ruby.network.routers2 system.ruby.network.routers3 ruby_system=system.ruby topology=Crossbar @@ -926,42 +972,342 @@ eventq_index=0 ordered=true randomization=false +[system.ruby.network.int_link_buffers36] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers37] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers38] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers39] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers40] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers41] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers42] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers43] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers44] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers45] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers46] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers47] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers48] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers49] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers50] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers51] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers52] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers53] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers54] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers55] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers56] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers57] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers58] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers59] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers60] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers61] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers62] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers63] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers64] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers65] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers66] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers67] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers68] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers69] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers70] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers71] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + [system.ruby.network.int_links0] type=SimpleIntLink bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers3 eventq_index=0 latency=1 link_id=3 -node_a=system.ruby.network.routers0 -node_b=system.ruby.network.routers3 +src_node=system.ruby.network.routers0 +src_outport= weight=1 [system.ruby.network.int_links1] type=SimpleIntLink bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers3 eventq_index=0 latency=1 link_id=4 -node_a=system.ruby.network.routers1 -node_b=system.ruby.network.routers3 +src_node=system.ruby.network.routers1 +src_outport= weight=1 [system.ruby.network.int_links2] type=SimpleIntLink bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers3 eventq_index=0 latency=1 link_id=5 -node_a=system.ruby.network.routers2 -node_b=system.ruby.network.routers3 +src_node=system.ruby.network.routers2 +src_outport= +weight=1 + +[system.ruby.network.int_links3] +type=SimpleIntLink +bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers0 +eventq_index=0 +latency=1 +link_id=6 +src_node=system.ruby.network.routers3 +src_outport= +weight=1 + +[system.ruby.network.int_links4] +type=SimpleIntLink +bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers1 +eventq_index=0 +latency=1 +link_id=7 +src_node=system.ruby.network.routers3 +src_outport= +weight=1 + +[system.ruby.network.int_links5] +type=SimpleIntLink +bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers2 +eventq_index=0 +latency=1 +link_id=8 +src_node=system.ruby.network.routers3 +src_outport= weight=1 [system.ruby.network.routers0] type=Switch children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17 port_buffers18 port_buffers19 port_buffers20 port_buffers21 port_buffers22 port_buffers23 clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED eventq_index=0 +latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 port_buffers=system.ruby.network.routers0.port_buffers00 system.ruby.network.routers0.port_buffers01 system.ruby.network.routers0.port_buffers02 system.ruby.network.routers0.port_buffers03 system.ruby.network.routers0.port_buffers04 system.ruby.network.routers0.port_buffers05 system.ruby.network.routers0.port_buffers06 system.ruby.network.routers0.port_buffers07 system.ruby.network.routers0.port_buffers08 system.ruby.network.routers0.port_buffers09 system.ruby.network.routers0.port_buffers10 system.ruby.network.routers0.port_buffers11 system.ruby.network.routers0.port_buffers12 system.ruby.network.routers0.port_buffers13 system.ruby.network.routers0.port_buffers14 system.ruby.network.routers0.port_buffers15 system.ruby.network.routers0.port_buffers16 system.ruby.network.routers0.port_buffers17 system.ruby.network.routers0.port_buffers18 system.ruby.network.routers0.port_buffers19 system.ruby.network.routers0.port_buffers20 system.ruby.network.routers0.port_buffers21 system.ruby.network.routers0.port_buffers22 system.ruby.network.routers0.port_buffers23 +power_model=Null router_id=0 virt_nets=6 @@ -1137,8 +1483,14 @@ randomization=false type=Switch children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17 port_buffers18 port_buffers19 port_buffers20 port_buffers21 port_buffers22 port_buffers23 clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED eventq_index=0 +latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 port_buffers=system.ruby.network.routers1.port_buffers00 system.ruby.network.routers1.port_buffers01 system.ruby.network.routers1.port_buffers02 system.ruby.network.routers1.port_buffers03 system.ruby.network.routers1.port_buffers04 system.ruby.network.routers1.port_buffers05 system.ruby.network.routers1.port_buffers06 system.ruby.network.routers1.port_buffers07 system.ruby.network.routers1.port_buffers08 system.ruby.network.routers1.port_buffers09 system.ruby.network.routers1.port_buffers10 system.ruby.network.routers1.port_buffers11 system.ruby.network.routers1.port_buffers12 system.ruby.network.routers1.port_buffers13 system.ruby.network.routers1.port_buffers14 system.ruby.network.routers1.port_buffers15 system.ruby.network.routers1.port_buffers16 system.ruby.network.routers1.port_buffers17 system.ruby.network.routers1.port_buffers18 system.ruby.network.routers1.port_buffers19 system.ruby.network.routers1.port_buffers20 system.ruby.network.routers1.port_buffers21 system.ruby.network.routers1.port_buffers22 system.ruby.network.routers1.port_buffers23 +power_model=Null router_id=1 virt_nets=6 @@ -1314,8 +1666,14 @@ randomization=false type=Switch children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17 port_buffers18 port_buffers19 port_buffers20 port_buffers21 port_buffers22 port_buffers23 clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED eventq_index=0 +latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 port_buffers=system.ruby.network.routers2.port_buffers00 system.ruby.network.routers2.port_buffers01 system.ruby.network.routers2.port_buffers02 system.ruby.network.routers2.port_buffers03 system.ruby.network.routers2.port_buffers04 system.ruby.network.routers2.port_buffers05 system.ruby.network.routers2.port_buffers06 system.ruby.network.routers2.port_buffers07 system.ruby.network.routers2.port_buffers08 system.ruby.network.routers2.port_buffers09 system.ruby.network.routers2.port_buffers10 system.ruby.network.routers2.port_buffers11 system.ruby.network.routers2.port_buffers12 system.ruby.network.routers2.port_buffers13 system.ruby.network.routers2.port_buffers14 system.ruby.network.routers2.port_buffers15 system.ruby.network.routers2.port_buffers16 system.ruby.network.routers2.port_buffers17 system.ruby.network.routers2.port_buffers18 system.ruby.network.routers2.port_buffers19 system.ruby.network.routers2.port_buffers20 system.ruby.network.routers2.port_buffers21 system.ruby.network.routers2.port_buffers22 system.ruby.network.routers2.port_buffers23 +power_model=Null router_id=2 virt_nets=6 @@ -1491,8 +1849,14 @@ randomization=false type=Switch children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17 port_buffers18 port_buffers19 port_buffers20 port_buffers21 port_buffers22 port_buffers23 port_buffers24 port_buffers25 port_buffers26 port_buffers27 port_buffers28 port_buffers29 port_buffers30 port_buffers31 port_buffers32 port_buffers33 port_buffers34 port_buffers35 clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED eventq_index=0 +latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 port_buffers=system.ruby.network.routers3.port_buffers00 system.ruby.network.routers3.port_buffers01 system.ruby.network.routers3.port_buffers02 system.ruby.network.routers3.port_buffers03 system.ruby.network.routers3.port_buffers04 system.ruby.network.routers3.port_buffers05 system.ruby.network.routers3.port_buffers06 system.ruby.network.routers3.port_buffers07 system.ruby.network.routers3.port_buffers08 system.ruby.network.routers3.port_buffers09 system.ruby.network.routers3.port_buffers10 system.ruby.network.routers3.port_buffers11 system.ruby.network.routers3.port_buffers12 system.ruby.network.routers3.port_buffers13 system.ruby.network.routers3.port_buffers14 system.ruby.network.routers3.port_buffers15 system.ruby.network.routers3.port_buffers16 system.ruby.network.routers3.port_buffers17 system.ruby.network.routers3.port_buffers18 system.ruby.network.routers3.port_buffers19 system.ruby.network.routers3.port_buffers20 system.ruby.network.routers3.port_buffers21 system.ruby.network.routers3.port_buffers22 system.ruby.network.routers3.port_buffers23 system.ruby.network.routers3.port_buffers24 system.ruby.network.routers3.port_buffers25 system.ruby.network.routers3.port_buffers26 system.ruby.network.routers3.port_buffers27 system.ruby.network.routers3.port_buffers28 system.ruby.network.routers3.port_buffers29 system.ruby.network.routers3.port_buffers30 system.ruby.network.routers3.port_buffers31 system.ruby.network.routers3.port_buffers32 system.ruby.network.routers3.port_buffers33 system.ruby.network.routers3.port_buffers34 system.ruby.network.routers3.port_buffers35 +power_model=Null router_id=3 virt_nets=6 @@ -1751,9 +2115,14 @@ randomization=false [system.sys_port_proxy] type=RubyPortProxy clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 is_cpu_sequencer=true no_retry_on_stall=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null ruby_system=system.ruby support_data_reqs=true support_inst_reqs=true diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simerr b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simerr index 1c18978fa..63982fce4 100755 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simerr +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simerr @@ -4,9 +4,8 @@ warn: rounding error > tolerance 1.250000 rounded to 1 warn: rounding error > tolerance 1.250000 rounded to 1 -warn: rounding error > tolerance - 1.250000 rounded to 1 warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes) warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files! warn: ignoring syscall sigprocmask(1, ...) diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout index 9a1a80ba2..57e88573f 100755 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout @@ -1,13 +1,15 @@ +Redirecting stdout to build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout +Redirecting stderr to build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 21 2016 14:12:23 -gem5 started Jan 21 2016 14:13:00 -gem5 executing on zizzer, pid 55410 -command line: build/ALPHA_MOESI_CMP_token/gem5.opt -d build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token +gem5 compiled Oct 13 2016 20:33:48 +gem5 started Oct 13 2016 20:34:16 +gem5 executing on e108600-lin, pid 27527 +command line: /work/curdun01/gem5-external.hg/build/ALPHA_MOESI_CMP_token/gem5.opt -d build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 40527 because target called exit() +Exiting @ tick 42756 because target called exit() diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt index 20325d4b9..0254766b0 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000041 # Number of seconds simulated -sim_ticks 40527 # Number of ticks simulated -final_tick 40527 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000043 # Number of seconds simulated +sim_ticks 42756 # Number of ticks simulated +final_tick 42756 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 89328 # Simulator instruction rate (inst/s) -host_op_rate 89293 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1403832 # Simulator tick rate (ticks/s) -host_mem_usage 454496 # Number of bytes of host memory used -host_seconds 0.03 # Real time elapsed on the host +host_inst_rate 50628 # Simulator instruction rate (inst/s) +host_op_rate 50604 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 839232 # Simulator tick rate (ticks/s) +host_mem_usage 411504 # Number of bytes of host memory used +host_seconds 0.05 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks -system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 40527 # Cumulative time (in ticks) in various power states +system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 42756 # Cumulative time (in ticks) in various power states system.mem_ctrls.bytes_read::ruby.dir_cntrl0 28672 # Number of bytes read from this memory system.mem_ctrls.bytes_read::total 28672 # Number of bytes read from this memory system.mem_ctrls.bytes_written::ruby.dir_cntrl0 5376 # Number of bytes written to this memory @@ -22,12 +22,12 @@ system.mem_ctrls.num_reads::ruby.dir_cntrl0 448 # system.mem_ctrls.num_reads::total 448 # Number of read requests responded to by this memory system.mem_ctrls.num_writes::ruby.dir_cntrl0 84 # Number of write requests responded to by this memory system.mem_ctrls.num_writes::total 84 # Number of write requests responded to by this memory -system.mem_ctrls.bw_read::ruby.dir_cntrl0 707478965 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_read::total 707478965 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::ruby.dir_cntrl0 132652306 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::total 132652306 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_total::ruby.dir_cntrl0 840131271 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.bw_total::total 840131271 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_read::ruby.dir_cntrl0 670595940 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 670595940 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::ruby.dir_cntrl0 125736739 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::total 125736739 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::ruby.dir_cntrl0 796332678 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 796332678 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrls.readReqs 448 # Number of read requests accepted system.mem_ctrls.writeReqs 84 # Number of write requests accepted system.mem_ctrls.readBursts 448 # Number of DRAM read bursts, including those serviced by the write queue @@ -74,7 +74,7 @@ system.mem_ctrls.perBankWrBursts::14 0 # Pe system.mem_ctrls.perBankWrBursts::15 1 # Per bank write bursts system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrls.totGap 40452 # Total gap between requests +system.mem_ctrls.totGap 42675 # Total gap between requests system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) @@ -185,20 +185,20 @@ system.mem_ctrls.wrQLenPdf::60 0 # Wh system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrls.bytesPerActivate::samples 73 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::mean 334.027397 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::gmean 221.884458 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::stdev 291.386817 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::0-127 19 26.03% 26.03% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::128-255 15 20.55% 46.58% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::256-383 13 17.81% 64.38% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::384-511 6 8.22% 72.60% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::512-639 7 9.59% 82.19% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::640-767 5 6.85% 89.04% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::768-895 1 1.37% 90.41% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::896-1023 2 2.74% 93.15% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::1024-1151 5 6.85% 100.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::total 73 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::samples 72 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 326.222222 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 214.888456 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 283.209683 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 20 27.78% 27.78% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 16 22.22% 50.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 10 13.89% 63.89% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 5 6.94% 70.83% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 9 12.50% 83.33% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 2 2.78% 86.11% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 6 8.33% 94.44% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 2 2.78% 97.22% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 2 2.78% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 72 # Bytes accessed per row activation system.mem_ctrls.rdPerTurnAround::samples 1 # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::mean 245 # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::gmean 245.000000 # Reads before turning the bus around for writes @@ -211,57 +211,67 @@ system.mem_ctrls.wrPerTurnAround::gmean 16.000000 # Wr system.mem_ctrls.wrPerTurnAround::stdev nan # Writes before turning the bus around for reads system.mem_ctrls.wrPerTurnAround::16 1 100.00% 100.00% # Writes before turning the bus around for reads system.mem_ctrls.wrPerTurnAround::total 1 # Writes before turning the bus around for reads -system.mem_ctrls.totQLat 2601 # Total ticks spent queuing -system.mem_ctrls.totMemAccLat 9726 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.totQLat 4832 # Total ticks spent queuing +system.mem_ctrls.totMemAccLat 11957 # Total ticks spent from burst creation until serviced by the DRAM system.mem_ctrls.totBusLat 1875 # Total ticks spent in databus transfers -system.mem_ctrls.avgQLat 6.94 # Average queueing delay per DRAM burst +system.mem_ctrls.avgQLat 12.89 # Average queueing delay per DRAM burst system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst -system.mem_ctrls.avgMemAccLat 25.94 # Average memory access latency per DRAM burst -system.mem_ctrls.avgRdBW 592.20 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrls.avgWrBW 25.27 # Average achieved write bandwidth in MiByte/s -system.mem_ctrls.avgRdBWSys 707.48 # Average system read bandwidth in MiByte/s -system.mem_ctrls.avgWrBWSys 132.65 # Average system write bandwidth in MiByte/s +system.mem_ctrls.avgMemAccLat 31.89 # Average memory access latency per DRAM burst +system.mem_ctrls.avgRdBW 561.32 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 23.95 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 670.60 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 125.74 # Average system write bandwidth in MiByte/s system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrls.busUtil 4.82 # Data bus utilization in percentage -system.mem_ctrls.busUtilRead 4.63 # Data bus utilization in percentage for reads -system.mem_ctrls.busUtilWrite 0.20 # Data bus utilization in percentage for writes +system.mem_ctrls.busUtil 4.57 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 4.39 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 0.19 # Data bus utilization in percentage for writes system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing -system.mem_ctrls.avgWrQLen 21.86 # Average write queue length when enqueuing -system.mem_ctrls.readRowHits 297 # Number of row buffer hits during reads +system.mem_ctrls.avgWrQLen 21.84 # Average write queue length when enqueuing +system.mem_ctrls.readRowHits 296 # Number of row buffer hits during reads system.mem_ctrls.writeRowHits 15 # Number of row buffer hits during writes -system.mem_ctrls.readRowHitRate 79.20 # Row buffer hit rate for reads +system.mem_ctrls.readRowHitRate 78.93 # Row buffer hit rate for reads system.mem_ctrls.writeRowHitRate 32.61 # Row buffer hit rate for writes -system.mem_ctrls.avgGap 76.04 # Average gap between requests -system.mem_ctrls.pageHitRate 74.11 # Row buffer hit rate, read and write combined -system.mem_ctrls_0.actEnergy 158760 # Energy for activate commands per rank (pJ) -system.mem_ctrls_0.preEnergy 88200 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_0.readEnergy 1896960 # Energy for read commands per rank (pJ) +system.mem_ctrls.avgGap 80.22 # Average gap between requests +system.mem_ctrls.pageHitRate 73.87 # Row buffer hit rate, read and write combined +system.mem_ctrls_0.actEnergy 178500 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 81144 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 1816416 # Energy for read commands per rank (pJ) system.mem_ctrls_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.mem_ctrls_0.refreshEnergy 2542800 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_0.actBackEnergy 25074756 # Energy for active background per rank (pJ) -system.mem_ctrls_0.preBackEnergy 1518600 # Energy for precharge background per rank (pJ) -system.mem_ctrls_0.totalEnergy 31280076 # Total energy per rank (pJ) -system.mem_ctrls_0.averagePower 798.164736 # Core power per rank (mW) -system.mem_ctrls_0.memoryStateTime::IDLE 2492 # Time in different power states +system.mem_ctrls_0.refreshEnergy 3073200.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 2612424 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 73344 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.actPowerDownEnergy 15837336 # Energy for active power-down per rank (pJ) +system.mem_ctrls_0.prePowerDownEnergy 808320 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls_0.totalEnergy 24480684 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 572.567219 # Core power per rank (mW) +system.mem_ctrls_0.totalIdleTime 36801 # Total Idle time Per DRAM Rank +system.mem_ctrls_0.memoryStateTime::IDLE 51 # Time in different power states system.mem_ctrls_0.memoryStateTime::REF 1300 # Time in different power states -system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT 35499 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrls_1.actEnergy 393120 # Energy for activate commands per rank (pJ) -system.mem_ctrls_1.preEnergy 218400 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_1.readEnergy 2658240 # Energy for read commands per rank (pJ) -system.mem_ctrls_1.writeEnergy 165888 # Energy for write commands per rank (pJ) -system.mem_ctrls_1.refreshEnergy 2542800 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_1.actBackEnergy 26158212 # Energy for active background per rank (pJ) -system.mem_ctrls_1.preBackEnergy 568200 # Energy for precharge background per rank (pJ) -system.mem_ctrls_1.totalEnergy 32704860 # Total energy per rank (pJ) -system.mem_ctrls_1.averagePower 834.520541 # Core power per rank (mW) -system.mem_ctrls_1.memoryStateTime::IDLE 821 # Time in different power states +system.mem_ctrls_0.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls_0.memoryStateTime::PRE_PDN 2105 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 4569 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT_PDN 34731 # Time in different power states +system.mem_ctrls_1.actEnergy 392700 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 197064 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 2467584 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 133632 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.refreshEnergy 3073200.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 3542208 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 293376 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.actPowerDownEnergy 15524520 # Energy for active power-down per rank (pJ) +system.mem_ctrls_1.prePowerDownEnergy 68736 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls_1.totalEnergy 25693020 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 600.921976 # Core power per rank (mW) +system.mem_ctrls_1.totalIdleTime 33391 # Total Idle time Per DRAM Rank +system.mem_ctrls_1.memoryStateTime::IDLE 512 # Time in different power states system.mem_ctrls_1.memoryStateTime::REF 1300 # Time in different power states -system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT 37083 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 40527 # Cumulative time (in ticks) in various power states +system.mem_ctrls_1.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls_1.memoryStateTime::PRE_PDN 179 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 6720 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT_PDN 34045 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 42756 # Cumulative time (in ticks) in various power states system.cpu.clk_domain.clock 1 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -296,8 +306,8 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 40527 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 40527 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 42756 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 42756 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 2577 # Number of instructions committed @@ -316,7 +326,7 @@ system.cpu.num_mem_refs 717 # nu system.cpu.num_load_insts 419 # Number of load instructions system.cpu.num_store_insts 298 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 40527 # Number of busy cycles +system.cpu.num_busy_cycles 42756 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 396 # Number of branches fetched @@ -356,7 +366,7 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 2585 # Class of executed instruction system.ruby.clk_domain.clock 1 # Clock period in ticks -system.ruby.pwrStateResidencyTicks::UNDEFINED 40527 # Cumulative time (in ticks) in various power states +system.ruby.pwrStateResidencyTicks::UNDEFINED 42756 # Cumulative time (in ticks) in various power states system.ruby.outstanding_req_hist_seqr::bucket_size 1 system.ruby.outstanding_req_hist_seqr::max_bucket 9 system.ruby.outstanding_req_hist_seqr::samples 3295 @@ -367,44 +377,44 @@ system.ruby.outstanding_req_hist_seqr::total 3295 system.ruby.latency_hist_seqr::bucket_size 64 system.ruby.latency_hist_seqr::max_bucket 639 system.ruby.latency_hist_seqr::samples 3294 -system.ruby.latency_hist_seqr::mean 11.303279 -system.ruby.latency_hist_seqr::gmean 1.905847 -system.ruby.latency_hist_seqr::stdev 27.108694 -system.ruby.latency_hist_seqr | 2919 88.62% 88.62% | 368 11.17% 99.79% | 2 0.06% 99.85% | 0 0.00% 99.85% | 3 0.09% 99.94% | 2 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.latency_hist_seqr::mean 11.979964 +system.ruby.latency_hist_seqr::gmean 1.922311 +system.ruby.latency_hist_seqr::stdev 28.863148 +system.ruby.latency_hist_seqr | 2919 88.62% 88.62% | 368 11.17% 99.79% | 2 0.06% 99.85% | 1 0.03% 99.88% | 0 0.00% 99.88% | 4 0.12% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.latency_hist_seqr::total 3294 system.ruby.hit_latency_hist_seqr::bucket_size 4 system.ruby.hit_latency_hist_seqr::max_bucket 39 system.ruby.hit_latency_hist_seqr::samples 2846 -system.ruby.hit_latency_hist_seqr::mean 1.554814 -system.ruby.hit_latency_hist_seqr::gmean 1.080771 -system.ruby.hit_latency_hist_seqr::stdev 3.499483 -system.ruby.hit_latency_hist_seqr | 2776 97.54% 97.54% | 0 0.00% 97.54% | 0 0.00% 97.54% | 0 0.00% 97.54% | 0 0.00% 97.54% | 9 0.32% 97.86% | 61 2.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.hit_latency_hist_seqr::mean 1.555868 +system.ruby.hit_latency_hist_seqr::gmean 1.080822 +system.ruby.hit_latency_hist_seqr::stdev 3.505788 +system.ruby.hit_latency_hist_seqr | 2776 97.54% 97.54% | 0 0.00% 97.54% | 0 0.00% 97.54% | 0 0.00% 97.54% | 0 0.00% 97.54% | 8 0.28% 97.82% | 62 2.18% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.hit_latency_hist_seqr::total 2846 system.ruby.miss_latency_hist_seqr::bucket_size 64 system.ruby.miss_latency_hist_seqr::max_bucket 639 system.ruby.miss_latency_hist_seqr::samples 448 -system.ruby.miss_latency_hist_seqr::mean 73.232143 -system.ruby.miss_latency_hist_seqr::gmean 69.999992 -system.ruby.miss_latency_hist_seqr::stdev 29.782878 -system.ruby.miss_latency_hist_seqr | 73 16.29% 16.29% | 368 82.14% 98.44% | 2 0.45% 98.88% | 0 0.00% 98.88% | 3 0.67% 99.55% | 2 0.45% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.miss_latency_hist_seqr::mean 78.200893 +system.ruby.miss_latency_hist_seqr::gmean 74.547837 +system.ruby.miss_latency_hist_seqr::stdev 31.179064 +system.ruby.miss_latency_hist_seqr | 73 16.29% 16.29% | 368 82.14% 98.44% | 2 0.45% 98.88% | 1 0.22% 99.11% | 0 0.00% 99.11% | 4 0.89% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.miss_latency_hist_seqr::total 448 system.ruby.Directory.incomplete_times_seqr 447 -system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 40527 # Cumulative time (in ticks) in various power states +system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 42756 # Cumulative time (in ticks) in various power states system.ruby.l1_cntrl0.L1Dcache.demand_hits 461 # Number of cache demand hits system.ruby.l1_cntrl0.L1Dcache.demand_misses 248 # Number of cache demand misses system.ruby.l1_cntrl0.L1Dcache.demand_accesses 709 # Number of cache demand accesses system.ruby.l1_cntrl0.L1Icache.demand_hits 2315 # Number of cache demand hits system.ruby.l1_cntrl0.L1Icache.demand_misses 270 # Number of cache demand misses system.ruby.l1_cntrl0.L1Icache.demand_accesses 2585 # Number of cache demand accesses -system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 40527 # Cumulative time (in ticks) in various power states -system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 40527 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 42756 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 42756 # Cumulative time (in ticks) in various power states system.ruby.l2_cntrl0.L2cache.demand_hits 64 # Number of cache demand hits system.ruby.l2_cntrl0.L2cache.demand_misses 454 # Number of cache demand misses system.ruby.l2_cntrl0.L2cache.demand_accesses 518 # Number of cache demand accesses -system.ruby.l2_cntrl0.pwrStateResidencyTicks::UNDEFINED 40527 # Cumulative time (in ticks) in various power states +system.ruby.l2_cntrl0.pwrStateResidencyTicks::UNDEFINED 42756 # Cumulative time (in ticks) in various power states system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 40527 # Cumulative time (in ticks) in various power states -system.ruby.network.routers0.percent_links_utilized 5.992918 +system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 42756 # Cumulative time (in ticks) in various power states +system.ruby.network.routers0.percent_links_utilized 5.680489 system.ruby.network.routers0.msg_count.Request_Control::1 518 system.ruby.network.routers0.msg_count.Response_Data::4 448 system.ruby.network.routers0.msg_count.ResponseL2hit_Data::4 70 @@ -417,8 +427,8 @@ system.ruby.network.routers0.msg_bytes.ResponseL2hit_Data::4 5040 system.ruby.network.routers0.msg_bytes.Response_Control::4 8 system.ruby.network.routers0.msg_bytes.Writeback_Data::4 36144 system.ruby.network.routers0.msg_bytes.Persistent_Control::3 128 -system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 40527 # Cumulative time (in ticks) in various power states -system.ruby.network.routers1.percent_links_utilized 4.472327 +system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 42756 # Cumulative time (in ticks) in various power states +system.ruby.network.routers1.percent_links_utilized 4.239171 system.ruby.network.routers1.msg_count.Request_Control::1 518 system.ruby.network.routers1.msg_count.Request_Control::2 454 system.ruby.network.routers1.msg_count.ResponseL2hit_Data::4 70 @@ -433,8 +443,8 @@ system.ruby.network.routers1.msg_bytes.Response_Control::4 8 system.ruby.network.routers1.msg_bytes.Writeback_Data::4 42192 system.ruby.network.routers1.msg_bytes.Writeback_Control::4 2920 system.ruby.network.routers1.msg_bytes.Persistent_Control::3 64 -system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 40527 # Cumulative time (in ticks) in various power states -system.ruby.network.routers2.percent_links_utilized 3.463740 +system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 42756 # Cumulative time (in ticks) in various power states +system.ruby.network.routers2.percent_links_utilized 3.283165 system.ruby.network.routers2.msg_count.Request_Control::2 454 system.ruby.network.routers2.msg_count.Response_Data::4 448 system.ruby.network.routers2.msg_count.Writeback_Data::4 84 @@ -445,8 +455,8 @@ system.ruby.network.routers2.msg_bytes.Response_Data::4 32256 system.ruby.network.routers2.msg_bytes.Writeback_Data::4 6048 system.ruby.network.routers2.msg_bytes.Writeback_Control::4 2920 system.ruby.network.routers2.msg_bytes.Persistent_Control::3 64 -system.ruby.network.routers3.pwrStateResidencyTicks::UNDEFINED 40527 # Cumulative time (in ticks) in various power states -system.ruby.network.routers3.percent_links_utilized 4.642995 +system.ruby.network.routers3.pwrStateResidencyTicks::UNDEFINED 42756 # Cumulative time (in ticks) in various power states +system.ruby.network.routers3.percent_links_utilized 4.400942 system.ruby.network.routers3.msg_count.Request_Control::1 518 system.ruby.network.routers3.msg_count.Request_Control::2 454 system.ruby.network.routers3.msg_count.Response_Data::4 448 @@ -463,7 +473,7 @@ system.ruby.network.routers3.msg_bytes.Response_Control::4 8 system.ruby.network.routers3.msg_bytes.Writeback_Data::4 42192 system.ruby.network.routers3.msg_bytes.Writeback_Control::4 2920 system.ruby.network.routers3.msg_bytes.Persistent_Control::3 128 -system.ruby.network.pwrStateResidencyTicks::UNDEFINED 40527 # Cumulative time (in ticks) in various power states +system.ruby.network.pwrStateResidencyTicks::UNDEFINED 42756 # Cumulative time (in ticks) in various power states system.ruby.network.msg_count.Request_Control 2916 system.ruby.network.msg_count.Response_Data 1344 system.ruby.network.msg_count.ResponseL2hit_Data 210 @@ -478,8 +488,8 @@ system.ruby.network.msg_byte.Response_Control 24 system.ruby.network.msg_byte.Writeback_Data 126576 system.ruby.network.msg_byte.Writeback_Control 8760 system.ruby.network.msg_byte.Persistent_Control 384 -system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 40527 # Cumulative time (in ticks) in various power states -system.ruby.network.routers0.throttle0.link_utilization 5.762825 +system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 42756 # Cumulative time (in ticks) in various power states +system.ruby.network.routers0.throttle0.link_utilization 5.462391 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 448 system.ruby.network.routers0.throttle0.msg_count.ResponseL2hit_Data::4 70 system.ruby.network.routers0.throttle0.msg_count.Response_Control::4 1 @@ -488,21 +498,21 @@ system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 32256 system.ruby.network.routers0.throttle0.msg_bytes.ResponseL2hit_Data::4 5040 system.ruby.network.routers0.throttle0.msg_bytes.Response_Control::4 8 system.ruby.network.routers0.throttle0.msg_bytes.Persistent_Control::3 64 -system.ruby.network.routers0.throttle1.link_utilization 6.223012 +system.ruby.network.routers0.throttle1.link_utilization 5.898587 system.ruby.network.routers0.throttle1.msg_count.Request_Control::1 518 system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::4 502 system.ruby.network.routers0.throttle1.msg_count.Persistent_Control::3 8 system.ruby.network.routers0.throttle1.msg_bytes.Request_Control::1 4144 system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::4 36144 system.ruby.network.routers0.throttle1.msg_bytes.Persistent_Control::3 64 -system.ruby.network.routers1.throttle0.link_utilization 6.223012 +system.ruby.network.routers1.throttle0.link_utilization 5.898587 system.ruby.network.routers1.throttle0.msg_count.Request_Control::1 518 system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::4 502 system.ruby.network.routers1.throttle0.msg_count.Persistent_Control::3 8 system.ruby.network.routers1.throttle0.msg_bytes.Request_Control::1 4144 system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::4 36144 system.ruby.network.routers1.throttle0.msg_bytes.Persistent_Control::3 64 -system.ruby.network.routers1.throttle1.link_utilization 2.721642 +system.ruby.network.routers1.throttle1.link_utilization 2.579755 system.ruby.network.routers1.throttle1.msg_count.Request_Control::2 454 system.ruby.network.routers1.throttle1.msg_count.ResponseL2hit_Data::4 70 system.ruby.network.routers1.throttle1.msg_count.Response_Control::4 1 @@ -513,7 +523,7 @@ system.ruby.network.routers1.throttle1.msg_bytes.ResponseL2hit_Data::4 5 system.ruby.network.routers1.throttle1.msg_bytes.Response_Control::4 8 system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Data::4 6048 system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::4 2920 -system.ruby.network.routers2.throttle0.link_utilization 1.953019 +system.ruby.network.routers2.throttle0.link_utilization 1.851202 system.ruby.network.routers2.throttle0.msg_count.Request_Control::2 454 system.ruby.network.routers2.throttle0.msg_count.Writeback_Data::4 84 system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::4 365 @@ -522,24 +532,24 @@ system.ruby.network.routers2.throttle0.msg_bytes.Request_Control::2 3632 system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Data::4 6048 system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::4 2920 system.ruby.network.routers2.throttle0.msg_bytes.Persistent_Control::3 64 -system.ruby.network.routers2.throttle1.link_utilization 4.974461 +system.ruby.network.routers2.throttle1.link_utilization 4.715128 system.ruby.network.routers2.throttle1.msg_count.Response_Data::4 448 system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::4 32256 -system.ruby.network.routers3.throttle0.link_utilization 5.752955 +system.ruby.network.routers3.throttle0.link_utilization 5.453036 system.ruby.network.routers3.throttle0.msg_count.Response_Data::4 448 system.ruby.network.routers3.throttle0.msg_count.ResponseL2hit_Data::4 70 system.ruby.network.routers3.throttle0.msg_count.Response_Control::4 1 system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::4 32256 system.ruby.network.routers3.throttle0.msg_bytes.ResponseL2hit_Data::4 5040 system.ruby.network.routers3.throttle0.msg_bytes.Response_Control::4 8 -system.ruby.network.routers3.throttle1.link_utilization 6.223012 +system.ruby.network.routers3.throttle1.link_utilization 5.898587 system.ruby.network.routers3.throttle1.msg_count.Request_Control::1 518 system.ruby.network.routers3.throttle1.msg_count.Writeback_Data::4 502 system.ruby.network.routers3.throttle1.msg_count.Persistent_Control::3 8 system.ruby.network.routers3.throttle1.msg_bytes.Request_Control::1 4144 system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::4 36144 system.ruby.network.routers3.throttle1.msg_bytes.Persistent_Control::3 64 -system.ruby.network.routers3.throttle2.link_utilization 1.953019 +system.ruby.network.routers3.throttle2.link_utilization 1.851202 system.ruby.network.routers3.throttle2.msg_count.Request_Control::2 454 system.ruby.network.routers3.throttle2.msg_count.Writeback_Data::4 84 system.ruby.network.routers3.throttle2.msg_count.Writeback_Control::4 365 @@ -548,36 +558,36 @@ system.ruby.network.routers3.throttle2.msg_bytes.Request_Control::2 3632 system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Data::4 6048 system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Control::4 2920 system.ruby.network.routers3.throttle2.msg_bytes.Persistent_Control::3 64 -system.ruby.LD.latency_hist_seqr::bucket_size 32 -system.ruby.LD.latency_hist_seqr::max_bucket 319 +system.ruby.LD.latency_hist_seqr::bucket_size 16 +system.ruby.LD.latency_hist_seqr::max_bucket 159 system.ruby.LD.latency_hist_seqr::samples 415 -system.ruby.LD.latency_hist_seqr::mean 27.009639 -system.ruby.LD.latency_hist_seqr::gmean 5.745092 -system.ruby.LD.latency_hist_seqr::stdev 35.695436 -system.ruby.LD.latency_hist_seqr | 266 64.10% 64.10% | 50 12.05% 76.14% | 86 20.72% 96.87% | 10 2.41% 99.28% | 2 0.48% 99.76% | 0 0.00% 99.76% | 0 0.00% 99.76% | 0 0.00% 99.76% | 0 0.00% 99.76% | 1 0.24% 100.00% +system.ruby.LD.latency_hist_seqr::mean 27.997590 +system.ruby.LD.latency_hist_seqr::gmean 5.837138 +system.ruby.LD.latency_hist_seqr::stdev 35.585408 +system.ruby.LD.latency_hist_seqr | 233 56.14% 56.14% | 33 7.95% 64.10% | 48 11.57% 75.66% | 2 0.48% 76.14% | 68 16.39% 92.53% | 18 4.34% 96.87% | 10 2.41% 99.28% | 1 0.24% 99.52% | 0 0.00% 99.52% | 2 0.48% 100.00% system.ruby.LD.latency_hist_seqr::total 415 system.ruby.LD.hit_latency_hist_seqr::bucket_size 4 system.ruby.LD.hit_latency_hist_seqr::max_bucket 39 system.ruby.LD.hit_latency_hist_seqr::samples 266 -system.ruby.LD.hit_latency_hist_seqr::mean 3.834586 -system.ruby.LD.hit_latency_hist_seqr::gmean 1.482071 -system.ruby.LD.hit_latency_hist_seqr::stdev 7.549265 -system.ruby.LD.hit_latency_hist_seqr | 233 87.59% 87.59% | 0 0.00% 87.59% | 0 0.00% 87.59% | 0 0.00% 87.59% | 0 0.00% 87.59% | 2 0.75% 88.35% | 31 11.65% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.hit_latency_hist_seqr::mean 3.845865 +system.ruby.LD.hit_latency_hist_seqr::gmean 1.482816 +system.ruby.LD.hit_latency_hist_seqr::stdev 7.577195 +system.ruby.LD.hit_latency_hist_seqr | 233 87.59% 87.59% | 0 0.00% 87.59% | 0 0.00% 87.59% | 0 0.00% 87.59% | 0 0.00% 87.59% | 1 0.38% 87.97% | 32 12.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.hit_latency_hist_seqr::total 266 -system.ruby.LD.miss_latency_hist_seqr::bucket_size 32 -system.ruby.LD.miss_latency_hist_seqr::max_bucket 319 +system.ruby.LD.miss_latency_hist_seqr::bucket_size 16 +system.ruby.LD.miss_latency_hist_seqr::max_bucket 159 system.ruby.LD.miss_latency_hist_seqr::samples 149 -system.ruby.LD.miss_latency_hist_seqr::mean 68.382550 -system.ruby.LD.miss_latency_hist_seqr::gmean 64.532565 -system.ruby.LD.miss_latency_hist_seqr::stdev 27.813471 -system.ruby.LD.miss_latency_hist_seqr | 0 0.00% 0.00% | 50 33.56% 33.56% | 86 57.72% 91.28% | 10 6.71% 97.99% | 2 1.34% 99.33% | 0 0.00% 99.33% | 0 0.00% 99.33% | 0 0.00% 99.33% | 0 0.00% 99.33% | 1 0.67% 100.00% +system.ruby.LD.miss_latency_hist_seqr::mean 71.114094 +system.ruby.LD.miss_latency_hist_seqr::gmean 67.393219 +system.ruby.LD.miss_latency_hist_seqr::stdev 22.792700 +system.ruby.LD.miss_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 48 32.21% 32.21% | 2 1.34% 33.56% | 68 45.64% 79.19% | 18 12.08% 91.28% | 10 6.71% 97.99% | 1 0.67% 98.66% | 0 0.00% 98.66% | 2 1.34% 100.00% system.ruby.LD.miss_latency_hist_seqr::total 149 system.ruby.ST.latency_hist_seqr::bucket_size 16 system.ruby.ST.latency_hist_seqr::max_bucket 159 system.ruby.ST.latency_hist_seqr::samples 294 -system.ruby.ST.latency_hist_seqr::mean 12.595238 -system.ruby.ST.latency_hist_seqr::gmean 2.381363 -system.ruby.ST.latency_hist_seqr::stdev 23.818056 +system.ruby.ST.latency_hist_seqr::mean 13.153061 +system.ruby.ST.latency_hist_seqr::gmean 2.398410 +system.ruby.ST.latency_hist_seqr::stdev 25.296880 system.ruby.ST.latency_hist_seqr | 228 77.55% 77.55% | 14 4.76% 82.31% | 20 6.80% 89.12% | 3 1.02% 90.14% | 23 7.82% 97.96% | 6 2.04% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ST.latency_hist_seqr::total 294 system.ruby.ST.hit_latency_hist_seqr::bucket_size 4 @@ -591,18 +601,18 @@ system.ruby.ST.hit_latency_hist_seqr::total 242 system.ruby.ST.miss_latency_hist_seqr::bucket_size 16 system.ruby.ST.miss_latency_hist_seqr::max_bucket 159 system.ruby.ST.miss_latency_hist_seqr::samples 52 -system.ruby.ST.miss_latency_hist_seqr::mean 60.865385 -system.ruby.ST.miss_latency_hist_seqr::gmean 58.719474 -system.ruby.ST.miss_latency_hist_seqr::stdev 16.012286 +system.ruby.ST.miss_latency_hist_seqr::mean 64.019231 +system.ruby.ST.miss_latency_hist_seqr::gmean 61.135942 +system.ruby.ST.miss_latency_hist_seqr::stdev 18.838311 system.ruby.ST.miss_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 20 38.46% 38.46% | 3 5.77% 44.23% | 23 44.23% 88.46% | 6 11.54% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ST.miss_latency_hist_seqr::total 52 system.ruby.IFETCH.latency_hist_seqr::bucket_size 64 system.ruby.IFETCH.latency_hist_seqr::max_bucket 639 system.ruby.IFETCH.latency_hist_seqr::samples 2585 -system.ruby.IFETCH.latency_hist_seqr::mean 8.634816 -system.ruby.IFETCH.latency_hist_seqr::gmean 1.556513 -system.ruby.IFETCH.latency_hist_seqr::stdev 24.922226 -system.ruby.IFETCH.latency_hist_seqr | 2338 90.44% 90.44% | 243 9.40% 99.85% | 0 0.00% 99.85% | 0 0.00% 99.85% | 2 0.08% 99.92% | 2 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.latency_hist_seqr::mean 9.275048 +system.ruby.IFETCH.latency_hist_seqr::gmean 1.568384 +system.ruby.IFETCH.latency_hist_seqr::stdev 27.157574 +system.ruby.IFETCH.latency_hist_seqr | 2338 90.44% 90.44% | 242 9.36% 99.81% | 0 0.00% 99.81% | 1 0.04% 99.85% | 0 0.00% 99.85% | 4 0.15% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.latency_hist_seqr::total 2585 system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 4 system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 39 @@ -615,10 +625,10 @@ system.ruby.IFETCH.hit_latency_hist_seqr::total 2338 system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 64 system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 639 system.ruby.IFETCH.miss_latency_hist_seqr::samples 247 -system.ruby.IFETCH.miss_latency_hist_seqr::mean 78.761134 -system.ruby.IFETCH.miss_latency_hist_seqr::gmean 76.290474 -system.ruby.IFETCH.miss_latency_hist_seqr::stdev 31.873920 -system.ruby.IFETCH.miss_latency_hist_seqr | 0 0.00% 0.00% | 243 98.38% 98.38% | 0 0.00% 98.38% | 0 0.00% 98.38% | 2 0.81% 99.19% | 2 0.81% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.miss_latency_hist_seqr::mean 85.461538 +system.ruby.IFETCH.miss_latency_hist_seqr::gmean 82.604305 +system.ruby.IFETCH.miss_latency_hist_seqr::stdev 35.418255 +system.ruby.IFETCH.miss_latency_hist_seqr | 0 0.00% 0.00% | 242 97.98% 97.98% | 0 0.00% 97.98% | 1 0.40% 98.38% | 0 0.00% 98.38% | 4 1.62% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.miss_latency_hist_seqr::total 247 system.ruby.L1Cache.hit_mach_latency_hist_seqr::bucket_size 1 system.ruby.L1Cache.hit_mach_latency_hist_seqr::max_bucket 9 @@ -630,18 +640,18 @@ system.ruby.L1Cache.hit_mach_latency_hist_seqr::total 2776 system.ruby.L2Cache.hit_mach_latency_hist_seqr::bucket_size 4 system.ruby.L2Cache.hit_mach_latency_hist_seqr::max_bucket 39 system.ruby.L2Cache.hit_mach_latency_hist_seqr::samples 70 -system.ruby.L2Cache.hit_mach_latency_hist_seqr::mean 23.557143 -system.ruby.L2Cache.hit_mach_latency_hist_seqr::gmean 23.524270 -system.ruby.L2Cache.hit_mach_latency_hist_seqr::stdev 1.199465 -system.ruby.L2Cache.hit_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 9 12.86% 12.86% | 61 87.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L2Cache.hit_mach_latency_hist_seqr::mean 23.600000 +system.ruby.L2Cache.hit_mach_latency_hist_seqr::gmean 23.569187 +system.ruby.L2Cache.hit_mach_latency_hist_seqr::stdev 1.159710 +system.ruby.L2Cache.hit_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 8 11.43% 11.43% | 62 88.57% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.L2Cache.hit_mach_latency_hist_seqr::total 70 system.ruby.Directory.miss_mach_latency_hist_seqr::bucket_size 64 system.ruby.Directory.miss_mach_latency_hist_seqr::max_bucket 639 system.ruby.Directory.miss_mach_latency_hist_seqr::samples 448 -system.ruby.Directory.miss_mach_latency_hist_seqr::mean 73.232143 -system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 69.999992 -system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 29.782878 -system.ruby.Directory.miss_mach_latency_hist_seqr | 73 16.29% 16.29% | 368 82.14% 98.44% | 2 0.45% 98.88% | 0 0.00% 98.88% | 3 0.67% 99.55% | 2 0.45% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_mach_latency_hist_seqr::mean 78.200893 +system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 74.547837 +system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 31.179064 +system.ruby.Directory.miss_mach_latency_hist_seqr | 73 16.29% 16.29% | 368 82.14% 98.44% | 2 0.45% 98.88% | 1 0.22% 99.11% | 0 0.00% 99.11% | 4 0.89% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.Directory.miss_mach_latency_hist_seqr::total 448 system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::bucket_size 1 system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::max_bucket 9 @@ -679,18 +689,18 @@ system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::total 233 system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::bucket_size 4 system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::max_bucket 39 system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::samples 33 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::mean 23.848485 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::gmean 23.840140 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::stdev 0.618527 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 2 6.06% 6.06% | 31 93.94% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::mean 23.939394 +system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::gmean 23.936802 +system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::stdev 0.348155 +system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 3.03% 3.03% | 32 96.97% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::total 33 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size 32 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket 319 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size 16 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket 159 system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples 149 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 68.382550 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 64.532565 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 27.813471 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 50 33.56% 33.56% | 86 57.72% 91.28% | 10 6.71% 97.99% | 2 1.34% 99.33% | 0 0.00% 99.33% | 0 0.00% 99.33% | 0 0.00% 99.33% | 0 0.00% 99.33% | 1 0.67% 100.00% +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 71.114094 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 67.393219 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 22.792700 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 48 32.21% 32.21% | 2 1.34% 33.56% | 68 45.64% 79.19% | 18 12.08% 91.28% | 10 6.71% 97.99% | 1 0.67% 98.66% | 0 0.00% 98.66% | 2 1.34% 100.00% system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total 149 system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::bucket_size 1 system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::max_bucket 9 @@ -710,9 +720,9 @@ system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::total 14 system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size 16 system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket 159 system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::samples 52 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 60.865385 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 58.719474 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 16.012286 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 64.019231 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 61.135942 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 18.838311 system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 20 38.46% 38.46% | 3 5.77% 44.23% | 23 44.23% 88.46% | 6 11.54% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total 52 system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::bucket_size 1 @@ -732,10 +742,10 @@ system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::total 23 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::samples 247 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 78.761134 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 76.290474 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 31.873920 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 243 98.38% 98.38% | 0 0.00% 98.38% | 0 0.00% 98.38% | 2 0.81% 99.19% | 2 0.81% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 85.461538 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 82.604305 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 35.418255 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 242 97.98% 97.98% | 0 0.00% 97.98% | 1 0.40% 98.38% | 0 0.00% 98.38% | 4 1.62% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::total 247 system.ruby.Directory_Controller.GETX 61 0.00% 0.00% system.ruby.Directory_Controller.GETS 398 0.00% 0.00% @@ -752,6 +762,7 @@ system.ruby.Directory_Controller.O.GETX 52 0.00% 0.00% system.ruby.Directory_Controller.O.GETS 396 0.00% 0.00% system.ruby.Directory_Controller.O.Ack_All_Tokens 15 0.00% 0.00% system.ruby.Directory_Controller.NO.GETX 6 0.00% 0.00% +system.ruby.Directory_Controller.NO.Lockdown 1 0.00% 0.00% system.ruby.Directory_Controller.NO.Data_Owner 3 0.00% 0.00% system.ruby.Directory_Controller.NO.Data_All_Tokens 81 0.00% 0.00% system.ruby.Directory_Controller.NO.Ack_Owner 16 0.00% 0.00% @@ -760,9 +771,9 @@ system.ruby.Directory_Controller.L.Unlockdown 4 0.00% 0.00% system.ruby.Directory_Controller.O_W.GETX 3 0.00% 0.00% system.ruby.Directory_Controller.O_W.GETS 2 0.00% 0.00% system.ruby.Directory_Controller.O_W.Memory_Ack 84 0.00% 0.00% -system.ruby.Directory_Controller.L_NO_W.Memory_Data 4 0.00% 0.00% -system.ruby.Directory_Controller.NO_W.Lockdown 4 0.00% 0.00% -system.ruby.Directory_Controller.NO_W.Memory_Data 444 0.00% 0.00% +system.ruby.Directory_Controller.L_NO_W.Memory_Data 3 0.00% 0.00% +system.ruby.Directory_Controller.NO_W.Lockdown 3 0.00% 0.00% +system.ruby.Directory_Controller.NO_W.Memory_Data 445 0.00% 0.00% system.ruby.L1Cache_Controller.Load 415 0.00% 0.00% system.ruby.L1Cache_Controller.Ifetch 2585 0.00% 0.00% system.ruby.L1Cache_Controller.Store 294 0.00% 0.00% @@ -781,7 +792,7 @@ system.ruby.L1Cache_Controller.S.Ifetch 158 0.00% 0.00% system.ruby.L1Cache_Controller.S.Store 8 0.00% 0.00% system.ruby.L1Cache_Controller.S.L1_Replacement 48 0.00% 0.00% system.ruby.L1Cache_Controller.M.Load 66 0.00% 0.00% -system.ruby.L1Cache_Controller.M.Ifetch 1099 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Ifetch 1098 0.00% 0.00% system.ruby.L1Cache_Controller.M.Store 29 0.00% 0.00% system.ruby.L1Cache_Controller.M.L1_Replacement 358 0.00% 0.00% system.ruby.L1Cache_Controller.M.Own_Lock_or_Unlock 4 0.00% 0.00% @@ -789,7 +800,7 @@ system.ruby.L1Cache_Controller.MM.Load 96 0.00% 0.00% system.ruby.L1Cache_Controller.MM.Store 103 0.00% 0.00% system.ruby.L1Cache_Controller.MM.L1_Replacement 96 0.00% 0.00% system.ruby.L1Cache_Controller.M_W.Load 36 0.00% 0.00% -system.ruby.L1Cache_Controller.M_W.Ifetch 1058 0.00% 0.00% +system.ruby.L1Cache_Controller.M_W.Ifetch 1059 0.00% 0.00% system.ruby.L1Cache_Controller.M_W.Store 3 0.00% 0.00% system.ruby.L1Cache_Controller.M_W.L1_Replacement 1 0.00% 0.00% system.ruby.L1Cache_Controller.M_W.Use_TimeoutNoStarvers 392 0.00% 0.00% diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini index 18d7c2ab4..8207d6ac7 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini @@ -14,6 +14,7 @@ children=clk_domain cpu dvfs_handler mem_ctrls ruby sys_port_proxy voltage_domai boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 exit_on_work_items=false init_param=0 @@ -22,11 +23,15 @@ kernel_addr_check=true load_addr_mask=1099511627775 load_offset=0 mem_mode=timing -mem_ranges=0:268435455 +mem_ranges=0:268435455:0:0:0:0 memories=system.mem_ctrls mmap_using_noreserve=false multi_thread=false num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null readfile= symbolfile= thermal_components= @@ -55,6 +60,7 @@ branchPred=Null checker=Null clk_domain=system.cpu.clk_domain cpu_id=0 +default_p_state=UNDEFINED do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true @@ -70,6 +76,10 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null profile=0 progress_interval=0 simpoint_start_insts= @@ -122,7 +132,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello +executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/alpha/tru64/hello gid=100 input=cin kvmInSE=false @@ -145,27 +155,27 @@ transition_latency=100000 [system.mem_ctrls] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -177,6 +187,7 @@ burst_length=8 channels=1 clk_domain=system.clk_domain conf_table_reported=true +default_p_state=UNDEFINED device_bus_width=8 device_rowbuffer_size=1024 device_size=536870912 @@ -184,12 +195,17 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 page_policy=open_adaptive -range=0:268435455 +power_model=Null +range=0:268435455:5:19:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10 @@ -211,9 +227,9 @@ tRTW=3 tWR=15 tWTR=8 tXAW=30 -tXP=0 +tXP=6 tXPDLL=0 -tXS=0 +tXS=270 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 @@ -227,12 +243,17 @@ access_backing_store=false all_instructions=false block_size_bytes=64 clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED eventq_index=0 hot_lines=false memory_size_bits=48 num_of_sequencers=1 number_of_virtual_networks=6 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 phys_mem=Null +power_model=Null randomization=false [system.ruby.clk_domain] @@ -249,6 +270,7 @@ children=directory dmaRequestToDir dmaResponseFromDir forwardFromDir probeFilter buffer_size=0 clk_domain=system.ruby.clk_domain cluster_id=0 +default_p_state=UNDEFINED directory=system.ruby.dir_cntrl0.directory dmaRequestToDir=system.ruby.dir_cntrl0.dmaRequestToDir dmaResponseFromDir=system.ruby.dir_cntrl0.dmaResponseFromDir @@ -257,6 +279,10 @@ forwardFromDir=system.ruby.dir_cntrl0.forwardFromDir from_memory_controller_latency=2 full_bit_dir_enabled=false number_of_TBEs=256 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null probeFilter=system.ruby.dir_cntrl0.probeFilter probe_filter_enabled=false recycle_latency=10 @@ -384,6 +410,7 @@ buffer_size=0 cache_response_latency=10 clk_domain=system.cpu.clk_domain cluster_id=0 +default_p_state=UNDEFINED eventq_index=0 forwardToCache=system.ruby.l1_cntrl0.forwardToCache issue_latency=2 @@ -391,6 +418,10 @@ l2_cache_hit_latency=10 mandatoryQueue=system.ruby.l1_cntrl0.mandatoryQueue no_mig_atomic=true number_of_TBEs=256 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null recycle_latency=10 requestFromCache=system.ruby.l1_cntrl0.requestFromCache responseFromCache=system.ruby.l1_cntrl0.responseFromCache @@ -522,17 +553,22 @@ coreid=99 dcache=system.ruby.l1_cntrl0.L1Dcache dcache_hit_latency=1 deadlock_threshold=500000 +default_p_state=UNDEFINED eventq_index=0 +garnet_standalone=false icache=system.ruby.l1_cntrl0.L1Icache icache_hit_latency=1 is_cpu_sequencer=true max_outstanding_requests=16 no_retry_on_stall=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null ruby_system=system.ruby support_data_reqs=true support_inst_reqs=true system=system -using_network_tester=false using_ruby_tester=false version=0 slave=system.cpu.icache_port system.cpu.dcache_port @@ -560,18 +596,23 @@ eventq_index=0 [system.ruby.network] type=SimpleNetwork -children=ext_links0 ext_links1 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_link_buffers20 int_link_buffers21 int_link_buffers22 int_link_buffers23 int_links0 int_links1 routers0 routers1 routers2 +children=ext_links0 ext_links1 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_link_buffers20 int_link_buffers21 int_link_buffers22 int_link_buffers23 int_link_buffers24 int_link_buffers25 int_link_buffers26 int_link_buffers27 int_link_buffers28 int_link_buffers29 int_link_buffers30 int_link_buffers31 int_link_buffers32 int_link_buffers33 int_link_buffers34 int_link_buffers35 int_link_buffers36 int_link_buffers37 int_link_buffers38 int_link_buffers39 int_link_buffers40 int_link_buffers41 int_link_buffers42 int_link_buffers43 int_link_buffers44 int_link_buffers45 int_link_buffers46 int_link_buffers47 int_links0 int_links1 int_links2 int_links3 routers0 routers1 routers2 adaptive_routing=false buffer_size=0 clk_domain=system.ruby.clk_domain control_msg_size=8 +default_p_state=UNDEFINED endpoint_bandwidth=1000 eventq_index=0 ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1 -int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19 system.ruby.network.int_link_buffers20 system.ruby.network.int_link_buffers21 system.ruby.network.int_link_buffers22 system.ruby.network.int_link_buffers23 -int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 +int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19 system.ruby.network.int_link_buffers20 system.ruby.network.int_link_buffers21 system.ruby.network.int_link_buffers22 system.ruby.network.int_link_buffers23 system.ruby.network.int_link_buffers24 system.ruby.network.int_link_buffers25 system.ruby.network.int_link_buffers26 system.ruby.network.int_link_buffers27 system.ruby.network.int_link_buffers28 system.ruby.network.int_link_buffers29 system.ruby.network.int_link_buffers30 system.ruby.network.int_link_buffers31 system.ruby.network.int_link_buffers32 system.ruby.network.int_link_buffers33 system.ruby.network.int_link_buffers34 system.ruby.network.int_link_buffers35 system.ruby.network.int_link_buffers36 system.ruby.network.int_link_buffers37 system.ruby.network.int_link_buffers38 system.ruby.network.int_link_buffers39 system.ruby.network.int_link_buffers40 system.ruby.network.int_link_buffers41 system.ruby.network.int_link_buffers42 system.ruby.network.int_link_buffers43 system.ruby.network.int_link_buffers44 system.ruby.network.int_link_buffers45 system.ruby.network.int_link_buffers46 system.ruby.network.int_link_buffers47 +int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2 system.ruby.network.int_links3 netifs= number_of_virtual_networks=6 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null routers=system.ruby.network.routers0 system.ruby.network.routers1 system.ruby.network.routers2 ruby_system=system.ruby topology=Crossbar @@ -766,32 +807,234 @@ eventq_index=0 ordered=true randomization=false +[system.ruby.network.int_link_buffers24] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers25] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers26] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers27] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers28] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers29] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers30] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers31] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers32] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers33] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers34] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers35] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers36] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers37] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers38] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers39] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers40] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers41] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers42] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers43] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers44] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers45] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers46] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers47] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + [system.ruby.network.int_links0] type=SimpleIntLink bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers2 eventq_index=0 latency=1 link_id=2 -node_a=system.ruby.network.routers0 -node_b=system.ruby.network.routers2 +src_node=system.ruby.network.routers0 +src_outport= weight=1 [system.ruby.network.int_links1] type=SimpleIntLink bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers2 eventq_index=0 latency=1 link_id=3 -node_a=system.ruby.network.routers1 -node_b=system.ruby.network.routers2 +src_node=system.ruby.network.routers1 +src_outport= +weight=1 + +[system.ruby.network.int_links2] +type=SimpleIntLink +bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers0 +eventq_index=0 +latency=1 +link_id=4 +src_node=system.ruby.network.routers2 +src_outport= +weight=1 + +[system.ruby.network.int_links3] +type=SimpleIntLink +bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers1 +eventq_index=0 +latency=1 +link_id=5 +src_node=system.ruby.network.routers2 +src_outport= weight=1 [system.ruby.network.routers0] type=Switch children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17 clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED eventq_index=0 +latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 port_buffers=system.ruby.network.routers0.port_buffers00 system.ruby.network.routers0.port_buffers01 system.ruby.network.routers0.port_buffers02 system.ruby.network.routers0.port_buffers03 system.ruby.network.routers0.port_buffers04 system.ruby.network.routers0.port_buffers05 system.ruby.network.routers0.port_buffers06 system.ruby.network.routers0.port_buffers07 system.ruby.network.routers0.port_buffers08 system.ruby.network.routers0.port_buffers09 system.ruby.network.routers0.port_buffers10 system.ruby.network.routers0.port_buffers11 system.ruby.network.routers0.port_buffers12 system.ruby.network.routers0.port_buffers13 system.ruby.network.routers0.port_buffers14 system.ruby.network.routers0.port_buffers15 system.ruby.network.routers0.port_buffers16 system.ruby.network.routers0.port_buffers17 +power_model=Null router_id=0 virt_nets=6 @@ -925,8 +1168,14 @@ randomization=false type=Switch children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17 clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED eventq_index=0 +latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 port_buffers=system.ruby.network.routers1.port_buffers00 system.ruby.network.routers1.port_buffers01 system.ruby.network.routers1.port_buffers02 system.ruby.network.routers1.port_buffers03 system.ruby.network.routers1.port_buffers04 system.ruby.network.routers1.port_buffers05 system.ruby.network.routers1.port_buffers06 system.ruby.network.routers1.port_buffers07 system.ruby.network.routers1.port_buffers08 system.ruby.network.routers1.port_buffers09 system.ruby.network.routers1.port_buffers10 system.ruby.network.routers1.port_buffers11 system.ruby.network.routers1.port_buffers12 system.ruby.network.routers1.port_buffers13 system.ruby.network.routers1.port_buffers14 system.ruby.network.routers1.port_buffers15 system.ruby.network.routers1.port_buffers16 system.ruby.network.routers1.port_buffers17 +power_model=Null router_id=1 virt_nets=6 @@ -1060,8 +1309,14 @@ randomization=false type=Switch children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17 port_buffers18 port_buffers19 port_buffers20 port_buffers21 port_buffers22 port_buffers23 clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED eventq_index=0 +latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 port_buffers=system.ruby.network.routers2.port_buffers00 system.ruby.network.routers2.port_buffers01 system.ruby.network.routers2.port_buffers02 system.ruby.network.routers2.port_buffers03 system.ruby.network.routers2.port_buffers04 system.ruby.network.routers2.port_buffers05 system.ruby.network.routers2.port_buffers06 system.ruby.network.routers2.port_buffers07 system.ruby.network.routers2.port_buffers08 system.ruby.network.routers2.port_buffers09 system.ruby.network.routers2.port_buffers10 system.ruby.network.routers2.port_buffers11 system.ruby.network.routers2.port_buffers12 system.ruby.network.routers2.port_buffers13 system.ruby.network.routers2.port_buffers14 system.ruby.network.routers2.port_buffers15 system.ruby.network.routers2.port_buffers16 system.ruby.network.routers2.port_buffers17 system.ruby.network.routers2.port_buffers18 system.ruby.network.routers2.port_buffers19 system.ruby.network.routers2.port_buffers20 system.ruby.network.routers2.port_buffers21 system.ruby.network.routers2.port_buffers22 system.ruby.network.routers2.port_buffers23 +power_model=Null router_id=2 virt_nets=6 @@ -1236,9 +1491,14 @@ randomization=false [system.sys_port_proxy] type=RubyPortProxy clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 is_cpu_sequencer=true no_retry_on_stall=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null ruby_system=system.ruby support_data_reqs=true support_inst_reqs=true diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simerr b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simerr index 1c18978fa..63982fce4 100755 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simerr +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simerr @@ -4,9 +4,8 @@ warn: rounding error > tolerance 1.250000 rounded to 1 warn: rounding error > tolerance 1.250000 rounded to 1 -warn: rounding error > tolerance - 1.250000 rounded to 1 warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes) warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files! warn: ignoring syscall sigprocmask(1, ...) diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout index 2cf0cc885..35b481dda 100755 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout @@ -1,13 +1,15 @@ +Redirecting stdout to build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout +Redirecting stderr to build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 21 2016 13:56:08 -gem5 started Jan 21 2016 13:56:42 -gem5 executing on zizzer, pid 39363 -command line: build/ALPHA_MOESI_hammer/gem5.opt -d build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer +gem5 compiled Oct 13 2016 20:24:36 +gem5 started Oct 13 2016 20:24:58 +gem5 executing on e108600-lin, pid 38874 +command line: /work/curdun01/gem5-external.hg/build/ALPHA_MOESI_hammer/gem5.opt -d build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 32936 because target called exit() +Exiting @ tick 35056 because target called exit() diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt index 71e93d920..4d9201d35 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000033 # Number of seconds simulated -sim_ticks 32936 # Number of ticks simulated -final_tick 32936 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000035 # Number of seconds simulated +sim_ticks 35056 # Number of ticks simulated +final_tick 35056 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 91605 # Simulator instruction rate (inst/s) -host_op_rate 91573 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1170024 # Simulator tick rate (ticks/s) -host_mem_usage 453424 # Number of bytes of host memory used -host_seconds 0.03 # Real time elapsed on the host +host_inst_rate 50934 # Simulator instruction rate (inst/s) +host_op_rate 50910 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 692254 # Simulator tick rate (ticks/s) +host_mem_usage 411180 # Number of bytes of host memory used +host_seconds 0.05 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks -system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 32936 # Cumulative time (in ticks) in various power states +system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 35056 # Cumulative time (in ticks) in various power states system.mem_ctrls.bytes_read::ruby.dir_cntrl0 28224 # Number of bytes read from this memory system.mem_ctrls.bytes_read::total 28224 # Number of bytes read from this memory system.mem_ctrls.bytes_written::ruby.dir_cntrl0 5184 # Number of bytes written to this memory @@ -22,12 +22,12 @@ system.mem_ctrls.num_reads::ruby.dir_cntrl0 441 # system.mem_ctrls.num_reads::total 441 # Number of read requests responded to by this memory system.mem_ctrls.num_writes::ruby.dir_cntrl0 81 # Number of write requests responded to by this memory system.mem_ctrls.num_writes::total 81 # Number of write requests responded to by this memory -system.mem_ctrls.bw_read::ruby.dir_cntrl0 856934661 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_read::total 856934661 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::ruby.dir_cntrl0 157396162 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::total 157396162 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_total::ruby.dir_cntrl0 1014330823 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.bw_total::total 1014330823 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_read::ruby.dir_cntrl0 805111821 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 805111821 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::ruby.dir_cntrl0 147877681 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::total 147877681 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::ruby.dir_cntrl0 952989503 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 952989503 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrls.readReqs 441 # Number of read requests accepted system.mem_ctrls.writeReqs 81 # Number of write requests accepted system.mem_ctrls.readBursts 441 # Number of DRAM read bursts, including those serviced by the write queue @@ -74,7 +74,7 @@ system.mem_ctrls.perBankWrBursts::14 0 # Pe system.mem_ctrls.perBankWrBursts::15 1 # Per bank write bursts system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrls.totGap 32872 # Total gap between requests +system.mem_ctrls.totGap 34986 # Total gap between requests system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) @@ -186,17 +186,17 @@ system.mem_ctrls.wrQLenPdf::61 0 # Wh system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see system.mem_ctrls.bytesPerActivate::samples 67 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::mean 358.208955 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::gmean 229.774303 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::stdev 311.560906 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::0-127 18 26.87% 26.87% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::128-255 13 19.40% 46.27% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::256-383 8 11.94% 58.21% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::384-511 7 10.45% 68.66% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::512-639 5 7.46% 76.12% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::640-767 6 8.96% 85.07% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::768-895 2 2.99% 88.06% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::896-1023 4 5.97% 94.03% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 356.298507 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 230.035457 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 306.978482 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 19 28.36% 28.36% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 11 16.42% 44.78% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 10 14.93% 59.70% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 7 10.45% 70.15% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 6 8.96% 79.10% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 4 5.97% 85.07% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 3 4.48% 89.55% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 3 4.48% 94.03% # Bytes accessed per row activation system.mem_ctrls.bytesPerActivate::1024-1151 4 5.97% 100.00% # Bytes accessed per row activation system.mem_ctrls.bytesPerActivate::total 67 # Bytes accessed per row activation system.mem_ctrls.rdPerTurnAround::samples 1 # Reads before turning the bus around for writes @@ -211,57 +211,67 @@ system.mem_ctrls.wrPerTurnAround::gmean 16.000000 # Wr system.mem_ctrls.wrPerTurnAround::stdev nan # Writes before turning the bus around for reads system.mem_ctrls.wrPerTurnAround::16 1 100.00% 100.00% # Writes before turning the bus around for reads system.mem_ctrls.wrPerTurnAround::total 1 # Writes before turning the bus around for reads -system.mem_ctrls.totQLat 2381 # Total ticks spent queuing -system.mem_ctrls.totMemAccLat 9506 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.totQLat 4501 # Total ticks spent queuing +system.mem_ctrls.totMemAccLat 11626 # Total ticks spent from burst creation until serviced by the DRAM system.mem_ctrls.totBusLat 1875 # Total ticks spent in databus transfers -system.mem_ctrls.avgQLat 6.35 # Average queueing delay per DRAM burst +system.mem_ctrls.avgQLat 12.00 # Average queueing delay per DRAM burst system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst -system.mem_ctrls.avgMemAccLat 25.35 # Average memory access latency per DRAM burst -system.mem_ctrls.avgRdBW 728.69 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrls.avgWrBW 31.09 # Average achieved write bandwidth in MiByte/s -system.mem_ctrls.avgRdBWSys 856.93 # Average system read bandwidth in MiByte/s -system.mem_ctrls.avgWrBWSys 157.40 # Average system write bandwidth in MiByte/s +system.mem_ctrls.avgMemAccLat 31.00 # Average memory access latency per DRAM burst +system.mem_ctrls.avgRdBW 684.62 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 29.21 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 805.11 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 147.88 # Average system write bandwidth in MiByte/s system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrls.busUtil 5.94 # Data bus utilization in percentage -system.mem_ctrls.busUtilRead 5.69 # Data bus utilization in percentage for reads -system.mem_ctrls.busUtilWrite 0.24 # Data bus utilization in percentage for writes +system.mem_ctrls.busUtil 5.58 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 5.35 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 0.23 # Data bus utilization in percentage for writes system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing -system.mem_ctrls.avgWrQLen 21.54 # Average write queue length when enqueuing +system.mem_ctrls.avgWrQLen 21.49 # Average write queue length when enqueuing system.mem_ctrls.readRowHits 302 # Number of row buffer hits during reads system.mem_ctrls.writeRowHits 15 # Number of row buffer hits during writes system.mem_ctrls.readRowHitRate 80.53 # Row buffer hit rate for reads system.mem_ctrls.writeRowHitRate 32.61 # Row buffer hit rate for writes -system.mem_ctrls.avgGap 62.97 # Average gap between requests +system.mem_ctrls.avgGap 67.02 # Average gap between requests system.mem_ctrls.pageHitRate 75.30 # Row buffer hit rate, read and write combined -system.mem_ctrls_0.actEnergy 151200 # Energy for activate commands per rank (pJ) -system.mem_ctrls_0.preEnergy 84000 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_0.readEnergy 1859520 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.actEnergy 164220 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 77280 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 1839264 # Energy for read commands per rank (pJ) system.mem_ctrls_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.mem_ctrls_0.refreshEnergy 2034240 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_0.actBackEnergy 21272400 # Energy for active background per rank (pJ) -system.mem_ctrls_0.preBackEnergy 182400 # Energy for precharge background per rank (pJ) -system.mem_ctrls_0.totalEnergy 25583760 # Total energy per rank (pJ) -system.mem_ctrls_0.averagePower 814.665648 # Core power per rank (mW) -system.mem_ctrls_0.memoryStateTime::IDLE 206 # Time in different power states +system.mem_ctrls_0.refreshEnergy 2458560.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 2689032 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 56064 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.actPowerDownEnergy 13011960 # Energy for active power-down per rank (pJ) +system.mem_ctrls_0.prePowerDownEnergy 183552 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls_0.totalEnergy 20479932 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 584.206184 # Core power per rank (mW) +system.mem_ctrls_0.totalIdleTime 29013 # Total Idle time Per DRAM Rank +system.mem_ctrls_0.memoryStateTime::IDLE 34 # Time in different power states system.mem_ctrls_0.memoryStateTime::REF 1040 # Time in different power states -system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT 30172 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrls_1.actEnergy 355320 # Energy for activate commands per rank (pJ) -system.mem_ctrls_1.preEnergy 197400 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_1.readEnergy 2620800 # Energy for read commands per rank (pJ) -system.mem_ctrls_1.writeEnergy 165888 # Energy for write commands per rank (pJ) -system.mem_ctrls_1.refreshEnergy 2034240 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_1.actBackEnergy 20904408 # Energy for active background per rank (pJ) -system.mem_ctrls_1.preBackEnergy 505200 # Energy for precharge background per rank (pJ) -system.mem_ctrls_1.totalEnergy 26783256 # Total energy per rank (pJ) -system.mem_ctrls_1.averagePower 852.861292 # Core power per rank (mW) -system.mem_ctrls_1.memoryStateTime::IDLE 1046 # Time in different power states +system.mem_ctrls_0.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls_0.memoryStateTime::PRE_PDN 478 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 4969 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT_PDN 28535 # Time in different power states +system.mem_ctrls_1.actEnergy 364140 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 181608 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 2444736 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 133632 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.refreshEnergy 2458560.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 3405408 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 211968 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.actPowerDownEnergy 12011952 # Energy for active power-down per rank (pJ) +system.mem_ctrls_1.prePowerDownEnergy 266496 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls_1.totalEnergy 21478500 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 612.691123 # Core power per rank (mW) +system.mem_ctrls_1.totalIdleTime 26306 # Total Idle time Per DRAM Rank +system.mem_ctrls_1.memoryStateTime::IDLE 440 # Time in different power states system.mem_ctrls_1.memoryStateTime::REF 1040 # Time in different power states -system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT 29634 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 32936 # Cumulative time (in ticks) in various power states +system.mem_ctrls_1.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls_1.memoryStateTime::PRE_PDN 694 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 6540 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT_PDN 26342 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 35056 # Cumulative time (in ticks) in various power states system.cpu.clk_domain.clock 1 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -296,8 +306,8 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 32936 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 32936 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 35056 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 35056 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 2577 # Number of instructions committed @@ -316,7 +326,7 @@ system.cpu.num_mem_refs 717 # nu system.cpu.num_load_insts 419 # Number of load instructions system.cpu.num_store_insts 298 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 32936 # Number of busy cycles +system.cpu.num_busy_cycles 35056 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 396 # Number of branches fetched @@ -356,7 +366,7 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 2585 # Class of executed instruction system.ruby.clk_domain.clock 1 # Clock period in ticks -system.ruby.pwrStateResidencyTicks::UNDEFINED 32936 # Cumulative time (in ticks) in various power states +system.ruby.pwrStateResidencyTicks::UNDEFINED 35056 # Cumulative time (in ticks) in various power states system.ruby.outstanding_req_hist_seqr::bucket_size 1 system.ruby.outstanding_req_hist_seqr::max_bucket 9 system.ruby.outstanding_req_hist_seqr::samples 3295 @@ -364,13 +374,13 @@ system.ruby.outstanding_req_hist_seqr::mean 1 system.ruby.outstanding_req_hist_seqr::gmean 1 system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 3295 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.outstanding_req_hist_seqr::total 3295 -system.ruby.latency_hist_seqr::bucket_size 64 -system.ruby.latency_hist_seqr::max_bucket 639 +system.ruby.latency_hist_seqr::bucket_size 32 +system.ruby.latency_hist_seqr::max_bucket 319 system.ruby.latency_hist_seqr::samples 3294 -system.ruby.latency_hist_seqr::mean 8.998786 -system.ruby.latency_hist_seqr::gmean 1.800750 -system.ruby.latency_hist_seqr::stdev 22.386902 -system.ruby.latency_hist_seqr | 3204 97.27% 97.27% | 86 2.61% 99.88% | 0 0.00% 99.88% | 0 0.00% 99.88% | 2 0.06% 99.94% | 2 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.latency_hist_seqr::mean 9.642380 +system.ruby.latency_hist_seqr::gmean 1.819734 +system.ruby.latency_hist_seqr::stdev 23.663336 +system.ruby.latency_hist_seqr | 2910 88.34% 88.34% | 293 8.89% 97.24% | 85 2.58% 99.82% | 2 0.06% 99.88% | 0 0.00% 99.88% | 0 0.00% 99.88% | 0 0.00% 99.88% | 0 0.00% 99.88% | 0 0.00% 99.88% | 4 0.12% 100.00% system.ruby.latency_hist_seqr::total 3294 system.ruby.hit_latency_hist_seqr::bucket_size 2 system.ruby.hit_latency_hist_seqr::max_bucket 19 @@ -380,19 +390,19 @@ system.ruby.hit_latency_hist_seqr::gmean 1.059708 system.ruby.hit_latency_hist_seqr::stdev 1.536503 system.ruby.hit_latency_hist_seqr | 2784 97.58% 97.58% | 0 0.00% 97.58% | 0 0.00% 97.58% | 0 0.00% 97.58% | 0 0.00% 97.58% | 69 2.42% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.hit_latency_hist_seqr::total 2853 -system.ruby.miss_latency_hist_seqr::bucket_size 64 -system.ruby.miss_latency_hist_seqr::max_bucket 639 +system.ruby.miss_latency_hist_seqr::bucket_size 32 +system.ruby.miss_latency_hist_seqr::max_bucket 319 system.ruby.miss_latency_hist_seqr::samples 441 -system.ruby.miss_latency_hist_seqr::mean 59.181406 -system.ruby.miss_latency_hist_seqr::gmean 55.608631 -system.ruby.miss_latency_hist_seqr::stdev 28.659343 -system.ruby.miss_latency_hist_seqr | 351 79.59% 79.59% | 86 19.50% 99.09% | 0 0.00% 99.09% | 0 0.00% 99.09% | 2 0.45% 99.55% | 2 0.45% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.miss_latency_hist_seqr::mean 63.988662 +system.ruby.miss_latency_hist_seqr::gmean 60.139666 +system.ruby.miss_latency_hist_seqr::stdev 27.525151 +system.ruby.miss_latency_hist_seqr | 57 12.93% 12.93% | 293 66.44% 79.37% | 85 19.27% 98.64% | 2 0.45% 99.09% | 0 0.00% 99.09% | 0 0.00% 99.09% | 0 0.00% 99.09% | 0 0.00% 99.09% | 0 0.00% 99.09% | 4 0.91% 100.00% system.ruby.miss_latency_hist_seqr::total 441 system.ruby.Directory.incomplete_times_seqr 440 system.ruby.dir_cntrl0.probeFilter.demand_hits 0 # Number of cache demand hits system.ruby.dir_cntrl0.probeFilter.demand_misses 0 # Number of cache demand misses system.ruby.dir_cntrl0.probeFilter.demand_accesses 0 # Number of cache demand accesses -system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 32936 # Cumulative time (in ticks) in various power states +system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 35056 # Cumulative time (in ticks) in various power states system.ruby.l1_cntrl0.L1Dcache.demand_hits 469 # Number of cache demand hits system.ruby.l1_cntrl0.L1Dcache.demand_misses 240 # Number of cache demand misses system.ruby.l1_cntrl0.L1Dcache.demand_accesses 709 # Number of cache demand accesses @@ -402,12 +412,12 @@ system.ruby.l1_cntrl0.L1Icache.demand_accesses 2585 system.ruby.l1_cntrl0.L2cache.demand_hits 69 # Number of cache demand hits system.ruby.l1_cntrl0.L2cache.demand_misses 441 # Number of cache demand misses system.ruby.l1_cntrl0.L2cache.demand_accesses 510 # Number of cache demand accesses -system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 32936 # Cumulative time (in ticks) in various power states -system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 32936 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 35056 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 35056 # Cumulative time (in ticks) in various power states system.ruby.l1_cntrl0.fully_busy_cycles 5 # cycles for which number of transistions == max transitions system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 32936 # Cumulative time (in ticks) in various power states -system.ruby.network.routers0.percent_links_utilized 5.141031 +system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 35056 # Cumulative time (in ticks) in various power states +system.ruby.network.routers0.percent_links_utilized 4.830129 system.ruby.network.routers0.msg_count.Request_Control::2 441 system.ruby.network.routers0.msg_count.Response_Data::4 441 system.ruby.network.routers0.msg_count.Writeback_Data::5 81 @@ -422,8 +432,8 @@ system.ruby.network.routers0.msg_bytes.Writeback_Control::2 3400 system.ruby.network.routers0.msg_bytes.Writeback_Control::3 3400 system.ruby.network.routers0.msg_bytes.Writeback_Control::5 2752 system.ruby.network.routers0.msg_bytes.Unblock_Control::5 3520 -system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 32936 # Cumulative time (in ticks) in various power states -system.ruby.network.routers1.percent_links_utilized 5.141031 +system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 35056 # Cumulative time (in ticks) in various power states +system.ruby.network.routers1.percent_links_utilized 4.830129 system.ruby.network.routers1.msg_count.Request_Control::2 441 system.ruby.network.routers1.msg_count.Response_Data::4 441 system.ruby.network.routers1.msg_count.Writeback_Data::5 81 @@ -438,8 +448,8 @@ system.ruby.network.routers1.msg_bytes.Writeback_Control::2 3400 system.ruby.network.routers1.msg_bytes.Writeback_Control::3 3400 system.ruby.network.routers1.msg_bytes.Writeback_Control::5 2752 system.ruby.network.routers1.msg_bytes.Unblock_Control::5 3520 -system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 32936 # Cumulative time (in ticks) in various power states -system.ruby.network.routers2.percent_links_utilized 5.141031 +system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 35056 # Cumulative time (in ticks) in various power states +system.ruby.network.routers2.percent_links_utilized 4.830129 system.ruby.network.routers2.msg_count.Request_Control::2 441 system.ruby.network.routers2.msg_count.Response_Data::4 441 system.ruby.network.routers2.msg_count.Writeback_Data::5 81 @@ -454,7 +464,7 @@ system.ruby.network.routers2.msg_bytes.Writeback_Control::2 3400 system.ruby.network.routers2.msg_bytes.Writeback_Control::3 3400 system.ruby.network.routers2.msg_bytes.Writeback_Control::5 2752 system.ruby.network.routers2.msg_bytes.Unblock_Control::5 3520 -system.ruby.network.pwrStateResidencyTicks::UNDEFINED 32936 # Cumulative time (in ticks) in various power states +system.ruby.network.pwrStateResidencyTicks::UNDEFINED 35056 # Cumulative time (in ticks) in various power states system.ruby.network.msg_count.Request_Control 1323 system.ruby.network.msg_count.Response_Data 1323 system.ruby.network.msg_count.Writeback_Data 243 @@ -465,13 +475,13 @@ system.ruby.network.msg_byte.Response_Data 95256 system.ruby.network.msg_byte.Writeback_Data 17496 system.ruby.network.msg_byte.Writeback_Control 28656 system.ruby.network.msg_byte.Unblock_Control 10560 -system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 32936 # Cumulative time (in ticks) in various power states -system.ruby.network.routers0.throttle0.link_utilization 6.670513 +system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 35056 # Cumulative time (in ticks) in various power states +system.ruby.network.routers0.throttle0.link_utilization 6.267115 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 441 system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 425 system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 31752 system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 3400 -system.ruby.network.routers0.throttle1.link_utilization 3.611550 +system.ruby.network.routers0.throttle1.link_utilization 3.393142 system.ruby.network.routers0.throttle1.msg_count.Request_Control::2 441 system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::5 81 system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::2 425 @@ -482,7 +492,7 @@ system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::5 5832 system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::2 3400 system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::5 2752 system.ruby.network.routers0.throttle1.msg_bytes.Unblock_Control::5 3520 -system.ruby.network.routers1.throttle0.link_utilization 3.611550 +system.ruby.network.routers1.throttle0.link_utilization 3.393142 system.ruby.network.routers1.throttle0.msg_count.Request_Control::2 441 system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::5 81 system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::2 425 @@ -493,17 +503,17 @@ system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::5 5832 system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::2 3400 system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::5 2752 system.ruby.network.routers1.throttle0.msg_bytes.Unblock_Control::5 3520 -system.ruby.network.routers1.throttle1.link_utilization 6.670513 +system.ruby.network.routers1.throttle1.link_utilization 6.267115 system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 441 system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 425 system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 31752 system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 3400 -system.ruby.network.routers2.throttle0.link_utilization 6.670513 +system.ruby.network.routers2.throttle0.link_utilization 6.267115 system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 441 system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 425 system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 31752 system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 3400 -system.ruby.network.routers2.throttle1.link_utilization 3.611550 +system.ruby.network.routers2.throttle1.link_utilization 3.393142 system.ruby.network.routers2.throttle1.msg_count.Request_Control::2 441 system.ruby.network.routers2.throttle1.msg_count.Writeback_Data::5 81 system.ruby.network.routers2.throttle1.msg_count.Writeback_Control::2 425 @@ -517,10 +527,10 @@ system.ruby.network.routers2.throttle1.msg_bytes.Unblock_Control::5 3520 system.ruby.LD.latency_hist_seqr::bucket_size 16 system.ruby.LD.latency_hist_seqr::max_bucket 159 system.ruby.LD.latency_hist_seqr::samples 415 -system.ruby.LD.latency_hist_seqr::mean 19.850602 -system.ruby.LD.latency_hist_seqr::gmean 4.833066 -system.ruby.LD.latency_hist_seqr::stdev 26.151303 -system.ruby.LD.latency_hist_seqr | 269 64.82% 64.82% | 42 10.12% 74.94% | 3 0.72% 75.66% | 70 16.87% 92.53% | 20 4.82% 97.35% | 11 2.65% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.latency_hist_seqr::mean 21.354217 +system.ruby.LD.latency_hist_seqr::gmean 4.945859 +system.ruby.LD.latency_hist_seqr::stdev 28.670834 +system.ruby.LD.latency_hist_seqr | 269 64.82% 64.82% | 42 10.12% 74.94% | 3 0.72% 75.66% | 69 16.63% 92.29% | 18 4.34% 96.63% | 14 3.37% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.latency_hist_seqr::total 415 system.ruby.LD.hit_latency_hist_seqr::bucket_size 2 system.ruby.LD.hit_latency_hist_seqr::max_bucket 19 @@ -533,18 +543,18 @@ system.ruby.LD.hit_latency_hist_seqr::total 269 system.ruby.LD.miss_latency_hist_seqr::bucket_size 16 system.ruby.LD.miss_latency_hist_seqr::max_bucket 159 system.ruby.LD.miss_latency_hist_seqr::samples 146 -system.ruby.LD.miss_latency_hist_seqr::mean 52.116438 -system.ruby.LD.miss_latency_hist_seqr::gmean 48.763829 -system.ruby.LD.miss_latency_hist_seqr::stdev 17.717519 -system.ruby.LD.miss_latency_hist_seqr | 0 0.00% 0.00% | 42 28.77% 28.77% | 3 2.05% 30.82% | 70 47.95% 78.77% | 20 13.70% 92.47% | 11 7.53% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.miss_latency_hist_seqr::mean 56.390411 +system.ruby.LD.miss_latency_hist_seqr::gmean 52.068669 +system.ruby.LD.miss_latency_hist_seqr::stdev 20.461022 +system.ruby.LD.miss_latency_hist_seqr | 0 0.00% 0.00% | 42 28.77% 28.77% | 3 2.05% 30.82% | 69 47.26% 78.08% | 18 12.33% 90.41% | 14 9.59% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.miss_latency_hist_seqr::total 146 -system.ruby.ST.latency_hist_seqr::bucket_size 32 -system.ruby.ST.latency_hist_seqr::max_bucket 319 +system.ruby.ST.latency_hist_seqr::bucket_size 8 +system.ruby.ST.latency_hist_seqr::max_bucket 79 system.ruby.ST.latency_hist_seqr::samples 294 -system.ruby.ST.latency_hist_seqr::mean 10.064626 -system.ruby.ST.latency_hist_seqr::gmean 2.035894 -system.ruby.ST.latency_hist_seqr::stdev 25.936505 -system.ruby.ST.latency_hist_seqr | 262 89.12% 89.12% | 22 7.48% 96.60% | 9 3.06% 99.66% | 0 0.00% 99.66% | 0 0.00% 99.66% | 0 0.00% 99.66% | 0 0.00% 99.66% | 0 0.00% 99.66% | 0 0.00% 99.66% | 1 0.34% 100.00% +system.ruby.ST.latency_hist_seqr::mean 9.778912 +system.ruby.ST.latency_hist_seqr::gmean 2.043604 +system.ruby.ST.latency_hist_seqr::stdev 20.538869 +system.ruby.ST.latency_hist_seqr | 236 80.27% 80.27% | 11 3.74% 84.01% | 0 0.00% 84.01% | 15 5.10% 89.12% | 0 0.00% 89.12% | 0 0.00% 89.12% | 0 0.00% 89.12% | 22 7.48% 96.60% | 5 1.70% 98.30% | 5 1.70% 100.00% system.ruby.ST.latency_hist_seqr::total 294 system.ruby.ST.hit_latency_hist_seqr::bucket_size 2 system.ruby.ST.hit_latency_hist_seqr::max_bucket 19 @@ -554,21 +564,21 @@ system.ruby.ST.hit_latency_hist_seqr::gmean 1.112699 system.ruby.ST.hit_latency_hist_seqr::stdev 2.066980 system.ruby.ST.hit_latency_hist_seqr | 236 95.55% 95.55% | 0 0.00% 95.55% | 0 0.00% 95.55% | 0 0.00% 95.55% | 0 0.00% 95.55% | 11 4.45% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ST.hit_latency_hist_seqr::total 247 -system.ruby.ST.miss_latency_hist_seqr::bucket_size 32 -system.ruby.ST.miss_latency_hist_seqr::max_bucket 319 +system.ruby.ST.miss_latency_hist_seqr::bucket_size 8 +system.ruby.ST.miss_latency_hist_seqr::max_bucket 79 system.ruby.ST.miss_latency_hist_seqr::samples 47 -system.ruby.ST.miss_latency_hist_seqr::mean 55.361702 -system.ruby.ST.miss_latency_hist_seqr::gmean 48.711518 -system.ruby.ST.miss_latency_hist_seqr::stdev 42.031265 -system.ruby.ST.miss_latency_hist_seqr | 15 31.91% 31.91% | 22 46.81% 78.72% | 9 19.15% 97.87% | 0 0.00% 97.87% | 0 0.00% 97.87% | 0 0.00% 97.87% | 0 0.00% 97.87% | 0 0.00% 97.87% | 0 0.00% 97.87% | 1 2.13% 100.00% +system.ruby.ST.miss_latency_hist_seqr::mean 53.574468 +system.ruby.ST.miss_latency_hist_seqr::gmean 49.876949 +system.ruby.ST.miss_latency_hist_seqr::stdev 18.206240 +system.ruby.ST.miss_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 15 31.91% 31.91% | 0 0.00% 31.91% | 0 0.00% 31.91% | 0 0.00% 31.91% | 22 46.81% 78.72% | 5 10.64% 89.36% | 5 10.64% 100.00% system.ruby.ST.miss_latency_hist_seqr::total 47 -system.ruby.IFETCH.latency_hist_seqr::bucket_size 64 -system.ruby.IFETCH.latency_hist_seqr::max_bucket 639 +system.ruby.IFETCH.latency_hist_seqr::bucket_size 32 +system.ruby.IFETCH.latency_hist_seqr::max_bucket 319 system.ruby.IFETCH.latency_hist_seqr::samples 2585 -system.ruby.IFETCH.latency_hist_seqr::mean 7.135397 -system.ruby.IFETCH.latency_hist_seqr::gmean 1.515500 -system.ruby.IFETCH.latency_hist_seqr::stdev 20.744191 -system.ruby.IFETCH.latency_hist_seqr | 2536 98.10% 98.10% | 46 1.78% 99.88% | 0 0.00% 99.88% | 0 0.00% 99.88% | 1 0.04% 99.92% | 2 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.latency_hist_seqr::mean 7.746615 +system.ruby.IFETCH.latency_hist_seqr::gmean 1.529553 +system.ruby.IFETCH.latency_hist_seqr::stdev 22.548460 +system.ruby.IFETCH.latency_hist_seqr | 2337 90.41% 90.41% | 199 7.70% 98.10% | 43 1.66% 99.77% | 2 0.08% 99.85% | 0 0.00% 99.85% | 0 0.00% 99.85% | 0 0.00% 99.85% | 0 0.00% 99.85% | 0 0.00% 99.85% | 4 0.15% 100.00% system.ruby.IFETCH.latency_hist_seqr::total 2585 system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 2 system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 19 @@ -578,13 +588,13 @@ system.ruby.IFETCH.hit_latency_hist_seqr::gmean 1.022830 system.ruby.IFETCH.hit_latency_hist_seqr::stdev 0.965875 system.ruby.IFETCH.hit_latency_hist_seqr | 2315 99.06% 99.06% | 0 0.00% 99.06% | 0 0.00% 99.06% | 0 0.00% 99.06% | 0 0.00% 99.06% | 22 0.94% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.hit_latency_hist_seqr::total 2337 -system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 64 -system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 639 +system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 32 +system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 319 system.ruby.IFETCH.miss_latency_hist_seqr::samples 248 -system.ruby.IFETCH.miss_latency_hist_seqr::mean 64.064516 -system.ruby.IFETCH.miss_latency_hist_seqr::gmean 61.606137 -system.ruby.IFETCH.miss_latency_hist_seqr::stdev 29.893804 -system.ruby.IFETCH.miss_latency_hist_seqr | 199 80.24% 80.24% | 46 18.55% 98.79% | 0 0.00% 98.79% | 0 0.00% 98.79% | 1 0.40% 99.19% | 2 0.81% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.miss_latency_hist_seqr::mean 70.435484 +system.ruby.IFETCH.miss_latency_hist_seqr::gmean 67.827440 +system.ruby.IFETCH.miss_latency_hist_seqr::stdev 30.751253 +system.ruby.IFETCH.miss_latency_hist_seqr | 0 0.00% 0.00% | 199 80.24% 80.24% | 43 17.34% 97.58% | 2 0.81% 98.39% | 0 0.00% 98.39% | 0 0.00% 98.39% | 0 0.00% 98.39% | 0 0.00% 98.39% | 0 0.00% 98.39% | 4 1.61% 100.00% system.ruby.IFETCH.miss_latency_hist_seqr::total 248 system.ruby.L1Cache.hit_mach_latency_hist_seqr::bucket_size 1 system.ruby.L1Cache.hit_mach_latency_hist_seqr::max_bucket 9 @@ -600,13 +610,13 @@ system.ruby.L2Cache.hit_mach_latency_hist_seqr::mean 11 system.ruby.L2Cache.hit_mach_latency_hist_seqr::gmean 11.000000 system.ruby.L2Cache.hit_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 69 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.L2Cache.hit_mach_latency_hist_seqr::total 69 -system.ruby.Directory.miss_mach_latency_hist_seqr::bucket_size 64 -system.ruby.Directory.miss_mach_latency_hist_seqr::max_bucket 639 +system.ruby.Directory.miss_mach_latency_hist_seqr::bucket_size 32 +system.ruby.Directory.miss_mach_latency_hist_seqr::max_bucket 319 system.ruby.Directory.miss_mach_latency_hist_seqr::samples 441 -system.ruby.Directory.miss_mach_latency_hist_seqr::mean 59.181406 -system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 55.608631 -system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 28.659343 -system.ruby.Directory.miss_mach_latency_hist_seqr | 351 79.59% 79.59% | 86 19.50% 99.09% | 0 0.00% 99.09% | 0 0.00% 99.09% | 2 0.45% 99.55% | 2 0.45% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_mach_latency_hist_seqr::mean 63.988662 +system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 60.139666 +system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 27.525151 +system.ruby.Directory.miss_mach_latency_hist_seqr | 57 12.93% 12.93% | 293 66.44% 79.37% | 85 19.27% 98.64% | 2 0.45% 99.09% | 0 0.00% 99.09% | 0 0.00% 99.09% | 0 0.00% 99.09% | 0 0.00% 99.09% | 0 0.00% 99.09% | 4 0.91% 100.00% system.ruby.Directory.miss_mach_latency_hist_seqr::total 441 system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::bucket_size 1 system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::max_bucket 9 @@ -651,10 +661,10 @@ system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::total 36 system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size 16 system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket 159 system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples 146 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 52.116438 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 48.763829 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 17.717519 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 42 28.77% 28.77% | 3 2.05% 30.82% | 70 47.95% 78.77% | 20 13.70% 92.47% | 11 7.53% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 56.390411 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 52.068669 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 20.461022 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 42 28.77% 28.77% | 3 2.05% 30.82% | 69 47.26% 78.08% | 18 12.33% 90.41% | 14 9.59% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total 146 system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::bucket_size 1 system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::max_bucket 9 @@ -670,13 +680,13 @@ system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::mean 11 system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::gmean 11.000000 system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 11 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::total 11 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size 32 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket 319 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size 8 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket 79 system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::samples 47 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 55.361702 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 48.711518 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 42.031265 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 15 31.91% 31.91% | 22 46.81% 78.72% | 9 19.15% 97.87% | 0 0.00% 97.87% | 0 0.00% 97.87% | 0 0.00% 97.87% | 0 0.00% 97.87% | 0 0.00% 97.87% | 0 0.00% 97.87% | 1 2.13% 100.00% +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 53.574468 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 49.876949 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 18.206240 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 15 31.91% 31.91% | 0 0.00% 31.91% | 0 0.00% 31.91% | 0 0.00% 31.91% | 22 46.81% 78.72% | 5 10.64% 89.36% | 5 10.64% 100.00% system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total 47 system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::bucket_size 1 system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::max_bucket 9 @@ -692,13 +702,13 @@ system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::mean 11 system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::gmean 11.000000 system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 22 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::total 22 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::bucket_size 32 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::max_bucket 319 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::samples 248 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 64.064516 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 61.606137 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 29.893804 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 199 80.24% 80.24% | 46 18.55% 98.79% | 0 0.00% 98.79% | 0 0.00% 98.79% | 1 0.40% 99.19% | 2 0.81% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 70.435484 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 67.827440 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 30.751253 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 199 80.24% 80.24% | 43 17.34% 97.58% | 2 0.81% 98.39% | 0 0.00% 98.39% | 0 0.00% 98.39% | 0 0.00% 98.39% | 0 0.00% 98.39% | 0 0.00% 98.39% | 4 1.61% 100.00% system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::total 248 system.ruby.Directory_Controller.GETX 51 0.00% 0.00% system.ruby.Directory_Controller.GETS 410 0.00% 0.00% diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini index 538bb6cd3..7199cc5b0 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini @@ -14,6 +14,7 @@ children=clk_domain cpu dvfs_handler mem_ctrls ruby sys_port_proxy voltage_domai boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 exit_on_work_items=false init_param=0 @@ -22,11 +23,15 @@ kernel_addr_check=true load_addr_mask=1099511627775 load_offset=0 mem_mode=timing -mem_ranges=0:268435455 +mem_ranges=0:268435455:0:0:0:0 memories=system.mem_ctrls mmap_using_noreserve=false multi_thread=false num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null readfile= symbolfile= thermal_components= @@ -55,6 +60,7 @@ branchPred=Null checker=Null clk_domain=system.cpu.clk_domain cpu_id=0 +default_p_state=UNDEFINED do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true @@ -70,6 +76,10 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null profile=0 progress_interval=0 simpoint_start_insts= @@ -122,7 +132,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello +executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/alpha/tru64/hello gid=100 input=cin kvmInSE=false @@ -145,27 +155,27 @@ transition_latency=100000 [system.mem_ctrls] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -177,6 +187,7 @@ burst_length=8 channels=1 clk_domain=system.clk_domain conf_table_reported=true +default_p_state=UNDEFINED device_bus_width=8 device_rowbuffer_size=1024 device_size=536870912 @@ -184,12 +195,17 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 page_policy=open_adaptive -range=0:268435455 +power_model=Null +range=0:268435455:5:19:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10 @@ -211,9 +227,9 @@ tRTW=3 tWR=15 tWTR=8 tXAW=30 -tXP=0 +tXP=6 tXPDLL=0 -tXS=0 +tXS=270 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 @@ -227,12 +243,17 @@ access_backing_store=false all_instructions=false block_size_bytes=64 clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED eventq_index=0 hot_lines=false memory_size_bits=48 num_of_sequencers=1 number_of_virtual_networks=5 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 phys_mem=Null +power_model=Null randomization=false [system.ruby.clk_domain] @@ -249,6 +270,7 @@ children=directory dmaRequestToDir dmaResponseFromDir forwardFromDir requestToDi buffer_size=0 clk_domain=system.ruby.clk_domain cluster_id=0 +default_p_state=UNDEFINED directory=system.ruby.dir_cntrl0.directory directory_latency=12 dmaRequestToDir=system.ruby.dir_cntrl0.dmaRequestToDir @@ -256,6 +278,10 @@ dmaResponseFromDir=system.ruby.dir_cntrl0.dmaResponseFromDir eventq_index=0 forwardFromDir=system.ruby.dir_cntrl0.forwardFromDir number_of_TBEs=256 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null recycle_latency=10 requestToDir=system.ruby.dir_cntrl0.requestToDir responseFromDir=system.ruby.dir_cntrl0.responseFromDir @@ -329,11 +355,16 @@ cacheMemory=system.ruby.l1_cntrl0.cacheMemory cache_response_latency=12 clk_domain=system.cpu.clk_domain cluster_id=0 +default_p_state=UNDEFINED eventq_index=0 forwardToCache=system.ruby.l1_cntrl0.forwardToCache issue_latency=2 mandatoryQueue=system.ruby.l1_cntrl0.mandatoryQueue number_of_TBEs=256 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null recycle_latency=10 requestFromCache=system.ruby.l1_cntrl0.requestFromCache responseFromCache=system.ruby.l1_cntrl0.responseFromCache @@ -415,17 +446,22 @@ coreid=99 dcache=system.ruby.l1_cntrl0.cacheMemory dcache_hit_latency=1 deadlock_threshold=500000 +default_p_state=UNDEFINED eventq_index=0 +garnet_standalone=false icache=system.ruby.l1_cntrl0.cacheMemory icache_hit_latency=1 is_cpu_sequencer=true max_outstanding_requests=16 no_retry_on_stall=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null ruby_system=system.ruby support_data_reqs=true support_inst_reqs=true system=system -using_network_tester=false using_ruby_tester=false version=0 slave=system.cpu.icache_port system.cpu.dcache_port @@ -438,18 +474,23 @@ eventq_index=0 [system.ruby.network] type=SimpleNetwork -children=ext_links0 ext_links1 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_links0 int_links1 routers0 routers1 routers2 +children=ext_links0 ext_links1 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_link_buffers20 int_link_buffers21 int_link_buffers22 int_link_buffers23 int_link_buffers24 int_link_buffers25 int_link_buffers26 int_link_buffers27 int_link_buffers28 int_link_buffers29 int_link_buffers30 int_link_buffers31 int_link_buffers32 int_link_buffers33 int_link_buffers34 int_link_buffers35 int_link_buffers36 int_link_buffers37 int_link_buffers38 int_link_buffers39 int_links0 int_links1 int_links2 int_links3 routers0 routers1 routers2 adaptive_routing=false buffer_size=0 clk_domain=system.ruby.clk_domain control_msg_size=8 +default_p_state=UNDEFINED endpoint_bandwidth=1000 eventq_index=0 ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1 -int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19 -int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 +int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19 system.ruby.network.int_link_buffers20 system.ruby.network.int_link_buffers21 system.ruby.network.int_link_buffers22 system.ruby.network.int_link_buffers23 system.ruby.network.int_link_buffers24 system.ruby.network.int_link_buffers25 system.ruby.network.int_link_buffers26 system.ruby.network.int_link_buffers27 system.ruby.network.int_link_buffers28 system.ruby.network.int_link_buffers29 system.ruby.network.int_link_buffers30 system.ruby.network.int_link_buffers31 system.ruby.network.int_link_buffers32 system.ruby.network.int_link_buffers33 system.ruby.network.int_link_buffers34 system.ruby.network.int_link_buffers35 system.ruby.network.int_link_buffers36 system.ruby.network.int_link_buffers37 system.ruby.network.int_link_buffers38 system.ruby.network.int_link_buffers39 +int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2 system.ruby.network.int_links3 netifs= number_of_virtual_networks=5 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null routers=system.ruby.network.routers0 system.ruby.network.routers1 system.ruby.network.routers2 ruby_system=system.ruby topology=Crossbar @@ -616,32 +657,206 @@ eventq_index=0 ordered=true randomization=false +[system.ruby.network.int_link_buffers20] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers21] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers22] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers23] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers24] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers25] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers26] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers27] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers28] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers29] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers30] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers31] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers32] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers33] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers34] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers35] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers36] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers37] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers38] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers39] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + [system.ruby.network.int_links0] type=SimpleIntLink bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers2 eventq_index=0 latency=1 link_id=2 -node_a=system.ruby.network.routers0 -node_b=system.ruby.network.routers2 +src_node=system.ruby.network.routers0 +src_outport= weight=1 [system.ruby.network.int_links1] type=SimpleIntLink bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers2 eventq_index=0 latency=1 link_id=3 -node_a=system.ruby.network.routers1 -node_b=system.ruby.network.routers2 +src_node=system.ruby.network.routers1 +src_outport= +weight=1 + +[system.ruby.network.int_links2] +type=SimpleIntLink +bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers0 +eventq_index=0 +latency=1 +link_id=4 +src_node=system.ruby.network.routers2 +src_outport= +weight=1 + +[system.ruby.network.int_links3] +type=SimpleIntLink +bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers1 +eventq_index=0 +latency=1 +link_id=5 +src_node=system.ruby.network.routers2 +src_outport= weight=1 [system.ruby.network.routers0] type=Switch children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED eventq_index=0 +latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 port_buffers=system.ruby.network.routers0.port_buffers00 system.ruby.network.routers0.port_buffers01 system.ruby.network.routers0.port_buffers02 system.ruby.network.routers0.port_buffers03 system.ruby.network.routers0.port_buffers04 system.ruby.network.routers0.port_buffers05 system.ruby.network.routers0.port_buffers06 system.ruby.network.routers0.port_buffers07 system.ruby.network.routers0.port_buffers08 system.ruby.network.routers0.port_buffers09 system.ruby.network.routers0.port_buffers10 system.ruby.network.routers0.port_buffers11 system.ruby.network.routers0.port_buffers12 system.ruby.network.routers0.port_buffers13 system.ruby.network.routers0.port_buffers14 +power_model=Null router_id=0 virt_nets=5 @@ -754,8 +969,14 @@ randomization=false type=Switch children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED eventq_index=0 +latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 port_buffers=system.ruby.network.routers1.port_buffers00 system.ruby.network.routers1.port_buffers01 system.ruby.network.routers1.port_buffers02 system.ruby.network.routers1.port_buffers03 system.ruby.network.routers1.port_buffers04 system.ruby.network.routers1.port_buffers05 system.ruby.network.routers1.port_buffers06 system.ruby.network.routers1.port_buffers07 system.ruby.network.routers1.port_buffers08 system.ruby.network.routers1.port_buffers09 system.ruby.network.routers1.port_buffers10 system.ruby.network.routers1.port_buffers11 system.ruby.network.routers1.port_buffers12 system.ruby.network.routers1.port_buffers13 system.ruby.network.routers1.port_buffers14 +power_model=Null router_id=1 virt_nets=5 @@ -868,8 +1089,14 @@ randomization=false type=Switch children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17 port_buffers18 port_buffers19 clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED eventq_index=0 +latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 port_buffers=system.ruby.network.routers2.port_buffers00 system.ruby.network.routers2.port_buffers01 system.ruby.network.routers2.port_buffers02 system.ruby.network.routers2.port_buffers03 system.ruby.network.routers2.port_buffers04 system.ruby.network.routers2.port_buffers05 system.ruby.network.routers2.port_buffers06 system.ruby.network.routers2.port_buffers07 system.ruby.network.routers2.port_buffers08 system.ruby.network.routers2.port_buffers09 system.ruby.network.routers2.port_buffers10 system.ruby.network.routers2.port_buffers11 system.ruby.network.routers2.port_buffers12 system.ruby.network.routers2.port_buffers13 system.ruby.network.routers2.port_buffers14 system.ruby.network.routers2.port_buffers15 system.ruby.network.routers2.port_buffers16 system.ruby.network.routers2.port_buffers17 system.ruby.network.routers2.port_buffers18 system.ruby.network.routers2.port_buffers19 +power_model=Null router_id=2 virt_nets=5 @@ -1016,9 +1243,14 @@ randomization=false [system.sys_port_proxy] type=RubyPortProxy clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 is_cpu_sequencer=true no_retry_on_stall=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null ruby_system=system.ruby support_data_reqs=true support_inst_reqs=true diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simerr b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simerr index 1c18978fa..63982fce4 100755 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simerr +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simerr @@ -4,9 +4,8 @@ warn: rounding error > tolerance 1.250000 rounded to 1 warn: rounding error > tolerance 1.250000 rounded to 1 -warn: rounding error > tolerance - 1.250000 rounded to 1 warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes) warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files! warn: ignoring syscall sigprocmask(1, ...) diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simout index 98025cd1e..d4c6f5ba8 100755 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simout +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simout @@ -1,13 +1,15 @@ +Redirecting stdout to build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby/simout +Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 21 2016 13:49:21 -gem5 started Jan 21 2016 13:50:26 -gem5 executing on zizzer, pid 34072 -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby +gem5 compiled Oct 11 2016 00:00:58 +gem5 started Oct 13 2016 20:19:46 +gem5 executing on e108600-lin, pid 28078 +command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/alpha/tru64/simple-timing-ruby Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 41659 because target called exit() +Exiting @ tick 43520 because target called exit() diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt index f97a14626..535942f10 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000042 # Number of seconds simulated -sim_ticks 41659 # Number of ticks simulated -final_tick 41659 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000044 # Number of seconds simulated +sim_ticks 43520 # Number of ticks simulated +final_tick 43520 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 54027 # Simulator instruction rate (inst/s) -host_op_rate 54016 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 873053 # Simulator tick rate (ticks/s) -host_mem_usage 453224 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host +host_inst_rate 93431 # Simulator instruction rate (inst/s) +host_op_rate 93392 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1576605 # Simulator tick rate (ticks/s) +host_mem_usage 411000 # Number of bytes of host memory used +host_seconds 0.03 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks -system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 41659 # Cumulative time (in ticks) in various power states +system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 43520 # Cumulative time (in ticks) in various power states system.mem_ctrls.bytes_read::ruby.dir_cntrl0 40064 # Number of bytes read from this memory system.mem_ctrls.bytes_read::total 40064 # Number of bytes read from this memory system.mem_ctrls.bytes_written::ruby.dir_cntrl0 39808 # Number of bytes written to this memory @@ -22,59 +22,59 @@ system.mem_ctrls.num_reads::ruby.dir_cntrl0 626 # system.mem_ctrls.num_reads::total 626 # Number of read requests responded to by this memory system.mem_ctrls.num_writes::ruby.dir_cntrl0 622 # Number of write requests responded to by this memory system.mem_ctrls.num_writes::total 622 # Number of write requests responded to by this memory -system.mem_ctrls.bw_read::ruby.dir_cntrl0 961712955 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_read::total 961712955 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::ruby.dir_cntrl0 955567824 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::total 955567824 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_total::ruby.dir_cntrl0 1917280780 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.bw_total::total 1917280780 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_read::ruby.dir_cntrl0 920588235 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 920588235 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::ruby.dir_cntrl0 914705882 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::total 914705882 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::ruby.dir_cntrl0 1835294118 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 1835294118 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrls.readReqs 626 # Number of read requests accepted system.mem_ctrls.writeReqs 622 # Number of write requests accepted system.mem_ctrls.readBursts 626 # Number of DRAM read bursts, including those serviced by the write queue system.mem_ctrls.writeBursts 622 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrls.bytesReadDRAM 24960 # Total number of bytes read from DRAM -system.mem_ctrls.bytesReadWrQ 15104 # Total number of bytes read from write queue -system.mem_ctrls.bytesWritten 24000 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadDRAM 24512 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 15552 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 23424 # Total number of bytes written to DRAM system.mem_ctrls.bytesReadSys 40064 # Total read bytes from the system interface side system.mem_ctrls.bytesWrittenSys 39808 # Total written bytes from the system interface side -system.mem_ctrls.servicedByWrQ 236 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrls.mergedWrBursts 219 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.servicedByWrQ 243 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 231 # Number of DRAM write bursts merged with an existing one system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.mem_ctrls.perBankRdBursts::0 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::1 1 # Per bank write bursts system.mem_ctrls.perBankRdBursts::2 1 # Per bank write bursts system.mem_ctrls.perBankRdBursts::3 30 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::4 23 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 24 # Per bank write bursts system.mem_ctrls.perBankRdBursts::5 0 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::6 58 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::7 62 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::8 63 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::9 4 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::10 24 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::11 15 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::12 32 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::13 66 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 53 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 53 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::8 68 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::9 5 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 25 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 14 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::12 30 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 68 # Per bank write bursts system.mem_ctrls.perBankRdBursts::14 10 # Per bank write bursts system.mem_ctrls.perBankRdBursts::15 1 # Per bank write bursts system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::1 1 # Per bank write bursts system.mem_ctrls.perBankWrBursts::2 1 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::3 31 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::4 22 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 32 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 23 # Per bank write bursts system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::6 54 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::7 57 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::8 65 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::9 3 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::10 21 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 48 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 43 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::8 68 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::9 5 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 23 # Per bank write bursts system.mem_ctrls.perBankWrBursts::11 15 # Per bank write bursts system.mem_ctrls.perBankWrBursts::12 31 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::13 63 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 65 # Per bank write bursts system.mem_ctrls.perBankWrBursts::14 10 # Per bank write bursts system.mem_ctrls.perBankWrBursts::15 1 # Per bank write bursts system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrls.totGap 41626 # Total gap between requests +system.mem_ctrls.totGap 43487 # Total gap between requests system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) @@ -89,7 +89,7 @@ system.mem_ctrls.writePktSize::3 0 # Wr system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::6 622 # Write request sizes (log2) -system.mem_ctrls.rdQLenPdf::0 390 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::0 383 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see @@ -136,24 +136,24 @@ system.mem_ctrls.wrQLenPdf::11 1 # Wh system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::15 3 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::16 3 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::17 18 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::18 25 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::19 27 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::20 27 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::21 25 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::22 25 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::23 24 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::24 24 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::25 24 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::26 24 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::27 24 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::28 23 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::29 23 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::30 23 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::31 23 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::32 23 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 6 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 7 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 17 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 23 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 23 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 26 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 28 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 24 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 23 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::24 23 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 22 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 22 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 22 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::28 22 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 22 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 22 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 22 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::32 22 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see @@ -185,89 +185,98 @@ system.mem_ctrls.wrQLenPdf::60 0 # Wh system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrls.bytesPerActivate::samples 105 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::mean 455.923810 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::gmean 317.170384 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::stdev 344.729986 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::0-127 11 10.48% 10.48% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::128-255 29 27.62% 38.10% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::256-383 10 9.52% 47.62% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::384-511 10 9.52% 57.14% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::512-639 14 13.33% 70.48% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::640-767 5 4.76% 75.24% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::768-895 4 3.81% 79.05% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::896-1023 5 4.76% 83.81% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::1024-1151 17 16.19% 100.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::total 105 # Bytes accessed per row activation -system.mem_ctrls.rdPerTurnAround::samples 23 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::mean 16.434783 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::gmean 16.058223 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::stdev 4.388270 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::12-13 3 13.04% 13.04% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::14-15 10 43.48% 56.52% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::16-17 5 21.74% 78.26% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::18-19 4 17.39% 95.65% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::34-35 1 4.35% 100.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::total 23 # Reads before turning the bus around for writes -system.mem_ctrls.wrPerTurnAround::samples 23 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::mean 16.304348 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::gmean 16.283756 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::stdev 0.875670 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::16 20 86.96% 86.96% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::17 1 4.35% 91.30% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::19 2 8.70% 100.00% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::total 23 # Writes before turning the bus around for reads -system.mem_ctrls.totQLat 4371 # Total ticks spent queuing -system.mem_ctrls.totMemAccLat 11781 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrls.totBusLat 1950 # Total ticks spent in databus transfers -system.mem_ctrls.avgQLat 11.21 # Average queueing delay per DRAM burst +system.mem_ctrls.bytesPerActivate::samples 113 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 404.389381 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 273.588270 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 327.373952 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 20 17.70% 17.70% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 26 23.01% 40.71% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 16 14.16% 54.87% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 15 13.27% 68.14% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 5 4.42% 72.57% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 6 5.31% 77.88% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 8 7.08% 84.96% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 5 4.42% 89.38% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 12 10.62% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 113 # Bytes accessed per row activation +system.mem_ctrls.rdPerTurnAround::samples 22 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::mean 17 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::gmean 16.662586 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::stdev 4.253850 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::14-15 8 36.36% 36.36% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::16-17 8 36.36% 72.73% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::18-19 5 22.73% 95.45% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::34-35 1 4.55% 100.00% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::total 22 # Reads before turning the bus around for writes +system.mem_ctrls.wrPerTurnAround::samples 22 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::mean 16.636364 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::gmean 16.596436 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::stdev 1.216766 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::16 17 77.27% 77.27% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::18 1 4.55% 81.82% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::19 4 18.18% 100.00% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::total 22 # Writes before turning the bus around for reads +system.mem_ctrls.totQLat 6435 # Total ticks spent queuing +system.mem_ctrls.totMemAccLat 13712 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.totBusLat 1915 # Total ticks spent in databus transfers +system.mem_ctrls.avgQLat 16.80 # Average queueing delay per DRAM burst system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst -system.mem_ctrls.avgMemAccLat 30.21 # Average memory access latency per DRAM burst -system.mem_ctrls.avgRdBW 599.15 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrls.avgWrBW 576.11 # Average achieved write bandwidth in MiByte/s -system.mem_ctrls.avgRdBWSys 961.71 # Average system read bandwidth in MiByte/s -system.mem_ctrls.avgWrBWSys 955.57 # Average system write bandwidth in MiByte/s +system.mem_ctrls.avgMemAccLat 35.80 # Average memory access latency per DRAM burst +system.mem_ctrls.avgRdBW 563.24 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 538.24 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 920.59 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 914.71 # Average system write bandwidth in MiByte/s system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrls.busUtil 9.18 # Data bus utilization in percentage -system.mem_ctrls.busUtilRead 4.68 # Data bus utilization in percentage for reads -system.mem_ctrls.busUtilWrite 4.50 # Data bus utilization in percentage for writes +system.mem_ctrls.busUtil 8.61 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 4.40 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 4.20 # Data bus utilization in percentage for writes system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing -system.mem_ctrls.avgWrQLen 24.82 # Average write queue length when enqueuing -system.mem_ctrls.readRowHits 298 # Number of row buffer hits during reads -system.mem_ctrls.writeRowHits 355 # Number of row buffer hits during writes -system.mem_ctrls.readRowHitRate 76.41 # Row buffer hit rate for reads -system.mem_ctrls.writeRowHitRate 88.09 # Row buffer hit rate for writes -system.mem_ctrls.avgGap 33.35 # Average gap between requests -system.mem_ctrls.pageHitRate 82.35 # Row buffer hit rate, read and write combined -system.mem_ctrls_0.actEnergy 234360 # Energy for activate commands per rank (pJ) -system.mem_ctrls_0.preEnergy 130200 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_0.readEnergy 1971840 # Energy for read commands per rank (pJ) -system.mem_ctrls_0.writeEnergy 1555200 # Energy for write commands per rank (pJ) -system.mem_ctrls_0.refreshEnergy 2542800 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_0.actBackEnergy 26028252 # Energy for active background per rank (pJ) -system.mem_ctrls_0.preBackEnergy 682200 # Energy for precharge background per rank (pJ) -system.mem_ctrls_0.totalEnergy 33144852 # Total energy per rank (pJ) -system.mem_ctrls_0.averagePower 845.747691 # Core power per rank (mW) -system.mem_ctrls_0.memoryStateTime::IDLE 1011 # Time in different power states +system.mem_ctrls.avgWrQLen 24.70 # Average write queue length when enqueuing +system.mem_ctrls.readRowHits 286 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 342 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 74.67 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate 87.47 # Row buffer hit rate for writes +system.mem_ctrls.avgGap 34.85 # Average gap between requests +system.mem_ctrls.pageHitRate 81.14 # Row buffer hit rate, read and write combined +system.mem_ctrls_0.actEnergy 264180 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 127512 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 1850688 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 1236096 # Energy for write commands per rank (pJ) +system.mem_ctrls_0.refreshEnergy 3073200.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 3917040 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 69120 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.actPowerDownEnergy 15256848 # Energy for active power-down per rank (pJ) +system.mem_ctrls_0.prePowerDownEnergy 496128 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls_0.totalEnergy 26290812 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 604.108732 # Core power per rank (mW) +system.mem_ctrls_0.totalIdleTime 34684 # Total Idle time Per DRAM Rank +system.mem_ctrls_0.memoryStateTime::IDLE 40 # Time in different power states system.mem_ctrls_0.memoryStateTime::REF 1300 # Time in different power states -system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT 36893 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrls_1.actEnergy 536760 # Energy for activate commands per rank (pJ) -system.mem_ctrls_1.preEnergy 298200 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_1.readEnergy 2608320 # Energy for read commands per rank (pJ) -system.mem_ctrls_1.writeEnergy 2166912 # Energy for write commands per rank (pJ) -system.mem_ctrls_1.refreshEnergy 2542800 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_1.actBackEnergy 26345628 # Energy for active background per rank (pJ) -system.mem_ctrls_1.preBackEnergy 403800 # Energy for precharge background per rank (pJ) -system.mem_ctrls_1.totalEnergy 34902420 # Total energy per rank (pJ) -system.mem_ctrls_1.averagePower 890.595050 # Core power per rank (mW) -system.mem_ctrls_1.memoryStateTime::IDLE 832 # Time in different power states +system.mem_ctrls_0.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls_0.memoryStateTime::PRE_PDN 1292 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 7430 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT_PDN 33458 # Time in different power states +system.mem_ctrls_1.actEnergy 599760 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 309120 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 2524704 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 1820736 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.refreshEnergy 3073200.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 5746968 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 231168 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.actPowerDownEnergy 13781232 # Energy for active power-down per rank (pJ) +system.mem_ctrls_1.prePowerDownEnergy 35712 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls_1.totalEnergy 28122600 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 646.199449 # Core power per rank (mW) +system.mem_ctrls_1.totalIdleTime 29649 # Total Idle time Per DRAM Rank +system.mem_ctrls_1.memoryStateTime::IDLE 448 # Time in different power states system.mem_ctrls_1.memoryStateTime::REF 1300 # Time in different power states -system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT 37357 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 41659 # Cumulative time (in ticks) in various power states +system.mem_ctrls_1.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls_1.memoryStateTime::PRE_PDN 93 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 11457 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT_PDN 30222 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 43520 # Cumulative time (in ticks) in various power states system.cpu.clk_domain.clock 1 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -302,8 +311,8 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 41659 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 41659 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 43520 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 43520 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 2577 # Number of instructions committed @@ -322,7 +331,7 @@ system.cpu.num_mem_refs 717 # nu system.cpu.num_load_insts 419 # Number of load instructions system.cpu.num_store_insts 298 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 41659 # Number of busy cycles +system.cpu.num_busy_cycles 43520 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 396 # Number of branches fetched @@ -362,7 +371,7 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 2585 # Class of executed instruction system.ruby.clk_domain.clock 1 # Clock period in ticks -system.ruby.pwrStateResidencyTicks::UNDEFINED 41659 # Cumulative time (in ticks) in various power states +system.ruby.pwrStateResidencyTicks::UNDEFINED 43520 # Cumulative time (in ticks) in various power states system.ruby.delayHist::bucket_size 1 # delay histogram for all message system.ruby.delayHist::max_bucket 9 # delay histogram for all message system.ruby.delayHist::samples 1248 # delay histogram for all message @@ -378,10 +387,10 @@ system.ruby.outstanding_req_hist_seqr::total 3295 system.ruby.latency_hist_seqr::bucket_size 64 system.ruby.latency_hist_seqr::max_bucket 639 system.ruby.latency_hist_seqr::samples 3294 -system.ruby.latency_hist_seqr::mean 11.646934 -system.ruby.latency_hist_seqr::gmean 2.114776 -system.ruby.latency_hist_seqr::stdev 26.263922 -system.ruby.latency_hist_seqr | 3185 96.69% 96.69% | 90 2.73% 99.42% | 14 0.43% 99.85% | 0 0.00% 99.85% | 2 0.06% 99.91% | 3 0.09% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.latency_hist_seqr::mean 12.211900 +system.ruby.latency_hist_seqr::gmean 2.131468 +system.ruby.latency_hist_seqr::stdev 27.594720 +system.ruby.latency_hist_seqr | 2924 88.77% 88.77% | 353 10.72% 99.48% | 12 0.36% 99.85% | 0 0.00% 99.85% | 2 0.06% 99.91% | 3 0.09% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.latency_hist_seqr::total 3294 system.ruby.hit_latency_hist_seqr::bucket_size 1 system.ruby.hit_latency_hist_seqr::max_bucket 9 @@ -393,21 +402,21 @@ system.ruby.hit_latency_hist_seqr::total 2668 system.ruby.miss_latency_hist_seqr::bucket_size 64 system.ruby.miss_latency_hist_seqr::max_bucket 639 system.ruby.miss_latency_hist_seqr::samples 626 -system.ruby.miss_latency_hist_seqr::mean 57.023962 -system.ruby.miss_latency_hist_seqr::gmean 51.467697 -system.ruby.miss_latency_hist_seqr::stdev 32.986607 -system.ruby.miss_latency_hist_seqr | 517 82.59% 82.59% | 90 14.38% 96.96% | 14 2.24% 99.20% | 0 0.00% 99.20% | 2 0.32% 99.52% | 3 0.48% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.miss_latency_hist_seqr::mean 59.996805 +system.ruby.miss_latency_hist_seqr::gmean 53.641558 +system.ruby.miss_latency_hist_seqr::stdev 34.472574 +system.ruby.miss_latency_hist_seqr | 256 40.89% 40.89% | 353 56.39% 97.28% | 12 1.92% 99.20% | 0 0.00% 99.20% | 2 0.32% 99.52% | 3 0.48% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.miss_latency_hist_seqr::total 626 system.ruby.Directory.incomplete_times_seqr 625 -system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 41659 # Cumulative time (in ticks) in various power states +system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 43520 # Cumulative time (in ticks) in various power states system.ruby.l1_cntrl0.cacheMemory.demand_hits 2668 # Number of cache demand hits system.ruby.l1_cntrl0.cacheMemory.demand_misses 626 # Number of cache demand misses system.ruby.l1_cntrl0.cacheMemory.demand_accesses 3294 # Number of cache demand accesses -system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 41659 # Cumulative time (in ticks) in various power states -system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 41659 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 43520 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 43520 # Cumulative time (in ticks) in various power states system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 41659 # Cumulative time (in ticks) in various power states -system.ruby.network.routers0.percent_links_utilized 7.489378 +system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 43520 # Cumulative time (in ticks) in various power states +system.ruby.network.routers0.percent_links_utilized 7.169118 system.ruby.network.routers0.msg_count.Control::2 626 system.ruby.network.routers0.msg_count.Data::2 622 system.ruby.network.routers0.msg_count.Response_Data::4 626 @@ -416,8 +425,8 @@ system.ruby.network.routers0.msg_bytes.Control::2 5008 system.ruby.network.routers0.msg_bytes.Data::2 44784 system.ruby.network.routers0.msg_bytes.Response_Data::4 45072 system.ruby.network.routers0.msg_bytes.Writeback_Control::3 4976 -system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 41659 # Cumulative time (in ticks) in various power states -system.ruby.network.routers1.percent_links_utilized 7.489378 +system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 43520 # Cumulative time (in ticks) in various power states +system.ruby.network.routers1.percent_links_utilized 7.169118 system.ruby.network.routers1.msg_count.Control::2 626 system.ruby.network.routers1.msg_count.Data::2 622 system.ruby.network.routers1.msg_count.Response_Data::4 626 @@ -426,8 +435,8 @@ system.ruby.network.routers1.msg_bytes.Control::2 5008 system.ruby.network.routers1.msg_bytes.Data::2 44784 system.ruby.network.routers1.msg_bytes.Response_Data::4 45072 system.ruby.network.routers1.msg_bytes.Writeback_Control::3 4976 -system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 41659 # Cumulative time (in ticks) in various power states -system.ruby.network.routers2.percent_links_utilized 7.489378 +system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 43520 # Cumulative time (in ticks) in various power states +system.ruby.network.routers2.percent_links_utilized 7.169118 system.ruby.network.routers2.msg_count.Control::2 626 system.ruby.network.routers2.msg_count.Data::2 622 system.ruby.network.routers2.msg_count.Response_Data::4 626 @@ -436,7 +445,7 @@ system.ruby.network.routers2.msg_bytes.Control::2 5008 system.ruby.network.routers2.msg_bytes.Data::2 44784 system.ruby.network.routers2.msg_bytes.Response_Data::4 45072 system.ruby.network.routers2.msg_bytes.Writeback_Control::3 4976 -system.ruby.network.pwrStateResidencyTicks::UNDEFINED 41659 # Cumulative time (in ticks) in various power states +system.ruby.network.pwrStateResidencyTicks::UNDEFINED 43520 # Cumulative time (in ticks) in various power states system.ruby.network.msg_count.Control 1878 system.ruby.network.msg_count.Data 1866 system.ruby.network.msg_count.Response_Data 1878 @@ -445,33 +454,33 @@ system.ruby.network.msg_byte.Control 15024 system.ruby.network.msg_byte.Data 134352 system.ruby.network.msg_byte.Response_Data 135216 system.ruby.network.msg_byte.Writeback_Control 14928 -system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 41659 # Cumulative time (in ticks) in various power states -system.ruby.network.routers0.throttle0.link_utilization 7.508582 +system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 43520 # Cumulative time (in ticks) in various power states +system.ruby.network.routers0.throttle0.link_utilization 7.187500 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 626 system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 622 system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 45072 system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 4976 -system.ruby.network.routers0.throttle1.link_utilization 7.470175 +system.ruby.network.routers0.throttle1.link_utilization 7.150735 system.ruby.network.routers0.throttle1.msg_count.Control::2 626 system.ruby.network.routers0.throttle1.msg_count.Data::2 622 system.ruby.network.routers0.throttle1.msg_bytes.Control::2 5008 system.ruby.network.routers0.throttle1.msg_bytes.Data::2 44784 -system.ruby.network.routers1.throttle0.link_utilization 7.470175 +system.ruby.network.routers1.throttle0.link_utilization 7.150735 system.ruby.network.routers1.throttle0.msg_count.Control::2 626 system.ruby.network.routers1.throttle0.msg_count.Data::2 622 system.ruby.network.routers1.throttle0.msg_bytes.Control::2 5008 system.ruby.network.routers1.throttle0.msg_bytes.Data::2 44784 -system.ruby.network.routers1.throttle1.link_utilization 7.508582 +system.ruby.network.routers1.throttle1.link_utilization 7.187500 system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 626 system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 622 system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 45072 system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 4976 -system.ruby.network.routers2.throttle0.link_utilization 7.508582 +system.ruby.network.routers2.throttle0.link_utilization 7.187500 system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 626 system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 622 system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 45072 system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 4976 -system.ruby.network.routers2.throttle1.link_utilization 7.470175 +system.ruby.network.routers2.throttle1.link_utilization 7.150735 system.ruby.network.routers2.throttle1.msg_count.Control::2 626 system.ruby.network.routers2.throttle1.msg_count.Data::2 622 system.ruby.network.routers2.throttle1.msg_bytes.Control::2 5008 @@ -486,13 +495,13 @@ system.ruby.delayVCHist.vnet_2::max_bucket 9 # system.ruby.delayVCHist.vnet_2::samples 622 # delay histogram for vnet_2 system.ruby.delayVCHist.vnet_2 | 622 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 system.ruby.delayVCHist.vnet_2::total 622 # delay histogram for vnet_2 -system.ruby.LD.latency_hist_seqr::bucket_size 32 -system.ruby.LD.latency_hist_seqr::max_bucket 319 +system.ruby.LD.latency_hist_seqr::bucket_size 64 +system.ruby.LD.latency_hist_seqr::max_bucket 639 system.ruby.LD.latency_hist_seqr::samples 415 -system.ruby.LD.latency_hist_seqr::mean 30.537349 -system.ruby.LD.latency_hist_seqr::gmean 9.686440 -system.ruby.LD.latency_hist_seqr::stdev 30.265140 -system.ruby.LD.latency_hist_seqr | 170 40.96% 40.96% | 203 48.92% 89.88% | 35 8.43% 98.31% | 3 0.72% 99.04% | 3 0.72% 99.76% | 1 0.24% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.latency_hist_seqr::mean 33.354217 +system.ruby.LD.latency_hist_seqr::gmean 9.992707 +system.ruby.LD.latency_hist_seqr::stdev 38.395820 +system.ruby.LD.latency_hist_seqr | 297 71.57% 71.57% | 114 27.47% 99.04% | 2 0.48% 99.52% | 0 0.00% 99.52% | 0 0.00% 99.52% | 2 0.48% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.latency_hist_seqr::total 415 system.ruby.LD.hit_latency_hist_seqr::bucket_size 1 system.ruby.LD.hit_latency_hist_seqr::max_bucket 9 @@ -501,21 +510,21 @@ system.ruby.LD.hit_latency_hist_seqr::mean 1 system.ruby.LD.hit_latency_hist_seqr::gmean 1 system.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 170 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.hit_latency_hist_seqr::total 170 -system.ruby.LD.miss_latency_hist_seqr::bucket_size 32 -system.ruby.LD.miss_latency_hist_seqr::max_bucket 319 +system.ruby.LD.miss_latency_hist_seqr::bucket_size 64 +system.ruby.LD.miss_latency_hist_seqr::max_bucket 639 system.ruby.LD.miss_latency_hist_seqr::samples 245 -system.ruby.LD.miss_latency_hist_seqr::mean 51.032653 -system.ruby.LD.miss_latency_hist_seqr::gmean 46.821080 -system.ruby.LD.miss_latency_hist_seqr::stdev 22.902478 -system.ruby.LD.miss_latency_hist_seqr | 0 0.00% 0.00% | 203 82.86% 82.86% | 35 14.29% 97.14% | 3 1.22% 98.37% | 3 1.22% 99.59% | 1 0.41% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.miss_latency_hist_seqr::mean 55.804082 +system.ruby.LD.miss_latency_hist_seqr::gmean 49.356103 +system.ruby.LD.miss_latency_hist_seqr::stdev 35.580698 +system.ruby.LD.miss_latency_hist_seqr | 127 51.84% 51.84% | 114 46.53% 98.37% | 2 0.82% 99.18% | 0 0.00% 99.18% | 0 0.00% 99.18% | 2 0.82% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.miss_latency_hist_seqr::total 245 -system.ruby.ST.latency_hist_seqr::bucket_size 64 -system.ruby.ST.latency_hist_seqr::max_bucket 639 +system.ruby.ST.latency_hist_seqr::bucket_size 32 +system.ruby.ST.latency_hist_seqr::max_bucket 319 system.ruby.ST.latency_hist_seqr::samples 294 -system.ruby.ST.latency_hist_seqr::mean 16.663265 -system.ruby.ST.latency_hist_seqr::gmean 3.036238 -system.ruby.ST.latency_hist_seqr::stdev 32.952425 -system.ruby.ST.latency_hist_seqr | 283 96.26% 96.26% | 6 2.04% 98.30% | 4 1.36% 99.66% | 0 0.00% 99.66% | 0 0.00% 99.66% | 1 0.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.latency_hist_seqr::mean 16.173469 +system.ruby.ST.latency_hist_seqr::gmean 3.033104 +system.ruby.ST.latency_hist_seqr::stdev 28.208400 +system.ruby.ST.latency_hist_seqr | 210 71.43% 71.43% | 44 14.97% 86.39% | 36 12.24% 98.64% | 1 0.34% 98.98% | 2 0.68% 99.66% | 1 0.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ST.latency_hist_seqr::total 294 system.ruby.ST.hit_latency_hist_seqr::bucket_size 1 system.ruby.ST.hit_latency_hist_seqr::max_bucket 9 @@ -524,21 +533,21 @@ system.ruby.ST.hit_latency_hist_seqr::mean 1 system.ruby.ST.hit_latency_hist_seqr::gmean 1 system.ruby.ST.hit_latency_hist_seqr | 0 0.00% 0.00% | 210 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ST.hit_latency_hist_seqr::total 210 -system.ruby.ST.miss_latency_hist_seqr::bucket_size 64 -system.ruby.ST.miss_latency_hist_seqr::max_bucket 639 +system.ruby.ST.miss_latency_hist_seqr::bucket_size 32 +system.ruby.ST.miss_latency_hist_seqr::max_bucket 319 system.ruby.ST.miss_latency_hist_seqr::samples 84 -system.ruby.ST.miss_latency_hist_seqr::mean 55.821429 -system.ruby.ST.miss_latency_hist_seqr::gmean 48.772534 -system.ruby.ST.miss_latency_hist_seqr::stdev 40.751129 -system.ruby.ST.miss_latency_hist_seqr | 73 86.90% 86.90% | 6 7.14% 94.05% | 4 4.76% 98.81% | 0 0.00% 98.81% | 0 0.00% 98.81% | 1 1.19% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.miss_latency_hist_seqr::mean 54.107143 +system.ruby.ST.miss_latency_hist_seqr::gmean 48.596564 +system.ruby.ST.miss_latency_hist_seqr::stdev 27.751487 +system.ruby.ST.miss_latency_hist_seqr | 0 0.00% 0.00% | 44 52.38% 52.38% | 36 42.86% 95.24% | 1 1.19% 96.43% | 2 2.38% 98.81% | 1 1.19% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ST.miss_latency_hist_seqr::total 84 system.ruby.IFETCH.latency_hist_seqr::bucket_size 64 system.ruby.IFETCH.latency_hist_seqr::max_bucket 639 system.ruby.IFETCH.latency_hist_seqr::samples 2585 -system.ruby.IFETCH.latency_hist_seqr::mean 8.043714 -system.ruby.IFETCH.latency_hist_seqr::gmean 1.589638 -system.ruby.IFETCH.latency_hist_seqr::stdev 23.152025 -system.ruby.IFETCH.latency_hist_seqr | 2529 97.83% 97.83% | 46 1.78% 99.61% | 6 0.23% 99.85% | 0 0.00% 99.85% | 2 0.08% 99.92% | 2 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.latency_hist_seqr::mean 8.367118 +system.ruby.IFETCH.latency_hist_seqr::gmean 1.597827 +system.ruby.IFETCH.latency_hist_seqr::stdev 23.571466 +system.ruby.IFETCH.latency_hist_seqr | 2373 91.80% 91.80% | 202 7.81% 99.61% | 7 0.27% 99.88% | 0 0.00% 99.88% | 2 0.08% 99.96% | 1 0.04% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.latency_hist_seqr::total 2585 system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 1 system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 9 @@ -550,18 +559,18 @@ system.ruby.IFETCH.hit_latency_hist_seqr::total 2288 system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 64 system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 639 system.ruby.IFETCH.miss_latency_hist_seqr::samples 297 -system.ruby.IFETCH.miss_latency_hist_seqr::mean 62.306397 -system.ruby.IFETCH.miss_latency_hist_seqr::gmean 56.498895 -system.ruby.IFETCH.miss_latency_hist_seqr::stdev 36.624977 -system.ruby.IFETCH.miss_latency_hist_seqr | 241 81.14% 81.14% | 46 15.49% 96.63% | 6 2.02% 98.65% | 0 0.00% 98.65% | 2 0.67% 99.33% | 2 0.67% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.miss_latency_hist_seqr::mean 65.121212 +system.ruby.IFETCH.miss_latency_hist_seqr::gmean 59.083052 +system.ruby.IFETCH.miss_latency_hist_seqr::stdev 34.625488 +system.ruby.IFETCH.miss_latency_hist_seqr | 85 28.62% 28.62% | 202 68.01% 96.63% | 7 2.36% 98.99% | 0 0.00% 98.99% | 2 0.67% 99.66% | 1 0.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.miss_latency_hist_seqr::total 297 system.ruby.Directory.miss_mach_latency_hist_seqr::bucket_size 64 system.ruby.Directory.miss_mach_latency_hist_seqr::max_bucket 639 system.ruby.Directory.miss_mach_latency_hist_seqr::samples 626 -system.ruby.Directory.miss_mach_latency_hist_seqr::mean 57.023962 -system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 51.467697 -system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 32.986607 -system.ruby.Directory.miss_mach_latency_hist_seqr | 517 82.59% 82.59% | 90 14.38% 96.96% | 14 2.24% 99.20% | 0 0.00% 99.20% | 2 0.32% 99.52% | 3 0.48% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_mach_latency_hist_seqr::mean 59.996805 +system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 53.641558 +system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 34.472574 +system.ruby.Directory.miss_mach_latency_hist_seqr | 256 40.89% 40.89% | 353 56.39% 97.28% | 12 1.92% 99.20% | 0 0.00% 99.20% | 2 0.32% 99.52% | 3 0.48% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.Directory.miss_mach_latency_hist_seqr::total 626 system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::bucket_size 1 system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::max_bucket 9 @@ -589,29 +598,29 @@ system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::gmean system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::stdev nan system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::total 1 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size 32 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket 319 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples 245 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 51.032653 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 46.821080 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 22.902478 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 203 82.86% 82.86% | 35 14.29% 97.14% | 3 1.22% 98.37% | 3 1.22% 99.59% | 1 0.41% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 55.804082 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 49.356103 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 35.580698 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 127 51.84% 51.84% | 114 46.53% 98.37% | 2 0.82% 99.18% | 0 0.00% 99.18% | 0 0.00% 99.18% | 2 0.82% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total 245 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size 32 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket 319 system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::samples 84 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 55.821429 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 48.772534 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 40.751129 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 73 86.90% 86.90% | 6 7.14% 94.05% | 4 4.76% 98.81% | 0 0.00% 98.81% | 0 0.00% 98.81% | 1 1.19% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 54.107143 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 48.596564 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 27.751487 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 44 52.38% 52.38% | 36 42.86% 95.24% | 1 1.19% 96.43% | 2 2.38% 98.81% | 1 1.19% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total 84 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::samples 297 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 62.306397 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 56.498895 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 36.624977 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 241 81.14% 81.14% | 46 15.49% 96.63% | 6 2.02% 98.65% | 0 0.00% 98.65% | 2 0.67% 99.33% | 2 0.67% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 65.121212 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 59.083052 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 34.625488 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 85 28.62% 28.62% | 202 68.01% 96.63% | 7 2.36% 98.99% | 0 0.00% 98.99% | 2 0.67% 99.66% | 1 0.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::total 297 system.ruby.Directory_Controller.GETX 626 0.00% 0.00% system.ruby.Directory_Controller.PUTX 622 0.00% 0.00% diff --git a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/config.ini b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/config.ini index a47bafcf6..fc8ce75af 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/config.ini +++ b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/config.ini @@ -151,7 +151,7 @@ useIndirect=true [system.cpu.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -631,7 +631,7 @@ opClass=InstPrefetch [system.cpu.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -691,7 +691,7 @@ id_aa64isar0_el1=0 id_aa64isar1_el1=0 id_aa64mmfr0_el1=15728642 id_aa64mmfr1_el1=0 -id_aa64pfr0_el1=17 +id_aa64pfr0_el1=34 id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 @@ -763,7 +763,7 @@ port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -880,6 +880,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -891,7 +892,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -899,29 +900,36 @@ width=16 master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -941,6 +949,7 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 @@ -950,7 +959,7 @@ p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 page_policy=open_adaptive power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 @@ -972,9 +981,9 @@ tRTW=2500 tWR=15000 tWTR=7500 tXAW=30000 -tXP=0 +tXP=6000 tXPDLL=0 -tXS=0 +tXS=270000 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 diff --git a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/simout b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/simout index 21abd8071..6a285f351 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/simout @@ -3,12 +3,12 @@ Redirecting stderr to build/ARM/tests/opt/quick/se/00.hello/arm/linux/minor-timi gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:37:41 -gem5 started Jul 21 2016 14:38:22 -gem5 executing on e108600-lin, pid 23083 +gem5 compiled Oct 11 2016 00:00:58 +gem5 started Oct 13 2016 20:42:59 +gem5 executing on e108600-lin, pid 17319 command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/minor-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/arm/linux/minor-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 30083500 because target called exit() +Exiting @ tick 32719500 because target called exit() diff --git a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt index 9ca1ab172..48cd9ae26 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000030 # Number of seconds simulated -sim_ticks 30404500 # Number of ticks simulated -final_tick 30404500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000033 # Number of seconds simulated +sim_ticks 32719500 # Number of ticks simulated +final_tick 32719500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 82707 # Simulator instruction rate (inst/s) -host_op_rate 96800 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 545818868 # Simulator tick rate (ticks/s) -host_mem_usage 269760 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host +host_inst_rate 127457 # Simulator instruction rate (inst/s) +host_op_rate 149152 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 904929733 # Simulator tick rate (ticks/s) +host_mem_usage 267332 # Number of bytes of host memory used +host_seconds 0.04 # Real time elapsed on the host sim_insts 4605 # Number of instructions simulated sim_ops 5391 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 30404500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 32719500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 19520 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 7424 # Number of bytes read from this memory system.physmem.bytes_read::total 26944 # Number of bytes read from this memory @@ -22,14 +22,14 @@ system.physmem.bytes_inst_read::total 19520 # Nu system.physmem.num_reads::cpu.inst 305 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 116 # Number of read requests responded to by this memory system.physmem.num_reads::total 421 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 642010229 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 244174382 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 886184611 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 642010229 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 642010229 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 642010229 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 244174382 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 886184611 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 596586134 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 226898333 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 823484466 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 596586134 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 596586134 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 596586134 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 226898333 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 823484466 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 421 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 421 # Number of DRAM read bursts, including those serviced by the write queue @@ -76,7 +76,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 30312500 # Total gap between requests +system.physmem.totGap 32621500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -91,9 +91,9 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 344 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 343 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 70 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 7 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 8 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -187,86 +187,96 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 63 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 402.285714 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 286.546821 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 324.800854 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 7 11.11% 11.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 19 30.16% 41.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 13 20.63% 61.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 6 9.52% 71.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2 3.17% 74.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 3 4.76% 79.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 3 4.76% 84.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1 1.59% 85.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 9 14.29% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 63 # Bytes accessed per row activation -system.physmem.totQLat 2201250 # Total ticks spent queuing -system.physmem.totMemAccLat 10095000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 70 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 374.857143 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 257.842659 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 316.227871 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 12 17.14% 17.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 20 28.57% 45.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 11 15.71% 61.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 9 12.86% 74.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2 2.86% 77.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 3 4.29% 81.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 4 5.71% 87.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2 2.86% 90.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7 10.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 70 # Bytes accessed per row activation +system.physmem.totQLat 5175000 # Total ticks spent queuing +system.physmem.totMemAccLat 13068750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2105000 # Total ticks spent in databus transfers -system.physmem.avgQLat 5228.62 # Average queueing delay per DRAM burst +system.physmem.avgQLat 12292.16 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 23978.62 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 886.18 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 31042.16 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 823.48 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 886.18 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 823.48 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 6.92 # Data bus utilization in percentage -system.physmem.busUtilRead 6.92 # Data bus utilization in percentage for reads +system.physmem.busUtil 6.43 # Data bus utilization in percentage +system.physmem.busUtilRead 6.43 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.22 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.23 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 349 # Number of row buffer hits during reads +system.physmem.readRowHits 347 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.90 # Row buffer hit rate for reads +system.physmem.readRowHitRate 82.42 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 72001.19 # Average gap between requests -system.physmem.pageHitRate 82.90 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 272160 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 148500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1942200 # Energy for read commands per rank (pJ) +system.physmem.avgGap 77485.75 # Average gap between requests +system.physmem.pageHitRate 82.42 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 349860 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 174570 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 2263380 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 16099650 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 48750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 20036940 # Total energy per rank (pJ) -system.physmem_0.averagePower 848.348875 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 12000 # Time in different power states -system.physmem_0.memoryStateTime::REF 780000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 22840500 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 128520 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 70125 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 694200 # Energy for read commands per rank (pJ) +system.physmem_0.refreshEnergy 2458560.000000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 4410090 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 59520 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 10437840 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 1440 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 20155260 # Total energy per rank (pJ) +system.physmem_0.averagePower 615.992054 # Core power per rank (mW) +system.physmem_0.totalIdleTime 22842000 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 30000 # Time in different power states +system.physmem_0.memoryStateTime::REF 1040000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 0 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 3750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 8749750 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 22896000 # Time in different power states +system.physmem_1.actEnergy 178500 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 91080 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 742560 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 15442155 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 625500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 18486180 # Total energy per rank (pJ) -system.physmem_1.averagePower 782.690871 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2431750 # Time in different power states -system.physmem_1.memoryStateTime::REF 780000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 21880250 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 30404500 # Cumulative time (in ticks) in various power states +system.physmem_1.refreshEnergy 2458560.000000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1743060 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 96480 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 12022440 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 876000 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 18208680 # Total energy per rank (pJ) +system.physmem_1.averagePower 556.500000 # Core power per rank (mW) +system.physmem_1.totalIdleTime 28380000 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 141000 # Time in different power states +system.physmem_1.memoryStateTime::REF 1040000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 0 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 2280750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 2887500 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 26370250 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 32719500 # Cumulative time (in ticks) in various power states system.cpu.branchPred.lookups 1968 # Number of BP lookups -system.cpu.branchPred.condPredicted 1178 # Number of conditional branches predicted +system.cpu.branchPred.condPredicted 1177 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 351 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 1660 # Number of BTB lookups +system.cpu.branchPred.BTBLookups 1659 # Number of BTB lookups system.cpu.branchPred.BTBHits 322 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 19.397590 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 220 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 19.409283 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 221 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 16 # Number of incorrect RAS predictions. system.cpu.branchPred.indirectLookups 135 # Number of indirect predictor lookups. system.cpu.branchPred.indirectHits 8 # Number of indirect target hits. system.cpu.branchPred.indirectMisses 127 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 62 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 30404500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 32719500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -296,7 +306,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 30404500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 32719500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -326,7 +336,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 30404500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 32719500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -356,7 +366,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 30404500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 32719500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -387,16 +397,16 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 30404500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 60809 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 32719500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 65439 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 4605 # Number of instructions committed system.cpu.committedOps 5391 # Number of ops (including micro ops) committed system.cpu.discardedOps 1193 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 13.204995 # CPI: cycles per instruction -system.cpu.ipc 0.075729 # IPC: instructions per cycle +system.cpu.cpi 14.210423 # CPI: cycles per instruction +system.cpu.ipc 0.070371 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction system.cpu.op_class_0::IntAlu 3419 63.42% 63.42% # Class of committed instruction system.cpu.op_class_0::IntMult 4 0.07% 63.49% # Class of committed instruction @@ -432,25 +442,25 @@ system.cpu.op_class_0::MemWrite 938 17.40% 100.00% # Cl system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 5391 # Class of committed instruction -system.cpu.tickCycles 10721 # Number of cycles that the object actually ticked -system.cpu.idleCycles 50088 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 30404500 # Cumulative time (in ticks) in various power states +system.cpu.tickCycles 10731 # Number of cycles that the object actually ticked +system.cpu.idleCycles 54708 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 32719500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 86.589882 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 86.904844 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1918 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 13.136986 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 86.589882 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.021140 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.021140 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 86.904844 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.021217 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.021217 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 36 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 110 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 120 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 4334 # Number of tag accesses system.cpu.dcache.tags.data_accesses 4334 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 30404500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 32719500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 1050 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1050 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 846 # number of WriteReq hits @@ -471,14 +481,14 @@ system.cpu.dcache.demand_misses::cpu.data 176 # n system.cpu.dcache.demand_misses::total 176 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 176 # number of overall misses system.cpu.dcache.overall_misses::total 176 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 6774500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 6774500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 5069500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 5069500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 11844000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 11844000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 11844000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 11844000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 7434500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 7434500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 5464500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 5464500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 12899000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 12899000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 12899000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 12899000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1159 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1159 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) @@ -499,14 +509,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.084942 system.cpu.dcache.demand_miss_rate::total 0.084942 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.084942 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.084942 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62151.376147 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 62151.376147 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75664.179104 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 75664.179104 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 67295.454545 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 67295.454545 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 67295.454545 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 67295.454545 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 68206.422018 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 68206.422018 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 81559.701493 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 81559.701493 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 73289.772727 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 73289.772727 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 73289.772727 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 73289.772727 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -529,14 +539,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 146 system.cpu.dcache.demand_mshr_misses::total 146 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 146 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 146 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6419000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6419000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3231000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3231000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9650000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9650000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9650000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 9650000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7061000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 7061000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3488000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3488000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10549000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10549000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10549000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10549000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.088870 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.088870 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047097 # mshr miss rate for WriteReq accesses @@ -545,67 +555,67 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.070463 system.cpu.dcache.demand_mshr_miss_rate::total 0.070463 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.070463 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.070463 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 62320.388350 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 62320.388350 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75139.534884 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75139.534884 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66095.890411 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 66095.890411 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66095.890411 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 66095.890411 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 30404500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 68553.398058 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 68553.398058 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 81116.279070 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 81116.279070 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 72253.424658 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 72253.424658 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 72253.424658 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 72253.424658 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 32719500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 4 # number of replacements -system.cpu.icache.tags.tagsinuse 162.072741 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1963 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 162.619345 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1965 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 322 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 6.096273 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 6.102484 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 162.072741 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.079137 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.079137 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 162.619345 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.079404 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.079404 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 318 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 103 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 215 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 98 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 220 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.155273 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 4892 # Number of tag accesses -system.cpu.icache.tags.data_accesses 4892 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 30404500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 1963 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1963 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1963 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1963 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1963 # number of overall hits -system.cpu.icache.overall_hits::total 1963 # number of overall hits +system.cpu.icache.tags.tag_accesses 4896 # Number of tag accesses +system.cpu.icache.tags.data_accesses 4896 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 32719500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 1965 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1965 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1965 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1965 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1965 # number of overall hits +system.cpu.icache.overall_hits::total 1965 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 322 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 322 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 322 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 322 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 322 # number of overall misses system.cpu.icache.overall_misses::total 322 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 23964000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 23964000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 23964000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 23964000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 23964000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 23964000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2285 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2285 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2285 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2285 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2285 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2285 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.140919 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.140919 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.140919 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.140919 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.140919 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.140919 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 74422.360248 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 74422.360248 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 74422.360248 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 74422.360248 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 74422.360248 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 74422.360248 # average overall miss latency +system.cpu.icache.ReadReq_miss_latency::cpu.inst 26079500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 26079500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 26079500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 26079500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 26079500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 26079500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 2287 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 2287 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 2287 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 2287 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 2287 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 2287 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.140796 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.140796 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.140796 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.140796 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.140796 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.140796 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 80992.236025 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 80992.236025 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 80992.236025 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 80992.236025 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 80992.236025 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 80992.236025 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -620,43 +630,43 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 322 system.cpu.icache.demand_mshr_misses::total 322 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 322 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 322 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23642000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 23642000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23642000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 23642000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23642000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 23642000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.140919 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.140919 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.140919 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.140919 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.140919 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.140919 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 73422.360248 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 73422.360248 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 73422.360248 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 73422.360248 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73422.360248 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 73422.360248 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 30404500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25757500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 25757500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25757500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 25757500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25757500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 25757500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.140796 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.140796 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.140796 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.140796 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.140796 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.140796 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 79992.236025 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 79992.236025 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 79992.236025 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 79992.236025 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 79992.236025 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 79992.236025 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 32719500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 223.657376 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 224.400944 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 42 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 421 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.099762 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 154.975765 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 68.681611 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004729 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.002096 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.006825 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 155.496620 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 68.904325 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004745 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.002103 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.006848 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 421 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 296 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 113 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 308 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012848 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 4189 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 4189 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 30404500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 32719500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackClean_hits::writebacks 3 # number of WritebackClean hits system.cpu.l2cache.WritebackClean_hits::total 3 # number of WritebackClean hits system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 17 # number of ReadCleanReq hits @@ -681,18 +691,18 @@ system.cpu.l2cache.demand_misses::total 429 # nu system.cpu.l2cache.overall_misses::cpu.inst 305 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 124 # number of overall misses system.cpu.l2cache.overall_misses::total 429 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3166500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 3166500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 22963500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 22963500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 6005000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 6005000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 22963500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 9171500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 32135000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 22963500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 9171500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 32135000 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3423500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 3423500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 25079000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 25079000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 6647000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 6647000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 25079000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 10070500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 35149500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 25079000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 10070500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 35149500 # number of overall miss cycles system.cpu.l2cache.WritebackClean_accesses::writebacks 3 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::total 3 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 43 # number of ReadExReq accesses(hits+misses) @@ -719,18 +729,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.916667 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.947205 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.849315 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.916667 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73639.534884 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73639.534884 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75290.163934 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75290.163934 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 74135.802469 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 74135.802469 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75290.163934 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73963.709677 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 74906.759907 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75290.163934 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73963.709677 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 74906.759907 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79616.279070 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79616.279070 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82226.229508 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82226.229508 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 82061.728395 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 82061.728395 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82226.229508 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81213.709677 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 81933.566434 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82226.229508 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81213.709677 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 81933.566434 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -755,18 +765,18 @@ system.cpu.l2cache.demand_mshr_misses::total 421 system.cpu.l2cache.overall_mshr_misses::cpu.inst 305 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 116 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 421 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2736500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2736500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 19913500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 19913500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4721000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4721000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19913500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7457500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 27371000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19913500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7457500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 27371000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2993500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2993500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 22029000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 22029000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5321000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5321000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22029000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8314500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 30343500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22029000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8314500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 30343500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.947205 # mshr miss rate for ReadCleanReq accesses @@ -779,25 +789,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.899573 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.947205 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.794521 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.899573 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63639.534884 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63639.534884 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65290.163934 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65290.163934 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 64671.232877 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 64671.232877 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65290.163934 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64288.793103 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65014.251781 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65290.163934 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64288.793103 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65014.251781 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69616.279070 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69616.279070 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72226.229508 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72226.229508 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72890.410959 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72890.410959 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72226.229508 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71676.724138 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72074.821853 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72226.229508 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71676.724138 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72074.821853 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 472 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 50 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 30404500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 32719500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 425 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 4 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 43 # Transaction distribution @@ -824,9 +834,9 @@ system.cpu.toL2Bus.snoop_fanout::min_value 0 # system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 468 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 240000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%) +system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 483000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 1.6 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.utilization 1.5 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 222992 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) system.membus.snoop_filter.tot_requests 421 # Total number of requests made to the snoop filter. @@ -835,7 +845,7 @@ system.membus.snoop_filter.hit_multi_requests 0 system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 30404500 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 32719500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 378 # Transaction distribution system.membus.trans_dist::ReadExReq 43 # Transaction distribution system.membus.trans_dist::ReadExResp 43 # Transaction distribution @@ -856,9 +866,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 421 # Request fanout histogram -system.membus.reqLayer0.occupancy 490000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.6 # Layer utilization (%) -system.membus.respLayer1.occupancy 2238500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 7.4 # Layer utilization (%) +system.membus.reqLayer0.occupancy 489500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.5 # Layer utilization (%) +system.membus.respLayer1.occupancy 2238250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 6.8 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini index 69978e99c..ff436d924 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini @@ -352,7 +352,7 @@ eventq_index=0 [system.cpu.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -756,7 +756,7 @@ pipelined=false [system.cpu.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -888,7 +888,7 @@ port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -1005,6 +1005,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -1016,7 +1017,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -1024,29 +1025,36 @@ width=16 master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -1066,6 +1074,7 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 @@ -1075,7 +1084,7 @@ p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 page_policy=open_adaptive power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 @@ -1097,9 +1106,9 @@ tRTW=2500 tWR=15000 tWTR=7500 tXAW=30000 -tXP=0 +tXP=6000 tXPDLL=0 -tXS=0 +tXS=270000 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout index 09d4a73db..e9b447feb 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout @@ -3,12 +3,12 @@ Redirecting stderr to build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing- gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 1 2016 17:10:05 -gem5 started Aug 1 2016 17:27:25 -gem5 executing on e108600-lin, pid 12519 +gem5 compiled Oct 11 2016 00:00:58 +gem5 started Oct 13 2016 20:42:58 +gem5 executing on e108600-lin, pid 17311 command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/arm/linux/o3-timing-checker Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 17232500 because target called exit() +Exiting @ tick 18422500 because target called exit() diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt index 012901358..bf47005a8 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000017 # Number of seconds simulated -sim_ticks 17458500 # Number of ticks simulated -final_tick 17458500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000018 # Number of seconds simulated +sim_ticks 18422500 # Number of ticks simulated +final_tick 18422500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 52261 # Simulator instruction rate (inst/s) -host_op_rate 61197 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 198636102 # Simulator tick rate (ticks/s) -host_mem_usage 269760 # Number of bytes of host memory used -host_seconds 0.09 # Real time elapsed on the host +host_inst_rate 65137 # Simulator instruction rate (inst/s) +host_op_rate 76274 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 261240377 # Simulator tick rate (ticks/s) +host_mem_usage 268360 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host sim_insts 4592 # Number of instructions simulated sim_ops 5378 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 17664 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 7744 # Number of bytes read from this memory system.physmem.bytes_read::total 25408 # Number of bytes read from this memory @@ -22,14 +22,14 @@ system.physmem.bytes_inst_read::total 17664 # Nu system.physmem.num_reads::cpu.inst 276 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 121 # Number of read requests responded to by this memory system.physmem.num_reads::total 397 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1011770771 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 443566171 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1455336942 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1011770771 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1011770771 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1011770771 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 443566171 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1455336942 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 958827521 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 420355543 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1379183064 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 958827521 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 958827521 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 958827521 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 420355543 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1379183064 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 397 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 397 # Number of DRAM read bursts, including those serviced by the write queue @@ -76,7 +76,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 17373000 # Total gap between requests +system.physmem.totGap 18337000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -91,12 +91,12 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 209 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 119 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 50 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 16 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 202 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 121 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 54 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 15 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -187,86 +187,96 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 61 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 398.688525 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 264.215339 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 341.944807 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 12 19.67% 19.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 15 24.59% 44.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 9 14.75% 59.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7 11.48% 70.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3 4.92% 75.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2 3.28% 78.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 2 3.28% 81.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2 3.28% 85.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 9 14.75% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 61 # Bytes accessed per row activation -system.physmem.totQLat 3455750 # Total ticks spent queuing -system.physmem.totMemAccLat 10899500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 59 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 407.864407 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 273.934367 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 344.219630 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 10 16.95% 16.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 17 28.81% 45.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 8 13.56% 59.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 7 11.86% 71.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1 1.69% 72.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2 3.39% 76.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 3 5.08% 81.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 3 5.08% 86.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8 13.56% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 59 # Bytes accessed per row activation +system.physmem.totQLat 5196750 # Total ticks spent queuing +system.physmem.totMemAccLat 12640500 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 1985000 # Total ticks spent in databus transfers -system.physmem.avgQLat 8704.66 # Average queueing delay per DRAM burst +system.physmem.avgQLat 13090.05 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27454.66 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1455.34 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 31840.05 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1379.18 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1455.34 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1379.18 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 11.37 # Data bus utilization in percentage -system.physmem.busUtilRead 11.37 # Data bus utilization in percentage for reads +system.physmem.busUtil 10.77 # Data bus utilization in percentage +system.physmem.busUtilRead 10.77 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.88 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.90 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing system.physmem.readRowHits 330 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 83.12 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 43760.71 # Average gap between requests +system.physmem.avgGap 46188.92 # Average gap between requests system.physmem.pageHitRate 83.12 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 294840 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 160875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 2051400 # Energy for read commands per rank (pJ) +system.physmem_0.actEnergy 314160 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 151800 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 2084880 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 10792665 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 32250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 14349150 # Total energy per rank (pJ) -system.physmem_0.averagePower 906.309806 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 11500 # Time in different power states +system.physmem_0.refreshEnergy 1229280.000000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 3077430 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 36000 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 5255970 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 20640 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 12170160 # Total energy per rank (pJ) +system.physmem_0.averagePower 660.613923 # Core power per rank (mW) +system.physmem_0.totalIdleTime 11420000 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 23500 # Time in different power states system.physmem_0.memoryStateTime::REF 520000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 15314750 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 143640 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 78375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 748800 # Energy for read commands per rank (pJ) +system.physmem_0.memoryStateTime::SREF 0 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 53500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 6303750 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 11521750 # Time in different power states +system.physmem_1.actEnergy 164220 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 72105 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 749700 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 10299330 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 466500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 12753765 # Total energy per rank (pJ) -system.physmem_1.averagePower 805.416167 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 734500 # Time in different power states +system.physmem_1.refreshEnergy 1229280.000000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1466040 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 65760 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 6124080 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 616800 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 10487985 # Total energy per rank (pJ) +system.physmem_1.averagePower 569.303026 # Core power per rank (mW) +system.physmem_1.totalIdleTime 14986000 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 116000 # Time in different power states system.physmem_1.memoryStateTime::REF 520000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 14593500 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 2836 # Number of BP lookups -system.cpu.branchPred.condPredicted 1744 # Number of conditional branches predicted +system.physmem_1.memoryStateTime::SREF 0 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 1605250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 2751250 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 13430000 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 2844 # Number of BP lookups +system.cpu.branchPred.condPredicted 1749 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 464 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 2400 # Number of BTB lookups -system.cpu.branchPred.BTBHits 864 # Number of BTB hits +system.cpu.branchPred.BTBLookups 2408 # Number of BTB lookups +system.cpu.branchPred.BTBHits 867 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 36.000000 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 36.004983 # BTB Hit Percentage system.cpu.branchPred.usedRAS 314 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 70 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 265 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 14 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 251 # Number of indirect misses. +system.cpu.branchPred.indirectLookups 266 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 13 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 253 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 63 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.checker.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states +system.cpu.checker.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -296,7 +306,7 @@ system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.checker.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.checker.dtb.walker.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states +system.cpu.checker.dtb.walker.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states system.cpu.checker.dtb.walker.walks 0 # Table walker walks requested system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -326,7 +336,7 @@ system.cpu.checker.dtb.inst_accesses 0 # IT system.cpu.checker.dtb.hits 0 # DTB hits system.cpu.checker.dtb.misses 0 # DTB misses system.cpu.checker.dtb.accesses 0 # DTB accesses -system.cpu.checker.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states +system.cpu.checker.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states system.cpu.checker.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -356,7 +366,7 @@ system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.checker.itb.walker.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states +system.cpu.checker.itb.walker.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states system.cpu.checker.itb.walker.walks 0 # Table walker walks requested system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -387,11 +397,11 @@ system.cpu.checker.itb.hits 0 # DT system.cpu.checker.itb.misses 0 # DTB misses system.cpu.checker.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.checker.pwrStateResidencyTicks::ON 17458500 # Cumulative time (in ticks) in various power states +system.cpu.checker.pwrStateResidencyTicks::ON 18422500 # Cumulative time (in ticks) in various power states system.cpu.checker.numCycles 5391 # number of cpu cycles simulated system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -421,7 +431,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -451,7 +461,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -481,7 +491,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -511,237 +521,237 @@ system.cpu.itb.inst_accesses 0 # IT system.cpu.itb.hits 0 # DTB hits system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses -system.cpu.pwrStateResidencyTicks::ON 17458500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 34918 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 18422500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 36846 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 7601 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 12293 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2836 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 1192 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 4902 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.icacheStallCycles 7661 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 12314 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2844 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 1194 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 5108 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 977 # Number of cycles fetch has spent squashing system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 248 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingTrapStallCycles 260 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 17 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 1960 # Number of cache lines fetched +system.cpu.fetch.CacheLines 1962 # Number of cache lines fetched system.cpu.fetch.IcacheSquashes 282 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 13257 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.116542 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.478893 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 13535 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.094422 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.458272 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 10565 79.69% 79.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 264 1.99% 81.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 184 1.39% 83.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 203 1.53% 84.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 282 2.13% 86.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 396 2.99% 89.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 139 1.05% 90.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 173 1.30% 92.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1051 7.93% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 10839 80.08% 80.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 264 1.95% 82.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 185 1.37% 83.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 204 1.51% 84.91% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 283 2.09% 87.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 398 2.94% 89.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 139 1.03% 90.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 173 1.28% 92.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1050 7.76% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 13257 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.081219 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.352053 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 6292 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 4354 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2143 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 134 # Number of cycles decode is unblocking +system.cpu.fetch.rateDist::total 13535 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.077186 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.334202 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 6279 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 4644 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2146 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 132 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 334 # Number of cycles decode is squashing system.cpu.decode.BranchResolved 431 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 160 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 12137 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 12150 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 489 # Number of squashed instructions handled by decode system.cpu.rename.SquashCycles 334 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 6521 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 773 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 2325 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2036 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 1268 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 11426 # Number of instructions processed by rename +system.cpu.rename.IdleCycles 6511 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 826 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 2470 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2033 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 1361 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 11433 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 4 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 168 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 132 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 1090 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 11634 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 52309 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 12345 # Number of integer rename lookups +system.cpu.rename.IQFullEvents 178 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 144 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 1169 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 11641 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 52345 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 12355 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 199 # Number of floating rename lookups system.cpu.rename.CommittedMaps 5494 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 6140 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 6147 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 40 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 34 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 441 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2200 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1540 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 32 # Number of conflicting loads. +system.cpu.rename.skidInsts 446 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2197 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1543 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 33 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 22 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 10163 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 43 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8100 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 40 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 4828 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 12342 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 6 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 13257 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.610998 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.340069 # Number of insts issued each cycle +system.cpu.iq.iqInstsAdded 10169 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 44 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 8096 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 37 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 4835 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 12334 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 7 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 13535 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.598153 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.329974 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 10033 75.68% 75.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1170 8.83% 84.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 770 5.81% 90.31% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 479 3.61% 93.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 341 2.57% 96.50% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 274 2.07% 98.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 121 0.91% 99.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 59 0.45% 99.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 10 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 10320 76.25% 76.25% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1163 8.59% 84.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 763 5.64% 90.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 482 3.56% 94.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 344 2.54% 96.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 273 2.02% 98.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 120 0.89% 99.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 60 0.44% 99.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 10 0.07% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 13257 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 13535 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 9 6.16% 6.16% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 6.16% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 6.16% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.16% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.16% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.16% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 6.16% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.16% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 6.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 6.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.16% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 65 44.52% 50.68% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 72 49.32% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 9 6.12% 6.12% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 6.12% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 6.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 6.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 6.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 6.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.12% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 66 44.90% 51.02% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 72 48.98% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5026 62.05% 62.05% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 7 0.09% 62.14% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.14% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 5023 62.04% 62.04% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 7 0.09% 62.13% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.13% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.13% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.13% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.13% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.13% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.13% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.13% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 62.17% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.17% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.17% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.17% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1881 23.22% 85.40% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1183 14.60% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 1876 23.17% 85.34% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1187 14.66% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8100 # Type of FU issued -system.cpu.iq.rate 0.231972 # Inst issue rate -system.cpu.iq.fu_busy_cnt 146 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.018025 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 29552 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 14921 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 7399 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 8096 # Type of FU issued +system.cpu.iq.rate 0.219725 # Inst issue rate +system.cpu.iq.fu_busy_cnt 147 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.018157 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 29820 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 14935 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 7404 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 91 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 132 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 32 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 8203 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 8200 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 43 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 23 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1173 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1170 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 19 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 602 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 605 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 31 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.rescheduledLoads 29 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 4 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewSquashCycles 334 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 684 # Number of cycles IEW is blocking +system.cpu.iew.iewBlockCycles 696 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 18 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 10215 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 130 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2200 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1540 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 31 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispatchedInsts 10222 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 131 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2197 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1543 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 32 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 13 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 4 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 19 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 94 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 263 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 357 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 7807 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1773 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 293 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedNotTakenIncorrect 262 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 356 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 7806 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1768 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 290 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 9 # number of nop insts executed -system.cpu.iew.exec_refs 2920 # number of memory reference insts executed -system.cpu.iew.exec_branches 1492 # Number of branches executed -system.cpu.iew.exec_stores 1147 # Number of stores executed -system.cpu.iew.exec_rate 0.223581 # Inst execution rate -system.cpu.iew.wb_sent 7528 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 7431 # cumulative count of insts written-back -system.cpu.iew.wb_producers 3502 # num instructions producing a value -system.cpu.iew.wb_consumers 6830 # num instructions consuming a value -system.cpu.iew.wb_rate 0.212813 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.512738 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 4836 # The number of squashed insts skipped by commit +system.cpu.iew.exec_refs 2921 # number of memory reference insts executed +system.cpu.iew.exec_branches 1491 # Number of branches executed +system.cpu.iew.exec_stores 1153 # Number of stores executed +system.cpu.iew.exec_rate 0.211855 # Inst execution rate +system.cpu.iew.wb_sent 7533 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 7436 # cumulative count of insts written-back +system.cpu.iew.wb_producers 3503 # num instructions producing a value +system.cpu.iew.wb_consumers 6835 # num instructions consuming a value +system.cpu.iew.wb_rate 0.201813 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.512509 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 4843 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 310 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 12404 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.433570 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.278209 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 12682 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.424066 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.266213 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 10353 83.47% 83.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 884 7.13% 90.59% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 420 3.39% 93.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 217 1.75% 95.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 107 0.86% 96.59% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 220 1.77% 98.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 55 0.44% 98.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 39 0.31% 99.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 109 0.88% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 10636 83.87% 83.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 879 6.93% 90.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 416 3.28% 94.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 218 1.72% 95.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 111 0.88% 96.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 220 1.73% 98.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 54 0.43% 98.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 39 0.31% 99.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 109 0.86% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 12404 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 12682 # Number of insts commited each cycle system.cpu.commit.committedInsts 4592 # Number of instructions committed system.cpu.commit.committedOps 5378 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -788,52 +798,52 @@ system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Cl system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 5378 # Class of committed instruction system.cpu.commit.bw_lim_events 109 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 22352 # The number of ROB reads -system.cpu.rob.rob_writes 21294 # The number of ROB writes +system.cpu.rob.rob_reads 22637 # The number of ROB reads +system.cpu.rob.rob_writes 21308 # The number of ROB writes system.cpu.timesIdled 191 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 21661 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 23311 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 4592 # Number of Instructions Simulated system.cpu.committedOps 5378 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 7.604094 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.604094 # CPI: Total CPI of All Threads -system.cpu.ipc 0.131508 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.131508 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 7649 # number of integer regfile reads -system.cpu.int_regfile_writes 4266 # number of integer regfile writes +system.cpu.cpi 8.023955 # CPI: Cycles Per Instruction +system.cpu.cpi_total 8.023955 # CPI: Total CPI of All Threads +system.cpu.ipc 0.124627 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.124627 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 7656 # number of integer regfile reads +system.cpu.int_regfile_writes 4268 # number of integer regfile writes system.cpu.fp_regfile_reads 32 # number of floating regfile reads system.cpu.cc_regfile_reads 27780 # number of cc regfile reads system.cpu.cc_regfile_writes 3273 # number of cc regfile writes -system.cpu.misc_regfile_reads 2976 # number of misc regfile reads +system.cpu.misc_regfile_reads 2974 # number of misc regfile reads system.cpu.misc_regfile_writes 24 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 88.222961 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2096 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 88.014551 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2093 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 147 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 14.258503 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 14.238095 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 88.222961 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.021539 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.021539 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 88.014551 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.021488 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.021488 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 147 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 92 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.035889 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 5341 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 5341 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 1478 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1478 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 5335 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 5335 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 1475 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1475 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 597 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 597 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 10 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 10 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 2075 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2075 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2075 # number of overall hits -system.cpu.dcache.overall_hits::total 2075 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 2072 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2072 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2072 # number of overall hits +system.cpu.dcache.overall_hits::total 2072 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 183 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 183 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 316 # number of WriteReq misses @@ -844,53 +854,53 @@ system.cpu.dcache.demand_misses::cpu.data 499 # n system.cpu.dcache.demand_misses::total 499 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 499 # number of overall misses system.cpu.dcache.overall_misses::total 499 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 10847000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 10847000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 22859500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 22859500 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 144000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 144000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 33706500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 33706500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 33706500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 33706500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1661 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1661 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11345000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11345000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 24463500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 24463500 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 156000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 156000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 35808500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 35808500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 35808500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 35808500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1658 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1658 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 12 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 12 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2574 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2574 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2574 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2574 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.110175 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.110175 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2571 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2571 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2571 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2571 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.110374 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.110374 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.346112 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.346112 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.166667 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.166667 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.193862 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.193862 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.193862 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.193862 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59273.224044 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 59273.224044 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 72340.189873 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 72340.189873 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 72000 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 72000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 67548.096192 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 67548.096192 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 67548.096192 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 67548.096192 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 147 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.194088 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.194088 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.194088 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.194088 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 61994.535519 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 61994.535519 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 77416.139241 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 77416.139241 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 78000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 78000 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 71760.521042 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 71760.521042 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 71760.521042 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 71760.521042 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 159 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 49 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 53 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.ReadReq_mshr_hits::cpu.data 78 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 78 # number of ReadReq MSHR hits @@ -910,140 +920,140 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 147 system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7089000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 7089000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3440000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3440000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10529000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10529000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10529000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10529000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.063215 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.063215 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7355500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 7355500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3668000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3668000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11023500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 11023500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11023500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 11023500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.063329 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.063329 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046002 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046002 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.057110 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.057110 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.057110 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.057110 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 67514.285714 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 67514.285714 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 81904.761905 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 81904.761905 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71625.850340 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 71625.850340 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71625.850340 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 71625.850340 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.057176 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.057176 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.057176 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.057176 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 70052.380952 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 70052.380952 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 87333.333333 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 87333.333333 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74989.795918 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 74989.795918 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74989.795918 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 74989.795918 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 2 # number of replacements -system.cpu.icache.tags.tagsinuse 149.958367 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1576 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 149.507349 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1577 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 294 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 5.360544 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 5.363946 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 149.958367 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.073222 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.073222 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 149.507349 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.073002 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.073002 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 292 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 166 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 126 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 161 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.142578 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 4214 # Number of tag accesses -system.cpu.icache.tags.data_accesses 4214 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 1576 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1576 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1576 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1576 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1576 # number of overall hits -system.cpu.icache.overall_hits::total 1576 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 384 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 384 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 384 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 384 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 384 # number of overall misses -system.cpu.icache.overall_misses::total 384 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 27225000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 27225000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 27225000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 27225000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 27225000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 27225000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1960 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1960 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1960 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1960 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1960 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1960 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.195918 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.195918 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.195918 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.195918 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.195918 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.195918 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70898.437500 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 70898.437500 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 70898.437500 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 70898.437500 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 70898.437500 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 70898.437500 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 433 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 4218 # Number of tag accesses +system.cpu.icache.tags.data_accesses 4218 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 1577 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1577 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1577 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1577 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1577 # number of overall hits +system.cpu.icache.overall_hits::total 1577 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 385 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 385 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 385 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 385 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 385 # number of overall misses +system.cpu.icache.overall_misses::total 385 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 28997500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 28997500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 28997500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 28997500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 28997500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 28997500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1962 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1962 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1962 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1962 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1962 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1962 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.196228 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.196228 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.196228 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.196228 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.196228 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.196228 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75318.181818 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 75318.181818 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 75318.181818 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 75318.181818 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 75318.181818 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 75318.181818 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 493 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 86.600000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 98.600000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.writebacks::writebacks 2 # number of writebacks system.cpu.icache.writebacks::total 2 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 90 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 90 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 90 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 90 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 90 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 90 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 91 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 91 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 91 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 91 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 91 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 91 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 294 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 294 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 294 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 294 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 294 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 294 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22193500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 22193500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22193500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 22193500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22193500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 22193500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.150000 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.150000 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.150000 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.150000 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.150000 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.150000 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75488.095238 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75488.095238 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75488.095238 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 75488.095238 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75488.095238 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 75488.095238 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23482000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 23482000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23482000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 23482000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23482000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 23482000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.149847 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.149847 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.149847 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.149847 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.149847 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.149847 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 79870.748299 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 79870.748299 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 79870.748299 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 79870.748299 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 79870.748299 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 79870.748299 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 215.001500 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 214.408451 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 39 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 397 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.098237 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 140.723037 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 74.278463 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004295 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.002267 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.006561 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 140.281348 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 74.127103 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004281 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.002262 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.006543 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 397 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 200 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 197 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 195 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 202 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012115 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 3933 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 3933 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackClean_hits::writebacks 1 # number of WritebackClean hits system.cpu.l2cache.WritebackClean_hits::total 1 # number of WritebackClean hits system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 18 # number of ReadCleanReq hits @@ -1068,18 +1078,18 @@ system.cpu.l2cache.demand_misses::total 403 # nu system.cpu.l2cache.overall_misses::cpu.inst 276 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 127 # number of overall misses system.cpu.l2cache.overall_misses::total 403 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3375000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 3375000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 21544500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 21544500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 6694500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 6694500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 21544500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 10069500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 31614000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 21544500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 10069500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 31614000 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3603000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 3603000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 22833000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 22833000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 6961000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 6961000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 22833000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 10564000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 33397000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 22833000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 10564000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 33397000 # number of overall miss cycles system.cpu.l2cache.WritebackClean_accesses::writebacks 1 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::total 1 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 42 # number of ReadExReq accesses(hits+misses) @@ -1106,18 +1116,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.913832 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.938776 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.863946 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.913832 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80357.142857 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80357.142857 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 78059.782609 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 78059.782609 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 78758.823529 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 78758.823529 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 78059.782609 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79287.401575 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 78446.650124 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 78059.782609 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79287.401575 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 78446.650124 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 85785.714286 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 85785.714286 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82728.260870 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82728.260870 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 81894.117647 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 81894.117647 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82728.260870 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 83181.102362 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 82870.967742 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82728.260870 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83181.102362 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 82870.967742 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1142,18 +1152,18 @@ system.cpu.l2cache.demand_mshr_misses::total 397 system.cpu.l2cache.overall_mshr_misses::cpu.inst 276 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 121 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 397 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2955000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2955000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 18784500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 18784500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5499000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5499000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18784500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8454000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 27238500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18784500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8454000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 27238500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3183000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3183000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 20073000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 20073000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5729500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5729500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 20073000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8912500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 28985500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 20073000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8912500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 28985500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.938776 # mshr miss rate for ReadCleanReq accesses @@ -1166,25 +1176,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.900227 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.938776 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.823129 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.900227 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70357.142857 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70357.142857 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 68059.782609 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 68059.782609 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 69607.594937 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 69607.594937 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68059.782609 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69867.768595 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68610.831234 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68059.782609 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69867.768595 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68610.831234 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 75785.714286 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 75785.714286 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72728.260870 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72728.260870 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72525.316456 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72525.316456 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72728.260870 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73657.024793 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73011.335013 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72728.260870 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73657.024793 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73011.335013 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 443 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 45 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 399 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 2 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 42 # Transaction distribution @@ -1211,18 +1221,18 @@ system.cpu.toL2Bus.snoop_fanout::min_value 0 # system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 441 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 223500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%) +system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 441000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.5 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.utilization 2.4 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 223494 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) system.membus.snoop_filter.tot_requests 397 # Total number of requests made to the snoop filter. system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 355 # Transaction distribution system.membus.trans_dist::ReadExReq 42 # Transaction distribution system.membus.trans_dist::ReadExResp 42 # Transaction distribution @@ -1243,9 +1253,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 397 # Request fanout histogram -system.membus.reqLayer0.occupancy 488000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 2102000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 12.0 # Layer utilization (%) +system.membus.reqLayer0.occupancy 486500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.6 # Layer utilization (%) +system.membus.respLayer1.occupancy 2098750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 11.4 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini index 9180fbc8c..4a82d75c8 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini @@ -172,7 +172,7 @@ useIndirect=true [system.cpu.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -534,7 +534,7 @@ pipelined=true [system.cpu.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -666,7 +666,7 @@ port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=Cache children=prefetcher tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=16 clk_domain=system.cpu_clk_domain clusivity=mostly_excl @@ -813,6 +813,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -824,7 +825,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -832,29 +833,36 @@ width=16 master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -874,6 +882,7 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 @@ -883,7 +892,7 @@ p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 page_policy=open_adaptive power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 @@ -905,9 +914,9 @@ tRTW=2500 tWR=15000 tWTR=7500 tXAW=30000 -tXP=0 +tXP=6000 tXPDLL=0 -tXS=0 +tXS=270000 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout index 9e032676c..81299f400 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout @@ -3,12 +3,12 @@ Redirecting stderr to build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing/ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 1 2016 17:10:05 -gem5 started Aug 1 2016 17:10:34 -gem5 executing on e108600-lin, pid 12211 +gem5 compiled Oct 11 2016 00:00:58 +gem5 started Oct 13 2016 20:52:56 +gem5 executing on e108600-lin, pid 17478 command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 18821000 because target called exit() +Exiting @ tick 20299000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt index bfd96912f..867d50715 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt @@ -1,39 +1,39 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000019 # Number of seconds simulated -sim_ticks 19046000 # Number of ticks simulated -final_tick 19046000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000020 # Number of seconds simulated +sim_ticks 20299000 # Number of ticks simulated +final_tick 20299000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 51970 # Simulator instruction rate (inst/s) -host_op_rate 60857 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 215490046 # Simulator tick rate (ticks/s) -host_mem_usage 266056 # Number of bytes of host memory used -host_seconds 0.09 # Real time elapsed on the host +host_inst_rate 44590 # Simulator instruction rate (inst/s) +host_op_rate 52212 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 197038809 # Simulator tick rate (ticks/s) +host_mem_usage 265156 # Number of bytes of host memory used +host_seconds 0.10 # Real time elapsed on the host sim_insts 4592 # Number of instructions simulated sim_ops 5378 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 19046000 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 20299000 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 18560 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 8192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 8128 # Number of bytes read from this memory system.physmem.bytes_read::cpu.l2cache.prefetcher 1728 # Number of bytes read from this memory -system.physmem.bytes_read::total 28480 # Number of bytes read from this memory +system.physmem.bytes_read::total 28416 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 18560 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 18560 # Number of instructions bytes read from this memory system.physmem.num_reads::cpu.inst 290 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 128 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 127 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.l2cache.prefetcher 27 # Number of read requests responded to by this memory -system.physmem.num_reads::total 445 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 974482831 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 430116560 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 90727712 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1495327103 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 974482831 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 974482831 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 974482831 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 430116560 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 90727712 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1495327103 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_reads::total 444 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 914330755 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 400413813 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 85127346 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1399871915 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 914330755 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 914330755 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 914330755 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 400413813 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 85127346 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1399871915 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 445 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 445 # Number of DRAM read bursts, including those serviced by the write queue @@ -80,7 +80,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 19004500 # Total gap between requests +system.physmem.totGap 20257500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -95,12 +95,12 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 246 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 132 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 35 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 15 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 241 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 137 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 36 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 16 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 2 # What read queue length does an incoming req see @@ -191,86 +191,96 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 63 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 429.714286 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 289.613657 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 357.341954 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 8 12.70% 12.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 17 26.98% 39.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 11 17.46% 57.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 6 9.52% 66.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3 4.76% 71.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2 3.17% 74.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 2 3.17% 77.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2 3.17% 80.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 12 19.05% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 63 # Bytes accessed per row activation -system.physmem.totQLat 4296708 # Total ticks spent queuing -system.physmem.totMemAccLat 12640458 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 62 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 435.612903 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 295.342416 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 353.563376 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 8 12.90% 12.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 16 25.81% 38.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 10 16.13% 54.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 7 11.29% 66.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2 3.23% 69.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 3 4.84% 74.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 2 3.23% 77.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 4 6.45% 83.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 10 16.13% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 62 # Bytes accessed per row activation +system.physmem.totQLat 6110750 # Total ticks spent queuing +system.physmem.totMemAccLat 14454500 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2225000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9655.52 # Average queueing delay per DRAM burst +system.physmem.avgQLat 13732.02 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28405.52 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1495.33 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 32482.02 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1403.02 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1495.33 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1403.02 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 11.68 # Data bus utilization in percentage -system.physmem.busUtilRead 11.68 # Data bus utilization in percentage for reads +system.physmem.busUtil 10.96 # Data bus utilization in percentage +system.physmem.busUtilRead 10.96 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.86 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.84 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing system.physmem.readRowHits 373 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 83.82 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 42706.74 # Average gap between requests +system.physmem.avgGap 45522.47 # Average gap between requests system.physmem.pageHitRate 83.82 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 287280 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 156750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 2152800 # Energy for read commands per rank (pJ) +system.physmem_0.actEnergy 349860 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 170775 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 2334780 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 10689210 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 123000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 14426160 # Total energy per rank (pJ) -system.physmem_0.averagePower 911.173851 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 148750 # Time in different power states +system.physmem_0.refreshEnergy 1229280.000000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 3572760 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 28800 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 5648700 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 960 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 13335915 # Total energy per rank (pJ) +system.physmem_0.averagePower 656.941626 # Core power per rank (mW) +system.physmem_0.totalIdleTime 12232500 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 19000 # Time in different power states system.physmem_0.memoryStateTime::REF 520000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 15177500 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 128520 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 70125 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 811200 # Energy for read commands per rank (pJ) +system.physmem_0.memoryStateTime::SREF 0 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 2500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 7376750 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 12380750 # Time in different power states +system.physmem_1.actEnergy 164220 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 64515 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 842520 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 10733670 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 84000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 12844635 # Total energy per rank (pJ) -system.physmem_1.averagePower 811.282804 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1145250 # Time in different power states +system.physmem_1.refreshEnergy 1229280.000000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1468320 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 69120 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 7424250 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 237600 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 11499825 # Total energy per rank (pJ) +system.physmem_1.averagePower 566.493842 # Core power per rank (mW) +system.physmem_1.totalIdleTime 16895250 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 110000 # Time in different power states system.physmem_1.memoryStateTime::REF 520000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 15228250 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 19046000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 2439 # Number of BP lookups -system.cpu.branchPred.condPredicted 1443 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 524 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 915 # Number of BTB lookups -system.cpu.branchPred.BTBHits 448 # Number of BTB hits +system.physmem_1.memoryStateTime::SREF 0 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 618500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 2773750 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 16276750 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 20299000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 2441 # Number of BP lookups +system.cpu.branchPred.condPredicted 1444 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 522 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 916 # Number of BTB lookups +system.cpu.branchPred.BTBHits 449 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 48.961749 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 49.017467 # BTB Hit Percentage system.cpu.branchPred.usedRAS 286 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 57 # Number of incorrect RAS predictions. system.cpu.branchPred.indirectLookups 163 # Number of indirect predictor lookups. system.cpu.branchPred.indirectHits 13 # Number of indirect target hits. system.cpu.branchPred.indirectMisses 150 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 60 # Number of mispredicted indirect branches. +system.cpu.branchPredindirectMispredicted 59 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 19046000 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 20299000 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -300,7 +310,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 19046000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 20299000 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -330,7 +340,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 19046000 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 20299000 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -360,7 +370,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 19046000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 20299000 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -391,85 +401,85 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 19046000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 38093 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 20299000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 40599 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 6117 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.icacheStallCycles 6170 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.Insts 11468 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2439 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 747 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 8723 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1091 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 171 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 274 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 416 # Number of stall cycles due to full MSHR +system.cpu.fetch.Branches 2441 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 748 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 8322 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1087 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 161 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 286 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 434 # Number of stall cycles due to full MSHR system.cpu.fetch.CacheLines 3907 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 178 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 16246 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.839530 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.200509 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheSquashes 179 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 15916 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.856748 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.206522 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 9855 60.66% 60.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2507 15.43% 76.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 520 3.20% 79.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 3364 20.71% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 9525 59.85% 59.85% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2508 15.76% 75.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 521 3.27% 78.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 3362 21.12% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 16246 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.064028 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.301053 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 5842 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 4705 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 5178 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 135 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 386 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 375 # Number of times decode resolved a branch +system.cpu.fetch.rateDist::total 15916 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.060125 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.282470 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 5812 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 4409 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 5179 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 132 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 384 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 374 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 162 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 10177 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 1679 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 386 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 6957 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 1136 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 2347 # count of cycles rename stalled for serializing inst +system.cpu.decode.DecodedInsts 10178 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 1683 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 384 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 6925 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 1165 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 2515 # count of cycles rename stalled for serializing inst system.cpu.rename.RunCycles 4188 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 1232 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 9097 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 461 # Number of squashed instructions processed by rename +system.cpu.rename.UnblockCycles 739 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 9100 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 467 # Number of squashed instructions processed by rename system.cpu.rename.ROBFullEvents 24 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 1 # Number of times rename has blocked due to IQ full system.cpu.rename.LQFullEvents 28 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 1125 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 9457 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 41127 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 9997 # Number of integer rename lookups +system.cpu.rename.SQFullEvents 631 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 9458 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 41150 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 10006 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 17 # Number of floating rename lookups system.cpu.rename.CommittedMaps 5494 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 3963 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 3964 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 29 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 27 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 333 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 1824 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1284 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.skidInsts 330 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 1823 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1289 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 8515 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 8513 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 38 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 7229 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 177 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 3175 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqInstsIssued 7228 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 182 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 3173 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedOperandsExamined 8254 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 1 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 16246 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.444971 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 0.838160 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 15916 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.454134 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.844472 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 11980 73.74% 73.74% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1997 12.29% 86.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 1618 9.96% 95.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 608 3.74% 99.74% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 43 0.26% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 11653 73.22% 73.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1992 12.52% 85.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 1620 10.18% 95.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 608 3.82% 99.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 43 0.27% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle @@ -477,147 +487,147 @@ system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Nu system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 4 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 16246 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 15916 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 416 28.89% 28.89% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 28.89% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 28.89% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 28.89% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 28.89% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 28.89% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 28.89% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 28.89% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 28.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 28.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 28.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 28.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 28.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 28.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 28.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 28.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 28.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 28.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 28.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 28.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 28.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 28.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 28.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 28.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 28.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 28.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 28.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 28.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 28.89% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 475 32.99% 61.87% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 549 38.12% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 416 28.85% 28.85% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 28.85% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 28.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 28.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 28.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 28.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 28.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 28.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 28.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 28.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 28.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 28.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 28.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 28.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 28.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 28.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 28.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 28.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 28.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 28.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 28.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 28.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 28.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 28.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 28.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 28.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 28.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 28.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 28.85% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 475 32.94% 61.79% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 551 38.21% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 4534 62.72% 62.72% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 5 0.07% 62.79% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.79% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.79% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.79% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.79% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.79% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.79% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.79% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 4533 62.71% 62.71% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 5 0.07% 62.78% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.78% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.78% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.78% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.78% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.78% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.78% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.78% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 62.83% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.83% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.83% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.83% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1606 22.22% 85.05% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1081 14.95% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 1605 22.21% 85.03% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1082 14.97% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 7229 # Type of FU issued -system.cpu.iq.rate 0.189772 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1440 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.199198 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 32277 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 11719 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 6614 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 7228 # Type of FU issued +system.cpu.iq.rate 0.178034 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1442 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.199502 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 31952 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 11715 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 6617 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 44 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 8641 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 8642 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 28 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 12 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 797 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 796 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 7 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 346 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 351 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 7 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 18 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 386 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 339 # Number of cycles IEW is blocking +system.cpu.iew.iewSquashCycles 384 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 345 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 11 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 8566 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispatchedInsts 8564 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 1824 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1284 # Number of dispatched store instructions +system.cpu.iew.iewDispLoadInsts 1823 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1289 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 26 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 6 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 7 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 59 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 319 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 60 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 318 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 378 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 6820 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1423 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 409 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 6821 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1422 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 407 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 13 # number of nop insts executed -system.cpu.iew.exec_refs 2448 # number of memory reference insts executed -system.cpu.iew.exec_branches 1296 # Number of branches executed +system.cpu.iew.exec_refs 2447 # number of memory reference insts executed +system.cpu.iew.exec_branches 1298 # Number of branches executed system.cpu.iew.exec_stores 1025 # Number of stores executed -system.cpu.iew.exec_rate 0.179036 # Inst execution rate -system.cpu.iew.wb_sent 6675 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 6630 # cumulative count of insts written-back -system.cpu.iew.wb_producers 2985 # num instructions producing a value -system.cpu.iew.wb_consumers 5422 # num instructions consuming a value -system.cpu.iew.wb_rate 0.174048 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.550535 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 2710 # The number of squashed insts skipped by commit +system.cpu.iew.exec_rate 0.168009 # Inst execution rate +system.cpu.iew.wb_sent 6677 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 6633 # cumulative count of insts written-back +system.cpu.iew.wb_producers 2981 # num instructions producing a value +system.cpu.iew.wb_consumers 5419 # num instructions consuming a value +system.cpu.iew.wb_rate 0.163378 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.550101 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 2706 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 365 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 15677 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.343050 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 0.979995 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 363 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 15349 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.350381 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 0.988718 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 13011 82.99% 82.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1405 8.96% 91.96% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 598 3.81% 95.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 299 1.91% 97.68% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 169 1.08% 98.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 80 0.51% 99.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 44 0.28% 99.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 28 0.18% 99.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 43 0.27% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 12681 82.62% 82.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1407 9.17% 91.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 599 3.90% 95.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 298 1.94% 97.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 170 1.11% 98.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 79 0.51% 99.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 44 0.29% 99.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 28 0.18% 99.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 43 0.28% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 15677 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 15349 # Number of insts commited each cycle system.cpu.commit.committedInsts 4592 # Number of instructions committed system.cpu.commit.committedOps 5378 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -664,40 +674,40 @@ system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Cl system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 5378 # Class of committed instruction system.cpu.commit.bw_lim_events 43 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 23565 # The number of ROB reads -system.cpu.rob.rob_writes 16751 # The number of ROB writes -system.cpu.timesIdled 216 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 21847 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 23233 # The number of ROB reads +system.cpu.rob.rob_writes 16740 # The number of ROB writes +system.cpu.timesIdled 212 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 24683 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 4592 # Number of Instructions Simulated system.cpu.committedOps 5378 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 8.295514 # CPI: Cycles Per Instruction -system.cpu.cpi_total 8.295514 # CPI: Total CPI of All Threads -system.cpu.ipc 0.120547 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.120547 # IPC: Total IPC of All Threads +system.cpu.cpi 8.841246 # CPI: Cycles Per Instruction +system.cpu.cpi_total 8.841246 # CPI: Total CPI of All Threads +system.cpu.ipc 0.113106 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.113106 # IPC: Total IPC of All Threads system.cpu.int_regfile_reads 6772 # number of integer regfile reads system.cpu.int_regfile_writes 3788 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.cc_regfile_reads 24217 # number of cc regfile reads +system.cpu.cc_regfile_reads 24220 # number of cc regfile reads system.cpu.cc_regfile_writes 2924 # number of cc regfile writes system.cpu.misc_regfile_reads 2559 # number of misc regfile reads system.cpu.misc_regfile_writes 24 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 19046000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 20299000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 1 # number of replacements -system.cpu.dcache.tags.tagsinuse 84.349867 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 84.063183 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1930 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 143 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 13.496503 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 84.349867 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.164746 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.164746 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 84.063183 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.164186 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.164186 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 142 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 89 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 90 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.277344 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 4725 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 4725 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 19046000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.tag_accesses 4723 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 4723 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 20299000 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 1188 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1188 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 722 # number of WriteReq hits @@ -710,76 +720,76 @@ system.cpu.dcache.demand_hits::cpu.data 1910 # nu system.cpu.dcache.demand_hits::total 1910 # number of demand (read+write) hits system.cpu.dcache.overall_hits::cpu.data 1910 # number of overall hits system.cpu.dcache.overall_hits::total 1910 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 168 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 168 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::cpu.data 167 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 167 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 191 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 191 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 359 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 359 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 359 # number of overall misses -system.cpu.dcache.overall_misses::total 359 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 10937500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 10937500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 9601000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 9601000 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 127000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 127000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 20538500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 20538500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 20538500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 20538500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1356 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1356 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 358 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 358 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 358 # number of overall misses +system.cpu.dcache.overall_misses::total 358 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 12032500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 12032500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 8019500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 8019500 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 139000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 139000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 20052000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 20052000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 20052000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 20052000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1355 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1355 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2269 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2269 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2269 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2269 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.123894 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.123894 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2268 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2268 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2268 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2268 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.123247 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.123247 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.209200 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.209200 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.181818 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.181818 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.158219 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.158219 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.158219 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.158219 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 65104.166667 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 65104.166667 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 50267.015707 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 50267.015707 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 63500 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 63500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 57210.306407 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 57210.306407 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 57210.306407 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 57210.306407 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.157848 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.157848 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.157848 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.157848 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 72050.898204 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 72050.898204 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41986.910995 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 41986.910995 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 69500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 69500 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 56011.173184 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 56011.173184 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 56011.173184 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 56011.173184 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 1304 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 853 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 18 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 72.444444 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 47.388889 # average number of cycles each access was blocked system.cpu.dcache.writebacks::writebacks 1 # number of writebacks system.cpu.dcache.writebacks::total 1 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 65 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 65 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 64 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 64 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 150 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 150 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 215 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 215 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 215 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 215 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 214 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 214 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 214 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 214 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 103 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 103 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 41 # number of WriteReq MSHR misses @@ -788,140 +798,140 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 144 system.cpu.dcache.demand_mshr_misses::total 144 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 144 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 144 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7149000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 7149000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2700500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2700500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9849500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9849500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9849500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 9849500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075959 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075959 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7984500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 7984500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2595500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2595500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10580000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10580000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10580000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10580000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076015 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076015 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044907 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044907 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.063464 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.063464 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.063464 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.063464 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 69407.766990 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 69407.766990 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 65865.853659 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 65865.853659 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68399.305556 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 68399.305556 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68399.305556 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 68399.305556 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 19046000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.063492 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.063492 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.063492 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.063492 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77519.417476 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77519.417476 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 63304.878049 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 63304.878049 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73472.222222 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 73472.222222 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73472.222222 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 73472.222222 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 20299000 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 44 # number of replacements -system.cpu.icache.tags.tagsinuse 137.872552 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 3542 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 137.515573 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 3540 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 299 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 11.846154 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 11.839465 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 137.872552 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.269282 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.269282 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 137.515573 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.268585 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.268585 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 255 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 155 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 100 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 145 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 110 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.498047 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 8107 # Number of tag accesses -system.cpu.icache.tags.data_accesses 8107 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 19046000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 3542 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 3542 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 3542 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 3542 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 3542 # number of overall hits -system.cpu.icache.overall_hits::total 3542 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 362 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 362 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 362 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 362 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 362 # number of overall misses -system.cpu.icache.overall_misses::total 362 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 22563992 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 22563992 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 22563992 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 22563992 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 22563992 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 22563992 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 3904 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 3904 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 3904 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 3904 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 3904 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 3904 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.092725 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.092725 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.092725 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.092725 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.092725 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.092725 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62331.469613 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 62331.469613 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 62331.469613 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 62331.469613 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 62331.469613 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 62331.469613 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 8558 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 35 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 95 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 8109 # Number of tag accesses +system.cpu.icache.tags.data_accesses 8109 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 20299000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 3540 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 3540 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 3540 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 3540 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 3540 # number of overall hits +system.cpu.icache.overall_hits::total 3540 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 365 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 365 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 365 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 365 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 365 # number of overall misses +system.cpu.icache.overall_misses::total 365 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 25051490 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 25051490 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 25051490 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 25051490 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 25051490 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 25051490 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 3905 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 3905 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 3905 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 3905 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 3905 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 3905 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.093470 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.093470 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.093470 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.093470 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.093470 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.093470 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68634.219178 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 68634.219178 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 68634.219178 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 68634.219178 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 68634.219178 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 68634.219178 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 9850 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 47 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 96 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 90.084211 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 35 # 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number of ReadSharedReq MSHR hits system.cpu.l2cache.ReadSharedReq_mshr_hits::total 5 # number of ReadSharedReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 6 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 7 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 5 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 6 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 6 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 7 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 5 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 6 # number of overall MSHR hits system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 53 # number of HardPFReq MSHR misses system.cpu.l2cache.HardPFReq_mshr_misses::total 53 # number of HardPFReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 30 # number of ReadExReq MSHR misses @@ -1040,21 +1048,21 @@ system.cpu.l2cache.overall_mshr_misses::cpu.inst 290 system.cpu.l2cache.overall_mshr_misses::cpu.data 128 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 53 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 471 # number of overall MSHR misses -system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 3053926 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 3053926 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2154000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2154000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 17682000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 17682000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6104000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 6104000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17682000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8258000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 25940000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17682000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8258000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 3053926 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 28993926 # number of overall MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 1766926 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 1766926 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2281000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2281000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 19850000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 19850000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6909500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 6909500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19850000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9190500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 29040500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19850000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9190500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 1766926 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 30807426 # number of overall MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.731707 # mshr miss rate for ReadExReq accesses @@ -1070,28 +1078,28 @@ system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.969900 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.888889 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 1.063205 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 57621.245283 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 57621.245283 # average HardPFReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71800 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71800 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 60972.413793 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 60972.413793 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 62285.714286 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 62285.714286 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60972.413793 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64515.625000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62057.416268 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60972.413793 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64515.625000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 57621.245283 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61558.229299 # average overall mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 33338.226415 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 33338.226415 # average HardPFReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 76033.333333 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 76033.333333 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 68448.275862 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 68448.275862 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70505.102041 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70505.102041 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68448.275862 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71800.781250 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69474.880383 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68448.275862 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71800.781250 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 33338.226415 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65408.547771 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 488 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 74 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 12 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 26 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 24 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 2 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 19046000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 20299000 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 401 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 45 # Transaction distribution system.cpu.toL2Bus.trans_dist::HardPFReq 69 # Transaction distribution @@ -1119,9 +1127,9 @@ system.cpu.toL2Bus.snoop_fanout::min_value 0 # system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 512 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 289000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.5 # Layer utilization (%) +system.cpu.toL2Bus.reqLayer0.utilization 1.4 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 448999 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.4 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.utilization 2.2 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 216995 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) system.membus.snoop_filter.tot_requests 445 # Total number of requests made to the snoop filter. @@ -1130,7 +1138,7 @@ system.membus.snoop_filter.hit_multi_requests 0 system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 19046000 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 20299000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 414 # Transaction distribution system.membus.trans_dist::ReadExReq 30 # Transaction distribution system.membus.trans_dist::ReadExResp 30 # Transaction distribution @@ -1151,9 +1159,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 445 # Request fanout histogram -system.membus.reqLayer0.occupancy 562944 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 3.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 2340257 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 12.3 # Layer utilization (%) +system.membus.reqLayer0.occupancy 564444 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.8 # Layer utilization (%) +system.membus.respLayer1.occupancy 2334750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 11.5 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini index fb58e2bf8..1e3a930b1 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini @@ -173,7 +173,7 @@ useIndirect=true [system.cpu.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -531,7 +531,7 @@ pipelined=false [system.cpu.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -593,7 +593,7 @@ size=64 [system.cpu.l2cache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -710,6 +710,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -721,7 +722,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -729,29 +730,36 @@ width=16 master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -771,6 +779,7 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 @@ -780,7 +789,7 @@ p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 page_policy=open_adaptive power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 @@ -802,9 +811,9 @@ tRTW=2500 tWR=15000 tWTR=7500 tXAW=30000 -tXP=0 +tXP=6000 tXPDLL=0 -tXS=0 +tXS=270000 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout index 8c26880d3..fa28c822f 100755 --- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout @@ -3,13 +3,13 @@ Redirecting stderr to build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timin gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:23:13 -gem5 started Jul 21 2016 14:23:47 -gem5 executing on e108600-lin, pid 13281 +gem5 compiled Oct 13 2016 20:36:34 +gem5 started Oct 13 2016 20:36:59 +gem5 executing on e108600-lin, pid 36840 command line: /work/curdun01/gem5-external.hg/build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/mips/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello World! -Exiting @ tick 22532000 because target called exit() +Exiting @ tick 24405000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt index fce732112..fb05a48a7 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000023 # Number of seconds simulated -sim_ticks 22838000 # Number of ticks simulated -final_tick 22838000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000024 # Number of seconds simulated +sim_ticks 24405000 # Number of ticks simulated +final_tick 24405000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 76246 # Simulator instruction rate (inst/s) -host_op_rate 76230 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 348191953 # Simulator tick rate (ticks/s) -host_mem_usage 252304 # Number of bytes of host memory used -host_seconds 0.07 # Real time elapsed on the host +host_inst_rate 101939 # Simulator instruction rate (inst/s) +host_op_rate 101907 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 497362491 # Simulator tick rate (ticks/s) +host_mem_usage 250452 # Number of bytes of host memory used +host_seconds 0.05 # Real time elapsed on the host sim_insts 4999 # Number of instructions simulated sim_ops 4999 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 22838000 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 24405000 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 21056 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 8960 # Number of bytes read from this memory system.physmem.bytes_read::total 30016 # Number of bytes read from this memory @@ -22,14 +22,14 @@ system.physmem.bytes_inst_read::total 21056 # Nu system.physmem.num_reads::cpu.inst 329 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 140 # Number of read requests responded to by this memory system.physmem.num_reads::total 469 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 921972152 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 392328575 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1314300727 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 921972152 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 921972152 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 921972152 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 392328575 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1314300727 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 862774022 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 367137882 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1229911903 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 862774022 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 862774022 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 862774022 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 367137882 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1229911903 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 469 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 469 # Number of DRAM read bursts, including those serviced by the write queue @@ -76,7 +76,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 22751500 # Total gap between requests +system.physmem.totGap 24305500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -91,11 +91,11 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 276 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 130 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 41 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 270 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 135 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 40 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 17 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -187,83 +187,94 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 105 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 259.047619 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 178.738362 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 250.145511 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 30 28.57% 28.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 33 31.43% 60.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 19 18.10% 78.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 9 8.57% 86.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 4 3.81% 90.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2 1.90% 92.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 2 1.90% 94.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 6 5.71% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 105 # Bytes accessed per row activation -system.physmem.totQLat 4619250 # Total ticks spent queuing -system.physmem.totMemAccLat 13413000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 114 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 261.614035 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 175.762153 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 255.654479 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 36 31.58% 31.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 34 29.82% 61.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 19 16.67% 78.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 8 7.02% 85.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 4 3.51% 88.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2 1.75% 90.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 4 3.51% 93.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 3 2.63% 96.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 4 3.51% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 114 # Bytes accessed per row activation +system.physmem.totQLat 7578250 # Total ticks spent queuing +system.physmem.totMemAccLat 16372000 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2345000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9849.15 # Average queueing delay per DRAM burst +system.physmem.avgQLat 16158.32 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28599.15 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1314.30 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 34908.32 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1229.91 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1314.30 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1229.91 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 10.27 # Data bus utilization in percentage -system.physmem.busUtilRead 10.27 # Data bus utilization in percentage for reads +system.physmem.busUtil 9.61 # Data bus utilization in percentage +system.physmem.busUtilRead 9.61 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.73 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.76 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 353 # Number of row buffer hits during reads +system.physmem.readRowHits 352 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 75.27 # Row buffer hit rate for reads +system.physmem.readRowHitRate 75.05 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 48510.66 # Average gap between requests -system.physmem.pageHitRate 75.27 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 128520 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 70125 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 514800 # Energy for read commands per rank (pJ) +system.physmem.avgGap 51824.09 # Average gap between requests +system.physmem.pageHitRate 75.05 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 192780 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 98670 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 756840 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 9522135 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1146750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 12399450 # Total energy per rank (pJ) -system.physmem_0.averagePower 783.164377 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 1868000 # Time in different power states -system.physmem_0.memoryStateTime::REF 520000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 13458250 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 521640 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 284625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 2168400 # Energy for read commands per rank (pJ) +system.physmem_0.refreshEnergy 1843920.000000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1602840 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 46080 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 8339100 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 953280 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 13833510 # Total energy per rank (pJ) +system.physmem_0.averagePower 566.830977 # Core power per rank (mW) +system.physmem_0.totalIdleTime 20709000 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 23500 # Time in different power states +system.physmem_0.memoryStateTime::REF 780000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 0 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 2481750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 2828750 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 18291000 # Time in different power states +system.physmem_1.actEnergy 642600 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 333960 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 2591820 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 10729395 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 87750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 14808930 # Total energy per rank (pJ) -system.physmem_1.averagePower 935.350071 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 200750 # Time in different power states -system.physmem_1.memoryStateTime::REF 520000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 15221750 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 22838000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 2189 # Number of BP lookups -system.cpu.branchPred.condPredicted 1457 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 425 # Number of conditional branches incorrect +system.physmem_1.refreshEnergy 1843920.000000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 4214580 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 89760 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 6593190 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 180480 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 16490310 # Total energy per rank (pJ) +system.physmem_1.averagePower 675.693915 # Core power per rank (mW) +system.physmem_1.totalIdleTime 14889250 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 122500 # Time in different power states +system.physmem_1.memoryStateTime::REF 780000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 0 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 470250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 8563750 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 14468500 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 24405000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 2188 # Number of BP lookups +system.cpu.branchPred.condPredicted 1456 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 424 # Number of conditional branches incorrect system.cpu.branchPred.BTBLookups 1784 # Number of BTB lookups system.cpu.branchPred.BTBHits 587 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.branchPred.BTBHitPct 32.903587 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 251 # Number of times the RAS was used to get a target. +system.cpu.branchPred.usedRAS 252 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 70 # Number of incorrect RAS predictions. system.cpu.branchPred.indirectLookups 270 # Number of indirect predictor lookups. system.cpu.branchPred.indirectHits 2 # Number of indirect target hits. system.cpu.branchPred.indirectMisses 268 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 96 # Number of mispredicted indirect branches. +system.cpu.branchPredindirectMispredicted 95 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses @@ -284,235 +295,235 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 7 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 22838000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 45677 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 24405000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 48811 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 9081 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 13012 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2189 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 840 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 4774 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 870 # Number of cycles fetch has spent squashing +system.cpu.fetch.icacheStallCycles 9089 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 13001 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2188 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 841 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 5447 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 868 # Number of cycles fetch has spent squashing system.cpu.fetch.PendingTrapStallCycles 205 # Number of stall cycles due to pending traps system.cpu.fetch.CacheLines 2050 # Number of cache lines fetched system.cpu.fetch.IcacheSquashes 263 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 14495 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.897689 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.187204 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 15175 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.856738 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.144886 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 11134 76.81% 76.81% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1506 10.39% 87.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 111 0.77% 87.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 162 1.12% 89.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 279 1.92% 91.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 100 0.69% 91.70% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 142 0.98% 92.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 158 1.09% 93.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 903 6.23% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 11815 77.86% 77.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1507 9.93% 87.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 111 0.73% 88.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 162 1.07% 89.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 279 1.84% 91.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 100 0.66% 92.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 140 0.92% 93.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 158 1.04% 94.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 903 5.95% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 14495 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.047923 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.284870 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8449 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 2734 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2777 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 140 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 395 # Number of cycles decode is squashing +system.cpu.fetch.rateDist::total 15175 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.044826 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.266354 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8420 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 3451 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2768 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 142 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 394 # Number of cycles decode is squashing system.cpu.decode.BranchResolved 183 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 40 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 12026 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 12000 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 160 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 395 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 8600 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 597 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 983 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2748 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 1172 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 11590 # Number of instructions processed by rename +system.cpu.rename.SquashCycles 394 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 8571 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 621 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 1023 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2740 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 1826 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 11562 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 5 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 4 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 177 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 968 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 6955 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 13597 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 13364 # Number of integer rename lookups +system.cpu.rename.LQFullEvents 193 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 1606 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 6927 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 13556 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 13323 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 3 # Number of floating rename lookups system.cpu.rename.CommittedMaps 3292 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 3663 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 3635 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 13 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 9 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 307 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2472 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1158 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.skidInsts 323 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2470 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1160 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 6 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 2 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 9034 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 10 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8125 # Number of instructions issued +system.cpu.iq.iqInstsAdded 9019 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 11 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 8119 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 19 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 4044 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 2026 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 14495 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.560538 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.289389 # Number of insts issued each cycle +system.cpu.iq.iqSquashedInstsExamined 4030 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 2019 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 15175 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.535025 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.265920 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 11167 77.04% 77.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1340 9.24% 86.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 721 4.97% 91.26% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 460 3.17% 94.43% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 343 2.37% 96.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 283 1.95% 98.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 110 0.76% 99.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 52 0.36% 99.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 11852 78.10% 78.10% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1334 8.79% 86.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 728 4.80% 91.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 454 2.99% 94.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 341 2.25% 96.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 284 1.87% 98.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 110 0.72% 99.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 53 0.35% 99.87% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 19 0.13% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 14495 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 15175 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 7 3.87% 3.87% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 3.87% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 3.87% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.87% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.87% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.87% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 3.87% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.87% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 3.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 3.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.87% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 117 64.64% 68.51% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 57 31.49% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 6 3.33% 3.33% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 3.33% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 3.33% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.33% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.33% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.33% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 3.33% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.33% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 3.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 3.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.33% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 117 65.00% 68.33% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 57 31.67% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 4784 58.88% 58.88% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 4 0.05% 58.93% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 1 0.01% 58.94% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 58.97% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 58.97% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 58.97% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 58.97% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 58.97% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 58.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 58.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 58.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 58.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 58.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 58.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 58.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 58.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 58.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 58.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 58.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 58.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 58.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 58.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 58.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 58.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 58.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 58.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 58.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 58.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 58.97% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2273 27.98% 86.94% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1061 13.06% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 4775 58.81% 58.81% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 4 0.05% 58.86% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 1 0.01% 58.87% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 58.90% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 58.90% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 58.90% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 58.90% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 58.90% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 58.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 58.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 58.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 58.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 58.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 58.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 58.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 58.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 58.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 58.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 58.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 58.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 58.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 58.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 58.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 58.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 58.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 58.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 58.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 58.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 58.90% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2274 28.01% 86.91% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1063 13.09% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8125 # Type of FU issued -system.cpu.iq.rate 0.177879 # Inst issue rate -system.cpu.iq.fu_busy_cnt 181 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.022277 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 30941 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 13095 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 7347 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 8119 # Type of FU issued +system.cpu.iq.rate 0.166335 # Inst issue rate +system.cpu.iq.fu_busy_cnt 180 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.022170 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 31608 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 13067 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 7338 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 4 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 2 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 8304 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 8297 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 2 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 78 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1337 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1335 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 10 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 257 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 259 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 25 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 395 # Number of cycles IEW is squashing +system.cpu.iew.iewSquashCycles 394 # Number of cycles IEW is squashing system.cpu.iew.iewBlockCycles 491 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 59 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 10646 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 156 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2472 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1158 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 10 # Number of dispatched non-speculative instructions +system.cpu.iew.iewUnblockCycles 74 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 10629 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 154 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2470 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1160 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 11 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 59 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 75 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 10 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 101 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 339 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 440 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 7799 # Number of executed instructions +system.cpu.iew.predictedNotTakenIncorrect 338 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 439 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 7792 # Number of executed instructions system.cpu.iew.iewExecLoadInsts 2130 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 326 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecSquashedInsts 327 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1602 # number of nop insts executed +system.cpu.iew.exec_nop 1599 # number of nop insts executed system.cpu.iew.exec_refs 3179 # number of memory reference insts executed -system.cpu.iew.exec_branches 1368 # Number of branches executed +system.cpu.iew.exec_branches 1364 # Number of branches executed system.cpu.iew.exec_stores 1049 # Number of stores executed -system.cpu.iew.exec_rate 0.170742 # Inst execution rate -system.cpu.iew.wb_sent 7444 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 7349 # cumulative count of insts written-back -system.cpu.iew.wb_producers 2873 # num instructions producing a value -system.cpu.iew.wb_consumers 4285 # num instructions consuming a value -system.cpu.iew.wb_rate 0.160891 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.670478 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 4999 # The number of squashed insts skipped by commit +system.cpu.iew.exec_rate 0.159636 # Inst execution rate +system.cpu.iew.wb_sent 7433 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 7340 # cumulative count of insts written-back +system.cpu.iew.wb_producers 2867 # num instructions producing a value +system.cpu.iew.wb_consumers 4275 # num instructions consuming a value +system.cpu.iew.wb_rate 0.150376 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.670643 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 4990 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 9 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 385 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 13612 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.414340 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.226502 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 384 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 14293 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.394599 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.198950 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 11422 83.91% 83.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 884 6.49% 90.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 520 3.82% 94.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 254 1.87% 96.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 161 1.18% 97.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 165 1.21% 98.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 61 0.45% 98.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 41 0.30% 99.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 104 0.76% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 12101 84.66% 84.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 885 6.19% 90.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 521 3.65% 94.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 254 1.78% 96.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 160 1.12% 97.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 166 1.16% 98.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 63 0.44% 99.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 41 0.29% 99.29% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 102 0.71% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 13612 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 14293 # Number of insts commited each cycle system.cpu.commit.committedInsts 5640 # Number of instructions committed system.cpu.commit.committedOps 5640 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -558,63 +569,63 @@ system.cpu.commit.op_class_0::MemWrite 901 15.98% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 5640 # Class of committed instruction -system.cpu.commit.bw_lim_events 104 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 24134 # The number of ROB reads -system.cpu.rob.rob_writes 22169 # The number of ROB writes +system.cpu.commit.bw_lim_events 102 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 24808 # The number of ROB reads +system.cpu.rob.rob_writes 22150 # The number of ROB writes system.cpu.timesIdled 264 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 31182 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 33636 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 4999 # Number of Instructions Simulated system.cpu.committedOps 4999 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 9.137227 # CPI: Cycles Per Instruction -system.cpu.cpi_total 9.137227 # CPI: Total CPI of All Threads -system.cpu.ipc 0.109442 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.109442 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 10569 # number of integer regfile reads -system.cpu.int_regfile_writes 5149 # number of integer regfile writes +system.cpu.cpi 9.764153 # CPI: Cycles Per Instruction +system.cpu.cpi_total 9.764153 # CPI: Total CPI of All Threads +system.cpu.ipc 0.102415 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.102415 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 10563 # number of integer regfile reads +system.cpu.int_regfile_writes 5141 # number of integer regfile writes system.cpu.fp_regfile_reads 3 # number of floating regfile reads system.cpu.fp_regfile_writes 1 # number of floating regfile writes -system.cpu.misc_regfile_reads 160 # number of misc regfile reads -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 22838000 # Cumulative time (in ticks) in various power states +system.cpu.misc_regfile_reads 161 # number of misc regfile reads +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 24405000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 90.737808 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2395 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 91.114118 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2396 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 140 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 17.107143 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 17.114286 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 90.737808 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.022153 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.022153 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 91.114118 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.022245 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.022245 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 140 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 34 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 106 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 109 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.034180 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 5954 # Number of tag accesses system.cpu.dcache.tags.data_accesses 5954 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 22838000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 24405000 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 1839 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1839 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 556 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 556 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2395 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2395 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2395 # number of overall hits -system.cpu.dcache.overall_hits::total 2395 # number of overall hits +system.cpu.dcache.WriteReq_hits::cpu.data 557 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 557 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 2396 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2396 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2396 # number of overall hits +system.cpu.dcache.overall_hits::total 2396 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 167 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 167 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 345 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 345 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 512 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 512 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 512 # number of overall misses -system.cpu.dcache.overall_misses::total 512 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 12256500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 12256500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 24340499 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 24340499 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 36596999 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 36596999 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 36596999 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 36596999 # number of overall miss cycles +system.cpu.dcache.WriteReq_misses::cpu.data 344 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 344 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 511 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 511 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 511 # number of overall misses +system.cpu.dcache.overall_misses::total 511 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 12711500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 12711500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 34219499 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 34219499 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 46930999 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 46930999 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 46930999 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 46930999 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 2006 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 2006 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 901 # number of WriteReq accesses(hits+misses) @@ -625,34 +636,34 @@ system.cpu.dcache.overall_accesses::cpu.data 2907 system.cpu.dcache.overall_accesses::total 2907 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.083250 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.083250 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.382908 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.382908 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.176127 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.176127 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.176127 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.176127 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 73392.215569 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 73392.215569 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70552.171014 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 70552.171014 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 71478.513672 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 71478.513672 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 71478.513672 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 71478.513672 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 600 # number of cycles access was blocked +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.381798 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.381798 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.175783 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.175783 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.175783 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.175783 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 76116.766467 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 76116.766467 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 99475.287791 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 99475.287791 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 91841.485323 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 91841.485323 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 91841.485323 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 91841.485323 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 636 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 10 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 60 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 63.600000 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.ReadReq_mshr_hits::cpu.data 77 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 77 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 295 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 295 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 372 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 372 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 372 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 372 # number of overall MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 294 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 294 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 371 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 371 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 371 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 371 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 90 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 90 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 50 # number of WriteReq MSHR misses @@ -661,14 +672,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 140 system.cpu.dcache.demand_mshr_misses::total 140 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 140 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 140 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7898000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 7898000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4132999 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4132999 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12030999 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 12030999 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12030999 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 12030999 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8095000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 8095000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4915999 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4915999 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13010999 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 13010999 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13010999 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 13010999 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.044865 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.044865 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055494 # mshr miss rate for WriteReq accesses @@ -677,67 +688,67 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.048160 system.cpu.dcache.demand_mshr_miss_rate::total 0.048160 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.048160 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.048160 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 87755.555556 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 87755.555556 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 82659.980000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 82659.980000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 85935.707143 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 85935.707143 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 85935.707143 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 85935.707143 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 22838000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 89944.444444 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 89944.444444 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 98319.980000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 98319.980000 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 92935.707143 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 92935.707143 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 92935.707143 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 92935.707143 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 24405000 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 17 # number of replacements -system.cpu.icache.tags.tagsinuse 158.952170 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1612 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 160.115290 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1613 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 332 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 4.855422 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 4.858434 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 158.952170 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.077613 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.077613 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 160.115290 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.078181 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.078181 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 315 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 141 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 174 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 132 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 183 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.153809 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 4432 # Number of tag accesses system.cpu.icache.tags.data_accesses 4432 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 22838000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 1612 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1612 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1612 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1612 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1612 # number of overall hits -system.cpu.icache.overall_hits::total 1612 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 438 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 438 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 438 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 438 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 438 # number of overall misses -system.cpu.icache.overall_misses::total 438 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 33275000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 33275000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 33275000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 33275000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 33275000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 33275000 # number of overall miss cycles +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 24405000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 1613 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1613 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1613 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1613 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1613 # number of overall hits +system.cpu.icache.overall_hits::total 1613 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 437 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 437 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 437 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 437 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 437 # number of overall misses +system.cpu.icache.overall_misses::total 437 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 35529000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 35529000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 35529000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 35529000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 35529000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 35529000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 2050 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 2050 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 2050 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::total 2050 # number of demand (read+write) accesses system.cpu.icache.overall_accesses::cpu.inst 2050 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 2050 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.213659 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.213659 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.213659 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.213659 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.213659 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.213659 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75970.319635 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 75970.319635 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 75970.319635 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 75970.319635 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 75970.319635 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 75970.319635 # average overall miss latency +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.213171 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.213171 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.213171 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.213171 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.213171 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.213171 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 81302.059497 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 81302.059497 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 81302.059497 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 81302.059497 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 81302.059497 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 81302.059497 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -746,55 +757,55 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.writebacks::writebacks 17 # number of writebacks system.cpu.icache.writebacks::total 17 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 106 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 106 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 106 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 106 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 106 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 106 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 105 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 105 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 105 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 105 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 105 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 105 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 332 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 332 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 332 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 332 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 332 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 332 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 26133000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 26133000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 26133000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 26133000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 26133000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 26133000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 28113000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 28113000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 28113000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 28113000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 28113000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 28113000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.161951 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.161951 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.161951 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.161951 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.161951 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.161951 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 78713.855422 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 78713.855422 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 78713.855422 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 78713.855422 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 78713.855422 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 78713.855422 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 22838000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 84677.710843 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 84677.710843 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 84677.710843 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 84677.710843 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 84677.710843 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 84677.710843 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 24405000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 251.694203 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 253.317608 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 20 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 469 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.042644 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 160.892029 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 90.802174 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004910 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.002771 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.007681 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 162.143256 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 91.174352 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004948 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.002782 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.007731 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 469 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 187 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 282 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 171 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 298 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.014313 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 4381 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 4381 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 22838000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 24405000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackClean_hits::writebacks 17 # number of WritebackClean hits system.cpu.l2cache.WritebackClean_hits::total 17 # number of WritebackClean hits system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 3 # number of ReadCleanReq hits @@ -815,18 +826,18 @@ system.cpu.l2cache.demand_misses::total 469 # nu system.cpu.l2cache.overall_misses::cpu.inst 329 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 140 # number of overall misses system.cpu.l2cache.overall_misses::total 469 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4057000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 4057000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 25602000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 25602000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 7760000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 7760000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 25602000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 11817000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 37419000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 25602000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 11817000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 37419000 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4840000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 4840000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 27582000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 27582000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 7957000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 7957000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 27582000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 12797000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 40379000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 27582000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 12797000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 40379000 # number of overall miss cycles system.cpu.l2cache.WritebackClean_accesses::writebacks 17 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::total 17 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 50 # number of ReadExReq accesses(hits+misses) @@ -853,18 +864,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.993644 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.990964 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.993644 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81140 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81140 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 77817.629179 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 77817.629179 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 86222.222222 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 86222.222222 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77817.629179 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 84407.142857 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 79784.648188 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77817.629179 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 84407.142857 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 79784.648188 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 96800 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 96800 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 83835.866261 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 83835.866261 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 88411.111111 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 88411.111111 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83835.866261 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 91407.142857 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 86095.948827 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83835.866261 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 91407.142857 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 86095.948827 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -883,18 +894,18 @@ system.cpu.l2cache.demand_mshr_misses::total 469 system.cpu.l2cache.overall_mshr_misses::cpu.inst 329 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 140 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 469 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3557000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3557000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 22312000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 22312000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6860000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 6860000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22312000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10417000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 32729000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22312000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10417000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 32729000 # number of overall MSHR miss cycles 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+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24292000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11397000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 35689000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.990964 # mshr miss rate for ReadCleanReq accesses @@ -907,25 +918,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.993644 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.990964 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.993644 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71140 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71140 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67817.629179 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67817.629179 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76222.222222 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76222.222222 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67817.629179 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 74407.142857 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69784.648188 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67817.629179 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 74407.142857 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69784.648188 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 86800 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 86800 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 73835.866261 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 73835.866261 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 78411.111111 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 78411.111111 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73835.866261 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 81407.142857 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 76095.948827 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73835.866261 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 81407.142857 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 76095.948827 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 489 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 17 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 22838000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 24405000 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 422 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 17 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 50 # Transaction distribution @@ -954,7 +965,7 @@ system.cpu.toL2Bus.snoop_fanout::total 472 # Re system.cpu.toL2Bus.reqLayer0.occupancy 261500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 498000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.2 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.utilization 2.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 210000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) system.membus.snoop_filter.tot_requests 469 # Total number of requests made to the snoop filter. @@ -963,7 +974,7 @@ system.membus.snoop_filter.hit_multi_requests 0 system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 22838000 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 24405000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 419 # Transaction distribution system.membus.trans_dist::ReadExReq 50 # Transaction distribution system.membus.trans_dist::ReadExResp 50 # Transaction distribution @@ -985,8 +996,8 @@ system.membus.snoop_fanout::min_value 0 # Re system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 469 # Request fanout histogram system.membus.reqLayer0.occupancy 581500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 2494250 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 10.9 # Layer utilization (%) +system.membus.reqLayer0.utilization 2.4 # Layer utilization (%) +system.membus.respLayer1.occupancy 2488500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 10.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/config.ini index ff42947ce..ff37cda83 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/config.ini +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/config.ini @@ -14,6 +14,7 @@ children=clk_domain cpu dvfs_handler mem_ctrls ruby sys_port_proxy voltage_domai boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 exit_on_work_items=false init_param=0 @@ -22,11 +23,15 @@ kernel_addr_check=true load_addr_mask=1099511627775 load_offset=0 mem_mode=timing -mem_ranges=0:268435455 +mem_ranges=0:268435455:0:0:0:0 memories=system.mem_ctrls mmap_using_noreserve=false multi_thread=false num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null readfile= symbolfile= thermal_components= @@ -55,6 +60,7 @@ branchPred=Null checker=Null clk_domain=system.cpu.clk_domain cpu_id=0 +default_p_state=UNDEFINED do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true @@ -70,6 +76,10 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null profile=0 progress_interval=0 simpoint_start_insts= @@ -124,7 +134,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/hello/bin/mips/linux/hello +executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/mips/linux/hello gid=100 input=cin kvmInSE=false @@ -147,27 +157,27 @@ transition_latency=100000 [system.mem_ctrls] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -179,6 +189,7 @@ burst_length=8 channels=1 clk_domain=system.clk_domain conf_table_reported=true +default_p_state=UNDEFINED device_bus_width=8 device_rowbuffer_size=1024 device_size=536870912 @@ -186,12 +197,17 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 page_policy=open_adaptive -range=0:268435455 +power_model=Null +range=0:268435455:5:19:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10 @@ -213,9 +229,9 @@ tRTW=3 tWR=15 tWTR=8 tXAW=30 -tXP=0 +tXP=6 tXPDLL=0 -tXS=0 +tXS=270 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 @@ -229,12 +245,17 @@ access_backing_store=false all_instructions=false block_size_bytes=64 clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED eventq_index=0 hot_lines=false memory_size_bits=48 num_of_sequencers=1 number_of_virtual_networks=5 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 phys_mem=Null +power_model=Null randomization=false [system.ruby.clk_domain] @@ -251,6 +272,7 @@ children=directory dmaRequestToDir dmaResponseFromDir forwardFromDir requestToDi buffer_size=0 clk_domain=system.ruby.clk_domain cluster_id=0 +default_p_state=UNDEFINED directory=system.ruby.dir_cntrl0.directory directory_latency=12 dmaRequestToDir=system.ruby.dir_cntrl0.dmaRequestToDir @@ -258,6 +280,10 @@ dmaResponseFromDir=system.ruby.dir_cntrl0.dmaResponseFromDir eventq_index=0 forwardFromDir=system.ruby.dir_cntrl0.forwardFromDir number_of_TBEs=256 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null recycle_latency=10 requestToDir=system.ruby.dir_cntrl0.requestToDir responseFromDir=system.ruby.dir_cntrl0.responseFromDir @@ -331,11 +357,16 @@ cacheMemory=system.ruby.l1_cntrl0.cacheMemory cache_response_latency=12 clk_domain=system.cpu.clk_domain cluster_id=0 +default_p_state=UNDEFINED eventq_index=0 forwardToCache=system.ruby.l1_cntrl0.forwardToCache issue_latency=2 mandatoryQueue=system.ruby.l1_cntrl0.mandatoryQueue number_of_TBEs=256 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null recycle_latency=10 requestFromCache=system.ruby.l1_cntrl0.requestFromCache responseFromCache=system.ruby.l1_cntrl0.responseFromCache @@ -417,17 +448,22 @@ coreid=99 dcache=system.ruby.l1_cntrl0.cacheMemory dcache_hit_latency=1 deadlock_threshold=500000 +default_p_state=UNDEFINED eventq_index=0 +garnet_standalone=false icache=system.ruby.l1_cntrl0.cacheMemory icache_hit_latency=1 is_cpu_sequencer=true max_outstanding_requests=16 no_retry_on_stall=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null ruby_system=system.ruby support_data_reqs=true support_inst_reqs=true system=system -using_network_tester=false using_ruby_tester=false version=0 slave=system.cpu.icache_port system.cpu.dcache_port @@ -440,18 +476,23 @@ eventq_index=0 [system.ruby.network] type=SimpleNetwork -children=ext_links0 ext_links1 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_links0 int_links1 routers0 routers1 routers2 +children=ext_links0 ext_links1 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_link_buffers20 int_link_buffers21 int_link_buffers22 int_link_buffers23 int_link_buffers24 int_link_buffers25 int_link_buffers26 int_link_buffers27 int_link_buffers28 int_link_buffers29 int_link_buffers30 int_link_buffers31 int_link_buffers32 int_link_buffers33 int_link_buffers34 int_link_buffers35 int_link_buffers36 int_link_buffers37 int_link_buffers38 int_link_buffers39 int_links0 int_links1 int_links2 int_links3 routers0 routers1 routers2 adaptive_routing=false buffer_size=0 clk_domain=system.ruby.clk_domain control_msg_size=8 +default_p_state=UNDEFINED endpoint_bandwidth=1000 eventq_index=0 ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1 -int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19 -int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 +int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19 system.ruby.network.int_link_buffers20 system.ruby.network.int_link_buffers21 system.ruby.network.int_link_buffers22 system.ruby.network.int_link_buffers23 system.ruby.network.int_link_buffers24 system.ruby.network.int_link_buffers25 system.ruby.network.int_link_buffers26 system.ruby.network.int_link_buffers27 system.ruby.network.int_link_buffers28 system.ruby.network.int_link_buffers29 system.ruby.network.int_link_buffers30 system.ruby.network.int_link_buffers31 system.ruby.network.int_link_buffers32 system.ruby.network.int_link_buffers33 system.ruby.network.int_link_buffers34 system.ruby.network.int_link_buffers35 system.ruby.network.int_link_buffers36 system.ruby.network.int_link_buffers37 system.ruby.network.int_link_buffers38 system.ruby.network.int_link_buffers39 +int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2 system.ruby.network.int_links3 netifs= number_of_virtual_networks=5 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null routers=system.ruby.network.routers0 system.ruby.network.routers1 system.ruby.network.routers2 ruby_system=system.ruby topology=Crossbar @@ -618,32 +659,206 @@ eventq_index=0 ordered=true randomization=false +[system.ruby.network.int_link_buffers20] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers21] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers22] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers23] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers24] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers25] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers26] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers27] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers28] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers29] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers30] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers31] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers32] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers33] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers34] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers35] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers36] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers37] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers38] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers39] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + [system.ruby.network.int_links0] type=SimpleIntLink bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers2 eventq_index=0 latency=1 link_id=2 -node_a=system.ruby.network.routers0 -node_b=system.ruby.network.routers2 +src_node=system.ruby.network.routers0 +src_outport= weight=1 [system.ruby.network.int_links1] type=SimpleIntLink bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers2 eventq_index=0 latency=1 link_id=3 -node_a=system.ruby.network.routers1 -node_b=system.ruby.network.routers2 +src_node=system.ruby.network.routers1 +src_outport= +weight=1 + +[system.ruby.network.int_links2] +type=SimpleIntLink +bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers0 +eventq_index=0 +latency=1 +link_id=4 +src_node=system.ruby.network.routers2 +src_outport= +weight=1 + +[system.ruby.network.int_links3] +type=SimpleIntLink +bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers1 +eventq_index=0 +latency=1 +link_id=5 +src_node=system.ruby.network.routers2 +src_outport= weight=1 [system.ruby.network.routers0] type=Switch children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED eventq_index=0 +latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 port_buffers=system.ruby.network.routers0.port_buffers00 system.ruby.network.routers0.port_buffers01 system.ruby.network.routers0.port_buffers02 system.ruby.network.routers0.port_buffers03 system.ruby.network.routers0.port_buffers04 system.ruby.network.routers0.port_buffers05 system.ruby.network.routers0.port_buffers06 system.ruby.network.routers0.port_buffers07 system.ruby.network.routers0.port_buffers08 system.ruby.network.routers0.port_buffers09 system.ruby.network.routers0.port_buffers10 system.ruby.network.routers0.port_buffers11 system.ruby.network.routers0.port_buffers12 system.ruby.network.routers0.port_buffers13 system.ruby.network.routers0.port_buffers14 +power_model=Null router_id=0 virt_nets=5 @@ -756,8 +971,14 @@ randomization=false type=Switch children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED eventq_index=0 +latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 port_buffers=system.ruby.network.routers1.port_buffers00 system.ruby.network.routers1.port_buffers01 system.ruby.network.routers1.port_buffers02 system.ruby.network.routers1.port_buffers03 system.ruby.network.routers1.port_buffers04 system.ruby.network.routers1.port_buffers05 system.ruby.network.routers1.port_buffers06 system.ruby.network.routers1.port_buffers07 system.ruby.network.routers1.port_buffers08 system.ruby.network.routers1.port_buffers09 system.ruby.network.routers1.port_buffers10 system.ruby.network.routers1.port_buffers11 system.ruby.network.routers1.port_buffers12 system.ruby.network.routers1.port_buffers13 system.ruby.network.routers1.port_buffers14 +power_model=Null router_id=1 virt_nets=5 @@ -870,8 +1091,14 @@ randomization=false type=Switch children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17 port_buffers18 port_buffers19 clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED eventq_index=0 +latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 port_buffers=system.ruby.network.routers2.port_buffers00 system.ruby.network.routers2.port_buffers01 system.ruby.network.routers2.port_buffers02 system.ruby.network.routers2.port_buffers03 system.ruby.network.routers2.port_buffers04 system.ruby.network.routers2.port_buffers05 system.ruby.network.routers2.port_buffers06 system.ruby.network.routers2.port_buffers07 system.ruby.network.routers2.port_buffers08 system.ruby.network.routers2.port_buffers09 system.ruby.network.routers2.port_buffers10 system.ruby.network.routers2.port_buffers11 system.ruby.network.routers2.port_buffers12 system.ruby.network.routers2.port_buffers13 system.ruby.network.routers2.port_buffers14 system.ruby.network.routers2.port_buffers15 system.ruby.network.routers2.port_buffers16 system.ruby.network.routers2.port_buffers17 system.ruby.network.routers2.port_buffers18 system.ruby.network.routers2.port_buffers19 +power_model=Null router_id=2 virt_nets=5 @@ -1018,9 +1245,14 @@ randomization=false [system.sys_port_proxy] type=RubyPortProxy clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 is_cpu_sequencer=true no_retry_on_stall=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null ruby_system=system.ruby support_data_reqs=true support_inst_reqs=true diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/simerr b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/simerr index ccfdd3697..f6f6f15a5 100755 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/simerr +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/simerr @@ -4,8 +4,7 @@ warn: rounding error > tolerance 1.250000 rounded to 1 warn: rounding error > tolerance 1.250000 rounded to 1 -warn: rounding error > tolerance - 1.250000 rounded to 1 warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes) warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files! diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/simout b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/simout index 735671e5f..2e6bde8a3 100755 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/simout +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/simout @@ -3,13 +3,13 @@ Redirecting stderr to build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-t gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 14 2016 22:04:10 -gem5 started Mar 14 2016 22:06:34 -gem5 executing on phenom, pid 29860 -command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing-ruby -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing-ruby +gem5 compiled Oct 13 2016 20:36:34 +gem5 started Oct 13 2016 20:36:59 +gem5 executing on e108600-lin, pid 36842 +command line: /work/curdun01/gem5-external.hg/build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing-ruby -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/mips/linux/simple-timing-ruby Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello World! -Exiting @ tick 100232 because target called exit() +Exiting @ tick 106125 because target called exit() diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt index 5b0097850..d2ad37c0f 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000100 # Number of seconds simulated -sim_ticks 100232 # Number of ticks simulated -final_tick 100232 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000106 # Number of seconds simulated +sim_ticks 106125 # Number of ticks simulated +final_tick 106125 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 93908 # Simulator instruction rate (inst/s) -host_op_rate 93894 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1668107 # Simulator tick rate (ticks/s) -host_mem_usage 455812 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host +host_inst_rate 64036 # Simulator instruction rate (inst/s) +host_op_rate 64023 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1204237 # Simulator tick rate (ticks/s) +host_mem_usage 413260 # Number of bytes of host memory used +host_seconds 0.09 # Real time elapsed on the host sim_insts 5641 # Number of instructions simulated sim_ops 5641 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks -system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 100232 # Cumulative time (in ticks) in various power states +system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 106125 # Cumulative time (in ticks) in various power states system.mem_ctrls.bytes_read::ruby.dir_cntrl0 94208 # Number of bytes read from this memory system.mem_ctrls.bytes_read::total 94208 # Number of bytes read from this memory system.mem_ctrls.bytes_written::ruby.dir_cntrl0 93952 # Number of bytes written to this memory @@ -22,59 +22,59 @@ system.mem_ctrls.num_reads::ruby.dir_cntrl0 1472 # system.mem_ctrls.num_reads::total 1472 # Number of read requests responded to by this memory system.mem_ctrls.num_writes::ruby.dir_cntrl0 1468 # Number of write requests responded to by this memory system.mem_ctrls.num_writes::total 1468 # Number of write requests responded to by this memory -system.mem_ctrls.bw_read::ruby.dir_cntrl0 939899433 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_read::total 939899433 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::ruby.dir_cntrl0 937345359 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::total 937345359 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_total::ruby.dir_cntrl0 1877244792 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.bw_total::total 1877244792 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_read::ruby.dir_cntrl0 887707892 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 887707892 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::ruby.dir_cntrl0 885295642 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::total 885295642 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::ruby.dir_cntrl0 1773003534 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 1773003534 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrls.readReqs 1472 # Number of read requests accepted system.mem_ctrls.writeReqs 1468 # Number of write requests accepted system.mem_ctrls.readBursts 1472 # Number of DRAM read bursts, including those serviced by the write queue system.mem_ctrls.writeBursts 1468 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrls.bytesReadDRAM 58752 # Total number of bytes read from DRAM -system.mem_ctrls.bytesReadWrQ 35456 # Total number of bytes read from write queue -system.mem_ctrls.bytesWritten 60352 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadDRAM 58880 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 35328 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 59776 # Total number of bytes written to DRAM system.mem_ctrls.bytesReadSys 94208 # Total read bytes from the system interface side system.mem_ctrls.bytesWrittenSys 93952 # Total written bytes from the system interface side -system.mem_ctrls.servicedByWrQ 554 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrls.mergedWrBursts 502 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.servicedByWrQ 552 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 510 # Number of DRAM write bursts merged with an existing one system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.mem_ctrls.perBankRdBursts::0 33 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::0 31 # Per bank write bursts system.mem_ctrls.perBankRdBursts::1 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::2 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::3 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::4 7 # Per bank write bursts system.mem_ctrls.perBankRdBursts::5 3 # Per bank write bursts system.mem_ctrls.perBankRdBursts::6 13 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::7 81 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 83 # Per bank write bursts system.mem_ctrls.perBankRdBursts::8 66 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::9 245 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::10 98 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::11 45 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::12 114 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::13 45 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::14 154 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::15 14 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::0 34 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::9 250 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 100 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 44 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::12 107 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 46 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 157 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::15 13 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 32 # Per bank write bursts system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::4 7 # Per bank write bursts system.mem_ctrls.perBankWrBursts::5 3 # Per bank write bursts system.mem_ctrls.perBankWrBursts::6 13 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::7 74 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 75 # Per bank write bursts system.mem_ctrls.perBankWrBursts::8 60 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::9 247 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::9 250 # Per bank write bursts system.mem_ctrls.perBankWrBursts::10 100 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::11 46 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::12 118 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::13 49 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::14 178 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::11 45 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::12 110 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 48 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 177 # Per bank write bursts system.mem_ctrls.perBankWrBursts::15 14 # Per bank write bursts system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrls.totGap 100183 # Total gap between requests +system.mem_ctrls.totGap 106076 # Total gap between requests system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) @@ -89,7 +89,7 @@ system.mem_ctrls.writePktSize::3 0 # Wr system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::6 1468 # Write request sizes (log2) -system.mem_ctrls.rdQLenPdf::0 918 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::0 920 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see @@ -136,25 +136,25 @@ system.mem_ctrls.wrQLenPdf::11 1 # Wh system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::15 5 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::16 8 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::17 50 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::18 60 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 8 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 11 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 51 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 61 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::19 60 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::20 67 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 61 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::21 61 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::22 59 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::23 58 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::24 58 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::25 58 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::26 58 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::27 58 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::28 58 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::29 58 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::30 58 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::31 58 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::32 58 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::33 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 58 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 59 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::24 57 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 57 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 57 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 57 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::28 57 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 57 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 57 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 57 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::32 57 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see @@ -185,90 +185,101 @@ system.mem_ctrls.wrQLenPdf::60 0 # Wh system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrls.bytesPerActivate::samples 336 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::mean 348.571429 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::gmean 224.382213 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::stdev 328.447975 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::0-127 77 22.92% 22.92% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::128-255 103 30.65% 53.57% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::256-383 48 14.29% 67.86% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::384-511 26 7.74% 75.60% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::512-639 11 3.27% 78.87% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::640-767 8 2.38% 81.25% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::768-895 13 3.87% 85.12% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::896-1023 7 2.08% 87.20% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::1024-1151 43 12.80% 100.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::total 336 # Bytes accessed per row activation -system.mem_ctrls.rdPerTurnAround::samples 58 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::mean 15.706897 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::gmean 15.549891 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::stdev 2.720995 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::12-13 5 8.62% 8.62% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::14-15 26 44.83% 53.45% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::16-17 25 43.10% 96.55% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::18-19 1 1.72% 98.28% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::34-35 1 1.72% 100.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::total 58 # Reads before turning the bus around for writes -system.mem_ctrls.wrPerTurnAround::samples 58 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::mean 16.258621 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::gmean 16.240724 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::stdev 0.806995 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::16 52 89.66% 89.66% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::18 4 6.90% 96.55% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::19 1 1.72% 98.28% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::20 1 1.72% 100.00% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::total 58 # Writes before turning the bus around for reads -system.mem_ctrls.totQLat 12638 # Total ticks spent queuing -system.mem_ctrls.totMemAccLat 30080 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrls.totBusLat 4590 # Total ticks spent in databus transfers -system.mem_ctrls.avgQLat 13.77 # Average queueing delay per DRAM burst +system.mem_ctrls.bytesPerActivate::samples 352 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 334.181818 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 220.342342 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 312.466834 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 73 20.74% 20.74% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 116 32.95% 53.69% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 49 13.92% 67.61% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 31 8.81% 76.42% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 18 5.11% 81.53% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 13 3.69% 85.23% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 9 2.56% 87.78% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 3 0.85% 88.64% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 40 11.36% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 352 # Bytes accessed per row activation +system.mem_ctrls.rdPerTurnAround::samples 57 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::mean 16 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::gmean 15.842454 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::stdev 2.738613 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::12-13 2 3.51% 3.51% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::14-15 25 43.86% 47.37% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::16-17 25 43.86% 91.23% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::18-19 4 7.02% 98.25% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::34-35 1 1.75% 100.00% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::total 57 # Reads before turning the bus around for writes +system.mem_ctrls.wrPerTurnAround::samples 57 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::mean 16.385965 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::gmean 16.360622 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::stdev 0.959062 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::16 48 84.21% 84.21% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::17 1 1.75% 85.96% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::18 4 7.02% 92.98% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::19 3 5.26% 98.25% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::20 1 1.75% 100.00% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::total 57 # Writes before turning the bus around for reads +system.mem_ctrls.totQLat 18473 # Total ticks spent queuing +system.mem_ctrls.totMemAccLat 35953 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.totBusLat 4600 # Total ticks spent in databus transfers +system.mem_ctrls.avgQLat 20.08 # Average queueing delay per DRAM burst system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst -system.mem_ctrls.avgMemAccLat 32.77 # Average memory access latency per DRAM burst -system.mem_ctrls.avgRdBW 586.16 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrls.avgWrBW 602.12 # Average achieved write bandwidth in MiByte/s -system.mem_ctrls.avgRdBWSys 939.90 # Average system read bandwidth in MiByte/s -system.mem_ctrls.avgWrBWSys 937.35 # Average system write bandwidth in MiByte/s +system.mem_ctrls.avgMemAccLat 39.08 # Average memory access latency per DRAM burst +system.mem_ctrls.avgRdBW 554.82 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 563.26 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 887.71 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 885.30 # Average system write bandwidth in MiByte/s system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrls.busUtil 9.28 # Data bus utilization in percentage -system.mem_ctrls.busUtilRead 4.58 # Data bus utilization in percentage for reads -system.mem_ctrls.busUtilWrite 4.70 # Data bus utilization in percentage for writes +system.mem_ctrls.busUtil 8.73 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 4.33 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 4.40 # Data bus utilization in percentage for writes system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing -system.mem_ctrls.avgWrQLen 25.54 # Average write queue length when enqueuing -system.mem_ctrls.readRowHits 642 # Number of row buffer hits during reads -system.mem_ctrls.writeRowHits 873 # Number of row buffer hits during writes -system.mem_ctrls.readRowHitRate 69.93 # Row buffer hit rate for reads -system.mem_ctrls.writeRowHitRate 90.37 # Row buffer hit rate for writes -system.mem_ctrls.avgGap 34.08 # Average gap between requests -system.mem_ctrls.pageHitRate 80.41 # Row buffer hit rate, read and write combined -system.mem_ctrls_0.actEnergy 491400 # Energy for activate commands per rank (pJ) -system.mem_ctrls_0.preEnergy 273000 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_0.readEnergy 1547520 # Energy for read commands per rank (pJ) -system.mem_ctrls_0.writeEnergy 1099008 # Energy for write commands per rank (pJ) -system.mem_ctrls_0.refreshEnergy 6102720 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_0.actBackEnergy 55680336 # Energy for active background per rank (pJ) -system.mem_ctrls_0.preBackEnergy 7372800 # Energy for precharge background per rank (pJ) -system.mem_ctrls_0.totalEnergy 72566784 # Total energy per rank (pJ) -system.mem_ctrls_0.averagePower 774.524869 # Core power per rank (mW) -system.mem_ctrls_0.memoryStateTime::IDLE 11950 # Time in different power states -system.mem_ctrls_0.memoryStateTime::REF 3120 # Time in different power states -system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT 78690 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrls_1.actEnergy 1882440 # Energy for activate commands per rank (pJ) -system.mem_ctrls_1.preEnergy 1045800 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_1.readEnergy 9247680 # Energy for read commands per rank (pJ) -system.mem_ctrls_1.writeEnergy 7993728 # Energy for write commands per rank (pJ) -system.mem_ctrls_1.refreshEnergy 6102720 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_1.actBackEnergy 63740592 # Energy for active background per rank (pJ) -system.mem_ctrls_1.preBackEnergy 302400 # Energy for precharge background per rank (pJ) -system.mem_ctrls_1.totalEnergy 90315360 # Total energy per rank (pJ) -system.mem_ctrls_1.averagePower 963.960210 # Core power per rank (mW) -system.mem_ctrls_1.memoryStateTime::IDLE 182 # Time in different power states -system.mem_ctrls_1.memoryStateTime::REF 3120 # Time in different power states -system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT 90404 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 100232 # Cumulative time (in ticks) in various power states +system.mem_ctrls.avgWrQLen 25.41 # Average write queue length when enqueuing +system.mem_ctrls.readRowHits 632 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 865 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 68.70 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate 90.29 # Row buffer hit rate for writes +system.mem_ctrls.avgGap 36.08 # Average gap between requests +system.mem_ctrls.pageHitRate 79.71 # Row buffer hit rate, read and write combined +system.mem_ctrls_0.actEnergy 542640 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 289800 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 1565088 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 1085760 # Energy for write commands per rank (pJ) +system.mem_ctrls_0.refreshEnergy 8604960.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 15123696 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 297600 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.actPowerDownEnergy 24352224 # Energy for active power-down per rank (pJ) +system.mem_ctrls_0.prePowerDownEnergy 7106304 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls_0.selfRefreshEnergy 647736.000000 # Energy for self refresh per rank (pJ) +system.mem_ctrls_0.totalEnergy 59655384 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 562.123760 # Core power per rank (mW) +system.mem_ctrls_0.totalIdleTime 71087 # Total Idle time Per DRAM Rank +system.mem_ctrls_0.memoryStateTime::IDLE 340 # Time in different power states +system.mem_ctrls_0.memoryStateTime::REF 3646 # Time in different power states +system.mem_ctrls_0.memoryStateTime::SREF 185 # Time in different power states +system.mem_ctrls_0.memoryStateTime::PRE_PDN 18506 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 30044 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT_PDN 53404 # Time in different power states +system.mem_ctrls_1.actEnergy 2006340 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 1070328 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 8944992 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 6715008 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.refreshEnergy 7990320.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 16837800 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 207360 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.actPowerDownEnergy 31179912 # Energy for active power-down per rank (pJ) +system.mem_ctrls_1.prePowerDownEnergy 108672 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls_1.totalEnergy 75060732 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 707.286049 # Core power per rank (mW) +system.mem_ctrls_1.totalIdleTime 68578 # Total Idle time Per DRAM Rank +system.mem_ctrls_1.memoryStateTime::IDLE 148 # Time in different power states +system.mem_ctrls_1.memoryStateTime::REF 3380 # Time in different power states +system.mem_ctrls_1.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls_1.memoryStateTime::PRE_PDN 283 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 33937 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT_PDN 68377 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 106125 # Cumulative time (in ticks) in various power states system.cpu.clk_domain.clock 1 # Clock period in ticks system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses @@ -289,8 +300,8 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 7 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 100232 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 100232 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 106125 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 106125 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 5641 # Number of instructions committed @@ -309,7 +320,7 @@ system.cpu.num_mem_refs 2037 # nu system.cpu.num_load_insts 1135 # Number of load instructions system.cpu.num_store_insts 902 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 100232 # Number of busy cycles +system.cpu.num_busy_cycles 106125 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 886 # Number of branches fetched @@ -349,7 +360,7 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 5642 # Class of executed instruction system.ruby.clk_domain.clock 1 # Clock period in ticks -system.ruby.pwrStateResidencyTicks::UNDEFINED 100232 # Cumulative time (in ticks) in various power states +system.ruby.pwrStateResidencyTicks::UNDEFINED 106125 # Cumulative time (in ticks) in various power states system.ruby.delayHist::bucket_size 1 # delay histogram for all message system.ruby.delayHist::max_bucket 9 # delay histogram for all message system.ruby.delayHist::samples 2940 # delay histogram for all message @@ -365,10 +376,10 @@ system.ruby.outstanding_req_hist_seqr::total 7679 system.ruby.latency_hist_seqr::bucket_size 64 system.ruby.latency_hist_seqr::max_bucket 639 system.ruby.latency_hist_seqr::samples 7678 -system.ruby.latency_hist_seqr::mean 12.054441 -system.ruby.latency_hist_seqr::gmean 2.136034 -system.ruby.latency_hist_seqr::stdev 27.599754 -system.ruby.latency_hist_seqr | 7372 96.01% 96.01% | 253 3.30% 99.31% | 37 0.48% 99.79% | 4 0.05% 99.84% | 6 0.08% 99.92% | 5 0.07% 99.99% | 0 0.00% 99.99% | 1 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.latency_hist_seqr::mean 12.821959 +system.ruby.latency_hist_seqr::gmean 2.158431 +system.ruby.latency_hist_seqr::stdev 29.332675 +system.ruby.latency_hist_seqr | 6783 88.34% 88.34% | 834 10.86% 99.21% | 40 0.52% 99.73% | 8 0.10% 99.83% | 8 0.10% 99.93% | 5 0.07% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.latency_hist_seqr::total 7678 system.ruby.hit_latency_hist_seqr::bucket_size 1 system.ruby.hit_latency_hist_seqr::max_bucket 9 @@ -380,21 +391,21 @@ system.ruby.hit_latency_hist_seqr::total 6206 system.ruby.miss_latency_hist_seqr::bucket_size 64 system.ruby.miss_latency_hist_seqr::max_bucket 639 system.ruby.miss_latency_hist_seqr::samples 1472 -system.ruby.miss_latency_hist_seqr::mean 58.660326 -system.ruby.miss_latency_hist_seqr::gmean 52.389786 -system.ruby.miss_latency_hist_seqr::stdev 35.865583 -system.ruby.miss_latency_hist_seqr | 1166 79.21% 79.21% | 253 17.19% 96.40% | 37 2.51% 98.91% | 4 0.27% 99.18% | 6 0.41% 99.59% | 5 0.34% 99.93% | 0 0.00% 99.93% | 1 0.07% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.miss_latency_hist_seqr::mean 62.663723 +system.ruby.miss_latency_hist_seqr::gmean 55.319189 +system.ruby.miss_latency_hist_seqr::stdev 37.614530 +system.ruby.miss_latency_hist_seqr | 577 39.20% 39.20% | 834 56.66% 95.86% | 40 2.72% 98.57% | 8 0.54% 99.12% | 8 0.54% 99.66% | 5 0.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.miss_latency_hist_seqr::total 1472 system.ruby.Directory.incomplete_times_seqr 1471 -system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 100232 # Cumulative time (in ticks) in various power states +system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 106125 # Cumulative time (in ticks) in various power states system.ruby.l1_cntrl0.cacheMemory.demand_hits 6206 # Number of cache demand hits system.ruby.l1_cntrl0.cacheMemory.demand_misses 1472 # Number of cache demand misses system.ruby.l1_cntrl0.cacheMemory.demand_accesses 7678 # Number of cache demand accesses -system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 100232 # Cumulative time (in ticks) in various power states -system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 100232 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 106125 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 106125 # Cumulative time (in ticks) in various power states system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 100232 # Cumulative time (in ticks) in various power states -system.ruby.network.routers0.percent_links_utilized 7.332987 +system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 106125 # Cumulative time (in ticks) in various power states +system.ruby.network.routers0.percent_links_utilized 6.925795 system.ruby.network.routers0.msg_count.Control::2 1472 system.ruby.network.routers0.msg_count.Data::2 1468 system.ruby.network.routers0.msg_count.Response_Data::4 1472 @@ -403,8 +414,8 @@ system.ruby.network.routers0.msg_bytes.Control::2 11776 system.ruby.network.routers0.msg_bytes.Data::2 105696 system.ruby.network.routers0.msg_bytes.Response_Data::4 105984 system.ruby.network.routers0.msg_bytes.Writeback_Control::3 11744 -system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 100232 # Cumulative time (in ticks) in various power states -system.ruby.network.routers1.percent_links_utilized 7.332987 +system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 106125 # Cumulative time (in ticks) in various power states +system.ruby.network.routers1.percent_links_utilized 6.925795 system.ruby.network.routers1.msg_count.Control::2 1472 system.ruby.network.routers1.msg_count.Data::2 1468 system.ruby.network.routers1.msg_count.Response_Data::4 1472 @@ -413,8 +424,8 @@ system.ruby.network.routers1.msg_bytes.Control::2 11776 system.ruby.network.routers1.msg_bytes.Data::2 105696 system.ruby.network.routers1.msg_bytes.Response_Data::4 105984 system.ruby.network.routers1.msg_bytes.Writeback_Control::3 11744 -system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 100232 # Cumulative time (in ticks) in various power states -system.ruby.network.routers2.percent_links_utilized 7.332987 +system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 106125 # Cumulative time (in ticks) in various power states +system.ruby.network.routers2.percent_links_utilized 6.925795 system.ruby.network.routers2.msg_count.Control::2 1472 system.ruby.network.routers2.msg_count.Data::2 1468 system.ruby.network.routers2.msg_count.Response_Data::4 1472 @@ -423,7 +434,7 @@ system.ruby.network.routers2.msg_bytes.Control::2 11776 system.ruby.network.routers2.msg_bytes.Data::2 105696 system.ruby.network.routers2.msg_bytes.Response_Data::4 105984 system.ruby.network.routers2.msg_bytes.Writeback_Control::3 11744 -system.ruby.network.pwrStateResidencyTicks::UNDEFINED 100232 # Cumulative time (in ticks) in various power states +system.ruby.network.pwrStateResidencyTicks::UNDEFINED 106125 # Cumulative time (in ticks) in various power states system.ruby.network.msg_count.Control 4416 system.ruby.network.msg_count.Data 4404 system.ruby.network.msg_count.Response_Data 4416 @@ -432,33 +443,33 @@ system.ruby.network.msg_byte.Control 35328 system.ruby.network.msg_byte.Data 317088 system.ruby.network.msg_byte.Response_Data 317952 system.ruby.network.msg_byte.Writeback_Control 35232 -system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 100232 # Cumulative time (in ticks) in various power states -system.ruby.network.routers0.throttle0.link_utilization 7.340969 +system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 106125 # Cumulative time (in ticks) in various power states +system.ruby.network.routers0.throttle0.link_utilization 6.933333 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1472 system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 1468 system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 105984 system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 11744 -system.ruby.network.routers0.throttle1.link_utilization 7.325006 +system.ruby.network.routers0.throttle1.link_utilization 6.918257 system.ruby.network.routers0.throttle1.msg_count.Control::2 1472 system.ruby.network.routers0.throttle1.msg_count.Data::2 1468 system.ruby.network.routers0.throttle1.msg_bytes.Control::2 11776 system.ruby.network.routers0.throttle1.msg_bytes.Data::2 105696 -system.ruby.network.routers1.throttle0.link_utilization 7.325006 +system.ruby.network.routers1.throttle0.link_utilization 6.918257 system.ruby.network.routers1.throttle0.msg_count.Control::2 1472 system.ruby.network.routers1.throttle0.msg_count.Data::2 1468 system.ruby.network.routers1.throttle0.msg_bytes.Control::2 11776 system.ruby.network.routers1.throttle0.msg_bytes.Data::2 105696 -system.ruby.network.routers1.throttle1.link_utilization 7.340969 +system.ruby.network.routers1.throttle1.link_utilization 6.933333 system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 1472 system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 1468 system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 105984 system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 11744 -system.ruby.network.routers2.throttle0.link_utilization 7.340969 +system.ruby.network.routers2.throttle0.link_utilization 6.933333 system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 1472 system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 1468 system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 105984 system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 11744 -system.ruby.network.routers2.throttle1.link_utilization 7.325006 +system.ruby.network.routers2.throttle1.link_utilization 6.918257 system.ruby.network.routers2.throttle1.msg_count.Control::2 1472 system.ruby.network.routers2.throttle1.msg_count.Data::2 1468 system.ruby.network.routers2.throttle1.msg_bytes.Control::2 11776 @@ -476,10 +487,10 @@ system.ruby.delayVCHist.vnet_2::total 1468 # de system.ruby.LD.latency_hist_seqr::bucket_size 64 system.ruby.LD.latency_hist_seqr::max_bucket 639 system.ruby.LD.latency_hist_seqr::samples 1135 -system.ruby.LD.latency_hist_seqr::mean 33.525991 -system.ruby.LD.latency_hist_seqr::gmean 10.018050 -system.ruby.LD.latency_hist_seqr::stdev 38.312060 -system.ruby.LD.latency_hist_seqr | 999 88.02% 88.02% | 116 10.22% 98.24% | 13 1.15% 99.38% | 0 0.00% 99.38% | 6 0.53% 99.91% | 1 0.09% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.latency_hist_seqr::mean 35.394714 +system.ruby.LD.latency_hist_seqr::gmean 10.319359 +system.ruby.LD.latency_hist_seqr::stdev 39.399406 +system.ruby.LD.latency_hist_seqr | 768 67.67% 67.67% | 344 30.31% 97.97% | 15 1.32% 99.30% | 4 0.35% 99.65% | 2 0.18% 99.82% | 2 0.18% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.latency_hist_seqr::total 1135 system.ruby.LD.hit_latency_hist_seqr::bucket_size 1 system.ruby.LD.hit_latency_hist_seqr::max_bucket 9 @@ -491,18 +502,18 @@ system.ruby.LD.hit_latency_hist_seqr::total 466 system.ruby.LD.miss_latency_hist_seqr::bucket_size 64 system.ruby.LD.miss_latency_hist_seqr::max_bucket 639 system.ruby.LD.miss_latency_hist_seqr::samples 669 -system.ruby.LD.miss_latency_hist_seqr::mean 56.182362 -system.ruby.LD.miss_latency_hist_seqr::gmean 49.875907 -system.ruby.LD.miss_latency_hist_seqr::stdev 35.208867 -system.ruby.LD.miss_latency_hist_seqr | 533 79.67% 79.67% | 116 17.34% 97.01% | 13 1.94% 98.95% | 0 0.00% 98.95% | 6 0.90% 99.85% | 1 0.15% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.miss_latency_hist_seqr::mean 59.352765 +system.ruby.LD.miss_latency_hist_seqr::gmean 52.447495 +system.ruby.LD.miss_latency_hist_seqr::stdev 35.144031 +system.ruby.LD.miss_latency_hist_seqr | 302 45.14% 45.14% | 344 51.42% 96.56% | 15 2.24% 98.80% | 4 0.60% 99.40% | 2 0.30% 99.70% | 2 0.30% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.miss_latency_hist_seqr::total 669 -system.ruby.ST.latency_hist_seqr::bucket_size 64 -system.ruby.ST.latency_hist_seqr::max_bucket 639 +system.ruby.ST.latency_hist_seqr::bucket_size 32 +system.ruby.ST.latency_hist_seqr::max_bucket 319 system.ruby.ST.latency_hist_seqr::samples 901 -system.ruby.ST.latency_hist_seqr::mean 13.069922 -system.ruby.ST.latency_hist_seqr::gmean 2.509564 -system.ruby.ST.latency_hist_seqr::stdev 28.093942 -system.ruby.ST.latency_hist_seqr | 870 96.56% 96.56% | 27 3.00% 99.56% | 3 0.33% 99.89% | 0 0.00% 99.89% | 0 0.00% 99.89% | 0 0.00% 99.89% | 0 0.00% 99.89% | 1 0.11% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.latency_hist_seqr::mean 13.442841 +system.ruby.ST.latency_hist_seqr::gmean 2.518866 +system.ruby.ST.latency_hist_seqr::stdev 27.757167 +system.ruby.ST.latency_hist_seqr | 684 75.92% 75.92% | 130 14.43% 90.34% | 81 8.99% 99.33% | 0 0.00% 99.33% | 1 0.11% 99.45% | 3 0.33% 99.78% | 0 0.00% 99.78% | 0 0.00% 99.78% | 1 0.11% 99.89% | 1 0.11% 100.00% system.ruby.ST.latency_hist_seqr::total 901 system.ruby.ST.hit_latency_hist_seqr::bucket_size 1 system.ruby.ST.hit_latency_hist_seqr::max_bucket 9 @@ -511,21 +522,21 @@ system.ruby.ST.hit_latency_hist_seqr::mean 1 system.ruby.ST.hit_latency_hist_seqr::gmean 1 system.ruby.ST.hit_latency_hist_seqr | 0 0.00% 0.00% | 684 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ST.hit_latency_hist_seqr::total 684 -system.ruby.ST.miss_latency_hist_seqr::bucket_size 64 -system.ruby.ST.miss_latency_hist_seqr::max_bucket 639 +system.ruby.ST.miss_latency_hist_seqr::bucket_size 32 +system.ruby.ST.miss_latency_hist_seqr::max_bucket 319 system.ruby.ST.miss_latency_hist_seqr::samples 217 -system.ruby.ST.miss_latency_hist_seqr::mean 51.115207 -system.ruby.ST.miss_latency_hist_seqr::gmean 45.620625 -system.ruby.ST.miss_latency_hist_seqr::stdev 37.056021 -system.ruby.ST.miss_latency_hist_seqr | 186 85.71% 85.71% | 27 12.44% 98.16% | 3 1.38% 99.54% | 0 0.00% 99.54% | 0 0.00% 99.54% | 0 0.00% 99.54% | 0 0.00% 99.54% | 1 0.46% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.miss_latency_hist_seqr::mean 52.663594 +system.ruby.ST.miss_latency_hist_seqr::gmean 46.326875 +system.ruby.ST.miss_latency_hist_seqr::stdev 34.272225 +system.ruby.ST.miss_latency_hist_seqr | 0 0.00% 0.00% | 130 59.91% 59.91% | 81 37.33% 97.24% | 0 0.00% 97.24% | 1 0.46% 97.70% | 3 1.38% 99.08% | 0 0.00% 99.08% | 0 0.00% 99.08% | 1 0.46% 99.54% | 1 0.46% 100.00% system.ruby.ST.miss_latency_hist_seqr::total 217 system.ruby.IFETCH.latency_hist_seqr::bucket_size 64 system.ruby.IFETCH.latency_hist_seqr::max_bucket 639 system.ruby.IFETCH.latency_hist_seqr::samples 5642 -system.ruby.IFETCH.latency_hist_seqr::mean 7.572847 -system.ruby.IFETCH.latency_hist_seqr::gmean 1.525495 -system.ruby.IFETCH.latency_hist_seqr::stdev 22.420339 -system.ruby.IFETCH.latency_hist_seqr | 5503 97.54% 97.54% | 110 1.95% 99.49% | 21 0.37% 99.86% | 4 0.07% 99.93% | 0 0.00% 99.93% | 4 0.07% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.latency_hist_seqr::mean 8.181850 +system.ruby.IFETCH.latency_hist_seqr::gmean 1.537199 +system.ruby.IFETCH.latency_hist_seqr::stdev 24.735651 +system.ruby.IFETCH.latency_hist_seqr | 5201 92.18% 92.18% | 409 7.25% 99.43% | 21 0.37% 99.81% | 4 0.07% 99.88% | 4 0.07% 99.95% | 3 0.05% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.latency_hist_seqr::total 5642 system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 1 system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 9 @@ -537,18 +548,18 @@ system.ruby.IFETCH.hit_latency_hist_seqr::total 5056 system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 64 system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 639 system.ruby.IFETCH.miss_latency_hist_seqr::samples 586 -system.ruby.IFETCH.miss_latency_hist_seqr::mean 64.283276 -system.ruby.IFETCH.miss_latency_hist_seqr::gmean 58.328027 -system.ruby.IFETCH.miss_latency_hist_seqr::stdev 35.386051 -system.ruby.IFETCH.miss_latency_hist_seqr | 447 76.28% 76.28% | 110 18.77% 95.05% | 21 3.58% 98.63% | 4 0.68% 99.32% | 0 0.00% 99.32% | 4 0.68% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.miss_latency_hist_seqr::mean 70.146758 +system.ruby.IFETCH.miss_latency_hist_seqr::gmean 62.782043 +system.ruby.IFETCH.miss_latency_hist_seqr::stdev 40.099052 +system.ruby.IFETCH.miss_latency_hist_seqr | 145 24.74% 24.74% | 409 69.80% 94.54% | 21 3.58% 98.12% | 4 0.68% 98.81% | 4 0.68% 99.49% | 3 0.51% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.miss_latency_hist_seqr::total 586 system.ruby.Directory.miss_mach_latency_hist_seqr::bucket_size 64 system.ruby.Directory.miss_mach_latency_hist_seqr::max_bucket 639 system.ruby.Directory.miss_mach_latency_hist_seqr::samples 1472 -system.ruby.Directory.miss_mach_latency_hist_seqr::mean 58.660326 -system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 52.389786 -system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 35.865583 -system.ruby.Directory.miss_mach_latency_hist_seqr | 1166 79.21% 79.21% | 253 17.19% 96.40% | 37 2.51% 98.91% | 4 0.27% 99.18% | 6 0.41% 99.59% | 5 0.34% 99.93% | 0 0.00% 99.93% | 1 0.07% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_mach_latency_hist_seqr::mean 62.663723 +system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 55.319189 +system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 37.614530 +system.ruby.Directory.miss_mach_latency_hist_seqr | 577 39.20% 39.20% | 834 56.66% 95.86% | 40 2.72% 98.57% | 8 0.54% 99.12% | 8 0.54% 99.66% | 5 0.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.Directory.miss_mach_latency_hist_seqr::total 1472 system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::bucket_size 1 system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::max_bucket 9 @@ -579,26 +590,26 @@ system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::total system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples 669 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 56.182362 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 49.875907 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 35.208867 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 533 79.67% 79.67% | 116 17.34% 97.01% | 13 1.94% 98.95% | 0 0.00% 98.95% | 6 0.90% 99.85% | 1 0.15% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 59.352765 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 52.447495 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 35.144031 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 302 45.14% 45.14% | 344 51.42% 96.56% | 15 2.24% 98.80% | 4 0.60% 99.40% | 2 0.30% 99.70% | 2 0.30% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total 669 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size 32 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket 319 system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::samples 217 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 51.115207 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 45.620625 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 37.056021 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 186 85.71% 85.71% | 27 12.44% 98.16% | 3 1.38% 99.54% | 0 0.00% 99.54% | 0 0.00% 99.54% | 0 0.00% 99.54% | 0 0.00% 99.54% | 1 0.46% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 52.663594 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 46.326875 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 34.272225 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 130 59.91% 59.91% | 81 37.33% 97.24% | 0 0.00% 97.24% | 1 0.46% 97.70% | 3 1.38% 99.08% | 0 0.00% 99.08% | 0 0.00% 99.08% | 1 0.46% 99.54% | 1 0.46% 100.00% system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total 217 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::samples 586 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 64.283276 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 58.328027 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 35.386051 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 447 76.28% 76.28% | 110 18.77% 95.05% | 21 3.58% 98.63% | 4 0.68% 99.32% | 0 0.00% 99.32% | 4 0.68% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 70.146758 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 62.782043 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 40.099052 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 145 24.74% 24.74% | 409 69.80% 94.54% | 21 3.58% 98.12% | 4 0.68% 98.81% | 4 0.68% 99.49% | 3 0.51% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::total 586 system.ruby.Directory_Controller.GETX 1472 0.00% 0.00% system.ruby.Directory_Controller.PUTX 1468 0.00% 0.00% diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini index 11c8c38c9..08a1c6669 100644 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini @@ -174,7 +174,7 @@ useIndirect=true [system.cpu.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -532,7 +532,7 @@ pipelined=false [system.cpu.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -591,7 +591,7 @@ size=64 [system.cpu.l2cache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -708,6 +708,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -719,7 +720,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -727,29 +728,36 @@ width=16 master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -769,6 +777,7 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 @@ -778,7 +787,7 @@ p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 page_policy=open_adaptive power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 @@ -800,9 +809,9 @@ tRTW=2500 tWR=15000 tWTR=7500 tXAW=30000 -tXP=0 +tXP=6000 tXPDLL=0 -tXS=0 +tXS=270000 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout index bd0101e05..7df757697 100755 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout @@ -3,12 +3,12 @@ Redirecting stderr to build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-tim gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:27:08 -gem5 started Jul 21 2016 14:27:33 -gem5 executing on e108600-lin, pid 27995 +gem5 compiled Oct 13 2016 20:40:28 +gem5 started Oct 13 2016 20:40:51 +gem5 executing on e108600-lin, pid 9917 command line: /work/curdun01/gem5-external.hg/build/POWER/gem5.opt -d build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/power/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 19908000 because target called exit() +Exiting @ tick 21268000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt index ee06020dc..cfc1cce24 100644 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000020 # Number of seconds simulated -sim_ticks 20159000 # Number of ticks simulated -final_tick 20159000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000021 # Number of seconds simulated +sim_ticks 21268000 # Number of ticks simulated +final_tick 21268000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 70194 # Simulator instruction rate (inst/s) -host_op_rate 70182 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 244226628 # Simulator tick rate (ticks/s) -host_mem_usage 249960 # Number of bytes of host memory used -host_seconds 0.08 # Real time elapsed on the host +host_inst_rate 112778 # Simulator instruction rate (inst/s) +host_op_rate 112739 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 413846380 # Simulator tick rate (ticks/s) +host_mem_usage 248372 # Number of bytes of host memory used +host_seconds 0.05 # Real time elapsed on the host sim_insts 5792 # Number of instructions simulated sim_ops 5792 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 20159000 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 21268000 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 21952 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 6400 # Number of bytes read from this memory system.physmem.bytes_read::total 28352 # Number of bytes read from this memory @@ -22,14 +22,14 @@ system.physmem.bytes_inst_read::total 21952 # Nu system.physmem.num_reads::cpu.inst 343 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 100 # Number of read requests responded to by this memory system.physmem.num_reads::total 443 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1088942904 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 317476065 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1406418969 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1088942904 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1088942904 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1088942904 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 317476065 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1406418969 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1032160993 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 300921572 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1333082565 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1032160993 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1032160993 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1032160993 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 300921572 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1333082565 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 445 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 445 # Number of DRAM read bursts, including those serviced by the write queue @@ -76,7 +76,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 20108500 # Total gap between requests +system.physmem.totGap 21217500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -91,11 +91,11 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 245 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 139 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 235 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 147 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 44 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 13 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -187,78 +187,89 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 76 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 341.894737 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 206.930275 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 338.261263 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 24 31.58% 31.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 19 25.00% 56.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 9 11.84% 68.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3 3.95% 72.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 4 5.26% 77.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 4 5.26% 82.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 5 6.58% 89.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8 10.53% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 76 # Bytes accessed per row activation -system.physmem.totQLat 3790750 # Total ticks spent queuing -system.physmem.totMemAccLat 12134500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 75 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 351.573333 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 215.062906 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 340.509998 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 23 30.67% 30.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 18 24.00% 54.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 11 14.67% 69.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2 2.67% 72.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3 4.00% 76.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 4 5.33% 81.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 2 2.67% 84.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 3 4.00% 88.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 9 12.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 75 # Bytes accessed per row activation +system.physmem.totQLat 5980000 # Total ticks spent queuing +system.physmem.totMemAccLat 14323750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2225000 # Total ticks spent in databus transfers -system.physmem.avgQLat 8518.54 # Average queueing delay per DRAM burst +system.physmem.avgQLat 13438.20 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27268.54 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1412.77 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 32188.20 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1339.10 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1412.77 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1339.10 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 11.04 # Data bus utilization in percentage -system.physmem.busUtilRead 11.04 # Data bus utilization in percentage for reads +system.physmem.busUtil 10.46 # Data bus utilization in percentage +system.physmem.busUtilRead 10.46 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.78 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.85 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing system.physmem.readRowHits 360 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 80.90 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 45187.64 # Average gap between requests +system.physmem.avgGap 47679.78 # Average gap between requests system.physmem.pageHitRate 80.90 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 438480 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 239250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 2496000 # Energy for read commands per rank (pJ) +system.physmem_0.actEnergy 528360 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 254265 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 2877420 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 10814895 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 32250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 15037995 # Total energy per rank (pJ) -system.physmem_0.averagePower 947.872361 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 11500 # Time in different power states +system.physmem_0.refreshEnergy 1229280.000000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 3922170 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 28320 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 5666370 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 64320 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 14570505 # Total energy per rank (pJ) +system.physmem_0.averagePower 685.066353 # Core power per rank (mW) +system.physmem_0.totalIdleTime 12593250 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 17500 # Time in different power states system.physmem_0.memoryStateTime::REF 520000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 15347250 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 68040 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 37125 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 288600 # Energy for read commands per rank (pJ) +system.physmem_0.memoryStateTime::SREF 0 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 167250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 8137250 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 12426000 # Time in different power states +system.physmem_1.actEnergy 78540 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 30360 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 299880 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 7519725 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 2903250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 11833860 # Total energy per rank (pJ) -system.physmem_1.averagePower 747.441023 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 6690750 # Time in different power states +system.physmem_1.refreshEnergy 1229280.000000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 747840 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1408800 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 6431880 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 712320 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 10938900 # Total energy per rank (pJ) +system.physmem_1.averagePower 514.317955 # Core power per rank (mW) +system.physmem_1.totalIdleTime 13775500 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 3585000 # Time in different power states system.physmem_1.memoryStateTime::REF 520000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 10557750 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 20159000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 2407 # Number of BP lookups -system.cpu.branchPred.condPredicted 1979 # Number of conditional branches predicted +system.physmem_1.memoryStateTime::SREF 0 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 1854750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1201500 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 14106750 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 21268000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 2411 # Number of BP lookups +system.cpu.branchPred.condPredicted 1982 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 409 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 2054 # Number of BTB lookups -system.cpu.branchPred.BTBHits 691 # Number of BTB hits +system.cpu.branchPred.BTBLookups 2056 # Number of BTB lookups +system.cpu.branchPred.BTBHits 693 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 33.641675 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 226 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 33.706226 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 227 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 35 # Number of incorrect RAS predictions. system.cpu.branchPred.indirectLookups 130 # Number of indirect predictor lookups. system.cpu.branchPred.indirectHits 19 # Number of indirect target hits. @@ -284,236 +295,236 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 9 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 20159000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 40319 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 21268000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 42537 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 7699 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 13357 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2407 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 936 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 4134 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 847 # Number of cycles fetch has spent squashing +system.cpu.fetch.icacheStallCycles 7672 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 13369 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2411 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 939 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 4149 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 849 # Number of cycles fetch has spent squashing system.cpu.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 146 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 22 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 1855 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 288 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 12429 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.074664 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.474276 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 1861 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 290 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 12418 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.076582 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.475981 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 10095 81.22% 81.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 166 1.34% 82.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 217 1.75% 84.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 147 1.18% 85.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 245 1.97% 87.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 146 1.17% 88.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 275 2.21% 90.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 148 1.19% 92.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 990 7.97% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 10084 81.20% 81.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 166 1.34% 82.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 214 1.72% 84.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 147 1.18% 85.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 241 1.94% 87.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 150 1.21% 88.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 280 2.25% 90.85% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 148 1.19% 92.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 988 7.96% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 12429 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.059699 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.331283 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 7289 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 2789 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 1948 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 128 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 275 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 323 # Number of times decode resolved a branch +system.cpu.fetch.rateDist::total 12418 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.056680 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.314291 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 7245 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 2821 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 1946 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 130 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 276 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 324 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 149 # Number of times decode detected a branch misprediction system.cpu.decode.DecodedInsts 11479 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 451 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 275 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 7458 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 805 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 449 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 1896 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 1546 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 11044 # Number of instructions processed by rename +system.cpu.rename.SquashCycles 276 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 7413 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 800 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 463 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 1897 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 1569 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 11042 # Number of instructions processed by rename system.cpu.rename.IQFullEvents 12 # Number of times rename has blocked due to IQ full system.cpu.rename.LQFullEvents 2 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 1504 # Number of times rename has blocked due to SQ full +system.cpu.rename.SQFullEvents 1522 # Number of times rename has blocked due to SQ full system.cpu.rename.RenamedOperands 9711 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 17893 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 17867 # Number of integer rename lookups +system.cpu.rename.RenameLookups 17897 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 17871 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 26 # Number of floating rename lookups system.cpu.rename.CommittedMaps 4998 # Number of HB maps that are committed system.cpu.rename.UndoneMaps 4713 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 27 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 27 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 365 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 1936 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1592 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.skidInsts 381 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 1937 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1590 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 55 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 30 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 10175 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 10171 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 63 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8810 # Number of instructions issued +system.cpu.iq.iqInstsIssued 8808 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 53 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 4446 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3475 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedInstsExamined 4442 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3474 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 47 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 12429 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.708826 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.510537 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 12418 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.709293 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.511827 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 9301 74.83% 74.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 985 7.93% 82.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 659 5.30% 88.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 457 3.68% 91.74% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 433 3.48% 95.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 286 2.30% 97.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 214 1.72% 99.24% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 62 0.50% 99.74% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 32 0.26% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 9303 74.92% 74.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 969 7.80% 82.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 656 5.28% 88.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 462 3.72% 91.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 429 3.45% 95.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 293 2.36% 97.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 212 1.71% 99.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 64 0.52% 99.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 30 0.24% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 12429 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 12418 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 12 6.35% 6.35% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 6.35% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 6.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 6.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 6.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 6.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.35% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 87 46.03% 52.38% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 90 47.62% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 12 6.32% 6.32% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 6.32% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 6.32% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.32% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.32% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.32% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 6.32% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.32% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 6.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 6.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.32% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.32% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 88 46.32% 52.63% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 90 47.37% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5533 62.80% 62.80% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 62.80% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.80% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 62.83% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.83% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.83% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.83% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.83% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.83% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1811 20.56% 83.38% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1464 16.62% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 5530 62.78% 62.78% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 62.78% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.78% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 62.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.81% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 1813 20.58% 83.39% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1463 16.61% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8810 # Type of FU issued -system.cpu.iq.rate 0.218507 # Inst issue rate -system.cpu.iq.fu_busy_cnt 189 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.021453 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 30229 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 14654 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 8112 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 8808 # Type of FU issued +system.cpu.iq.rate 0.207067 # Inst issue rate +system.cpu.iq.fu_busy_cnt 190 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.021571 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 30215 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 14647 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 8115 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 62 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 36 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 27 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 8965 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 8964 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 34 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 83 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 79 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 975 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 976 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 6 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 546 # Number of stores squashed +system.cpu.iew.lsq.thread0.memOrderViolation 7 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 544 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 7 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 275 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 721 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 77 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 10238 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 276 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 722 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 71 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 10234 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 32 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 1936 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1592 # Number of dispatched store instructions +system.cpu.iew.iewDispLoadInsts 1937 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1590 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 53 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 12 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 66 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 6 # Number of memory order violations +system.cpu.iew.iewLSQFullEvents 60 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 7 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 68 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 256 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 324 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 8460 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1699 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 350 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 8463 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1703 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 345 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3077 # number of memory reference insts executed -system.cpu.iew.exec_branches 1359 # Number of branches executed -system.cpu.iew.exec_stores 1378 # Number of stores executed -system.cpu.iew.exec_rate 0.209827 # Inst execution rate -system.cpu.iew.wb_sent 8239 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 8139 # cumulative count of insts written-back -system.cpu.iew.wb_producers 4432 # num instructions producing a value -system.cpu.iew.wb_consumers 7119 # num instructions consuming a value -system.cpu.iew.wb_rate 0.201865 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.622559 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 4448 # The number of squashed insts skipped by commit +system.cpu.iew.exec_refs 3080 # number of memory reference insts executed +system.cpu.iew.exec_branches 1358 # Number of branches executed +system.cpu.iew.exec_stores 1377 # Number of stores executed +system.cpu.iew.exec_rate 0.198956 # Inst execution rate +system.cpu.iew.wb_sent 8242 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 8142 # cumulative count of insts written-back +system.cpu.iew.wb_producers 4448 # num instructions producing a value +system.cpu.iew.wb_consumers 7158 # num instructions consuming a value +system.cpu.iew.wb_rate 0.191410 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.621403 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 4444 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 16 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 270 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 11727 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.493903 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.354058 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 11716 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.494367 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.358573 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 9550 81.44% 81.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 859 7.32% 88.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 529 4.51% 93.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 217 1.85% 95.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 185 1.58% 96.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 107 0.91% 97.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 121 1.03% 98.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 9551 81.52% 81.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 850 7.26% 88.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 527 4.50% 93.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 215 1.84% 95.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 176 1.50% 96.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 112 0.96% 97.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 126 1.08% 98.64% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::7 49 0.42% 99.06% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::8 110 0.94% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 11727 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 11716 # Number of insts commited each cycle system.cpu.commit.committedInsts 5792 # Number of instructions committed system.cpu.commit.committedOps 5792 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -560,99 +571,99 @@ system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Cl system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 5792 # Class of committed instruction system.cpu.commit.bw_lim_events 110 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 21857 # The number of ROB reads -system.cpu.rob.rob_writes 21183 # The number of ROB writes -system.cpu.timesIdled 230 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 27890 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 21842 # The number of ROB reads +system.cpu.rob.rob_writes 21175 # The number of ROB writes +system.cpu.timesIdled 228 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 30119 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5792 # Number of Instructions Simulated system.cpu.committedOps 5792 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 6.961153 # CPI: Cycles Per Instruction -system.cpu.cpi_total 6.961153 # CPI: Total CPI of All Threads -system.cpu.ipc 0.143654 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.143654 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 13369 # number of integer regfile reads -system.cpu.int_regfile_writes 7149 # number of integer regfile writes +system.cpu.cpi 7.344095 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.344095 # CPI: Total CPI of All Threads +system.cpu.ipc 0.136164 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.136164 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 13368 # number of integer regfile reads +system.cpu.int_regfile_writes 7153 # number of integer regfile writes system.cpu.fp_regfile_reads 25 # number of floating regfile reads system.cpu.fp_regfile_writes 2 # number of floating regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 20159000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 21268000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 64.445386 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2199 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 64.389343 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2206 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 102 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 21.558824 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 21.627451 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 64.445386 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.015734 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.015734 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 64.389343 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.015720 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.015720 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 102 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 75 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 77 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.024902 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 5374 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 5374 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 20159000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 1477 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1477 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 722 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 722 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2199 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2199 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2199 # number of overall hits -system.cpu.dcache.overall_hits::total 2199 # number of overall hits +system.cpu.dcache.tags.tag_accesses 5390 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 5390 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 21268000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 1485 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1485 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 721 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 721 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 2206 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2206 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2206 # number of overall hits +system.cpu.dcache.overall_hits::total 2206 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 113 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 113 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 324 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 324 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 437 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 437 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 437 # number of overall misses -system.cpu.dcache.overall_misses::total 437 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 7904000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 7904000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 32053496 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 32053496 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 39957496 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 39957496 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 39957496 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 39957496 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1590 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1590 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_misses::cpu.data 325 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 325 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 438 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 438 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 438 # number of overall misses +system.cpu.dcache.overall_misses::total 438 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 8211000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 8211000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 32489496 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 32489496 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 40700496 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 40700496 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 40700496 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 40700496 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1598 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1598 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1046 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 1046 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2636 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2636 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2636 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2636 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.071069 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.071069 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.309751 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.309751 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.165781 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.165781 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.165781 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.165781 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 69946.902655 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 69946.902655 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 98930.543210 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 98930.543210 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 91435.917620 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 91435.917620 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 91435.917620 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 91435.917620 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 604 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 2644 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2644 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2644 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2644 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.070713 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.070713 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.310707 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.310707 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.165658 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.165658 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.165658 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.165658 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 72663.716814 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 72663.716814 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 99967.680000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 99967.680000 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 92923.506849 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 92923.506849 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 92923.506849 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 92923.506849 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 612 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 6 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 100.666667 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 102 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.ReadReq_mshr_hits::cpu.data 56 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 56 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 277 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 277 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 333 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 333 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 333 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 333 # number of overall MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 278 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 278 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 334 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 334 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 334 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 334 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 57 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 57 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 47 # number of WriteReq MSHR misses @@ -661,88 +672,88 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 104 system.cpu.dcache.demand_mshr_misses::total 104 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 104 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 104 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4485500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4485500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4548998 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4548998 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9034498 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9034498 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9034498 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 9034498 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.035849 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.035849 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4669500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4669500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4693998 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4693998 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9363498 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9363498 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9363498 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 9363498 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.035670 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.035670 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044933 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044933 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.039454 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.039454 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.039454 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.039454 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78692.982456 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78692.982456 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 96787.191489 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 96787.191489 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 86870.173077 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 86870.173077 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 86870.173077 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 86870.173077 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 20159000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.039334 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.039334 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.039334 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.039334 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 81921.052632 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 81921.052632 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 99872.297872 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 99872.297872 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 90033.634615 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 90033.634615 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 90033.634615 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 90033.634615 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 21268000 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 169.030938 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1419 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 168.912200 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1425 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 349 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 4.065903 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 4.083095 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 169.030938 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.082535 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.082535 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 168.912200 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.082477 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.082477 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 349 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 183 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 166 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 170 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 179 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.170410 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 4059 # Number of tag accesses -system.cpu.icache.tags.data_accesses 4059 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 20159000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 1419 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1419 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1419 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1419 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1419 # number of overall hits -system.cpu.icache.overall_hits::total 1419 # number of overall hits +system.cpu.icache.tags.tag_accesses 4071 # Number of tag accesses +system.cpu.icache.tags.data_accesses 4071 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 21268000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 1425 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1425 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1425 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1425 # number of demand (read+write) hits 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-system.cpu.icache.overall_miss_latency::cpu.inst 31654500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 31654500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1855 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1855 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1855 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1855 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1855 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1855 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.235040 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.235040 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.235040 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.235040 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.235040 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.235040 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72602.064220 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 72602.064220 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 72602.064220 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 72602.064220 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 72602.064220 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 72602.064220 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 507 # number of cycles access was blocked +system.cpu.icache.ReadReq_miss_latency::cpu.inst 33901500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 33901500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 33901500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 33901500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 33901500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 33901500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1861 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1861 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1861 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1861 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1861 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1861 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.234283 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.234283 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.234283 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.234283 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.234283 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.234283 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77755.733945 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 77755.733945 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 77755.733945 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 77755.733945 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 77755.733945 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 77755.733945 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 567 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 101.400000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 113.400000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.ReadReq_mshr_hits::cpu.inst 86 # number of ReadReq MSHR hits system.cpu.icache.ReadReq_mshr_hits::total 86 # number of ReadReq MSHR hits @@ -756,43 +767,43 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 350 system.cpu.icache.demand_mshr_misses::total 350 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 350 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 350 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 26454000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 26454000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 26454000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 26454000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 26454000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 26454000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.188679 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.188679 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.188679 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.188679 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.188679 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.188679 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75582.857143 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75582.857143 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75582.857143 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 75582.857143 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75582.857143 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 75582.857143 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 20159000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 28298000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 28298000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 28298000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 28298000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 28298000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 28298000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.188071 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.188071 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.188071 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.188071 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.188071 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.188071 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 80851.428571 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 80851.428571 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 80851.428571 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 80851.428571 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 80851.428571 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 80851.428571 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 21268000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 231.417144 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 231.224808 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 8 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 443 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.018059 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 167.835616 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 63.581529 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005122 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.001940 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.007062 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 167.706281 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 63.518527 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005118 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.001938 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.007056 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 443 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 202 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 241 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 187 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 256 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.013519 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 4075 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 4075 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 20159000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 21268000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 6 # number of ReadCleanReq hits system.cpu.l2cache.ReadCleanReq_hits::total 6 # number of ReadCleanReq hits system.cpu.l2cache.ReadSharedReq_hits::cpu.data 2 # number of ReadSharedReq hits @@ -815,18 +826,18 @@ system.cpu.l2cache.demand_misses::total 446 # nu system.cpu.l2cache.overall_misses::cpu.inst 344 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 102 # number of overall misses system.cpu.l2cache.overall_misses::total 446 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4475000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 4475000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 25861000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 25861000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4379000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 4379000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 25861000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 8854000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 34715000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 25861000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 8854000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 34715000 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4620000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 4620000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 27705000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 27705000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4563000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 4563000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 27705000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 9183000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 36888000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 27705000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 9183000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 36888000 # number of overall miss cycles system.cpu.l2cache.ReadExReq_accesses::cpu.data 47 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 47 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 350 # number of ReadCleanReq accesses(hits+misses) @@ -851,18 +862,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.982379 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.982857 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.980769 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.982379 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 95212.765957 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 95212.765957 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75177.325581 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75177.325581 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 79618.181818 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 79618.181818 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75177.325581 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 86803.921569 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 77836.322870 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75177.325581 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 86803.921569 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 77836.322870 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 98297.872340 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 98297.872340 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 80537.790698 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 80537.790698 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 82963.636364 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 82963.636364 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80537.790698 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 90029.411765 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 82708.520179 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80537.790698 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 90029.411765 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 82708.520179 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -881,18 +892,18 @@ system.cpu.l2cache.demand_mshr_misses::total 446 system.cpu.l2cache.overall_mshr_misses::cpu.inst 344 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 102 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 446 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4005000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4005000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 22431000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 22431000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 3849000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 3849000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22431000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7854000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 30285000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22431000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7854000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 30285000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4150000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4150000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 24275000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 24275000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4033000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4033000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24275000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8183000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 32458000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24275000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8183000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 32458000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.982857 # mshr miss rate for ReadCleanReq accesses @@ -905,25 +916,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.982379 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.982857 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.980769 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.982379 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 85212.765957 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 85212.765957 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65206.395349 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65206.395349 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 69981.818182 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 69981.818182 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65206.395349 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 77000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67903.587444 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65206.395349 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 77000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67903.587444 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 88297.872340 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 88297.872340 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70566.860465 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70566.860465 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73327.272727 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73327.272727 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70566.860465 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 80225.490196 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72775.784753 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70566.860465 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 80225.490196 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72775.784753 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 454 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 8 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 20159000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 21268000 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 404 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 47 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 47 # Transaction distribution @@ -951,16 +962,16 @@ system.cpu.toL2Bus.snoop_fanout::total 454 # Re system.cpu.toL2Bus.reqLayer0.occupancy 227000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 523500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.6 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.utilization 2.5 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 153000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) system.membus.snoop_filter.tot_requests 445 # Total number of requests made to the snoop filter. system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 20159000 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 21268000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 396 # Transaction distribution system.membus.trans_dist::ReadExReq 47 # Transaction distribution system.membus.trans_dist::ReadExResp 47 # Transaction distribution @@ -981,9 +992,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 445 # Request fanout histogram -system.membus.reqLayer0.occupancy 553500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 2340000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 11.6 # Layer utilization (%) +system.membus.reqLayer0.occupancy 553000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.6 # Layer utilization (%) +system.membus.respLayer1.occupancy 2325250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 10.9 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini index 0ce55f79c..7609bf228 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini @@ -14,6 +14,7 @@ children=clk_domain cpu dvfs_handler mem_ctrls ruby sys_port_proxy voltage_domai boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 exit_on_work_items=false init_param=0 @@ -22,11 +23,15 @@ kernel_addr_check=true load_addr_mask=1099511627775 load_offset=0 mem_mode=timing -mem_ranges=0:268435455 +mem_ranges=0:268435455:0:0:0:0 memories=system.mem_ctrls mmap_using_noreserve=false multi_thread=false num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null readfile= symbolfile= thermal_components= @@ -55,6 +60,7 @@ branchPred=Null checker=Null clk_domain=system.cpu.clk_domain cpu_id=0 +default_p_state=UNDEFINED do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true @@ -70,6 +76,10 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null profile=0 progress_interval=0 simpoint_start_insts= @@ -121,7 +131,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/dist/m5/regression/test-progs/hello/bin/sparc/linux/hello +executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/sparc/linux/hello gid=100 input=cin kvmInSE=false @@ -144,27 +154,27 @@ transition_latency=100000 [system.mem_ctrls] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -176,6 +186,7 @@ burst_length=8 channels=1 clk_domain=system.clk_domain conf_table_reported=true +default_p_state=UNDEFINED device_bus_width=8 device_rowbuffer_size=1024 device_size=536870912 @@ -183,12 +194,17 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 page_policy=open_adaptive -range=0:268435455 +power_model=Null +range=0:268435455:5:19:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10 @@ -210,9 +226,9 @@ tRTW=3 tWR=15 tWTR=8 tXAW=30 -tXP=0 +tXP=6 tXPDLL=0 -tXS=0 +tXS=270 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 @@ -226,12 +242,17 @@ access_backing_store=false all_instructions=false block_size_bytes=64 clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED eventq_index=0 hot_lines=false memory_size_bits=48 num_of_sequencers=1 number_of_virtual_networks=5 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 phys_mem=Null +power_model=Null randomization=false [system.ruby.clk_domain] @@ -248,6 +269,7 @@ children=directory dmaRequestToDir dmaResponseFromDir forwardFromDir requestToDi buffer_size=0 clk_domain=system.ruby.clk_domain cluster_id=0 +default_p_state=UNDEFINED directory=system.ruby.dir_cntrl0.directory directory_latency=12 dmaRequestToDir=system.ruby.dir_cntrl0.dmaRequestToDir @@ -255,6 +277,10 @@ dmaResponseFromDir=system.ruby.dir_cntrl0.dmaResponseFromDir eventq_index=0 forwardFromDir=system.ruby.dir_cntrl0.forwardFromDir number_of_TBEs=256 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null recycle_latency=10 requestToDir=system.ruby.dir_cntrl0.requestToDir responseFromDir=system.ruby.dir_cntrl0.responseFromDir @@ -328,11 +354,16 @@ cacheMemory=system.ruby.l1_cntrl0.cacheMemory cache_response_latency=12 clk_domain=system.cpu.clk_domain cluster_id=0 +default_p_state=UNDEFINED eventq_index=0 forwardToCache=system.ruby.l1_cntrl0.forwardToCache issue_latency=2 mandatoryQueue=system.ruby.l1_cntrl0.mandatoryQueue number_of_TBEs=256 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null recycle_latency=10 requestFromCache=system.ruby.l1_cntrl0.requestFromCache responseFromCache=system.ruby.l1_cntrl0.responseFromCache @@ -414,17 +445,22 @@ coreid=99 dcache=system.ruby.l1_cntrl0.cacheMemory dcache_hit_latency=1 deadlock_threshold=500000 +default_p_state=UNDEFINED eventq_index=0 +garnet_standalone=false icache=system.ruby.l1_cntrl0.cacheMemory icache_hit_latency=1 is_cpu_sequencer=true max_outstanding_requests=16 no_retry_on_stall=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null ruby_system=system.ruby support_data_reqs=true support_inst_reqs=true system=system -using_network_tester=false using_ruby_tester=false version=0 slave=system.cpu.icache_port system.cpu.dcache_port @@ -437,18 +473,23 @@ eventq_index=0 [system.ruby.network] type=SimpleNetwork -children=ext_links0 ext_links1 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_links0 int_links1 routers0 routers1 routers2 +children=ext_links0 ext_links1 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_link_buffers20 int_link_buffers21 int_link_buffers22 int_link_buffers23 int_link_buffers24 int_link_buffers25 int_link_buffers26 int_link_buffers27 int_link_buffers28 int_link_buffers29 int_link_buffers30 int_link_buffers31 int_link_buffers32 int_link_buffers33 int_link_buffers34 int_link_buffers35 int_link_buffers36 int_link_buffers37 int_link_buffers38 int_link_buffers39 int_links0 int_links1 int_links2 int_links3 routers0 routers1 routers2 adaptive_routing=false buffer_size=0 clk_domain=system.ruby.clk_domain control_msg_size=8 +default_p_state=UNDEFINED endpoint_bandwidth=1000 eventq_index=0 ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1 -int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19 -int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 +int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19 system.ruby.network.int_link_buffers20 system.ruby.network.int_link_buffers21 system.ruby.network.int_link_buffers22 system.ruby.network.int_link_buffers23 system.ruby.network.int_link_buffers24 system.ruby.network.int_link_buffers25 system.ruby.network.int_link_buffers26 system.ruby.network.int_link_buffers27 system.ruby.network.int_link_buffers28 system.ruby.network.int_link_buffers29 system.ruby.network.int_link_buffers30 system.ruby.network.int_link_buffers31 system.ruby.network.int_link_buffers32 system.ruby.network.int_link_buffers33 system.ruby.network.int_link_buffers34 system.ruby.network.int_link_buffers35 system.ruby.network.int_link_buffers36 system.ruby.network.int_link_buffers37 system.ruby.network.int_link_buffers38 system.ruby.network.int_link_buffers39 +int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2 system.ruby.network.int_links3 netifs= number_of_virtual_networks=5 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null routers=system.ruby.network.routers0 system.ruby.network.routers1 system.ruby.network.routers2 ruby_system=system.ruby topology=Crossbar @@ -615,32 +656,206 @@ eventq_index=0 ordered=true randomization=false +[system.ruby.network.int_link_buffers20] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers21] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers22] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers23] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers24] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers25] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers26] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers27] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers28] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers29] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers30] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers31] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers32] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers33] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers34] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers35] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers36] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers37] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers38] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers39] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + [system.ruby.network.int_links0] type=SimpleIntLink bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers2 eventq_index=0 latency=1 link_id=2 -node_a=system.ruby.network.routers0 -node_b=system.ruby.network.routers2 +src_node=system.ruby.network.routers0 +src_outport= weight=1 [system.ruby.network.int_links1] type=SimpleIntLink bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers2 eventq_index=0 latency=1 link_id=3 -node_a=system.ruby.network.routers1 -node_b=system.ruby.network.routers2 +src_node=system.ruby.network.routers1 +src_outport= +weight=1 + +[system.ruby.network.int_links2] +type=SimpleIntLink +bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers0 +eventq_index=0 +latency=1 +link_id=4 +src_node=system.ruby.network.routers2 +src_outport= +weight=1 + +[system.ruby.network.int_links3] +type=SimpleIntLink +bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers1 +eventq_index=0 +latency=1 +link_id=5 +src_node=system.ruby.network.routers2 +src_outport= weight=1 [system.ruby.network.routers0] type=Switch children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED eventq_index=0 +latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 port_buffers=system.ruby.network.routers0.port_buffers00 system.ruby.network.routers0.port_buffers01 system.ruby.network.routers0.port_buffers02 system.ruby.network.routers0.port_buffers03 system.ruby.network.routers0.port_buffers04 system.ruby.network.routers0.port_buffers05 system.ruby.network.routers0.port_buffers06 system.ruby.network.routers0.port_buffers07 system.ruby.network.routers0.port_buffers08 system.ruby.network.routers0.port_buffers09 system.ruby.network.routers0.port_buffers10 system.ruby.network.routers0.port_buffers11 system.ruby.network.routers0.port_buffers12 system.ruby.network.routers0.port_buffers13 system.ruby.network.routers0.port_buffers14 +power_model=Null router_id=0 virt_nets=5 @@ -753,8 +968,14 @@ randomization=false type=Switch children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED eventq_index=0 +latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 port_buffers=system.ruby.network.routers1.port_buffers00 system.ruby.network.routers1.port_buffers01 system.ruby.network.routers1.port_buffers02 system.ruby.network.routers1.port_buffers03 system.ruby.network.routers1.port_buffers04 system.ruby.network.routers1.port_buffers05 system.ruby.network.routers1.port_buffers06 system.ruby.network.routers1.port_buffers07 system.ruby.network.routers1.port_buffers08 system.ruby.network.routers1.port_buffers09 system.ruby.network.routers1.port_buffers10 system.ruby.network.routers1.port_buffers11 system.ruby.network.routers1.port_buffers12 system.ruby.network.routers1.port_buffers13 system.ruby.network.routers1.port_buffers14 +power_model=Null router_id=1 virt_nets=5 @@ -867,8 +1088,14 @@ randomization=false type=Switch children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17 port_buffers18 port_buffers19 clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED eventq_index=0 +latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 port_buffers=system.ruby.network.routers2.port_buffers00 system.ruby.network.routers2.port_buffers01 system.ruby.network.routers2.port_buffers02 system.ruby.network.routers2.port_buffers03 system.ruby.network.routers2.port_buffers04 system.ruby.network.routers2.port_buffers05 system.ruby.network.routers2.port_buffers06 system.ruby.network.routers2.port_buffers07 system.ruby.network.routers2.port_buffers08 system.ruby.network.routers2.port_buffers09 system.ruby.network.routers2.port_buffers10 system.ruby.network.routers2.port_buffers11 system.ruby.network.routers2.port_buffers12 system.ruby.network.routers2.port_buffers13 system.ruby.network.routers2.port_buffers14 system.ruby.network.routers2.port_buffers15 system.ruby.network.routers2.port_buffers16 system.ruby.network.routers2.port_buffers17 system.ruby.network.routers2.port_buffers18 system.ruby.network.routers2.port_buffers19 +power_model=Null router_id=2 virt_nets=5 @@ -1015,9 +1242,14 @@ randomization=false [system.sys_port_proxy] type=RubyPortProxy clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 is_cpu_sequencer=true no_retry_on_stall=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null ruby_system=system.ruby support_data_reqs=true support_inst_reqs=true diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simerr b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simerr index ccfdd3697..f6f6f15a5 100755 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simerr +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simerr @@ -4,8 +4,7 @@ warn: rounding error > tolerance 1.250000 rounded to 1 warn: rounding error > tolerance 1.250000 rounded to 1 -warn: rounding error > tolerance - 1.250000 rounded to 1 warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes) warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files! diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simout b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simout index ed1dc8177..36ed80c84 100755 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simout +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simout @@ -1,11 +1,13 @@ +Redirecting stdout to build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing-ruby/simout +Redirecting stderr to build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing-ruby/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 21 2016 14:30:54 -gem5 started Jan 21 2016 14:31:28 -gem5 executing on zizzer, pid 8746 -command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing-ruby -re /z/atgutier/gem5/gem5-commit/tests/run.py build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing-ruby +gem5 compiled Oct 13 2016 20:43:27 +gem5 started Oct 13 2016 20:46:33 +gem5 executing on e108600-lin, pid 17405 +command line: /work/curdun01/gem5-external.hg/build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing-ruby -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/sparc/linux/simple-timing-ruby Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... -Hello World!Exiting @ tick 81703 because target called exit() +Hello World!Exiting @ tick 86746 because target called exit() diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt index 3b20a8d52..a1c151f90 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000082 # Number of seconds simulated -sim_ticks 81703 # Number of ticks simulated -final_tick 81703 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000087 # Number of seconds simulated +sim_ticks 86746 # Number of ticks simulated +final_tick 86746 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 107011 # Simulator instruction rate (inst/s) -host_op_rate 106993 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1640735 # Simulator tick rate (ticks/s) -host_mem_usage 456212 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host +host_inst_rate 61570 # Simulator instruction rate (inst/s) +host_op_rate 61552 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1002076 # Simulator tick rate (ticks/s) +host_mem_usage 413704 # Number of bytes of host memory used +host_seconds 0.09 # Real time elapsed on the host sim_insts 5327 # Number of instructions simulated sim_ops 5327 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks -system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 81703 # Cumulative time (in ticks) in various power states +system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 86746 # Cumulative time (in ticks) in various power states system.mem_ctrls.bytes_read::ruby.dir_cntrl0 82496 # Number of bytes read from this memory system.mem_ctrls.bytes_read::total 82496 # Number of bytes read from this memory system.mem_ctrls.bytes_written::ruby.dir_cntrl0 82240 # Number of bytes written to this memory @@ -22,59 +22,59 @@ system.mem_ctrls.num_reads::ruby.dir_cntrl0 1289 # system.mem_ctrls.num_reads::total 1289 # Number of read requests responded to by this memory system.mem_ctrls.num_writes::ruby.dir_cntrl0 1285 # Number of write requests responded to by this memory system.mem_ctrls.num_writes::total 1285 # Number of write requests responded to by this memory -system.mem_ctrls.bw_read::ruby.dir_cntrl0 1009705886 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_read::total 1009705886 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::ruby.dir_cntrl0 1006572586 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::total 1006572586 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_total::ruby.dir_cntrl0 2016278472 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.bw_total::total 2016278472 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_read::ruby.dir_cntrl0 951006386 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 951006386 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::ruby.dir_cntrl0 948055242 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::total 948055242 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::ruby.dir_cntrl0 1899061628 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 1899061628 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrls.readReqs 1289 # Number of read requests accepted system.mem_ctrls.writeReqs 1285 # Number of write requests accepted system.mem_ctrls.readBursts 1289 # Number of DRAM read bursts, including those serviced by the write queue system.mem_ctrls.writeBursts 1285 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrls.bytesReadDRAM 43904 # Total number of bytes read from DRAM -system.mem_ctrls.bytesReadWrQ 38592 # Total number of bytes read from write queue -system.mem_ctrls.bytesWritten 43776 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadDRAM 44800 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 37696 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 45504 # Total number of bytes written to DRAM system.mem_ctrls.bytesReadSys 82496 # Total read bytes from the system interface side system.mem_ctrls.bytesWrittenSys 82240 # Total written bytes from the system interface side -system.mem_ctrls.servicedByWrQ 603 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrls.mergedWrBursts 579 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.servicedByWrQ 589 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 555 # Number of DRAM write bursts merged with an existing one system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.mem_ctrls.perBankRdBursts::0 28 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::1 18 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 17 # Per bank write bursts system.mem_ctrls.perBankRdBursts::2 1 # Per bank write bursts system.mem_ctrls.perBankRdBursts::3 8 # Per bank write bursts system.mem_ctrls.perBankRdBursts::4 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::5 119 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::6 115 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::7 134 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::8 61 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::9 34 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::10 12 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::11 59 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 121 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 141 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::8 55 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::9 31 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 13 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 62 # Per bank write bursts system.mem_ctrls.perBankRdBursts::12 21 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::13 59 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::14 9 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 61 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 14 # Per bank write bursts system.mem_ctrls.perBankRdBursts::15 8 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::0 29 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 28 # Per bank write bursts system.mem_ctrls.perBankWrBursts::1 18 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::2 2 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 1 # Per bank write bursts system.mem_ctrls.perBankWrBursts::3 8 # Per bank write bursts system.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::5 117 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::6 112 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::7 138 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::8 63 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 118 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 114 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 141 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::8 61 # Per bank write bursts system.mem_ctrls.perBankWrBursts::9 35 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::10 13 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::11 59 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::12 21 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::13 51 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::14 10 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 14 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::11 62 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::12 23 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 64 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 16 # Per bank write bursts system.mem_ctrls.perBankWrBursts::15 8 # Per bank write bursts system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrls.totGap 81643 # Total gap between requests +system.mem_ctrls.totGap 86680 # Total gap between requests system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) @@ -89,7 +89,7 @@ system.mem_ctrls.writePktSize::3 0 # Wr system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::6 1285 # Write request sizes (log2) -system.mem_ctrls.rdQLenPdf::0 686 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::0 700 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see @@ -136,25 +136,25 @@ system.mem_ctrls.wrQLenPdf::11 1 # Wh system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::15 5 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::16 5 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::17 34 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 3 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 3 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 35 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::18 45 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::19 45 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::20 48 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::21 46 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::22 42 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::23 42 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::24 42 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::25 42 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::26 42 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::27 42 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::28 42 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::29 42 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::30 42 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::31 42 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::32 42 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::33 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 49 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 49 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 46 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 44 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::24 44 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 44 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 44 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 44 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::28 44 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 44 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 44 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 44 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::32 44 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see @@ -185,95 +185,103 @@ system.mem_ctrls.wrQLenPdf::60 0 # Wh system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrls.bytesPerActivate::samples 227 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::mean 379.207048 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::gmean 252.014148 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::stdev 323.708826 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::0-127 44 19.38% 19.38% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::128-255 63 27.75% 47.14% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::256-383 29 12.78% 59.91% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::384-511 17 7.49% 67.40% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::512-639 17 7.49% 74.89% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::640-767 17 7.49% 82.38% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::768-895 9 3.96% 86.34% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::896-1023 6 2.64% 88.99% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::1024-1151 25 11.01% 100.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::total 227 # Bytes accessed per row activation -system.mem_ctrls.rdPerTurnAround::samples 42 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::mean 16.190476 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::gmean 15.978361 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::stdev 3.255300 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::12-13 3 7.14% 7.14% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::14-15 10 23.81% 30.95% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::16-17 26 61.90% 92.86% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::18-19 1 2.38% 95.24% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::20-21 1 2.38% 97.62% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::34-35 1 2.38% 100.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::total 42 # Reads before turning the bus around for writes -system.mem_ctrls.wrPerTurnAround::samples 42 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::mean 16.285714 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::gmean 16.270299 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::stdev 0.741972 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::16 36 85.71% 85.71% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::17 1 2.38% 88.10% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::18 4 9.52% 97.62% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::19 1 2.38% 100.00% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::total 42 # Writes before turning the bus around for reads -system.mem_ctrls.totQLat 8350 # Total ticks spent queuing -system.mem_ctrls.totMemAccLat 21384 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrls.totBusLat 3430 # Total ticks spent in databus transfers -system.mem_ctrls.avgQLat 12.17 # Average queueing delay per DRAM burst +system.mem_ctrls.bytesPerActivate::samples 247 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 359.384615 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 236.451062 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 319.751749 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 54 21.86% 21.86% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 65 26.32% 48.18% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 38 15.38% 63.56% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 27 10.93% 74.49% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 8 3.24% 77.73% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 10 4.05% 81.78% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 11 4.45% 86.23% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 9 3.64% 89.88% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 25 10.12% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 247 # Bytes accessed per row activation +system.mem_ctrls.rdPerTurnAround::samples 44 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::mean 15.840909 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::gmean 15.640724 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::stdev 3.183849 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::12-13 2 4.55% 4.55% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::14-15 21 47.73% 52.27% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::16-17 18 40.91% 93.18% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::18-19 2 4.55% 97.73% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::34-35 1 2.27% 100.00% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::total 44 # Reads before turning the bus around for writes +system.mem_ctrls.wrPerTurnAround::samples 44 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::mean 16.159091 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::gmean 16.147705 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::stdev 0.644951 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::16 41 93.18% 93.18% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::17 1 2.27% 95.45% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::19 2 4.55% 100.00% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::total 44 # Writes before turning the bus around for reads +system.mem_ctrls.totQLat 12987 # Total ticks spent queuing +system.mem_ctrls.totMemAccLat 26287 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.totBusLat 3500 # Total ticks spent in databus transfers +system.mem_ctrls.avgQLat 18.55 # Average queueing delay per DRAM burst system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst -system.mem_ctrls.avgMemAccLat 31.17 # Average memory access latency per DRAM burst -system.mem_ctrls.avgRdBW 537.36 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrls.avgWrBW 535.79 # Average achieved write bandwidth in MiByte/s -system.mem_ctrls.avgRdBWSys 1009.71 # Average system read bandwidth in MiByte/s -system.mem_ctrls.avgWrBWSys 1006.57 # Average system write bandwidth in MiByte/s +system.mem_ctrls.avgMemAccLat 37.55 # Average memory access latency per DRAM burst +system.mem_ctrls.avgRdBW 516.45 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 524.57 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 951.01 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 948.06 # Average system write bandwidth in MiByte/s system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrls.busUtil 8.38 # Data bus utilization in percentage -system.mem_ctrls.busUtilRead 4.20 # Data bus utilization in percentage for reads -system.mem_ctrls.busUtilWrite 4.19 # Data bus utilization in percentage for writes +system.mem_ctrls.busUtil 8.13 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 4.03 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 4.10 # Data bus utilization in percentage for writes system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing -system.mem_ctrls.avgWrQLen 25.98 # Average write queue length when enqueuing -system.mem_ctrls.readRowHits 503 # Number of row buffer hits during reads -system.mem_ctrls.writeRowHits 635 # Number of row buffer hits during writes -system.mem_ctrls.readRowHitRate 73.32 # Row buffer hit rate for reads -system.mem_ctrls.writeRowHitRate 89.94 # Row buffer hit rate for writes -system.mem_ctrls.avgGap 31.72 # Average gap between requests -system.mem_ctrls.pageHitRate 81.75 # Row buffer hit rate, read and write combined -system.mem_ctrls_0.actEnergy 960120 # Energy for activate commands per rank (pJ) -system.mem_ctrls_0.preEnergy 533400 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_0.readEnergy 4992000 # Energy for read commands per rank (pJ) -system.mem_ctrls_0.writeEnergy 3981312 # Energy for write commands per rank (pJ) -system.mem_ctrls_0.refreshEnergy 5085600 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_0.actBackEnergy 48305448 # Energy for active background per rank (pJ) -system.mem_ctrls_0.preBackEnergy 4498800 # Energy for precharge background per rank (pJ) -system.mem_ctrls_0.totalEnergy 68356680 # Total energy per rank (pJ) -system.mem_ctrls_0.averagePower 875.021505 # Core power per rank (mW) -system.mem_ctrls_0.memoryStateTime::IDLE 7218 # Time in different power states -system.mem_ctrls_0.memoryStateTime::REF 2600 # Time in different power states -system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT 68316 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrls_1.actEnergy 703080 # Energy for activate commands per rank (pJ) -system.mem_ctrls_1.preEnergy 390600 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_1.readEnergy 3107520 # Energy for read commands per rank (pJ) -system.mem_ctrls_1.writeEnergy 2602368 # Energy for write commands per rank (pJ) -system.mem_ctrls_1.refreshEnergy 5085600 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_1.actBackEnergy 45961380 # Energy for active background per rank (pJ) -system.mem_ctrls_1.preBackEnergy 6555000 # Energy for precharge background per rank (pJ) -system.mem_ctrls_1.totalEnergy 64405548 # Total energy per rank (pJ) -system.mem_ctrls_1.averagePower 824.443779 # Core power per rank (mW) -system.mem_ctrls_1.memoryStateTime::IDLE 10688 # Time in different power states -system.mem_ctrls_1.memoryStateTime::REF 2600 # Time in different power states -system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT 64875 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 81703 # Cumulative time (in ticks) in various power states +system.mem_ctrls.avgWrQLen 25.18 # Average write queue length when enqueuing +system.mem_ctrls.readRowHits 508 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 652 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 72.57 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate 89.32 # Row buffer hit rate for writes +system.mem_ctrls.avgGap 33.68 # Average gap between requests +system.mem_ctrls.pageHitRate 81.12 # Row buffer hit rate, read and write combined +system.mem_ctrls_0.actEnergy 1099560 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 587328 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 4969440 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 3574656 # Energy for write commands per rank (pJ) +system.mem_ctrls_0.refreshEnergy 6761040.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 10338432 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 148224 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.actPowerDownEnergy 27605784 # Energy for active power-down per rank (pJ) +system.mem_ctrls_0.prePowerDownEnergy 1209216 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls_0.totalEnergy 56293680 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 648.948424 # Core power per rank (mW) +system.mem_ctrls_0.totalIdleTime 63519 # Total Idle time Per DRAM Rank +system.mem_ctrls_0.memoryStateTime::IDLE 64 # Time in different power states +system.mem_ctrls_0.memoryStateTime::REF 2860 # Time in different power states +system.mem_ctrls_0.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls_0.memoryStateTime::PRE_PDN 3149 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 20134 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT_PDN 60539 # Time in different power states +system.mem_ctrls_1.actEnergy 692580 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 367080 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 3027360 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 2363616 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.refreshEnergy 6761040.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 9621600 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 296448 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.actPowerDownEnergy 26302992 # Energy for active power-down per rank (pJ) +system.mem_ctrls_1.prePowerDownEnergy 2761728 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls_1.totalEnergy 52194444 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 601.692804 # Core power per rank (mW) +system.mem_ctrls_1.totalIdleTime 64843 # Total Idle time Per DRAM Rank +system.mem_ctrls_1.memoryStateTime::IDLE 422 # Time in different power states +system.mem_ctrls_1.memoryStateTime::REF 2860 # Time in different power states +system.mem_ctrls_1.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls_1.memoryStateTime::PRE_PDN 7192 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 18590 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT_PDN 57682 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 86746 # Cumulative time (in ticks) in various power states system.cpu.clk_domain.clock 1 # Clock period in ticks system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 81703 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 81703 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 86746 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 86746 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 5327 # Number of instructions committed @@ -292,7 +300,7 @@ system.cpu.num_mem_refs 1401 # nu system.cpu.num_load_insts 723 # Number of load instructions system.cpu.num_store_insts 678 # Number of store instructions system.cpu.num_idle_cycles 0.999988 # Number of idle cycles -system.cpu.num_busy_cycles 81702.000012 # Number of busy cycles +system.cpu.num_busy_cycles 86745.000012 # Number of busy cycles system.cpu.not_idle_fraction 0.999988 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000012 # Percentage of idle cycles system.cpu.Branches 1121 # Number of branches fetched @@ -332,7 +340,7 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 5370 # Class of executed instruction system.ruby.clk_domain.clock 1 # Clock period in ticks -system.ruby.pwrStateResidencyTicks::UNDEFINED 81703 # Cumulative time (in ticks) in various power states +system.ruby.pwrStateResidencyTicks::UNDEFINED 86746 # Cumulative time (in ticks) in various power states system.ruby.delayHist::bucket_size 1 # delay histogram for all message system.ruby.delayHist::max_bucket 9 # delay histogram for all message system.ruby.delayHist::samples 2574 # delay histogram for all message @@ -348,10 +356,10 @@ system.ruby.outstanding_req_hist_seqr::total 6759 system.ruby.latency_hist_seqr::bucket_size 64 system.ruby.latency_hist_seqr::max_bucket 639 system.ruby.latency_hist_seqr::samples 6758 -system.ruby.latency_hist_seqr::mean 11.089819 -system.ruby.latency_hist_seqr::gmean 2.095228 -system.ruby.latency_hist_seqr::stdev 25.111209 -system.ruby.latency_hist_seqr | 6551 96.94% 96.94% | 169 2.50% 99.44% | 28 0.41% 99.85% | 2 0.03% 99.88% | 5 0.07% 99.96% | 2 0.03% 99.99% | 1 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.latency_hist_seqr::mean 11.836046 +system.ruby.latency_hist_seqr::gmean 2.117342 +system.ruby.latency_hist_seqr::stdev 27.149732 +system.ruby.latency_hist_seqr | 6079 89.95% 89.95% | 633 9.37% 99.32% | 36 0.53% 99.85% | 1 0.01% 99.87% | 6 0.09% 99.96% | 2 0.03% 99.99% | 0 0.00% 99.99% | 1 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.latency_hist_seqr::total 6758 system.ruby.hit_latency_hist_seqr::bucket_size 1 system.ruby.hit_latency_hist_seqr::max_bucket 9 @@ -363,21 +371,21 @@ system.ruby.hit_latency_hist_seqr::total 5469 system.ruby.miss_latency_hist_seqr::bucket_size 64 system.ruby.miss_latency_hist_seqr::max_bucket 639 system.ruby.miss_latency_hist_seqr::samples 1289 -system.ruby.miss_latency_hist_seqr::mean 53.899147 -system.ruby.miss_latency_hist_seqr::gmean 48.323546 -system.ruby.miss_latency_hist_seqr::stdev 32.275754 -system.ruby.miss_latency_hist_seqr | 1082 83.94% 83.94% | 169 13.11% 97.05% | 28 2.17% 99.22% | 2 0.16% 99.38% | 5 0.39% 99.77% | 2 0.16% 99.92% | 1 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.miss_latency_hist_seqr::mean 57.811482 +system.ruby.miss_latency_hist_seqr::gmean 51.058094 +system.ruby.miss_latency_hist_seqr::stdev 35.397665 +system.ruby.miss_latency_hist_seqr | 610 47.32% 47.32% | 633 49.11% 96.43% | 36 2.79% 99.22% | 1 0.08% 99.30% | 6 0.47% 99.77% | 2 0.16% 99.92% | 0 0.00% 99.92% | 1 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.miss_latency_hist_seqr::total 1289 system.ruby.Directory.incomplete_times_seqr 1288 -system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 81703 # Cumulative time (in ticks) in various power states +system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 86746 # Cumulative time (in ticks) in various power states system.ruby.l1_cntrl0.cacheMemory.demand_hits 5469 # Number of cache demand hits system.ruby.l1_cntrl0.cacheMemory.demand_misses 1289 # Number of cache demand misses system.ruby.l1_cntrl0.cacheMemory.demand_accesses 6758 # Number of cache demand accesses -system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 81703 # Cumulative time (in ticks) in various power states -system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 81703 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 86746 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 86746 # Cumulative time (in ticks) in various power states system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 81703 # Cumulative time (in ticks) in various power states -system.ruby.network.routers0.percent_links_utilized 7.876088 +system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 86746 # Cumulative time (in ticks) in various power states +system.ruby.network.routers0.percent_links_utilized 7.418209 system.ruby.network.routers0.msg_count.Control::2 1289 system.ruby.network.routers0.msg_count.Data::2 1285 system.ruby.network.routers0.msg_count.Response_Data::4 1289 @@ -386,8 +394,8 @@ system.ruby.network.routers0.msg_bytes.Control::2 10312 system.ruby.network.routers0.msg_bytes.Data::2 92520 system.ruby.network.routers0.msg_bytes.Response_Data::4 92808 system.ruby.network.routers0.msg_bytes.Writeback_Control::3 10280 -system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 81703 # Cumulative time (in ticks) in various power states -system.ruby.network.routers1.percent_links_utilized 7.876088 +system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 86746 # Cumulative time (in ticks) in various power states +system.ruby.network.routers1.percent_links_utilized 7.418209 system.ruby.network.routers1.msg_count.Control::2 1289 system.ruby.network.routers1.msg_count.Data::2 1285 system.ruby.network.routers1.msg_count.Response_Data::4 1289 @@ -396,8 +404,8 @@ system.ruby.network.routers1.msg_bytes.Control::2 10312 system.ruby.network.routers1.msg_bytes.Data::2 92520 system.ruby.network.routers1.msg_bytes.Response_Data::4 92808 system.ruby.network.routers1.msg_bytes.Writeback_Control::3 10280 -system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 81703 # Cumulative time (in ticks) in various power states -system.ruby.network.routers2.percent_links_utilized 7.876088 +system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 86746 # Cumulative time (in ticks) in various power states +system.ruby.network.routers2.percent_links_utilized 7.418209 system.ruby.network.routers2.msg_count.Control::2 1289 system.ruby.network.routers2.msg_count.Data::2 1285 system.ruby.network.routers2.msg_count.Response_Data::4 1289 @@ -406,7 +414,7 @@ system.ruby.network.routers2.msg_bytes.Control::2 10312 system.ruby.network.routers2.msg_bytes.Data::2 92520 system.ruby.network.routers2.msg_bytes.Response_Data::4 92808 system.ruby.network.routers2.msg_bytes.Writeback_Control::3 10280 -system.ruby.network.pwrStateResidencyTicks::UNDEFINED 81703 # Cumulative time (in ticks) in various power states +system.ruby.network.pwrStateResidencyTicks::UNDEFINED 86746 # Cumulative time (in ticks) in various power states system.ruby.network.msg_count.Control 3867 system.ruby.network.msg_count.Data 3855 system.ruby.network.msg_count.Response_Data 3867 @@ -415,33 +423,33 @@ system.ruby.network.msg_byte.Control 30936 system.ruby.network.msg_byte.Data 277560 system.ruby.network.msg_byte.Response_Data 278424 system.ruby.network.msg_byte.Writeback_Control 30840 -system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 81703 # Cumulative time (in ticks) in various power states -system.ruby.network.routers0.throttle0.link_utilization 7.885879 +system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 86746 # Cumulative time (in ticks) in various power states +system.ruby.network.routers0.throttle0.link_utilization 7.427432 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1289 system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 1285 system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 92808 system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 10280 -system.ruby.network.routers0.throttle1.link_utilization 7.866296 +system.ruby.network.routers0.throttle1.link_utilization 7.408987 system.ruby.network.routers0.throttle1.msg_count.Control::2 1289 system.ruby.network.routers0.throttle1.msg_count.Data::2 1285 system.ruby.network.routers0.throttle1.msg_bytes.Control::2 10312 system.ruby.network.routers0.throttle1.msg_bytes.Data::2 92520 -system.ruby.network.routers1.throttle0.link_utilization 7.866296 +system.ruby.network.routers1.throttle0.link_utilization 7.408987 system.ruby.network.routers1.throttle0.msg_count.Control::2 1289 system.ruby.network.routers1.throttle0.msg_count.Data::2 1285 system.ruby.network.routers1.throttle0.msg_bytes.Control::2 10312 system.ruby.network.routers1.throttle0.msg_bytes.Data::2 92520 -system.ruby.network.routers1.throttle1.link_utilization 7.885879 +system.ruby.network.routers1.throttle1.link_utilization 7.427432 system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 1289 system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 1285 system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 92808 system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 10280 -system.ruby.network.routers2.throttle0.link_utilization 7.885879 +system.ruby.network.routers2.throttle0.link_utilization 7.427432 system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 1289 system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 1285 system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 92808 system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 10280 -system.ruby.network.routers2.throttle1.link_utilization 7.866296 +system.ruby.network.routers2.throttle1.link_utilization 7.408987 system.ruby.network.routers2.throttle1.msg_count.Control::2 1289 system.ruby.network.routers2.throttle1.msg_count.Data::2 1285 system.ruby.network.routers2.throttle1.msg_bytes.Control::2 10312 @@ -459,10 +467,10 @@ system.ruby.delayVCHist.vnet_2::total 1285 # de system.ruby.LD.latency_hist_seqr::bucket_size 64 system.ruby.LD.latency_hist_seqr::max_bucket 639 system.ruby.LD.latency_hist_seqr::samples 715 -system.ruby.LD.latency_hist_seqr::mean 28.394406 -system.ruby.LD.latency_hist_seqr::gmean 8.251059 -system.ruby.LD.latency_hist_seqr::stdev 33.266069 -system.ruby.LD.latency_hist_seqr | 656 91.75% 91.75% | 50 6.99% 98.74% | 8 1.12% 99.86% | 0 0.00% 99.86% | 0 0.00% 99.86% | 0 0.00% 99.86% | 1 0.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.latency_hist_seqr::mean 30.464336 +system.ruby.LD.latency_hist_seqr::gmean 8.484057 +system.ruby.LD.latency_hist_seqr::stdev 36.464169 +system.ruby.LD.latency_hist_seqr | 540 75.52% 75.52% | 163 22.80% 98.32% | 10 1.40% 99.72% | 0 0.00% 99.72% | 1 0.14% 99.86% | 1 0.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.latency_hist_seqr::total 715 system.ruby.LD.hit_latency_hist_seqr::bucket_size 1 system.ruby.LD.hit_latency_hist_seqr::max_bucket 9 @@ -474,18 +482,18 @@ system.ruby.LD.hit_latency_hist_seqr::total 320 system.ruby.LD.miss_latency_hist_seqr::bucket_size 64 system.ruby.LD.miss_latency_hist_seqr::max_bucket 639 system.ruby.LD.miss_latency_hist_seqr::samples 395 -system.ruby.LD.miss_latency_hist_seqr::mean 50.587342 -system.ruby.LD.miss_latency_hist_seqr::gmean 45.603541 -system.ruby.LD.miss_latency_hist_seqr::stdev 30.035585 -system.ruby.LD.miss_latency_hist_seqr | 336 85.06% 85.06% | 50 12.66% 97.72% | 8 2.03% 99.75% | 0 0.00% 99.75% | 0 0.00% 99.75% | 0 0.00% 99.75% | 1 0.25% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.miss_latency_hist_seqr::mean 54.334177 +system.ruby.LD.miss_latency_hist_seqr::gmean 47.961199 +system.ruby.LD.miss_latency_hist_seqr::stdev 33.663530 +system.ruby.LD.miss_latency_hist_seqr | 220 55.70% 55.70% | 163 41.27% 96.96% | 10 2.53% 99.49% | 0 0.00% 99.49% | 1 0.25% 99.75% | 1 0.25% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.miss_latency_hist_seqr::total 395 -system.ruby.ST.latency_hist_seqr::bucket_size 32 -system.ruby.ST.latency_hist_seqr::max_bucket 319 +system.ruby.ST.latency_hist_seqr::bucket_size 64 +system.ruby.ST.latency_hist_seqr::max_bucket 639 system.ruby.ST.latency_hist_seqr::samples 673 -system.ruby.ST.latency_hist_seqr::mean 16.656761 -system.ruby.ST.latency_hist_seqr::gmean 2.888882 -system.ruby.ST.latency_hist_seqr::stdev 31.530024 -system.ruby.ST.latency_hist_seqr | 494 73.40% 73.40% | 146 21.69% 95.10% | 26 3.86% 98.96% | 0 0.00% 98.96% | 4 0.59% 99.55% | 0 0.00% 99.55% | 1 0.15% 99.70% | 0 0.00% 99.70% | 1 0.15% 99.85% | 1 0.15% 100.00% +system.ruby.ST.latency_hist_seqr::mean 17.630015 +system.ruby.ST.latency_hist_seqr::gmean 2.926423 +system.ruby.ST.latency_hist_seqr::stdev 33.570929 +system.ruby.ST.latency_hist_seqr | 555 82.47% 82.47% | 110 16.34% 98.81% | 6 0.89% 99.70% | 0 0.00% 99.70% | 1 0.15% 99.85% | 1 0.15% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ST.latency_hist_seqr::total 673 system.ruby.ST.hit_latency_hist_seqr::bucket_size 1 system.ruby.ST.hit_latency_hist_seqr::max_bucket 9 @@ -494,21 +502,21 @@ system.ruby.ST.hit_latency_hist_seqr::mean 1 system.ruby.ST.hit_latency_hist_seqr::gmean 1 system.ruby.ST.hit_latency_hist_seqr | 0 0.00% 0.00% | 494 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ST.hit_latency_hist_seqr::total 494 -system.ruby.ST.miss_latency_hist_seqr::bucket_size 32 -system.ruby.ST.miss_latency_hist_seqr::max_bucket 319 +system.ruby.ST.miss_latency_hist_seqr::bucket_size 64 +system.ruby.ST.miss_latency_hist_seqr::max_bucket 639 system.ruby.ST.miss_latency_hist_seqr::samples 179 -system.ruby.ST.miss_latency_hist_seqr::mean 59.865922 -system.ruby.ST.miss_latency_hist_seqr::gmean 53.981018 -system.ruby.ST.miss_latency_hist_seqr::stdev 34.573548 -system.ruby.ST.miss_latency_hist_seqr | 0 0.00% 0.00% | 146 81.56% 81.56% | 26 14.53% 96.09% | 0 0.00% 96.09% | 4 2.23% 98.32% | 0 0.00% 98.32% | 1 0.56% 98.88% | 0 0.00% 98.88% | 1 0.56% 99.44% | 1 0.56% 100.00% +system.ruby.ST.miss_latency_hist_seqr::mean 63.525140 +system.ruby.ST.miss_latency_hist_seqr::gmean 56.666113 +system.ruby.ST.miss_latency_hist_seqr::stdev 37.000656 +system.ruby.ST.miss_latency_hist_seqr | 61 34.08% 34.08% | 110 61.45% 95.53% | 6 3.35% 98.88% | 0 0.00% 98.88% | 1 0.56% 99.44% | 1 0.56% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ST.miss_latency_hist_seqr::total 179 system.ruby.IFETCH.latency_hist_seqr::bucket_size 64 system.ruby.IFETCH.latency_hist_seqr::max_bucket 639 system.ruby.IFETCH.latency_hist_seqr::samples 5370 -system.ruby.IFETCH.latency_hist_seqr::mean 8.088082 -system.ruby.IFETCH.latency_hist_seqr::gmean 1.676829 -system.ruby.IFETCH.latency_hist_seqr::stdev 21.661449 -system.ruby.IFETCH.latency_hist_seqr | 5255 97.86% 97.86% | 93 1.73% 99.59% | 16 0.30% 99.89% | 1 0.02% 99.91% | 3 0.06% 99.96% | 2 0.04% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.latency_hist_seqr::mean 8.629609 +system.ruby.IFETCH.latency_hist_seqr::gmean 1.690107 +system.ruby.IFETCH.latency_hist_seqr::stdev 23.432463 +system.ruby.IFETCH.latency_hist_seqr | 4984 92.81% 92.81% | 360 6.70% 99.52% | 20 0.37% 99.89% | 1 0.02% 99.91% | 4 0.07% 99.98% | 0 0.00% 99.98% | 0 0.00% 99.98% | 1 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.latency_hist_seqr::total 5370 system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 1 system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 9 @@ -520,18 +528,18 @@ system.ruby.IFETCH.hit_latency_hist_seqr::total 4655 system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 64 system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 639 system.ruby.IFETCH.miss_latency_hist_seqr::samples 715 -system.ruby.IFETCH.miss_latency_hist_seqr::mean 54.234965 -system.ruby.IFETCH.miss_latency_hist_seqr::gmean 48.531211 -system.ruby.IFETCH.miss_latency_hist_seqr::stdev 32.684395 -system.ruby.IFETCH.miss_latency_hist_seqr | 600 83.92% 83.92% | 93 13.01% 96.92% | 16 2.24% 99.16% | 1 0.14% 99.30% | 3 0.42% 99.72% | 2 0.28% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.miss_latency_hist_seqr::mean 58.302098 +system.ruby.IFETCH.miss_latency_hist_seqr::gmean 51.492810 +system.ruby.IFETCH.miss_latency_hist_seqr::stdev 35.756740 +system.ruby.IFETCH.miss_latency_hist_seqr | 329 46.01% 46.01% | 360 50.35% 96.36% | 20 2.80% 99.16% | 1 0.14% 99.30% | 4 0.56% 99.86% | 0 0.00% 99.86% | 0 0.00% 99.86% | 1 0.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.miss_latency_hist_seqr::total 715 system.ruby.Directory.miss_mach_latency_hist_seqr::bucket_size 64 system.ruby.Directory.miss_mach_latency_hist_seqr::max_bucket 639 system.ruby.Directory.miss_mach_latency_hist_seqr::samples 1289 -system.ruby.Directory.miss_mach_latency_hist_seqr::mean 53.899147 -system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 48.323546 -system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 32.275754 -system.ruby.Directory.miss_mach_latency_hist_seqr | 1082 83.94% 83.94% | 169 13.11% 97.05% | 28 2.17% 99.22% | 2 0.16% 99.38% | 5 0.39% 99.77% | 2 0.16% 99.92% | 1 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_mach_latency_hist_seqr::mean 57.811482 +system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 51.058094 +system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 35.397665 +system.ruby.Directory.miss_mach_latency_hist_seqr | 610 47.32% 47.32% | 633 49.11% 96.43% | 36 2.79% 99.22% | 1 0.08% 99.30% | 6 0.47% 99.77% | 2 0.16% 99.92% | 0 0.00% 99.92% | 1 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.Directory.miss_mach_latency_hist_seqr::total 1289 system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::bucket_size 1 system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::max_bucket 9 @@ -562,26 +570,26 @@ system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::total system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples 395 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 50.587342 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 45.603541 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 30.035585 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 336 85.06% 85.06% | 50 12.66% 97.72% | 8 2.03% 99.75% | 0 0.00% 99.75% | 0 0.00% 99.75% | 0 0.00% 99.75% | 1 0.25% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 54.334177 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 47.961199 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 33.663530 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 220 55.70% 55.70% | 163 41.27% 96.96% | 10 2.53% 99.49% | 0 0.00% 99.49% | 1 0.25% 99.75% | 1 0.25% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total 395 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size 32 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket 319 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::samples 179 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 59.865922 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 53.981018 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 34.573548 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 146 81.56% 81.56% | 26 14.53% 96.09% | 0 0.00% 96.09% | 4 2.23% 98.32% | 0 0.00% 98.32% | 1 0.56% 98.88% | 0 0.00% 98.88% | 1 0.56% 99.44% | 1 0.56% 100.00% +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 63.525140 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 56.666113 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 37.000656 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 61 34.08% 34.08% | 110 61.45% 95.53% | 6 3.35% 98.88% | 0 0.00% 98.88% | 1 0.56% 99.44% | 1 0.56% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total 179 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::samples 715 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 54.234965 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 48.531211 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 32.684395 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 600 83.92% 83.92% | 93 13.01% 96.92% | 16 2.24% 99.16% | 1 0.14% 99.30% | 3 0.42% 99.72% | 2 0.28% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 58.302098 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 51.492810 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 35.756740 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 329 46.01% 46.01% | 360 50.35% 96.36% | 20 2.80% 99.16% | 1 0.14% 99.30% | 4 0.56% 99.86% | 0 0.00% 99.86% | 0 0.00% 99.86% | 1 0.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::total 715 system.ruby.Directory_Controller.GETX 1289 0.00% 0.00% system.ruby.Directory_Controller.PUTX 1285 0.00% 0.00% diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini index 8fda1a50c..774234af5 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini @@ -179,7 +179,7 @@ useIndirect=true [system.cpu.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -552,7 +552,7 @@ pipelined=false [system.cpu.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -639,7 +639,7 @@ port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -756,6 +756,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -767,7 +768,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -775,29 +776,36 @@ width=16 master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -817,6 +825,7 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 @@ -826,7 +835,7 @@ p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 page_policy=open_adaptive power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 @@ -848,9 +857,9 @@ tRTW=2500 tWR=15000 tWTR=7500 tXAW=30000 -tXP=0 +tXP=6000 tXPDLL=0 -tXS=0 +tXS=270000 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout index 8cf3e8140..ce4c9483b 100755 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout @@ -3,12 +3,12 @@ Redirecting stderr to build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing/ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:35:23 -gem5 started Jul 21 2016 14:36:18 -gem5 executing on e108600-lin, pid 18560 +gem5 compiled Oct 11 2016 00:00:58 +gem5 started Oct 13 2016 21:09:20 +gem5 executing on e108600-lin, pid 17644 command line: /work/curdun01/gem5-external.hg/build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 21273500 because target called exit() +Exiting @ tick 22466500 because target called exit() diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt index 401e565b1..d0952668c 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt @@ -1,62 +1,62 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000021 # Number of seconds simulated -sim_ticks 21382500 # Number of ticks simulated -final_tick 21382500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000022 # Number of seconds simulated +sim_ticks 22466500 # Number of ticks simulated +final_tick 22466500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 21602 # Simulator instruction rate (inst/s) -host_op_rate 39134 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 85845466 # Simulator tick rate (ticks/s) -host_mem_usage 271116 # Number of bytes of host memory used -host_seconds 0.25 # Real time elapsed on the host +host_inst_rate 32079 # Simulator instruction rate (inst/s) +host_op_rate 58113 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 133941475 # Simulator tick rate (ticks/s) +host_mem_usage 269032 # Number of bytes of host memory used +host_seconds 0.17 # Real time elapsed on the host sim_insts 5380 # Number of instructions simulated sim_ops 9747 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 21382500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 17792 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 8896 # Number of bytes read from this memory -system.physmem.bytes_read::total 26688 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 17792 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 17792 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 278 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 139 # Number of read requests responded to by this memory -system.physmem.num_reads::total 417 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 832082310 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 416041155 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1248123465 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 832082310 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 832082310 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 832082310 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 416041155 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1248123465 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 417 # Number of read requests accepted +system.physmem.pwrStateResidencyTicks::UNDEFINED 22466500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 17728 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9024 # Number of bytes read from this memory +system.physmem.bytes_read::total 26752 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 17728 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 17728 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 277 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 141 # Number of read requests responded to by this memory +system.physmem.num_reads::total 418 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 789085972 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 401664701 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1190750673 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 789085972 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 789085972 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 789085972 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 401664701 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1190750673 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 418 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 417 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 418 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 26688 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 26752 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 26688 # Total read bytes from the system interface side +system.physmem.bytesReadSys 26752 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 31 # Per bank write bursts +system.physmem.perBankRdBursts::0 32 # Per bank write bursts system.physmem.perBankRdBursts::1 1 # Per bank write bursts system.physmem.perBankRdBursts::2 5 # Per bank write bursts system.physmem.perBankRdBursts::3 8 # Per bank write bursts -system.physmem.perBankRdBursts::4 51 # Per bank write bursts +system.physmem.perBankRdBursts::4 50 # Per bank write bursts system.physmem.perBankRdBursts::5 44 # Per bank write bursts system.physmem.perBankRdBursts::6 21 # Per bank write bursts system.physmem.perBankRdBursts::7 37 # Per bank write bursts -system.physmem.perBankRdBursts::8 23 # Per bank write bursts +system.physmem.perBankRdBursts::8 24 # Per bank write bursts system.physmem.perBankRdBursts::9 71 # Per bank write bursts system.physmem.perBankRdBursts::10 64 # Per bank write bursts system.physmem.perBankRdBursts::11 16 # Per bank write bursts system.physmem.perBankRdBursts::12 2 # Per bank write bursts -system.physmem.perBankRdBursts::13 19 # Per bank write bursts -system.physmem.perBankRdBursts::14 7 # Per bank write bursts +system.physmem.perBankRdBursts::13 20 # Per bank write bursts +system.physmem.perBankRdBursts::14 6 # Per bank write bursts system.physmem.perBankRdBursts::15 17 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts @@ -76,14 +76,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 21259500 # Total gap between requests +system.physmem.totGap 22337000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 417 # Read request sizes (log2) +system.physmem.readPktSize::6 418 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -91,11 +91,11 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 246 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 125 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 40 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 242 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 129 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 38 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 8 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -187,318 +187,328 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 97 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 248.742268 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 161.877699 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 262.561948 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 36 37.11% 37.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 27 27.84% 64.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 16 16.49% 81.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 4 4.12% 85.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2 2.06% 87.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 4 4.12% 91.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 2 2.06% 93.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1 1.03% 94.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 5 5.15% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 97 # Bytes accessed per row activation -system.physmem.totQLat 5040250 # Total ticks spent queuing -system.physmem.totMemAccLat 12859000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2085000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12086.93 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 95 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 246.568421 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 159.892164 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 259.040400 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 37 38.95% 38.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 23 24.21% 63.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 16 16.84% 80.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 6 6.32% 86.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2 2.11% 88.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 3 3.16% 91.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 2 2.11% 93.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2 2.11% 95.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 4 4.21% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 95 # Bytes accessed per row activation +system.physmem.totQLat 6803250 # Total ticks spent queuing +system.physmem.totMemAccLat 14640750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2090000 # Total ticks spent in databus transfers +system.physmem.avgQLat 16275.72 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30836.93 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1248.12 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 35025.72 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1190.75 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1248.12 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1190.75 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 9.75 # Data bus utilization in percentage -system.physmem.busUtilRead 9.75 # Data bus utilization in percentage for reads +system.physmem.busUtil 9.30 # Data bus utilization in percentage +system.physmem.busUtilRead 9.30 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.67 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.69 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 309 # Number of row buffer hits during reads +system.physmem.readRowHits 310 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 74.10 # Row buffer hit rate for reads +system.physmem.readRowHitRate 74.16 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 50982.01 # Average gap between requests -system.physmem.pageHitRate 74.10 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 173880 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 94875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 912600 # Energy for read commands per rank (pJ) +system.physmem.avgGap 53437.80 # Average gap between requests +system.physmem.pageHitRate 74.16 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 285600 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 125235 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1413720 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 10792665 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 32250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 13023390 # Total energy per rank (pJ) -system.physmem_0.averagePower 822.573188 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 13750 # Time in different power states +system.physmem_0.refreshEnergy 1229280.000000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 2399130 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 30240 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 7645980 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 138240 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 13267425 # Total energy per rank (pJ) +system.physmem_0.averagePower 590.516301 # Core power per rank (mW) +system.physmem_0.totalIdleTime 17035500 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 23500 # Time in different power states system.physmem_0.memoryStateTime::REF 520000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 15314750 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 415800 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 226875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1497600 # Energy for read commands per rank (pJ) +system.physmem_0.memoryStateTime::SREF 0 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 359250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 4794250 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 16769500 # Time in different power states +system.physmem_1.actEnergy 485520 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 235290 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1570800 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 10696050 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 117000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 13970445 # Total energy per rank (pJ) -system.physmem_1.averagePower 882.390336 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 103000 # Time in different power states +system.physmem_1.refreshEnergy 1229280.000000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 2963430 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 82560 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 7182000 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 1440 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 13750320 # Total energy per rank (pJ) +system.physmem_1.averagePower 612.009347 # Core power per rank (mW) +system.physmem_1.totalIdleTime 14672000 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 109000 # Time in different power states system.physmem_1.memoryStateTime::REF 520000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 15223250 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 21382500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 3511 # Number of BP lookups -system.cpu.branchPred.condPredicted 3511 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 567 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 2933 # Number of BTB lookups +system.physmem_1.memoryStateTime::SREF 0 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 3500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 6091750 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 15742250 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 22466500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 3488 # Number of BP lookups +system.cpu.branchPred.condPredicted 3488 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 571 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 2960 # Number of BTB lookups system.cpu.branchPred.BTBHits 0 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 414 # Number of times the RAS was used to get a target. +system.cpu.branchPred.usedRAS 360 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 94 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 2933 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 496 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 2437 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 406 # Number of mispredicted indirect branches. +system.cpu.branchPred.indirectLookups 2960 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 483 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 2477 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 410 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 21382500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 22466500 # Cumulative time (in ticks) in various power states system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 21382500 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 21382500 # Cumulative time (in ticks) in various power states +system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 22466500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 22466500 # Cumulative time (in ticks) in various power states system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 21382500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 42766 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 22466500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 44934 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 11494 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 15919 # Number of instructions fetch has processed -system.cpu.fetch.Branches 3511 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 910 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 9718 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1335 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 93 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.icacheStallCycles 12177 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 15717 # Number of instructions fetch has processed +system.cpu.fetch.Branches 3488 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 843 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 10477 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1321 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 78 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 1414 # Number of stall cycles due to pending traps system.cpu.fetch.PendingQuiesceStallCycles 15 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 30 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 2042 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 273 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 23431 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.223593 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.745730 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheWaitRetryStallCycles 15 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 2026 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 276 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 24836 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.141770 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.668775 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 19161 81.78% 81.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 166 0.71% 82.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 156 0.67% 83.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 235 1.00% 84.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 218 0.93% 85.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 215 0.92% 86.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 266 1.14% 87.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 168 0.72% 87.85% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 2846 12.15% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 20599 82.94% 82.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 175 0.70% 83.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 165 0.66% 84.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 225 0.91% 85.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 209 0.84% 86.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 222 0.89% 86.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 269 1.08% 88.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 159 0.64% 88.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 2813 11.33% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 23431 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.082098 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.372235 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 11586 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 7313 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 3407 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 458 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 667 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 26631 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 667 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 11849 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 2059 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 1032 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 3561 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 4263 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 25112 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 14 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 80 # Number of times rename has blocked due to IQ full -system.cpu.rename.SQFullEvents 4127 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 28145 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 61260 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 35084 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 24836 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.077625 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.349780 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 12221 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 8128 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 3370 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 457 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 660 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 26405 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 660 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 12481 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 1971 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 1213 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 3524 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 4987 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 24875 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 8 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 82 # Number of times rename has blocked due to IQ full +system.cpu.rename.SQFullEvents 4849 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 27762 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 60616 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 34638 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 4 # Number of floating rename lookups system.cpu.rename.CommittedMaps 11063 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 17082 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 24 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 24 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 1417 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2745 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1552 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 11 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 7 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 21890 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 22 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 18162 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 138 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 12165 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 16733 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 10 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 23431 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.775127 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.748484 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 16699 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 25 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 25 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 1436 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2622 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1598 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 10 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 11 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 21775 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 23 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 18112 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 144 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 12051 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 16553 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 11 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 24836 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.729264 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.710819 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 18255 77.91% 77.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1208 5.16% 83.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 874 3.73% 86.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 566 2.42% 89.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 836 3.57% 92.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 600 2.56% 95.34% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 613 2.62% 97.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 346 1.48% 99.43% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 133 0.57% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 19691 79.28% 79.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1200 4.83% 84.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 866 3.49% 87.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 575 2.32% 89.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 815 3.28% 93.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 575 2.32% 95.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 614 2.47% 97.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 364 1.47% 99.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 136 0.55% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 23431 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 24836 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 213 76.07% 76.07% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 76.07% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 76.07% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 76.07% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 76.07% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 76.07% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 76.07% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 76.07% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 76.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 76.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 76.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 76.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 76.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 76.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 76.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 76.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 76.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 76.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 76.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 76.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 76.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 76.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 76.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 76.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 76.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 76.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 76.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 76.07% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 76.07% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 51 18.21% 94.29% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 16 5.71% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 223 79.93% 79.93% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 79.93% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 79.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 79.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 79.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 79.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 79.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 79.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 79.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 79.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 79.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 79.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 79.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 79.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 79.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 79.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 79.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 79.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 79.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 79.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 79.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 79.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 79.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 79.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 79.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 79.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 79.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 79.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 79.93% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 41 14.70% 94.62% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 15 5.38% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 14483 79.74% 79.75% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 6 0.03% 79.79% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 7 0.04% 79.83% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 79.83% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 79.83% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 79.83% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 79.83% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 79.83% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 79.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 79.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 79.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 79.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 79.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 79.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 79.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 79.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 79.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 79.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 79.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 79.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 79.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 79.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 79.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 79.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 79.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 79.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 79.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 79.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 79.83% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2327 12.81% 92.64% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1337 7.36% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 14478 79.94% 79.95% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 6 0.03% 79.98% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 7 0.04% 80.02% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.02% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.02% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.02% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.02% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.02% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.02% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.02% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2258 12.47% 92.49% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1361 7.51% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 18162 # Type of FU issued -system.cpu.iq.rate 0.424683 # Inst issue rate -system.cpu.iq.fu_busy_cnt 280 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.015417 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 60165 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 34082 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 16453 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 18112 # Type of FU issued +system.cpu.iq.rate 0.403080 # Inst issue rate +system.cpu.iq.fu_busy_cnt 279 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.015404 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 61475 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 33854 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 16418 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 8 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 4 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 18436 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 18385 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 4 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 200 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 215 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1692 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 9 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.squashedLoads 1569 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 13 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 13 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 617 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 663 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 9 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 2 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 667 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1486 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 141 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 21912 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 9 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2745 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1552 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 22 # Number of dispatched non-speculative instructions +system.cpu.iew.iewSquashCycles 660 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1482 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 153 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 21798 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 34 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2622 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1598 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 23 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 140 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 152 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 13 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 120 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 685 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 805 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 17078 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2088 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1084 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 118 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 680 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 798 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 17038 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2047 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1074 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3333 # number of memory reference insts executed -system.cpu.iew.exec_branches 1727 # Number of branches executed -system.cpu.iew.exec_stores 1245 # Number of stores executed -system.cpu.iew.exec_rate 0.399336 # Inst execution rate -system.cpu.iew.wb_sent 16776 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 16457 # cumulative count of insts written-back -system.cpu.iew.wb_producers 11050 # num instructions producing a value -system.cpu.iew.wb_consumers 17247 # num instructions consuming a value -system.cpu.iew.wb_rate 0.384815 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.640691 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 12164 # The number of squashed insts skipped by commit +system.cpu.iew.exec_refs 3306 # number of memory reference insts executed +system.cpu.iew.exec_branches 1731 # Number of branches executed +system.cpu.iew.exec_stores 1259 # Number of stores executed +system.cpu.iew.exec_rate 0.379178 # Inst execution rate +system.cpu.iew.wb_sent 16737 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 16422 # cumulative count of insts written-back +system.cpu.iew.wb_producers 11019 # num instructions producing a value +system.cpu.iew.wb_consumers 17148 # num instructions consuming a value +system.cpu.iew.wb_rate 0.365469 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.642582 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 12050 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 12 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 655 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 21365 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.456213 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.347578 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 648 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 22793 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.427631 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.307645 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 18118 84.80% 84.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 989 4.63% 89.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 572 2.68% 92.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 729 3.41% 95.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 380 1.78% 97.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 132 0.62% 97.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 120 0.56% 98.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 73 0.34% 98.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 252 1.18% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 19538 85.72% 85.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1001 4.39% 90.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 566 2.48% 92.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 727 3.19% 95.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 384 1.68% 97.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 133 0.58% 98.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 124 0.54% 98.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 72 0.32% 98.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 248 1.09% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 21365 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 22793 # Number of insts commited each cycle system.cpu.commit.committedInsts 5380 # Number of instructions committed system.cpu.commit.committedOps 9747 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -544,94 +554,94 @@ system.cpu.commit.op_class_0::MemWrite 935 9.59% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 9747 # Class of committed instruction -system.cpu.commit.bw_lim_events 252 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 43024 # The number of ROB reads -system.cpu.rob.rob_writes 45919 # The number of ROB writes -system.cpu.timesIdled 159 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 19335 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 248 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 44342 # The number of ROB reads +system.cpu.rob.rob_writes 45672 # The number of ROB writes +system.cpu.timesIdled 156 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 20098 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5380 # Number of Instructions Simulated system.cpu.committedOps 9747 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 7.949071 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.949071 # CPI: Total CPI of All Threads -system.cpu.ipc 0.125801 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.125801 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 21733 # number of integer regfile reads -system.cpu.int_regfile_writes 13291 # number of integer regfile writes +system.cpu.cpi 8.352045 # CPI: Cycles Per Instruction +system.cpu.cpi_total 8.352045 # CPI: Total CPI of All Threads +system.cpu.ipc 0.119731 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.119731 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 21663 # number of integer regfile reads +system.cpu.int_regfile_writes 13219 # number of integer regfile writes system.cpu.fp_regfile_reads 4 # number of floating regfile reads -system.cpu.cc_regfile_reads 8307 # number of cc regfile reads -system.cpu.cc_regfile_writes 5092 # number of cc regfile writes -system.cpu.misc_regfile_reads 7667 # number of misc regfile reads +system.cpu.cc_regfile_reads 8286 # number of cc regfile reads +system.cpu.cc_regfile_writes 5066 # number of cc regfile writes +system.cpu.misc_regfile_reads 7640 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 21382500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 22466500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 81.328051 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2579 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 139 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 18.553957 # Average number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 81.537714 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2520 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 141 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 17.872340 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 81.328051 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.019855 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.019855 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 139 # Occupied blocks per task id +system.cpu.dcache.tags.occ_blocks::cpu.data 81.537714 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.019907 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.019907 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 92 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.033936 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 5679 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 5679 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 21382500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 1719 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1719 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 860 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 860 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2579 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2579 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2579 # number of overall hits -system.cpu.dcache.overall_hits::total 2579 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 116 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 116 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 75 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 75 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 191 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 191 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 191 # number of overall misses -system.cpu.dcache.overall_misses::total 191 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 9465500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 9465500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 6317000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 6317000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 15782500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 15782500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 15782500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 15782500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1835 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1835 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.age_task_id_blocks_1024::1 94 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.034424 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 5567 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 5567 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 22466500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 1661 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1661 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 859 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 859 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 2520 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2520 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2520 # number of overall hits +system.cpu.dcache.overall_hits::total 2520 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 117 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 117 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 76 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 76 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 193 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 193 # number of demand (read+write) misses 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+system.cpu.dcache.ReadReq_accesses::total 1778 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 935 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 935 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2770 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2770 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2770 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2770 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.063215 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.063215 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.080214 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.080214 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.068953 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.068953 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.068953 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.068953 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 81599.137931 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 81599.137931 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 84226.666667 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 84226.666667 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 82630.890052 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 82630.890052 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 82630.890052 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 82630.890052 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 124 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 2713 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2713 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2713 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2713 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.065804 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.065804 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.081283 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.081283 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.071139 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.071139 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.071139 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.071139 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 87401.709402 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 87401.709402 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 93032.894737 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 93032.894737 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 89619.170984 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 89619.170984 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 89619.170984 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 89619.170984 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 132 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 41.333333 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 44 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.ReadReq_mshr_hits::cpu.data 52 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 52 # number of ReadReq MSHR hits @@ -639,96 +649,96 @@ system.cpu.dcache.demand_mshr_hits::cpu.data 52 system.cpu.dcache.demand_mshr_hits::total 52 # number of demand (read+write) MSHR hits system.cpu.dcache.overall_mshr_hits::cpu.data 52 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::total 52 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 64 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 64 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 75 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 75 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 139 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 139 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 139 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 139 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5739000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5739000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6242000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 6242000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11981000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 11981000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11981000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 11981000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.034877 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.034877 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.080214 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.080214 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.050181 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.050181 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.050181 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.050181 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 89671.875000 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 89671.875000 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 83226.666667 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 83226.666667 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 86194.244604 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 86194.244604 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 86194.244604 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 86194.244604 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 21382500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 65 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 65 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 76 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 141 # number of demand (read+write) MSHR misses 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-system.cpu.icache.tags.total_refs 1656 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 279 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 5.935484 # Average number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 130.260906 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1641 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 278 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 5.902878 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 130.610950 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.063775 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.063775 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 279 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 148 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.136230 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 4363 # Number of tag accesses -system.cpu.icache.tags.data_accesses 4363 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 21382500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 1656 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1656 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1656 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1656 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1656 # number of overall hits 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cycles -system.cpu.icache.overall_miss_latency::total 29282500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2042 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2042 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2042 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2042 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2042 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2042 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.189030 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.189030 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.189030 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.189030 # miss rate for demand accesses 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percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.063604 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 278 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 140 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 138 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.135742 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 4330 # Number of tag accesses +system.cpu.icache.tags.data_accesses 4330 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 22466500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 1641 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1641 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1641 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1641 # 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number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 19629000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 19629000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5002000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5002000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19629000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10381000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 30010000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19629000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10381000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 30010000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 76 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 76 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 277 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 277 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 65 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 65 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 277 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 141 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 418 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 277 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 418 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6120500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6120500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 20007500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 20007500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5700000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5700000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 20007500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11820500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 31828000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 20007500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11820500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 31828000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.996416 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.996416 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.996403 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.996403 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996416 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996403 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.997608 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996416 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.997613 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996403 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.997608 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71720 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71720 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70607.913669 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70607.913669 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 78156.250000 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 78156.250000 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70607.913669 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 74683.453237 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71966.426859 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70607.913669 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 74683.453237 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71966.426859 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 418 # Total number of requests made to the snoop filter. +system.cpu.l2cache.overall_mshr_miss_rate::total 0.997613 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80532.894737 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80532.894737 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72229.241877 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72229.241877 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 87692.307692 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 87692.307692 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72229.241877 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 83833.333333 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 76143.540670 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72229.241877 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 83833.333333 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 76143.540670 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 419 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 21382500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 22466500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 343 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 75 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 75 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 279 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 64 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 558 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 278 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 836 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17856 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8896 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 26752 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadExReq 76 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 76 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 278 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 65 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 556 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 282 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 838 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17792 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9024 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 26816 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 418 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.002392 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.048912 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 419 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.002387 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.048853 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 417 99.76% 99.76% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 418 99.76% 99.76% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 1 0.24% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 418 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 209000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 418500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 208500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 417 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_fanout::total 419 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 209500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 417000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 1.9 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 211500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) +system.membus.snoop_filter.tot_requests 418 # Total number of requests made to the snoop filter. system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 21382500 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 22466500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 342 # Transaction distribution -system.membus.trans_dist::ReadExReq 75 # Transaction distribution -system.membus.trans_dist::ReadExResp 75 # Transaction distribution +system.membus.trans_dist::ReadExReq 76 # Transaction distribution +system.membus.trans_dist::ReadExResp 76 # Transaction distribution system.membus.trans_dist::ReadSharedReq 342 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 834 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 834 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 834 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26688 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 26688 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 26688 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 836 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 836 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 836 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26752 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 26752 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 26752 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 417 # Request fanout histogram +system.membus.snoop_fanout::samples 418 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 417 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 418 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 417 # Request fanout histogram -system.membus.reqLayer0.occupancy 503500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 2228500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 10.4 # Layer utilization (%) +system.membus.snoop_fanout::total 418 # Request fanout histogram +system.membus.reqLayer0.occupancy 506000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.3 # Layer utilization (%) +system.membus.respLayer1.occupancy 2231250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 9.9 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini index f585dbbc0..49adea038 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini @@ -14,6 +14,7 @@ children=clk_domain cpu dvfs_handler mem_ctrls ruby sys_port_proxy voltage_domai boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 exit_on_work_items=false init_param=0 @@ -22,11 +23,15 @@ kernel_addr_check=true load_addr_mask=1099511627775 load_offset=0 mem_mode=timing -mem_ranges=0:268435455 +mem_ranges=0:268435455:0:0:0:0 memories=system.mem_ctrls mmap_using_noreserve=false multi_thread=false num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null readfile= symbolfile= thermal_components= @@ -55,6 +60,7 @@ branchPred=Null checker=Null clk_domain=system.cpu.clk_domain cpu_id=0 +default_p_state=UNDEFINED do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true @@ -70,6 +76,10 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null profile=0 progress_interval=0 simpoint_start_insts= @@ -105,18 +115,28 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=X86PagetableWalker clk_domain=system.cpu.clk_domain +default_p_state=UNDEFINED eventq_index=0 num_squash_per_cycle=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null system=system port=system.ruby.l1_cntrl0.sequencer.slave[3] [system.cpu.interrupts] type=X86LocalApic clk_domain=system.cpu.apic_clk_domain +default_p_state=UNDEFINED eventq_index=0 int_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 pio_addr=2305843009213693952 pio_latency=100 +power_model=Null system=system int_master=system.ruby.l1_cntrl0.sequencer.slave[4] int_slave=system.ruby.l1_cntrl0.sequencer.master[1] @@ -136,8 +156,13 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=X86PagetableWalker clk_domain=system.cpu.clk_domain +default_p_state=UNDEFINED eventq_index=0 num_squash_per_cycle=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null system=system port=system.ruby.l1_cntrl0.sequencer.slave[2] @@ -155,7 +180,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/dist/m5/regression/test-progs/hello/bin/x86/linux/hello +executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/x86/linux/hello gid=100 input=cin kvmInSE=false @@ -178,27 +203,27 @@ transition_latency=100000 [system.mem_ctrls] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -210,6 +235,7 @@ burst_length=8 channels=1 clk_domain=system.clk_domain conf_table_reported=true +default_p_state=UNDEFINED device_bus_width=8 device_rowbuffer_size=1024 device_size=536870912 @@ -217,12 +243,17 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 page_policy=open_adaptive -range=0:268435455 +power_model=Null +range=0:268435455:5:19:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10 @@ -244,9 +275,9 @@ tRTW=3 tWR=15 tWTR=8 tXAW=30 -tXP=0 +tXP=6 tXPDLL=0 -tXS=0 +tXS=270 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 @@ -260,12 +291,17 @@ access_backing_store=false all_instructions=false block_size_bytes=64 clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED eventq_index=0 hot_lines=false memory_size_bits=48 num_of_sequencers=1 number_of_virtual_networks=5 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 phys_mem=Null +power_model=Null randomization=false [system.ruby.clk_domain] @@ -282,6 +318,7 @@ children=directory dmaRequestToDir dmaResponseFromDir forwardFromDir requestToDi buffer_size=0 clk_domain=system.ruby.clk_domain cluster_id=0 +default_p_state=UNDEFINED directory=system.ruby.dir_cntrl0.directory directory_latency=12 dmaRequestToDir=system.ruby.dir_cntrl0.dmaRequestToDir @@ -289,6 +326,10 @@ dmaResponseFromDir=system.ruby.dir_cntrl0.dmaResponseFromDir eventq_index=0 forwardFromDir=system.ruby.dir_cntrl0.forwardFromDir number_of_TBEs=256 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null recycle_latency=10 requestToDir=system.ruby.dir_cntrl0.requestToDir responseFromDir=system.ruby.dir_cntrl0.responseFromDir @@ -362,11 +403,16 @@ cacheMemory=system.ruby.l1_cntrl0.cacheMemory cache_response_latency=12 clk_domain=system.cpu.clk_domain cluster_id=0 +default_p_state=UNDEFINED eventq_index=0 forwardToCache=system.ruby.l1_cntrl0.forwardToCache issue_latency=2 mandatoryQueue=system.ruby.l1_cntrl0.mandatoryQueue number_of_TBEs=256 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null recycle_latency=10 requestFromCache=system.ruby.l1_cntrl0.requestFromCache responseFromCache=system.ruby.l1_cntrl0.responseFromCache @@ -448,17 +494,22 @@ coreid=99 dcache=system.ruby.l1_cntrl0.cacheMemory dcache_hit_latency=1 deadlock_threshold=500000 +default_p_state=UNDEFINED eventq_index=0 +garnet_standalone=false icache=system.ruby.l1_cntrl0.cacheMemory icache_hit_latency=1 is_cpu_sequencer=true max_outstanding_requests=16 no_retry_on_stall=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null ruby_system=system.ruby support_data_reqs=true support_inst_reqs=true system=system -using_network_tester=false using_ruby_tester=false version=0 master=system.cpu.interrupts.pio system.cpu.interrupts.int_slave @@ -472,18 +523,23 @@ eventq_index=0 [system.ruby.network] type=SimpleNetwork -children=ext_links0 ext_links1 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_links0 int_links1 routers0 routers1 routers2 +children=ext_links0 ext_links1 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_link_buffers20 int_link_buffers21 int_link_buffers22 int_link_buffers23 int_link_buffers24 int_link_buffers25 int_link_buffers26 int_link_buffers27 int_link_buffers28 int_link_buffers29 int_link_buffers30 int_link_buffers31 int_link_buffers32 int_link_buffers33 int_link_buffers34 int_link_buffers35 int_link_buffers36 int_link_buffers37 int_link_buffers38 int_link_buffers39 int_links0 int_links1 int_links2 int_links3 routers0 routers1 routers2 adaptive_routing=false buffer_size=0 clk_domain=system.ruby.clk_domain control_msg_size=8 +default_p_state=UNDEFINED endpoint_bandwidth=1000 eventq_index=0 ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1 -int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19 -int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 +int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19 system.ruby.network.int_link_buffers20 system.ruby.network.int_link_buffers21 system.ruby.network.int_link_buffers22 system.ruby.network.int_link_buffers23 system.ruby.network.int_link_buffers24 system.ruby.network.int_link_buffers25 system.ruby.network.int_link_buffers26 system.ruby.network.int_link_buffers27 system.ruby.network.int_link_buffers28 system.ruby.network.int_link_buffers29 system.ruby.network.int_link_buffers30 system.ruby.network.int_link_buffers31 system.ruby.network.int_link_buffers32 system.ruby.network.int_link_buffers33 system.ruby.network.int_link_buffers34 system.ruby.network.int_link_buffers35 system.ruby.network.int_link_buffers36 system.ruby.network.int_link_buffers37 system.ruby.network.int_link_buffers38 system.ruby.network.int_link_buffers39 +int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2 system.ruby.network.int_links3 netifs= number_of_virtual_networks=5 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null routers=system.ruby.network.routers0 system.ruby.network.routers1 system.ruby.network.routers2 ruby_system=system.ruby topology=Crossbar @@ -650,32 +706,206 @@ eventq_index=0 ordered=true randomization=false +[system.ruby.network.int_link_buffers20] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers21] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers22] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers23] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers24] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers25] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers26] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers27] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers28] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers29] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers30] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers31] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers32] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers33] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers34] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers35] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers36] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers37] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers38] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers39] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + [system.ruby.network.int_links0] type=SimpleIntLink bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers2 eventq_index=0 latency=1 link_id=2 -node_a=system.ruby.network.routers0 -node_b=system.ruby.network.routers2 +src_node=system.ruby.network.routers0 +src_outport= weight=1 [system.ruby.network.int_links1] type=SimpleIntLink bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers2 eventq_index=0 latency=1 link_id=3 -node_a=system.ruby.network.routers1 -node_b=system.ruby.network.routers2 +src_node=system.ruby.network.routers1 +src_outport= +weight=1 + +[system.ruby.network.int_links2] +type=SimpleIntLink +bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers0 +eventq_index=0 +latency=1 +link_id=4 +src_node=system.ruby.network.routers2 +src_outport= +weight=1 + +[system.ruby.network.int_links3] +type=SimpleIntLink +bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers1 +eventq_index=0 +latency=1 +link_id=5 +src_node=system.ruby.network.routers2 +src_outport= weight=1 [system.ruby.network.routers0] type=Switch children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED eventq_index=0 +latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 port_buffers=system.ruby.network.routers0.port_buffers00 system.ruby.network.routers0.port_buffers01 system.ruby.network.routers0.port_buffers02 system.ruby.network.routers0.port_buffers03 system.ruby.network.routers0.port_buffers04 system.ruby.network.routers0.port_buffers05 system.ruby.network.routers0.port_buffers06 system.ruby.network.routers0.port_buffers07 system.ruby.network.routers0.port_buffers08 system.ruby.network.routers0.port_buffers09 system.ruby.network.routers0.port_buffers10 system.ruby.network.routers0.port_buffers11 system.ruby.network.routers0.port_buffers12 system.ruby.network.routers0.port_buffers13 system.ruby.network.routers0.port_buffers14 +power_model=Null router_id=0 virt_nets=5 @@ -788,8 +1018,14 @@ randomization=false type=Switch children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED eventq_index=0 +latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 port_buffers=system.ruby.network.routers1.port_buffers00 system.ruby.network.routers1.port_buffers01 system.ruby.network.routers1.port_buffers02 system.ruby.network.routers1.port_buffers03 system.ruby.network.routers1.port_buffers04 system.ruby.network.routers1.port_buffers05 system.ruby.network.routers1.port_buffers06 system.ruby.network.routers1.port_buffers07 system.ruby.network.routers1.port_buffers08 system.ruby.network.routers1.port_buffers09 system.ruby.network.routers1.port_buffers10 system.ruby.network.routers1.port_buffers11 system.ruby.network.routers1.port_buffers12 system.ruby.network.routers1.port_buffers13 system.ruby.network.routers1.port_buffers14 +power_model=Null router_id=1 virt_nets=5 @@ -902,8 +1138,14 @@ randomization=false type=Switch children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17 port_buffers18 port_buffers19 clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED eventq_index=0 +latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 port_buffers=system.ruby.network.routers2.port_buffers00 system.ruby.network.routers2.port_buffers01 system.ruby.network.routers2.port_buffers02 system.ruby.network.routers2.port_buffers03 system.ruby.network.routers2.port_buffers04 system.ruby.network.routers2.port_buffers05 system.ruby.network.routers2.port_buffers06 system.ruby.network.routers2.port_buffers07 system.ruby.network.routers2.port_buffers08 system.ruby.network.routers2.port_buffers09 system.ruby.network.routers2.port_buffers10 system.ruby.network.routers2.port_buffers11 system.ruby.network.routers2.port_buffers12 system.ruby.network.routers2.port_buffers13 system.ruby.network.routers2.port_buffers14 system.ruby.network.routers2.port_buffers15 system.ruby.network.routers2.port_buffers16 system.ruby.network.routers2.port_buffers17 system.ruby.network.routers2.port_buffers18 system.ruby.network.routers2.port_buffers19 +power_model=Null router_id=2 virt_nets=5 @@ -1050,9 +1292,14 @@ randomization=false [system.sys_port_proxy] type=RubyPortProxy clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 is_cpu_sequencer=true no_retry_on_stall=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null ruby_system=system.ruby support_data_reqs=true support_inst_reqs=true diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simerr b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simerr index ccfdd3697..f6f6f15a5 100755 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simerr +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simerr @@ -4,8 +4,7 @@ warn: rounding error > tolerance 1.250000 rounded to 1 warn: rounding error > tolerance 1.250000 rounded to 1 -warn: rounding error > tolerance - 1.250000 rounded to 1 warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes) warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files! diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simout b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simout index 944308c19..60c5b94b3 100755 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simout +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simout @@ -1,12 +1,14 @@ +Redirecting stdout to build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing-ruby/simout +Redirecting stderr to build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing-ruby/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 21 2016 14:41:03 -gem5 started Jan 21 2016 14:41:52 -gem5 executing on zizzer, pid 17892 -command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing-ruby -re /z/atgutier/gem5/gem5-commit/tests/run.py build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing-ruby +gem5 compiled Oct 11 2016 00:00:58 +gem5 started Oct 13 2016 21:09:01 +gem5 executing on e108600-lin, pid 17636 +command line: /work/curdun01/gem5-external.hg/build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing-ruby -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/x86/linux/simple-timing-ruby Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 87948 because target called exit() +Exiting @ tick 91859 because target called exit() diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt index 5369fe205..61c4aeeab 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000088 # Number of seconds simulated -sim_ticks 87948 # Number of ticks simulated -final_tick 87948 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000092 # Number of seconds simulated +sim_ticks 91859 # Number of ticks simulated +final_tick 91859 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 83700 # Simulator instruction rate (inst/s) -host_op_rate 151608 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1367648 # Simulator tick rate (ticks/s) -host_mem_usage 473696 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host +host_inst_rate 42401 # Simulator instruction rate (inst/s) +host_op_rate 76797 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 723555 # Simulator tick rate (ticks/s) +host_mem_usage 431840 # Number of bytes of host memory used +host_seconds 0.13 # Real time elapsed on the host sim_insts 5381 # Number of instructions simulated sim_ops 9748 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks -system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 87948 # Cumulative time (in ticks) in various power states +system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 91859 # Cumulative time (in ticks) in various power states system.mem_ctrls.bytes_read::ruby.dir_cntrl0 88128 # Number of bytes read from this memory system.mem_ctrls.bytes_read::total 88128 # Number of bytes read from this memory system.mem_ctrls.bytes_written::ruby.dir_cntrl0 87872 # Number of bytes written to this memory @@ -22,59 +22,59 @@ system.mem_ctrls.num_reads::ruby.dir_cntrl0 1377 # system.mem_ctrls.num_reads::total 1377 # Number of read requests responded to by this memory system.mem_ctrls.num_writes::ruby.dir_cntrl0 1373 # Number of write requests responded to by this memory system.mem_ctrls.num_writes::total 1373 # Number of write requests responded to by this memory -system.mem_ctrls.bw_read::ruby.dir_cntrl0 1002046664 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_read::total 1002046664 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::ruby.dir_cntrl0 999135853 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::total 999135853 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_total::ruby.dir_cntrl0 2001182517 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.bw_total::total 2001182517 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_read::ruby.dir_cntrl0 959383403 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 959383403 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::ruby.dir_cntrl0 956596523 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::total 956596523 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::ruby.dir_cntrl0 1915979926 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 1915979926 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrls.readReqs 1377 # Number of read requests accepted system.mem_ctrls.writeReqs 1373 # Number of write requests accepted system.mem_ctrls.readBursts 1377 # Number of DRAM read bursts, including those serviced by the write queue system.mem_ctrls.writeBursts 1373 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrls.bytesReadDRAM 40320 # Total number of bytes read from DRAM -system.mem_ctrls.bytesReadWrQ 47808 # Total number of bytes read from write queue -system.mem_ctrls.bytesWritten 39936 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadDRAM 41408 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 46720 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 41728 # Total number of bytes written to DRAM system.mem_ctrls.bytesReadSys 88128 # Total read bytes from the system interface side system.mem_ctrls.bytesWrittenSys 87872 # Total written bytes from the system interface side -system.mem_ctrls.servicedByWrQ 747 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrls.mergedWrBursts 722 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.servicedByWrQ 730 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 702 # Number of DRAM write bursts merged with an existing one system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.mem_ctrls.perBankRdBursts::0 59 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::1 1 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::0 60 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 2 # Per bank write bursts system.mem_ctrls.perBankRdBursts::2 6 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::3 9 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::4 52 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::5 55 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::6 37 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::7 64 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::8 25 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::9 119 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::10 121 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::11 21 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 10 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 51 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 53 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 39 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 57 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::8 28 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::9 129 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 115 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 24 # Per bank write bursts system.mem_ctrls.perBankRdBursts::12 2 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::13 21 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 28 # Per bank write bursts system.mem_ctrls.perBankRdBursts::14 8 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::15 30 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::0 51 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::1 1 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::15 35 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 55 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 2 # Per bank write bursts system.mem_ctrls.perBankWrBursts::2 6 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::3 7 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 8 # Per bank write bursts system.mem_ctrls.perBankWrBursts::4 52 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::5 50 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::6 36 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::7 66 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::8 25 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::9 120 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::10 125 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::11 23 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 48 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 38 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 60 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::8 28 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::9 130 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 123 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::11 24 # Per bank write bursts system.mem_ctrls.perBankWrBursts::12 2 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::13 21 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 31 # Per bank write bursts system.mem_ctrls.perBankWrBursts::14 8 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::15 31 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::15 37 # Per bank write bursts system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrls.totGap 87868 # Total gap between requests +system.mem_ctrls.totGap 91773 # Total gap between requests system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) @@ -89,7 +89,7 @@ system.mem_ctrls.writePktSize::3 0 # Wr system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::6 1373 # Write request sizes (log2) -system.mem_ctrls.rdQLenPdf::0 630 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::0 647 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see @@ -137,23 +137,23 @@ system.mem_ctrls.wrQLenPdf::12 1 # Wh system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::15 6 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::16 8 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::17 41 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::18 40 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::19 39 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::20 40 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::21 39 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::22 39 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::23 39 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::24 39 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::25 39 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::26 39 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::27 38 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::28 38 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::29 38 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::30 38 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::31 38 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::32 38 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 6 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 33 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 42 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 42 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 43 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 44 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 40 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 40 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::24 40 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 40 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 40 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 40 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::28 40 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 40 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 40 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 40 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::32 40 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see @@ -185,98 +185,108 @@ system.mem_ctrls.wrQLenPdf::60 0 # Wh system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrls.bytesPerActivate::samples 271 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::mean 293.313653 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::gmean 193.377642 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::stdev 283.497497 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::0-127 72 26.57% 26.57% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::128-255 83 30.63% 57.20% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::256-383 37 13.65% 70.85% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::384-511 23 8.49% 79.34% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::512-639 21 7.75% 87.08% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::640-767 5 1.85% 88.93% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::768-895 7 2.58% 91.51% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::896-1023 3 1.11% 92.62% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::1024-1151 20 7.38% 100.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::total 271 # Bytes accessed per row activation -system.mem_ctrls.rdPerTurnAround::samples 38 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::mean 16.289474 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::gmean 16.048466 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::stdev 3.463383 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::12-13 1 2.63% 2.63% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::14-15 15 39.47% 42.11% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::16-17 16 42.11% 84.21% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::18-19 4 10.53% 94.74% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::20-21 1 2.63% 97.37% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::34-35 1 2.63% 100.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::total 38 # Reads before turning the bus around for writes -system.mem_ctrls.wrPerTurnAround::samples 38 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::mean 16.421053 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::gmean 16.397539 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::stdev 0.919212 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::16 31 81.58% 81.58% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::18 5 13.16% 94.74% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::19 2 5.26% 100.00% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::total 38 # Writes before turning the bus around for reads -system.mem_ctrls.totQLat 9303 # Total ticks spent queuing -system.mem_ctrls.totMemAccLat 21273 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrls.totBusLat 3150 # Total ticks spent in databus transfers -system.mem_ctrls.avgQLat 14.77 # Average queueing delay per DRAM burst +system.mem_ctrls.bytesPerActivate::samples 263 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 304.669202 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 201.653389 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 284.735596 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 72 27.38% 27.38% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 68 25.86% 53.23% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 44 16.73% 69.96% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 29 11.03% 80.99% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 12 4.56% 85.55% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 9 3.42% 88.97% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 6 2.28% 91.25% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 3 1.14% 92.40% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 20 7.60% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 263 # Bytes accessed per row activation +system.mem_ctrls.rdPerTurnAround::samples 40 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::mean 16.100000 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::gmean 15.846587 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::stdev 3.484765 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::12-13 3 7.50% 7.50% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::14-15 12 30.00% 37.50% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::16-17 19 47.50% 85.00% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::18-19 4 10.00% 95.00% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::20-21 1 2.50% 97.50% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::34-35 1 2.50% 100.00% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::total 40 # Reads before turning the bus around for writes +system.mem_ctrls.wrPerTurnAround::samples 40 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::mean 16.300000 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::gmean 16.281263 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::stdev 0.822753 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::16 35 87.50% 87.50% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::18 3 7.50% 95.00% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::19 2 5.00% 100.00% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::total 40 # Writes before turning the bus around for reads +system.mem_ctrls.totQLat 12721 # Total ticks spent queuing +system.mem_ctrls.totMemAccLat 25014 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.totBusLat 3235 # Total ticks spent in databus transfers +system.mem_ctrls.avgQLat 19.66 # Average queueing delay per DRAM burst system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst -system.mem_ctrls.avgMemAccLat 33.77 # Average memory access latency per DRAM burst -system.mem_ctrls.avgRdBW 458.45 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrls.avgWrBW 454.09 # Average achieved write bandwidth in MiByte/s -system.mem_ctrls.avgRdBWSys 1002.05 # Average system read bandwidth in MiByte/s -system.mem_ctrls.avgWrBWSys 999.14 # Average system write bandwidth in MiByte/s +system.mem_ctrls.avgMemAccLat 38.66 # Average memory access latency per DRAM burst +system.mem_ctrls.avgRdBW 450.78 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 454.26 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 959.38 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 956.60 # Average system write bandwidth in MiByte/s system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrls.busUtil 7.13 # Data bus utilization in percentage -system.mem_ctrls.busUtilRead 3.58 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtil 7.07 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 3.52 # Data bus utilization in percentage for reads system.mem_ctrls.busUtilWrite 3.55 # Data bus utilization in percentage for writes system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing -system.mem_ctrls.avgWrQLen 25.04 # Average write queue length when enqueuing -system.mem_ctrls.readRowHits 420 # Number of row buffer hits during reads -system.mem_ctrls.writeRowHits 556 # Number of row buffer hits during writes -system.mem_ctrls.readRowHitRate 66.67 # Row buffer hit rate for reads -system.mem_ctrls.writeRowHitRate 85.41 # Row buffer hit rate for writes -system.mem_ctrls.avgGap 31.95 # Average gap between requests -system.mem_ctrls.pageHitRate 76.19 # Row buffer hit rate, read and write combined -system.mem_ctrls_0.actEnergy 657720 # Energy for activate commands per rank (pJ) -system.mem_ctrls_0.preEnergy 365400 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_0.readEnergy 3407040 # Energy for read commands per rank (pJ) -system.mem_ctrls_0.writeEnergy 2623104 # Energy for write commands per rank (pJ) -system.mem_ctrls_0.refreshEnergy 5594160 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_0.actBackEnergy 51093432 # Energy for active background per rank (pJ) -system.mem_ctrls_0.preBackEnergy 6724800 # Energy for precharge background per rank (pJ) -system.mem_ctrls_0.totalEnergy 70465656 # Total energy per rank (pJ) -system.mem_ctrls_0.averagePower 820.264661 # Core power per rank (mW) -system.mem_ctrls_0.memoryStateTime::IDLE 10886 # Time in different power states -system.mem_ctrls_0.memoryStateTime::REF 2860 # Time in different power states -system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT 72174 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrls_1.actEnergy 1368360 # Energy for activate commands per rank (pJ) -system.mem_ctrls_1.preEnergy 760200 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_1.readEnergy 4268160 # Energy for read commands per rank (pJ) -system.mem_ctrls_1.writeEnergy 3680640 # Energy for write commands per rank (pJ) -system.mem_ctrls_1.refreshEnergy 5594160 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_1.actBackEnergy 54919728 # Energy for active background per rank (pJ) -system.mem_ctrls_1.preBackEnergy 3368400 # Energy for precharge background per rank (pJ) -system.mem_ctrls_1.totalEnergy 73959648 # Total energy per rank (pJ) -system.mem_ctrls_1.averagePower 860.936931 # Core power per rank (mW) -system.mem_ctrls_1.memoryStateTime::IDLE 5575 # Time in different power states -system.mem_ctrls_1.memoryStateTime::REF 2860 # Time in different power states -system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT 77782 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 87948 # Cumulative time (in ticks) in various power states +system.mem_ctrls.avgWrQLen 25.84 # Average write queue length when enqueuing +system.mem_ctrls.readRowHits 435 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 591 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 67.23 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate 88.08 # Row buffer hit rate for writes +system.mem_ctrls.avgGap 33.37 # Average gap between requests +system.mem_ctrls.pageHitRate 77.85 # Row buffer hit rate, read and write combined +system.mem_ctrls_0.actEnergy 664020 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 340032 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 3175872 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 2246688 # Energy for write commands per rank (pJ) +system.mem_ctrls_0.refreshEnergy 7375680.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 10273224 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 269568 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.actPowerDownEnergy 25208136 # Energy for active power-down per rank (pJ) +system.mem_ctrls_0.prePowerDownEnergy 4818816 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls_0.selfRefreshEnergy 743760.000000 # Energy for self refresh per rank (pJ) +system.mem_ctrls_0.totalEnergy 55115796 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 600.004311 # Core power per rank (mW) +system.mem_ctrls_0.totalIdleTime 68393 # Total Idle time Per DRAM Rank +system.mem_ctrls_0.memoryStateTime::IDLE 346 # Time in different power states +system.mem_ctrls_0.memoryStateTime::REF 3126 # Time in different power states +system.mem_ctrls_0.memoryStateTime::SREF 798 # Time in different power states +system.mem_ctrls_0.memoryStateTime::PRE_PDN 12549 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 19759 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT_PDN 55281 # Time in different power states +system.mem_ctrls_1.actEnergy 1285200 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 676200 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 4215456 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 3198816 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.refreshEnergy 6761040.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 9576912 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 183552 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.actPowerDownEnergy 28147512 # Energy for active power-down per rank (pJ) +system.mem_ctrls_1.prePowerDownEnergy 3322368 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls_1.totalEnergy 57367056 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 624.512089 # Core power per rank (mW) +system.mem_ctrls_1.totalIdleTime 70328 # Total Idle time Per DRAM Rank +system.mem_ctrls_1.memoryStateTime::IDLE 150 # Time in different power states +system.mem_ctrls_1.memoryStateTime::REF 2866 # Time in different power states +system.mem_ctrls_1.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls_1.memoryStateTime::PRE_PDN 8652 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 18464 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT_PDN 61727 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 91859 # Cumulative time (in ticks) in various power states system.cpu.clk_domain.clock 1 # Clock period in ticks -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 87948 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 91859 # Cumulative time (in ticks) in various power states system.cpu.apic_clk_domain.clock 16 # Clock period in ticks -system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 87948 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 87948 # Cumulative time (in ticks) in various power states +system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 91859 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 91859 # Cumulative time (in ticks) in various power states system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 87948 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 87948 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 91859 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 91859 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 5381 # Number of instructions committed @@ -297,7 +307,7 @@ system.cpu.num_mem_refs 1988 # nu system.cpu.num_load_insts 1053 # Number of load instructions system.cpu.num_store_insts 935 # Number of store instructions system.cpu.num_idle_cycles 0.999989 # Number of idle cycles -system.cpu.num_busy_cycles 87947.000011 # Number of busy cycles +system.cpu.num_busy_cycles 91858.000011 # Number of busy cycles system.cpu.not_idle_fraction 0.999989 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000011 # Percentage of idle cycles system.cpu.Branches 1208 # Number of branches fetched @@ -337,7 +347,7 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 9748 # Class of executed instruction system.ruby.clk_domain.clock 1 # Clock period in ticks -system.ruby.pwrStateResidencyTicks::UNDEFINED 87948 # Cumulative time (in ticks) in various power states +system.ruby.pwrStateResidencyTicks::UNDEFINED 91859 # Cumulative time (in ticks) in various power states system.ruby.delayHist::bucket_size 1 # delay histogram for all message system.ruby.delayHist::max_bucket 9 # delay histogram for all message system.ruby.delayHist::samples 2750 # delay histogram for all message @@ -353,10 +363,10 @@ system.ruby.outstanding_req_hist_seqr::total 8852 system.ruby.latency_hist_seqr::bucket_size 64 system.ruby.latency_hist_seqr::max_bucket 639 system.ruby.latency_hist_seqr::samples 8852 -system.ruby.latency_hist_seqr::mean 8.935382 -system.ruby.latency_hist_seqr::gmean 1.815175 -system.ruby.latency_hist_seqr::stdev 22.675647 -system.ruby.latency_hist_seqr | 8624 97.42% 97.42% | 191 2.16% 99.58% | 24 0.27% 99.85% | 5 0.06% 99.91% | 2 0.02% 99.93% | 6 0.07% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.latency_hist_seqr::mean 9.377203 +system.ruby.latency_hist_seqr::gmean 1.827971 +system.ruby.latency_hist_seqr::stdev 23.652747 +system.ruby.latency_hist_seqr | 8226 92.93% 92.93% | 589 6.65% 99.58% | 26 0.29% 99.88% | 4 0.05% 99.92% | 3 0.03% 99.95% | 4 0.05% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.latency_hist_seqr::total 8852 system.ruby.hit_latency_hist_seqr::bucket_size 1 system.ruby.hit_latency_hist_seqr::max_bucket 9 @@ -368,21 +378,21 @@ system.ruby.hit_latency_hist_seqr::total 7475 system.ruby.miss_latency_hist_seqr::bucket_size 64 system.ruby.miss_latency_hist_seqr::max_bucket 639 system.ruby.miss_latency_hist_seqr::samples 1377 -system.ruby.miss_latency_hist_seqr::mean 52.012346 -system.ruby.miss_latency_hist_seqr::gmean 46.179478 -system.ruby.miss_latency_hist_seqr::stdev 33.292581 -system.ruby.miss_latency_hist_seqr | 1149 83.44% 83.44% | 191 13.87% 97.31% | 24 1.74% 99.06% | 5 0.36% 99.42% | 2 0.15% 99.56% | 6 0.44% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.miss_latency_hist_seqr::mean 54.852578 +system.ruby.miss_latency_hist_seqr::gmean 48.312712 +system.ruby.miss_latency_hist_seqr::stdev 33.880423 +system.ruby.miss_latency_hist_seqr | 751 54.54% 54.54% | 589 42.77% 97.31% | 26 1.89% 99.20% | 4 0.29% 99.49% | 3 0.22% 99.71% | 4 0.29% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.miss_latency_hist_seqr::total 1377 system.ruby.Directory.incomplete_times_seqr 1376 -system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 87948 # Cumulative time (in ticks) in various power states +system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 91859 # Cumulative time (in ticks) in various power states system.ruby.l1_cntrl0.cacheMemory.demand_hits 7475 # Number of cache demand hits system.ruby.l1_cntrl0.cacheMemory.demand_misses 1377 # Number of cache demand misses system.ruby.l1_cntrl0.cacheMemory.demand_accesses 8852 # Number of cache demand accesses -system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 87948 # Cumulative time (in ticks) in various power states -system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 87948 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 91859 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 91859 # Cumulative time (in ticks) in various power states system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 87948 # Cumulative time (in ticks) in various power states -system.ruby.network.routers0.percent_links_utilized 7.817119 +system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 91859 # Cumulative time (in ticks) in various power states +system.ruby.network.routers0.percent_links_utilized 7.484297 system.ruby.network.routers0.msg_count.Control::2 1377 system.ruby.network.routers0.msg_count.Data::2 1373 system.ruby.network.routers0.msg_count.Response_Data::4 1377 @@ -391,8 +401,8 @@ system.ruby.network.routers0.msg_bytes.Control::2 11016 system.ruby.network.routers0.msg_bytes.Data::2 98856 system.ruby.network.routers0.msg_bytes.Response_Data::4 99144 system.ruby.network.routers0.msg_bytes.Writeback_Control::3 10984 -system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 87948 # Cumulative time (in ticks) in various power states -system.ruby.network.routers1.percent_links_utilized 7.817119 +system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 91859 # Cumulative time (in ticks) in various power states +system.ruby.network.routers1.percent_links_utilized 7.484297 system.ruby.network.routers1.msg_count.Control::2 1377 system.ruby.network.routers1.msg_count.Data::2 1373 system.ruby.network.routers1.msg_count.Response_Data::4 1377 @@ -401,8 +411,8 @@ system.ruby.network.routers1.msg_bytes.Control::2 11016 system.ruby.network.routers1.msg_bytes.Data::2 98856 system.ruby.network.routers1.msg_bytes.Response_Data::4 99144 system.ruby.network.routers1.msg_bytes.Writeback_Control::3 10984 -system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 87948 # Cumulative time (in ticks) in various power states -system.ruby.network.routers2.percent_links_utilized 7.817119 +system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 91859 # Cumulative time (in ticks) in various power states +system.ruby.network.routers2.percent_links_utilized 7.484297 system.ruby.network.routers2.msg_count.Control::2 1377 system.ruby.network.routers2.msg_count.Data::2 1373 system.ruby.network.routers2.msg_count.Response_Data::4 1377 @@ -411,7 +421,7 @@ system.ruby.network.routers2.msg_bytes.Control::2 11016 system.ruby.network.routers2.msg_bytes.Data::2 98856 system.ruby.network.routers2.msg_bytes.Response_Data::4 99144 system.ruby.network.routers2.msg_bytes.Writeback_Control::3 10984 -system.ruby.network.pwrStateResidencyTicks::UNDEFINED 87948 # Cumulative time (in ticks) in various power states +system.ruby.network.pwrStateResidencyTicks::UNDEFINED 91859 # Cumulative time (in ticks) in various power states system.ruby.network.msg_count.Control 4131 system.ruby.network.msg_count.Data 4119 system.ruby.network.msg_count.Response_Data 4131 @@ -420,33 +430,33 @@ system.ruby.network.msg_byte.Control 33048 system.ruby.network.msg_byte.Data 296568 system.ruby.network.msg_byte.Response_Data 297432 system.ruby.network.msg_byte.Writeback_Control 32952 -system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 87948 # Cumulative time (in ticks) in various power states -system.ruby.network.routers0.throttle0.link_utilization 7.826215 +system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 91859 # Cumulative time (in ticks) in various power states +system.ruby.network.routers0.throttle0.link_utilization 7.493006 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1377 system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 1373 system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 99144 system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 10984 -system.ruby.network.routers0.throttle1.link_utilization 7.808023 +system.ruby.network.routers0.throttle1.link_utilization 7.475588 system.ruby.network.routers0.throttle1.msg_count.Control::2 1377 system.ruby.network.routers0.throttle1.msg_count.Data::2 1373 system.ruby.network.routers0.throttle1.msg_bytes.Control::2 11016 system.ruby.network.routers0.throttle1.msg_bytes.Data::2 98856 -system.ruby.network.routers1.throttle0.link_utilization 7.808023 +system.ruby.network.routers1.throttle0.link_utilization 7.475588 system.ruby.network.routers1.throttle0.msg_count.Control::2 1377 system.ruby.network.routers1.throttle0.msg_count.Data::2 1373 system.ruby.network.routers1.throttle0.msg_bytes.Control::2 11016 system.ruby.network.routers1.throttle0.msg_bytes.Data::2 98856 -system.ruby.network.routers1.throttle1.link_utilization 7.826215 +system.ruby.network.routers1.throttle1.link_utilization 7.493006 system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 1377 system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 1373 system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 99144 system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 10984 -system.ruby.network.routers2.throttle0.link_utilization 7.826215 +system.ruby.network.routers2.throttle0.link_utilization 7.493006 system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 1377 system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 1373 system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 99144 system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 10984 -system.ruby.network.routers2.throttle1.link_utilization 7.808023 +system.ruby.network.routers2.throttle1.link_utilization 7.475588 system.ruby.network.routers2.throttle1.msg_count.Control::2 1377 system.ruby.network.routers2.throttle1.msg_count.Data::2 1373 system.ruby.network.routers2.throttle1.msg_bytes.Control::2 11016 @@ -464,10 +474,10 @@ system.ruby.delayVCHist.vnet_2::total 1373 # de system.ruby.LD.latency_hist_seqr::bucket_size 32 system.ruby.LD.latency_hist_seqr::max_bucket 319 system.ruby.LD.latency_hist_seqr::samples 1045 -system.ruby.LD.latency_hist_seqr::mean 22.607656 -system.ruby.LD.latency_hist_seqr::gmean 5.952637 -system.ruby.LD.latency_hist_seqr::stdev 28.358291 -system.ruby.LD.latency_hist_seqr | 546 52.25% 52.25% | 420 40.19% 92.44% | 70 6.70% 99.14% | 2 0.19% 99.33% | 2 0.19% 99.52% | 4 0.38% 99.90% | 0 0.00% 99.90% | 1 0.10% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.latency_hist_seqr::mean 23.607656 +system.ruby.LD.latency_hist_seqr::gmean 6.057935 +system.ruby.LD.latency_hist_seqr::stdev 29.475705 +system.ruby.LD.latency_hist_seqr | 546 52.25% 52.25% | 330 31.58% 83.83% | 162 15.50% 99.33% | 1 0.10% 99.43% | 4 0.38% 99.81% | 1 0.10% 99.90% | 0 0.00% 99.90% | 1 0.10% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.latency_hist_seqr::total 1045 system.ruby.LD.hit_latency_hist_seqr::bucket_size 1 system.ruby.LD.hit_latency_hist_seqr::max_bucket 9 @@ -479,18 +489,18 @@ system.ruby.LD.hit_latency_hist_seqr::total 546 system.ruby.LD.miss_latency_hist_seqr::bucket_size 32 system.ruby.LD.miss_latency_hist_seqr::max_bucket 319 system.ruby.LD.miss_latency_hist_seqr::samples 499 -system.ruby.LD.miss_latency_hist_seqr::mean 46.250501 -system.ruby.LD.miss_latency_hist_seqr::gmean 41.916728 -system.ruby.LD.miss_latency_hist_seqr::stdev 24.776985 -system.ruby.LD.miss_latency_hist_seqr | 0 0.00% 0.00% | 420 84.17% 84.17% | 70 14.03% 98.20% | 2 0.40% 98.60% | 2 0.40% 99.00% | 4 0.80% 99.80% | 0 0.00% 99.80% | 1 0.20% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.miss_latency_hist_seqr::mean 48.344689 +system.ruby.LD.miss_latency_hist_seqr::gmean 43.484561 +system.ruby.LD.miss_latency_hist_seqr::stdev 25.453032 +system.ruby.LD.miss_latency_hist_seqr | 0 0.00% 0.00% | 330 66.13% 66.13% | 162 32.46% 98.60% | 1 0.20% 98.80% | 4 0.80% 99.60% | 1 0.20% 99.80% | 0 0.00% 99.80% | 1 0.20% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.miss_latency_hist_seqr::total 499 system.ruby.ST.latency_hist_seqr::bucket_size 64 system.ruby.ST.latency_hist_seqr::max_bucket 639 system.ruby.ST.latency_hist_seqr::samples 935 -system.ruby.ST.latency_hist_seqr::mean 15.124064 -system.ruby.ST.latency_hist_seqr::gmean 2.829099 -system.ruby.ST.latency_hist_seqr::stdev 31.003309 -system.ruby.ST.latency_hist_seqr | 897 95.94% 95.94% | 28 2.99% 98.93% | 5 0.53% 99.47% | 3 0.32% 99.79% | 0 0.00% 99.79% | 2 0.21% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.latency_hist_seqr::mean 16.455615 +system.ruby.ST.latency_hist_seqr::gmean 2.877223 +system.ruby.ST.latency_hist_seqr::stdev 34.720603 +system.ruby.ST.latency_hist_seqr | 821 87.81% 87.81% | 102 10.91% 98.72% | 6 0.64% 99.36% | 2 0.21% 99.57% | 2 0.21% 99.79% | 2 0.21% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ST.latency_hist_seqr::total 935 system.ruby.ST.hit_latency_hist_seqr::bucket_size 1 system.ruby.ST.hit_latency_hist_seqr::max_bucket 9 @@ -502,18 +512,18 @@ system.ruby.ST.hit_latency_hist_seqr::total 681 system.ruby.ST.miss_latency_hist_seqr::bucket_size 64 system.ruby.ST.miss_latency_hist_seqr::max_bucket 639 system.ruby.ST.miss_latency_hist_seqr::samples 254 -system.ruby.ST.miss_latency_hist_seqr::mean 52.992126 -system.ruby.ST.miss_latency_hist_seqr::gmean 45.979346 -system.ruby.ST.miss_latency_hist_seqr::stdev 39.646660 -system.ruby.ST.miss_latency_hist_seqr | 216 85.04% 85.04% | 28 11.02% 96.06% | 5 1.97% 98.03% | 3 1.18% 99.21% | 0 0.00% 99.21% | 2 0.79% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.miss_latency_hist_seqr::mean 57.893701 +system.ruby.ST.miss_latency_hist_seqr::gmean 48.924758 +system.ruby.ST.miss_latency_hist_seqr::stdev 45.645746 +system.ruby.ST.miss_latency_hist_seqr | 140 55.12% 55.12% | 102 40.16% 95.28% | 6 2.36% 97.64% | 2 0.79% 98.43% | 2 0.79% 99.21% | 2 0.79% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ST.miss_latency_hist_seqr::total 254 system.ruby.IFETCH.latency_hist_seqr::bucket_size 64 system.ruby.IFETCH.latency_hist_seqr::max_bucket 639 system.ruby.IFETCH.latency_hist_seqr::samples 6864 -system.ruby.IFETCH.latency_hist_seqr::mean 6.015589 -system.ruby.IFETCH.latency_hist_seqr::gmean 1.426336 -system.ruby.IFETCH.latency_hist_seqr::stdev 19.173758 -system.ruby.IFETCH.latency_hist_seqr | 6753 98.38% 98.38% | 91 1.33% 99.71% | 13 0.19% 99.90% | 1 0.01% 99.91% | 2 0.03% 99.94% | 4 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.latency_hist_seqr::mean 6.251748 +system.ruby.IFETCH.latency_hist_seqr::gmean 1.432185 +system.ruby.IFETCH.latency_hist_seqr::stdev 19.434647 +system.ruby.IFETCH.latency_hist_seqr | 6521 95.00% 95.00% | 324 4.72% 99.72% | 15 0.22% 99.94% | 1 0.01% 99.96% | 1 0.01% 99.97% | 2 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.latency_hist_seqr::total 6864 system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 1 system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 9 @@ -525,10 +535,10 @@ system.ruby.IFETCH.hit_latency_hist_seqr::total 6241 system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 64 system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 639 system.ruby.IFETCH.miss_latency_hist_seqr::samples 623 -system.ruby.IFETCH.miss_latency_hist_seqr::mean 56.260032 -system.ruby.IFETCH.miss_latency_hist_seqr::gmean 50.022291 -system.ruby.IFETCH.miss_latency_hist_seqr::stdev 35.712767 -system.ruby.IFETCH.miss_latency_hist_seqr | 512 82.18% 82.18% | 91 14.61% 96.79% | 13 2.09% 98.88% | 1 0.16% 99.04% | 2 0.32% 99.36% | 4 0.64% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.miss_latency_hist_seqr::mean 58.861958 +system.ruby.IFETCH.miss_latency_hist_seqr::gmean 52.329270 +system.ruby.IFETCH.miss_latency_hist_seqr::stdev 33.443818 +system.ruby.IFETCH.miss_latency_hist_seqr | 280 44.94% 44.94% | 324 52.01% 96.95% | 15 2.41% 99.36% | 1 0.16% 99.52% | 1 0.16% 99.68% | 2 0.32% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.miss_latency_hist_seqr::total 623 system.ruby.RMW_Read.latency_hist_seqr::bucket_size 4 system.ruby.RMW_Read.latency_hist_seqr::max_bucket 39 @@ -556,10 +566,10 @@ system.ruby.RMW_Read.miss_latency_hist_seqr::total 1 system.ruby.Directory.miss_mach_latency_hist_seqr::bucket_size 64 system.ruby.Directory.miss_mach_latency_hist_seqr::max_bucket 639 system.ruby.Directory.miss_mach_latency_hist_seqr::samples 1377 -system.ruby.Directory.miss_mach_latency_hist_seqr::mean 52.012346 -system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 46.179478 -system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 33.292581 -system.ruby.Directory.miss_mach_latency_hist_seqr | 1149 83.44% 83.44% | 191 13.87% 97.31% | 24 1.74% 99.06% | 5 0.36% 99.42% | 2 0.15% 99.56% | 6 0.44% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_mach_latency_hist_seqr::mean 54.852578 +system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 48.312712 +system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 33.880423 +system.ruby.Directory.miss_mach_latency_hist_seqr | 751 54.54% 54.54% | 589 42.77% 97.31% | 26 1.89% 99.20% | 4 0.29% 99.49% | 3 0.22% 99.71% | 4 0.29% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.Directory.miss_mach_latency_hist_seqr::total 1377 system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::bucket_size 1 system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::max_bucket 9 @@ -590,26 +600,26 @@ system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::total system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size 32 system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket 319 system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples 499 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 46.250501 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 41.916728 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 24.776985 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 420 84.17% 84.17% | 70 14.03% 98.20% | 2 0.40% 98.60% | 2 0.40% 99.00% | 4 0.80% 99.80% | 0 0.00% 99.80% | 1 0.20% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 48.344689 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 43.484561 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 25.453032 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 330 66.13% 66.13% | 162 32.46% 98.60% | 1 0.20% 98.80% | 4 0.80% 99.60% | 1 0.20% 99.80% | 0 0.00% 99.80% | 1 0.20% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total 499 system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::samples 254 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 52.992126 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 45.979346 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 39.646660 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 216 85.04% 85.04% | 28 11.02% 96.06% | 5 1.97% 98.03% | 3 1.18% 99.21% | 0 0.00% 99.21% | 2 0.79% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 57.893701 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 48.924758 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 45.645746 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 140 55.12% 55.12% | 102 40.16% 95.28% | 6 2.36% 97.64% | 2 0.79% 98.43% | 2 0.79% 99.21% | 2 0.79% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total 254 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::samples 623 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 56.260032 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 50.022291 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 35.712767 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 512 82.18% 82.18% | 91 14.61% 96.79% | 13 2.09% 98.88% | 1 0.16% 99.04% | 2 0.32% 99.36% | 4 0.64% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 58.861958 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 52.329270 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 33.443818 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 280 44.94% 44.94% | 324 52.01% 96.95% | 15 2.41% 99.36% | 1 0.16% 99.52% | 1 0.16% 99.68% | 2 0.32% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::total 623 system.ruby.RMW_Read.Directory.miss_type_mach_latency_hist_seqr::bucket_size 4 system.ruby.RMW_Read.Directory.miss_type_mach_latency_hist_seqr::max_bucket 39 diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/config.ini b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/config.ini index 83c5a15fe..965e2a045 100644 --- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/config.ini +++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/config.ini @@ -173,7 +173,7 @@ useIndirect=true [system.cpu.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -531,7 +531,7 @@ pipelined=false [system.cpu.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -600,7 +600,7 @@ size=48 [system.cpu.l2cache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -740,6 +740,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -751,7 +752,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -759,29 +760,36 @@ width=16 master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -801,6 +809,7 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 @@ -810,7 +819,7 @@ p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 page_policy=open_adaptive power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 @@ -832,9 +841,9 @@ tRTW=2500 tWR=15000 tWTR=7500 tXAW=30000 -tXP=0 +tXP=6000 tXPDLL=0 -tXS=0 +tXS=270000 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/simout b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/simout index b07f24804..237d01682 100755 --- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/simout +++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 19 2016 12:23:51 -gem5 started Jul 19 2016 12:24:26 -gem5 executing on e108600-lin, pid 39592 +gem5 compiled Oct 11 2016 00:00:58 +gem5 started Oct 13 2016 20:19:48 +gem5 executing on e108600-lin, pid 28095 command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing-mt -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/01.hello-2T-smt/alpha/linux/o3-timing-mt Global frequency set at 1000000000000 ticks per second @@ -14,4 +14,4 @@ info: Increasing stack size by one page. info: Increasing stack size by one page. Hello world! Hello world! -Exiting @ tick 25580500 because target called exit() +Exiting @ tick 26661500 because target called exit() diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/stats.txt b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/stats.txt index ad56ff040..0fd976f9c 100644 --- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/stats.txt +++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/stats.txt @@ -1,43 +1,43 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000026 # Number of seconds simulated -sim_ticks 25607000 # Number of ticks simulated -final_tick 25607000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000027 # Number of seconds simulated +sim_ticks 26661500 # Number of ticks simulated +final_tick 26661500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 110915 # Simulator instruction rate (inst/s) -host_op_rate 110902 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 222369986 # Simulator tick rate (ticks/s) -host_mem_usage 254744 # Number of bytes of host memory used -host_seconds 0.12 # Real time elapsed on the host +host_inst_rate 67147 # Simulator instruction rate (inst/s) +host_op_rate 67138 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 140157650 # Simulator tick rate (ticks/s) +host_mem_usage 253164 # Number of bytes of host memory used +host_seconds 0.19 # Real time elapsed on the host sim_insts 12770 # Number of instructions simulated sim_ops 12770 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 25607000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 39936 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 21824 # Number of bytes read from this memory -system.physmem.bytes_read::total 61760 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 39936 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 39936 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 624 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 341 # Number of read requests responded to by this memory -system.physmem.num_reads::total 965 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1559573554 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 852266958 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2411840512 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1559573554 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1559573554 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1559573554 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 852266958 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2411840512 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 966 # Number of read requests accepted +system.physmem.pwrStateResidencyTicks::UNDEFINED 26661500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 40000 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 21888 # Number of bytes read from this memory +system.physmem.bytes_read::total 61888 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 40000 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 40000 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 625 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 342 # Number of read requests responded to by this memory +system.physmem.num_reads::total 967 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1500290681 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 820959061 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2321249742 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1500290681 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1500290681 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1500290681 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 820959061 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2321249742 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 968 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 966 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 968 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 61824 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 61952 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 61824 # Total read bytes from the system interface side +system.physmem.bytesReadSys 61952 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one @@ -47,11 +47,11 @@ system.physmem.perBankRdBursts::1 150 # Pe system.physmem.perBankRdBursts::2 77 # Per bank write bursts system.physmem.perBankRdBursts::3 58 # Per bank write bursts system.physmem.perBankRdBursts::4 90 # Per bank write bursts -system.physmem.perBankRdBursts::5 46 # Per bank write bursts -system.physmem.perBankRdBursts::6 32 # Per bank write bursts +system.physmem.perBankRdBursts::5 45 # Per bank write bursts +system.physmem.perBankRdBursts::6 33 # Per bank write bursts system.physmem.perBankRdBursts::7 50 # Per bank write bursts -system.physmem.perBankRdBursts::8 41 # Per bank write bursts -system.physmem.perBankRdBursts::9 37 # Per bank write bursts +system.physmem.perBankRdBursts::8 42 # Per bank write bursts +system.physmem.perBankRdBursts::9 38 # Per bank write bursts system.physmem.perBankRdBursts::10 28 # Per bank write bursts system.physmem.perBankRdBursts::11 34 # Per bank write bursts system.physmem.perBankRdBursts::12 15 # Per bank write bursts @@ -76,14 +76,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 25577000 # Total gap between requests +system.physmem.totGap 26630500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 966 # Read request sizes (log2) +system.physmem.readPktSize::6 968 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -91,14 +91,14 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 351 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 323 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 171 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 89 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 23 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 332 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 313 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 185 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 94 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 37 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 7 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see @@ -187,105 +187,115 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 211 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 278.748815 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 172.887192 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 291.495109 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 76 36.02% 36.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 57 27.01% 63.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 23 10.90% 73.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 12 5.69% 79.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 8 3.79% 83.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 11 5.21% 88.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 6 2.84% 91.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 6 2.84% 94.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 12 5.69% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 211 # Bytes accessed per row activation -system.physmem.totQLat 14120500 # Total ticks spent queuing -system.physmem.totMemAccLat 32233000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 4830000 # Total ticks spent in databus transfers -system.physmem.avgQLat 14617.49 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 202 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 289.584158 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 180.299588 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 295.891915 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 69 34.16% 34.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 55 27.23% 61.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 20 9.90% 71.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 16 7.92% 79.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 9 4.46% 83.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 7 3.47% 87.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 9 4.46% 91.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 3 1.49% 93.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 14 6.93% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 202 # Bytes accessed per row activation +system.physmem.totQLat 15942250 # Total ticks spent queuing +system.physmem.totMemAccLat 34092250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 4840000 # Total ticks spent in databus transfers +system.physmem.avgQLat 16469.27 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 33367.49 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2414.34 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 35219.27 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2323.65 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2414.34 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 2323.65 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 18.86 # Data bus utilization in percentage -system.physmem.busUtilRead 18.86 # Data bus utilization in percentage for reads +system.physmem.busUtil 18.15 # Data bus utilization in percentage +system.physmem.busUtilRead 18.15 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 2.46 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 745 # Number of row buffer hits during reads +system.physmem.readRowHits 755 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 77.12 # Row buffer hit rate for reads +system.physmem.readRowHitRate 78.00 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 26477.23 # Average gap between requests -system.physmem.pageHitRate 77.12 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 861840 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 470250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 4477200 # Energy for read commands per rank (pJ) +system.physmem.avgGap 27510.85 # Average gap between requests +system.physmem.pageHitRate 78.00 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 849660 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 436425 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 4191180 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 16092810 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 54750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 23482530 # Total energy per rank (pJ) -system.physmem_0.averagePower 994.232548 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 763000 # Time in different power states +system.physmem_0.refreshEnergy 1843920.000000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 6127500 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 47520 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 5972460 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 1440 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 19470105 # Total energy per rank (pJ) +system.physmem_0.averagePower 730.243038 # Core power per rank (mW) +system.physmem_0.totalIdleTime 12953500 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 40500 # Time in different power states system.physmem_0.memoryStateTime::REF 780000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 22830000 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 703080 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 383625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 2628600 # Energy for read commands per rank (pJ) +system.physmem_0.memoryStateTime::SREF 0 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 3750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 12735000 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 13102250 # Time in different power states +system.physmem_1.actEnergy 671160 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 330165 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 2720340 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 15488325 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 585000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 21314310 # Total energy per rank (pJ) -system.physmem_1.averagePower 902.431754 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 878500 # Time in different power states +system.physmem_1.refreshEnergy 1843920.000000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 4612440 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 162240 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 6908970 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 373920 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 17623155 # Total energy per rank (pJ) +system.physmem_1.averagePower 660.971589 # Core power per rank (mW) +system.physmem_1.totalIdleTime 16131250 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 312000 # Time in different power states system.physmem_1.memoryStateTime::REF 780000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 21974000 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 25607000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 4896 # Number of BP lookups -system.cpu.branchPred.condPredicted 2917 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 793 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 3827 # Number of BTB lookups -system.cpu.branchPred.BTBHits 1151 # Number of BTB hits +system.physmem_1.memoryStateTime::SREF 0 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 973000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 9438250 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 15158250 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 26661500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 4864 # Number of BP lookups +system.cpu.branchPred.condPredicted 2895 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 795 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 3714 # Number of BTB lookups +system.cpu.branchPred.BTBHits 1183 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 30.075777 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 688 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 51 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 820 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 149 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 671 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 136 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 31.852450 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 710 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 56 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 762 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 147 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 615 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 133 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 4131 # DTB read hits -system.cpu.dtb.read_misses 80 # DTB read misses +system.cpu.dtb.read_hits 4130 # DTB read hits +system.cpu.dtb.read_misses 76 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 4211 # DTB read accesses -system.cpu.dtb.write_hits 2002 # DTB write hits -system.cpu.dtb.write_misses 47 # DTB write misses +system.cpu.dtb.read_accesses 4206 # DTB read accesses +system.cpu.dtb.write_hits 2011 # DTB write hits +system.cpu.dtb.write_misses 48 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 2049 # DTB write accesses -system.cpu.dtb.data_hits 6133 # DTB hits -system.cpu.dtb.data_misses 127 # DTB misses +system.cpu.dtb.write_accesses 2059 # DTB write accesses +system.cpu.dtb.data_hits 6141 # DTB hits +system.cpu.dtb.data_misses 124 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 6260 # DTB accesses -system.cpu.itb.fetch_hits 3841 # ITB hits +system.cpu.dtb.data_accesses 6265 # DTB accesses +system.cpu.itb.fetch_hits 3836 # ITB hits system.cpu.itb.fetch_misses 50 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 3891 # ITB accesses +system.cpu.itb.fetch_accesses 3886 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -300,313 +310,313 @@ system.cpu.itb.data_acv 0 # DT system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload0.num_syscalls 17 # Number of system calls system.cpu.workload1.num_syscalls 17 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 25607000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 51215 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 26661500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 53324 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 758 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 28344 # Number of instructions fetch has processed -system.cpu.fetch.Branches 4896 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 1988 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 10026 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 873 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 478 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.CacheLines 3841 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 575 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 26635 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.064164 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.464308 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 748 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 27869 # Number of instructions fetch has processed +system.cpu.fetch.Branches 4864 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 2040 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 9408 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 875 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 344 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.CacheLines 3836 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 566 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 26300 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.059658 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.449516 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 21569 80.98% 80.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 505 1.90% 82.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 398 1.49% 84.37% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 435 1.63% 86.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 472 1.77% 87.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 332 1.25% 89.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 468 1.76% 90.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 266 1.00% 91.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 2190 8.22% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 21275 80.89% 80.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 504 1.92% 82.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 391 1.49% 84.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 446 1.70% 85.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 478 1.82% 87.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 367 1.40% 89.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 469 1.78% 90.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 276 1.05% 92.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 2094 7.96% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 26635 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.095597 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.553432 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 36561 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 11106 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 3971 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 513 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 726 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 381 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 147 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 24763 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 394 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 726 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 36906 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 4191 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 1623 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 4148 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 5283 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 23783 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 30 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 282 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 398 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 4456 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 17841 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 29807 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 29789 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 26300 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.091216 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.522635 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 36528 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 10375 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 3958 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 495 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 725 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 405 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 151 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 24583 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 377 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 725 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 36872 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 3499 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 1435 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 4116 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 5434 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 23584 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 36 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 223 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 328 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 4703 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 17574 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 29532 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 29514 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 16 # Number of floating rename lookups system.cpu.rename.CommittedMaps 9154 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 8687 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 8420 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 57 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 45 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 1771 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2529 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1253 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 14 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 4 # Number of conflicting stores. -system.cpu.memDep1.insertedLoads 1973 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep1.insertedStores 1111 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep1.conflictingLoads 6 # Number of conflicting loads. -system.cpu.memDep1.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 21942 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 50 # Number of non-speculative instructions added to the IQ +system.cpu.rename.skidInsts 1621 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 1925 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1093 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 7 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. +system.cpu.memDep1.insertedLoads 2578 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep1.insertedStores 1286 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep1.conflictingLoads 15 # Number of conflicting loads. +system.cpu.memDep1.conflictingStores 4 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 21800 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 51 # Number of non-speculative instructions added to the IQ system.cpu.iq.iqInstsIssued 19296 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 47 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 9221 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 4863 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 16 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 26635 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.724460 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.451046 # Number of insts issued each cycle +system.cpu.iq.iqSquashedInstsIssued 51 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 9080 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 4753 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 17 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 26300 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.733688 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.450617 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 19310 72.50% 72.50% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 2394 8.99% 81.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 1620 6.08% 87.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 1274 4.78% 92.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 1030 3.87% 96.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 532 2.00% 98.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 319 1.20% 99.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 102 0.38% 99.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 54 0.20% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 18970 72.13% 72.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 2362 8.98% 81.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 1626 6.18% 87.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 1294 4.92% 92.21% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 1061 4.03% 96.25% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 563 2.14% 98.39% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 282 1.07% 99.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 87 0.33% 99.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 55 0.21% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 26635 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 26300 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 28 9.18% 9.18% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 9.18% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 9.18% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.18% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.18% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.18% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 9.18% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 9.18% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 9.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 9.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 9.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 9.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 9.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 9.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 9.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 9.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 9.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 9.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 9.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 9.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 9.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 9.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 9.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.18% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 201 65.90% 75.08% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 76 24.92% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 29 9.70% 9.70% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 9.70% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 9.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 9.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 9.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 9.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 9.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 9.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 9.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 9.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 9.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 9.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 9.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 9.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 9.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 9.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 9.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 9.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 9.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 9.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.70% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 191 63.88% 73.58% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 79 26.42% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 6749 65.93% 65.95% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.01% 65.96% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.96% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.98% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2387 23.32% 89.30% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1095 10.70% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 5884 66.04% 66.06% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.01% 66.07% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.07% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 66.09% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.09% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.09% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.09% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.09% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.09% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2015 22.62% 88.71% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1006 11.29% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 10236 # Type of FU issued +system.cpu.iq.FU_type_0::total 8910 # Type of FU issued system.cpu.iq.FU_type_1::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_1::IntAlu 6020 66.45% 66.47% # Type of FU issued -system.cpu.iq.FU_type_1::IntMult 1 0.01% 66.48% # Type of FU issued -system.cpu.iq.FU_type_1::IntDiv 0 0.00% 66.48% # Type of FU issued -system.cpu.iq.FU_type_1::FloatAdd 2 0.02% 66.50% # Type of FU issued -system.cpu.iq.FU_type_1::FloatCmp 0 0.00% 66.50% # Type of FU issued -system.cpu.iq.FU_type_1::FloatCvt 0 0.00% 66.50% # Type of FU issued -system.cpu.iq.FU_type_1::FloatMult 0 0.00% 66.50% # Type of FU issued -system.cpu.iq.FU_type_1::FloatDiv 0 0.00% 66.50% # Type of FU issued -system.cpu.iq.FU_type_1::FloatSqrt 0 0.00% 66.50% # Type of FU issued -system.cpu.iq.FU_type_1::SimdAdd 0 0.00% 66.50% # Type of FU issued -system.cpu.iq.FU_type_1::SimdAddAcc 0 0.00% 66.50% # Type of FU issued -system.cpu.iq.FU_type_1::SimdAlu 0 0.00% 66.50% # Type of FU issued -system.cpu.iq.FU_type_1::SimdCmp 0 0.00% 66.50% # Type of FU issued -system.cpu.iq.FU_type_1::SimdCvt 0 0.00% 66.50% # Type of FU issued -system.cpu.iq.FU_type_1::SimdMisc 0 0.00% 66.50% # Type of FU issued -system.cpu.iq.FU_type_1::SimdMult 0 0.00% 66.50% # Type of FU issued -system.cpu.iq.FU_type_1::SimdMultAcc 0 0.00% 66.50% # Type of FU issued -system.cpu.iq.FU_type_1::SimdShift 0 0.00% 66.50% # Type of FU issued -system.cpu.iq.FU_type_1::SimdShiftAcc 0 0.00% 66.50% # Type of FU issued -system.cpu.iq.FU_type_1::SimdSqrt 0 0.00% 66.50% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatAdd 0 0.00% 66.50% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatAlu 0 0.00% 66.50% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatCmp 0 0.00% 66.50% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatCvt 0 0.00% 66.50% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatDiv 0 0.00% 66.50% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatMisc 0 0.00% 66.50% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatMult 0 0.00% 66.50% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatMultAcc 0 0.00% 66.50% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatSqrt 0 0.00% 66.50% # Type of FU issued -system.cpu.iq.FU_type_1::MemRead 2019 22.28% 88.79% # Type of FU issued -system.cpu.iq.FU_type_1::MemWrite 1016 11.21% 100.00% # Type of FU issued +system.cpu.iq.FU_type_1::IntAlu 6849 65.94% 65.96% # Type of FU issued +system.cpu.iq.FU_type_1::IntMult 1 0.01% 65.97% # Type of FU issued +system.cpu.iq.FU_type_1::IntDiv 0 0.00% 65.97% # Type of FU issued +system.cpu.iq.FU_type_1::FloatAdd 2 0.02% 65.99% # Type of FU issued +system.cpu.iq.FU_type_1::FloatCmp 0 0.00% 65.99% # Type of FU issued +system.cpu.iq.FU_type_1::FloatCvt 0 0.00% 65.99% # Type of FU issued +system.cpu.iq.FU_type_1::FloatMult 0 0.00% 65.99% # Type of FU issued +system.cpu.iq.FU_type_1::FloatDiv 0 0.00% 65.99% # Type of FU issued +system.cpu.iq.FU_type_1::FloatSqrt 0 0.00% 65.99% # Type of FU issued +system.cpu.iq.FU_type_1::SimdAdd 0 0.00% 65.99% # Type of FU issued +system.cpu.iq.FU_type_1::SimdAddAcc 0 0.00% 65.99% # Type of FU issued +system.cpu.iq.FU_type_1::SimdAlu 0 0.00% 65.99% # Type of FU issued +system.cpu.iq.FU_type_1::SimdCmp 0 0.00% 65.99% # Type of FU issued +system.cpu.iq.FU_type_1::SimdCvt 0 0.00% 65.99% # Type of FU issued +system.cpu.iq.FU_type_1::SimdMisc 0 0.00% 65.99% # Type of FU issued +system.cpu.iq.FU_type_1::SimdMult 0 0.00% 65.99% # Type of FU issued +system.cpu.iq.FU_type_1::SimdMultAcc 0 0.00% 65.99% # Type of FU issued +system.cpu.iq.FU_type_1::SimdShift 0 0.00% 65.99% # Type of FU issued +system.cpu.iq.FU_type_1::SimdShiftAcc 0 0.00% 65.99% # Type of FU issued +system.cpu.iq.FU_type_1::SimdSqrt 0 0.00% 65.99% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatAdd 0 0.00% 65.99% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatAlu 0 0.00% 65.99% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatCmp 0 0.00% 65.99% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatCvt 0 0.00% 65.99% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatDiv 0 0.00% 65.99% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatMisc 0 0.00% 65.99% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatMult 0 0.00% 65.99% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatMultAcc 0 0.00% 65.99% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatSqrt 0 0.00% 65.99% # Type of FU issued +system.cpu.iq.FU_type_1::MemRead 2411 23.21% 89.21% # Type of FU issued +system.cpu.iq.FU_type_1::MemWrite 1121 10.79% 100.00% # Type of FU issued system.cpu.iq.FU_type_1::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_1::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_1::total 9060 # Type of FU issued +system.cpu.iq.FU_type_1::total 10386 # Type of FU issued system.cpu.iq.FU_type::total 19296 0.00% 0.00% # Type of FU issued -system.cpu.iq.rate 0.376765 # Inst issue rate -system.cpu.iq.fu_busy_cnt::0 157 # FU busy when requested +system.cpu.iq.rate 0.361863 # Inst issue rate +system.cpu.iq.fu_busy_cnt::0 151 # FU busy when requested system.cpu.iq.fu_busy_cnt::1 148 # FU busy when requested -system.cpu.iq.fu_busy_cnt::total 305 # FU busy when requested -system.cpu.iq.fu_busy_rate::0 0.008136 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_busy_cnt::total 299 # FU busy when requested +system.cpu.iq.fu_busy_rate::0 0.007825 # FU busy rate (busy events/executed inst) system.cpu.iq.fu_busy_rate::1 0.007670 # FU busy rate (busy events/executed inst) -system.cpu.iq.fu_busy_rate::total 0.015806 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 65537 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 31224 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 17544 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fu_busy_rate::total 0.015495 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 65200 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 30942 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 17504 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 42 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 20 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 20 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 19575 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 19569 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 22 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 93 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 39 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1344 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 20 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 388 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 740 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 13 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 228 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 261 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread1.forwLoads 45 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.cacheBlocked 290 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread1.forwLoads 97 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread1.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread1.squashedLoads 788 # Number of loads squashed -system.cpu.iew.lsq.thread1.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread1.memOrderViolation 12 # Number of memory ordering violations -system.cpu.iew.lsq.thread1.squashedStores 246 # Number of stores squashed +system.cpu.iew.lsq.thread1.squashedLoads 1393 # Number of loads squashed +system.cpu.iew.lsq.thread1.ignoredResponses 14 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread1.memOrderViolation 19 # Number of memory ordering violations +system.cpu.iew.lsq.thread1.squashedStores 421 # Number of stores squashed system.cpu.iew.lsq.thread1.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread1.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread1.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread1.cacheBlocked 288 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread1.cacheBlocked 234 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 726 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 2949 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 377 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 22125 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 143 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 4502 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 2364 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 50 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 25 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 340 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 725 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1992 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 420 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 21985 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 174 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 4503 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 2379 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 51 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 21 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 390 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 32 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 130 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 639 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 769 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 18625 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts::0 2260 # Number of load instructions executed -system.cpu.iew.iewExecLoadInsts::1 1960 # Number of load instructions executed -system.cpu.iew.iewExecLoadInsts::total 4220 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 671 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 134 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 638 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 772 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 18585 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts::0 1945 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts::1 2264 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts::total 4209 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 711 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp::0 0 # number of swp insts executed system.cpu.iew.exec_swp::1 0 # number of swp insts executed system.cpu.iew.exec_swp::total 0 # number of swp insts executed -system.cpu.iew.exec_nop::0 66 # number of nop insts executed -system.cpu.iew.exec_nop::1 67 # number of nop insts executed -system.cpu.iew.exec_nop::total 133 # number of nop insts executed -system.cpu.iew.exec_refs::0 3318 # number of memory reference insts executed -system.cpu.iew.exec_refs::1 2963 # number of memory reference insts executed -system.cpu.iew.exec_refs::total 6281 # number of memory reference insts executed -system.cpu.iew.exec_branches::0 1546 # Number of branches executed -system.cpu.iew.exec_branches::1 1419 # Number of branches executed -system.cpu.iew.exec_branches::total 2965 # Number of branches executed -system.cpu.iew.exec_stores::0 1058 # Number of stores executed -system.cpu.iew.exec_stores::1 1003 # Number of stores executed -system.cpu.iew.exec_stores::total 2061 # Number of stores executed -system.cpu.iew.exec_rate 0.363663 # Inst execution rate -system.cpu.iew.wb_sent::0 9379 # cumulative count of insts sent to commit -system.cpu.iew.wb_sent::1 8440 # cumulative count of insts sent to commit -system.cpu.iew.wb_sent::total 17819 # cumulative count of insts sent to commit -system.cpu.iew.wb_count::0 9213 # cumulative count of insts written-back -system.cpu.iew.wb_count::1 8351 # cumulative count of insts written-back -system.cpu.iew.wb_count::total 17564 # cumulative count of insts written-back -system.cpu.iew.wb_producers::0 4854 # num instructions producing a value -system.cpu.iew.wb_producers::1 4443 # num instructions producing a value -system.cpu.iew.wb_producers::total 9297 # num instructions producing a value -system.cpu.iew.wb_consumers::0 6502 # num instructions consuming a value -system.cpu.iew.wb_consumers::1 5954 # num instructions consuming a value -system.cpu.iew.wb_consumers::total 12456 # num instructions consuming a value -system.cpu.iew.wb_rate::0 0.179889 # insts written-back per cycle -system.cpu.iew.wb_rate::1 0.163058 # insts written-back per cycle -system.cpu.iew.wb_rate::total 0.342946 # insts written-back per cycle -system.cpu.iew.wb_fanout::0 0.746540 # average fanout of values written-back -system.cpu.iew.wb_fanout::1 0.746221 # average fanout of values written-back -system.cpu.iew.wb_fanout::total 0.746387 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 9288 # The number of squashed insts skipped by commit +system.cpu.iew.exec_nop::0 63 # number of nop insts executed +system.cpu.iew.exec_nop::1 71 # number of nop insts executed +system.cpu.iew.exec_nop::total 134 # number of nop insts executed +system.cpu.iew.exec_refs::0 2942 # number of memory reference insts executed +system.cpu.iew.exec_refs::1 3338 # number of memory reference insts executed +system.cpu.iew.exec_refs::total 6280 # number of memory reference insts executed +system.cpu.iew.exec_branches::0 1393 # Number of branches executed +system.cpu.iew.exec_branches::1 1580 # Number of branches executed +system.cpu.iew.exec_branches::total 2973 # Number of branches executed +system.cpu.iew.exec_stores::0 997 # Number of stores executed +system.cpu.iew.exec_stores::1 1074 # Number of stores executed +system.cpu.iew.exec_stores::total 2071 # Number of stores executed +system.cpu.iew.exec_rate 0.348530 # Inst execution rate +system.cpu.iew.wb_sent::0 8281 # cumulative count of insts sent to commit +system.cpu.iew.wb_sent::1 9496 # cumulative count of insts sent to commit +system.cpu.iew.wb_sent::total 17777 # cumulative count of insts sent to commit +system.cpu.iew.wb_count::0 8197 # cumulative count of insts written-back +system.cpu.iew.wb_count::1 9327 # cumulative count of insts written-back +system.cpu.iew.wb_count::total 17524 # cumulative count of insts written-back +system.cpu.iew.wb_producers::0 4340 # num instructions producing a value +system.cpu.iew.wb_producers::1 4919 # num instructions producing a value +system.cpu.iew.wb_producers::total 9259 # num instructions producing a value +system.cpu.iew.wb_consumers::0 5879 # num instructions consuming a value +system.cpu.iew.wb_consumers::1 6619 # num instructions consuming a value +system.cpu.iew.wb_consumers::total 12498 # num instructions consuming a value +system.cpu.iew.wb_rate::0 0.153721 # insts written-back per cycle +system.cpu.iew.wb_rate::1 0.174912 # insts written-back per cycle +system.cpu.iew.wb_rate::total 0.328633 # insts written-back per cycle +system.cpu.iew.wb_fanout::0 0.738221 # average fanout of values written-back +system.cpu.iew.wb_fanout::1 0.743164 # average fanout of values written-back +system.cpu.iew.wb_fanout::total 0.740839 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 9130 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 34 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 647 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 26599 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.481371 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.387327 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 646 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 26282 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.487178 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.404713 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 21475 80.74% 80.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 2692 10.12% 90.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 910 3.42% 94.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 379 1.42% 95.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 247 0.93% 96.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 153 0.58% 97.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 207 0.78% 97.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 128 0.48% 98.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 408 1.53% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 21298 81.04% 81.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 2499 9.51% 90.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 926 3.52% 94.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 403 1.53% 95.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 249 0.95% 96.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 154 0.59% 97.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 215 0.82% 97.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 116 0.44% 98.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 422 1.61% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 26599 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 26282 # Number of insts commited each cycle system.cpu.commit.committedInsts::0 6402 # Number of instructions committed system.cpu.commit.committedInsts::1 6402 # Number of instructions committed system.cpu.commit.committedInsts::total 12804 # Number of instructions committed @@ -708,256 +718,256 @@ system.cpu.commit.op_class_1::IprAccess 0 0.00% 100.00% # Cl system.cpu.commit.op_class_1::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_1::total 6402 # Class of committed instruction system.cpu.commit.op_class::total 12804 0.00% 0.00% # Class of committed instruction -system.cpu.commit.bw_lim_events 408 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 113983 # The number of ROB reads -system.cpu.rob.rob_writes 45899 # The number of ROB writes -system.cpu.timesIdled 392 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 24580 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 422 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 113054 # The number of ROB reads +system.cpu.rob.rob_writes 45570 # The number of ROB writes +system.cpu.timesIdled 413 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 27024 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts::0 6385 # Number of Instructions Simulated system.cpu.committedInsts::1 6385 # Number of Instructions Simulated system.cpu.committedInsts::total 12770 # Number of Instructions Simulated system.cpu.committedOps::0 6385 # Number of Ops (including micro ops) Simulated system.cpu.committedOps::1 6385 # Number of Ops (including micro ops) Simulated system.cpu.committedOps::total 12770 # Number of Ops (including micro ops) Simulated -system.cpu.cpi::0 8.021143 # CPI: Cycles Per Instruction -system.cpu.cpi::1 8.021143 # CPI: Cycles Per Instruction -system.cpu.cpi_total 4.010572 # CPI: Total CPI of All Threads -system.cpu.ipc::0 0.124671 # IPC: Instructions Per Cycle -system.cpu.ipc::1 0.124671 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.249341 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 23552 # number of integer regfile reads -system.cpu.int_regfile_writes 13174 # number of integer regfile writes +system.cpu.cpi::0 8.351449 # CPI: Cycles Per Instruction +system.cpu.cpi::1 8.351449 # CPI: Cycles Per Instruction +system.cpu.cpi_total 4.175724 # CPI: Total CPI of All Threads +system.cpu.ipc::0 0.119740 # IPC: Instructions Per Cycle +system.cpu.ipc::1 0.119740 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.239479 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 23475 # number of integer regfile reads +system.cpu.int_regfile_writes 13132 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads system.cpu.fp_regfile_writes 4 # number of floating regfile writes system.cpu.misc_regfile_reads 2 # number of misc regfile reads system.cpu.misc_regfile_writes 2 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 25607000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 26661500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements::0 0 # number of replacements system.cpu.dcache.tags.replacements::1 0 # number of replacements system.cpu.dcache.tags.replacements::total 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 214.351374 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 4238 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 341 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 12.428152 # Average number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 216.020971 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 4236 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 342 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 12.385965 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 214.351374 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.052332 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.052332 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 341 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 77 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 264 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.083252 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 10843 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 10843 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 25607000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 3221 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 3221 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 1017 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 1017 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 4238 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 4238 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 4238 # number of overall hits -system.cpu.dcache.overall_hits::total 4238 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 300 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 300 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 713 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 713 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1013 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1013 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1013 # number of overall misses -system.cpu.dcache.overall_misses::total 1013 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 25278500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 25278500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 49654940 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 49654940 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 74933440 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 74933440 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 74933440 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 74933440 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 3521 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 3521 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.occ_blocks::cpu.data 216.020971 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.052739 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.052739 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 342 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 72 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 270 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.083496 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 10868 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 10868 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 26661500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 3224 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 3224 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 1012 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 1012 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 4236 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 4236 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 4236 # number of overall hits +system.cpu.dcache.overall_hits::total 4236 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 309 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 309 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 718 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 718 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1027 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1027 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1027 # number of overall misses +system.cpu.dcache.overall_misses::total 1027 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 24016000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 24016000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 51330451 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 51330451 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 75346451 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 75346451 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 75346451 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 75346451 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 3533 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 3533 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1730 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 1730 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 5251 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 5251 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 5251 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 5251 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.085203 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.085203 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.412139 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.412139 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.192916 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.192916 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.192916 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.192916 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 84261.666667 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 84261.666667 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69642.272090 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 69642.272090 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 73971.806515 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 73971.806515 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 73971.806515 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 73971.806515 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 6514 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 5263 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 5263 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 5263 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 5263 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.087461 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.087461 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.415029 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.415029 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.195136 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.195136 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.195136 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.195136 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 77721.682848 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 77721.682848 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 71490.878830 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 71490.878830 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 73365.580331 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 73365.580331 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 73365.580331 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 73365.580331 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 5997 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 137 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 108 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 47.547445 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 55.527778 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 103 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 103 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 568 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 568 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 671 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 671 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 671 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 671 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 197 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 197 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 145 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 145 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 342 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 342 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 342 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 342 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 18892500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 18892500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12000985 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 12000985 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 30893485 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 30893485 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 30893485 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 30893485 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.055950 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.055950 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083815 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.083815 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.065130 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.065130 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.065130 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.065130 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 95901.015228 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 95901.015228 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 82765.413793 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 82765.413793 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 90331.827485 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 90331.827485 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 90331.827485 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 90331.827485 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 25607000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 110 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 110 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 574 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 574 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 684 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 684 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 684 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 684 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 199 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 199 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 144 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 144 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 343 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 343 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 343 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 343 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17847000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 17847000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12459487 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 12459487 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 30306487 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 30306487 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 30306487 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 30306487 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.056326 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.056326 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083237 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.083237 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.065172 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.065172 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.065172 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.065172 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 89683.417085 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 89683.417085 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 86524.215278 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 86524.215278 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 88357.104956 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 88357.104956 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 88357.104956 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 88357.104956 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 26661500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements::0 7 # number of replacements system.cpu.icache.tags.replacements::1 0 # number of replacements system.cpu.icache.tags.replacements::total 7 # number of replacements -system.cpu.icache.tags.tagsinuse 314.192674 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 2931 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 627 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 4.674641 # Average number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 318.055053 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 2937 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 628 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 4.676752 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 314.192674 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.153414 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.153414 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 620 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 246 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 374 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.302734 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 8297 # Number of tag accesses -system.cpu.icache.tags.data_accesses 8297 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 25607000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 2931 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 2931 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 2931 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 2931 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 2931 # number of overall hits -system.cpu.icache.overall_hits::total 2931 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 904 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 904 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 904 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 904 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 904 # 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average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 94357.868020 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 94357.868020 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82129.006410 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 88780.701754 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 84483.954451 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82129.006410 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 88780.701754 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 84483.954451 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.996910 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 84886.206897 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 84886.206897 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 86044.800000 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 86044.800000 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 88212.121212 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 88212.121212 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 86044.800000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 86806.122449 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 86314.566116 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 86044.800000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 86806.122449 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 86314.566116 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1036,120 +1046,120 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 145 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 145 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 624 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 624 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 197 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 197 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 624 # 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number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 45008500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 26953000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 71961500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 45008500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 26953000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 71961500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 625 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 625 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 198 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 198 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 625 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 343 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 968 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 625 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 343 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 968 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10858500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10858500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 47528000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 47528000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 15496000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 15496000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 47528000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 26354500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 73882500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 47528000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 26354500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 73882500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.995215 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.995215 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.995223 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.995223 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.995215 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.995223 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.996904 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.995215 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.996910 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.995223 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.996904 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71203.448276 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71203.448276 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72129.006410 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72129.006410 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 84408.629442 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 84408.629442 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72129.006410 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 78809.941520 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 74494.306418 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72129.006410 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 78809.941520 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 74494.306418 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 976 # Total number of requests made to the snoop filter. +system.cpu.l2cache.overall_mshr_miss_rate::total 0.996910 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 74886.206897 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 74886.206897 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 76044.800000 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 76044.800000 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 78262.626263 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 78262.626263 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 76044.800000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 76835.276968 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 76324.896694 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 76044.800000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 76835.276968 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 76324.896694 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 978 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 9 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 25607000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 823 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 26661500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 825 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 7 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 145 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 145 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 627 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 197 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1261 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 683 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 1944 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 40576 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 21824 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 62400 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadCleanReq 628 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 198 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1263 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 685 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 1948 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 40640 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 21888 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 62528 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 969 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.002064 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.045408 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 971 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.002060 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.045361 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 967 99.79% 99.79% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 969 99.79% 99.79% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 2 0.21% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 969 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 495000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 971 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 496000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 940500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 3.7 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 511500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 2.0 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 966 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.respLayer0.occupancy 942000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 3.5 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 513000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.9 # Layer utilization (%) +system.membus.snoop_filter.tot_requests 968 # Total number of requests made to the snoop filter. system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 25607000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 820 # Transaction distribution +system.membus.pwrStateResidencyTicks::UNDEFINED 26661500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 822 # Transaction distribution system.membus.trans_dist::ReadExReq 145 # Transaction distribution system.membus.trans_dist::ReadExResp 145 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 821 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1931 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1931 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 61760 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 61760 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 823 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1935 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1935 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 61888 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 61888 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 966 # Request fanout histogram +system.membus.snoop_fanout::samples 968 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 966 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 968 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 966 # Request fanout histogram -system.membus.reqLayer0.occupancy 1177000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 4.6 # Layer utilization (%) -system.membus.respLayer1.occupancy 5133750 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 20.0 # Layer utilization (%) +system.membus.snoop_fanout::total 968 # Request fanout histogram +system.membus.reqLayer0.occupancy 1179500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 4.4 # Layer utilization (%) +system.membus.respLayer1.occupancy 5127250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 19.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini index 50d6b0572..c4ebeae2c 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini +++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini @@ -173,7 +173,7 @@ useIndirect=true [system.cpu.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -531,7 +531,7 @@ pipelined=false [system.cpu.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -590,7 +590,7 @@ size=64 [system.cpu.l2cache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -707,6 +707,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -718,7 +719,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -726,29 +727,36 @@ width=16 master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -768,6 +776,7 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 @@ -777,7 +786,7 @@ p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 page_policy=open_adaptive power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 @@ -799,9 +808,9 @@ tRTW=2500 tWR=15000 tWTR=7500 tXAW=30000 -tXP=0 +tXP=6000 tXPDLL=0 -tXS=0 +tXS=270000 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout index a008eb955..e1ebd0d0b 100755 --- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout +++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3- gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:30:06 -gem5 started Jul 21 2016 14:30:36 -gem5 executing on e108600-lin, pid 38673 +gem5 compiled Oct 13 2016 20:43:27 +gem5 started Oct 13 2016 20:45:42 +gem5 executing on e108600-lin, pid 17390 command line: /work/curdun01/gem5-external.hg/build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/02.insttest/sparc/linux/o3-timing Global frequency set at 1000000000000 ticks per second @@ -21,4 +21,4 @@ LDTX: Passed LDTW: Passed STTW: Passed Done -Exiting @ tick 28845500 because target called exit() +Exiting @ tick 29908500 because target called exit() diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt index 698dda741..24ae64048 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt @@ -1,50 +1,50 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000029 # Number of seconds simulated -sim_ticks 29089500 # Number of ticks simulated -final_tick 29089500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000030 # Number of seconds simulated +sim_ticks 29908500 # Number of ticks simulated +final_tick 29908500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 39190 # Simulator instruction rate (inst/s) -host_op_rate 39188 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 78964807 # Simulator tick rate (ticks/s) -host_mem_usage 252916 # Number of bytes of host memory used -host_seconds 0.37 # Real time elapsed on the host +host_inst_rate 58398 # Simulator instruction rate (inst/s) +host_op_rate 58392 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 120966219 # Simulator tick rate (ticks/s) +host_mem_usage 251080 # Number of bytes of host memory used +host_seconds 0.25 # Real time elapsed on the host sim_insts 14436 # Number of instructions simulated sim_ops 14436 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 29089500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 23232 # Number of bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 29908500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 23360 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 9408 # Number of bytes read from this memory -system.physmem.bytes_read::total 32640 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 23232 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 23232 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 363 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 32768 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 23360 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 23360 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 365 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 147 # Number of read requests responded to by this memory -system.physmem.num_reads::total 510 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 798638684 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 323415665 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1122054350 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 798638684 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 798638684 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 798638684 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 323415665 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1122054350 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 511 # Number of read requests accepted +system.physmem.num_reads::total 512 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 781048866 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 314559406 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1095608272 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 781048866 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 781048866 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 781048866 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 314559406 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1095608272 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 513 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 511 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 513 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 32704 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 32832 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 32704 # Total read bytes from the system interface side +system.physmem.bytesReadSys 32832 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 105 # Per bank write bursts system.physmem.perBankRdBursts::1 28 # Per bank write bursts -system.physmem.perBankRdBursts::2 53 # Per bank write bursts +system.physmem.perBankRdBursts::2 55 # Per bank write bursts system.physmem.perBankRdBursts::3 27 # Per bank write bursts system.physmem.perBankRdBursts::4 23 # Per bank write bursts system.physmem.perBankRdBursts::5 0 # Per bank write bursts @@ -76,14 +76,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 29058000 # Total gap between requests +system.physmem.totGap 29877000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 511 # Read request sizes (log2) +system.physmem.readPktSize::6 513 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -91,10 +91,10 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 298 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 149 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 51 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 9 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 282 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 156 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 58 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 13 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -187,310 +187,321 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 75 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 411.306667 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 274.853259 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 343.874505 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 13 17.33% 17.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 19 25.33% 42.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 12 16.00% 58.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 6 8.00% 66.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 5 6.67% 73.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 8 10.67% 84.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1 1.33% 85.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 11 14.67% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 75 # Bytes accessed per row activation -system.physmem.totQLat 3266500 # Total ticks spent queuing -system.physmem.totMemAccLat 12847750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2555000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6392.37 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 78 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 394.666667 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 253.933476 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 348.475070 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 17 21.79% 21.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 19 24.36% 46.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 12 15.38% 61.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 5 6.41% 67.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 5 6.41% 74.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1 1.28% 75.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 6 7.69% 83.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1 1.28% 84.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 12 15.38% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 78 # Bytes accessed per row activation +system.physmem.totQLat 6721500 # Total ticks spent queuing +system.physmem.totMemAccLat 16340250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2565000 # Total ticks spent in databus transfers +system.physmem.avgQLat 13102.34 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25142.37 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1124.25 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 31852.34 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1097.75 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1124.25 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1097.75 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 8.78 # Data bus utilization in percentage -system.physmem.busUtilRead 8.78 # Data bus utilization in percentage for reads +system.physmem.busUtil 8.58 # Data bus utilization in percentage +system.physmem.busUtilRead 8.58 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.54 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.64 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 427 # Number of row buffer hits during reads +system.physmem.readRowHits 424 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.56 # Row buffer hit rate for reads +system.physmem.readRowHitRate 82.65 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 56864.97 # Average gap between requests -system.physmem.pageHitRate 83.56 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 309960 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 169125 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 2113800 # Energy for read commands per rank (pJ) +system.physmem.avgGap 58239.77 # Average gap between requests +system.physmem.pageHitRate 82.65 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 357000 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 174570 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 2199120 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 16083405 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 63000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 20264970 # Total energy per rank (pJ) -system.physmem_0.averagePower 858.003493 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 22500 # Time in different power states +system.physmem_0.refreshEnergy 1843920.000000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 3642300 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 63360 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 9900900 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 16800 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 18197970 # Total energy per rank (pJ) +system.physmem_0.averagePower 608.449701 # Core power per rank (mW) +system.physmem_0.totalIdleTime 21617000 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 40500 # Time in different power states system.physmem_0.memoryStateTime::REF 780000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 22830000 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 241920 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 132000 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1396200 # Energy for read commands per rank (pJ) +system.physmem_0.memoryStateTime::SREF 0 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 44000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 7338500 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 21705500 # Time in different power states +system.physmem_1.actEnergy 278460 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 121440 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1463700 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 15332715 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 721500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 19350015 # Total energy per rank (pJ) -system.physmem_1.averagePower 819.264991 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 4570750 # Time in different power states +system.physmem_1.refreshEnergy 1843920.000000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 2522250 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 86880 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 10426440 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 493920 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 17237010 # Total energy per rank (pJ) +system.physmem_1.averagePower 576.319973 # Core power per rank (mW) +system.physmem_1.totalIdleTime 24154250 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 143000 # Time in different power states system.physmem_1.memoryStateTime::REF 780000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 21719750 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 29089500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 12614 # Number of BP lookups -system.cpu.branchPred.condPredicted 7656 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1475 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9453 # Number of BTB lookups +system.physmem_1.memoryStateTime::SREF 0 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 1286000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 4831250 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 22868250 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 29908500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 12304 # Number of BP lookups +system.cpu.branchPred.condPredicted 7429 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1435 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9156 # Number of BTB lookups system.cpu.branchPred.BTBHits 0 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 736 # Number of times the RAS was used to get a target. +system.cpu.branchPred.usedRAS 730 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 166 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 9453 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 1844 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 7609 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 897 # Number of mispredicted indirect branches. +system.cpu.branchPred.indirectLookups 9156 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 1824 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 7332 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 865 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.workload.num_syscalls 18 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 29089500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 58180 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 29908500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 59818 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 15554 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 59055 # Number of instructions fetch has processed -system.cpu.fetch.Branches 12614 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 2580 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 17529 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 3145 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 6 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1090 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 25 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 7530 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 720 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 35776 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.650688 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.904189 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 15502 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 57440 # Number of instructions fetch has processed +system.cpu.fetch.Branches 12304 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 2554 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 17524 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 3065 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1117 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 12 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 7446 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 730 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 35692 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.609324 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.874327 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 23025 64.36% 64.36% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 4506 12.60% 76.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 507 1.42% 78.37% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 451 1.26% 79.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 761 2.13% 81.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 707 1.98% 83.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 297 0.83% 84.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 355 0.99% 85.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 5167 14.44% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 23194 64.98% 64.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 4479 12.55% 77.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 496 1.39% 78.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 441 1.24% 80.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 761 2.13% 82.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 680 1.91% 84.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 284 0.80% 84.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 358 1.00% 85.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 4999 14.01% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 35776 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.216810 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.015040 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 12463 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 13012 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 7932 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 797 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1572 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 42051 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 1572 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 13239 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 1819 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 9760 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 7921 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 1465 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 37034 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 10 # Number of times rename has blocked due to IQ full -system.cpu.rename.SQFullEvents 1048 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 31990 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 66442 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 54845 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 35692 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.205691 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.960246 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 12333 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 13299 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 7732 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 796 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1532 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 41071 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 1532 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 13082 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 2036 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 9748 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 7750 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 1544 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 36233 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 13 # Number of times rename has blocked due to IQ full +system.cpu.rename.SQFullEvents 1128 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 31392 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 65112 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 53717 # Number of integer rename lookups system.cpu.rename.CommittedMaps 13819 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 18171 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 796 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 801 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 4352 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 4576 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 2920 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 15 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 11 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 28828 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 757 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 25362 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 118 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 15149 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 11337 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 282 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 35776 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.708911 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.503990 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 17573 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 793 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 793 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 4281 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 4496 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 2885 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 12 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 8 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 28450 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 744 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 25032 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 132 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 14758 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 10993 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 269 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 35692 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.701334 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.501806 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 26518 74.12% 74.12% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 3268 9.13% 83.26% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 1619 4.53% 87.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 1541 4.31% 92.09% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 1236 3.45% 95.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 752 2.10% 97.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 465 1.30% 98.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 277 0.77% 99.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 100 0.28% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 26613 74.56% 74.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 3169 8.88% 83.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 1586 4.44% 87.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 1525 4.27% 92.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 1197 3.35% 95.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 748 2.10% 97.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 484 1.36% 98.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 276 0.77% 99.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 94 0.26% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 35776 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 35692 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 154 52.56% 52.56% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 52.56% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 52.56% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 52.56% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 52.56% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 52.56% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 52.56% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 52.56% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 52.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 52.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 52.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 52.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 52.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 52.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 52.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 52.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 52.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 52.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 52.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 52.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 52.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 52.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 52.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 52.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 52.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 52.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 52.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 52.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 52.56% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 51 17.41% 69.97% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 88 30.03% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 164 53.07% 53.07% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 53.07% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 53.07% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 53.07% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 53.07% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 53.07% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 53.07% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 53.07% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 53.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 53.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 53.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 53.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 53.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 53.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 53.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 53.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 53.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 53.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 53.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 53.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 53.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 53.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 53.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 53.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 53.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 53.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 53.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 53.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 53.07% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 53 17.15% 70.23% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 92 29.77% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 18584 73.27% 73.27% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 73.27% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 73.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 73.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 73.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 73.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 73.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 73.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 73.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 73.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 73.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 73.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 73.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 73.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 73.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 73.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 73.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 73.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 73.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 73.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 73.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 73.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 73.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 73.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 73.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 73.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 73.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 73.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 73.27% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 4272 16.84% 90.12% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 2506 9.88% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 18346 73.29% 73.29% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 73.29% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 73.29% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 73.29% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 73.29% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 73.29% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 73.29% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 73.29% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 73.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 73.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 73.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 73.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 73.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 73.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 73.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 73.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 73.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 73.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 73.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 73.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 73.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 73.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 73.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 73.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 73.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 73.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 73.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 73.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 73.29% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 4185 16.72% 90.01% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 2501 9.99% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 25362 # Type of FU issued -system.cpu.iq.rate 0.435923 # Inst issue rate -system.cpu.iq.fu_busy_cnt 293 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.011553 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 86911 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 44761 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 22611 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 25032 # Type of FU issued +system.cpu.iq.rate 0.418469 # Inst issue rate +system.cpu.iq.fu_busy_cnt 309 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.012344 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 86197 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 43979 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 22374 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 25655 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 25341 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 33 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 32 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2351 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 2271 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 28 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1472 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 1437 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 26 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 22 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1572 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1852 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 15 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 31164 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 242 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 4576 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 2920 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 757 # Number of dispatched non-speculative instructions +system.cpu.iew.iewSquashCycles 1532 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 2073 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 16 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 30726 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 235 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 4496 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 2885 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 744 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 7 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 4 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 28 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 211 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1624 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1835 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 23718 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 3945 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1644 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 207 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1575 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1782 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 23436 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 3882 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1596 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1579 # number of nop insts executed -system.cpu.iew.exec_refs 6245 # number of memory reference insts executed -system.cpu.iew.exec_branches 5021 # Number of branches executed -system.cpu.iew.exec_stores 2300 # Number of stores executed -system.cpu.iew.exec_rate 0.407666 # Inst execution rate -system.cpu.iew.wb_sent 23107 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 22611 # cumulative count of insts written-back -system.cpu.iew.wb_producers 10526 # num instructions producing a value -system.cpu.iew.wb_consumers 13786 # num instructions consuming a value -system.cpu.iew.wb_rate 0.388639 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.763528 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 15913 # The number of squashed insts skipped by commit +system.cpu.iew.exec_nop 1532 # number of nop insts executed +system.cpu.iew.exec_refs 6191 # number of memory reference insts executed +system.cpu.iew.exec_branches 4986 # Number of branches executed +system.cpu.iew.exec_stores 2309 # Number of stores executed +system.cpu.iew.exec_rate 0.391788 # Inst execution rate +system.cpu.iew.wb_sent 22845 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 22374 # cumulative count of insts written-back +system.cpu.iew.wb_producers 10411 # num instructions producing a value +system.cpu.iew.wb_consumers 13650 # num instructions consuming a value +system.cpu.iew.wb_rate 0.374035 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.762711 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 15475 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 475 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1475 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 32637 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.464565 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.243420 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1435 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 32615 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.464878 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.257144 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 25892 79.33% 79.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 3639 11.15% 90.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 1211 3.71% 94.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 601 1.84% 96.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 338 1.04% 97.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 300 0.92% 97.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 374 1.15% 99.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 54 0.17% 99.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 228 0.70% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 25974 79.64% 79.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 3555 10.90% 90.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 1191 3.65% 94.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 577 1.77% 95.96% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 319 0.98% 96.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 311 0.95% 97.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 392 1.20% 99.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 57 0.17% 99.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 239 0.73% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 32637 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 32615 # Number of insts commited each cycle system.cpu.commit.committedInsts 15162 # Number of instructions committed system.cpu.commit.committedOps 15162 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -536,104 +547,104 @@ system.cpu.commit.op_class_0::MemWrite 1448 9.55% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 15162 # Class of committed instruction -system.cpu.commit.bw_lim_events 228 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 62661 # The number of ROB reads -system.cpu.rob.rob_writes 65377 # The number of ROB writes -system.cpu.timesIdled 196 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 22404 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 239 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 62190 # The number of ROB reads +system.cpu.rob.rob_writes 64431 # The number of ROB writes +system.cpu.timesIdled 194 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 24126 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 14436 # Number of Instructions Simulated system.cpu.committedOps 14436 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 4.030202 # CPI: Cycles Per Instruction -system.cpu.cpi_total 4.030202 # CPI: Total CPI of All Threads -system.cpu.ipc 0.248127 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.248127 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 36851 # number of integer regfile reads -system.cpu.int_regfile_writes 20552 # number of integer regfile writes -system.cpu.misc_regfile_reads 8143 # number of misc regfile reads +system.cpu.cpi 4.143669 # CPI: Cycles Per Instruction +system.cpu.cpi_total 4.143669 # CPI: Total CPI of All Threads +system.cpu.ipc 0.241332 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.241332 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 36480 # number of integer regfile reads +system.cpu.int_regfile_writes 20296 # number of integer regfile writes +system.cpu.misc_regfile_reads 8094 # number of misc regfile reads system.cpu.misc_regfile_writes 569 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 29089500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 29908500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 99.825953 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 4648 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 99.158435 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 4579 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 31.835616 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 31.363014 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 99.825953 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.024372 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.024372 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 99.158435 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.024209 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.024209 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 21 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 125 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 10540 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 10540 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 29089500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 3609 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 3609 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 10412 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 10412 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 29908500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 3540 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 3540 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 1033 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 1033 # number of WriteReq hits system.cpu.dcache.SwapReq_hits::cpu.data 6 # number of SwapReq hits system.cpu.dcache.SwapReq_hits::total 6 # number of SwapReq hits -system.cpu.dcache.demand_hits::cpu.data 4642 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 4642 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 4642 # number of overall hits -system.cpu.dcache.overall_hits::total 4642 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 140 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 140 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 4573 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 4573 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 4573 # number of overall hits +system.cpu.dcache.overall_hits::total 4573 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 145 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 145 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 409 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 409 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 549 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 549 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 549 # number of overall misses -system.cpu.dcache.overall_misses::total 549 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 9476500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 9476500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 27259981 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 27259981 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 36736481 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 36736481 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 36736481 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 36736481 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 3749 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 3749 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 554 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 554 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 554 # number of overall misses +system.cpu.dcache.overall_misses::total 554 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11443500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11443500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 29003985 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 29003985 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 40447485 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 40447485 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 40447485 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 40447485 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 3685 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 3685 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 1442 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SwapReq_accesses::cpu.data 6 # number of SwapReq accesses(hits+misses) system.cpu.dcache.SwapReq_accesses::total 6 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 5191 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 5191 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 5191 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 5191 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.037343 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.037343 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 5127 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 5127 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 5127 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 5127 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.039349 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.039349 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.283634 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.283634 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.105760 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.105760 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.105760 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.105760 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 67689.285714 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 67689.285714 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 66650.320293 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 66650.320293 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 66915.265938 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 66915.265938 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 66915.265938 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 66915.265938 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 1333 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.108055 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.108055 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.108055 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.108055 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 78920.689655 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 78920.689655 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70914.388753 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 70914.388753 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 73009.900722 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 73009.900722 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 73009.900722 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 73009.900722 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 1437 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 23 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 19 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 57.956522 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 75.631579 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 75 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 75 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 80 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 80 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 326 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 326 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 401 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 401 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 401 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 401 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 406 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 406 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 406 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 406 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 65 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 65 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 83 # number of WriteReq MSHR misses @@ -642,138 +653,138 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 148 system.cpu.dcache.demand_mshr_misses::total 148 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 148 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 148 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5190500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5190500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6454500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 6454500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11645000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 11645000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11645000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 11645000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017338 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017338 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6078000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6078000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6888000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 6888000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12966000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 12966000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12966000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12966000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017639 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017639 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.057559 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.057559 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.028511 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.028511 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028511 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.028511 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 79853.846154 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 79853.846154 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77765.060241 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77765.060241 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78682.432432 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 78682.432432 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78682.432432 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 78682.432432 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 29089500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.028867 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.028867 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028867 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.028867 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 93507.692308 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 93507.692308 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 82987.951807 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 82987.951807 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 87608.108108 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 87608.108108 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 87608.108108 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 87608.108108 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 29908500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 206.188252 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 6949 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 365 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 19.038356 # Average number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 204.747820 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 6856 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 367 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 18.681199 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 206.188252 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.100678 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.100678 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 365 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 90 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 204.747820 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.099975 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.099975 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 367 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 92 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 275 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.178223 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 15425 # Number of tag accesses -system.cpu.icache.tags.data_accesses 15425 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 29089500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 6949 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 6949 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 6949 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 6949 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 6949 # number of overall hits -system.cpu.icache.overall_hits::total 6949 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 581 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 581 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 581 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 581 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 581 # number of overall misses -system.cpu.icache.overall_misses::total 581 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 40938500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 40938500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 40938500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 40938500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 40938500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 40938500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 7530 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 7530 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 7530 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 7530 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 7530 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 7530 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.077158 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.077158 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.077158 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.077158 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.077158 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.077158 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70462.134251 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 70462.134251 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 70462.134251 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 70462.134251 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 70462.134251 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 70462.134251 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 194 # number of cycles access was blocked +system.cpu.icache.tags.occ_task_id_percent::1024 0.179199 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 15259 # Number of tag accesses +system.cpu.icache.tags.data_accesses 15259 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 29908500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 6856 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 6856 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 6856 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 6856 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 6856 # number of overall hits +system.cpu.icache.overall_hits::total 6856 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 590 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 590 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 590 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 590 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 590 # number of overall misses +system.cpu.icache.overall_misses::total 590 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 45891500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 45891500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 45891500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 45891500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 45891500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 45891500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 7446 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 7446 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 7446 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 7446 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 7446 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 7446 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.079237 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.079237 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.079237 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.079237 # 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number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 148 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 511 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5499000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5499000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 23777000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 23777000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4465500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4465500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 23777000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9964500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 33741500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 23777000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9964500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 33741500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::total 513 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5932500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5932500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 26034000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 26034000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5353000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5353000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 26034000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11285500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 37319500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 26034000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11285500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 37319500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.994521 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.994521 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.994550 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.994550 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.994521 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.994550 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.996101 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.994521 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.996117 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.994550 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.996101 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66253.012048 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66253.012048 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65501.377410 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65501.377410 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 68700 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 68700 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65501.377410 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67327.702703 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66030.332681 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65501.377410 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67327.702703 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66030.332681 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 513 # Total number of requests made to the snoop filter. +system.cpu.l2cache.overall_mshr_miss_rate::total 0.996117 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71475.903614 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71475.903614 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 71326.027397 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 71326.027397 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 82353.846154 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 82353.846154 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71326.027397 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 76253.378378 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72747.563353 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71326.027397 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 76253.378378 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72747.563353 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 515 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 2 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 29089500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 428 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 29908500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 430 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 83 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 83 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 365 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 367 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 65 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 730 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 734 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 294 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 1024 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23360 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 1028 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23488 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 32704 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 32832 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 513 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.003899 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.062378 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 515 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.003883 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.062257 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 511 99.61% 99.61% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 513 99.61% 99.61% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 2 0.39% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 513 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 256500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 515 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 257500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 547500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 1.9 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 550500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 1.8 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 219000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 511 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) +system.membus.snoop_filter.tot_requests 513 # Total number of requests made to the snoop filter. system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 29089500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 426 # Transaction distribution +system.membus.pwrStateResidencyTicks::UNDEFINED 29908500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 428 # Transaction distribution system.membus.trans_dist::ReadExReq 83 # Transaction distribution system.membus.trans_dist::ReadExResp 83 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 428 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1020 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1020 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 32576 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 32576 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 430 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1024 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1024 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 32704 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 32704 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 511 # Request fanout histogram +system.membus.snoop_fanout::samples 513 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 511 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 513 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 511 # Request fanout histogram -system.membus.reqLayer0.occupancy 623000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 513 # Request fanout histogram +system.membus.reqLayer0.occupancy 627500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 2693500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 9.3 # Layer utilization (%) +system.membus.respLayer1.occupancy 2707250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 9.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/config.ini b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/config.ini index 407eb5e1e..1efeb5f99 100644 --- a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/config.ini +++ b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/config.ini @@ -23,7 +23,7 @@ kernel_addr_check=true load_addr_mask=1099511627775 load_offset=0 mem_mode=timing -mem_ranges=0:536870911 +mem_ranges=0:536870911:0:0:0:0 memories=system.mem_ctrl mmap_using_noreserve=false multi_thread=false @@ -153,27 +153,27 @@ transition_latency=100000000 [system.mem_ctrl] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -193,6 +193,7 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 @@ -202,7 +203,7 @@ p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 page_policy=open_adaptive power_model=Null -range=0:536870911 +range=0:536870911:0:0:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 @@ -224,9 +225,9 @@ tRTW=2500 tWR=15000 tWTR=7500 tXAW=30000 -tXP=0 +tXP=6000 tXPDLL=0 -tXS=0 +tXS=270000 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 @@ -235,6 +236,7 @@ port=system.membus.master[0] [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -246,7 +248,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -254,3 +256,10 @@ width=16 master=system.mem_ctrl.port slave=system.cpu.icache_port system.cpu.dcache_port system.system_port +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + diff --git a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/simout b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/simout index 7b44dd5a2..4e8f563cb 100755 --- a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/simout +++ b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linu gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 19 2016 12:23:51 -gem5 started Jul 19 2016 12:24:26 -gem5 executing on e108600-lin, pid 39594 +gem5 compiled Oct 11 2016 00:00:58 +gem5 started Oct 13 2016 20:19:47 +gem5 executing on e108600-lin, pid 28091 command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-simple -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-simple Global frequency set at 1000000000000 ticks per second @@ -13,4 +13,4 @@ Beginning simulation! info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 405365000 because target called exit() +Exiting @ tick 461109000 because target called exit() diff --git a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/stats.txt b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/stats.txt index f8c482cd0..090f011e7 100644 --- a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000415 # Number of seconds simulated -sim_ticks 414695000 # Number of ticks simulated -final_tick 414695000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000461 # Number of seconds simulated +sim_ticks 461109000 # Number of ticks simulated +final_tick 461109000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 187951 # Simulator instruction rate (inst/s) -host_op_rate 187881 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 12069868237 # Simulator tick rate (ticks/s) -host_mem_usage 635076 # Number of bytes of host memory used +host_inst_rate 212686 # Simulator instruction rate (inst/s) +host_op_rate 212584 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 15184120914 # Simulator tick rate (ticks/s) +host_mem_usage 634004 # Number of bytes of host memory used host_seconds 0.03 # Real time elapsed on the host sim_insts 6453 # Number of instructions simulated sim_ops 6453 # Number of ops (including micro ops) simulated system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 414695000 # Cumulative time (in ticks) in various power states +system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 461109000 # Cumulative time (in ticks) in various power states system.mem_ctrl.bytes_read::cpu.inst 25852 # Number of bytes read from this memory system.mem_ctrl.bytes_read::cpu.data 8844 # Number of bytes read from this memory system.mem_ctrl.bytes_read::total 34696 # Number of bytes read from this memory @@ -26,63 +26,63 @@ system.mem_ctrl.num_reads::cpu.data 1190 # Nu system.mem_ctrl.num_reads::total 7653 # Number of read requests responded to by this memory system.mem_ctrl.num_writes::cpu.data 865 # Number of write requests responded to by this memory system.mem_ctrl.num_writes::total 865 # Number of write requests responded to by this memory -system.mem_ctrl.bw_read::cpu.inst 62339792 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::cpu.data 21326517 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::total 83666309 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::cpu.inst 62339792 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::total 62339792 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_write::cpu.data 16146807 # Write bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_write::total 16146807 # Write bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.inst 62339792 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.data 37473324 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::total 99813116 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_read::cpu.inst 56064835 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::cpu.data 19179847 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::total 75244682 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::cpu.inst 56064835 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::total 56064835 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_write::cpu.data 14521512 # Write bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_write::total 14521512 # Write bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.inst 56064835 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.data 33701359 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::total 89766194 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrl.readReqs 7654 # Number of read requests accepted system.mem_ctrl.writeReqs 865 # Number of write requests accepted system.mem_ctrl.readBursts 7654 # Number of DRAM read bursts, including those serviced by the write queue system.mem_ctrl.writeBursts 865 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrl.bytesReadDRAM 478016 # Total number of bytes read from DRAM -system.mem_ctrl.bytesReadWrQ 11840 # Total number of bytes read from write queue +system.mem_ctrl.bytesReadDRAM 477504 # Total number of bytes read from DRAM +system.mem_ctrl.bytesReadWrQ 12352 # Total number of bytes read from write queue system.mem_ctrl.bytesWritten 6144 # Total number of bytes written to DRAM system.mem_ctrl.bytesReadSys 34700 # Total read bytes from the system interface side system.mem_ctrl.bytesWrittenSys 6696 # Total written bytes from the system interface side -system.mem_ctrl.servicedByWrQ 185 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrl.mergedWrBursts 746 # Number of DRAM write bursts merged with an existing one +system.mem_ctrl.servicedByWrQ 193 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrl.mergedWrBursts 752 # Number of DRAM write bursts merged with an existing one system.mem_ctrl.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.mem_ctrl.perBankRdBursts::0 1736 # Per bank write bursts system.mem_ctrl.perBankRdBursts::1 393 # Per bank write bursts system.mem_ctrl.perBankRdBursts::2 768 # Per bank write bursts system.mem_ctrl.perBankRdBursts::3 800 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::4 766 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::4 764 # Per bank write bursts system.mem_ctrl.perBankRdBursts::5 293 # Per bank write bursts system.mem_ctrl.perBankRdBursts::6 6 # Per bank write bursts system.mem_ctrl.perBankRdBursts::7 26 # Per bank write bursts system.mem_ctrl.perBankRdBursts::8 0 # Per bank write bursts system.mem_ctrl.perBankRdBursts::9 1 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::10 257 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::10 249 # Per bank write bursts system.mem_ctrl.perBankRdBursts::11 578 # Per bank write bursts system.mem_ctrl.perBankRdBursts::12 167 # Per bank write bursts system.mem_ctrl.perBankRdBursts::13 1431 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::14 89 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::14 91 # Per bank write bursts system.mem_ctrl.perBankRdBursts::15 158 # Per bank write bursts system.mem_ctrl.perBankWrBursts::0 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::1 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::2 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::3 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::4 26 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::5 3 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::4 18 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::5 7 # Per bank write bursts system.mem_ctrl.perBankWrBursts::6 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::7 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::8 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::9 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::10 5 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::10 7 # Per bank write bursts system.mem_ctrl.perBankWrBursts::11 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::12 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::13 18 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::13 20 # Per bank write bursts system.mem_ctrl.perBankWrBursts::14 44 # Per bank write bursts system.mem_ctrl.perBankWrBursts::15 0 # Per bank write bursts system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrl.totGap 414618000 # Total gap between requests +system.mem_ctrl.totGap 461032000 # Total gap between requests system.mem_ctrl.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrl.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrl.readPktSize::2 6633 # Read request sizes (log2) @@ -97,7 +97,7 @@ system.mem_ctrl.writePktSize::3 809 # Wr system.mem_ctrl.writePktSize::4 0 # Write request sizes (log2) system.mem_ctrl.writePktSize::5 0 # Write request sizes (log2) system.mem_ctrl.writePktSize::6 0 # Write request sizes (log2) -system.mem_ctrl.rdQLenPdf::0 7469 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::0 7461 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::1 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::2 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::3 0 # What read queue length does an incoming req see @@ -146,12 +146,12 @@ system.mem_ctrl.wrQLenPdf::13 1 # Wh system.mem_ctrl.wrQLenPdf::14 1 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::15 1 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::16 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::17 7 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::18 7 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::19 7 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::20 7 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::21 7 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::22 7 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::17 6 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::18 6 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::19 6 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::20 6 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::21 6 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::22 6 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::23 6 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::24 6 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::25 6 # What write queue length does an incoming req see @@ -193,87 +193,95 @@ system.mem_ctrl.wrQLenPdf::60 0 # Wh system.mem_ctrl.wrQLenPdf::61 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrl.bytesPerActivate::samples 765 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::mean 630.044444 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::gmean 420.142008 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::stdev 402.263677 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::0-127 142 18.56% 18.56% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::128-255 72 9.41% 27.97% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::256-383 39 5.10% 33.07% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::384-511 50 6.54% 39.61% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::512-639 49 6.41% 46.01% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::640-767 26 3.40% 49.41% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::768-895 27 3.53% 52.94% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::896-1023 39 5.10% 58.04% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::1024-1151 321 41.96% 100.00% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::total 765 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::samples 766 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::mean 629.556136 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::gmean 420.481555 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::stdev 399.288519 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::0-127 144 18.80% 18.80% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::128-255 67 8.75% 27.55% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::256-383 42 5.48% 33.03% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::384-511 49 6.40% 39.43% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::512-639 40 5.22% 44.65% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::640-767 39 5.09% 49.74% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::768-895 38 4.96% 54.70% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::896-1023 34 4.44% 59.14% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::1024-1151 313 40.86% 100.00% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::total 766 # Bytes accessed per row activation system.mem_ctrl.rdPerTurnAround::samples 6 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::mean 1155.166667 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::gmean 1053.155116 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::stdev 490.786070 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::512-575 1 16.67% 16.67% # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::576-639 1 16.67% 33.33% # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::1152-1215 1 16.67% 50.00% # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::1280-1343 1 16.67% 66.67% # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::1408-1471 1 16.67% 83.33% # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::1728-1791 1 16.67% 100.00% # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::mean 1237 # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::gmean 1086.549947 # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::stdev 686.122730 # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::512-639 2 33.33% 33.33% # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::1152-1279 2 33.33% 66.67% # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::1408-1535 1 16.67% 83.33% # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::2304-2431 1 16.67% 100.00% # Reads before turning the bus around for writes system.mem_ctrl.rdPerTurnAround::total 6 # Reads before turning the bus around for writes system.mem_ctrl.wrPerTurnAround::samples 6 # Writes before turning the bus around for reads system.mem_ctrl.wrPerTurnAround::mean 16 # Writes before turning the bus around for reads system.mem_ctrl.wrPerTurnAround::gmean 16.000000 # Writes before turning the bus around for reads system.mem_ctrl.wrPerTurnAround::16 6 100.00% 100.00% # Writes before turning the bus around for reads system.mem_ctrl.wrPerTurnAround::total 6 # Writes before turning the bus around for reads -system.mem_ctrl.totQLat 26666250 # Total ticks spent queuing -system.mem_ctrl.totMemAccLat 166710000 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrl.totBusLat 37345000 # Total ticks spent in databus transfers -system.mem_ctrl.avgQLat 3570.26 # Average queueing delay per DRAM burst +system.mem_ctrl.totQLat 73323250 # Total ticks spent queuing +system.mem_ctrl.totMemAccLat 213217000 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrl.totBusLat 37305000 # Total ticks spent in databus transfers +system.mem_ctrl.avgQLat 9827.54 # Average queueing delay per DRAM burst system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.mem_ctrl.avgMemAccLat 22320.26 # Average memory access latency per DRAM burst -system.mem_ctrl.avgRdBW 1152.69 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrl.avgWrBW 14.82 # Average achieved write bandwidth in MiByte/s -system.mem_ctrl.avgRdBWSys 83.68 # Average system read bandwidth in MiByte/s -system.mem_ctrl.avgWrBWSys 16.15 # Average system write bandwidth in MiByte/s +system.mem_ctrl.avgMemAccLat 28577.54 # Average memory access latency per DRAM burst +system.mem_ctrl.avgRdBW 1035.56 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrl.avgWrBW 13.32 # Average achieved write bandwidth in MiByte/s +system.mem_ctrl.avgRdBWSys 75.25 # Average system read bandwidth in MiByte/s +system.mem_ctrl.avgWrBWSys 14.52 # Average system write bandwidth in MiByte/s system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrl.busUtil 9.12 # Data bus utilization in percentage -system.mem_ctrl.busUtilRead 9.01 # Data bus utilization in percentage for reads -system.mem_ctrl.busUtilWrite 0.12 # Data bus utilization in percentage for writes +system.mem_ctrl.busUtil 8.19 # Data bus utilization in percentage +system.mem_ctrl.busUtilRead 8.09 # Data bus utilization in percentage for reads +system.mem_ctrl.busUtilWrite 0.10 # Data bus utilization in percentage for writes system.mem_ctrl.avgRdQLen 1.00 # Average read queue length when enqueuing -system.mem_ctrl.avgWrQLen 22.92 # Average write queue length when enqueuing -system.mem_ctrl.readRowHits 6707 # Number of row buffer hits during reads -system.mem_ctrl.writeRowHits 88 # Number of row buffer hits during writes -system.mem_ctrl.readRowHitRate 89.80 # Row buffer hit rate for reads -system.mem_ctrl.writeRowHitRate 73.95 # Row buffer hit rate for writes -system.mem_ctrl.avgGap 48669.80 # Average gap between requests -system.mem_ctrl.pageHitRate 89.55 # Row buffer hit rate, read and write combined -system.mem_ctrl_0.actEnergy 3409560 # Energy for activate commands per rank (pJ) -system.mem_ctrl_0.preEnergy 1860375 # Energy for precharge commands per rank (pJ) -system.mem_ctrl_0.readEnergy 37159200 # Energy for read commands per rank (pJ) -system.mem_ctrl_0.writeEnergy 187920 # Energy for write commands per rank (pJ) -system.mem_ctrl_0.refreshEnergy 26953680 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_0.actBackEnergy 262129320 # Energy for active background per rank (pJ) -system.mem_ctrl_0.preBackEnergy 17820750 # Energy for precharge background per rank (pJ) -system.mem_ctrl_0.totalEnergy 349520805 # Total energy per rank (pJ) -system.mem_ctrl_0.averagePower 846.438251 # Core power per rank (mW) -system.mem_ctrl_0.memoryStateTime::IDLE 26708250 # Time in different power states -system.mem_ctrl_0.memoryStateTime::REF 13780000 # Time in different power states -system.mem_ctrl_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrl_0.memoryStateTime::ACT 372456750 # Time in different power states -system.mem_ctrl_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrl_1.actEnergy 2373840 # Energy for activate commands per rank (pJ) -system.mem_ctrl_1.preEnergy 1295250 # Energy for precharge commands per rank (pJ) -system.mem_ctrl_1.readEnergy 20833800 # Energy for read commands per rank (pJ) -system.mem_ctrl_1.writeEnergy 434160 # Energy for write commands per rank (pJ) -system.mem_ctrl_1.refreshEnergy 26953680 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_1.actBackEnergy 231001335 # Energy for active background per rank (pJ) -system.mem_ctrl_1.preBackEnergy 45144000 # Energy for precharge background per rank (pJ) -system.mem_ctrl_1.totalEnergy 328036065 # Total energy per rank (pJ) -system.mem_ctrl_1.averagePower 794.350717 # Core power per rank (mW) -system.mem_ctrl_1.memoryStateTime::IDLE 73389500 # Time in different power states -system.mem_ctrl_1.memoryStateTime::REF 13780000 # Time in different power states -system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrl_1.memoryStateTime::ACT 325838500 # Time in different power states -system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 414695000 # Cumulative time (in ticks) in various power states +system.mem_ctrl.avgWrQLen 23.97 # Average write queue length when enqueuing +system.mem_ctrl.readRowHits 6701 # Number of row buffer hits during reads +system.mem_ctrl.writeRowHits 86 # Number of row buffer hits during writes +system.mem_ctrl.readRowHitRate 89.81 # Row buffer hit rate for reads +system.mem_ctrl.writeRowHitRate 76.11 # Row buffer hit rate for writes +system.mem_ctrl.avgGap 54118.09 # Average gap between requests +system.mem_ctrl.pageHitRate 89.61 # Row buffer hit rate, read and write combined +system.mem_ctrl_0.actEnergy 3184440 # Energy for activate commands per rank (pJ) +system.mem_ctrl_0.preEnergy 1681185 # Energy for precharge commands per rank (pJ) +system.mem_ctrl_0.readEnergy 34164900 # Energy for read commands per rank (pJ) +system.mem_ctrl_0.writeEnergy 130500 # Energy for write commands per rank (pJ) +system.mem_ctrl_0.refreshEnergy 36263760.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrl_0.actBackEnergy 65335680 # Energy for active background per rank (pJ) +system.mem_ctrl_0.preBackEnergy 1899360 # Energy for precharge background per rank (pJ) +system.mem_ctrl_0.actPowerDownEnergy 128211240 # Energy for active power-down per rank (pJ) +system.mem_ctrl_0.prePowerDownEnergy 12180000 # Energy for precharge power-down per rank (pJ) +system.mem_ctrl_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrl_0.totalEnergy 283051065 # Total energy per rank (pJ) +system.mem_ctrl_0.averagePower 613.847162 # Core power per rank (mW) +system.mem_ctrl_0.totalIdleTime 312833500 # Total Idle time Per DRAM Rank +system.mem_ctrl_0.memoryStateTime::IDLE 882000 # Time in different power states +system.mem_ctrl_0.memoryStateTime::REF 15340000 # Time in different power states +system.mem_ctrl_0.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrl_0.memoryStateTime::PRE_PDN 31715250 # Time in different power states +system.mem_ctrl_0.memoryStateTime::ACT 132053500 # Time in different power states +system.mem_ctrl_0.memoryStateTime::ACT_PDN 281118250 # Time in different power states +system.mem_ctrl_1.actEnergy 2313360 # Energy for activate commands per rank (pJ) +system.mem_ctrl_1.preEnergy 1225785 # Energy for precharge commands per rank (pJ) +system.mem_ctrl_1.readEnergy 19099500 # Energy for read commands per rank (pJ) +system.mem_ctrl_1.writeEnergy 370620 # Energy for write commands per rank (pJ) +system.mem_ctrl_1.refreshEnergy 35649120.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrl_1.actBackEnergy 44402430 # Energy for active background per rank (pJ) +system.mem_ctrl_1.preBackEnergy 1287360 # Energy for precharge background per rank (pJ) +system.mem_ctrl_1.actPowerDownEnergy 129142620 # Energy for active power-down per rank (pJ) +system.mem_ctrl_1.prePowerDownEnergy 18055680 # Energy for precharge power-down per rank (pJ) +system.mem_ctrl_1.selfRefreshEnergy 8894220 # Energy for self refresh per rank (pJ) +system.mem_ctrl_1.totalEnergy 260440695 # Total energy per rank (pJ) +system.mem_ctrl_1.averagePower 564.812507 # Core power per rank (mW) +system.mem_ctrl_1.totalIdleTime 359701750 # Total Idle time Per DRAM Rank +system.mem_ctrl_1.memoryStateTime::IDLE 1420000 # Time in different power states +system.mem_ctrl_1.memoryStateTime::REF 15098000 # Time in different power states +system.mem_ctrl_1.memoryStateTime::SREF 30156500 # Time in different power states +system.mem_ctrl_1.memoryStateTime::PRE_PDN 47020500 # Time in different power states +system.mem_ctrl_1.memoryStateTime::ACT 84176750 # Time in different power states +system.mem_ctrl_1.memoryStateTime::ACT_PDN 283237250 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 461109000 # Cumulative time (in ticks) in various power states system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -307,8 +315,8 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 414695000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 414695 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 461109000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 461109 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 6453 # Number of instructions committed @@ -327,7 +335,7 @@ system.cpu.num_mem_refs 2065 # nu system.cpu.num_load_insts 1197 # Number of load instructions system.cpu.num_store_insts 868 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 414695 # Number of busy cycles +system.cpu.num_busy_cycles 461109 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 1060 # Number of branches fetched @@ -372,7 +380,7 @@ system.membus.snoop_filter.hit_multi_requests 0 system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 414695000 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 461109000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 7654 # Transaction distribution system.membus.trans_dist::ReadResp 7653 # Transaction distribution system.membus.trans_dist::WriteReq 865 # Transaction distribution @@ -396,10 +404,10 @@ system.membus.snoop_fanout::min_value 0 # Re system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 8519 # Request fanout histogram system.membus.reqLayer0.occupancy 9384000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.3 # Layer utilization (%) -system.membus.respLayer0.occupancy 14691750 # Layer occupancy (ticks) -system.membus.respLayer0.utilization 3.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 3578000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.9 # Layer utilization (%) +system.membus.reqLayer0.utilization 2.0 # Layer utilization (%) +system.membus.respLayer0.occupancy 14690000 # Layer occupancy (ticks) +system.membus.respLayer0.utilization 3.2 # Layer utilization (%) +system.membus.respLayer1.occupancy 3572750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.8 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/config.ini b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/config.ini index f8108d4cd..5a1f94c78 100644 --- a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/config.ini +++ b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/config.ini @@ -23,7 +23,7 @@ kernel_addr_check=true load_addr_mask=1099511627775 load_offset=0 mem_mode=timing -mem_ranges=0:536870911 +mem_ranges=0:536870911:0:0:0:0 memories=system.mem_ctrl mmap_using_noreserve=false multi_thread=false @@ -100,7 +100,7 @@ icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.clk_domain clusivity=mostly_incl @@ -151,7 +151,7 @@ size=64 [system.cpu.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.clk_domain clusivity=mostly_incl @@ -275,7 +275,7 @@ system=system [system.l2cache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.clk_domain clusivity=mostly_incl @@ -320,27 +320,27 @@ size=262144 [system.mem_ctrl] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -360,6 +360,7 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 @@ -369,7 +370,7 @@ p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 page_policy=open_adaptive power_model=Null -range=0:536870911 +range=0:536870911:0:0:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 @@ -391,9 +392,9 @@ tRTW=2500 tWR=15000 tWTR=7500 tXAW=30000 -tXP=0 +tXP=6000 tXPDLL=0 -tXS=0 +tXS=270000 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 @@ -402,6 +403,7 @@ port=system.membus.master[0] [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -413,7 +415,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -421,3 +423,10 @@ width=16 master=system.mem_ctrl.port slave=system.l2cache.mem_side system.system_port +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + diff --git a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/simout b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/simout index 7505aca67..2e75b8af5 100755 --- a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/simout +++ b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linu gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 19 2016 12:23:51 -gem5 started Jul 19 2016 12:24:26 -gem5 executing on e108600-lin, pid 39597 +gem5 compiled Oct 11 2016 00:00:58 +gem5 started Oct 13 2016 20:19:46 +gem5 executing on e108600-lin, pid 28074 command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-two-level -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-two-level Global frequency set at 1000000000000 ticks per second @@ -13,4 +13,4 @@ Beginning simulation! info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 61470000 because target called exit() +Exiting @ tick 64758000 because target called exit() diff --git a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/stats.txt b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/stats.txt index 1f58ca472..47755a477 100644 --- a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000062 # Number of seconds simulated -sim_ticks 62213000 # Number of ticks simulated -final_tick 62213000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000065 # Number of seconds simulated +sim_ticks 64758000 # Number of ticks simulated +final_tick 64758000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 276862 # Simulator instruction rate (inst/s) -host_op_rate 276760 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2667377590 # Simulator tick rate (ticks/s) -host_mem_usage 639424 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host +host_inst_rate 560678 # Simulator instruction rate (inst/s) +host_op_rate 559951 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5612828222 # Simulator tick rate (ticks/s) +host_mem_usage 638096 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 6453 # Number of instructions simulated sim_ops 6453 # Number of ops (including micro ops) simulated system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 62213000 # Cumulative time (in ticks) in various power states +system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 64758000 # Cumulative time (in ticks) in various power states system.mem_ctrl.bytes_read::cpu.inst 17792 # Number of bytes read from this memory system.mem_ctrl.bytes_read::cpu.data 10752 # Number of bytes read from this memory system.mem_ctrl.bytes_read::total 28544 # Number of bytes read from this memory @@ -22,14 +22,14 @@ system.mem_ctrl.bytes_inst_read::total 17792 # Nu system.mem_ctrl.num_reads::cpu.inst 278 # Number of read requests responded to by this memory system.mem_ctrl.num_reads::cpu.data 168 # Number of read requests responded to by this memory system.mem_ctrl.num_reads::total 446 # Number of read requests responded to by this memory -system.mem_ctrl.bw_read::cpu.inst 285985244 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::cpu.data 172825615 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::total 458810859 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::cpu.inst 285985244 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::total 285985244 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.inst 285985244 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.data 172825615 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::total 458810859 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_read::cpu.inst 274745977 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::cpu.data 166033540 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::total 440779518 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::cpu.inst 274745977 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::total 274745977 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.inst 274745977 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.data 166033540 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::total 440779518 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrl.readReqs 446 # Number of read requests accepted system.mem_ctrl.writeReqs 0 # Number of write requests accepted system.mem_ctrl.readBursts 446 # Number of DRAM read bursts, including those serviced by the write queue @@ -76,7 +76,7 @@ system.mem_ctrl.perBankWrBursts::14 0 # Pe system.mem_ctrl.perBankWrBursts::15 0 # Per bank write bursts system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrl.totGap 61962000 # Total gap between requests +system.mem_ctrl.totGap 64501000 # Total gap between requests system.mem_ctrl.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrl.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrl.readPktSize::2 0 # Read request sizes (log2) @@ -187,70 +187,80 @@ system.mem_ctrl.wrQLenPdf::60 0 # Wh system.mem_ctrl.wrQLenPdf::61 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrl.bytesPerActivate::samples 95 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::mean 270.147368 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::gmean 185.768755 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::stdev 255.860208 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::0-127 22 23.16% 23.16% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::128-255 36 37.89% 61.05% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::256-383 14 14.74% 75.79% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::384-511 5 5.26% 81.05% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::512-639 6 6.32% 87.37% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::640-767 6 6.32% 93.68% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::768-895 1 1.05% 94.74% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::1024-1151 5 5.26% 100.00% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::total 95 # Bytes accessed per row activation -system.mem_ctrl.totQLat 3590750 # Total ticks spent queuing -system.mem_ctrl.totMemAccLat 11953250 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrl.bytesPerActivate::samples 105 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::mean 264.533333 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::gmean 181.831163 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::stdev 249.307389 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::0-127 27 25.71% 25.71% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::128-255 40 38.10% 63.81% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::256-383 10 9.52% 73.33% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::384-511 9 8.57% 81.90% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::512-639 7 6.67% 88.57% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::640-767 6 5.71% 94.29% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::768-895 1 0.95% 95.24% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::1024-1151 5 4.76% 100.00% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::total 105 # Bytes accessed per row activation +system.mem_ctrl.totQLat 6134000 # Total ticks spent queuing +system.mem_ctrl.totMemAccLat 14496500 # Total ticks spent from burst creation until serviced by the DRAM system.mem_ctrl.totBusLat 2230000 # Total ticks spent in databus transfers -system.mem_ctrl.avgQLat 8051.01 # Average queueing delay per DRAM burst +system.mem_ctrl.avgQLat 13753.36 # Average queueing delay per DRAM burst system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.mem_ctrl.avgMemAccLat 26801.01 # Average memory access latency per DRAM burst -system.mem_ctrl.avgRdBW 458.81 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrl.avgMemAccLat 32503.36 # Average memory access latency per DRAM burst +system.mem_ctrl.avgRdBW 440.78 # Average DRAM read bandwidth in MiByte/s system.mem_ctrl.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.mem_ctrl.avgRdBWSys 458.81 # Average system read bandwidth in MiByte/s +system.mem_ctrl.avgRdBWSys 440.78 # Average system read bandwidth in MiByte/s system.mem_ctrl.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrl.busUtil 3.58 # Data bus utilization in percentage -system.mem_ctrl.busUtilRead 3.58 # Data bus utilization in percentage for reads +system.mem_ctrl.busUtil 3.44 # Data bus utilization in percentage +system.mem_ctrl.busUtilRead 3.44 # Data bus utilization in percentage for reads system.mem_ctrl.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.mem_ctrl.avgRdQLen 1.00 # Average read queue length when enqueuing system.mem_ctrl.avgWrQLen 0.00 # Average write queue length when enqueuing -system.mem_ctrl.readRowHits 340 # Number of row buffer hits during reads +system.mem_ctrl.readRowHits 337 # Number of row buffer hits during reads system.mem_ctrl.writeRowHits 0 # Number of row buffer hits during writes -system.mem_ctrl.readRowHitRate 76.23 # Row buffer hit rate for reads +system.mem_ctrl.readRowHitRate 75.56 # Row buffer hit rate for reads system.mem_ctrl.writeRowHitRate nan # Row buffer hit rate for writes -system.mem_ctrl.avgGap 138928.25 # Average gap between requests -system.mem_ctrl.pageHitRate 76.23 # Row buffer hit rate, read and write combined -system.mem_ctrl_0.actEnergy 309960 # Energy for activate commands per rank (pJ) -system.mem_ctrl_0.preEnergy 169125 # Energy for precharge commands per rank (pJ) -system.mem_ctrl_0.readEnergy 1583400 # Energy for read commands per rank (pJ) +system.mem_ctrl.avgGap 144621.08 # Average gap between requests +system.mem_ctrl.pageHitRate 75.56 # Row buffer hit rate, read and write combined +system.mem_ctrl_0.actEnergy 314160 # Energy for activate commands per rank (pJ) +system.mem_ctrl_0.preEnergy 163185 # Energy for precharge commands per rank (pJ) +system.mem_ctrl_0.readEnergy 1542240 # Energy for read commands per rank (pJ) system.mem_ctrl_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.mem_ctrl_0.refreshEnergy 3559920 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_0.actBackEnergy 37021500 # Energy for active background per rank (pJ) -system.mem_ctrl_0.preBackEnergy 383250 # Energy for precharge background per rank (pJ) -system.mem_ctrl_0.totalEnergy 43027155 # Total energy per rank (pJ) -system.mem_ctrl_0.averagePower 785.686791 # Core power per rank (mW) -system.mem_ctrl_0.memoryStateTime::IDLE 966000 # Time in different power states -system.mem_ctrl_0.memoryStateTime::REF 1820000 # Time in different power states -system.mem_ctrl_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrl_0.memoryStateTime::ACT 52514000 # Time in different power states -system.mem_ctrl_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrl_1.actEnergy 370440 # Energy for activate commands per rank (pJ) -system.mem_ctrl_1.preEnergy 202125 # Energy for precharge commands per rank (pJ) -system.mem_ctrl_1.readEnergy 1466400 # Energy for read commands per rank (pJ) +system.mem_ctrl_0.refreshEnergy 4917120.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrl_0.actBackEnergy 3812160 # Energy for active background per rank (pJ) +system.mem_ctrl_0.preBackEnergy 131040 # Energy for precharge background per rank (pJ) +system.mem_ctrl_0.actPowerDownEnergy 22575420 # Energy for active power-down per rank (pJ) +system.mem_ctrl_0.prePowerDownEnergy 2515200 # Energy for precharge power-down per rank (pJ) +system.mem_ctrl_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrl_0.totalEnergy 35970525 # Total energy per rank (pJ) +system.mem_ctrl_0.averagePower 555.454282 # Core power per rank (mW) +system.mem_ctrl_0.totalIdleTime 55623250 # Total Idle time Per DRAM Rank +system.mem_ctrl_0.memoryStateTime::IDLE 77000 # Time in different power states +system.mem_ctrl_0.memoryStateTime::REF 2080000 # Time in different power states +system.mem_ctrl_0.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrl_0.memoryStateTime::PRE_PDN 6549500 # Time in different power states +system.mem_ctrl_0.memoryStateTime::ACT 6531250 # Time in different power states +system.mem_ctrl_0.memoryStateTime::ACT_PDN 49520250 # Time in different power states +system.mem_ctrl_1.actEnergy 464100 # Energy for activate commands per rank (pJ) +system.mem_ctrl_1.preEnergy 235290 # Energy for precharge commands per rank (pJ) +system.mem_ctrl_1.readEnergy 1642200 # Energy for read commands per rank (pJ) system.mem_ctrl_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.mem_ctrl_1.refreshEnergy 3559920 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_1.actBackEnergy 35989515 # Energy for active background per rank (pJ) -system.mem_ctrl_1.preBackEnergy 1288500 # Energy for precharge background per rank (pJ) -system.mem_ctrl_1.totalEnergy 42876900 # Total energy per rank (pJ) -system.mem_ctrl_1.averagePower 782.943096 # Core power per rank (mW) -system.mem_ctrl_1.memoryStateTime::IDLE 1815750 # Time in different power states -system.mem_ctrl_1.memoryStateTime::REF 1820000 # Time in different power states -system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrl_1.memoryStateTime::ACT 51141750 # Time in different power states -system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 62213000 # Cumulative time (in ticks) in various power states +system.mem_ctrl_1.refreshEnergy 4917120.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrl_1.actBackEnergy 4174680 # Energy for active background per rank (pJ) +system.mem_ctrl_1.preBackEnergy 251520 # Energy for precharge background per rank (pJ) +system.mem_ctrl_1.actPowerDownEnergy 24338430 # Energy for active power-down per rank (pJ) +system.mem_ctrl_1.prePowerDownEnergy 604800 # Energy for precharge power-down per rank (pJ) +system.mem_ctrl_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrl_1.totalEnergy 36628140 # Total energy per rank (pJ) +system.mem_ctrl_1.averagePower 565.609126 # Core power per rank (mW) +system.mem_ctrl_1.totalIdleTime 54728750 # Total Idle time Per DRAM Rank +system.mem_ctrl_1.memoryStateTime::IDLE 283000 # Time in different power states +system.mem_ctrl_1.memoryStateTime::REF 2080000 # Time in different power states +system.mem_ctrl_1.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrl_1.memoryStateTime::PRE_PDN 1573250 # Time in different power states +system.mem_ctrl_1.memoryStateTime::ACT 7457000 # Time in different power states +system.mem_ctrl_1.memoryStateTime::ACT_PDN 53364750 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 64758000 # Cumulative time (in ticks) in various power states system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -284,8 +294,8 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 62213000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 62213 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 64758000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 64758 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 6453 # Number of instructions committed @@ -304,7 +314,7 @@ system.cpu.num_mem_refs 2065 # nu system.cpu.num_load_insts 1197 # Number of load instructions system.cpu.num_store_insts 868 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 62213 # Number of busy cycles +system.cpu.num_busy_cycles 64758 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 1060 # Number of branches fetched @@ -343,23 +353,23 @@ system.cpu.op_class::MemWrite 868 13.43% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 6463 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 62213000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 64758000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 104.646393 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 104.399751 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1887 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 168 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 11.232143 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 104.646393 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.102194 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.102194 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 104.399751 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.101953 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.101953 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 168 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 12 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 156 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.164062 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 4278 # Number of tag accesses system.cpu.dcache.tags.data_accesses 4278 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 62213000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 64758000 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 1095 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1095 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 792 # number of WriteReq hits @@ -376,14 +386,14 @@ system.cpu.dcache.demand_misses::cpu.data 168 # n system.cpu.dcache.demand_misses::total 168 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 168 # number of overall misses system.cpu.dcache.overall_misses::total 168 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 9887000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 9887000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 7630000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 7630000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 17517000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 17517000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 17517000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 17517000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 10261000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 10261000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 7802000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 7802000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 18063000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 18063000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 18063000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 18063000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1190 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1190 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) @@ -400,14 +410,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.081752 system.cpu.dcache.demand_miss_rate::total 0.081752 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.081752 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.081752 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 104073.684211 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 104073.684211 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 104520.547945 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 104520.547945 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 104267.857143 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 104267.857143 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 104267.857143 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 104267.857143 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 108010.526316 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 108010.526316 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 106876.712329 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 106876.712329 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 107517.857143 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 107517.857143 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 107517.857143 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 107517.857143 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -422,14 +432,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 168 system.cpu.dcache.demand_mshr_misses::total 168 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 168 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9697000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 9697000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7484000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 7484000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 17181000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 17181000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 17181000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 17181000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10071000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 10071000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7656000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 7656000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 17727000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 17727000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 17727000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 17727000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.079832 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.079832 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses @@ -438,31 +448,31 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.081752 system.cpu.dcache.demand_mshr_miss_rate::total 0.081752 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.081752 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.081752 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 102073.684211 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 102073.684211 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 102520.547945 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 102520.547945 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 102267.857143 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 102267.857143 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 102267.857143 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 102267.857143 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 62213000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 106010.526316 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 106010.526316 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 104876.712329 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 104876.712329 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 105517.857143 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 105517.857143 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 105517.857143 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 105517.857143 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 64758000 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 62 # number of replacements -system.cpu.icache.tags.tagsinuse 113.718871 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 113.445692 # Cycle average of tags in use system.cpu.icache.tags.total_refs 6183 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 281 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 22.003559 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 113.718871 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.444214 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.444214 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 113.445692 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.443147 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.443147 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 219 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 167 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.855469 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 13209 # Number of tag accesses system.cpu.icache.tags.data_accesses 13209 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 62213000 # Cumulative time (in ticks) in various power states +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 64758000 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 6183 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 6183 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 6183 # number of demand (read+write) hits @@ -475,12 +485,12 @@ system.cpu.icache.demand_misses::cpu.inst 281 # n system.cpu.icache.demand_misses::total 281 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 281 # number of overall misses system.cpu.icache.overall_misses::total 281 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 28558000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 28558000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 28558000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 28558000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 28558000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 28558000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 30557000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 30557000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 30557000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 30557000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 30557000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 30557000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 6464 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 6464 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 6464 # number of demand (read+write) accesses @@ -493,12 +503,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.043472 system.cpu.icache.demand_miss_rate::total 0.043472 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.043472 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.043472 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 101629.893238 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 101629.893238 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 101629.893238 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 101629.893238 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 101629.893238 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 101629.893238 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 108743.772242 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 108743.772242 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 108743.772242 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 108743.772242 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 108743.772242 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 108743.772242 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -511,31 +521,31 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 281 system.cpu.icache.demand_mshr_misses::total 281 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 281 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 281 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 27996000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 27996000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 27996000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 27996000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 27996000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 27996000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 29995000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 29995000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 29995000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 29995000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 29995000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 29995000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.043472 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.043472 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.043472 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.043472 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.043472 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.043472 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 99629.893238 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 99629.893238 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 99629.893238 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 99629.893238 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 99629.893238 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 99629.893238 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 106743.772242 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 106743.772242 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 106743.772242 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 106743.772242 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 106743.772242 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 106743.772242 # average overall mshr miss latency system.l2bus.snoop_filter.tot_requests 511 # Total number of requests made to the snoop filter. system.l2bus.snoop_filter.hit_single_requests 63 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.l2bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.l2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.l2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.l2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.l2bus.pwrStateResidencyTicks::UNDEFINED 62213000 # Cumulative time (in ticks) in various power states +system.l2bus.pwrStateResidencyTicks::UNDEFINED 64758000 # Cumulative time (in ticks) in various power states system.l2bus.trans_dist::ReadResp 376 # Transaction distribution system.l2bus.trans_dist::CleanEvict 62 # Transaction distribution system.l2bus.trans_dist::ReadExReq 73 # Transaction distribution @@ -563,28 +573,28 @@ system.l2bus.snoop_fanout::total 449 # Re system.l2bus.reqLayer0.occupancy 511000 # Layer occupancy (ticks) system.l2bus.reqLayer0.utilization 0.8 # Layer utilization (%) system.l2bus.respLayer0.occupancy 843000 # Layer occupancy (ticks) -system.l2bus.respLayer0.utilization 1.4 # Layer utilization (%) +system.l2bus.respLayer0.utilization 1.3 # Layer utilization (%) system.l2bus.respLayer1.occupancy 504000 # Layer occupancy (ticks) system.l2bus.respLayer1.utilization 0.8 # Layer utilization (%) -system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 62213000 # Cumulative time (in ticks) in various power states +system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 64758000 # Cumulative time (in ticks) in various power states system.l2cache.tags.replacements 0 # number of replacements -system.l2cache.tags.tagsinuse 233.175851 # Cycle average of tags in use +system.l2cache.tags.tagsinuse 232.606847 # Cycle average of tags in use system.l2cache.tags.total_refs 65 # Total number of references to valid blocks. system.l2cache.tags.sampled_refs 446 # Sample count of references to valid blocks. system.l2cache.tags.avg_refs 0.145740 # Average number of references to valid blocks. system.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2cache.tags.occ_blocks::cpu.inst 128.472749 # Average occupied blocks per requestor -system.l2cache.tags.occ_blocks::cpu.data 104.703102 # Average occupied blocks per requestor -system.l2cache.tags.occ_percent::cpu.inst 0.031365 # Average percentage of cache occupancy -system.l2cache.tags.occ_percent::cpu.data 0.025562 # Average percentage of cache occupancy -system.l2cache.tags.occ_percent::total 0.056928 # Average percentage of cache occupancy +system.l2cache.tags.occ_blocks::cpu.inst 128.152617 # Average occupied blocks per requestor +system.l2cache.tags.occ_blocks::cpu.data 104.454231 # Average occupied blocks per requestor +system.l2cache.tags.occ_percent::cpu.inst 0.031287 # Average percentage of cache occupancy +system.l2cache.tags.occ_percent::cpu.data 0.025502 # Average percentage of cache occupancy +system.l2cache.tags.occ_percent::total 0.056789 # Average percentage of cache occupancy system.l2cache.tags.occ_task_id_blocks::1024 446 # Occupied blocks per task id system.l2cache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id system.l2cache.tags.age_task_id_blocks_1024::1 384 # Occupied blocks per task id system.l2cache.tags.occ_task_id_percent::1024 0.108887 # Percentage of cache occupancy per task id system.l2cache.tags.tag_accesses 4534 # Number of tag accesses system.l2cache.tags.data_accesses 4534 # Number of data accesses -system.l2cache.pwrStateResidencyTicks::UNDEFINED 62213000 # Cumulative time (in ticks) in various power states +system.l2cache.pwrStateResidencyTicks::UNDEFINED 64758000 # Cumulative time (in ticks) in various power states system.l2cache.ReadSharedReq_hits::cpu.inst 3 # number of ReadSharedReq hits system.l2cache.ReadSharedReq_hits::total 3 # number of ReadSharedReq hits system.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits @@ -602,17 +612,17 @@ system.l2cache.demand_misses::total 446 # nu system.l2cache.overall_misses::cpu.inst 278 # number of overall misses system.l2cache.overall_misses::cpu.data 168 # number of overall misses system.l2cache.overall_misses::total 446 # number of overall misses -system.l2cache.ReadExReq_miss_latency::cpu.data 7265000 # number of ReadExReq miss cycles -system.l2cache.ReadExReq_miss_latency::total 7265000 # number of ReadExReq miss cycles -system.l2cache.ReadSharedReq_miss_latency::cpu.inst 27088000 # number of ReadSharedReq miss cycles -system.l2cache.ReadSharedReq_miss_latency::cpu.data 9412000 # number of ReadSharedReq miss cycles -system.l2cache.ReadSharedReq_miss_latency::total 36500000 # number of ReadSharedReq miss cycles -system.l2cache.demand_miss_latency::cpu.inst 27088000 # number of demand (read+write) miss cycles -system.l2cache.demand_miss_latency::cpu.data 16677000 # number of demand (read+write) miss cycles -system.l2cache.demand_miss_latency::total 43765000 # number of demand (read+write) miss cycles -system.l2cache.overall_miss_latency::cpu.inst 27088000 # number of overall miss cycles -system.l2cache.overall_miss_latency::cpu.data 16677000 # number of overall miss cycles -system.l2cache.overall_miss_latency::total 43765000 # number of overall miss cycles +system.l2cache.ReadExReq_miss_latency::cpu.data 7437000 # number of ReadExReq miss cycles +system.l2cache.ReadExReq_miss_latency::total 7437000 # number of ReadExReq miss cycles +system.l2cache.ReadSharedReq_miss_latency::cpu.inst 29087000 # number of ReadSharedReq miss cycles +system.l2cache.ReadSharedReq_miss_latency::cpu.data 9786000 # number of ReadSharedReq miss cycles +system.l2cache.ReadSharedReq_miss_latency::total 38873000 # number of ReadSharedReq miss cycles +system.l2cache.demand_miss_latency::cpu.inst 29087000 # number of demand (read+write) miss cycles +system.l2cache.demand_miss_latency::cpu.data 17223000 # number of demand (read+write) miss cycles +system.l2cache.demand_miss_latency::total 46310000 # number of demand (read+write) miss cycles +system.l2cache.overall_miss_latency::cpu.inst 29087000 # number of overall miss cycles +system.l2cache.overall_miss_latency::cpu.data 17223000 # number of overall miss cycles +system.l2cache.overall_miss_latency::total 46310000 # number of overall miss cycles system.l2cache.ReadExReq_accesses::cpu.data 73 # number of ReadExReq accesses(hits+misses) system.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses) system.l2cache.ReadSharedReq_accesses::cpu.inst 281 # number of ReadSharedReq accesses(hits+misses) @@ -635,17 +645,17 @@ system.l2cache.demand_miss_rate::total 0.993318 # mi system.l2cache.overall_miss_rate::cpu.inst 0.989324 # miss rate for overall accesses system.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.l2cache.overall_miss_rate::total 0.993318 # miss rate for overall accesses -system.l2cache.ReadExReq_avg_miss_latency::cpu.data 99520.547945 # average ReadExReq miss latency -system.l2cache.ReadExReq_avg_miss_latency::total 99520.547945 # average ReadExReq miss latency -system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 97438.848921 # average ReadSharedReq miss latency -system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 99073.684211 # average ReadSharedReq miss latency -system.l2cache.ReadSharedReq_avg_miss_latency::total 97855.227882 # average ReadSharedReq miss latency -system.l2cache.demand_avg_miss_latency::cpu.inst 97438.848921 # average overall miss latency -system.l2cache.demand_avg_miss_latency::cpu.data 99267.857143 # average overall miss latency -system.l2cache.demand_avg_miss_latency::total 98127.802691 # average overall miss latency -system.l2cache.overall_avg_miss_latency::cpu.inst 97438.848921 # average overall miss latency -system.l2cache.overall_avg_miss_latency::cpu.data 99267.857143 # average overall miss latency -system.l2cache.overall_avg_miss_latency::total 98127.802691 # average overall miss latency +system.l2cache.ReadExReq_avg_miss_latency::cpu.data 101876.712329 # average ReadExReq miss latency +system.l2cache.ReadExReq_avg_miss_latency::total 101876.712329 # average ReadExReq miss latency +system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 104629.496403 # average ReadSharedReq miss latency +system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 103010.526316 # average ReadSharedReq miss latency +system.l2cache.ReadSharedReq_avg_miss_latency::total 104217.158177 # average ReadSharedReq miss latency +system.l2cache.demand_avg_miss_latency::cpu.inst 104629.496403 # average overall miss latency +system.l2cache.demand_avg_miss_latency::cpu.data 102517.857143 # average overall miss latency +system.l2cache.demand_avg_miss_latency::total 103834.080717 # average overall miss latency +system.l2cache.overall_avg_miss_latency::cpu.inst 104629.496403 # average overall miss latency +system.l2cache.overall_avg_miss_latency::cpu.data 102517.857143 # average overall miss latency +system.l2cache.overall_avg_miss_latency::total 103834.080717 # average overall miss latency system.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -663,17 +673,17 @@ system.l2cache.demand_mshr_misses::total 446 # nu system.l2cache.overall_mshr_misses::cpu.inst 278 # number of overall MSHR misses system.l2cache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses system.l2cache.overall_mshr_misses::total 446 # number of overall MSHR misses -system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5805000 # number of ReadExReq MSHR miss cycles -system.l2cache.ReadExReq_mshr_miss_latency::total 5805000 # number of ReadExReq MSHR miss cycles -system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 21528000 # number of ReadSharedReq MSHR miss cycles -system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7512000 # number of ReadSharedReq MSHR miss cycles -system.l2cache.ReadSharedReq_mshr_miss_latency::total 29040000 # number of ReadSharedReq MSHR miss cycles -system.l2cache.demand_mshr_miss_latency::cpu.inst 21528000 # number of demand (read+write) MSHR miss cycles -system.l2cache.demand_mshr_miss_latency::cpu.data 13317000 # number of demand (read+write) MSHR miss cycles -system.l2cache.demand_mshr_miss_latency::total 34845000 # number of demand (read+write) MSHR miss cycles -system.l2cache.overall_mshr_miss_latency::cpu.inst 21528000 # number of overall MSHR miss cycles -system.l2cache.overall_mshr_miss_latency::cpu.data 13317000 # number of overall MSHR miss cycles -system.l2cache.overall_mshr_miss_latency::total 34845000 # number of overall MSHR miss cycles +system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5977000 # number of ReadExReq MSHR miss cycles +system.l2cache.ReadExReq_mshr_miss_latency::total 5977000 # number of ReadExReq MSHR miss cycles +system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 23527000 # number of ReadSharedReq MSHR miss cycles +system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7886000 # number of ReadSharedReq MSHR miss cycles +system.l2cache.ReadSharedReq_mshr_miss_latency::total 31413000 # number of ReadSharedReq MSHR miss cycles +system.l2cache.demand_mshr_miss_latency::cpu.inst 23527000 # number of demand (read+write) MSHR miss cycles +system.l2cache.demand_mshr_miss_latency::cpu.data 13863000 # number of demand (read+write) MSHR miss cycles +system.l2cache.demand_mshr_miss_latency::total 37390000 # number of demand (read+write) MSHR miss cycles +system.l2cache.overall_mshr_miss_latency::cpu.inst 23527000 # number of overall MSHR miss cycles +system.l2cache.overall_mshr_miss_latency::cpu.data 13863000 # number of overall MSHR miss cycles +system.l2cache.overall_mshr_miss_latency::total 37390000 # number of overall MSHR miss cycles system.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.inst 0.989324 # mshr miss rate for ReadSharedReq accesses @@ -685,24 +695,24 @@ system.l2cache.demand_mshr_miss_rate::total 0.993318 # system.l2cache.overall_mshr_miss_rate::cpu.inst 0.989324 # mshr miss rate for overall accesses system.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.l2cache.overall_mshr_miss_rate::total 0.993318 # mshr miss rate for overall accesses -system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79520.547945 # average ReadExReq mshr miss latency -system.l2cache.ReadExReq_avg_mshr_miss_latency::total 79520.547945 # average ReadExReq mshr miss latency -system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 77438.848921 # average ReadSharedReq mshr miss latency -system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79073.684211 # average ReadSharedReq mshr miss latency -system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 77855.227882 # average ReadSharedReq mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 77438.848921 # average overall mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::cpu.data 79267.857143 # average overall mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::total 78127.802691 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 77438.848921 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::cpu.data 79267.857143 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::total 78127.802691 # average overall mshr miss latency +system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 81876.712329 # average ReadExReq mshr miss latency +system.l2cache.ReadExReq_avg_mshr_miss_latency::total 81876.712329 # average ReadExReq mshr miss latency +system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 84629.496403 # average ReadSharedReq mshr miss latency +system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 83010.526316 # average ReadSharedReq mshr miss latency +system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 84217.158177 # average ReadSharedReq mshr miss latency +system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 84629.496403 # average overall mshr miss latency +system.l2cache.demand_avg_mshr_miss_latency::cpu.data 82517.857143 # average overall mshr miss latency +system.l2cache.demand_avg_mshr_miss_latency::total 83834.080717 # average overall mshr miss latency +system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 84629.496403 # average overall mshr miss latency +system.l2cache.overall_avg_mshr_miss_latency::cpu.data 82517.857143 # average overall mshr miss latency +system.l2cache.overall_avg_mshr_miss_latency::total 83834.080717 # average overall mshr miss latency system.membus.snoop_filter.tot_requests 446 # Total number of requests made to the snoop filter. system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 62213000 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 64758000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 373 # Transaction distribution system.membus.trans_dist::ReadExReq 73 # Transaction distribution system.membus.trans_dist::ReadExResp 73 # Transaction distribution @@ -725,7 +735,7 @@ system.membus.snoop_fanout::max_value 0 # Re system.membus.snoop_fanout::total 446 # Request fanout histogram system.membus.reqLayer0.occupancy 446000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.7 # Layer utilization (%) -system.membus.respLayer0.occupancy 2375750 # Layer occupancy (ticks) -system.membus.respLayer0.utilization 3.8 # Layer utilization (%) +system.membus.respLayer0.occupancy 2377500 # Layer occupancy (ticks) +system.membus.respLayer0.utilization 3.7 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/config.ini b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/config.ini index 6eea99b33..2d26791e9 100644 --- a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/config.ini +++ b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/config.ini @@ -23,7 +23,7 @@ kernel_addr_check=true load_addr_mask=1099511627775 load_offset=0 mem_mode=timing -mem_ranges=0:536870911 +mem_ranges=0:536870911:0:0:0:0 memories=system.mem_ctrl mmap_using_noreserve=false multi_thread=false @@ -166,7 +166,7 @@ id_aa64isar0_el1=0 id_aa64isar1_el1=0 id_aa64mmfr0_el1=15728642 id_aa64mmfr1_el1=0 -id_aa64pfr0_el1=17 +id_aa64pfr0_el1=34 id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 @@ -271,27 +271,27 @@ transition_latency=100000000 [system.mem_ctrl] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -311,6 +311,7 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 @@ -320,7 +321,7 @@ p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 page_policy=open_adaptive power_model=Null -range=0:536870911 +range=0:536870911:0:0:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 @@ -342,9 +343,9 @@ tRTW=2500 tWR=15000 tWTR=7500 tXAW=30000 -tXP=0 +tXP=6000 tXPDLL=0 -tXS=0 +tXS=270000 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 @@ -353,6 +354,7 @@ port=system.membus.master[0] [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -364,7 +366,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -372,3 +374,10 @@ width=16 master=system.mem_ctrl.port slave=system.cpu.icache_port system.cpu.dcache_port system.system_port +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + diff --git a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/simout b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/simout index eb0348157..40266a5d8 100755 --- a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/simout +++ b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/simout @@ -3,13 +3,13 @@ Redirecting stderr to build/ARM/tests/opt/quick/se/03.learning-gem5/arm/linux/le gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:37:41 -gem5 started Jul 21 2016 15:05:26 -gem5 executing on e108600-lin, pid 24207 +gem5 compiled Oct 11 2016 00:00:58 +gem5 started Oct 13 2016 21:05:23 +gem5 executing on e108600-lin, pid 17594 command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/03.learning-gem5/arm/linux/learning-gem5-p1-simple -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/03.learning-gem5/arm/linux/learning-gem5-p1-simple Global frequency set at 1000000000000 ticks per second Beginning simulation! info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 325849000 because target called exit() +Exiting @ tick 372284000 because target called exit() diff --git a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/stats.txt b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/stats.txt index 670cfd0c1..afb55617d 100644 --- a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000333 # Number of seconds simulated -sim_ticks 332645000 # Number of ticks simulated -final_tick 332645000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000372 # Number of seconds simulated +sim_ticks 372284000 # Number of ticks simulated +final_tick 372284000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 141116 # Simulator instruction rate (inst/s) -host_op_rate 163173 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 9403646091 # Simulator tick rate (ticks/s) -host_mem_usage 651444 # Number of bytes of host memory used +host_inst_rate 131983 # Simulator instruction rate (inst/s) +host_op_rate 152589 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 9840410910 # Simulator tick rate (ticks/s) +host_mem_usage 650048 # Number of bytes of host memory used host_seconds 0.04 # Real time elapsed on the host sim_insts 4988 # Number of instructions simulated sim_ops 5770 # Number of ops (including micro ops) simulated system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 332645000 # Cumulative time (in ticks) in various power states +system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 372284000 # Cumulative time (in ticks) in various power states system.mem_ctrl.bytes_read::cpu.inst 20108 # Number of bytes read from this memory system.mem_ctrl.bytes_read::cpu.data 4672 # Number of bytes read from this memory system.mem_ctrl.bytes_read::total 24780 # Number of bytes read from this memory @@ -26,16 +26,16 @@ system.mem_ctrl.num_reads::cpu.data 1061 # Nu system.mem_ctrl.num_reads::total 6088 # Number of read requests responded to by this memory system.mem_ctrl.num_writes::cpu.data 936 # Number of write requests responded to by this memory system.mem_ctrl.num_writes::total 936 # Number of write requests responded to by this memory -system.mem_ctrl.bw_read::cpu.inst 60448827 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::cpu.data 14045003 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::total 74493830 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::cpu.inst 60448827 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::total 60448827 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_write::cpu.data 11110944 # Write bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_write::total 11110944 # Write bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.inst 60448827 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.data 25155947 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::total 85604774 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_read::cpu.inst 54012528 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::cpu.data 12549559 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::total 66562087 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::cpu.inst 54012528 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::total 54012528 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_write::cpu.data 9927905 # Write bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_write::total 9927905 # Write bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.inst 54012528 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.data 22477463 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::total 76489992 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrl.readReqs 6089 # Number of read requests accepted system.mem_ctrl.writeReqs 936 # Number of write requests accepted system.mem_ctrl.readBursts 6089 # Number of DRAM read bursts, including those serviced by the write queue @@ -82,7 +82,7 @@ system.mem_ctrl.perBankWrBursts::14 0 # Pe system.mem_ctrl.perBankWrBursts::15 0 # Per bank write bursts system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrl.totGap 332568000 # Total gap between requests +system.mem_ctrl.totGap 372207000 # Total gap between requests system.mem_ctrl.readPktSize::0 70 # Read request sizes (log2) system.mem_ctrl.readPktSize::1 1 # Read request sizes (log2) system.mem_ctrl.readPktSize::2 5858 # Read request sizes (log2) @@ -193,20 +193,20 @@ system.mem_ctrl.wrQLenPdf::60 0 # Wh system.mem_ctrl.wrQLenPdf::61 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrl.bytesPerActivate::samples 498 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::mean 770.698795 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::gmean 632.685353 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::stdev 340.090332 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::0-127 21 4.22% 4.22% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::128-255 40 8.03% 12.25% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::256-383 36 7.23% 19.48% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::384-511 28 5.62% 25.10% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::512-639 23 4.62% 29.72% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::640-767 25 5.02% 34.74% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::768-895 24 4.82% 39.56% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::896-1023 28 5.62% 45.18% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::1024-1151 273 54.82% 100.00% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::total 498 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::samples 514 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::mean 749.322957 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::gmean 608.037375 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::stdev 344.826867 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::0-127 25 4.86% 4.86% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::128-255 42 8.17% 13.04% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::256-383 44 8.56% 21.60% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::384-511 26 5.06% 26.65% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::512-639 25 4.86% 31.52% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::640-767 34 6.61% 38.13% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::768-895 27 5.25% 43.39% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::896-1023 27 5.25% 48.64% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::1024-1151 264 51.36% 100.00% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::total 514 # Bytes accessed per row activation system.mem_ctrl.rdPerTurnAround::samples 4 # Reads before turning the bus around for writes system.mem_ctrl.rdPerTurnAround::mean 1490.500000 # Reads before turning the bus around for writes system.mem_ctrl.rdPerTurnAround::gmean 1373.591360 # Reads before turning the bus around for writes @@ -221,58 +221,68 @@ system.mem_ctrl.wrPerTurnAround::mean 16 # Wr system.mem_ctrl.wrPerTurnAround::gmean 16.000000 # Writes before turning the bus around for reads system.mem_ctrl.wrPerTurnAround::16 4 100.00% 100.00% # Writes before turning the bus around for reads system.mem_ctrl.wrPerTurnAround::total 4 # Writes before turning the bus around for reads -system.mem_ctrl.totQLat 17899250 # Total ticks spent queuing -system.mem_ctrl.totMemAccLat 130193000 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrl.totQLat 57609500 # Total ticks spent queuing +system.mem_ctrl.totMemAccLat 169903250 # Total ticks spent from burst creation until serviced by the DRAM system.mem_ctrl.totBusLat 29945000 # Total ticks spent in databus transfers -system.mem_ctrl.avgQLat 2988.69 # Average queueing delay per DRAM burst +system.mem_ctrl.avgQLat 9619.22 # Average queueing delay per DRAM burst system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.mem_ctrl.avgMemAccLat 21738.69 # Average memory access latency per DRAM burst -system.mem_ctrl.avgRdBW 1152.27 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrl.avgWrBW 12.31 # Average achieved write bandwidth in MiByte/s -system.mem_ctrl.avgRdBWSys 74.51 # Average system read bandwidth in MiByte/s -system.mem_ctrl.avgWrBWSys 11.11 # Average system write bandwidth in MiByte/s +system.mem_ctrl.avgMemAccLat 28369.22 # Average memory access latency per DRAM burst +system.mem_ctrl.avgRdBW 1029.58 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrl.avgWrBW 11.00 # Average achieved write bandwidth in MiByte/s +system.mem_ctrl.avgRdBWSys 66.57 # Average system read bandwidth in MiByte/s +system.mem_ctrl.avgWrBWSys 9.93 # Average system write bandwidth in MiByte/s system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrl.busUtil 9.10 # Data bus utilization in percentage -system.mem_ctrl.busUtilRead 9.00 # Data bus utilization in percentage for reads -system.mem_ctrl.busUtilWrite 0.10 # Data bus utilization in percentage for writes +system.mem_ctrl.busUtil 8.13 # Data bus utilization in percentage +system.mem_ctrl.busUtilRead 8.04 # Data bus utilization in percentage for reads +system.mem_ctrl.busUtilWrite 0.09 # Data bus utilization in percentage for writes system.mem_ctrl.avgRdQLen 1.00 # Average read queue length when enqueuing system.mem_ctrl.avgWrQLen 24.94 # Average write queue length when enqueuing -system.mem_ctrl.readRowHits 5487 # Number of row buffer hits during reads +system.mem_ctrl.readRowHits 5473 # Number of row buffer hits during reads system.mem_ctrl.writeRowHits 62 # Number of row buffer hits during writes -system.mem_ctrl.readRowHitRate 91.62 # Row buffer hit rate for reads +system.mem_ctrl.readRowHitRate 91.38 # Row buffer hit rate for reads system.mem_ctrl.writeRowHitRate 76.54 # Row buffer hit rate for writes -system.mem_ctrl.avgGap 47340.64 # Average gap between requests -system.mem_ctrl.pageHitRate 91.42 # Row buffer hit rate, read and write combined -system.mem_ctrl_0.actEnergy 2812320 # Energy for activate commands per rank (pJ) -system.mem_ctrl_0.preEnergy 1534500 # Energy for precharge commands per rank (pJ) -system.mem_ctrl_0.readEnergy 38048400 # Energy for read commands per rank (pJ) +system.mem_ctrl.avgGap 52983.20 # Average gap between requests +system.mem_ctrl.pageHitRate 91.19 # Row buffer hit rate, read and write combined +system.mem_ctrl_0.actEnergy 2727480 # Energy for activate commands per rank (pJ) +system.mem_ctrl_0.preEnergy 1438305 # Energy for precharge commands per rank (pJ) +system.mem_ctrl_0.readEnergy 35364420 # Energy for read commands per rank (pJ) system.mem_ctrl_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.mem_ctrl_0.refreshEnergy 21359520 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_0.actBackEnergy 216770715 # Energy for active background per rank (pJ) -system.mem_ctrl_0.preBackEnergy 6219750 # Energy for precharge background per rank (pJ) -system.mem_ctrl_0.totalEnergy 286745205 # Total energy per rank (pJ) -system.mem_ctrl_0.averagePower 876.139742 # Core power per rank (mW) -system.mem_ctrl_0.memoryStateTime::IDLE 7265500 # Time in different power states -system.mem_ctrl_0.memoryStateTime::REF 10920000 # Time in different power states -system.mem_ctrl_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrl_0.memoryStateTime::ACT 309110750 # Time in different power states -system.mem_ctrl_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrl_1.actEnergy 922320 # Energy for activate commands per rank (pJ) -system.mem_ctrl_1.preEnergy 503250 # Energy for precharge commands per rank (pJ) -system.mem_ctrl_1.readEnergy 7893600 # Energy for read commands per rank (pJ) -system.mem_ctrl_1.writeEnergy 311040 # Energy for write commands per rank (pJ) -system.mem_ctrl_1.refreshEnergy 21359520 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_1.actBackEnergy 188416350 # Energy for active background per rank (pJ) -system.mem_ctrl_1.preBackEnergy 31092000 # Energy for precharge background per rank (pJ) -system.mem_ctrl_1.totalEnergy 250498080 # Total energy per rank (pJ) -system.mem_ctrl_1.averagePower 765.387945 # Core power per rank (mW) -system.mem_ctrl_1.memoryStateTime::IDLE 51038750 # Time in different power states -system.mem_ctrl_1.memoryStateTime::REF 10920000 # Time in different power states -system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrl_1.memoryStateTime::ACT 265729250 # Time in different power states -system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 332645000 # Cumulative time (in ticks) in various power states -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 332645000 # Cumulative time (in ticks) in various power states +system.mem_ctrl_0.refreshEnergy 28888080.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrl_0.actBackEnergy 64999380 # Energy for active background per rank (pJ) +system.mem_ctrl_0.preBackEnergy 1619520 # Energy for precharge background per rank (pJ) +system.mem_ctrl_0.actPowerDownEnergy 98643060 # Energy for active power-down per rank (pJ) +system.mem_ctrl_0.prePowerDownEnergy 3533760 # Energy for precharge power-down per rank (pJ) +system.mem_ctrl_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrl_0.totalEnergy 237214005 # Total energy per rank (pJ) +system.mem_ctrl_0.averagePower 637.183891 # Core power per rank (mW) +system.mem_ctrl_0.totalIdleTime 225396250 # Total Idle time Per DRAM Rank +system.mem_ctrl_0.memoryStateTime::IDLE 954000 # Time in different power states +system.mem_ctrl_0.memoryStateTime::REF 12220000 # Time in different power states +system.mem_ctrl_0.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrl_0.memoryStateTime::PRE_PDN 9196500 # Time in different power states +system.mem_ctrl_0.memoryStateTime::ACT 133713750 # Time in different power states +system.mem_ctrl_0.memoryStateTime::ACT_PDN 216199750 # Time in different power states +system.mem_ctrl_1.actEnergy 971040 # Energy for activate commands per rank (pJ) +system.mem_ctrl_1.preEnergy 512325 # Energy for precharge commands per rank (pJ) +system.mem_ctrl_1.readEnergy 7389900 # Energy for read commands per rank (pJ) +system.mem_ctrl_1.writeEnergy 334080 # Energy for write commands per rank (pJ) +system.mem_ctrl_1.refreshEnergy 27658800.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrl_1.actBackEnergy 18607080 # Energy for active background per rank (pJ) +system.mem_ctrl_1.preBackEnergy 791520 # Energy for precharge background per rank (pJ) +system.mem_ctrl_1.actPowerDownEnergy 128152530 # Energy for active power-down per rank (pJ) +system.mem_ctrl_1.prePowerDownEnergy 7837920 # Energy for precharge power-down per rank (pJ) +system.mem_ctrl_1.selfRefreshEnergy 7265340 # Energy for self refresh per rank (pJ) +system.mem_ctrl_1.totalEnergy 199520535 # Total energy per rank (pJ) +system.mem_ctrl_1.averagePower 535.934929 # Core power per rank (mW) +system.mem_ctrl_1.totalIdleTime 328663750 # Total Idle time Per DRAM Rank +system.mem_ctrl_1.memoryStateTime::IDLE 770000 # Time in different power states +system.mem_ctrl_1.memoryStateTime::REF 11706000 # Time in different power states +system.mem_ctrl_1.memoryStateTime::SREF 27971000 # Time in different power states +system.mem_ctrl_1.memoryStateTime::PRE_PDN 20415250 # Time in different power states +system.mem_ctrl_1.memoryStateTime::ACT 30385000 # Time in different power states +system.mem_ctrl_1.memoryStateTime::ACT_PDN 281036750 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 372284000 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 372284000 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -302,7 +312,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 332645000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 372284000 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -332,7 +342,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 332645000 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 372284000 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -362,7 +372,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 332645000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 372284000 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -393,8 +403,8 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 332645000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 332645 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 372284000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 372284 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 4988 # Number of instructions committed @@ -415,7 +425,7 @@ system.cpu.num_mem_refs 2035 # nu system.cpu.num_load_insts 1085 # Number of load instructions system.cpu.num_store_insts 950 # Number of store instructions system.cpu.num_idle_cycles 0.001000 # Number of idle cycles -system.cpu.num_busy_cycles 332644.999000 # Number of busy cycles +system.cpu.num_busy_cycles 372283.999000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 1107 # Number of branches fetched @@ -460,7 +470,7 @@ system.membus.snoop_filter.hit_multi_requests 0 system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 332645000 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 372284000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 6078 # Transaction distribution system.membus.trans_dist::ReadResp 6088 # Transaction distribution system.membus.trans_dist::WriteReq 925 # Transaction distribution @@ -487,10 +497,10 @@ system.membus.snoop_fanout::min_value 0 # Re system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 7025 # Request fanout histogram system.membus.reqLayer0.occupancy 7961000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.4 # Layer utilization (%) -system.membus.respLayer0.occupancy 11412500 # Layer occupancy (ticks) -system.membus.respLayer0.utilization 3.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 3325250 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 1.0 # Layer utilization (%) +system.membus.reqLayer0.utilization 2.1 # Layer utilization (%) +system.membus.respLayer0.occupancy 11413250 # Layer occupancy (ticks) +system.membus.respLayer0.utilization 3.1 # Layer utilization (%) +system.membus.respLayer1.occupancy 3327250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.9 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/config.ini b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/config.ini index ad9e5a13b..733323a88 100644 --- a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/config.ini +++ b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/config.ini @@ -23,7 +23,7 @@ kernel_addr_check=true load_addr_mask=1099511627775 load_offset=0 mem_mode=timing -mem_ranges=0:536870911 +mem_ranges=0:536870911:0:0:0:0 memories=system.mem_ctrl mmap_using_noreserve=false multi_thread=false @@ -102,7 +102,7 @@ icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.clk_domain clusivity=mostly_incl @@ -198,7 +198,7 @@ sys=system [system.cpu.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.clk_domain clusivity=mostly_incl @@ -258,7 +258,7 @@ id_aa64isar0_el1=0 id_aa64isar1_el1=0 id_aa64mmfr0_el1=15728642 id_aa64mmfr1_el1=0 -id_aa64pfr0_el1=17 +id_aa64pfr0_el1=34 id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 @@ -393,7 +393,7 @@ system=system [system.l2cache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.clk_domain clusivity=mostly_incl @@ -438,27 +438,27 @@ size=262144 [system.mem_ctrl] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -478,6 +478,7 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 @@ -487,7 +488,7 @@ p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 page_policy=open_adaptive power_model=Null -range=0:536870911 +range=0:536870911:0:0:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 @@ -509,9 +510,9 @@ tRTW=2500 tWR=15000 tWTR=7500 tXAW=30000 -tXP=0 +tXP=6000 tXPDLL=0 -tXS=0 +tXS=270000 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 @@ -520,6 +521,7 @@ port=system.membus.master[0] [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -531,7 +533,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -539,3 +541,10 @@ width=16 master=system.mem_ctrl.port slave=system.l2cache.mem_side system.system_port +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + diff --git a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/simout b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/simout index a3411dc5e..7a7d67b77 100755 --- a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/simout +++ b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/simout @@ -3,13 +3,13 @@ Redirecting stderr to build/ARM/tests/opt/quick/se/03.learning-gem5/arm/linux/le gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:37:41 -gem5 started Jul 21 2016 15:03:01 -gem5 executing on e108600-lin, pid 24156 +gem5 compiled Oct 11 2016 00:00:58 +gem5 started Oct 13 2016 21:05:17 +gem5 executing on e108600-lin, pid 17589 command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/03.learning-gem5/arm/linux/learning-gem5-p1-two-level -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/03.learning-gem5/arm/linux/learning-gem5-p1-two-level Global frequency set at 1000000000000 ticks per second Beginning simulation! info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 49855000 because target called exit() +Exiting @ tick 52453000 because target called exit() diff --git a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/stats.txt b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/stats.txt index 005f27b4b..3eb7c70d8 100644 --- a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000050 # Number of seconds simulated -sim_ticks 50074000 # Number of ticks simulated -final_tick 50074000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000052 # Number of seconds simulated +sim_ticks 52453000 # Number of ticks simulated +final_tick 52453000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 207988 # Simulator instruction rate (inst/s) -host_op_rate 240459 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2085706484 # Simulator tick rate (ticks/s) -host_mem_usage 655032 # Number of bytes of host memory used +host_inst_rate 234245 # Simulator instruction rate (inst/s) +host_op_rate 270642 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2457731659 # Simulator tick rate (ticks/s) +host_mem_usage 654144 # Number of bytes of host memory used host_seconds 0.02 # Real time elapsed on the host sim_insts 4988 # Number of instructions simulated sim_ops 5770 # Number of ops (including micro ops) simulated system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 50074000 # Cumulative time (in ticks) in various power states +system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 52453000 # Cumulative time (in ticks) in various power states system.mem_ctrl.bytes_read::cpu.inst 14400 # Number of bytes read from this memory system.mem_ctrl.bytes_read::cpu.data 8064 # Number of bytes read from this memory system.mem_ctrl.bytes_read::total 22464 # Number of bytes read from this memory @@ -22,14 +22,14 @@ system.mem_ctrl.bytes_inst_read::total 14400 # Nu system.mem_ctrl.num_reads::cpu.inst 225 # Number of read requests responded to by this memory system.mem_ctrl.num_reads::cpu.data 126 # Number of read requests responded to by this memory system.mem_ctrl.num_reads::total 351 # Number of read requests responded to by this memory -system.mem_ctrl.bw_read::cpu.inst 287574390 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::cpu.data 161041658 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::total 448616048 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::cpu.inst 287574390 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::total 287574390 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.inst 287574390 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.data 161041658 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::total 448616048 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_read::cpu.inst 274531485 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::cpu.data 153737632 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::total 428269117 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::cpu.inst 274531485 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::total 274531485 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.inst 274531485 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.data 153737632 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::total 428269117 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrl.readReqs 351 # Number of read requests accepted system.mem_ctrl.writeReqs 0 # Number of write requests accepted system.mem_ctrl.readBursts 351 # Number of DRAM read bursts, including those serviced by the write queue @@ -76,7 +76,7 @@ system.mem_ctrl.perBankWrBursts::14 0 # Pe system.mem_ctrl.perBankWrBursts::15 0 # Per bank write bursts system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrl.totGap 49975000 # Total gap between requests +system.mem_ctrl.totGap 52348000 # Total gap between requests system.mem_ctrl.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrl.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrl.readPktSize::2 0 # Read request sizes (log2) @@ -187,71 +187,81 @@ system.mem_ctrl.wrQLenPdf::60 0 # Wh system.mem_ctrl.wrQLenPdf::61 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrl.bytesPerActivate::samples 73 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::mean 300.712329 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::gmean 213.377798 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::stdev 265.316032 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::0-127 14 19.18% 19.18% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::128-255 25 34.25% 53.42% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::256-383 14 19.18% 72.60% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::384-511 5 6.85% 79.45% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::512-639 7 9.59% 89.04% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::640-767 1 1.37% 90.41% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::768-895 2 2.74% 93.15% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::1024-1151 5 6.85% 100.00% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::total 73 # Bytes accessed per row activation -system.mem_ctrl.totQLat 2342250 # Total ticks spent queuing -system.mem_ctrl.totMemAccLat 8923500 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrl.bytesPerActivate::samples 75 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::mean 285.866667 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::gmean 188.503913 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::stdev 282.583704 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::0-127 22 29.33% 29.33% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::128-255 20 26.67% 56.00% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::256-383 15 20.00% 76.00% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::384-511 4 5.33% 81.33% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::512-639 4 5.33% 86.67% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::640-767 2 2.67% 89.33% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::768-895 2 2.67% 92.00% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::1024-1151 6 8.00% 100.00% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::total 75 # Bytes accessed per row activation +system.mem_ctrl.totQLat 4720500 # Total ticks spent queuing +system.mem_ctrl.totMemAccLat 11301750 # Total ticks spent from burst creation until serviced by the DRAM system.mem_ctrl.totBusLat 1755000 # Total ticks spent in databus transfers -system.mem_ctrl.avgQLat 6673.08 # Average queueing delay per DRAM burst +system.mem_ctrl.avgQLat 13448.72 # Average queueing delay per DRAM burst system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.mem_ctrl.avgMemAccLat 25423.08 # Average memory access latency per DRAM burst -system.mem_ctrl.avgRdBW 448.62 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrl.avgMemAccLat 32198.72 # Average memory access latency per DRAM burst +system.mem_ctrl.avgRdBW 428.27 # Average DRAM read bandwidth in MiByte/s system.mem_ctrl.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.mem_ctrl.avgRdBWSys 448.62 # Average system read bandwidth in MiByte/s +system.mem_ctrl.avgRdBWSys 428.27 # Average system read bandwidth in MiByte/s system.mem_ctrl.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrl.busUtil 3.50 # Data bus utilization in percentage -system.mem_ctrl.busUtilRead 3.50 # Data bus utilization in percentage for reads +system.mem_ctrl.busUtil 3.35 # Data bus utilization in percentage +system.mem_ctrl.busUtilRead 3.35 # Data bus utilization in percentage for reads system.mem_ctrl.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.mem_ctrl.avgRdQLen 1.00 # Average read queue length when enqueuing system.mem_ctrl.avgWrQLen 0.00 # Average write queue length when enqueuing -system.mem_ctrl.readRowHits 274 # Number of row buffer hits during reads +system.mem_ctrl.readRowHits 270 # Number of row buffer hits during reads system.mem_ctrl.writeRowHits 0 # Number of row buffer hits during writes -system.mem_ctrl.readRowHitRate 78.06 # Row buffer hit rate for reads +system.mem_ctrl.readRowHitRate 76.92 # Row buffer hit rate for reads system.mem_ctrl.writeRowHitRate nan # Row buffer hit rate for writes -system.mem_ctrl.avgGap 142378.92 # Average gap between requests -system.mem_ctrl.pageHitRate 78.06 # Row buffer hit rate, read and write combined -system.mem_ctrl_0.actEnergy 347760 # Energy for activate commands per rank (pJ) +system.mem_ctrl.avgGap 149139.60 # Average gap between requests +system.mem_ctrl.pageHitRate 76.92 # Row buffer hit rate, read and write combined +system.mem_ctrl_0.actEnergy 378420 # Energy for activate commands per rank (pJ) system.mem_ctrl_0.preEnergy 189750 # Energy for precharge commands per rank (pJ) -system.mem_ctrl_0.readEnergy 1817400 # Energy for read commands per rank (pJ) +system.mem_ctrl_0.readEnergy 1813560 # Energy for read commands per rank (pJ) system.mem_ctrl_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.mem_ctrl_0.refreshEnergy 3051360 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_0.actBackEnergy 31477680 # Energy for active background per rank (pJ) -system.mem_ctrl_0.preBackEnergy 574500 # Energy for precharge background per rank (pJ) -system.mem_ctrl_0.totalEnergy 37458450 # Total energy per rank (pJ) -system.mem_ctrl_0.averagePower 797.370018 # Core power per rank (mW) -system.mem_ctrl_0.memoryStateTime::IDLE 805250 # Time in different power states +system.mem_ctrl_0.refreshEnergy 3687840.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrl_0.actBackEnergy 4500720 # Energy for active background per rank (pJ) +system.mem_ctrl_0.preBackEnergy 84480 # Energy for precharge background per rank (pJ) +system.mem_ctrl_0.actPowerDownEnergy 19212990 # Energy for active power-down per rank (pJ) +system.mem_ctrl_0.prePowerDownEnergy 88320 # Energy for precharge power-down per rank (pJ) +system.mem_ctrl_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrl_0.totalEnergy 29956080 # Total energy per rank (pJ) +system.mem_ctrl_0.averagePower 571.095108 # Core power per rank (mW) +system.mem_ctrl_0.totalIdleTime 42304000 # Total Idle time Per DRAM Rank +system.mem_ctrl_0.memoryStateTime::IDLE 53000 # Time in different power states system.mem_ctrl_0.memoryStateTime::REF 1560000 # Time in different power states -system.mem_ctrl_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrl_0.memoryStateTime::ACT 44626000 # Time in different power states -system.mem_ctrl_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrl_1.actEnergy 189000 # Energy for activate commands per rank (pJ) -system.mem_ctrl_1.preEnergy 103125 # Energy for precharge commands per rank (pJ) -system.mem_ctrl_1.readEnergy 741000 # Energy for read commands per rank (pJ) +system.mem_ctrl_0.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrl_0.memoryStateTime::PRE_PDN 229750 # Time in different power states +system.mem_ctrl_0.memoryStateTime::ACT 8478750 # Time in different power states +system.mem_ctrl_0.memoryStateTime::ACT_PDN 42131500 # Time in different power states +system.mem_ctrl_1.actEnergy 199920 # Energy for activate commands per rank (pJ) +system.mem_ctrl_1.preEnergy 94875 # Energy for precharge commands per rank (pJ) +system.mem_ctrl_1.readEnergy 692580 # Energy for read commands per rank (pJ) system.mem_ctrl_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.mem_ctrl_1.refreshEnergy 3051360 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_1.actBackEnergy 30101985 # Energy for active background per rank (pJ) -system.mem_ctrl_1.preBackEnergy 1781250 # Energy for precharge background per rank (pJ) -system.mem_ctrl_1.totalEnergy 35967720 # Total energy per rank (pJ) -system.mem_ctrl_1.averagePower 765.637167 # Core power per rank (mW) -system.mem_ctrl_1.memoryStateTime::IDLE 3011750 # Time in different power states +system.mem_ctrl_1.refreshEnergy 3687840.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrl_1.actBackEnergy 2032620 # Energy for active background per rank (pJ) +system.mem_ctrl_1.preBackEnergy 139680 # Energy for precharge background per rank (pJ) +system.mem_ctrl_1.actPowerDownEnergy 19936320 # Energy for active power-down per rank (pJ) +system.mem_ctrl_1.prePowerDownEnergy 1502400 # Energy for precharge power-down per rank (pJ) +system.mem_ctrl_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrl_1.totalEnergy 28286235 # Total energy per rank (pJ) +system.mem_ctrl_1.averagePower 539.260491 # Core power per rank (mW) +system.mem_ctrl_1.totalIdleTime 44784500 # Total Idle time Per DRAM Rank +system.mem_ctrl_1.memoryStateTime::IDLE 200000 # Time in different power states system.mem_ctrl_1.memoryStateTime::REF 1560000 # Time in different power states -system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrl_1.memoryStateTime::ACT 42630250 # Time in different power states -system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 50074000 # Cumulative time (in ticks) in various power states -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 50074000 # Cumulative time (in ticks) in various power states +system.mem_ctrl_1.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrl_1.memoryStateTime::PRE_PDN 3909750 # Time in different power states +system.mem_ctrl_1.memoryStateTime::ACT 3056250 # Time in different power states +system.mem_ctrl_1.memoryStateTime::ACT_PDN 43727000 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 52453000 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 52453000 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -281,7 +291,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 50074000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 52453000 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -311,7 +321,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 50074000 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 52453000 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -341,7 +351,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 50074000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 52453000 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -372,8 +382,8 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 50074000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 50074 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 52453000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 52453 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 4988 # Number of instructions committed @@ -394,7 +404,7 @@ system.cpu.num_mem_refs 2035 # nu system.cpu.num_load_insts 1085 # Number of load instructions system.cpu.num_store_insts 950 # Number of store instructions system.cpu.num_idle_cycles 0.001000 # Number of idle cycles -system.cpu.num_busy_cycles 50073.999000 # Number of busy cycles +system.cpu.num_busy_cycles 52452.999000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 1107 # Number of branches fetched @@ -433,23 +443,23 @@ system.cpu.op_class::MemWrite 950 16.29% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 5831 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 50074000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 52453000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 84.375326 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 84.380856 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1855 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 142 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 13.063380 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 84.375326 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.082398 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.082398 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 84.380856 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.082403 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.082403 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 142 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 123 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.138672 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 4136 # Number of tag accesses system.cpu.dcache.tags.data_accesses 4136 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 50074000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 52453000 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 951 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 951 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 882 # number of WriteReq hits @@ -470,14 +480,14 @@ system.cpu.dcache.demand_misses::cpu.data 142 # n system.cpu.dcache.demand_misses::total 142 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 142 # number of overall misses system.cpu.dcache.overall_misses::total 142 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 8615000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 8615000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4388000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4388000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 13003000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 13003000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 13003000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 13003000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 9073000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 9073000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4652000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4652000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 13725000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 13725000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 13725000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 13725000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1050 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1050 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses) @@ -498,14 +508,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.071899 system.cpu.dcache.demand_miss_rate::total 0.071899 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.071899 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.071899 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 87020.202020 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 87020.202020 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 102046.511628 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 102046.511628 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 91570.422535 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 91570.422535 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 91570.422535 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 91570.422535 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 91646.464646 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 91646.464646 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 108186.046512 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 108186.046512 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 96654.929577 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 96654.929577 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 96654.929577 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 96654.929577 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -520,14 +530,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 142 system.cpu.dcache.demand_mshr_misses::total 142 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 142 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8417000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 8417000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4302000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4302000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12719000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 12719000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12719000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 12719000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8875000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 8875000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4566000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4566000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13441000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 13441000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13441000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 13441000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.094286 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.094286 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046486 # mshr miss rate for WriteReq accesses @@ -536,31 +546,31 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.071899 system.cpu.dcache.demand_mshr_miss_rate::total 0.071899 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.071899 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.071899 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 85020.202020 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 85020.202020 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 100046.511628 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 100046.511628 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 89570.422535 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 89570.422535 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 89570.422535 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 89570.422535 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 50074000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 89646.464646 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 89646.464646 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 106186.046512 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 106186.046512 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 94654.929577 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 94654.929577 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 94654.929577 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 94654.929577 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 52453000 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 70 # number of replacements -system.cpu.icache.tags.tagsinuse 96.598037 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 96.586088 # Cycle average of tags in use system.cpu.icache.tags.total_refs 4779 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 249 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 19.192771 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 96.598037 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.377336 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.377336 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 96.586088 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.377289 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.377289 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 179 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 128 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.699219 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 10305 # Number of tag accesses system.cpu.icache.tags.data_accesses 10305 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 50074000 # Cumulative time (in ticks) in various power states +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 52453000 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 4779 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 4779 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 4779 # number of demand (read+write) hits @@ -573,12 +583,12 @@ system.cpu.icache.demand_misses::cpu.inst 249 # n system.cpu.icache.demand_misses::total 249 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 249 # number of overall misses system.cpu.icache.overall_misses::total 249 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 23815000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 23815000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 23815000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 23815000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 23815000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 23815000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 25472000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 25472000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 25472000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 25472000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 25472000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 25472000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 5028 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 5028 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 5028 # number of demand (read+write) accesses @@ -591,12 +601,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.049523 system.cpu.icache.demand_miss_rate::total 0.049523 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.049523 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.049523 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 95642.570281 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 95642.570281 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 95642.570281 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 95642.570281 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 95642.570281 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 95642.570281 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 102297.188755 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 102297.188755 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 102297.188755 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 102297.188755 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 102297.188755 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 102297.188755 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -609,31 +619,31 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 249 system.cpu.icache.demand_mshr_misses::total 249 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 249 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 249 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23317000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 23317000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23317000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 23317000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23317000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 23317000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24974000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 24974000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24974000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 24974000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24974000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 24974000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.049523 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.049523 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.049523 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.049523 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.049523 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.049523 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 93642.570281 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 93642.570281 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 93642.570281 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 93642.570281 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 93642.570281 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 93642.570281 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 100297.188755 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 100297.188755 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 100297.188755 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 100297.188755 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 100297.188755 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 100297.188755 # average overall mshr miss latency system.l2bus.snoop_filter.tot_requests 461 # Total number of requests made to the snoop filter. system.l2bus.snoop_filter.hit_single_requests 94 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.l2bus.snoop_filter.hit_multi_requests 10 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.l2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.l2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.l2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.l2bus.pwrStateResidencyTicks::UNDEFINED 50074000 # Cumulative time (in ticks) in various power states +system.l2bus.pwrStateResidencyTicks::UNDEFINED 52453000 # Cumulative time (in ticks) in various power states system.l2bus.trans_dist::ReadResp 348 # Transaction distribution system.l2bus.trans_dist::CleanEvict 70 # Transaction distribution system.l2bus.trans_dist::ReadExReq 43 # Transaction distribution @@ -661,28 +671,28 @@ system.l2bus.snoop_fanout::total 391 # Re system.l2bus.reqLayer0.occupancy 461000 # Layer occupancy (ticks) system.l2bus.reqLayer0.utilization 0.9 # Layer utilization (%) system.l2bus.respLayer0.occupancy 747000 # Layer occupancy (ticks) -system.l2bus.respLayer0.utilization 1.5 # Layer utilization (%) +system.l2bus.respLayer0.utilization 1.4 # Layer utilization (%) system.l2bus.respLayer1.occupancy 426000 # Layer occupancy (ticks) -system.l2bus.respLayer1.utilization 0.9 # Layer utilization (%) -system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 50074000 # Cumulative time (in ticks) in various power states +system.l2bus.respLayer1.utilization 0.8 # Layer utilization (%) +system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 52453000 # Cumulative time (in ticks) in various power states system.l2cache.tags.replacements 0 # number of replacements -system.l2cache.tags.tagsinuse 184.338383 # Cycle average of tags in use +system.l2cache.tags.tagsinuse 184.362995 # Cycle average of tags in use system.l2cache.tags.total_refs 100 # Total number of references to valid blocks. system.l2cache.tags.sampled_refs 351 # Sample count of references to valid blocks. system.l2cache.tags.avg_refs 0.284900 # Average number of references to valid blocks. system.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2cache.tags.occ_blocks::cpu.inst 107.366220 # Average occupied blocks per requestor -system.l2cache.tags.occ_blocks::cpu.data 76.972162 # Average occupied blocks per requestor -system.l2cache.tags.occ_percent::cpu.inst 0.026212 # Average percentage of cache occupancy -system.l2cache.tags.occ_percent::cpu.data 0.018792 # Average percentage of cache occupancy -system.l2cache.tags.occ_percent::total 0.045004 # Average percentage of cache occupancy +system.l2cache.tags.occ_blocks::cpu.inst 107.367017 # Average occupied blocks per requestor +system.l2cache.tags.occ_blocks::cpu.data 76.995978 # Average occupied blocks per requestor +system.l2cache.tags.occ_percent::cpu.inst 0.026213 # Average percentage of cache occupancy +system.l2cache.tags.occ_percent::cpu.data 0.018798 # Average percentage of cache occupancy +system.l2cache.tags.occ_percent::total 0.045010 # Average percentage of cache occupancy system.l2cache.tags.occ_task_id_blocks::1024 351 # Occupied blocks per task id -system.l2cache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id -system.l2cache.tags.age_task_id_blocks_1024::1 289 # Occupied blocks per task id +system.l2cache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id +system.l2cache.tags.age_task_id_blocks_1024::1 292 # Occupied blocks per task id system.l2cache.tags.occ_task_id_percent::1024 0.085693 # Percentage of cache occupancy per task id system.l2cache.tags.tag_accesses 3959 # Number of tag accesses system.l2cache.tags.data_accesses 3959 # Number of data accesses -system.l2cache.pwrStateResidencyTicks::UNDEFINED 50074000 # Cumulative time (in ticks) in various power states +system.l2cache.pwrStateResidencyTicks::UNDEFINED 52453000 # Cumulative time (in ticks) in various power states system.l2cache.ReadSharedReq_hits::cpu.inst 24 # number of ReadSharedReq hits system.l2cache.ReadSharedReq_hits::cpu.data 16 # number of ReadSharedReq hits system.l2cache.ReadSharedReq_hits::total 40 # number of ReadSharedReq hits @@ -703,17 +713,17 @@ system.l2cache.demand_misses::total 351 # nu system.l2cache.overall_misses::cpu.inst 225 # number of overall misses system.l2cache.overall_misses::cpu.data 126 # number of overall misses system.l2cache.overall_misses::total 351 # number of overall misses -system.l2cache.ReadExReq_miss_latency::cpu.data 4173000 # number of ReadExReq miss cycles -system.l2cache.ReadExReq_miss_latency::total 4173000 # number of ReadExReq miss cycles -system.l2cache.ReadSharedReq_miss_latency::cpu.inst 22026000 # number of ReadSharedReq miss cycles -system.l2cache.ReadSharedReq_miss_latency::cpu.data 7756000 # number of ReadSharedReq miss cycles -system.l2cache.ReadSharedReq_miss_latency::total 29782000 # number of ReadSharedReq miss cycles -system.l2cache.demand_miss_latency::cpu.inst 22026000 # number of demand (read+write) miss cycles -system.l2cache.demand_miss_latency::cpu.data 11929000 # number of demand (read+write) miss cycles -system.l2cache.demand_miss_latency::total 33955000 # number of demand (read+write) miss cycles -system.l2cache.overall_miss_latency::cpu.inst 22026000 # number of overall miss cycles -system.l2cache.overall_miss_latency::cpu.data 11929000 # number of overall miss cycles -system.l2cache.overall_miss_latency::total 33955000 # number of overall miss cycles +system.l2cache.ReadExReq_miss_latency::cpu.data 4437000 # number of ReadExReq miss cycles +system.l2cache.ReadExReq_miss_latency::total 4437000 # number of ReadExReq miss cycles +system.l2cache.ReadSharedReq_miss_latency::cpu.inst 23683000 # number of ReadSharedReq miss cycles +system.l2cache.ReadSharedReq_miss_latency::cpu.data 8214000 # number of ReadSharedReq miss cycles +system.l2cache.ReadSharedReq_miss_latency::total 31897000 # number of ReadSharedReq miss cycles +system.l2cache.demand_miss_latency::cpu.inst 23683000 # number of demand (read+write) miss cycles +system.l2cache.demand_miss_latency::cpu.data 12651000 # number of demand (read+write) miss cycles +system.l2cache.demand_miss_latency::total 36334000 # number of demand (read+write) miss cycles +system.l2cache.overall_miss_latency::cpu.inst 23683000 # number of overall miss cycles +system.l2cache.overall_miss_latency::cpu.data 12651000 # number of overall miss cycles +system.l2cache.overall_miss_latency::total 36334000 # number of overall miss cycles system.l2cache.ReadExReq_accesses::cpu.data 43 # number of ReadExReq accesses(hits+misses) system.l2cache.ReadExReq_accesses::total 43 # number of ReadExReq accesses(hits+misses) system.l2cache.ReadSharedReq_accesses::cpu.inst 249 # number of ReadSharedReq accesses(hits+misses) @@ -736,17 +746,17 @@ system.l2cache.demand_miss_rate::total 0.897698 # mi system.l2cache.overall_miss_rate::cpu.inst 0.903614 # miss rate for overall accesses system.l2cache.overall_miss_rate::cpu.data 0.887324 # miss rate for overall accesses system.l2cache.overall_miss_rate::total 0.897698 # miss rate for overall accesses -system.l2cache.ReadExReq_avg_miss_latency::cpu.data 97046.511628 # average ReadExReq miss latency -system.l2cache.ReadExReq_avg_miss_latency::total 97046.511628 # average ReadExReq miss latency -system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 97893.333333 # average ReadSharedReq miss latency -system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 93445.783133 # average ReadSharedReq miss latency -system.l2cache.ReadSharedReq_avg_miss_latency::total 96694.805195 # average ReadSharedReq miss latency -system.l2cache.demand_avg_miss_latency::cpu.inst 97893.333333 # average overall miss latency -system.l2cache.demand_avg_miss_latency::cpu.data 94674.603175 # average overall miss latency -system.l2cache.demand_avg_miss_latency::total 96737.891738 # average overall miss latency -system.l2cache.overall_avg_miss_latency::cpu.inst 97893.333333 # average overall miss latency -system.l2cache.overall_avg_miss_latency::cpu.data 94674.603175 # average overall miss latency -system.l2cache.overall_avg_miss_latency::total 96737.891738 # average overall miss latency +system.l2cache.ReadExReq_avg_miss_latency::cpu.data 103186.046512 # average ReadExReq miss latency +system.l2cache.ReadExReq_avg_miss_latency::total 103186.046512 # average ReadExReq miss latency +system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 105257.777778 # average ReadSharedReq miss latency +system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 98963.855422 # average ReadSharedReq miss latency +system.l2cache.ReadSharedReq_avg_miss_latency::total 103561.688312 # average ReadSharedReq miss latency +system.l2cache.demand_avg_miss_latency::cpu.inst 105257.777778 # average overall miss latency +system.l2cache.demand_avg_miss_latency::cpu.data 100404.761905 # average overall miss latency +system.l2cache.demand_avg_miss_latency::total 103515.669516 # average overall miss latency +system.l2cache.overall_avg_miss_latency::cpu.inst 105257.777778 # average overall miss latency +system.l2cache.overall_avg_miss_latency::cpu.data 100404.761905 # average overall miss latency +system.l2cache.overall_avg_miss_latency::total 103515.669516 # average overall miss latency system.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -764,17 +774,17 @@ system.l2cache.demand_mshr_misses::total 351 # nu system.l2cache.overall_mshr_misses::cpu.inst 225 # number of overall MSHR misses system.l2cache.overall_mshr_misses::cpu.data 126 # number of overall MSHR misses system.l2cache.overall_mshr_misses::total 351 # number of overall MSHR misses -system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3313000 # number of ReadExReq MSHR miss cycles -system.l2cache.ReadExReq_mshr_miss_latency::total 3313000 # number of ReadExReq MSHR miss cycles -system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 17526000 # number of ReadSharedReq MSHR miss cycles -system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6096000 # number of ReadSharedReq MSHR miss cycles -system.l2cache.ReadSharedReq_mshr_miss_latency::total 23622000 # number of ReadSharedReq MSHR miss cycles -system.l2cache.demand_mshr_miss_latency::cpu.inst 17526000 # number of demand (read+write) MSHR miss cycles -system.l2cache.demand_mshr_miss_latency::cpu.data 9409000 # number of demand (read+write) MSHR miss cycles -system.l2cache.demand_mshr_miss_latency::total 26935000 # number of demand (read+write) MSHR miss cycles -system.l2cache.overall_mshr_miss_latency::cpu.inst 17526000 # number of overall MSHR miss cycles -system.l2cache.overall_mshr_miss_latency::cpu.data 9409000 # number of overall MSHR miss cycles -system.l2cache.overall_mshr_miss_latency::total 26935000 # number of overall MSHR miss cycles +system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3577000 # number of ReadExReq MSHR miss cycles +system.l2cache.ReadExReq_mshr_miss_latency::total 3577000 # number of ReadExReq MSHR miss cycles +system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 19183000 # number of ReadSharedReq MSHR miss cycles +system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6554000 # number of ReadSharedReq MSHR miss cycles +system.l2cache.ReadSharedReq_mshr_miss_latency::total 25737000 # number of ReadSharedReq MSHR miss cycles +system.l2cache.demand_mshr_miss_latency::cpu.inst 19183000 # number of demand (read+write) MSHR miss cycles +system.l2cache.demand_mshr_miss_latency::cpu.data 10131000 # number of demand (read+write) MSHR miss cycles +system.l2cache.demand_mshr_miss_latency::total 29314000 # number of demand (read+write) MSHR miss cycles +system.l2cache.overall_mshr_miss_latency::cpu.inst 19183000 # number of overall MSHR miss cycles +system.l2cache.overall_mshr_miss_latency::cpu.data 10131000 # number of overall MSHR miss cycles +system.l2cache.overall_mshr_miss_latency::total 29314000 # number of overall MSHR miss cycles system.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.inst 0.903614 # mshr miss rate for ReadSharedReq accesses @@ -786,24 +796,24 @@ system.l2cache.demand_mshr_miss_rate::total 0.897698 # system.l2cache.overall_mshr_miss_rate::cpu.inst 0.903614 # mshr miss rate for overall accesses system.l2cache.overall_mshr_miss_rate::cpu.data 0.887324 # mshr miss rate for overall accesses system.l2cache.overall_mshr_miss_rate::total 0.897698 # mshr miss rate for overall accesses -system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 77046.511628 # average ReadExReq mshr miss latency -system.l2cache.ReadExReq_avg_mshr_miss_latency::total 77046.511628 # average ReadExReq mshr miss latency -system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 77893.333333 # average ReadSharedReq mshr miss latency -system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73445.783133 # average ReadSharedReq mshr miss latency -system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76694.805195 # average ReadSharedReq mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 77893.333333 # average overall mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::cpu.data 74674.603175 # average overall mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::total 76737.891738 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 77893.333333 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::cpu.data 74674.603175 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::total 76737.891738 # average overall mshr miss latency +system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 83186.046512 # average ReadExReq mshr miss latency +system.l2cache.ReadExReq_avg_mshr_miss_latency::total 83186.046512 # average ReadExReq mshr miss latency +system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 85257.777778 # average ReadSharedReq mshr miss latency +system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 78963.855422 # average ReadSharedReq mshr miss latency +system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 83561.688312 # average ReadSharedReq mshr miss latency +system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 85257.777778 # average overall mshr miss latency +system.l2cache.demand_avg_mshr_miss_latency::cpu.data 80404.761905 # average overall mshr miss latency +system.l2cache.demand_avg_mshr_miss_latency::total 83515.669516 # average overall mshr miss latency +system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 85257.777778 # average overall mshr miss latency +system.l2cache.overall_avg_mshr_miss_latency::cpu.data 80404.761905 # average overall mshr miss latency +system.l2cache.overall_avg_mshr_miss_latency::total 83515.669516 # average overall mshr miss latency system.membus.snoop_filter.tot_requests 351 # Total number of requests made to the snoop filter. system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 50074000 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 52453000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 308 # Transaction distribution system.membus.trans_dist::ReadExReq 43 # Transaction distribution system.membus.trans_dist::ReadExResp 43 # Transaction distribution @@ -826,7 +836,7 @@ system.membus.snoop_fanout::max_value 0 # Re system.membus.snoop_fanout::total 351 # Request fanout histogram system.membus.reqLayer0.occupancy 351000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.7 # Layer utilization (%) -system.membus.respLayer0.occupancy 1865500 # Layer occupancy (ticks) -system.membus.respLayer0.utilization 3.7 # Layer utilization (%) +system.membus.respLayer0.occupancy 1866250 # Layer occupancy (ticks) +system.membus.respLayer0.utilization 3.6 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/config.ini b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/config.ini index de0268a39..3f1a37472 100644 --- a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/config.ini +++ b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/config.ini @@ -23,7 +23,7 @@ kernel_addr_check=true load_addr_mask=1099511627775 load_offset=0 mem_mode=timing -mem_ranges=0:536870911 +mem_ranges=0:536870911:0:0:0:0 memories=system.mem_ctrl mmap_using_noreserve=false multi_thread=false @@ -155,27 +155,27 @@ transition_latency=100000000 [system.mem_ctrl] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -195,6 +195,7 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 @@ -204,7 +205,7 @@ p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 page_policy=open_adaptive power_model=Null -range=0:536870911 +range=0:536870911:0:0:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 @@ -226,9 +227,9 @@ tRTW=2500 tWR=15000 tWTR=7500 tXAW=30000 -tXP=0 +tXP=6000 tXPDLL=0 -tXS=0 +tXS=270000 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 @@ -237,6 +238,7 @@ port=system.membus.master[0] [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -248,7 +250,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -256,3 +258,10 @@ width=16 master=system.mem_ctrl.port slave=system.cpu.icache_port system.cpu.dcache_port system.system_port +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + diff --git a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/simout b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/simout index 194a454d5..05f1fc1ff 100755 --- a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/simout +++ b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:23:13 -gem5 started Jul 21 2016 14:23:48 -gem5 executing on e108600-lin, pid 13288 +gem5 compiled Oct 13 2016 20:36:34 +gem5 started Oct 13 2016 20:36:59 +gem5 executing on e108600-lin, pid 36838 command line: /work/curdun01/gem5-external.hg/build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-simple -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-simple Global frequency set at 1000000000000 ticks per second @@ -13,4 +13,4 @@ Beginning simulation! info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello World! -Exiting @ tick 368887000 because target called exit() +Exiting @ tick 423127000 because target called exit() diff --git a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/stats.txt b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/stats.txt index 60c6ac279..b290494a3 100644 --- a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000377 # Number of seconds simulated -sim_ticks 376893000 # Number of ticks simulated -final_tick 376893000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000423 # Number of seconds simulated +sim_ticks 423127000 # Number of ticks simulated +final_tick 423127000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 173660 # Simulator instruction rate (inst/s) -host_op_rate 173583 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 11593149844 # Simulator tick rate (ticks/s) -host_mem_usage 632708 # Number of bytes of host memory used -host_seconds 0.03 # Real time elapsed on the host +host_inst_rate 243919 # Simulator instruction rate (inst/s) +host_op_rate 243782 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 18277293383 # Simulator tick rate (ticks/s) +host_mem_usage 631884 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host sim_insts 5641 # Number of instructions simulated sim_ops 5641 # Number of ops (including micro ops) simulated system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 376893000 # Cumulative time (in ticks) in various power states +system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 423127000 # Cumulative time (in ticks) in various power states system.mem_ctrl.bytes_read::cpu.inst 22568 # Number of bytes read from this memory system.mem_ctrl.bytes_read::cpu.data 4301 # Number of bytes read from this memory system.mem_ctrl.bytes_read::total 26869 # Number of bytes read from this memory @@ -26,27 +26,27 @@ system.mem_ctrl.num_reads::cpu.data 1135 # Nu system.mem_ctrl.num_reads::total 6777 # Number of read requests responded to by this memory system.mem_ctrl.num_writes::cpu.data 901 # Number of write requests responded to by this memory system.mem_ctrl.num_writes::total 901 # Number of write requests responded to by this memory -system.mem_ctrl.bw_read::cpu.inst 59879064 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::cpu.data 11411727 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::total 71290791 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::cpu.inst 59879064 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::total 59879064 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_write::cpu.data 9554436 # Write bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_write::total 9554436 # Write bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.inst 59879064 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.data 20966163 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::total 80845227 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_read::cpu.inst 53336232 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::cpu.data 10164797 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::total 63501029 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::cpu.inst 53336232 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::total 53336232 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_write::cpu.data 8510447 # Write bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_write::total 8510447 # Write bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.inst 53336232 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.data 18675244 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::total 72011476 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrl.readReqs 6778 # Number of read requests accepted system.mem_ctrl.writeReqs 901 # Number of write requests accepted system.mem_ctrl.readBursts 6778 # Number of DRAM read bursts, including those serviced by the write queue system.mem_ctrl.writeBursts 901 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrl.bytesReadDRAM 428096 # Total number of bytes read from DRAM -system.mem_ctrl.bytesReadWrQ 5696 # Total number of bytes read from write queue +system.mem_ctrl.bytesReadDRAM 427712 # Total number of bytes read from DRAM +system.mem_ctrl.bytesReadWrQ 6080 # Total number of bytes read from write queue system.mem_ctrl.bytesWritten 4096 # Total number of bytes written to DRAM system.mem_ctrl.bytesReadSys 26873 # Total read bytes from the system interface side system.mem_ctrl.bytesWrittenSys 3601 # Total written bytes from the system interface side -system.mem_ctrl.servicedByWrQ 89 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrl.mergedWrBursts 811 # Number of DRAM write bursts merged with an existing one +system.mem_ctrl.servicedByWrQ 95 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrl.mergedWrBursts 808 # Number of DRAM write bursts merged with an existing one system.mem_ctrl.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.mem_ctrl.perBankRdBursts::0 275 # Per bank write bursts system.mem_ctrl.perBankRdBursts::1 0 # Per bank write bursts @@ -55,14 +55,14 @@ system.mem_ctrl.perBankRdBursts::3 0 # Pe system.mem_ctrl.perBankRdBursts::4 215 # Per bank write bursts system.mem_ctrl.perBankRdBursts::5 18 # Per bank write bursts system.mem_ctrl.perBankRdBursts::6 105 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::7 519 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::7 516 # Per bank write bursts system.mem_ctrl.perBankRdBursts::8 543 # Per bank write bursts system.mem_ctrl.perBankRdBursts::9 1212 # Per bank write bursts system.mem_ctrl.perBankRdBursts::10 899 # Per bank write bursts system.mem_ctrl.perBankRdBursts::11 350 # Per bank write bursts system.mem_ctrl.perBankRdBursts::12 677 # Per bank write bursts system.mem_ctrl.perBankRdBursts::13 398 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::14 1429 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::14 1426 # Per bank write bursts system.mem_ctrl.perBankRdBursts::15 49 # Per bank write bursts system.mem_ctrl.perBankWrBursts::0 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::1 0 # Per bank write bursts @@ -71,18 +71,18 @@ system.mem_ctrl.perBankWrBursts::3 0 # Pe system.mem_ctrl.perBankWrBursts::4 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::5 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::6 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::7 8 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::7 5 # Per bank write bursts system.mem_ctrl.perBankWrBursts::8 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::9 7 # Per bank write bursts system.mem_ctrl.perBankWrBursts::10 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::11 2 # Per bank write bursts system.mem_ctrl.perBankWrBursts::12 30 # Per bank write bursts system.mem_ctrl.perBankWrBursts::13 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::14 14 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::15 3 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::14 19 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::15 1 # Per bank write bursts system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrl.totGap 376816000 # Total gap between requests +system.mem_ctrl.totGap 423050000 # Total gap between requests system.mem_ctrl.readPktSize::0 79 # Read request sizes (log2) system.mem_ctrl.readPktSize::1 1 # Read request sizes (log2) system.mem_ctrl.readPktSize::2 6698 # Read request sizes (log2) @@ -97,7 +97,7 @@ system.mem_ctrl.writePktSize::3 0 # Wr system.mem_ctrl.writePktSize::4 0 # Write request sizes (log2) system.mem_ctrl.writePktSize::5 0 # Write request sizes (log2) system.mem_ctrl.writePktSize::6 0 # Write request sizes (log2) -system.mem_ctrl.rdQLenPdf::0 6689 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::0 6683 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::1 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::2 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::3 0 # What read queue length does an incoming req see @@ -155,9 +155,9 @@ system.mem_ctrl.wrQLenPdf::22 5 # Wh system.mem_ctrl.wrQLenPdf::23 5 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::24 5 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::25 5 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::26 4 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::27 4 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::28 4 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::26 5 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::27 5 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::28 5 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::29 4 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::30 4 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::31 4 # What write queue length does an incoming req see @@ -193,26 +193,26 @@ system.mem_ctrl.wrQLenPdf::60 0 # Wh system.mem_ctrl.wrQLenPdf::61 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrl.bytesPerActivate::samples 838 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::mean 513.374702 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::gmean 298.080754 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::stdev 413.335022 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::0-127 263 31.38% 31.38% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::128-255 85 10.14% 41.53% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::256-383 42 5.01% 46.54% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::384-511 43 5.13% 51.67% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::512-639 44 5.25% 56.92% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::640-767 53 6.32% 63.25% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::768-895 15 1.79% 65.04% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::896-1023 22 2.63% 67.66% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::1024-1151 271 32.34% 100.00% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::total 838 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::samples 846 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::mean 508.141844 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::gmean 296.960814 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::stdev 409.521445 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::0-127 262 30.97% 30.97% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::128-255 81 9.57% 40.54% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::256-383 50 5.91% 46.45% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::384-511 56 6.62% 53.07% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::512-639 41 4.85% 57.92% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::640-767 45 5.32% 63.24% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::768-895 28 3.31% 66.55% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::896-1023 22 2.60% 69.15% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::1024-1151 261 30.85% 100.00% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::total 846 # Bytes accessed per row activation system.mem_ctrl.rdPerTurnAround::samples 4 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::mean 1522.250000 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::gmean 1505.224255 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::stdev 263.075876 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::1216-1279 1 25.00% 25.00% # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::1280-1343 1 25.00% 50.00% # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::mean 1385.500000 # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::gmean 1320.719140 # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::stdev 457.578044 # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::768-831 1 25.00% 25.00% # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::1216-1279 1 25.00% 50.00% # Reads before turning the bus around for writes system.mem_ctrl.rdPerTurnAround::1664-1727 1 25.00% 75.00% # Reads before turning the bus around for writes system.mem_ctrl.rdPerTurnAround::1792-1855 1 25.00% 100.00% # Reads before turning the bus around for writes system.mem_ctrl.rdPerTurnAround::total 4 # Reads before turning the bus around for writes @@ -221,57 +221,67 @@ system.mem_ctrl.wrPerTurnAround::mean 16 # Wr system.mem_ctrl.wrPerTurnAround::gmean 16.000000 # Writes before turning the bus around for reads system.mem_ctrl.wrPerTurnAround::16 4 100.00% 100.00% # Writes before turning the bus around for reads system.mem_ctrl.wrPerTurnAround::total 4 # Writes before turning the bus around for reads -system.mem_ctrl.totQLat 28198000 # Total ticks spent queuing -system.mem_ctrl.totMemAccLat 153616750 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrl.totBusLat 33445000 # Total ticks spent in databus transfers -system.mem_ctrl.avgQLat 4215.58 # Average queueing delay per DRAM burst +system.mem_ctrl.totQLat 74613750 # Total ticks spent queuing +system.mem_ctrl.totMemAccLat 199920000 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrl.totBusLat 33415000 # Total ticks spent in databus transfers +system.mem_ctrl.avgQLat 11164.71 # Average queueing delay per DRAM burst system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.mem_ctrl.avgMemAccLat 22965.58 # Average memory access latency per DRAM burst -system.mem_ctrl.avgRdBW 1135.86 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrl.avgWrBW 10.87 # Average achieved write bandwidth in MiByte/s -system.mem_ctrl.avgRdBWSys 71.30 # Average system read bandwidth in MiByte/s -system.mem_ctrl.avgWrBWSys 9.55 # Average system write bandwidth in MiByte/s +system.mem_ctrl.avgMemAccLat 29914.71 # Average memory access latency per DRAM burst +system.mem_ctrl.avgRdBW 1010.84 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrl.avgWrBW 9.68 # Average achieved write bandwidth in MiByte/s +system.mem_ctrl.avgRdBWSys 63.51 # Average system read bandwidth in MiByte/s +system.mem_ctrl.avgWrBWSys 8.51 # Average system write bandwidth in MiByte/s system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrl.busUtil 8.96 # Data bus utilization in percentage -system.mem_ctrl.busUtilRead 8.87 # Data bus utilization in percentage for reads +system.mem_ctrl.busUtil 7.97 # Data bus utilization in percentage +system.mem_ctrl.busUtilRead 7.90 # Data bus utilization in percentage for reads system.mem_ctrl.busUtilWrite 0.08 # Data bus utilization in percentage for writes system.mem_ctrl.avgRdQLen 1.00 # Average read queue length when enqueuing -system.mem_ctrl.avgWrQLen 23.23 # Average write queue length when enqueuing -system.mem_ctrl.readRowHits 5853 # Number of row buffer hits during reads +system.mem_ctrl.avgWrQLen 22.62 # Average write queue length when enqueuing +system.mem_ctrl.readRowHits 5839 # Number of row buffer hits during reads system.mem_ctrl.writeRowHits 57 # Number of row buffer hits during writes -system.mem_ctrl.readRowHitRate 87.50 # Row buffer hit rate for reads -system.mem_ctrl.writeRowHitRate 63.33 # Row buffer hit rate for writes -system.mem_ctrl.avgGap 49070.97 # Average gap between requests -system.mem_ctrl.pageHitRate 87.18 # Row buffer hit rate, read and write combined -system.mem_ctrl_0.actEnergy 1020600 # Energy for activate commands per rank (pJ) -system.mem_ctrl_0.preEnergy 556875 # Energy for precharge commands per rank (pJ) -system.mem_ctrl_0.readEnergy 8806200 # Energy for read commands per rank (pJ) -system.mem_ctrl_0.writeEnergy 51840 # Energy for write commands per rank (pJ) -system.mem_ctrl_0.refreshEnergy 24410880 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_0.actBackEnergy 141780375 # Energy for active background per rank (pJ) -system.mem_ctrl_0.preBackEnergy 100031250 # Energy for precharge background per rank (pJ) -system.mem_ctrl_0.totalEnergy 276658020 # Total energy per rank (pJ) -system.mem_ctrl_0.averagePower 739.727326 # Core power per rank (mW) -system.mem_ctrl_0.memoryStateTime::IDLE 165010500 # Time in different power states -system.mem_ctrl_0.memoryStateTime::REF 12480000 # Time in different power states -system.mem_ctrl_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrl_0.memoryStateTime::ACT 196602500 # Time in different power states -system.mem_ctrl_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrl_1.actEnergy 5299560 # Energy for activate commands per rank (pJ) -system.mem_ctrl_1.preEnergy 2891625 # Energy for precharge commands per rank (pJ) -system.mem_ctrl_1.readEnergy 42939000 # Energy for read commands per rank (pJ) -system.mem_ctrl_1.writeEnergy 362880 # Energy for write commands per rank (pJ) -system.mem_ctrl_1.refreshEnergy 24410880 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_1.actBackEnergy 252188235 # Energy for active background per rank (pJ) -system.mem_ctrl_1.preBackEnergy 3192750 # Energy for precharge background per rank (pJ) -system.mem_ctrl_1.totalEnergy 331284930 # Total energy per rank (pJ) -system.mem_ctrl_1.averagePower 885.747138 # Core power per rank (mW) -system.mem_ctrl_1.memoryStateTime::IDLE 2538750 # Time in different power states -system.mem_ctrl_1.memoryStateTime::REF 12480000 # Time in different power states -system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrl_1.memoryStateTime::ACT 359011750 # Time in different power states -system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 376893000 # Cumulative time (in ticks) in various power states +system.mem_ctrl.readRowHitRate 87.37 # Row buffer hit rate for reads +system.mem_ctrl.writeRowHitRate 61.29 # Row buffer hit rate for writes +system.mem_ctrl.avgGap 55091.81 # Average gap between requests +system.mem_ctrl.pageHitRate 87.01 # Row buffer hit rate, read and write combined +system.mem_ctrl_0.actEnergy 985320 # Energy for activate commands per rank (pJ) +system.mem_ctrl_0.preEnergy 519915 # Energy for precharge commands per rank (pJ) +system.mem_ctrl_0.readEnergy 8061060 # Energy for read commands per rank (pJ) +system.mem_ctrl_0.writeEnergy 26100 # Energy for write commands per rank (pJ) +system.mem_ctrl_0.refreshEnergy 33190560.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrl_0.actBackEnergy 21232500 # Energy for active background per rank (pJ) +system.mem_ctrl_0.preBackEnergy 1932000 # Energy for precharge background per rank (pJ) +system.mem_ctrl_0.actPowerDownEnergy 84890100 # Energy for active power-down per rank (pJ) +system.mem_ctrl_0.prePowerDownEnergy 43723680 # Energy for precharge power-down per rank (pJ) +system.mem_ctrl_0.selfRefreshEnergy 22684200 # Energy for self refresh per rank (pJ) +system.mem_ctrl_0.totalEnergy 217245435 # Total energy per rank (pJ) +system.mem_ctrl_0.averagePower 513.427832 # Core power per rank (mW) +system.mem_ctrl_0.totalIdleTime 369366500 # Total Idle time Per DRAM Rank +system.mem_ctrl_0.memoryStateTime::IDLE 2976000 # Time in different power states +system.mem_ctrl_0.memoryStateTime::REF 14106000 # Time in different power states +system.mem_ctrl_0.memoryStateTime::SREF 71507250 # Time in different power states +system.mem_ctrl_0.memoryStateTime::PRE_PDN 113857500 # Time in different power states +system.mem_ctrl_0.memoryStateTime::ACT 34569250 # Time in different power states +system.mem_ctrl_0.memoryStateTime::ACT_PDN 186111000 # Time in different power states +system.mem_ctrl_1.actEnergy 5090820 # Energy for activate commands per rank (pJ) +system.mem_ctrl_1.preEnergy 2690655 # Energy for precharge commands per rank (pJ) +system.mem_ctrl_1.readEnergy 39648420 # Energy for read commands per rank (pJ) +system.mem_ctrl_1.writeEnergy 307980 # Energy for write commands per rank (pJ) +system.mem_ctrl_1.refreshEnergy 33190560.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrl_1.actBackEnergy 77391750 # Energy for active background per rank (pJ) +system.mem_ctrl_1.preBackEnergy 1169760 # Energy for precharge background per rank (pJ) +system.mem_ctrl_1.actPowerDownEnergy 113578770 # Energy for active power-down per rank (pJ) +system.mem_ctrl_1.prePowerDownEnergy 493920 # Energy for precharge power-down per rank (pJ) +system.mem_ctrl_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrl_1.totalEnergy 273562635 # Total energy per rank (pJ) +system.mem_ctrl_1.averagePower 646.525303 # Core power per rank (mW) +system.mem_ctrl_1.totalIdleTime 250424500 # Total Idle time Per DRAM Rank +system.mem_ctrl_1.memoryStateTime::IDLE 900000 # Time in different power states +system.mem_ctrl_1.memoryStateTime::REF 14040000 # Time in different power states +system.mem_ctrl_1.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrl_1.memoryStateTime::PRE_PDN 1291250 # Time in different power states +system.mem_ctrl_1.memoryStateTime::ACT 157762500 # Time in different power states +system.mem_ctrl_1.memoryStateTime::ACT_PDN 249133250 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 423127000 # Cumulative time (in ticks) in various power states system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.read_accesses 0 # DTB read accesses @@ -291,8 +301,8 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 7 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 376893000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 376893 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 423127000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 423127 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 5641 # Number of instructions committed @@ -311,7 +321,7 @@ system.cpu.num_mem_refs 2037 # nu system.cpu.num_load_insts 1135 # Number of load instructions system.cpu.num_store_insts 902 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 376893 # Number of busy cycles +system.cpu.num_busy_cycles 423127 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 886 # Number of branches fetched @@ -356,7 +366,7 @@ system.membus.snoop_filter.hit_multi_requests 0 system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 376893000 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 423127000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 6778 # Transaction distribution system.membus.trans_dist::ReadResp 6777 # Transaction distribution system.membus.trans_dist::WriteReq 901 # Transaction distribution @@ -380,10 +390,10 @@ system.membus.snoop_fanout::min_value 0 # Re system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 7679 # Request fanout histogram system.membus.reqLayer0.occupancy 8580000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.3 # Layer utilization (%) -system.membus.respLayer0.occupancy 12853500 # Layer occupancy (ticks) -system.membus.respLayer0.utilization 3.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 3555500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.9 # Layer utilization (%) +system.membus.reqLayer0.utilization 2.0 # Layer utilization (%) +system.membus.respLayer0.occupancy 12855500 # Layer occupancy (ticks) +system.membus.respLayer0.utilization 3.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 3550250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.8 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/config.ini b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/config.ini index cf4a132b7..4bc508e65 100644 --- a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/config.ini +++ b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/config.ini @@ -23,7 +23,7 @@ kernel_addr_check=true load_addr_mask=1099511627775 load_offset=0 mem_mode=timing -mem_ranges=0:536870911 +mem_ranges=0:536870911:0:0:0:0 memories=system.mem_ctrl mmap_using_noreserve=false multi_thread=false @@ -100,7 +100,7 @@ icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.clk_domain clusivity=mostly_incl @@ -151,7 +151,7 @@ size=64 [system.cpu.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.clk_domain clusivity=mostly_incl @@ -277,7 +277,7 @@ system=system [system.l2cache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.clk_domain clusivity=mostly_incl @@ -322,27 +322,27 @@ size=262144 [system.mem_ctrl] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -362,6 +362,7 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 @@ -371,7 +372,7 @@ p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 page_policy=open_adaptive power_model=Null -range=0:536870911 +range=0:536870911:0:0:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 @@ -393,9 +394,9 @@ tRTW=2500 tWR=15000 tWTR=7500 tXAW=30000 -tXP=0 +tXP=6000 tXPDLL=0 -tXS=0 +tXS=270000 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 @@ -404,6 +405,7 @@ port=system.membus.master[0] [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -415,7 +417,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -423,3 +425,10 @@ width=16 master=system.mem_ctrl.port slave=system.l2cache.mem_side system.system_port +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + diff --git a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/simout b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/simout index 760ae9b2e..26dbf1e79 100755 --- a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/simout +++ b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:23:13 -gem5 started Jul 21 2016 14:23:48 -gem5 executing on e108600-lin, pid 13287 +gem5 compiled Oct 13 2016 20:36:34 +gem5 started Oct 13 2016 20:36:59 +gem5 executing on e108600-lin, pid 36839 command line: /work/curdun01/gem5-external.hg/build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-two-level -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-two-level Global frequency set at 1000000000000 ticks per second @@ -13,4 +13,4 @@ Beginning simulation! info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello World! -Exiting @ tick 58892000 because target called exit() +Exiting @ tick 62333000 because target called exit() diff --git a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/stats.txt b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/stats.txt index 27ea6dc01..3bd6c6ff6 100644 --- a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000059 # Number of seconds simulated -sim_ticks 59115000 # Number of ticks simulated -final_tick 59115000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000062 # Number of seconds simulated +sim_ticks 62333000 # Number of ticks simulated +final_tick 62333000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 219311 # Simulator instruction rate (inst/s) -host_op_rate 219196 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2295881155 # Simulator tick rate (ticks/s) -host_mem_usage 637060 # Number of bytes of host memory used -host_seconds 0.03 # Real time elapsed on the host +host_inst_rate 499257 # Simulator instruction rate (inst/s) +host_op_rate 498740 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5505866075 # Simulator tick rate (ticks/s) +host_mem_usage 635976 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 5641 # Number of instructions simulated sim_ops 5641 # Number of ops (including micro ops) simulated system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 59115000 # Cumulative time (in ticks) in various power states +system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 62333000 # Cumulative time (in ticks) in various power states system.mem_ctrl.bytes_read::cpu.inst 18752 # Number of bytes read from this memory system.mem_ctrl.bytes_read::cpu.data 8768 # Number of bytes read from this memory system.mem_ctrl.bytes_read::total 27520 # Number of bytes read from this memory @@ -22,14 +22,14 @@ system.mem_ctrl.bytes_inst_read::total 18752 # Nu system.mem_ctrl.num_reads::cpu.inst 293 # Number of read requests responded to by this memory system.mem_ctrl.num_reads::cpu.data 137 # Number of read requests responded to by this memory system.mem_ctrl.num_reads::total 430 # Number of read requests responded to by this memory -system.mem_ctrl.bw_read::cpu.inst 317212213 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::cpu.data 148321069 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::total 465533283 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::cpu.inst 317212213 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::total 317212213 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.inst 317212213 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.data 148321069 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::total 465533283 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_read::cpu.inst 300835833 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::cpu.data 140663854 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::total 441499687 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::cpu.inst 300835833 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::total 300835833 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.inst 300835833 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.data 140663854 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::total 441499687 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrl.readReqs 430 # Number of read requests accepted system.mem_ctrl.writeReqs 0 # Number of write requests accepted system.mem_ctrl.readBursts 430 # Number of DRAM read bursts, including those serviced by the write queue @@ -76,7 +76,7 @@ system.mem_ctrl.perBankWrBursts::14 0 # Pe system.mem_ctrl.perBankWrBursts::15 0 # Per bank write bursts system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrl.totGap 58984000 # Total gap between requests +system.mem_ctrl.totGap 62196000 # Total gap between requests system.mem_ctrl.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrl.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrl.readPktSize::2 0 # Read request sizes (log2) @@ -187,70 +187,81 @@ system.mem_ctrl.wrQLenPdf::60 0 # Wh system.mem_ctrl.wrQLenPdf::61 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrl.bytesPerActivate::samples 110 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::mean 237.963636 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::gmean 174.172417 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::stdev 212.375811 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::0-127 28 25.45% 25.45% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::128-255 42 38.18% 63.64% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::256-383 19 17.27% 80.91% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::384-511 8 7.27% 88.18% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::512-639 4 3.64% 91.82% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::640-767 4 3.64% 95.45% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::768-895 2 1.82% 97.27% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::1024-1151 3 2.73% 100.00% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::total 110 # Bytes accessed per row activation -system.mem_ctrl.totQLat 3632500 # Total ticks spent queuing -system.mem_ctrl.totMemAccLat 11695000 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrl.bytesPerActivate::samples 113 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::mean 241.840708 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::gmean 173.064480 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::stdev 223.138673 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::0-127 30 26.55% 26.55% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::128-255 41 36.28% 62.83% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::256-383 20 17.70% 80.53% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::384-511 8 7.08% 87.61% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::512-639 5 4.42% 92.04% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::640-767 2 1.77% 93.81% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::768-895 3 2.65% 96.46% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::896-1023 1 0.88% 97.35% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::1024-1151 3 2.65% 100.00% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::total 113 # Bytes accessed per row activation +system.mem_ctrl.totQLat 6850250 # Total ticks spent queuing +system.mem_ctrl.totMemAccLat 14912750 # Total ticks spent from burst creation until serviced by the DRAM system.mem_ctrl.totBusLat 2150000 # Total ticks spent in databus transfers -system.mem_ctrl.avgQLat 8447.67 # Average queueing delay per DRAM burst +system.mem_ctrl.avgQLat 15930.81 # Average queueing delay per DRAM burst system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.mem_ctrl.avgMemAccLat 27197.67 # Average memory access latency per DRAM burst -system.mem_ctrl.avgRdBW 465.53 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrl.avgMemAccLat 34680.81 # Average memory access latency per DRAM burst +system.mem_ctrl.avgRdBW 441.50 # Average DRAM read bandwidth in MiByte/s system.mem_ctrl.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.mem_ctrl.avgRdBWSys 465.53 # Average system read bandwidth in MiByte/s +system.mem_ctrl.avgRdBWSys 441.50 # Average system read bandwidth in MiByte/s system.mem_ctrl.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrl.busUtil 3.64 # Data bus utilization in percentage -system.mem_ctrl.busUtilRead 3.64 # Data bus utilization in percentage for reads +system.mem_ctrl.busUtil 3.45 # Data bus utilization in percentage +system.mem_ctrl.busUtilRead 3.45 # Data bus utilization in percentage for reads system.mem_ctrl.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.mem_ctrl.avgRdQLen 1.00 # Average read queue length when enqueuing system.mem_ctrl.avgWrQLen 0.00 # Average write queue length when enqueuing -system.mem_ctrl.readRowHits 315 # Number of row buffer hits during reads +system.mem_ctrl.readRowHits 316 # Number of row buffer hits during reads system.mem_ctrl.writeRowHits 0 # Number of row buffer hits during writes -system.mem_ctrl.readRowHitRate 73.26 # Row buffer hit rate for reads +system.mem_ctrl.readRowHitRate 73.49 # Row buffer hit rate for reads system.mem_ctrl.writeRowHitRate nan # Row buffer hit rate for writes -system.mem_ctrl.avgGap 137172.09 # Average gap between requests -system.mem_ctrl.pageHitRate 73.26 # Row buffer hit rate, read and write combined -system.mem_ctrl_0.actEnergy 196560 # Energy for activate commands per rank (pJ) -system.mem_ctrl_0.preEnergy 107250 # Energy for precharge commands per rank (pJ) -system.mem_ctrl_0.readEnergy 670800 # Energy for read commands per rank (pJ) +system.mem_ctrl.avgGap 144641.86 # Average gap between requests +system.mem_ctrl.pageHitRate 73.49 # Row buffer hit rate, read and write combined +system.mem_ctrl_0.actEnergy 192780 # Energy for activate commands per rank (pJ) +system.mem_ctrl_0.preEnergy 98670 # Energy for precharge commands per rank (pJ) +system.mem_ctrl_0.readEnergy 671160 # Energy for read commands per rank (pJ) system.mem_ctrl_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.mem_ctrl_0.refreshEnergy 3559920 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_0.actBackEnergy 25637175 # Energy for active background per rank (pJ) -system.mem_ctrl_0.preBackEnergy 10369500 # Energy for precharge background per rank (pJ) -system.mem_ctrl_0.totalEnergy 40541205 # Total energy per rank (pJ) -system.mem_ctrl_0.averagePower 740.292712 # Core power per rank (mW) -system.mem_ctrl_0.memoryStateTime::IDLE 17115500 # Time in different power states -system.mem_ctrl_0.memoryStateTime::REF 1820000 # Time in different power states -system.mem_ctrl_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrl_0.memoryStateTime::ACT 35842000 # Time in different power states -system.mem_ctrl_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrl_1.actEnergy 612360 # Energy for activate commands per rank (pJ) -system.mem_ctrl_1.preEnergy 334125 # Energy for precharge commands per rank (pJ) -system.mem_ctrl_1.readEnergy 2425800 # Energy for read commands per rank (pJ) +system.mem_ctrl_0.refreshEnergy 4917120.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrl_0.actBackEnergy 2176830 # Energy for active background per rank (pJ) +system.mem_ctrl_0.preBackEnergy 210240 # Energy for precharge background per rank (pJ) +system.mem_ctrl_0.actPowerDownEnergy 19527630 # Energy for active power-down per rank (pJ) +system.mem_ctrl_0.prePowerDownEnergy 3815040 # Energy for precharge power-down per rank (pJ) +system.mem_ctrl_0.selfRefreshEnergy 1573140 # Energy for self refresh per rank (pJ) +system.mem_ctrl_0.totalEnergy 33182610 # Total energy per rank (pJ) +system.mem_ctrl_0.averagePower 532.337778 # Core power per rank (mW) +system.mem_ctrl_0.totalIdleTime 56494000 # Total Idle time Per DRAM Rank +system.mem_ctrl_0.memoryStateTime::IDLE 323000 # Time in different power states +system.mem_ctrl_0.memoryStateTime::REF 2086000 # Time in different power states +system.mem_ctrl_0.memoryStateTime::SREF 4253250 # Time in different power states +system.mem_ctrl_0.memoryStateTime::PRE_PDN 9935000 # Time in different power states +system.mem_ctrl_0.memoryStateTime::ACT 2911750 # Time in different power states +system.mem_ctrl_0.memoryStateTime::ACT_PDN 42824000 # Time in different power states +system.mem_ctrl_1.actEnergy 621180 # Energy for activate commands per rank (pJ) +system.mem_ctrl_1.preEnergy 330165 # Energy for precharge commands per rank (pJ) +system.mem_ctrl_1.readEnergy 2399040 # Energy for read commands per rank (pJ) system.mem_ctrl_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.mem_ctrl_1.refreshEnergy 3559920 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_1.actBackEnergy 37236105 # Energy for active background per rank (pJ) -system.mem_ctrl_1.preBackEnergy 195000 # Energy for precharge background per rank (pJ) -system.mem_ctrl_1.totalEnergy 44363310 # Total energy per rank (pJ) -system.mem_ctrl_1.averagePower 810.085321 # Core power per rank (mW) -system.mem_ctrl_1.memoryStateTime::IDLE 336500 # Time in different power states -system.mem_ctrl_1.memoryStateTime::REF 1820000 # Time in different power states -system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrl_1.memoryStateTime::ACT 52811500 # Time in different power states -system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 59115000 # Cumulative time (in ticks) in various power states +system.mem_ctrl_1.refreshEnergy 4917120.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrl_1.actBackEnergy 5632170 # Energy for active background per rank (pJ) +system.mem_ctrl_1.preBackEnergy 168480 # Energy for precharge background per rank (pJ) +system.mem_ctrl_1.actPowerDownEnergy 22617030 # Energy for active power-down per rank (pJ) +system.mem_ctrl_1.prePowerDownEnergy 64320 # Energy for precharge power-down per rank (pJ) +system.mem_ctrl_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrl_1.totalEnergy 36749505 # Total energy per rank (pJ) +system.mem_ctrl_1.averagePower 587.463363 # Core power per rank (mW) +system.mem_ctrl_1.totalIdleTime 49768000 # Total Idle time Per DRAM Rank +system.mem_ctrl_1.memoryStateTime::IDLE 176000 # Time in different power states +system.mem_ctrl_1.memoryStateTime::REF 1843250 # Time in different power states +system.mem_ctrl_1.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrl_1.memoryStateTime::PRE_PDN 167500 # Time in different power states +system.mem_ctrl_1.memoryStateTime::ACT 10545750 # Time in different power states +system.mem_ctrl_1.memoryStateTime::ACT_PDN 49600500 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 62333000 # Cumulative time (in ticks) in various power states system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.read_accesses 0 # DTB read accesses @@ -270,8 +281,8 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 7 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 59115000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 59115 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 62333000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 62333 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 5641 # Number of instructions committed @@ -290,7 +301,7 @@ system.cpu.num_mem_refs 2037 # nu system.cpu.num_load_insts 1135 # Number of load instructions system.cpu.num_store_insts 902 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 59115 # Number of busy cycles +system.cpu.num_busy_cycles 62333 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 886 # Number of branches fetched @@ -329,23 +340,23 @@ system.cpu.op_class::MemWrite 902 15.99% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 5642 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 59115000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 62333000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 86.123929 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 86.045434 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1899 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 137 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 13.861314 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 86.123929 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.084105 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.084105 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 86.045434 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.084029 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.084029 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 137 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.133789 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 4209 # Number of tag accesses system.cpu.dcache.tags.data_accesses 4209 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 59115000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 62333000 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 1048 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1048 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 851 # number of WriteReq hits @@ -362,14 +373,14 @@ system.cpu.dcache.demand_misses::cpu.data 137 # n system.cpu.dcache.demand_misses::total 137 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 137 # number of overall misses system.cpu.dcache.overall_misses::total 137 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 9045000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 9045000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 5476000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 5476000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 14521000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 14521000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 14521000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 14521000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 10089000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 10089000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 5605000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 5605000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 15694000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 15694000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 15694000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 15694000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1135 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1135 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 901 # number of WriteReq accesses(hits+misses) @@ -386,14 +397,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.067289 system.cpu.dcache.demand_miss_rate::total 0.067289 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.067289 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.067289 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 103965.517241 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 103965.517241 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 109520 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 109520 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 105992.700730 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 105992.700730 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 105992.700730 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 105992.700730 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 115965.517241 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 115965.517241 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 112100 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 112100 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 114554.744526 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 114554.744526 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 114554.744526 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 114554.744526 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -408,14 +419,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 137 system.cpu.dcache.demand_mshr_misses::total 137 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 137 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 137 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8871000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 8871000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5376000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5376000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14247000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 14247000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14247000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 14247000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9915000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 9915000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5505000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5505000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15420000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 15420000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15420000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 15420000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076652 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076652 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055494 # mshr miss rate for WriteReq accesses @@ -424,31 +435,31 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.067289 system.cpu.dcache.demand_mshr_miss_rate::total 0.067289 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.067289 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.067289 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 101965.517241 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 101965.517241 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 107520 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 107520 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 103992.700730 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 103992.700730 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 103992.700730 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 103992.700730 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 59115000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 113965.517241 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 113965.517241 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 110100 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 110100 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 112554.744526 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 112554.744526 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 112554.744526 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 112554.744526 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 62333000 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 94 # number of replacements -system.cpu.icache.tags.tagsinuse 109.937395 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 109.768952 # Cycle average of tags in use system.cpu.icache.tags.total_refs 5346 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 297 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 18 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 109.937395 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.429443 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.429443 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 109.768952 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.428785 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.428785 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 203 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 140 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 141 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.792969 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 11583 # Number of tag accesses system.cpu.icache.tags.data_accesses 11583 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 59115000 # Cumulative time (in ticks) in various power states +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 62333000 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 5346 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 5346 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 5346 # number of demand (read+write) hits @@ -461,12 +472,12 @@ system.cpu.icache.demand_misses::cpu.inst 297 # n system.cpu.icache.demand_misses::total 297 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 297 # number of overall misses system.cpu.icache.overall_misses::total 297 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 30106000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 30106000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 30106000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 30106000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 30106000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 30106000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 32151000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 32151000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 32151000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 32151000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 32151000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 32151000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 5643 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 5643 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 5643 # number of demand (read+write) accesses @@ -479,12 +490,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.052632 system.cpu.icache.demand_miss_rate::total 0.052632 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.052632 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.052632 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 101367.003367 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 101367.003367 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 101367.003367 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 101367.003367 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 101367.003367 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 101367.003367 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 108252.525253 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 108252.525253 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 108252.525253 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 108252.525253 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 108252.525253 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 108252.525253 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -497,31 +508,31 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 297 system.cpu.icache.demand_mshr_misses::total 297 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 297 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 297 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 29512000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 29512000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 29512000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 29512000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 29512000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 29512000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 31557000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 31557000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 31557000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 31557000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 31557000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 31557000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.052632 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.052632 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.052632 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.052632 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.052632 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.052632 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 99367.003367 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 99367.003367 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 99367.003367 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 99367.003367 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 99367.003367 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 99367.003367 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 106252.525253 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 106252.525253 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 106252.525253 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 106252.525253 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 106252.525253 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 106252.525253 # average overall mshr miss latency system.l2bus.snoop_filter.tot_requests 528 # Total number of requests made to the snoop filter. system.l2bus.snoop_filter.hit_single_requests 94 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.l2bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.l2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.l2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.l2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.l2bus.pwrStateResidencyTicks::UNDEFINED 59115000 # Cumulative time (in ticks) in various power states +system.l2bus.pwrStateResidencyTicks::UNDEFINED 62333000 # Cumulative time (in ticks) in various power states system.l2bus.trans_dist::ReadResp 384 # Transaction distribution system.l2bus.trans_dist::CleanEvict 94 # Transaction distribution system.l2bus.trans_dist::ReadExReq 50 # Transaction distribution @@ -547,30 +558,30 @@ system.l2bus.snoop_fanout::min_value 0 # Re system.l2bus.snoop_fanout::max_value 0 # Request fanout histogram system.l2bus.snoop_fanout::total 434 # Request fanout histogram system.l2bus.reqLayer0.occupancy 528000 # Layer occupancy (ticks) -system.l2bus.reqLayer0.utilization 0.9 # Layer utilization (%) +system.l2bus.reqLayer0.utilization 0.8 # Layer utilization (%) system.l2bus.respLayer0.occupancy 891000 # Layer occupancy (ticks) -system.l2bus.respLayer0.utilization 1.5 # Layer utilization (%) +system.l2bus.respLayer0.utilization 1.4 # Layer utilization (%) system.l2bus.respLayer1.occupancy 411000 # Layer occupancy (ticks) system.l2bus.respLayer1.utilization 0.7 # Layer utilization (%) -system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 59115000 # Cumulative time (in ticks) in various power states +system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 62333000 # Cumulative time (in ticks) in various power states system.l2cache.tags.replacements 0 # number of replacements -system.l2cache.tags.tagsinuse 216.263710 # Cycle average of tags in use +system.l2cache.tags.tagsinuse 215.766788 # Cycle average of tags in use system.l2cache.tags.total_refs 98 # Total number of references to valid blocks. system.l2cache.tags.sampled_refs 430 # Sample count of references to valid blocks. system.l2cache.tags.avg_refs 0.227907 # Average number of references to valid blocks. system.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2cache.tags.occ_blocks::cpu.inst 130.091113 # Average occupied blocks per requestor -system.l2cache.tags.occ_blocks::cpu.data 86.172597 # Average occupied blocks per requestor -system.l2cache.tags.occ_percent::cpu.inst 0.031761 # Average percentage of cache occupancy -system.l2cache.tags.occ_percent::cpu.data 0.021038 # Average percentage of cache occupancy -system.l2cache.tags.occ_percent::total 0.052799 # Average percentage of cache occupancy +system.l2cache.tags.occ_blocks::cpu.inst 129.675199 # Average occupied blocks per requestor +system.l2cache.tags.occ_blocks::cpu.data 86.091590 # Average occupied blocks per requestor +system.l2cache.tags.occ_percent::cpu.inst 0.031659 # Average percentage of cache occupancy +system.l2cache.tags.occ_percent::cpu.data 0.021018 # Average percentage of cache occupancy +system.l2cache.tags.occ_percent::total 0.052677 # Average percentage of cache occupancy system.l2cache.tags.occ_task_id_blocks::1024 430 # Occupied blocks per task id -system.l2cache.tags.age_task_id_blocks_1024::0 76 # Occupied blocks per task id -system.l2cache.tags.age_task_id_blocks_1024::1 354 # Occupied blocks per task id +system.l2cache.tags.age_task_id_blocks_1024::0 74 # Occupied blocks per task id +system.l2cache.tags.age_task_id_blocks_1024::1 356 # Occupied blocks per task id system.l2cache.tags.occ_task_id_percent::1024 0.104980 # Percentage of cache occupancy per task id system.l2cache.tags.tag_accesses 4654 # Number of tag accesses system.l2cache.tags.data_accesses 4654 # Number of data accesses -system.l2cache.pwrStateResidencyTicks::UNDEFINED 59115000 # Cumulative time (in ticks) in various power states +system.l2cache.pwrStateResidencyTicks::UNDEFINED 62333000 # Cumulative time (in ticks) in various power states system.l2cache.ReadSharedReq_hits::cpu.inst 4 # number of ReadSharedReq hits system.l2cache.ReadSharedReq_hits::total 4 # number of ReadSharedReq hits system.l2cache.demand_hits::cpu.inst 4 # number of demand (read+write) hits @@ -588,17 +599,17 @@ system.l2cache.demand_misses::total 430 # nu system.l2cache.overall_misses::cpu.inst 293 # number of overall misses system.l2cache.overall_misses::cpu.data 137 # number of overall misses system.l2cache.overall_misses::total 430 # number of overall misses -system.l2cache.ReadExReq_miss_latency::cpu.data 5226000 # number of ReadExReq miss cycles -system.l2cache.ReadExReq_miss_latency::total 5226000 # number of ReadExReq miss cycles -system.l2cache.ReadSharedReq_miss_latency::cpu.inst 28537000 # number of ReadSharedReq miss cycles -system.l2cache.ReadSharedReq_miss_latency::cpu.data 8610000 # number of ReadSharedReq miss cycles -system.l2cache.ReadSharedReq_miss_latency::total 37147000 # number of ReadSharedReq miss cycles -system.l2cache.demand_miss_latency::cpu.inst 28537000 # number of demand (read+write) miss cycles -system.l2cache.demand_miss_latency::cpu.data 13836000 # number of demand (read+write) miss cycles -system.l2cache.demand_miss_latency::total 42373000 # number of demand (read+write) miss cycles -system.l2cache.overall_miss_latency::cpu.inst 28537000 # number of overall miss cycles -system.l2cache.overall_miss_latency::cpu.data 13836000 # number of overall miss cycles -system.l2cache.overall_miss_latency::total 42373000 # number of overall miss cycles +system.l2cache.ReadExReq_miss_latency::cpu.data 5355000 # number of ReadExReq miss cycles +system.l2cache.ReadExReq_miss_latency::total 5355000 # number of ReadExReq miss cycles +system.l2cache.ReadSharedReq_miss_latency::cpu.inst 30582000 # number of ReadSharedReq miss cycles +system.l2cache.ReadSharedReq_miss_latency::cpu.data 9654000 # number of ReadSharedReq miss cycles +system.l2cache.ReadSharedReq_miss_latency::total 40236000 # number of ReadSharedReq miss cycles +system.l2cache.demand_miss_latency::cpu.inst 30582000 # number of demand (read+write) miss cycles +system.l2cache.demand_miss_latency::cpu.data 15009000 # number of demand (read+write) miss cycles +system.l2cache.demand_miss_latency::total 45591000 # number of demand (read+write) miss cycles +system.l2cache.overall_miss_latency::cpu.inst 30582000 # number of overall miss cycles +system.l2cache.overall_miss_latency::cpu.data 15009000 # number of overall miss cycles +system.l2cache.overall_miss_latency::total 45591000 # number of overall miss cycles system.l2cache.ReadExReq_accesses::cpu.data 50 # number of ReadExReq accesses(hits+misses) system.l2cache.ReadExReq_accesses::total 50 # number of ReadExReq accesses(hits+misses) system.l2cache.ReadSharedReq_accesses::cpu.inst 297 # number of ReadSharedReq accesses(hits+misses) @@ -621,17 +632,17 @@ system.l2cache.demand_miss_rate::total 0.990783 # mi system.l2cache.overall_miss_rate::cpu.inst 0.986532 # miss rate for overall accesses system.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.l2cache.overall_miss_rate::total 0.990783 # miss rate for overall accesses -system.l2cache.ReadExReq_avg_miss_latency::cpu.data 104520 # average ReadExReq miss latency -system.l2cache.ReadExReq_avg_miss_latency::total 104520 # average ReadExReq miss latency -system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 97395.904437 # average ReadSharedReq miss latency -system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 98965.517241 # average ReadSharedReq miss latency -system.l2cache.ReadSharedReq_avg_miss_latency::total 97755.263158 # average ReadSharedReq miss latency -system.l2cache.demand_avg_miss_latency::cpu.inst 97395.904437 # average overall miss latency -system.l2cache.demand_avg_miss_latency::cpu.data 100992.700730 # average overall miss latency -system.l2cache.demand_avg_miss_latency::total 98541.860465 # average overall miss latency -system.l2cache.overall_avg_miss_latency::cpu.inst 97395.904437 # average overall miss latency -system.l2cache.overall_avg_miss_latency::cpu.data 100992.700730 # average overall miss latency -system.l2cache.overall_avg_miss_latency::total 98541.860465 # average overall miss latency +system.l2cache.ReadExReq_avg_miss_latency::cpu.data 107100 # average ReadExReq miss latency +system.l2cache.ReadExReq_avg_miss_latency::total 107100 # average ReadExReq miss latency +system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 104375.426621 # average ReadSharedReq miss latency +system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 110965.517241 # average ReadSharedReq miss latency +system.l2cache.ReadSharedReq_avg_miss_latency::total 105884.210526 # average ReadSharedReq miss latency +system.l2cache.demand_avg_miss_latency::cpu.inst 104375.426621 # average overall miss latency +system.l2cache.demand_avg_miss_latency::cpu.data 109554.744526 # average overall miss latency +system.l2cache.demand_avg_miss_latency::total 106025.581395 # average overall miss latency +system.l2cache.overall_avg_miss_latency::cpu.inst 104375.426621 # average overall miss latency +system.l2cache.overall_avg_miss_latency::cpu.data 109554.744526 # average overall miss latency +system.l2cache.overall_avg_miss_latency::total 106025.581395 # average overall miss latency system.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -649,17 +660,17 @@ system.l2cache.demand_mshr_misses::total 430 # nu system.l2cache.overall_mshr_misses::cpu.inst 293 # number of overall MSHR misses system.l2cache.overall_mshr_misses::cpu.data 137 # number of overall MSHR misses system.l2cache.overall_mshr_misses::total 430 # number of overall MSHR misses -system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4226000 # number of ReadExReq MSHR miss cycles -system.l2cache.ReadExReq_mshr_miss_latency::total 4226000 # number of ReadExReq MSHR miss cycles -system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 22677000 # number of ReadSharedReq MSHR miss cycles -system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6870000 # number of ReadSharedReq MSHR miss cycles -system.l2cache.ReadSharedReq_mshr_miss_latency::total 29547000 # number of ReadSharedReq MSHR miss cycles -system.l2cache.demand_mshr_miss_latency::cpu.inst 22677000 # number of demand (read+write) MSHR miss cycles -system.l2cache.demand_mshr_miss_latency::cpu.data 11096000 # number of demand (read+write) MSHR miss cycles -system.l2cache.demand_mshr_miss_latency::total 33773000 # number of demand (read+write) MSHR miss cycles -system.l2cache.overall_mshr_miss_latency::cpu.inst 22677000 # number of overall MSHR miss cycles -system.l2cache.overall_mshr_miss_latency::cpu.data 11096000 # number of overall MSHR miss cycles -system.l2cache.overall_mshr_miss_latency::total 33773000 # number of overall MSHR miss cycles +system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4355000 # number of ReadExReq MSHR miss cycles +system.l2cache.ReadExReq_mshr_miss_latency::total 4355000 # number of ReadExReq MSHR miss cycles +system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 24722000 # number of ReadSharedReq MSHR miss cycles +system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7914000 # number of ReadSharedReq MSHR miss cycles +system.l2cache.ReadSharedReq_mshr_miss_latency::total 32636000 # number of ReadSharedReq MSHR miss cycles +system.l2cache.demand_mshr_miss_latency::cpu.inst 24722000 # number of demand (read+write) MSHR miss cycles +system.l2cache.demand_mshr_miss_latency::cpu.data 12269000 # number of demand (read+write) MSHR miss cycles +system.l2cache.demand_mshr_miss_latency::total 36991000 # number of demand (read+write) MSHR miss cycles +system.l2cache.overall_mshr_miss_latency::cpu.inst 24722000 # number of overall MSHR miss cycles +system.l2cache.overall_mshr_miss_latency::cpu.data 12269000 # number of overall MSHR miss cycles +system.l2cache.overall_mshr_miss_latency::total 36991000 # number of overall MSHR miss cycles system.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.inst 0.986532 # mshr miss rate for ReadSharedReq accesses @@ -671,24 +682,24 @@ system.l2cache.demand_mshr_miss_rate::total 0.990783 # system.l2cache.overall_mshr_miss_rate::cpu.inst 0.986532 # mshr miss rate for overall accesses system.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.l2cache.overall_mshr_miss_rate::total 0.990783 # mshr miss rate for overall accesses -system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 84520 # average ReadExReq mshr miss latency -system.l2cache.ReadExReq_avg_mshr_miss_latency::total 84520 # average ReadExReq mshr miss latency -system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 77395.904437 # average ReadSharedReq mshr miss latency -system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 78965.517241 # average ReadSharedReq mshr miss latency -system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 77755.263158 # average ReadSharedReq mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 77395.904437 # average overall mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::cpu.data 80992.700730 # average overall mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::total 78541.860465 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 77395.904437 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::cpu.data 80992.700730 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::total 78541.860465 # average overall mshr miss latency +system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 87100 # average ReadExReq mshr miss latency +system.l2cache.ReadExReq_avg_mshr_miss_latency::total 87100 # average ReadExReq mshr miss latency +system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 84375.426621 # average ReadSharedReq mshr miss latency +system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 90965.517241 # average ReadSharedReq mshr miss latency +system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 85884.210526 # average ReadSharedReq mshr miss latency +system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 84375.426621 # average overall mshr miss latency +system.l2cache.demand_avg_mshr_miss_latency::cpu.data 89554.744526 # average overall mshr miss latency +system.l2cache.demand_avg_mshr_miss_latency::total 86025.581395 # average overall mshr miss latency +system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 84375.426621 # average overall mshr miss latency +system.l2cache.overall_avg_mshr_miss_latency::cpu.data 89554.744526 # average overall mshr miss latency +system.l2cache.overall_avg_mshr_miss_latency::total 86025.581395 # average overall mshr miss latency system.membus.snoop_filter.tot_requests 430 # Total number of requests made to the snoop filter. system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 59115000 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 62333000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 380 # Transaction distribution system.membus.trans_dist::ReadExReq 50 # Transaction distribution system.membus.trans_dist::ReadExResp 50 # Transaction distribution @@ -711,7 +722,7 @@ system.membus.snoop_fanout::max_value 0 # Re system.membus.snoop_fanout::total 430 # Request fanout histogram system.membus.reqLayer0.occupancy 430000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.7 # Layer utilization (%) -system.membus.respLayer0.occupancy 2298000 # Layer occupancy (ticks) -system.membus.respLayer0.utilization 3.9 # Layer utilization (%) +system.membus.respLayer0.occupancy 2298250 # Layer occupancy (ticks) +system.membus.respLayer0.utilization 3.7 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/config.ini b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/config.ini index a434b8376..d1ab85628 100644 --- a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/config.ini +++ b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/config.ini @@ -23,7 +23,7 @@ kernel_addr_check=true load_addr_mask=1099511627775 load_offset=0 mem_mode=timing -mem_ranges=0:536870911 +mem_ranges=0:536870911:0:0:0:0 memories=system.mem_ctrl mmap_using_noreserve=false multi_thread=false @@ -152,27 +152,27 @@ transition_latency=100000000 [system.mem_ctrl] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -192,6 +192,7 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 @@ -201,7 +202,7 @@ p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 page_policy=open_adaptive power_model=Null -range=0:536870911 +range=0:536870911:0:0:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 @@ -223,9 +224,9 @@ tRTW=2500 tWR=15000 tWTR=7500 tXAW=30000 -tXP=0 +tXP=6000 tXPDLL=0 -tXS=0 +tXS=270000 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 @@ -234,6 +235,7 @@ port=system.membus.master[0] [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -245,7 +247,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -253,3 +255,10 @@ width=16 master=system.mem_ctrl.port slave=system.cpu.icache_port system.cpu.dcache_port system.system_port +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + diff --git a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/simout b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/simout index 9b1207098..4568a6760 100755 --- a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/simout +++ b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/simout @@ -3,12 +3,12 @@ Redirecting stderr to build/SPARC/tests/opt/quick/se/03.learning-gem5/sparc/linu gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:30:06 -gem5 started Jul 21 2016 14:30:37 -gem5 executing on e108600-lin, pid 38687 +gem5 compiled Oct 13 2016 20:43:27 +gem5 started Oct 13 2016 20:47:16 +gem5 executing on e108600-lin, pid 17418 command line: /work/curdun01/gem5-external.hg/build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-simple -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-simple Global frequency set at 1000000000000 ticks per second Beginning simulation! info: Entering event queue @ 0. Starting simulation... -Hello World!Exiting @ tick 333033000 because target called exit() +Hello World!Exiting @ tick 380341000 because target called exit() diff --git a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/stats.txt b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/stats.txt index 9a120d100..ba7428ffa 100644 --- a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000340 # Number of seconds simulated -sim_ticks 340278000 # Number of ticks simulated -final_tick 340278000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000380 # Number of seconds simulated +sim_ticks 380341000 # Number of ticks simulated +final_tick 380341000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 140763 # Simulator instruction rate (inst/s) -host_op_rate 140716 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 8627820590 # Simulator tick rate (ticks/s) -host_mem_usage 633396 # Number of bytes of host memory used +host_inst_rate 148243 # Simulator instruction rate (inst/s) +host_op_rate 148143 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 10150108269 # Simulator tick rate (ticks/s) +host_mem_usage 632328 # Number of bytes of host memory used host_seconds 0.04 # Real time elapsed on the host sim_insts 5548 # Number of instructions simulated sim_ops 5548 # Number of ops (including micro ops) simulated system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 340278000 # Cumulative time (in ticks) in various power states +system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 380341000 # Cumulative time (in ticks) in various power states system.mem_ctrl.bytes_read::cpu.inst 22364 # Number of bytes read from this memory system.mem_ctrl.bytes_read::cpu.data 4640 # Number of bytes read from this memory system.mem_ctrl.bytes_read::total 27004 # Number of bytes read from this memory @@ -26,26 +26,26 @@ system.mem_ctrl.num_reads::cpu.data 718 # Nu system.mem_ctrl.num_reads::total 6309 # Number of read requests responded to by this memory system.mem_ctrl.num_writes::cpu.data 673 # Number of write requests responded to by this memory system.mem_ctrl.num_writes::total 673 # Number of write requests responded to by this memory -system.mem_ctrl.bw_read::cpu.inst 65722733 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::cpu.data 13635909 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::total 79358642 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::cpu.inst 65722733 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::total 65722733 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_write::cpu.data 14884888 # Write bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_write::total 14884888 # Write bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.inst 65722733 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.data 28520798 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::total 94243530 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_read::cpu.inst 58799866 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::cpu.data 12199579 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::total 70999445 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::cpu.inst 58799866 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::total 58799866 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_write::cpu.data 13316997 # Write bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_write::total 13316997 # Write bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.inst 58799866 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.data 25516576 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::total 84316442 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrl.readReqs 6310 # Number of read requests accepted system.mem_ctrl.writeReqs 673 # Number of write requests accepted system.mem_ctrl.readBursts 6310 # Number of DRAM read bursts, including those serviced by the write queue system.mem_ctrl.writeBursts 673 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrl.bytesReadDRAM 397824 # Total number of bytes read from DRAM -system.mem_ctrl.bytesReadWrQ 6016 # Total number of bytes read from write queue +system.mem_ctrl.bytesReadDRAM 397760 # Total number of bytes read from DRAM +system.mem_ctrl.bytesReadWrQ 6080 # Total number of bytes read from write queue system.mem_ctrl.bytesWritten 6144 # Total number of bytes written to DRAM system.mem_ctrl.bytesReadSys 27008 # Total read bytes from the system interface side system.mem_ctrl.bytesWrittenSys 5065 # Total written bytes from the system interface side -system.mem_ctrl.servicedByWrQ 94 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrl.servicedByWrQ 95 # Number of DRAM read bursts serviced by the write queue system.mem_ctrl.mergedWrBursts 548 # Number of DRAM write bursts merged with an existing one system.mem_ctrl.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.mem_ctrl.perBankRdBursts::0 220 # Per bank write bursts @@ -53,7 +53,7 @@ system.mem_ctrl.perBankRdBursts::1 84 # Pe system.mem_ctrl.perBankRdBursts::2 2 # Per bank write bursts system.mem_ctrl.perBankRdBursts::3 199 # Per bank write bursts system.mem_ctrl.perBankRdBursts::4 0 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::5 1005 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::5 1004 # Per bank write bursts system.mem_ctrl.perBankRdBursts::6 1555 # Per bank write bursts system.mem_ctrl.perBankRdBursts::7 875 # Per bank write bursts system.mem_ctrl.perBankRdBursts::8 710 # Per bank write bursts @@ -69,7 +69,7 @@ system.mem_ctrl.perBankWrBursts::1 0 # Pe system.mem_ctrl.perBankWrBursts::2 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::3 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::4 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::5 17 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::5 16 # Per bank write bursts system.mem_ctrl.perBankWrBursts::6 42 # Per bank write bursts system.mem_ctrl.perBankWrBursts::7 19 # Per bank write bursts system.mem_ctrl.perBankWrBursts::8 0 # Per bank write bursts @@ -77,12 +77,12 @@ system.mem_ctrl.perBankWrBursts::9 5 # Pe system.mem_ctrl.perBankWrBursts::10 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::11 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::12 4 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::13 9 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::13 10 # Per bank write bursts system.mem_ctrl.perBankWrBursts::14 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::15 0 # Per bank write bursts system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrl.totGap 340201000 # Total gap between requests +system.mem_ctrl.totGap 380264000 # Total gap between requests system.mem_ctrl.readPktSize::0 88 # Read request sizes (log2) system.mem_ctrl.readPktSize::1 2 # Read request sizes (log2) system.mem_ctrl.readPktSize::2 5711 # Read request sizes (log2) @@ -97,7 +97,7 @@ system.mem_ctrl.writePktSize::3 604 # Wr system.mem_ctrl.writePktSize::4 0 # Write request sizes (log2) system.mem_ctrl.writePktSize::5 0 # Write request sizes (log2) system.mem_ctrl.writePktSize::6 0 # Write request sizes (log2) -system.mem_ctrl.rdQLenPdf::0 6216 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::0 6215 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::1 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::2 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::3 0 # What read queue length does an incoming req see @@ -193,24 +193,24 @@ system.mem_ctrl.wrQLenPdf::60 0 # Wh system.mem_ctrl.wrQLenPdf::61 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrl.bytesPerActivate::samples 569 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::mean 706.474517 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::gmean 522.857650 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::stdev 386.052257 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::0-127 51 8.96% 8.96% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::128-255 75 13.18% 22.14% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::256-383 39 6.85% 29.00% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::384-511 23 4.04% 33.04% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::512-639 22 3.87% 36.91% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::640-767 18 3.16% 40.07% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::768-895 19 3.34% 43.41% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::896-1023 24 4.22% 47.63% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::1024-1151 298 52.37% 100.00% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::total 569 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::samples 575 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::mean 700.438261 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::gmean 528.229400 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::stdev 375.888489 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::0-127 45 7.83% 7.83% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::128-255 73 12.70% 20.52% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::256-383 37 6.43% 26.96% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::384-511 35 6.09% 33.04% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::512-639 26 4.52% 37.57% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::640-767 27 4.70% 42.26% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::768-895 26 4.52% 46.78% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::896-1023 27 4.70% 51.48% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::1024-1151 279 48.52% 100.00% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::total 575 # Bytes accessed per row activation system.mem_ctrl.rdPerTurnAround::samples 6 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::mean 772.333333 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::gmean 643.216539 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::stdev 524.537383 # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::mean 772.166667 # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::gmean 643.154197 # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::stdev 524.176084 # Reads before turning the bus around for writes system.mem_ctrl.rdPerTurnAround::256-319 2 33.33% 33.33% # Reads before turning the bus around for writes system.mem_ctrl.rdPerTurnAround::640-703 1 16.67% 50.00% # Reads before turning the bus around for writes system.mem_ctrl.rdPerTurnAround::704-767 1 16.67% 66.67% # Reads before turning the bus around for writes @@ -222,60 +222,70 @@ system.mem_ctrl.wrPerTurnAround::mean 16 # Wr system.mem_ctrl.wrPerTurnAround::gmean 16.000000 # Writes before turning the bus around for reads system.mem_ctrl.wrPerTurnAround::16 6 100.00% 100.00% # Writes before turning the bus around for reads system.mem_ctrl.wrPerTurnAround::total 6 # Writes before turning the bus around for reads -system.mem_ctrl.totQLat 19583750 # Total ticks spent queuing -system.mem_ctrl.totMemAccLat 136133750 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrl.totBusLat 31080000 # Total ticks spent in databus transfers -system.mem_ctrl.avgQLat 3150.54 # Average queueing delay per DRAM burst +system.mem_ctrl.totQLat 59680000 # Total ticks spent queuing +system.mem_ctrl.totMemAccLat 176211250 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrl.totBusLat 31075000 # Total ticks spent in databus transfers +system.mem_ctrl.avgQLat 9602.57 # Average queueing delay per DRAM burst system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.mem_ctrl.avgMemAccLat 21900.54 # Average memory access latency per DRAM burst -system.mem_ctrl.avgRdBW 1169.11 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrl.avgWrBW 18.06 # Average achieved write bandwidth in MiByte/s -system.mem_ctrl.avgRdBWSys 79.37 # Average system read bandwidth in MiByte/s -system.mem_ctrl.avgWrBWSys 14.88 # Average system write bandwidth in MiByte/s +system.mem_ctrl.avgMemAccLat 28352.57 # Average memory access latency per DRAM burst +system.mem_ctrl.avgRdBW 1045.80 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrl.avgWrBW 16.15 # Average achieved write bandwidth in MiByte/s +system.mem_ctrl.avgRdBWSys 71.01 # Average system read bandwidth in MiByte/s +system.mem_ctrl.avgWrBWSys 13.32 # Average system write bandwidth in MiByte/s system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrl.busUtil 9.27 # Data bus utilization in percentage -system.mem_ctrl.busUtilRead 9.13 # Data bus utilization in percentage for reads -system.mem_ctrl.busUtilWrite 0.14 # Data bus utilization in percentage for writes +system.mem_ctrl.busUtil 8.30 # Data bus utilization in percentage +system.mem_ctrl.busUtilRead 8.17 # Data bus utilization in percentage for reads +system.mem_ctrl.busUtilWrite 0.13 # Data bus utilization in percentage for writes system.mem_ctrl.avgRdQLen 1.00 # Average read queue length when enqueuing -system.mem_ctrl.avgWrQLen 23.19 # Average write queue length when enqueuing -system.mem_ctrl.readRowHits 5657 # Number of row buffer hits during reads -system.mem_ctrl.writeRowHits 82 # Number of row buffer hits during writes -system.mem_ctrl.readRowHitRate 91.01 # Row buffer hit rate for reads -system.mem_ctrl.writeRowHitRate 65.60 # Row buffer hit rate for writes -system.mem_ctrl.avgGap 48718.46 # Average gap between requests -system.mem_ctrl.pageHitRate 90.51 # Row buffer hit rate, read and write combined -system.mem_ctrl_0.actEnergy 2653560 # Energy for activate commands per rank (pJ) -system.mem_ctrl_0.preEnergy 1447875 # Energy for precharge commands per rank (pJ) -system.mem_ctrl_0.readEnergy 30108000 # Energy for read commands per rank (pJ) -system.mem_ctrl_0.writeEnergy 505440 # Energy for write commands per rank (pJ) -system.mem_ctrl_0.refreshEnergy 21868080 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_0.actBackEnergy 217242675 # Energy for active background per rank (pJ) -system.mem_ctrl_0.preBackEnergy 10477500 # Energy for precharge background per rank (pJ) -system.mem_ctrl_0.totalEnergy 284303130 # Total energy per rank (pJ) -system.mem_ctrl_0.averagePower 848.491929 # Core power per rank (mW) -system.mem_ctrl_0.memoryStateTime::IDLE 15805250 # Time in different power states -system.mem_ctrl_0.memoryStateTime::REF 11180000 # Time in different power states -system.mem_ctrl_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrl_0.memoryStateTime::ACT 311151750 # Time in different power states -system.mem_ctrl_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrl_1.actEnergy 1617840 # Energy for activate commands per rank (pJ) -system.mem_ctrl_1.preEnergy 882750 # Energy for precharge commands per rank (pJ) -system.mem_ctrl_1.readEnergy 17635800 # Energy for read commands per rank (pJ) -system.mem_ctrl_1.writeEnergy 116640 # Energy for write commands per rank (pJ) -system.mem_ctrl_1.refreshEnergy 21868080 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_1.actBackEnergy 174520890 # Energy for active background per rank (pJ) -system.mem_ctrl_1.preBackEnergy 47944500 # Energy for precharge background per rank (pJ) -system.mem_ctrl_1.totalEnergy 264586500 # Total energy per rank (pJ) -system.mem_ctrl_1.averagePower 789.680799 # Core power per rank (mW) -system.mem_ctrl_1.memoryStateTime::IDLE 79696000 # Time in different power states -system.mem_ctrl_1.memoryStateTime::REF 11180000 # Time in different power states -system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrl_1.memoryStateTime::ACT 245540000 # Time in different power states -system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 340278000 # Cumulative time (in ticks) in various power states +system.mem_ctrl.avgWrQLen 23.12 # Average write queue length when enqueuing +system.mem_ctrl.readRowHits 5650 # Number of row buffer hits during reads +system.mem_ctrl.writeRowHits 83 # Number of row buffer hits during writes +system.mem_ctrl.readRowHitRate 90.91 # Row buffer hit rate for reads +system.mem_ctrl.writeRowHitRate 66.40 # Row buffer hit rate for writes +system.mem_ctrl.avgGap 54455.68 # Average gap between requests +system.mem_ctrl.pageHitRate 90.43 # Row buffer hit rate, read and write combined +system.mem_ctrl_0.actEnergy 2598960 # Energy for activate commands per rank (pJ) +system.mem_ctrl_0.preEnergy 1377585 # Energy for precharge commands per rank (pJ) +system.mem_ctrl_0.readEnergy 28124460 # Energy for read commands per rank (pJ) +system.mem_ctrl_0.writeEnergy 401940 # Energy for write commands per rank (pJ) +system.mem_ctrl_0.refreshEnergy 29502720.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrl_0.actBackEnergy 55884510 # Energy for active background per rank (pJ) +system.mem_ctrl_0.preBackEnergy 903360 # Energy for precharge background per rank (pJ) +system.mem_ctrl_0.actPowerDownEnergy 108619200 # Energy for active power-down per rank (pJ) +system.mem_ctrl_0.prePowerDownEnergy 6618240 # Energy for precharge power-down per rank (pJ) +system.mem_ctrl_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrl_0.totalEnergy 234030975 # Total energy per rank (pJ) +system.mem_ctrl_0.averagePower 615.318415 # Core power per rank (mW) +system.mem_ctrl_0.totalIdleTime 255286000 # Total Idle time Per DRAM Rank +system.mem_ctrl_0.memoryStateTime::IDLE 462000 # Time in different power states +system.mem_ctrl_0.memoryStateTime::REF 12480000 # Time in different power states +system.mem_ctrl_0.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrl_0.memoryStateTime::PRE_PDN 17232500 # Time in different power states +system.mem_ctrl_0.memoryStateTime::ACT 111848750 # Time in different power states +system.mem_ctrl_0.memoryStateTime::ACT_PDN 238317750 # Time in different power states +system.mem_ctrl_1.actEnergy 1527960 # Energy for activate commands per rank (pJ) +system.mem_ctrl_1.preEnergy 804540 # Energy for precharge commands per rank (pJ) +system.mem_ctrl_1.readEnergy 16243500 # Energy for read commands per rank (pJ) +system.mem_ctrl_1.writeEnergy 99180 # Energy for write commands per rank (pJ) +system.mem_ctrl_1.refreshEnergy 28273440.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrl_1.actBackEnergy 35538930 # Energy for active background per rank (pJ) +system.mem_ctrl_1.preBackEnergy 1997760 # Energy for precharge background per rank (pJ) +system.mem_ctrl_1.actPowerDownEnergy 96272430 # Energy for active power-down per rank (pJ) +system.mem_ctrl_1.prePowerDownEnergy 16892160 # Energy for precharge power-down per rank (pJ) +system.mem_ctrl_1.selfRefreshEnergy 11758020 # Energy for self refresh per rank (pJ) +system.mem_ctrl_1.totalEnergy 209407920 # Total energy per rank (pJ) +system.mem_ctrl_1.averagePower 550.579039 # Core power per rank (mW) +system.mem_ctrl_1.totalIdleTime 297220000 # Total Idle time Per DRAM Rank +system.mem_ctrl_1.memoryStateTime::IDLE 3473000 # Time in different power states +system.mem_ctrl_1.memoryStateTime::REF 11978000 # Time in different power states +system.mem_ctrl_1.memoryStateTime::SREF 42087750 # Time in different power states +system.mem_ctrl_1.memoryStateTime::PRE_PDN 43986250 # Time in different power states +system.mem_ctrl_1.memoryStateTime::ACT 67670000 # Time in different power states +system.mem_ctrl_1.memoryStateTime::ACT_PDN 211146000 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 380341000 # Cumulative time (in ticks) in various power states system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 340278000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 340278 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 380341000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 380341 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 5548 # Number of instructions committed @@ -294,7 +304,7 @@ system.cpu.num_mem_refs 1404 # nu system.cpu.num_load_insts 726 # Number of load instructions system.cpu.num_store_insts 678 # Number of store instructions system.cpu.num_idle_cycles 0.001000 # Number of idle cycles -system.cpu.num_busy_cycles 340277.999000 # Number of busy cycles +system.cpu.num_busy_cycles 380340.999000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 1187 # Number of branches fetched @@ -339,7 +349,7 @@ system.membus.snoop_filter.hit_multi_requests 0 system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 340278000 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 380341000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 6310 # Transaction distribution system.membus.trans_dist::ReadResp 6309 # Transaction distribution system.membus.trans_dist::WriteReq 673 # Transaction distribution @@ -363,10 +373,10 @@ system.membus.snoop_fanout::min_value 0 # Re system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 6983 # Request fanout histogram system.membus.reqLayer0.occupancy 7656000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.2 # Layer utilization (%) -system.membus.respLayer0.occupancy 12692500 # Layer occupancy (ticks) -system.membus.respLayer0.utilization 3.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 2298500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.7 # Layer utilization (%) +system.membus.reqLayer0.utilization 2.0 # Layer utilization (%) +system.membus.respLayer0.occupancy 12691750 # Layer occupancy (ticks) +system.membus.respLayer0.utilization 3.3 # Layer utilization (%) +system.membus.respLayer1.occupancy 2300750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.6 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/config.ini b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/config.ini index 24d190659..d90641228 100644 --- a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/config.ini +++ b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/config.ini @@ -23,7 +23,7 @@ kernel_addr_check=true load_addr_mask=1099511627775 load_offset=0 mem_mode=timing -mem_ranges=0:536870911 +mem_ranges=0:536870911:0:0:0:0 memories=system.mem_ctrl mmap_using_noreserve=false multi_thread=false @@ -100,7 +100,7 @@ icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.clk_domain clusivity=mostly_incl @@ -151,7 +151,7 @@ size=64 [system.cpu.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.clk_domain clusivity=mostly_incl @@ -274,7 +274,7 @@ system=system [system.l2cache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.clk_domain clusivity=mostly_incl @@ -319,27 +319,27 @@ size=262144 [system.mem_ctrl] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -359,6 +359,7 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 @@ -368,7 +369,7 @@ p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 page_policy=open_adaptive power_model=Null -range=0:536870911 +range=0:536870911:0:0:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 @@ -390,9 +391,9 @@ tRTW=2500 tWR=15000 tWTR=7500 tXAW=30000 -tXP=0 +tXP=6000 tXPDLL=0 -tXS=0 +tXS=270000 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 @@ -401,6 +402,7 @@ port=system.membus.master[0] [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -412,7 +414,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -420,3 +422,10 @@ width=16 master=system.mem_ctrl.port slave=system.l2cache.mem_side system.system_port +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + diff --git a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/simout b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/simout index 362a2e4dd..95530f5be 100755 --- a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/simout +++ b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/simout @@ -3,12 +3,12 @@ Redirecting stderr to build/SPARC/tests/opt/quick/se/03.learning-gem5/sparc/linu gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:30:06 -gem5 started Jul 21 2016 14:30:36 -gem5 executing on e108600-lin, pid 38678 +gem5 compiled Oct 13 2016 20:43:27 +gem5 started Oct 13 2016 20:45:43 +gem5 executing on e108600-lin, pid 17392 command line: /work/curdun01/gem5-external.hg/build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-two-level -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-two-level Global frequency set at 1000000000000 ticks per second Beginning simulation! info: Entering event queue @ 0. Starting simulation... -Hello World!Exiting @ tick 53334000 because target called exit() +Hello World!Exiting @ tick 56511000 because target called exit() diff --git a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/stats.txt b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/stats.txt index 563f4d9b3..898894976 100644 --- a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000054 # Number of seconds simulated -sim_ticks 53605000 # Number of ticks simulated -final_tick 53605000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000057 # Number of seconds simulated +sim_ticks 56511000 # Number of ticks simulated +final_tick 56511000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 205629 # Simulator instruction rate (inst/s) -host_op_rate 205519 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1984690430 # Simulator tick rate (ticks/s) -host_mem_usage 637752 # Number of bytes of host memory used -host_seconds 0.03 # Real time elapsed on the host +host_inst_rate 292382 # Simulator instruction rate (inst/s) +host_op_rate 292023 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2971184542 # Simulator tick rate (ticks/s) +host_mem_usage 636424 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host sim_insts 5548 # Number of instructions simulated sim_ops 5548 # Number of ops (including micro ops) simulated system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 53605000 # Cumulative time (in ticks) in various power states +system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 56511000 # Cumulative time (in ticks) in various power states system.mem_ctrl.bytes_read::cpu.inst 16448 # Number of bytes read from this memory system.mem_ctrl.bytes_read::cpu.data 8768 # Number of bytes read from this memory system.mem_ctrl.bytes_read::total 25216 # Number of bytes read from this memory @@ -22,14 +22,14 @@ system.mem_ctrl.bytes_inst_read::total 16448 # Nu system.mem_ctrl.num_reads::cpu.inst 257 # Number of read requests responded to by this memory system.mem_ctrl.num_reads::cpu.data 137 # Number of read requests responded to by this memory system.mem_ctrl.num_reads::total 394 # Number of read requests responded to by this memory -system.mem_ctrl.bw_read::cpu.inst 306837049 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::cpu.data 163566831 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::total 470403880 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::cpu.inst 306837049 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::total 306837049 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.inst 306837049 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.data 163566831 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::total 470403880 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_read::cpu.inst 291058378 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::cpu.data 155155633 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::total 446214011 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::cpu.inst 291058378 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::total 291058378 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.inst 291058378 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.data 155155633 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::total 446214011 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrl.readReqs 394 # Number of read requests accepted system.mem_ctrl.writeReqs 0 # Number of write requests accepted system.mem_ctrl.readBursts 394 # Number of DRAM read bursts, including those serviced by the write queue @@ -76,7 +76,7 @@ system.mem_ctrl.perBankWrBursts::14 0 # Pe system.mem_ctrl.perBankWrBursts::15 0 # Per bank write bursts system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrl.totGap 53508000 # Total gap between requests +system.mem_ctrl.totGap 56394000 # Total gap between requests system.mem_ctrl.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrl.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrl.readPktSize::2 0 # Read request sizes (log2) @@ -187,77 +187,83 @@ system.mem_ctrl.wrQLenPdf::60 0 # Wh system.mem_ctrl.wrQLenPdf::61 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrl.bytesPerActivate::samples 92 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::mean 246.260870 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::gmean 176.635417 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::stdev 203.037423 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::64-127 28 30.43% 30.43% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::128-191 15 16.30% 46.74% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::192-255 11 11.96% 58.70% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::256-319 8 8.70% 67.39% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::320-383 6 6.52% 73.91% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::384-447 7 7.61% 81.52% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::448-511 3 3.26% 84.78% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::512-575 3 3.26% 88.04% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::576-639 6 6.52% 94.57% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::640-703 2 2.17% 96.74% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::768-831 1 1.09% 97.83% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::896-959 2 2.17% 100.00% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::total 92 # Bytes accessed per row activation -system.mem_ctrl.totQLat 2887500 # Total ticks spent queuing -system.mem_ctrl.totMemAccLat 10275000 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrl.bytesPerActivate::samples 98 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::mean 248.816327 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::gmean 183.748429 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::stdev 196.431638 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::0-127 26 26.53% 26.53% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::128-255 31 31.63% 58.16% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::256-383 15 15.31% 73.47% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::384-511 13 13.27% 86.73% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::512-639 9 9.18% 95.92% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::640-767 2 2.04% 97.96% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::896-1023 1 1.02% 98.98% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::1024-1151 1 1.02% 100.00% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::total 98 # Bytes accessed per row activation +system.mem_ctrl.totQLat 5793000 # Total ticks spent queuing +system.mem_ctrl.totMemAccLat 13180500 # Total ticks spent from burst creation until serviced by the DRAM system.mem_ctrl.totBusLat 1970000 # Total ticks spent in databus transfers -system.mem_ctrl.avgQLat 7328.68 # Average queueing delay per DRAM burst +system.mem_ctrl.avgQLat 14703.05 # Average queueing delay per DRAM burst system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.mem_ctrl.avgMemAccLat 26078.68 # Average memory access latency per DRAM burst -system.mem_ctrl.avgRdBW 470.40 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrl.avgMemAccLat 33453.05 # Average memory access latency per DRAM burst +system.mem_ctrl.avgRdBW 446.21 # Average DRAM read bandwidth in MiByte/s system.mem_ctrl.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.mem_ctrl.avgRdBWSys 470.40 # Average system read bandwidth in MiByte/s +system.mem_ctrl.avgRdBWSys 446.21 # Average system read bandwidth in MiByte/s system.mem_ctrl.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrl.busUtil 3.68 # Data bus utilization in percentage -system.mem_ctrl.busUtilRead 3.68 # Data bus utilization in percentage for reads +system.mem_ctrl.busUtil 3.49 # Data bus utilization in percentage +system.mem_ctrl.busUtilRead 3.49 # Data bus utilization in percentage for reads system.mem_ctrl.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.mem_ctrl.avgRdQLen 1.00 # Average read queue length when enqueuing system.mem_ctrl.avgWrQLen 0.00 # Average write queue length when enqueuing -system.mem_ctrl.readRowHits 296 # Number of row buffer hits during reads +system.mem_ctrl.readRowHits 292 # Number of row buffer hits during reads system.mem_ctrl.writeRowHits 0 # Number of row buffer hits during writes -system.mem_ctrl.readRowHitRate 75.13 # Row buffer hit rate for reads +system.mem_ctrl.readRowHitRate 74.11 # Row buffer hit rate for reads system.mem_ctrl.writeRowHitRate nan # Row buffer hit rate for writes -system.mem_ctrl.avgGap 135807.11 # Average gap between requests -system.mem_ctrl.pageHitRate 75.13 # Row buffer hit rate, read and write combined -system.mem_ctrl_0.actEnergy 378000 # Energy for activate commands per rank (pJ) -system.mem_ctrl_0.preEnergy 206250 # Energy for precharge commands per rank (pJ) -system.mem_ctrl_0.readEnergy 1614600 # Energy for read commands per rank (pJ) +system.mem_ctrl.avgGap 143131.98 # Average gap between requests +system.mem_ctrl.pageHitRate 74.11 # Row buffer hit rate, read and write combined +system.mem_ctrl_0.actEnergy 421260 # Energy for activate commands per rank (pJ) +system.mem_ctrl_0.preEnergy 216315 # Energy for precharge commands per rank (pJ) +system.mem_ctrl_0.readEnergy 1756440 # Energy for read commands per rank (pJ) system.mem_ctrl_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.mem_ctrl_0.refreshEnergy 3051360 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_0.actBackEnergy 30461940 # Energy for active background per rank (pJ) -system.mem_ctrl_0.preBackEnergy 1478250 # Energy for precharge background per rank (pJ) -system.mem_ctrl_0.totalEnergy 37190400 # Total energy per rank (pJ) -system.mem_ctrl_0.averagePower 791.306152 # Core power per rank (mW) -system.mem_ctrl_0.memoryStateTime::IDLE 2310750 # Time in different power states -system.mem_ctrl_0.memoryStateTime::REF 1560000 # Time in different power states -system.mem_ctrl_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrl_0.memoryStateTime::ACT 43141000 # Time in different power states -system.mem_ctrl_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrl_1.actEnergy 272160 # Energy for activate commands per rank (pJ) -system.mem_ctrl_1.preEnergy 148500 # Energy for precharge commands per rank (pJ) -system.mem_ctrl_1.readEnergy 1053000 # Energy for read commands per rank (pJ) +system.mem_ctrl_0.refreshEnergy 4302480.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrl_0.actBackEnergy 4075500 # Energy for active background per rank (pJ) +system.mem_ctrl_0.preBackEnergy 122880 # Energy for precharge background per rank (pJ) +system.mem_ctrl_0.actPowerDownEnergy 21123630 # Energy for active power-down per rank (pJ) +system.mem_ctrl_0.prePowerDownEnergy 357120 # Energy for precharge power-down per rank (pJ) +system.mem_ctrl_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrl_0.totalEnergy 32375625 # Total energy per rank (pJ) +system.mem_ctrl_0.averagePower 572.905837 # Core power per rank (mW) +system.mem_ctrl_0.totalIdleTime 47002000 # Total Idle time Per DRAM Rank +system.mem_ctrl_0.memoryStateTime::IDLE 71000 # Time in different power states +system.mem_ctrl_0.memoryStateTime::REF 1820000 # Time in different power states +system.mem_ctrl_0.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrl_0.memoryStateTime::PRE_PDN 929250 # Time in different power states +system.mem_ctrl_0.memoryStateTime::ACT 7357750 # Time in different power states +system.mem_ctrl_0.memoryStateTime::ACT_PDN 46333000 # Time in different power states +system.mem_ctrl_1.actEnergy 307020 # Energy for activate commands per rank (pJ) +system.mem_ctrl_1.preEnergy 155595 # Energy for precharge commands per rank (pJ) +system.mem_ctrl_1.readEnergy 1056720 # Energy for read commands per rank (pJ) system.mem_ctrl_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.mem_ctrl_1.refreshEnergy 3051360 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_1.actBackEnergy 29252115 # Energy for active background per rank (pJ) -system.mem_ctrl_1.preBackEnergy 2526750 # Energy for precharge background per rank (pJ) -system.mem_ctrl_1.totalEnergy 36303885 # Total energy per rank (pJ) -system.mem_ctrl_1.averagePower 772.793039 # Core power per rank (mW) -system.mem_ctrl_1.memoryStateTime::IDLE 5312750 # Time in different power states -system.mem_ctrl_1.memoryStateTime::REF 1560000 # Time in different power states -system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrl_1.memoryStateTime::ACT 41373250 # Time in different power states -system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 53605000 # Cumulative time (in ticks) in various power states +system.mem_ctrl_1.refreshEnergy 4302480.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrl_1.actBackEnergy 2785590 # Energy for active background per rank (pJ) +system.mem_ctrl_1.preBackEnergy 293760 # Energy for precharge background per rank (pJ) +system.mem_ctrl_1.actPowerDownEnergy 20523420 # Energy for active power-down per rank (pJ) +system.mem_ctrl_1.prePowerDownEnergy 1777920 # Energy for precharge power-down per rank (pJ) +system.mem_ctrl_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrl_1.totalEnergy 31202505 # Total energy per rank (pJ) +system.mem_ctrl_1.averagePower 552.146785 # Core power per rank (mW) +system.mem_ctrl_1.totalIdleTime 49582750 # Total Idle time Per DRAM Rank +system.mem_ctrl_1.memoryStateTime::IDLE 557000 # Time in different power states +system.mem_ctrl_1.memoryStateTime::REF 1820000 # Time in different power states +system.mem_ctrl_1.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrl_1.memoryStateTime::PRE_PDN 4629500 # Time in different power states +system.mem_ctrl_1.memoryStateTime::ACT 4495750 # Time in different power states +system.mem_ctrl_1.memoryStateTime::ACT_PDN 45008750 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 56511000 # Cumulative time (in ticks) in various power states system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 53605000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 53605 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 56511000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 56511 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 5548 # Number of instructions committed @@ -276,7 +282,7 @@ system.cpu.num_mem_refs 1404 # nu system.cpu.num_load_insts 726 # Number of load instructions system.cpu.num_store_insts 678 # Number of store instructions system.cpu.num_idle_cycles 0.001000 # Number of idle cycles -system.cpu.num_busy_cycles 53604.999000 # Number of busy cycles +system.cpu.num_busy_cycles 56510.999000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 1187 # Number of branches fetched @@ -315,23 +321,23 @@ system.cpu.op_class::MemWrite 678 12.13% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 5591 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 53605000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 56511000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 83.787726 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 83.847801 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1253 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 138 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 9.079710 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 83.787726 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.081824 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.081824 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 83.847801 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.081883 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.081883 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 138 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 10 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 128 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.134766 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 2920 # Number of tag accesses system.cpu.dcache.tags.data_accesses 2920 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 53605000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 56511000 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 662 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 662 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 591 # number of WriteReq hits @@ -348,14 +354,14 @@ system.cpu.dcache.demand_misses::cpu.data 138 # n system.cpu.dcache.demand_misses::total 138 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 138 # number of overall misses system.cpu.dcache.overall_misses::total 138 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5756000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5756000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 8522000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 8522000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 14278000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 14278000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 14278000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 14278000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 6576000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 6576000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 8937000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 8937000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 15513000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 15513000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 15513000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 15513000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 718 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 718 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 673 # number of WriteReq accesses(hits+misses) @@ -372,14 +378,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.099209 system.cpu.dcache.demand_miss_rate::total 0.099209 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.099209 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.099209 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 102785.714286 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 102785.714286 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 103926.829268 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 103926.829268 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 103463.768116 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 103463.768116 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 103463.768116 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 103463.768116 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 117428.571429 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 117428.571429 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 108987.804878 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 108987.804878 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 112413.043478 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 112413.043478 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 112413.043478 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 112413.043478 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -394,14 +400,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 138 system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5644000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5644000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8358000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8358000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14002000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 14002000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14002000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 14002000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6464000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6464000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8773000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8773000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15237000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 15237000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15237000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 15237000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.077994 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.077994 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.121842 # mshr miss rate for WriteReq accesses @@ -410,31 +416,31 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.099209 system.cpu.dcache.demand_mshr_miss_rate::total 0.099209 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.099209 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.099209 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 100785.714286 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 100785.714286 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 101926.829268 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 101926.829268 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 101463.768116 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 101463.768116 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 101463.768116 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 101463.768116 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 53605000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 115428.571429 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 115428.571429 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 106987.804878 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 106987.804878 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 110413.043478 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 110413.043478 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 110413.043478 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 110413.043478 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 56511000 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 71 # number of replacements -system.cpu.icache.tags.tagsinuse 98.163046 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 98.324434 # Cycle average of tags in use system.cpu.icache.tags.total_refs 5333 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 259 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 20.590734 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 98.163046 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.383449 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.383449 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 98.324434 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.384080 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.384080 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 188 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 129 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 134 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.734375 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 11443 # Number of tag accesses system.cpu.icache.tags.data_accesses 11443 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 53605000 # Cumulative time (in ticks) in various power states +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 56511000 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 5333 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 5333 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 5333 # number of demand (read+write) hits @@ -447,12 +453,12 @@ system.cpu.icache.demand_misses::cpu.inst 259 # n system.cpu.icache.demand_misses::total 259 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 259 # number of overall misses system.cpu.icache.overall_misses::total 259 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 26157000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 26157000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 26157000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 26157000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 26157000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 26157000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 27828000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 27828000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 27828000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 27828000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 27828000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 27828000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 5592 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 5592 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 5592 # number of demand (read+write) accesses @@ -465,12 +471,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.046316 system.cpu.icache.demand_miss_rate::total 0.046316 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.046316 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.046316 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 100992.277992 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 100992.277992 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 100992.277992 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 100992.277992 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 100992.277992 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 100992.277992 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 107444.015444 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 107444.015444 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 107444.015444 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 107444.015444 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 107444.015444 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 107444.015444 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -483,31 +489,31 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 259 system.cpu.icache.demand_mshr_misses::total 259 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 259 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 259 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25639000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 25639000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25639000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 25639000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25639000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 25639000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 27310000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 27310000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 27310000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 27310000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 27310000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 27310000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.046316 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.046316 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.046316 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.046316 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.046316 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.046316 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 98992.277992 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 98992.277992 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 98992.277992 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 98992.277992 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 98992.277992 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 98992.277992 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 105444.015444 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 105444.015444 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 105444.015444 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 105444.015444 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 105444.015444 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 105444.015444 # average overall mshr miss latency system.l2bus.snoop_filter.tot_requests 468 # Total number of requests made to the snoop filter. system.l2bus.snoop_filter.hit_single_requests 73 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.l2bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.l2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.l2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.l2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.l2bus.pwrStateResidencyTicks::UNDEFINED 53605000 # Cumulative time (in ticks) in various power states +system.l2bus.pwrStateResidencyTicks::UNDEFINED 56511000 # Cumulative time (in ticks) in various power states system.l2bus.trans_dist::ReadResp 315 # Transaction distribution system.l2bus.trans_dist::CleanEvict 71 # Transaction distribution system.l2bus.trans_dist::ReadExReq 82 # Transaction distribution @@ -533,30 +539,30 @@ system.l2bus.snoop_fanout::min_value 0 # Re system.l2bus.snoop_fanout::max_value 1 # Request fanout histogram system.l2bus.snoop_fanout::total 397 # Request fanout histogram system.l2bus.reqLayer0.occupancy 468000 # Layer occupancy (ticks) -system.l2bus.reqLayer0.utilization 0.9 # Layer utilization (%) +system.l2bus.reqLayer0.utilization 0.8 # Layer utilization (%) system.l2bus.respLayer0.occupancy 777000 # Layer occupancy (ticks) system.l2bus.respLayer0.utilization 1.4 # Layer utilization (%) system.l2bus.respLayer1.occupancy 414000 # Layer occupancy (ticks) -system.l2bus.respLayer1.utilization 0.8 # Layer utilization (%) -system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 53605000 # Cumulative time (in ticks) in various power states +system.l2bus.respLayer1.utilization 0.7 # Layer utilization (%) +system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 56511000 # Cumulative time (in ticks) in various power states system.l2cache.tags.replacements 0 # number of replacements -system.l2cache.tags.tagsinuse 200.697345 # Cycle average of tags in use +system.l2cache.tags.tagsinuse 201.052259 # Cycle average of tags in use system.l2cache.tags.total_refs 73 # Total number of references to valid blocks. system.l2cache.tags.sampled_refs 394 # Sample count of references to valid blocks. system.l2cache.tags.avg_refs 0.185279 # Average number of references to valid blocks. system.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2cache.tags.occ_blocks::cpu.inst 117.835895 # Average occupied blocks per requestor -system.l2cache.tags.occ_blocks::cpu.data 82.861451 # Average occupied blocks per requestor -system.l2cache.tags.occ_percent::cpu.inst 0.028769 # Average percentage of cache occupancy -system.l2cache.tags.occ_percent::cpu.data 0.020230 # Average percentage of cache occupancy -system.l2cache.tags.occ_percent::total 0.048998 # Average percentage of cache occupancy +system.l2cache.tags.occ_blocks::cpu.inst 118.133782 # Average occupied blocks per requestor +system.l2cache.tags.occ_blocks::cpu.data 82.918477 # Average occupied blocks per requestor +system.l2cache.tags.occ_percent::cpu.inst 0.028841 # Average percentage of cache occupancy +system.l2cache.tags.occ_percent::cpu.data 0.020244 # Average percentage of cache occupancy +system.l2cache.tags.occ_percent::total 0.049085 # Average percentage of cache occupancy system.l2cache.tags.occ_task_id_blocks::1024 394 # Occupied blocks per task id -system.l2cache.tags.age_task_id_blocks_1024::0 68 # Occupied blocks per task id -system.l2cache.tags.age_task_id_blocks_1024::1 326 # Occupied blocks per task id +system.l2cache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id +system.l2cache.tags.age_task_id_blocks_1024::1 332 # Occupied blocks per task id system.l2cache.tags.occ_task_id_percent::1024 0.096191 # Percentage of cache occupancy per task id system.l2cache.tags.tag_accesses 4130 # Number of tag accesses system.l2cache.tags.data_accesses 4130 # Number of data accesses -system.l2cache.pwrStateResidencyTicks::UNDEFINED 53605000 # Cumulative time (in ticks) in various power states +system.l2cache.pwrStateResidencyTicks::UNDEFINED 56511000 # Cumulative time (in ticks) in various power states system.l2cache.ReadSharedReq_hits::cpu.inst 2 # number of ReadSharedReq hits system.l2cache.ReadSharedReq_hits::cpu.data 1 # number of ReadSharedReq hits system.l2cache.ReadSharedReq_hits::total 3 # number of ReadSharedReq hits @@ -577,17 +583,17 @@ system.l2cache.demand_misses::total 394 # nu system.l2cache.overall_misses::cpu.inst 257 # number of overall misses system.l2cache.overall_misses::cpu.data 137 # number of overall misses system.l2cache.overall_misses::total 394 # number of overall misses -system.l2cache.ReadExReq_miss_latency::cpu.data 8112000 # number of ReadExReq miss cycles -system.l2cache.ReadExReq_miss_latency::total 8112000 # number of ReadExReq miss cycles -system.l2cache.ReadSharedReq_miss_latency::cpu.inst 24816000 # number of ReadSharedReq miss cycles -system.l2cache.ReadSharedReq_miss_latency::cpu.data 5453000 # number of ReadSharedReq miss cycles -system.l2cache.ReadSharedReq_miss_latency::total 30269000 # number of ReadSharedReq miss cycles -system.l2cache.demand_miss_latency::cpu.inst 24816000 # number of demand (read+write) miss cycles -system.l2cache.demand_miss_latency::cpu.data 13565000 # number of demand (read+write) miss cycles -system.l2cache.demand_miss_latency::total 38381000 # number of demand (read+write) miss cycles -system.l2cache.overall_miss_latency::cpu.inst 24816000 # number of overall miss cycles -system.l2cache.overall_miss_latency::cpu.data 13565000 # number of overall miss cycles -system.l2cache.overall_miss_latency::total 38381000 # number of overall miss cycles +system.l2cache.ReadExReq_miss_latency::cpu.data 8527000 # number of ReadExReq miss cycles +system.l2cache.ReadExReq_miss_latency::total 8527000 # number of ReadExReq miss cycles +system.l2cache.ReadSharedReq_miss_latency::cpu.inst 26487000 # number of ReadSharedReq miss cycles +system.l2cache.ReadSharedReq_miss_latency::cpu.data 6273000 # number of ReadSharedReq miss cycles +system.l2cache.ReadSharedReq_miss_latency::total 32760000 # number of ReadSharedReq miss cycles +system.l2cache.demand_miss_latency::cpu.inst 26487000 # number of demand (read+write) miss cycles +system.l2cache.demand_miss_latency::cpu.data 14800000 # number of demand (read+write) miss cycles +system.l2cache.demand_miss_latency::total 41287000 # number of demand (read+write) miss cycles +system.l2cache.overall_miss_latency::cpu.inst 26487000 # number of overall miss cycles +system.l2cache.overall_miss_latency::cpu.data 14800000 # number of overall miss cycles +system.l2cache.overall_miss_latency::total 41287000 # number of overall miss cycles system.l2cache.ReadExReq_accesses::cpu.data 82 # number of ReadExReq accesses(hits+misses) system.l2cache.ReadExReq_accesses::total 82 # number of ReadExReq accesses(hits+misses) system.l2cache.ReadSharedReq_accesses::cpu.inst 259 # number of ReadSharedReq accesses(hits+misses) @@ -610,17 +616,17 @@ system.l2cache.demand_miss_rate::total 0.992443 # mi system.l2cache.overall_miss_rate::cpu.inst 0.992278 # miss rate for overall accesses system.l2cache.overall_miss_rate::cpu.data 0.992754 # miss rate for overall accesses system.l2cache.overall_miss_rate::total 0.992443 # miss rate for overall accesses -system.l2cache.ReadExReq_avg_miss_latency::cpu.data 98926.829268 # average ReadExReq miss latency -system.l2cache.ReadExReq_avg_miss_latency::total 98926.829268 # average ReadExReq miss latency -system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 96560.311284 # average ReadSharedReq miss latency -system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 99145.454545 # average ReadSharedReq miss latency -system.l2cache.ReadSharedReq_avg_miss_latency::total 97016.025641 # average ReadSharedReq miss latency -system.l2cache.demand_avg_miss_latency::cpu.inst 96560.311284 # average overall miss latency -system.l2cache.demand_avg_miss_latency::cpu.data 99014.598540 # average overall miss latency -system.l2cache.demand_avg_miss_latency::total 97413.705584 # average overall miss latency -system.l2cache.overall_avg_miss_latency::cpu.inst 96560.311284 # average overall miss latency -system.l2cache.overall_avg_miss_latency::cpu.data 99014.598540 # average overall miss latency -system.l2cache.overall_avg_miss_latency::total 97413.705584 # average overall miss latency +system.l2cache.ReadExReq_avg_miss_latency::cpu.data 103987.804878 # average ReadExReq miss latency +system.l2cache.ReadExReq_avg_miss_latency::total 103987.804878 # average ReadExReq miss latency +system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 103062.256809 # average ReadSharedReq miss latency +system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 114054.545455 # average ReadSharedReq miss latency +system.l2cache.ReadSharedReq_avg_miss_latency::total 105000 # average ReadSharedReq miss latency +system.l2cache.demand_avg_miss_latency::cpu.inst 103062.256809 # average overall miss latency +system.l2cache.demand_avg_miss_latency::cpu.data 108029.197080 # average overall miss latency +system.l2cache.demand_avg_miss_latency::total 104789.340102 # average overall miss latency +system.l2cache.overall_avg_miss_latency::cpu.inst 103062.256809 # average overall miss latency +system.l2cache.overall_avg_miss_latency::cpu.data 108029.197080 # average overall miss latency +system.l2cache.overall_avg_miss_latency::total 104789.340102 # average overall miss latency system.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -638,17 +644,17 @@ system.l2cache.demand_mshr_misses::total 394 # nu system.l2cache.overall_mshr_misses::cpu.inst 257 # number of overall MSHR misses system.l2cache.overall_mshr_misses::cpu.data 137 # number of overall MSHR misses system.l2cache.overall_mshr_misses::total 394 # number of overall MSHR misses -system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6472000 # number of ReadExReq MSHR miss cycles -system.l2cache.ReadExReq_mshr_miss_latency::total 6472000 # number of ReadExReq MSHR miss cycles -system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 19676000 # number of ReadSharedReq MSHR miss cycles -system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4353000 # number of ReadSharedReq MSHR miss cycles -system.l2cache.ReadSharedReq_mshr_miss_latency::total 24029000 # number of ReadSharedReq MSHR miss cycles -system.l2cache.demand_mshr_miss_latency::cpu.inst 19676000 # number of demand (read+write) MSHR miss cycles -system.l2cache.demand_mshr_miss_latency::cpu.data 10825000 # number of demand (read+write) MSHR miss cycles -system.l2cache.demand_mshr_miss_latency::total 30501000 # number of demand (read+write) MSHR miss cycles -system.l2cache.overall_mshr_miss_latency::cpu.inst 19676000 # number of overall MSHR miss cycles -system.l2cache.overall_mshr_miss_latency::cpu.data 10825000 # number of overall MSHR miss cycles -system.l2cache.overall_mshr_miss_latency::total 30501000 # number of overall MSHR miss cycles +system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6887000 # number of ReadExReq MSHR miss cycles +system.l2cache.ReadExReq_mshr_miss_latency::total 6887000 # number of ReadExReq MSHR miss cycles +system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 21347000 # number of ReadSharedReq MSHR miss cycles +system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5173000 # number of ReadSharedReq MSHR miss cycles +system.l2cache.ReadSharedReq_mshr_miss_latency::total 26520000 # number of ReadSharedReq MSHR miss cycles +system.l2cache.demand_mshr_miss_latency::cpu.inst 21347000 # number of demand (read+write) MSHR miss cycles +system.l2cache.demand_mshr_miss_latency::cpu.data 12060000 # number of demand (read+write) MSHR miss cycles +system.l2cache.demand_mshr_miss_latency::total 33407000 # number of demand (read+write) MSHR miss cycles +system.l2cache.overall_mshr_miss_latency::cpu.inst 21347000 # number of overall MSHR miss cycles +system.l2cache.overall_mshr_miss_latency::cpu.data 12060000 # number of overall MSHR miss cycles +system.l2cache.overall_mshr_miss_latency::total 33407000 # number of overall MSHR miss cycles system.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.inst 0.992278 # mshr miss rate for ReadSharedReq accesses @@ -660,24 +666,24 @@ system.l2cache.demand_mshr_miss_rate::total 0.992443 # system.l2cache.overall_mshr_miss_rate::cpu.inst 0.992278 # mshr miss rate for overall accesses system.l2cache.overall_mshr_miss_rate::cpu.data 0.992754 # mshr miss rate for overall accesses system.l2cache.overall_mshr_miss_rate::total 0.992443 # mshr miss rate for overall accesses -system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78926.829268 # average ReadExReq mshr miss latency -system.l2cache.ReadExReq_avg_mshr_miss_latency::total 78926.829268 # average ReadExReq mshr miss latency -system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 76560.311284 # average ReadSharedReq mshr miss latency -system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79145.454545 # average ReadSharedReq mshr miss latency -system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 77016.025641 # average ReadSharedReq mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 76560.311284 # average overall mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::cpu.data 79014.598540 # average overall mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::total 77413.705584 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 76560.311284 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::cpu.data 79014.598540 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::total 77413.705584 # average overall mshr miss latency +system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 83987.804878 # average ReadExReq mshr miss latency +system.l2cache.ReadExReq_avg_mshr_miss_latency::total 83987.804878 # average ReadExReq mshr miss latency +system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 83062.256809 # average ReadSharedReq mshr miss latency +system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 94054.545455 # average ReadSharedReq mshr miss latency +system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 85000 # average ReadSharedReq mshr miss latency +system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 83062.256809 # average overall mshr miss latency +system.l2cache.demand_avg_mshr_miss_latency::cpu.data 88029.197080 # average overall mshr miss latency +system.l2cache.demand_avg_mshr_miss_latency::total 84789.340102 # average overall mshr miss latency +system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 83062.256809 # average overall mshr miss latency +system.l2cache.overall_avg_mshr_miss_latency::cpu.data 88029.197080 # average overall mshr miss latency +system.l2cache.overall_avg_mshr_miss_latency::total 84789.340102 # average overall mshr miss latency system.membus.snoop_filter.tot_requests 394 # Total number of requests made to the snoop filter. system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 53605000 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 56511000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 312 # Transaction distribution system.membus.trans_dist::ReadExReq 82 # Transaction distribution system.membus.trans_dist::ReadExResp 82 # Transaction distribution @@ -700,7 +706,7 @@ system.membus.snoop_fanout::max_value 0 # Re system.membus.snoop_fanout::total 394 # Request fanout histogram system.membus.reqLayer0.occupancy 394000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.7 # Layer utilization (%) -system.membus.respLayer0.occupancy 2102000 # Layer occupancy (ticks) -system.membus.respLayer0.utilization 3.9 # Layer utilization (%) +system.membus.respLayer0.occupancy 2102500 # Layer occupancy (ticks) +system.membus.respLayer0.utilization 3.7 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/config.ini b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/config.ini index f9a7ceaa3..612b72e20 100644 --- a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/config.ini +++ b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/config.ini @@ -23,7 +23,7 @@ kernel_addr_check=true load_addr_mask=1099511627775 load_offset=0 mem_mode=timing -mem_ranges=0:536870911 +mem_ranges=0:536870911:0:0:0:0 memories=system.mem_ctrl mmap_using_noreserve=false multi_thread=false @@ -199,27 +199,27 @@ transition_latency=100000000 [system.mem_ctrl] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -239,6 +239,7 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 @@ -248,7 +249,7 @@ p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 page_policy=open_adaptive power_model=Null -range=0:536870911 +range=0:536870911:0:0:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 @@ -270,9 +271,9 @@ tRTW=2500 tWR=15000 tWTR=7500 tXAW=30000 -tXP=0 +tXP=6000 tXPDLL=0 -tXS=0 +tXS=270000 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 @@ -281,6 +282,7 @@ port=system.membus.master[2] [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -292,7 +294,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -300,3 +302,10 @@ width=16 master=system.cpu.interrupts.pio system.cpu.interrupts.int_slave system.mem_ctrl.port slave=system.cpu.icache_port system.cpu.dcache_port system.cpu.interrupts.int_master system.system_port +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + diff --git a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/simout b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/simout index c68473235..3227a9df4 100755 --- a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/simout +++ b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/simout @@ -3,13 +3,13 @@ Redirecting stderr to build/X86/tests/opt/quick/se/03.learning-gem5/x86/linux/le gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:35:23 -gem5 started Jul 21 2016 14:36:19 -gem5 executing on e108600-lin, pid 18562 +gem5 compiled Oct 11 2016 00:00:58 +gem5 started Oct 13 2016 21:11:23 +gem5 executing on e108600-lin, pid 17668 command line: /work/curdun01/gem5-external.hg/build/X86/gem5.opt -d build/X86/tests/opt/quick/se/03.learning-gem5/x86/linux/learning-gem5-p1-simple -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/03.learning-gem5/x86/linux/learning-gem5-p1-simple Global frequency set at 1000000000000 ticks per second Beginning simulation! info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 445082000 because target called exit() +Exiting @ tick 507841000 because target called exit() diff --git a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/stats.txt b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/stats.txt index 7312a839d..d3b77ec90 100644 --- a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000455 # Number of seconds simulated -sim_ticks 454507000 # Number of ticks simulated -final_tick 454507000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000508 # Number of seconds simulated +sim_ticks 507841000 # Number of ticks simulated +final_tick 507841000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 76712 # Simulator instruction rate (inst/s) -host_op_rate 138489 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 6101741543 # Simulator tick rate (ticks/s) -host_mem_usage 651776 # Number of bytes of host memory used -host_seconds 0.07 # Real time elapsed on the host +host_inst_rate 96340 # Simulator instruction rate (inst/s) +host_op_rate 173892 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 8558810197 # Simulator tick rate (ticks/s) +host_mem_usage 650468 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host sim_insts 5712 # Number of instructions simulated sim_ops 10314 # Number of ops (including micro ops) simulated system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 454507000 # Cumulative time (in ticks) in various power states +system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 507841000 # Cumulative time (in ticks) in various power states system.mem_ctrl.bytes_read::cpu.inst 58264 # Number of bytes read from this memory system.mem_ctrl.bytes_read::cpu.data 7167 # Number of bytes read from this memory system.mem_ctrl.bytes_read::total 65431 # Number of bytes read from this memory @@ -26,29 +26,29 @@ system.mem_ctrl.num_reads::cpu.data 1084 # Nu system.mem_ctrl.num_reads::total 8367 # Number of read requests responded to by this memory system.mem_ctrl.num_writes::cpu.data 941 # Number of write requests responded to by this memory system.mem_ctrl.num_writes::total 941 # Number of write requests responded to by this memory -system.mem_ctrl.bw_read::cpu.inst 128191645 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::cpu.data 15768734 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::total 143960379 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::cpu.inst 128191645 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::total 128191645 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_write::cpu.data 15753333 # Write bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_write::total 15753333 # Write bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.inst 128191645 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.data 31522067 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::total 159713712 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_read::cpu.inst 114728823 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::cpu.data 14112685 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::total 128841507 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::cpu.inst 114728823 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::total 114728823 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_write::cpu.data 14098901 # Write bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_write::total 14098901 # Write bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.inst 114728823 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.data 28211586 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::total 142940409 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrl.readReqs 8367 # Number of read requests accepted system.mem_ctrl.writeReqs 941 # Number of write requests accepted system.mem_ctrl.readBursts 8367 # Number of DRAM read bursts, including those serviced by the write queue system.mem_ctrl.writeBursts 941 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrl.bytesReadDRAM 524736 # Total number of bytes read from DRAM -system.mem_ctrl.bytesReadWrQ 10752 # Total number of bytes read from write queue -system.mem_ctrl.bytesWritten 6144 # Total number of bytes written to DRAM +system.mem_ctrl.bytesReadDRAM 525184 # Total number of bytes read from DRAM +system.mem_ctrl.bytesReadWrQ 10304 # Total number of bytes read from write queue +system.mem_ctrl.bytesWritten 7168 # Total number of bytes written to DRAM system.mem_ctrl.bytesReadSys 65431 # Total read bytes from the system interface side system.mem_ctrl.bytesWrittenSys 7160 # Total written bytes from the system interface side -system.mem_ctrl.servicedByWrQ 168 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrl.mergedWrBursts 819 # Number of DRAM write bursts merged with an existing one +system.mem_ctrl.servicedByWrQ 161 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrl.mergedWrBursts 810 # Number of DRAM write bursts merged with an existing one system.mem_ctrl.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.mem_ctrl.perBankRdBursts::0 273 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::0 277 # Per bank write bursts system.mem_ctrl.perBankRdBursts::1 4 # Per bank write bursts system.mem_ctrl.perBankRdBursts::2 227 # Per bank write bursts system.mem_ctrl.perBankRdBursts::3 102 # Per bank write bursts @@ -58,13 +58,13 @@ system.mem_ctrl.perBankRdBursts::6 1103 # Pe system.mem_ctrl.perBankRdBursts::7 906 # Per bank write bursts system.mem_ctrl.perBankRdBursts::8 703 # Per bank write bursts system.mem_ctrl.perBankRdBursts::9 490 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::10 1055 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::10 1059 # Per bank write bursts system.mem_ctrl.perBankRdBursts::11 59 # Per bank write bursts system.mem_ctrl.perBankRdBursts::12 11 # Per bank write bursts system.mem_ctrl.perBankRdBursts::13 489 # Per bank write bursts system.mem_ctrl.perBankRdBursts::14 78 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::15 115 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::0 6 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::15 114 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::0 10 # Per bank write bursts system.mem_ctrl.perBankWrBursts::1 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::2 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::3 0 # Per bank write bursts @@ -72,17 +72,17 @@ system.mem_ctrl.perBankWrBursts::4 0 # Pe system.mem_ctrl.perBankWrBursts::5 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::6 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::7 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::8 2 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::9 53 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::10 23 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::8 3 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::9 54 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::10 34 # Per bank write bursts system.mem_ctrl.perBankWrBursts::11 7 # Per bank write bursts system.mem_ctrl.perBankWrBursts::12 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::13 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::14 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::15 5 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::15 4 # Per bank write bursts system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrl.totGap 454381000 # Total gap between requests +system.mem_ctrl.totGap 507709000 # Total gap between requests system.mem_ctrl.readPktSize::0 135 # Read request sizes (log2) system.mem_ctrl.readPktSize::1 14 # Read request sizes (log2) system.mem_ctrl.readPktSize::2 119 # Read request sizes (log2) @@ -97,7 +97,7 @@ system.mem_ctrl.writePktSize::3 861 # Wr system.mem_ctrl.writePktSize::4 0 # Write request sizes (log2) system.mem_ctrl.writePktSize::5 0 # Write request sizes (log2) system.mem_ctrl.writePktSize::6 0 # Write request sizes (log2) -system.mem_ctrl.rdQLenPdf::0 8199 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::0 8206 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::1 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::2 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::3 0 # What read queue length does an incoming req see @@ -146,8 +146,8 @@ system.mem_ctrl.wrQLenPdf::13 1 # Wh system.mem_ctrl.wrQLenPdf::14 1 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::15 1 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::16 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::17 7 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::18 7 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::17 8 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::18 8 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::19 7 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::20 7 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::21 7 # What write queue length does an incoming req see @@ -155,13 +155,13 @@ system.mem_ctrl.wrQLenPdf::22 7 # Wh system.mem_ctrl.wrQLenPdf::23 7 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::24 7 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::25 7 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::26 6 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::27 6 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::28 6 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::29 6 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::30 6 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::31 6 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::32 6 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::26 7 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::27 7 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::28 7 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::29 7 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::30 7 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::31 7 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::32 7 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::33 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::34 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::35 0 # What write queue length does an incoming req see @@ -193,94 +193,105 @@ system.mem_ctrl.wrQLenPdf::60 0 # Wh system.mem_ctrl.wrQLenPdf::61 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrl.bytesPerActivate::samples 849 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::mean 622.812721 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::gmean 426.803074 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::stdev 394.306776 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::0-127 142 16.73% 16.73% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::128-255 69 8.13% 24.85% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::256-383 77 9.07% 33.92% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::384-511 63 7.42% 41.34% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::512-639 55 6.48% 47.82% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::640-767 39 4.59% 52.41% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::768-895 28 3.30% 55.71% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::896-1023 21 2.47% 58.19% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::1024-1151 355 41.81% 100.00% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::total 849 # Bytes accessed per row activation -system.mem_ctrl.rdPerTurnAround::samples 6 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::mean 1282.333333 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::gmean 1020.532539 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::stdev 764.587906 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::256-383 1 16.67% 16.67% # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::384-511 1 16.67% 33.33% # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::1280-1407 1 16.67% 50.00% # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::1408-1535 1 16.67% 66.67% # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::1920-2047 1 16.67% 83.33% # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::2048-2175 1 16.67% 100.00% # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::total 6 # Reads before turning the bus around for writes -system.mem_ctrl.wrPerTurnAround::samples 6 # Writes before turning the bus around for reads +system.mem_ctrl.bytesPerActivate::samples 856 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::mean 618.018692 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::gmean 421.107711 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::stdev 393.969749 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::0-127 148 17.29% 17.29% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::128-255 75 8.76% 26.05% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::256-383 73 8.53% 34.58% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::384-511 52 6.07% 40.65% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::512-639 57 6.66% 47.31% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::640-767 49 5.72% 53.04% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::768-895 36 4.21% 57.24% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::896-1023 15 1.75% 59.00% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::1024-1151 351 41.00% 100.00% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::total 856 # Bytes accessed per row activation +system.mem_ctrl.rdPerTurnAround::samples 7 # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::mean 1165.285714 # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::gmean 941.793638 # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::stdev 714.559471 # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::256-383 1 14.29% 14.29% # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::384-511 1 14.29% 28.57% # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::640-767 1 14.29% 42.86% # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::1280-1407 1 14.29% 57.14% # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::1408-1535 1 14.29% 71.43% # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::1920-2047 1 14.29% 85.71% # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::2048-2175 1 14.29% 100.00% # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::total 7 # Reads before turning the bus around for writes +system.mem_ctrl.wrPerTurnAround::samples 7 # Writes before turning the bus around for reads system.mem_ctrl.wrPerTurnAround::mean 16 # Writes before turning the bus around for reads system.mem_ctrl.wrPerTurnAround::gmean 16.000000 # Writes before turning the bus around for reads -system.mem_ctrl.wrPerTurnAround::16 6 100.00% 100.00% # Writes before turning the bus around for reads -system.mem_ctrl.wrPerTurnAround::total 6 # Writes before turning the bus around for reads -system.mem_ctrl.totQLat 29381000 # Total ticks spent queuing -system.mem_ctrl.totMemAccLat 183112250 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrl.totBusLat 40995000 # Total ticks spent in databus transfers -system.mem_ctrl.avgQLat 3583.49 # Average queueing delay per DRAM burst +system.mem_ctrl.wrPerTurnAround::16 7 100.00% 100.00% # Writes before turning the bus around for reads +system.mem_ctrl.wrPerTurnAround::total 7 # Writes before turning the bus around for reads +system.mem_ctrl.totQLat 82515500 # Total ticks spent queuing +system.mem_ctrl.totMemAccLat 236378000 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrl.totBusLat 41030000 # Total ticks spent in databus transfers +system.mem_ctrl.avgQLat 10055.51 # Average queueing delay per DRAM burst system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.mem_ctrl.avgMemAccLat 22333.49 # Average memory access latency per DRAM burst -system.mem_ctrl.avgRdBW 1154.52 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrl.avgWrBW 13.52 # Average achieved write bandwidth in MiByte/s -system.mem_ctrl.avgRdBWSys 143.96 # Average system read bandwidth in MiByte/s -system.mem_ctrl.avgWrBWSys 15.75 # Average system write bandwidth in MiByte/s +system.mem_ctrl.avgMemAccLat 28805.51 # Average memory access latency per DRAM burst +system.mem_ctrl.avgRdBW 1034.15 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrl.avgWrBW 14.11 # Average achieved write bandwidth in MiByte/s +system.mem_ctrl.avgRdBWSys 128.84 # Average system read bandwidth in MiByte/s +system.mem_ctrl.avgWrBWSys 14.10 # Average system write bandwidth in MiByte/s system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrl.busUtil 9.13 # Data bus utilization in percentage -system.mem_ctrl.busUtilRead 9.02 # Data bus utilization in percentage for reads +system.mem_ctrl.busUtil 8.19 # Data bus utilization in percentage +system.mem_ctrl.busUtilRead 8.08 # Data bus utilization in percentage for reads system.mem_ctrl.busUtilWrite 0.11 # Data bus utilization in percentage for writes system.mem_ctrl.avgRdQLen 1.00 # Average read queue length when enqueuing -system.mem_ctrl.avgWrQLen 23.84 # Average write queue length when enqueuing -system.mem_ctrl.readRowHits 7356 # Number of row buffer hits during reads -system.mem_ctrl.writeRowHits 85 # Number of row buffer hits during writes -system.mem_ctrl.readRowHitRate 89.72 # Row buffer hit rate for reads -system.mem_ctrl.writeRowHitRate 69.67 # Row buffer hit rate for writes -system.mem_ctrl.avgGap 48816.18 # Average gap between requests +system.mem_ctrl.avgWrQLen 23.79 # Average write queue length when enqueuing +system.mem_ctrl.readRowHits 7357 # Number of row buffer hits during reads +system.mem_ctrl.writeRowHits 98 # Number of row buffer hits during writes +system.mem_ctrl.readRowHitRate 89.65 # Row buffer hit rate for reads +system.mem_ctrl.writeRowHitRate 74.81 # Row buffer hit rate for writes +system.mem_ctrl.avgGap 54545.44 # Average gap between requests system.mem_ctrl.pageHitRate 89.42 # Row buffer hit rate, read and write combined -system.mem_ctrl_0.actEnergy 3281040 # Energy for activate commands per rank (pJ) -system.mem_ctrl_0.preEnergy 1790250 # Energy for precharge commands per rank (pJ) -system.mem_ctrl_0.readEnergy 40294800 # Energy for read commands per rank (pJ) -system.mem_ctrl_0.writeEnergy 38880 # Energy for write commands per rank (pJ) -system.mem_ctrl_0.refreshEnergy 29496480 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_0.actBackEnergy 248297130 # Energy for active background per rank (pJ) -system.mem_ctrl_0.preBackEnergy 53313000 # Energy for precharge background per rank (pJ) -system.mem_ctrl_0.totalEnergy 376511580 # Total energy per rank (pJ) -system.mem_ctrl_0.averagePower 833.243697 # Core power per rank (mW) -system.mem_ctrl_0.memoryStateTime::IDLE 86206500 # Time in different power states -system.mem_ctrl_0.memoryStateTime::REF 15080000 # Time in different power states -system.mem_ctrl_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrl_0.memoryStateTime::ACT 350589750 # Time in different power states -system.mem_ctrl_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrl_1.actEnergy 3129840 # Energy for activate commands per rank (pJ) -system.mem_ctrl_1.preEnergy 1707750 # Energy for precharge commands per rank (pJ) -system.mem_ctrl_1.readEnergy 23275200 # Energy for read commands per rank (pJ) -system.mem_ctrl_1.writeEnergy 583200 # Energy for write commands per rank (pJ) -system.mem_ctrl_1.refreshEnergy 29496480 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_1.actBackEnergy 273625650 # Energy for active background per rank (pJ) -system.mem_ctrl_1.preBackEnergy 31095000 # Energy for precharge background per rank (pJ) -system.mem_ctrl_1.totalEnergy 362913120 # Total energy per rank (pJ) -system.mem_ctrl_1.averagePower 803.149454 # Core power per rank (mW) -system.mem_ctrl_1.memoryStateTime::IDLE 50725000 # Time in different power states -system.mem_ctrl_1.memoryStateTime::REF 15080000 # Time in different power states -system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrl_1.memoryStateTime::ACT 387261000 # Time in different power states -system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 454507000 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 454507000 # Cumulative time (in ticks) in various power states +system.mem_ctrl_0.actEnergy 3127320 # Energy for activate commands per rank (pJ) +system.mem_ctrl_0.preEnergy 1647030 # Energy for precharge commands per rank (pJ) +system.mem_ctrl_0.readEnergy 37149420 # Energy for read commands per rank (pJ) +system.mem_ctrl_0.writeEnergy 52200 # Energy for write commands per rank (pJ) +system.mem_ctrl_0.refreshEnergy 36263760.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrl_0.actBackEnergy 70559160 # Energy for active background per rank (pJ) +system.mem_ctrl_0.preBackEnergy 1716480 # Energy for precharge background per rank (pJ) +system.mem_ctrl_0.actPowerDownEnergy 113314290 # Energy for active power-down per rank (pJ) +system.mem_ctrl_0.prePowerDownEnergy 13222080 # Energy for precharge power-down per rank (pJ) +system.mem_ctrl_0.selfRefreshEnergy 17426520 # Energy for self refresh per rank (pJ) +system.mem_ctrl_0.totalEnergy 294478260 # Total energy per rank (pJ) +system.mem_ctrl_0.averagePower 579.862821 # Core power per rank (mW) +system.mem_ctrl_0.totalIdleTime 347720500 # Total Idle time Per DRAM Rank +system.mem_ctrl_0.memoryStateTime::IDLE 1584000 # Time in different power states +system.mem_ctrl_0.memoryStateTime::REF 15358000 # Time in different power states +system.mem_ctrl_0.memoryStateTime::SREF 65707000 # Time in different power states +system.mem_ctrl_0.memoryStateTime::PRE_PDN 34427500 # Time in different power states +system.mem_ctrl_0.memoryStateTime::ACT 142245250 # Time in different power states +system.mem_ctrl_0.memoryStateTime::ACT_PDN 248519250 # Time in different power states +system.mem_ctrl_1.actEnergy 3034500 # Energy for activate commands per rank (pJ) +system.mem_ctrl_1.preEnergy 1601490 # Energy for precharge commands per rank (pJ) +system.mem_ctrl_1.readEnergy 21441420 # Energy for read commands per rank (pJ) +system.mem_ctrl_1.writeEnergy 532440 # Energy for write commands per rank (pJ) +system.mem_ctrl_1.refreshEnergy 39336960.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrl_1.actBackEnergy 51598110 # Energy for active background per rank (pJ) +system.mem_ctrl_1.preBackEnergy 1155360 # Energy for precharge background per rank (pJ) +system.mem_ctrl_1.actPowerDownEnergy 151289970 # Energy for active power-down per rank (pJ) +system.mem_ctrl_1.prePowerDownEnergy 18740160 # Energy for precharge power-down per rank (pJ) +system.mem_ctrl_1.selfRefreshEnergy 3216240 # Energy for self refresh per rank (pJ) +system.mem_ctrl_1.totalEnergy 291946650 # Total energy per rank (pJ) +system.mem_ctrl_1.averagePower 574.877779 # Core power per rank (mW) +system.mem_ctrl_1.totalIdleTime 391695500 # Total Idle time Per DRAM Rank +system.mem_ctrl_1.memoryStateTime::IDLE 757000 # Time in different power states +system.mem_ctrl_1.memoryStateTime::REF 16646000 # Time in different power states +system.mem_ctrl_1.memoryStateTime::SREF 11100000 # Time in different power states +system.mem_ctrl_1.memoryStateTime::PRE_PDN 48800500 # Time in different power states +system.mem_ctrl_1.memoryStateTime::ACT 98712250 # Time in different power states +system.mem_ctrl_1.memoryStateTime::ACT_PDN 331825250 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 507841000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 507841000 # Cumulative time (in ticks) in various power states system.cpu.apic_clk_domain.clock 16000 # Clock period in ticks -system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 454507000 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 454507000 # Cumulative time (in ticks) in various power states +system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 507841000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 507841000 # Cumulative time (in ticks) in various power states system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 454507000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 454507 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 507841000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 507841 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 5712 # Number of instructions committed @@ -301,7 +312,7 @@ system.cpu.num_mem_refs 2025 # nu system.cpu.num_load_insts 1084 # Number of load instructions system.cpu.num_store_insts 941 # Number of store instructions system.cpu.num_idle_cycles 0.001000 # Number of idle cycles -system.cpu.num_busy_cycles 454506.999000 # Number of busy cycles +system.cpu.num_busy_cycles 507840.999000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 1306 # Number of branches fetched @@ -346,7 +357,7 @@ system.membus.snoop_filter.hit_multi_requests 0 system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 454507000 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 507841000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 8367 # Transaction distribution system.membus.trans_dist::ReadResp 8367 # Transaction distribution system.membus.trans_dist::WriteReq 941 # Transaction distribution @@ -374,10 +385,10 @@ system.membus.snoop_fanout::min_value 0 # Re system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 9308 # Request fanout histogram system.membus.reqLayer2.occupancy 10249000 # Layer occupancy (ticks) -system.membus.reqLayer2.utilization 2.3 # Layer utilization (%) -system.membus.respLayer0.occupancy 16547250 # Layer occupancy (ticks) -system.membus.respLayer0.utilization 3.6 # Layer utilization (%) -system.membus.respLayer1.occupancy 3431500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.8 # Layer utilization (%) +system.membus.reqLayer2.utilization 2.0 # Layer utilization (%) +system.membus.respLayer0.occupancy 16544750 # Layer occupancy (ticks) +system.membus.respLayer0.utilization 3.3 # Layer utilization (%) +system.membus.respLayer1.occupancy 3432250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.7 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/config.ini b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/config.ini index 1ce461f16..c3a9301a3 100644 --- a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/config.ini +++ b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/config.ini @@ -23,7 +23,7 @@ kernel_addr_check=true load_addr_mask=1099511627775 load_offset=0 mem_mode=timing -mem_ranges=0:536870911 +mem_ranges=0:536870911:0:0:0:0 memories=system.mem_ctrl mmap_using_noreserve=false multi_thread=false @@ -106,7 +106,7 @@ eventq_index=0 [system.cpu.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.clk_domain clusivity=mostly_incl @@ -171,7 +171,7 @@ system=system [system.cpu.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.clk_domain clusivity=mostly_incl @@ -321,7 +321,7 @@ system=system [system.l2cache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.clk_domain clusivity=mostly_incl @@ -366,27 +366,27 @@ size=262144 [system.mem_ctrl] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -406,6 +406,7 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 @@ -415,7 +416,7 @@ p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 page_policy=open_adaptive power_model=Null -range=0:536870911 +range=0:536870911:0:0:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 @@ -437,9 +438,9 @@ tRTW=2500 tWR=15000 tWTR=7500 tXAW=30000 -tXP=0 +tXP=6000 tXPDLL=0 -tXS=0 +tXS=270000 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 @@ -448,6 +449,7 @@ port=system.membus.master[2] [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -459,7 +461,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -467,3 +469,10 @@ width=16 master=system.cpu.interrupts.pio system.cpu.interrupts.int_slave system.mem_ctrl.port slave=system.l2cache.mem_side system.cpu.interrupts.int_master system.system_port +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + diff --git a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/simout b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/simout index cdf63e901..736ff89ea 100755 --- a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/simout +++ b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/simout @@ -3,13 +3,13 @@ Redirecting stderr to build/X86/tests/opt/quick/se/03.learning-gem5/x86/linux/le gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:35:23 -gem5 started Jul 21 2016 14:36:17 -gem5 executing on e108600-lin, pid 18545 +gem5 compiled Oct 11 2016 00:00:58 +gem5 started Oct 13 2016 21:09:22 +gem5 executing on e108600-lin, pid 17647 command line: /work/curdun01/gem5-external.hg/build/X86/gem5.opt -d build/X86/tests/opt/quick/se/03.learning-gem5/x86/linux/learning-gem5-p1-two-level -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/03.learning-gem5/x86/linux/learning-gem5-p1-two-level Global frequency set at 1000000000000 ticks per second Beginning simulation! info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 55844000 because target called exit() +Exiting @ tick 58513000 because target called exit() diff --git a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/stats.txt b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/stats.txt index a74924642..bf9b895e3 100644 --- a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000056 # Number of seconds simulated -sim_ticks 56435000 # Number of ticks simulated -final_tick 56435000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000059 # Number of seconds simulated +sim_ticks 58513000 # Number of ticks simulated +final_tick 58513000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 125605 # Simulator instruction rate (inst/s) -host_op_rate 226732 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1240265940 # Simulator tick rate (ticks/s) -host_mem_usage 656384 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host +host_inst_rate 325988 # Simulator instruction rate (inst/s) +host_op_rate 588251 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3335289412 # Simulator tick rate (ticks/s) +host_mem_usage 654560 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host sim_insts 5712 # Number of instructions simulated sim_ops 10314 # Number of ops (including micro ops) simulated system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states +system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 58513000 # Cumulative time (in ticks) in various power states system.mem_ctrl.bytes_read::cpu.inst 14656 # Number of bytes read from this memory system.mem_ctrl.bytes_read::cpu.data 8640 # Number of bytes read from this memory system.mem_ctrl.bytes_read::total 23296 # Number of bytes read from this memory @@ -22,14 +22,14 @@ system.mem_ctrl.bytes_inst_read::total 14656 # Nu system.mem_ctrl.num_reads::cpu.inst 229 # Number of read requests responded to by this memory system.mem_ctrl.num_reads::cpu.data 135 # Number of read requests responded to by this memory system.mem_ctrl.num_reads::total 364 # Number of read requests responded to by this memory -system.mem_ctrl.bw_read::cpu.inst 259696997 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::cpu.data 153096483 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::total 412793479 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::cpu.inst 259696997 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::total 259696997 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.inst 259696997 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.data 153096483 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::total 412793479 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_read::cpu.inst 250474254 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::cpu.data 147659494 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::total 398133748 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::cpu.inst 250474254 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::total 250474254 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.inst 250474254 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.data 147659494 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::total 398133748 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrl.readReqs 364 # Number of read requests accepted system.mem_ctrl.writeReqs 0 # Number of write requests accepted system.mem_ctrl.readBursts 364 # Number of DRAM read bursts, including those serviced by the write queue @@ -76,7 +76,7 @@ system.mem_ctrl.perBankWrBursts::14 0 # Pe system.mem_ctrl.perBankWrBursts::15 0 # Per bank write bursts system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrl.totGap 56304000 # Total gap between requests +system.mem_ctrl.totGap 58376000 # Total gap between requests system.mem_ctrl.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrl.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrl.readPktSize::2 0 # Read request sizes (log2) @@ -187,77 +187,88 @@ system.mem_ctrl.wrQLenPdf::60 0 # Wh system.mem_ctrl.wrQLenPdf::61 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrl.bytesPerActivate::samples 117 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::mean 193.094017 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::gmean 128.926887 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::stdev 215.889898 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::0-127 57 48.72% 48.72% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::128-255 28 23.93% 72.65% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::256-383 16 13.68% 86.32% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::384-511 6 5.13% 91.45% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::512-639 2 1.71% 93.16% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::640-767 2 1.71% 94.87% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::768-895 3 2.56% 97.44% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::1024-1151 3 2.56% 100.00% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::total 117 # Bytes accessed per row activation -system.mem_ctrl.totQLat 3777750 # Total ticks spent queuing -system.mem_ctrl.totMemAccLat 10602750 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrl.bytesPerActivate::samples 108 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::mean 199.703704 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::gmean 135.091179 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::stdev 199.282229 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::0-127 52 48.15% 48.15% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::128-255 21 19.44% 67.59% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::256-383 15 13.89% 81.48% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::384-511 8 7.41% 88.89% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::512-639 7 6.48% 95.37% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::640-767 2 1.85% 97.22% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::768-895 1 0.93% 98.15% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::896-1023 1 0.93% 99.07% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::1024-1151 1 0.93% 100.00% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::total 108 # Bytes accessed per row activation +system.mem_ctrl.totQLat 5858750 # Total ticks spent queuing +system.mem_ctrl.totMemAccLat 12683750 # Total ticks spent from burst creation until serviced by the DRAM system.mem_ctrl.totBusLat 1820000 # Total ticks spent in databus transfers -system.mem_ctrl.avgQLat 10378.43 # Average queueing delay per DRAM burst +system.mem_ctrl.avgQLat 16095.47 # Average queueing delay per DRAM burst system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.mem_ctrl.avgMemAccLat 29128.43 # Average memory access latency per DRAM burst -system.mem_ctrl.avgRdBW 412.79 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrl.avgMemAccLat 34845.47 # Average memory access latency per DRAM burst +system.mem_ctrl.avgRdBW 398.13 # Average DRAM read bandwidth in MiByte/s system.mem_ctrl.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.mem_ctrl.avgRdBWSys 412.79 # Average system read bandwidth in MiByte/s +system.mem_ctrl.avgRdBWSys 398.13 # Average system read bandwidth in MiByte/s system.mem_ctrl.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrl.busUtil 3.22 # Data bus utilization in percentage -system.mem_ctrl.busUtilRead 3.22 # Data bus utilization in percentage for reads +system.mem_ctrl.busUtil 3.11 # Data bus utilization in percentage +system.mem_ctrl.busUtilRead 3.11 # Data bus utilization in percentage for reads system.mem_ctrl.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.mem_ctrl.avgRdQLen 1.00 # Average read queue length when enqueuing system.mem_ctrl.avgWrQLen 0.00 # Average write queue length when enqueuing -system.mem_ctrl.readRowHits 241 # Number of row buffer hits during reads +system.mem_ctrl.readRowHits 248 # Number of row buffer hits during reads system.mem_ctrl.writeRowHits 0 # Number of row buffer hits during writes -system.mem_ctrl.readRowHitRate 66.21 # Row buffer hit rate for reads +system.mem_ctrl.readRowHitRate 68.13 # Row buffer hit rate for reads system.mem_ctrl.writeRowHitRate nan # Row buffer hit rate for writes -system.mem_ctrl.avgGap 154681.32 # Average gap between requests -system.mem_ctrl.pageHitRate 66.21 # Row buffer hit rate, read and write combined -system.mem_ctrl_0.actEnergy 309960 # Energy for activate commands per rank (pJ) -system.mem_ctrl_0.preEnergy 169125 # Energy for precharge commands per rank (pJ) -system.mem_ctrl_0.readEnergy 1201200 # Energy for read commands per rank (pJ) +system.mem_ctrl.avgGap 160373.63 # Average gap between requests +system.mem_ctrl.pageHitRate 68.13 # Row buffer hit rate, read and write combined +system.mem_ctrl_0.actEnergy 292740 # Energy for activate commands per rank (pJ) +system.mem_ctrl_0.preEnergy 136620 # Energy for precharge commands per rank (pJ) +system.mem_ctrl_0.readEnergy 1170960 # Energy for read commands per rank (pJ) system.mem_ctrl_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.mem_ctrl_0.refreshEnergy 3559920 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_0.actBackEnergy 32277105 # Energy for active background per rank (pJ) -system.mem_ctrl_0.preBackEnergy 4545000 # Energy for precharge background per rank (pJ) -system.mem_ctrl_0.totalEnergy 42062310 # Total energy per rank (pJ) -system.mem_ctrl_0.averagePower 768.068476 # Core power per rank (mW) -system.mem_ctrl_0.memoryStateTime::IDLE 7392500 # Time in different power states +system.mem_ctrl_0.refreshEnergy 4302480.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrl_0.actBackEnergy 2975970 # Energy for active background per rank (pJ) +system.mem_ctrl_0.preBackEnergy 96960 # Energy for precharge background per rank (pJ) +system.mem_ctrl_0.actPowerDownEnergy 20164320 # Energy for active power-down per rank (pJ) +system.mem_ctrl_0.prePowerDownEnergy 2885760 # Energy for precharge power-down per rank (pJ) +system.mem_ctrl_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrl_0.totalEnergy 32025810 # Total energy per rank (pJ) +system.mem_ctrl_0.averagePower 547.321100 # Core power per rank (mW) +system.mem_ctrl_0.totalIdleTime 51467750 # Total Idle time Per DRAM Rank +system.mem_ctrl_0.memoryStateTime::IDLE 59000 # Time in different power states system.mem_ctrl_0.memoryStateTime::REF 1820000 # Time in different power states -system.mem_ctrl_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrl_0.memoryStateTime::ACT 45565000 # Time in different power states -system.mem_ctrl_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrl_1.actEnergy 574560 # Energy for activate commands per rank (pJ) -system.mem_ctrl_1.preEnergy 313500 # Energy for precharge commands per rank (pJ) -system.mem_ctrl_1.readEnergy 1552200 # Energy for read commands per rank (pJ) +system.mem_ctrl_0.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrl_0.memoryStateTime::PRE_PDN 7513000 # Time in different power states +system.mem_ctrl_0.memoryStateTime::ACT 4902000 # Time in different power states +system.mem_ctrl_0.memoryStateTime::ACT_PDN 44219000 # Time in different power states +system.mem_ctrl_1.actEnergy 535500 # Energy for activate commands per rank (pJ) +system.mem_ctrl_1.preEnergy 273240 # Energy for precharge commands per rank (pJ) +system.mem_ctrl_1.readEnergy 1428000 # Energy for read commands per rank (pJ) system.mem_ctrl_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.mem_ctrl_1.refreshEnergy 3559920 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_1.actBackEnergy 36915480 # Energy for active background per rank (pJ) -system.mem_ctrl_1.preBackEnergy 476250 # Energy for precharge background per rank (pJ) -system.mem_ctrl_1.totalEnergy 43391910 # Total energy per rank (pJ) -system.mem_ctrl_1.averagePower 792.347310 # Core power per rank (mW) -system.mem_ctrl_1.memoryStateTime::IDLE 2122500 # Time in different power states +system.mem_ctrl_1.refreshEnergy 4302480.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrl_1.actBackEnergy 3735210 # Energy for active background per rank (pJ) +system.mem_ctrl_1.preBackEnergy 150720 # Energy for precharge background per rank (pJ) +system.mem_ctrl_1.actPowerDownEnergy 22328040 # Energy for active power-down per rank (pJ) +system.mem_ctrl_1.prePowerDownEnergy 370560 # Energy for precharge power-down per rank (pJ) +system.mem_ctrl_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrl_1.totalEnergy 33123750 # Total energy per rank (pJ) +system.mem_ctrl_1.averagePower 566.084895 # Core power per rank (mW) +system.mem_ctrl_1.totalIdleTime 49870500 # Total Idle time Per DRAM Rank +system.mem_ctrl_1.memoryStateTime::IDLE 184000 # Time in different power states system.mem_ctrl_1.memoryStateTime::REF 1820000 # Time in different power states -system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrl_1.memoryStateTime::ACT 52384500 # Time in different power states -system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states +system.mem_ctrl_1.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrl_1.memoryStateTime::PRE_PDN 965000 # Time in different power states +system.mem_ctrl_1.memoryStateTime::ACT 6563000 # Time in different power states +system.mem_ctrl_1.memoryStateTime::ACT_PDN 48981000 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 58513000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 58513000 # Cumulative time (in ticks) in various power states system.cpu.apic_clk_domain.clock 16000 # Clock period in ticks -system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states +system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 58513000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 58513000 # Cumulative time (in ticks) in various power states system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 56435000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 56435 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 58513000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 58513 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 5712 # Number of instructions committed @@ -278,7 +289,7 @@ system.cpu.num_mem_refs 2025 # nu system.cpu.num_load_insts 1084 # Number of load instructions system.cpu.num_store_insts 941 # Number of store instructions system.cpu.num_idle_cycles 0.001000 # Number of idle cycles -system.cpu.num_busy_cycles 56434.999000 # Number of busy cycles +system.cpu.num_busy_cycles 58512.999000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 1306 # Number of branches fetched @@ -317,23 +328,23 @@ system.cpu.op_class::MemWrite 941 9.12% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 10314 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 58513000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 81.661133 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 81.299644 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1890 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 135 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 14 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 81.661133 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.079747 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.079747 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 81.299644 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.079394 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.079394 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 135 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 12 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 123 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.131836 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 4185 # Number of tag accesses system.cpu.dcache.tags.data_accesses 4185 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 58513000 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 1028 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1028 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 862 # number of WriteReq hits @@ -350,14 +361,14 @@ system.cpu.dcache.demand_misses::cpu.data 135 # n system.cpu.dcache.demand_misses::total 135 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 135 # number of overall misses system.cpu.dcache.overall_misses::total 135 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 6076000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 6076000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 8376000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 8376000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 14452000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 14452000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 14452000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 14452000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 6406000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 6406000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 8602000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 8602000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 15008000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 15008000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 15008000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 15008000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1084 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1084 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 941 # number of WriteReq accesses(hits+misses) @@ -374,14 +385,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.066667 system.cpu.dcache.demand_miss_rate::total 0.066667 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.066667 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.066667 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 108500 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 108500 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 106025.316456 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 106025.316456 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 107051.851852 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 107051.851852 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 107051.851852 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 107051.851852 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 114392.857143 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 114392.857143 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 108886.075949 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 108886.075949 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 111170.370370 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 111170.370370 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 111170.370370 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 111170.370370 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -396,14 +407,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 135 system.cpu.dcache.demand_mshr_misses::total 135 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 135 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5964000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5964000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8218000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8218000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14182000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 14182000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14182000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 14182000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6294000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6294000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8444000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8444000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14738000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 14738000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14738000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 14738000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.051661 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.051661 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083953 # mshr miss rate for WriteReq accesses @@ -412,31 +423,31 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.066667 system.cpu.dcache.demand_mshr_miss_rate::total 0.066667 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.066667 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.066667 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 106500 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 106500 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 104025.316456 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 104025.316456 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 105051.851852 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 105051.851852 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 105051.851852 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 105051.851852 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 112392.857143 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 112392.857143 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 106886.075949 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 106886.075949 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 109170.370370 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 109170.370370 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 109170.370370 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 109170.370370 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 58513000 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 58 # number of replacements -system.cpu.icache.tags.tagsinuse 91.248553 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 90.704136 # Cycle average of tags in use system.cpu.icache.tags.total_refs 7048 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 235 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 29.991489 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 91.248553 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.356440 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.356440 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 90.704136 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.354313 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.354313 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 177 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 43 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 134 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.691406 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 14801 # Number of tag accesses system.cpu.icache.tags.data_accesses 14801 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 58513000 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 7048 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 7048 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 7048 # number of demand (read+write) hits @@ -449,12 +460,12 @@ system.cpu.icache.demand_misses::cpu.inst 235 # n system.cpu.icache.demand_misses::total 235 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 235 # number of overall misses system.cpu.icache.overall_misses::total 235 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 24107000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 24107000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 24107000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 24107000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 24107000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 24107000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 25629000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 25629000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 25629000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 25629000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 25629000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 25629000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 7283 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 7283 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 7283 # number of demand (read+write) accesses @@ -467,12 +478,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.032267 system.cpu.icache.demand_miss_rate::total 0.032267 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.032267 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.032267 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 102582.978723 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 102582.978723 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 102582.978723 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 102582.978723 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 102582.978723 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 102582.978723 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 109059.574468 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 109059.574468 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 109059.574468 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 109059.574468 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 109059.574468 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 109059.574468 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -485,31 +496,31 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 235 system.cpu.icache.demand_mshr_misses::total 235 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 235 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 235 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23637000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 23637000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23637000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 23637000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23637000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 23637000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25159000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 25159000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25159000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 25159000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25159000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 25159000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.032267 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.032267 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.032267 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.032267 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.032267 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.032267 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 100582.978723 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 100582.978723 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 100582.978723 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 100582.978723 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 100582.978723 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 100582.978723 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 107059.574468 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 107059.574468 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 107059.574468 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 107059.574468 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 107059.574468 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 107059.574468 # average overall mshr miss latency system.l2bus.snoop_filter.tot_requests 428 # Total number of requests made to the snoop filter. system.l2bus.snoop_filter.hit_single_requests 59 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.l2bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.l2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.l2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.l2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.l2bus.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states +system.l2bus.pwrStateResidencyTicks::UNDEFINED 58513000 # Cumulative time (in ticks) in various power states system.l2bus.trans_dist::ReadResp 291 # Transaction distribution system.l2bus.trans_dist::CleanEvict 58 # Transaction distribution system.l2bus.trans_dist::ReadExReq 79 # Transaction distribution @@ -535,30 +546,30 @@ system.l2bus.snoop_fanout::min_value 0 # Re system.l2bus.snoop_fanout::max_value 1 # Request fanout histogram system.l2bus.snoop_fanout::total 370 # Request fanout histogram system.l2bus.reqLayer0.occupancy 428000 # Layer occupancy (ticks) -system.l2bus.reqLayer0.utilization 0.8 # Layer utilization (%) +system.l2bus.reqLayer0.utilization 0.7 # Layer utilization (%) system.l2bus.respLayer0.occupancy 705000 # Layer occupancy (ticks) system.l2bus.respLayer0.utilization 1.2 # Layer utilization (%) system.l2bus.respLayer1.occupancy 405000 # Layer occupancy (ticks) system.l2bus.respLayer1.utilization 0.7 # Layer utilization (%) -system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states +system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 58513000 # Cumulative time (in ticks) in various power states system.l2cache.tags.replacements 0 # number of replacements -system.l2cache.tags.tagsinuse 188.623694 # Cycle average of tags in use +system.l2cache.tags.tagsinuse 187.541609 # Cycle average of tags in use system.l2cache.tags.total_refs 64 # Total number of references to valid blocks. system.l2cache.tags.sampled_refs 364 # Sample count of references to valid blocks. system.l2cache.tags.avg_refs 0.175824 # Average number of references to valid blocks. system.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2cache.tags.occ_blocks::cpu.inst 106.912326 # Average occupied blocks per requestor -system.l2cache.tags.occ_blocks::cpu.data 81.711368 # Average occupied blocks per requestor -system.l2cache.tags.occ_percent::cpu.inst 0.026102 # Average percentage of cache occupancy -system.l2cache.tags.occ_percent::cpu.data 0.019949 # Average percentage of cache occupancy -system.l2cache.tags.occ_percent::total 0.046051 # Average percentage of cache occupancy +system.l2cache.tags.occ_blocks::cpu.inst 106.193515 # Average occupied blocks per requestor +system.l2cache.tags.occ_blocks::cpu.data 81.348095 # Average occupied blocks per requestor +system.l2cache.tags.occ_percent::cpu.inst 0.025926 # Average percentage of cache occupancy +system.l2cache.tags.occ_percent::cpu.data 0.019860 # Average percentage of cache occupancy +system.l2cache.tags.occ_percent::total 0.045787 # Average percentage of cache occupancy system.l2cache.tags.occ_task_id_blocks::1024 364 # Occupied blocks per task id system.l2cache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id system.l2cache.tags.age_task_id_blocks_1024::1 309 # Occupied blocks per task id system.l2cache.tags.occ_task_id_percent::1024 0.088867 # Percentage of cache occupancy per task id system.l2cache.tags.tag_accesses 3788 # Number of tag accesses system.l2cache.tags.data_accesses 3788 # Number of data accesses -system.l2cache.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states +system.l2cache.pwrStateResidencyTicks::UNDEFINED 58513000 # Cumulative time (in ticks) in various power states system.l2cache.ReadSharedReq_hits::cpu.inst 6 # number of ReadSharedReq hits system.l2cache.ReadSharedReq_hits::total 6 # number of ReadSharedReq hits system.l2cache.demand_hits::cpu.inst 6 # number of demand (read+write) hits @@ -576,17 +587,17 @@ system.l2cache.demand_misses::total 364 # nu system.l2cache.overall_misses::cpu.inst 229 # number of overall misses system.l2cache.overall_misses::cpu.data 135 # number of overall misses system.l2cache.overall_misses::total 364 # number of overall misses -system.l2cache.ReadExReq_miss_latency::cpu.data 7981000 # number of ReadExReq miss cycles -system.l2cache.ReadExReq_miss_latency::total 7981000 # number of ReadExReq miss cycles -system.l2cache.ReadSharedReq_miss_latency::cpu.inst 22804000 # number of ReadSharedReq miss cycles -system.l2cache.ReadSharedReq_miss_latency::cpu.data 5796000 # number of ReadSharedReq miss cycles -system.l2cache.ReadSharedReq_miss_latency::total 28600000 # number of ReadSharedReq miss cycles -system.l2cache.demand_miss_latency::cpu.inst 22804000 # number of demand (read+write) miss cycles -system.l2cache.demand_miss_latency::cpu.data 13777000 # number of demand (read+write) miss cycles -system.l2cache.demand_miss_latency::total 36581000 # number of demand (read+write) miss cycles -system.l2cache.overall_miss_latency::cpu.inst 22804000 # number of overall miss cycles -system.l2cache.overall_miss_latency::cpu.data 13777000 # number of overall miss cycles -system.l2cache.overall_miss_latency::total 36581000 # number of overall miss cycles +system.l2cache.ReadExReq_miss_latency::cpu.data 8207000 # number of ReadExReq miss cycles +system.l2cache.ReadExReq_miss_latency::total 8207000 # number of ReadExReq miss cycles +system.l2cache.ReadSharedReq_miss_latency::cpu.inst 24326000 # number of ReadSharedReq miss cycles +system.l2cache.ReadSharedReq_miss_latency::cpu.data 6126000 # number of ReadSharedReq miss cycles +system.l2cache.ReadSharedReq_miss_latency::total 30452000 # number of ReadSharedReq miss cycles +system.l2cache.demand_miss_latency::cpu.inst 24326000 # number of demand (read+write) miss cycles +system.l2cache.demand_miss_latency::cpu.data 14333000 # number of demand (read+write) miss cycles +system.l2cache.demand_miss_latency::total 38659000 # number of demand (read+write) miss cycles +system.l2cache.overall_miss_latency::cpu.inst 24326000 # number of overall miss cycles +system.l2cache.overall_miss_latency::cpu.data 14333000 # number of overall miss cycles +system.l2cache.overall_miss_latency::total 38659000 # number of overall miss cycles system.l2cache.ReadExReq_accesses::cpu.data 79 # number of ReadExReq accesses(hits+misses) system.l2cache.ReadExReq_accesses::total 79 # number of ReadExReq accesses(hits+misses) system.l2cache.ReadSharedReq_accesses::cpu.inst 235 # number of ReadSharedReq accesses(hits+misses) @@ -609,17 +620,17 @@ system.l2cache.demand_miss_rate::total 0.983784 # mi system.l2cache.overall_miss_rate::cpu.inst 0.974468 # miss rate for overall accesses system.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.l2cache.overall_miss_rate::total 0.983784 # miss rate for overall accesses -system.l2cache.ReadExReq_avg_miss_latency::cpu.data 101025.316456 # average ReadExReq miss latency -system.l2cache.ReadExReq_avg_miss_latency::total 101025.316456 # average ReadExReq miss latency -system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 99580.786026 # average ReadSharedReq miss latency -system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 103500 # average ReadSharedReq miss latency -system.l2cache.ReadSharedReq_avg_miss_latency::total 100350.877193 # average ReadSharedReq miss latency -system.l2cache.demand_avg_miss_latency::cpu.inst 99580.786026 # average overall miss latency -system.l2cache.demand_avg_miss_latency::cpu.data 102051.851852 # average overall miss latency -system.l2cache.demand_avg_miss_latency::total 100497.252747 # average overall miss latency -system.l2cache.overall_avg_miss_latency::cpu.inst 99580.786026 # average overall miss latency -system.l2cache.overall_avg_miss_latency::cpu.data 102051.851852 # average overall miss latency -system.l2cache.overall_avg_miss_latency::total 100497.252747 # average overall miss latency +system.l2cache.ReadExReq_avg_miss_latency::cpu.data 103886.075949 # average ReadExReq miss latency +system.l2cache.ReadExReq_avg_miss_latency::total 103886.075949 # average ReadExReq miss latency +system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 106227.074236 # average ReadSharedReq miss latency +system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 109392.857143 # average ReadSharedReq miss latency +system.l2cache.ReadSharedReq_avg_miss_latency::total 106849.122807 # average ReadSharedReq miss latency +system.l2cache.demand_avg_miss_latency::cpu.inst 106227.074236 # average overall miss latency +system.l2cache.demand_avg_miss_latency::cpu.data 106170.370370 # average overall miss latency +system.l2cache.demand_avg_miss_latency::total 106206.043956 # average overall miss latency +system.l2cache.overall_avg_miss_latency::cpu.inst 106227.074236 # average overall miss latency +system.l2cache.overall_avg_miss_latency::cpu.data 106170.370370 # average overall miss latency +system.l2cache.overall_avg_miss_latency::total 106206.043956 # average overall miss latency system.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -637,17 +648,17 @@ system.l2cache.demand_mshr_misses::total 364 # nu system.l2cache.overall_mshr_misses::cpu.inst 229 # number of overall MSHR misses system.l2cache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses system.l2cache.overall_mshr_misses::total 364 # number of overall MSHR misses -system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6401000 # number of ReadExReq MSHR miss cycles -system.l2cache.ReadExReq_mshr_miss_latency::total 6401000 # number of ReadExReq MSHR miss cycles -system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 18224000 # number of ReadSharedReq MSHR miss cycles -system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4676000 # number of ReadSharedReq MSHR miss cycles -system.l2cache.ReadSharedReq_mshr_miss_latency::total 22900000 # number of ReadSharedReq MSHR miss cycles -system.l2cache.demand_mshr_miss_latency::cpu.inst 18224000 # number of demand (read+write) MSHR miss cycles -system.l2cache.demand_mshr_miss_latency::cpu.data 11077000 # number of demand (read+write) MSHR miss cycles -system.l2cache.demand_mshr_miss_latency::total 29301000 # number of demand (read+write) MSHR miss cycles -system.l2cache.overall_mshr_miss_latency::cpu.inst 18224000 # number of overall MSHR miss cycles -system.l2cache.overall_mshr_miss_latency::cpu.data 11077000 # number of overall MSHR miss cycles -system.l2cache.overall_mshr_miss_latency::total 29301000 # number of overall MSHR miss cycles +system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6627000 # number of ReadExReq MSHR miss cycles +system.l2cache.ReadExReq_mshr_miss_latency::total 6627000 # number of ReadExReq MSHR miss cycles +system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 19746000 # number of ReadSharedReq MSHR miss cycles +system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5006000 # number of ReadSharedReq MSHR miss cycles +system.l2cache.ReadSharedReq_mshr_miss_latency::total 24752000 # number of ReadSharedReq MSHR miss cycles +system.l2cache.demand_mshr_miss_latency::cpu.inst 19746000 # number of demand (read+write) MSHR miss cycles +system.l2cache.demand_mshr_miss_latency::cpu.data 11633000 # number of demand (read+write) MSHR miss cycles +system.l2cache.demand_mshr_miss_latency::total 31379000 # number of demand (read+write) MSHR miss cycles +system.l2cache.overall_mshr_miss_latency::cpu.inst 19746000 # number of overall MSHR miss cycles +system.l2cache.overall_mshr_miss_latency::cpu.data 11633000 # number of overall MSHR miss cycles +system.l2cache.overall_mshr_miss_latency::total 31379000 # number of overall MSHR miss cycles system.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.inst 0.974468 # mshr miss rate for ReadSharedReq accesses @@ -659,24 +670,24 @@ system.l2cache.demand_mshr_miss_rate::total 0.983784 # system.l2cache.overall_mshr_miss_rate::cpu.inst 0.974468 # mshr miss rate for overall accesses system.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.l2cache.overall_mshr_miss_rate::total 0.983784 # mshr miss rate for overall accesses -system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 81025.316456 # average ReadExReq mshr miss latency -system.l2cache.ReadExReq_avg_mshr_miss_latency::total 81025.316456 # average ReadExReq mshr miss latency -system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 79580.786026 # average ReadSharedReq mshr miss latency -system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 83500 # average ReadSharedReq mshr miss latency -system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 80350.877193 # average ReadSharedReq mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 79580.786026 # average overall mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::cpu.data 82051.851852 # average overall mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::total 80497.252747 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 79580.786026 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::cpu.data 82051.851852 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::total 80497.252747 # average overall mshr miss latency +system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 83886.075949 # average ReadExReq mshr miss latency +system.l2cache.ReadExReq_avg_mshr_miss_latency::total 83886.075949 # average ReadExReq mshr miss latency +system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 86227.074236 # average ReadSharedReq mshr miss latency +system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 89392.857143 # average ReadSharedReq mshr miss latency +system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 86849.122807 # average ReadSharedReq mshr miss latency +system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 86227.074236 # average overall mshr miss latency +system.l2cache.demand_avg_mshr_miss_latency::cpu.data 86170.370370 # average overall mshr miss latency +system.l2cache.demand_avg_mshr_miss_latency::total 86206.043956 # average overall mshr miss latency +system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 86227.074236 # average overall mshr miss latency +system.l2cache.overall_avg_mshr_miss_latency::cpu.data 86170.370370 # average overall mshr miss latency +system.l2cache.overall_avg_mshr_miss_latency::total 86206.043956 # average overall mshr miss latency system.membus.snoop_filter.tot_requests 364 # Total number of requests made to the snoop filter. system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 56435000 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 58513000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 285 # Transaction distribution system.membus.trans_dist::ReadExReq 79 # Transaction distribution system.membus.trans_dist::ReadExResp 79 # Transaction distribution @@ -701,7 +712,7 @@ system.membus.snoop_fanout::max_value 0 # Re system.membus.snoop_fanout::total 364 # Request fanout histogram system.membus.reqLayer2.occupancy 364000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.6 # Layer utilization (%) -system.membus.respLayer0.occupancy 1954250 # Layer occupancy (ticks) -system.membus.respLayer0.utilization 3.5 # Layer utilization (%) +system.membus.respLayer0.occupancy 1951250 # Layer occupancy (ticks) +system.membus.respLayer0.utilization 3.3 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_RfO/config.ini b/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_RfO/config.ini index 19a9a115f..bd0cc03e4 100644 --- a/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_RfO/config.ini +++ b/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_RfO/config.ini @@ -14,6 +14,7 @@ children=clk_domain cp_cntrl0 cpu0 cpu1 cpu2 dir_cntrl0 dispatcher_coalescer dis boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 exit_on_work_items=false init_param=0 @@ -22,13 +23,19 @@ kernel_addr_check=true load_addr_mask=1099511627775 load_offset=0 mem_mode=timing -mem_ranges=0:536870911 +mem_ranges=0:536870911:0:0:0:0 memories=system.mem_ctrls system.ruby.phys_mem mmap_using_noreserve=false multi_thread=false num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null readfile= symbolfile= +thermal_components= +thermal_model=Null work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -56,11 +63,16 @@ L2cache=system.cp_cntrl0.L2cache buffer_size=0 clk_domain=system.clk_domain cluster_id=0 +default_p_state=UNDEFINED eventq_index=0 issue_latency=15 l2_hit_latency=18 mandatoryQueue=system.cp_cntrl0.mandatoryQueue number_of_TBEs=256 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null probeToCore=system.cp_cntrl0.probeToCore recycle_latency=10 requestFromCore=system.cp_cntrl0.requestFromCore @@ -218,17 +230,22 @@ coreid=0 dcache=system.cp_cntrl0.L1D0cache dcache_hit_latency=2 deadlock_threshold=500000 +default_p_state=UNDEFINED eventq_index=0 +garnet_standalone=false icache=system.cp_cntrl0.L1Icache icache_hit_latency=2 is_cpu_sequencer=true max_outstanding_requests=16 no_retry_on_stall=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null ruby_system=system.ruby support_data_reqs=true support_inst_reqs=true system=system -using_network_tester=false using_ruby_tester=false version=0 master=system.cpu0.interrupts.pio system.cpu0.interrupts.int_slave @@ -242,17 +259,22 @@ coreid=1 dcache=system.cp_cntrl0.L1D1cache dcache_hit_latency=2 deadlock_threshold=500000 +default_p_state=UNDEFINED eventq_index=0 +garnet_standalone=false icache=system.cp_cntrl0.L1Icache icache_hit_latency=2 is_cpu_sequencer=true max_outstanding_requests=16 no_retry_on_stall=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null ruby_system=system.ruby support_data_reqs=true support_inst_reqs=true system=system -using_network_tester=false using_ruby_tester=false version=1 @@ -278,6 +300,7 @@ branchPred=Null checker=Null clk_domain=system.cpu0.clk_domain cpu_id=0 +default_p_state=UNDEFINED do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true @@ -293,6 +316,10 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null profile=0 progress_interval=0 simpoint_start_insts= @@ -328,18 +355,28 @@ walker=system.cpu0.dtb.walker [system.cpu0.dtb.walker] type=X86PagetableWalker clk_domain=system.cpu0.clk_domain +default_p_state=UNDEFINED eventq_index=0 num_squash_per_cycle=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null system=system port=system.cp_cntrl0.sequencer.slave[3] [system.cpu0.interrupts] type=X86LocalApic clk_domain=system.cpu0.apic_clk_domain +default_p_state=UNDEFINED eventq_index=0 int_latency=1000 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=2305843009213693952 pio_latency=100000 +power_model=Null system=system int_master=system.cp_cntrl0.sequencer.slave[4] int_slave=system.cp_cntrl0.sequencer.master[1] @@ -359,8 +396,13 @@ walker=system.cpu0.itb.walker [system.cpu0.itb.walker] type=X86PagetableWalker clk_domain=system.cpu0.clk_domain +default_p_state=UNDEFINED eventq_index=0 num_squash_per_cycle=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null system=system port=system.cp_cntrl0.sequencer.slave[2] @@ -378,7 +420,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/gpu-hello/bin/x86/linux/gpu-hello +executable=/arm/projectscratch/randd/systems/dist/test-progs/gpu-hello/bin/x86/linux/gpu-hello gid=100 input=cin kvmInSE=false @@ -397,10 +439,15 @@ children=CUs0 CUs1 clk_domain CUs=system.cpu1.CUs0 system.cpu1.CUs1 clk_domain=system.cpu1.clk_domain cpu_pointer=system.cpu0 +default_p_state=UNDEFINED eventq_index=0 globalmem=65536 impl_kern_boundary_sync=false n_wf=8 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null separate_acquire_release=false timing=true translation=false @@ -413,6 +460,7 @@ coalescer_to_vrf_bus_width=32 countPages=false cu_id=0 debugSegFault=false +default_p_state=UNDEFINED dpbypass_pipe_length=4 eventq_index=0 execPolicy=OLDEST-FIRST @@ -428,7 +476,11 @@ n_wf=8 num_SIMDs=4 num_global_mem_pipes=1 num_shared_mem_pipes=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 perLaneTLB=false +power_model=Null prefetch_depth=0 prefetch_prev_type=PF_PHASE prefetch_stride=1 @@ -448,9 +500,14 @@ translation_port=system.l1_coalescer0.slave[0] [system.cpu1.CUs0.ldsBus] type=Bridge clk_domain=system.cpu1.clk_domain +default_p_state=UNDEFINED delay=0 eventq_index=0 -ranges=0:18446744073709551615 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +ranges=0:18446744073709551615:0:0:0:0 req_size=16 resp_size=16 master=system.cpu1.CUs0.localDataStore.cuPort @@ -461,8 +518,13 @@ type=LdsState bankConflictPenalty=1 banks=32 clk_domain=system.cpu1.clk_domain +default_p_state=UNDEFINED eventq_index=0 -range=0:65535 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +range=0:65535:0:0:0:0 size=65536 cuPort=system.cpu1.CUs0.ldsBus.master @@ -472,6 +534,7 @@ eventq_index=0 min_alloc=4 num_regs_per_simd=2048 simd_id=0 +wfSize=64 [system.cpu1.CUs0.vector_register_file1] type=VectorRegisterFile @@ -479,6 +542,7 @@ eventq_index=0 min_alloc=4 num_regs_per_simd=2048 simd_id=1 +wfSize=64 [system.cpu1.CUs0.vector_register_file2] type=VectorRegisterFile @@ -486,6 +550,7 @@ eventq_index=0 min_alloc=4 num_regs_per_simd=2048 simd_id=2 +wfSize=64 [system.cpu1.CUs0.vector_register_file3] type=VectorRegisterFile @@ -493,197 +558,230 @@ eventq_index=0 min_alloc=4 num_regs_per_simd=2048 simd_id=3 +wfSize=64 [system.cpu1.CUs0.wavefronts00] type=Wavefront eventq_index=0 simdId=0 +wfSize=64 wf_slot_id=0 [system.cpu1.CUs0.wavefronts01] type=Wavefront eventq_index=0 simdId=0 +wfSize=64 wf_slot_id=1 [system.cpu1.CUs0.wavefronts02] type=Wavefront eventq_index=0 simdId=0 +wfSize=64 wf_slot_id=2 [system.cpu1.CUs0.wavefronts03] type=Wavefront eventq_index=0 simdId=0 +wfSize=64 wf_slot_id=3 [system.cpu1.CUs0.wavefronts04] type=Wavefront eventq_index=0 simdId=0 +wfSize=64 wf_slot_id=4 [system.cpu1.CUs0.wavefronts05] type=Wavefront eventq_index=0 simdId=0 +wfSize=64 wf_slot_id=5 [system.cpu1.CUs0.wavefronts06] type=Wavefront eventq_index=0 simdId=0 +wfSize=64 wf_slot_id=6 [system.cpu1.CUs0.wavefronts07] type=Wavefront eventq_index=0 simdId=0 +wfSize=64 wf_slot_id=7 [system.cpu1.CUs0.wavefronts08] type=Wavefront eventq_index=0 simdId=1 +wfSize=64 wf_slot_id=0 [system.cpu1.CUs0.wavefronts09] type=Wavefront eventq_index=0 simdId=1 +wfSize=64 wf_slot_id=1 [system.cpu1.CUs0.wavefronts10] type=Wavefront eventq_index=0 simdId=1 +wfSize=64 wf_slot_id=2 [system.cpu1.CUs0.wavefronts11] type=Wavefront eventq_index=0 simdId=1 +wfSize=64 wf_slot_id=3 [system.cpu1.CUs0.wavefronts12] type=Wavefront eventq_index=0 simdId=1 +wfSize=64 wf_slot_id=4 [system.cpu1.CUs0.wavefronts13] type=Wavefront eventq_index=0 simdId=1 +wfSize=64 wf_slot_id=5 [system.cpu1.CUs0.wavefronts14] type=Wavefront eventq_index=0 simdId=1 +wfSize=64 wf_slot_id=6 [system.cpu1.CUs0.wavefronts15] type=Wavefront eventq_index=0 simdId=1 +wfSize=64 wf_slot_id=7 [system.cpu1.CUs0.wavefronts16] type=Wavefront eventq_index=0 simdId=2 +wfSize=64 wf_slot_id=0 [system.cpu1.CUs0.wavefronts17] type=Wavefront eventq_index=0 simdId=2 +wfSize=64 wf_slot_id=1 [system.cpu1.CUs0.wavefronts18] type=Wavefront eventq_index=0 simdId=2 +wfSize=64 wf_slot_id=2 [system.cpu1.CUs0.wavefronts19] type=Wavefront eventq_index=0 simdId=2 +wfSize=64 wf_slot_id=3 [system.cpu1.CUs0.wavefronts20] type=Wavefront eventq_index=0 simdId=2 +wfSize=64 wf_slot_id=4 [system.cpu1.CUs0.wavefronts21] type=Wavefront eventq_index=0 simdId=2 +wfSize=64 wf_slot_id=5 [system.cpu1.CUs0.wavefronts22] type=Wavefront eventq_index=0 simdId=2 +wfSize=64 wf_slot_id=6 [system.cpu1.CUs0.wavefronts23] type=Wavefront eventq_index=0 simdId=2 +wfSize=64 wf_slot_id=7 [system.cpu1.CUs0.wavefronts24] type=Wavefront eventq_index=0 simdId=3 +wfSize=64 wf_slot_id=0 [system.cpu1.CUs0.wavefronts25] type=Wavefront eventq_index=0 simdId=3 +wfSize=64 wf_slot_id=1 [system.cpu1.CUs0.wavefronts26] type=Wavefront eventq_index=0 simdId=3 +wfSize=64 wf_slot_id=2 [system.cpu1.CUs0.wavefronts27] type=Wavefront eventq_index=0 simdId=3 +wfSize=64 wf_slot_id=3 [system.cpu1.CUs0.wavefronts28] type=Wavefront eventq_index=0 simdId=3 +wfSize=64 wf_slot_id=4 [system.cpu1.CUs0.wavefronts29] type=Wavefront eventq_index=0 simdId=3 +wfSize=64 wf_slot_id=5 [system.cpu1.CUs0.wavefronts30] type=Wavefront eventq_index=0 simdId=3 +wfSize=64 wf_slot_id=6 [system.cpu1.CUs0.wavefronts31] type=Wavefront eventq_index=0 simdId=3 +wfSize=64 wf_slot_id=7 [system.cpu1.CUs1] @@ -694,6 +792,7 @@ coalescer_to_vrf_bus_width=32 countPages=false cu_id=1 debugSegFault=false +default_p_state=UNDEFINED dpbypass_pipe_length=4 eventq_index=0 execPolicy=OLDEST-FIRST @@ -709,7 +808,11 @@ n_wf=8 num_SIMDs=4 num_global_mem_pipes=1 num_shared_mem_pipes=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 perLaneTLB=false +power_model=Null prefetch_depth=0 prefetch_prev_type=PF_PHASE prefetch_stride=1 @@ -729,9 +832,14 @@ translation_port=system.l1_coalescer1.slave[0] [system.cpu1.CUs1.ldsBus] type=Bridge clk_domain=system.cpu1.clk_domain +default_p_state=UNDEFINED delay=0 eventq_index=0 -ranges=0:18446744073709551615 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +ranges=0:18446744073709551615:0:0:0:0 req_size=16 resp_size=16 master=system.cpu1.CUs1.localDataStore.cuPort @@ -742,8 +850,13 @@ type=LdsState bankConflictPenalty=1 banks=32 clk_domain=system.cpu1.clk_domain +default_p_state=UNDEFINED eventq_index=0 -range=0:65535 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +range=0:65535:0:0:0:0 size=65536 cuPort=system.cpu1.CUs1.ldsBus.master @@ -753,6 +866,7 @@ eventq_index=0 min_alloc=4 num_regs_per_simd=2048 simd_id=0 +wfSize=64 [system.cpu1.CUs1.vector_register_file1] type=VectorRegisterFile @@ -760,6 +874,7 @@ eventq_index=0 min_alloc=4 num_regs_per_simd=2048 simd_id=1 +wfSize=64 [system.cpu1.CUs1.vector_register_file2] type=VectorRegisterFile @@ -767,6 +882,7 @@ eventq_index=0 min_alloc=4 num_regs_per_simd=2048 simd_id=2 +wfSize=64 [system.cpu1.CUs1.vector_register_file3] type=VectorRegisterFile @@ -774,197 +890,230 @@ eventq_index=0 min_alloc=4 num_regs_per_simd=2048 simd_id=3 +wfSize=64 [system.cpu1.CUs1.wavefronts00] type=Wavefront eventq_index=0 simdId=0 +wfSize=64 wf_slot_id=0 [system.cpu1.CUs1.wavefronts01] type=Wavefront eventq_index=0 simdId=0 +wfSize=64 wf_slot_id=1 [system.cpu1.CUs1.wavefronts02] type=Wavefront eventq_index=0 simdId=0 +wfSize=64 wf_slot_id=2 [system.cpu1.CUs1.wavefronts03] type=Wavefront eventq_index=0 simdId=0 +wfSize=64 wf_slot_id=3 [system.cpu1.CUs1.wavefronts04] type=Wavefront eventq_index=0 simdId=0 +wfSize=64 wf_slot_id=4 [system.cpu1.CUs1.wavefronts05] type=Wavefront eventq_index=0 simdId=0 +wfSize=64 wf_slot_id=5 [system.cpu1.CUs1.wavefronts06] type=Wavefront eventq_index=0 simdId=0 +wfSize=64 wf_slot_id=6 [system.cpu1.CUs1.wavefronts07] type=Wavefront eventq_index=0 simdId=0 +wfSize=64 wf_slot_id=7 [system.cpu1.CUs1.wavefronts08] type=Wavefront eventq_index=0 simdId=1 +wfSize=64 wf_slot_id=0 [system.cpu1.CUs1.wavefronts09] type=Wavefront eventq_index=0 simdId=1 +wfSize=64 wf_slot_id=1 [system.cpu1.CUs1.wavefronts10] type=Wavefront eventq_index=0 simdId=1 +wfSize=64 wf_slot_id=2 [system.cpu1.CUs1.wavefronts11] type=Wavefront eventq_index=0 simdId=1 +wfSize=64 wf_slot_id=3 [system.cpu1.CUs1.wavefronts12] type=Wavefront eventq_index=0 simdId=1 +wfSize=64 wf_slot_id=4 [system.cpu1.CUs1.wavefronts13] type=Wavefront eventq_index=0 simdId=1 +wfSize=64 wf_slot_id=5 [system.cpu1.CUs1.wavefronts14] type=Wavefront eventq_index=0 simdId=1 +wfSize=64 wf_slot_id=6 [system.cpu1.CUs1.wavefronts15] type=Wavefront eventq_index=0 simdId=1 +wfSize=64 wf_slot_id=7 [system.cpu1.CUs1.wavefronts16] type=Wavefront eventq_index=0 simdId=2 +wfSize=64 wf_slot_id=0 [system.cpu1.CUs1.wavefronts17] type=Wavefront eventq_index=0 simdId=2 +wfSize=64 wf_slot_id=1 [system.cpu1.CUs1.wavefronts18] type=Wavefront eventq_index=0 simdId=2 +wfSize=64 wf_slot_id=2 [system.cpu1.CUs1.wavefronts19] type=Wavefront eventq_index=0 simdId=2 +wfSize=64 wf_slot_id=3 [system.cpu1.CUs1.wavefronts20] type=Wavefront eventq_index=0 simdId=2 +wfSize=64 wf_slot_id=4 [system.cpu1.CUs1.wavefronts21] type=Wavefront eventq_index=0 simdId=2 +wfSize=64 wf_slot_id=5 [system.cpu1.CUs1.wavefronts22] type=Wavefront eventq_index=0 simdId=2 +wfSize=64 wf_slot_id=6 [system.cpu1.CUs1.wavefronts23] type=Wavefront eventq_index=0 simdId=2 +wfSize=64 wf_slot_id=7 [system.cpu1.CUs1.wavefronts24] type=Wavefront eventq_index=0 simdId=3 +wfSize=64 wf_slot_id=0 [system.cpu1.CUs1.wavefronts25] type=Wavefront eventq_index=0 simdId=3 +wfSize=64 wf_slot_id=1 [system.cpu1.CUs1.wavefronts26] type=Wavefront eventq_index=0 simdId=3 +wfSize=64 wf_slot_id=2 [system.cpu1.CUs1.wavefronts27] type=Wavefront eventq_index=0 simdId=3 +wfSize=64 wf_slot_id=3 [system.cpu1.CUs1.wavefronts28] type=Wavefront eventq_index=0 simdId=3 +wfSize=64 wf_slot_id=4 [system.cpu1.CUs1.wavefronts29] type=Wavefront eventq_index=0 simdId=3 +wfSize=64 wf_slot_id=5 [system.cpu1.CUs1.wavefronts30] type=Wavefront eventq_index=0 simdId=3 +wfSize=64 wf_slot_id=6 [system.cpu1.CUs1.wavefronts31] type=Wavefront eventq_index=0 simdId=3 +wfSize=64 wf_slot_id=7 [system.cpu1.clk_domain] @@ -987,9 +1136,14 @@ children=cl_driver cl_driver=system.cpu2.cl_driver clk_domain=system.clk_domain cpu=system.cpu0 +default_p_state=UNDEFINED eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=8589934592 pio_latency=1000 +power_model=Null shader_pointer=system.cpu1 system=system dma=system.piobus.slave[1] @@ -998,7 +1152,7 @@ translation_port=system.dispatcher_coalescer.slave[0] [system.cpu2.cl_driver] type=ClDriver -codefile=/home/stever/hg/m5sim.org/gem5/tests/test-progs/gpu-hello/bin/x86/linux/gpu-hello-kernel.asm +codefile=/arm/projectscratch/randd/systems/dist/test-progs/gpu-hello/bin/x86/linux/gpu-hello-kernel.asm eventq_index=0 filename=hsa @@ -1012,11 +1166,16 @@ TCC_select_num_bits=0 buffer_size=0 clk_domain=system.clk_domain cluster_id=0 +default_p_state=UNDEFINED directory=system.dir_cntrl0.directory eventq_index=0 l3_hit_latency=15 noTCCdir=false number_of_TBEs=5120 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null probeToCore=system.dir_cntrl0.probeToCore recycle_latency=10 requestFromCores=system.dir_cntrl0.requestFromCores @@ -1131,8 +1290,13 @@ type=TLBCoalescer children=clk_domain clk_domain=system.dispatcher_coalescer.clk_domain coalescingWindow=1 +default_p_state=UNDEFINED disableCoalescing=false eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null probesPerCycle=2 master=system.dispatcher_tlb.slave[0] slave=system.cpu2.translation_port @@ -1158,11 +1322,16 @@ accessDistance=false allocationPolicy=true assoc=32 clk_domain=system.dispatcher_tlb.clk_domain +default_p_state=UNDEFINED eventq_index=0 hitLatency=1 maxOutstandingReqs=64 missLatency1=5 missLatency2=750 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null size=32 master=system.l2_coalescer.slave[1] slave=system.dispatcher_coalescer.master[0] @@ -1194,8 +1363,13 @@ type=TLBCoalescer children=clk_domain clk_domain=system.l1_coalescer0.clk_domain coalescingWindow=1 +default_p_state=UNDEFINED disableCoalescing=false eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null probesPerCycle=2 master=system.l1_tlb0.slave[0] slave=system.cpu1.CUs0.translation_port[0] @@ -1219,8 +1393,13 @@ type=TLBCoalescer children=clk_domain clk_domain=system.l1_coalescer1.clk_domain coalescingWindow=1 +default_p_state=UNDEFINED disableCoalescing=false eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null probesPerCycle=2 master=system.l1_tlb1.slave[0] slave=system.cpu1.CUs1.translation_port[0] @@ -1246,11 +1425,16 @@ accessDistance=false allocationPolicy=true assoc=32 clk_domain=system.l1_tlb0.clk_domain +default_p_state=UNDEFINED eventq_index=0 hitLatency=1 maxOutstandingReqs=64 missLatency1=5 missLatency2=750 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null size=32 master=system.l2_coalescer.slave[2] slave=system.l1_coalescer0.master[0] @@ -1276,11 +1460,16 @@ accessDistance=false allocationPolicy=true assoc=32 clk_domain=system.l1_tlb1.clk_domain +default_p_state=UNDEFINED eventq_index=0 hitLatency=1 maxOutstandingReqs=64 missLatency1=5 missLatency2=750 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null size=32 master=system.l2_coalescer.slave[3] slave=system.l1_coalescer1.master[0] @@ -1304,8 +1493,13 @@ type=TLBCoalescer children=clk_domain clk_domain=system.l2_coalescer.clk_domain coalescingWindow=1 +default_p_state=UNDEFINED disableCoalescing=false eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null probesPerCycle=2 master=system.l2_tlb.slave[0] slave=system.sqc_tlb.master[0] system.dispatcher_tlb.master[0] system.l1_tlb0.master[0] system.l1_tlb1.master[0] @@ -1331,11 +1525,16 @@ accessDistance=false allocationPolicy=true assoc=32 clk_domain=system.l2_tlb.clk_domain +default_p_state=UNDEFINED eventq_index=0 hitLatency=69 maxOutstandingReqs=64 missLatency1=5 missLatency2=750 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null size=4096 master=system.l3_coalescer.slave[0] slave=system.l2_coalescer.master[0] @@ -1359,8 +1558,13 @@ type=TLBCoalescer children=clk_domain clk_domain=system.l3_coalescer.clk_domain coalescingWindow=1 +default_p_state=UNDEFINED disableCoalescing=false eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null probesPerCycle=2 master=system.l3_tlb.slave[0] slave=system.l2_tlb.master[0] @@ -1386,11 +1590,16 @@ accessDistance=false allocationPolicy=true assoc=32 clk_domain=system.l3_tlb.clk_domain +default_p_state=UNDEFINED eventq_index=0 hitLatency=150 maxOutstandingReqs=64 missLatency1=5 missLatency2=750 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null size=8192 slave=system.l3_coalescer.master[0] @@ -1410,27 +1619,27 @@ voltage=1.000000 [system.mem_ctrls] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -1442,6 +1651,7 @@ burst_length=8 channels=1 clk_domain=system.clk_domain conf_table_reported=true +default_p_state=UNDEFINED device_bus_width=8 device_rowbuffer_size=1024 device_size=536870912 @@ -1449,12 +1659,17 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=false max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 page_policy=open_adaptive -range=0:536870911 +power_model=Null +range=0:536870911:5:19:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 @@ -1476,9 +1691,9 @@ tRTW=2500 tWR=15000 tWTR=7500 tXAW=30000 -tXP=0 +tXP=6000 tXPDLL=0 -tXS=0 +tXS=270000 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 @@ -1488,9 +1703,14 @@ port=system.dir_cntrl0.memory [system.piobus] type=NoncoherentXBar clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=0 frontend_latency=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null response_latency=0 use_default_range=false width=32 @@ -1504,12 +1724,17 @@ access_backing_store=true all_instructions=false block_size_bytes=64 clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED eventq_index=0 hot_lines=false memory_size_bits=48 num_of_sequencers=5 number_of_virtual_networks=10 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 phys_mem=system.ruby.phys_mem +power_model=Null randomization=false [system.ruby.clk_domain] @@ -1522,18 +1747,23 @@ voltage_domain=system.voltage_domain [system.ruby.network] type=SimpleNetwork -children=ext_links0 ext_links1 ext_links2 ext_links3 ext_links4 ext_links5 ext_links6 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_link_buffers20 int_link_buffers21 int_link_buffers22 int_link_buffers23 int_link_buffers24 int_link_buffers25 int_link_buffers26 int_link_buffers27 int_link_buffers28 int_link_buffers29 int_link_buffers30 int_link_buffers31 int_link_buffers32 int_link_buffers33 int_link_buffers34 int_link_buffers35 int_link_buffers36 int_link_buffers37 int_link_buffers38 int_link_buffers39 int_links0 int_links1 +children=ext_links0 ext_links1 ext_links2 ext_links3 ext_links4 ext_links5 ext_links6 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_link_buffers20 int_link_buffers21 int_link_buffers22 int_link_buffers23 int_link_buffers24 int_link_buffers25 int_link_buffers26 int_link_buffers27 int_link_buffers28 int_link_buffers29 int_link_buffers30 int_link_buffers31 int_link_buffers32 int_link_buffers33 int_link_buffers34 int_link_buffers35 int_link_buffers36 int_link_buffers37 int_link_buffers38 int_link_buffers39 int_link_buffers40 int_link_buffers41 int_link_buffers42 int_link_buffers43 int_link_buffers44 int_link_buffers45 int_link_buffers46 int_link_buffers47 int_link_buffers48 int_link_buffers49 int_link_buffers50 int_link_buffers51 int_link_buffers52 int_link_buffers53 int_link_buffers54 int_link_buffers55 int_link_buffers56 int_link_buffers57 int_link_buffers58 int_link_buffers59 int_link_buffers60 int_link_buffers61 int_link_buffers62 int_link_buffers63 int_link_buffers64 int_link_buffers65 int_link_buffers66 int_link_buffers67 int_link_buffers68 int_link_buffers69 int_link_buffers70 int_link_buffers71 int_link_buffers72 int_link_buffers73 int_link_buffers74 int_link_buffers75 int_link_buffers76 int_link_buffers77 int_link_buffers78 int_link_buffers79 int_links0 int_links1 int_links2 int_links3 adaptive_routing=false buffer_size=0 clk_domain=system.ruby.clk_domain control_msg_size=8 +default_p_state=UNDEFINED endpoint_bandwidth=1000 eventq_index=0 ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1 system.ruby.network.ext_links2 system.ruby.network.ext_links3 system.ruby.network.ext_links4 system.ruby.network.ext_links5 system.ruby.network.ext_links6 -int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19 system.ruby.network.int_link_buffers20 system.ruby.network.int_link_buffers21 system.ruby.network.int_link_buffers22 system.ruby.network.int_link_buffers23 system.ruby.network.int_link_buffers24 system.ruby.network.int_link_buffers25 system.ruby.network.int_link_buffers26 system.ruby.network.int_link_buffers27 system.ruby.network.int_link_buffers28 system.ruby.network.int_link_buffers29 system.ruby.network.int_link_buffers30 system.ruby.network.int_link_buffers31 system.ruby.network.int_link_buffers32 system.ruby.network.int_link_buffers33 system.ruby.network.int_link_buffers34 system.ruby.network.int_link_buffers35 system.ruby.network.int_link_buffers36 system.ruby.network.int_link_buffers37 system.ruby.network.int_link_buffers38 system.ruby.network.int_link_buffers39 -int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 +int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19 system.ruby.network.int_link_buffers20 system.ruby.network.int_link_buffers21 system.ruby.network.int_link_buffers22 system.ruby.network.int_link_buffers23 system.ruby.network.int_link_buffers24 system.ruby.network.int_link_buffers25 system.ruby.network.int_link_buffers26 system.ruby.network.int_link_buffers27 system.ruby.network.int_link_buffers28 system.ruby.network.int_link_buffers29 system.ruby.network.int_link_buffers30 system.ruby.network.int_link_buffers31 system.ruby.network.int_link_buffers32 system.ruby.network.int_link_buffers33 system.ruby.network.int_link_buffers34 system.ruby.network.int_link_buffers35 system.ruby.network.int_link_buffers36 system.ruby.network.int_link_buffers37 system.ruby.network.int_link_buffers38 system.ruby.network.int_link_buffers39 system.ruby.network.int_link_buffers40 system.ruby.network.int_link_buffers41 system.ruby.network.int_link_buffers42 system.ruby.network.int_link_buffers43 system.ruby.network.int_link_buffers44 system.ruby.network.int_link_buffers45 system.ruby.network.int_link_buffers46 system.ruby.network.int_link_buffers47 system.ruby.network.int_link_buffers48 system.ruby.network.int_link_buffers49 system.ruby.network.int_link_buffers50 system.ruby.network.int_link_buffers51 system.ruby.network.int_link_buffers52 system.ruby.network.int_link_buffers53 system.ruby.network.int_link_buffers54 system.ruby.network.int_link_buffers55 system.ruby.network.int_link_buffers56 system.ruby.network.int_link_buffers57 system.ruby.network.int_link_buffers58 system.ruby.network.int_link_buffers59 system.ruby.network.int_link_buffers60 system.ruby.network.int_link_buffers61 system.ruby.network.int_link_buffers62 system.ruby.network.int_link_buffers63 system.ruby.network.int_link_buffers64 system.ruby.network.int_link_buffers65 system.ruby.network.int_link_buffers66 system.ruby.network.int_link_buffers67 system.ruby.network.int_link_buffers68 system.ruby.network.int_link_buffers69 system.ruby.network.int_link_buffers70 system.ruby.network.int_link_buffers71 system.ruby.network.int_link_buffers72 system.ruby.network.int_link_buffers73 system.ruby.network.int_link_buffers74 system.ruby.network.int_link_buffers75 system.ruby.network.int_link_buffers76 system.ruby.network.int_link_buffers77 system.ruby.network.int_link_buffers78 system.ruby.network.int_link_buffers79 +int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2 system.ruby.network.int_links3 netifs= number_of_virtual_networks=10 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null routers=system.ruby.network.ext_links0.int_node system.ruby.network.ext_links1.int_node system.ruby.network.ext_links2.int_node ruby_system=system.ruby topology=Crossbar @@ -1555,8 +1785,14 @@ weight=1 type=Switch children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17 port_buffers18 port_buffers19 port_buffers20 port_buffers21 port_buffers22 port_buffers23 port_buffers24 port_buffers25 port_buffers26 port_buffers27 port_buffers28 port_buffers29 port_buffers30 port_buffers31 port_buffers32 port_buffers33 port_buffers34 port_buffers35 port_buffers36 port_buffers37 port_buffers38 port_buffers39 port_buffers40 port_buffers41 port_buffers42 port_buffers43 port_buffers44 port_buffers45 port_buffers46 port_buffers47 port_buffers48 port_buffers49 port_buffers50 port_buffers51 port_buffers52 port_buffers53 port_buffers54 port_buffers55 port_buffers56 port_buffers57 port_buffers58 port_buffers59 port_buffers60 port_buffers61 port_buffers62 port_buffers63 port_buffers64 port_buffers65 port_buffers66 port_buffers67 port_buffers68 port_buffers69 port_buffers70 port_buffers71 port_buffers72 port_buffers73 port_buffers74 port_buffers75 port_buffers76 port_buffers77 port_buffers78 port_buffers79 port_buffers80 port_buffers81 port_buffers82 port_buffers83 port_buffers84 port_buffers85 port_buffers86 port_buffers87 port_buffers88 port_buffers89 clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED eventq_index=0 +latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 port_buffers=system.ruby.network.ext_links0.int_node.port_buffers00 system.ruby.network.ext_links0.int_node.port_buffers01 system.ruby.network.ext_links0.int_node.port_buffers02 system.ruby.network.ext_links0.int_node.port_buffers03 system.ruby.network.ext_links0.int_node.port_buffers04 system.ruby.network.ext_links0.int_node.port_buffers05 system.ruby.network.ext_links0.int_node.port_buffers06 system.ruby.network.ext_links0.int_node.port_buffers07 system.ruby.network.ext_links0.int_node.port_buffers08 system.ruby.network.ext_links0.int_node.port_buffers09 system.ruby.network.ext_links0.int_node.port_buffers10 system.ruby.network.ext_links0.int_node.port_buffers11 system.ruby.network.ext_links0.int_node.port_buffers12 system.ruby.network.ext_links0.int_node.port_buffers13 system.ruby.network.ext_links0.int_node.port_buffers14 system.ruby.network.ext_links0.int_node.port_buffers15 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system.ruby.network.ext_links0.int_node.port_buffers88 system.ruby.network.ext_links0.int_node.port_buffers89 +power_model=Null router_id=0 virt_nets=10 @@ -2205,8 +2441,14 @@ weight=1 type=Switch children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17 port_buffers18 port_buffers19 port_buffers20 port_buffers21 port_buffers22 port_buffers23 port_buffers24 port_buffers25 port_buffers26 port_buffers27 port_buffers28 port_buffers29 port_buffers30 port_buffers31 port_buffers32 port_buffers33 port_buffers34 port_buffers35 port_buffers36 port_buffers37 port_buffers38 port_buffers39 port_buffers40 port_buffers41 port_buffers42 port_buffers43 port_buffers44 port_buffers45 port_buffers46 port_buffers47 port_buffers48 port_buffers49 port_buffers50 port_buffers51 port_buffers52 port_buffers53 port_buffers54 port_buffers55 port_buffers56 port_buffers57 port_buffers58 port_buffers59 port_buffers60 port_buffers61 port_buffers62 port_buffers63 port_buffers64 port_buffers65 port_buffers66 port_buffers67 port_buffers68 port_buffers69 port_buffers70 port_buffers71 port_buffers72 port_buffers73 port_buffers74 port_buffers75 port_buffers76 port_buffers77 port_buffers78 port_buffers79 clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED eventq_index=0 +latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 port_buffers=system.ruby.network.ext_links1.int_node.port_buffers00 system.ruby.network.ext_links1.int_node.port_buffers01 system.ruby.network.ext_links1.int_node.port_buffers02 system.ruby.network.ext_links1.int_node.port_buffers03 system.ruby.network.ext_links1.int_node.port_buffers04 system.ruby.network.ext_links1.int_node.port_buffers05 system.ruby.network.ext_links1.int_node.port_buffers06 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system.ruby.network.ext_links1.int_node.port_buffers79 +power_model=Null router_id=1 virt_nets=10 @@ -2785,8 +3027,14 @@ weight=1 type=Switch children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17 port_buffers18 port_buffers19 port_buffers20 port_buffers21 port_buffers22 port_buffers23 port_buffers24 port_buffers25 port_buffers26 port_buffers27 port_buffers28 port_buffers29 port_buffers30 port_buffers31 port_buffers32 port_buffers33 port_buffers34 port_buffers35 port_buffers36 port_buffers37 port_buffers38 port_buffers39 port_buffers40 port_buffers41 port_buffers42 port_buffers43 port_buffers44 port_buffers45 port_buffers46 port_buffers47 port_buffers48 port_buffers49 port_buffers50 port_buffers51 port_buffers52 port_buffers53 port_buffers54 port_buffers55 port_buffers56 port_buffers57 port_buffers58 port_buffers59 port_buffers60 port_buffers61 port_buffers62 port_buffers63 port_buffers64 port_buffers65 port_buffers66 port_buffers67 port_buffers68 port_buffers69 port_buffers70 port_buffers71 port_buffers72 port_buffers73 port_buffers74 port_buffers75 port_buffers76 port_buffers77 port_buffers78 port_buffers79 clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED eventq_index=0 +latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 port_buffers=system.ruby.network.ext_links2.int_node.port_buffers00 system.ruby.network.ext_links2.int_node.port_buffers01 system.ruby.network.ext_links2.int_node.port_buffers02 system.ruby.network.ext_links2.int_node.port_buffers03 system.ruby.network.ext_links2.int_node.port_buffers04 system.ruby.network.ext_links2.int_node.port_buffers05 system.ruby.network.ext_links2.int_node.port_buffers06 system.ruby.network.ext_links2.int_node.port_buffers07 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+power_model=Null router_id=2 virt_nets=10 @@ -3670,24 +3918,332 @@ eventq_index=0 ordered=true randomization=false +[system.ruby.network.int_link_buffers40] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers41] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers42] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers43] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers44] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers45] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers46] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers47] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers48] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers49] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers50] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers51] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers52] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers53] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers54] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers55] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers56] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers57] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers58] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers59] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers60] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers61] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers62] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers63] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers64] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers65] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers66] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers67] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers68] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers69] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers70] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers71] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers72] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers73] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers74] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers75] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers76] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers77] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers78] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers79] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + [system.ruby.network.int_links0] type=SimpleIntLink bandwidth_factor=512 +dst_inport= +dst_node=system.ruby.network.ext_links1.int_node eventq_index=0 latency=1 link_id=0 -node_a=system.ruby.network.ext_links0.int_node -node_b=system.ruby.network.ext_links1.int_node +src_node=system.ruby.network.ext_links0.int_node +src_outport= weight=1 [system.ruby.network.int_links1] type=SimpleIntLink bandwidth_factor=512 +dst_inport= +dst_node=system.ruby.network.ext_links0.int_node eventq_index=0 latency=1 link_id=1 -node_a=system.ruby.network.ext_links0.int_node -node_b=system.ruby.network.ext_links2.int_node +src_node=system.ruby.network.ext_links1.int_node +src_outport= +weight=1 + +[system.ruby.network.int_links2] +type=SimpleIntLink +bandwidth_factor=512 +dst_inport= +dst_node=system.ruby.network.ext_links2.int_node +eventq_index=0 +latency=1 +link_id=2 +src_node=system.ruby.network.ext_links0.int_node +src_outport= +weight=1 + +[system.ruby.network.int_links3] +type=SimpleIntLink +bandwidth_factor=512 +dst_inport= +dst_node=system.ruby.network.ext_links0.int_node +eventq_index=0 +latency=1 +link_id=3 +src_node=system.ruby.network.ext_links2.int_node +src_outport= weight=1 [system.ruby.phys_mem] @@ -3695,12 +4251,18 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.ruby.clk_domain conf_table_reported=true +default_p_state=UNDEFINED eventq_index=0 in_addr_map=false +kvm_map=true latency=30000 latency_var=0 null=false -range=0:536870911 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +range=0:536870911:0:0:0:0 [system.sqc_cntrl0] type=SQC_Controller @@ -3710,11 +4272,16 @@ TCC_select_num_bits=0 buffer_size=0 clk_domain=system.clk_domain cluster_id=0 +default_p_state=UNDEFINED eventq_index=0 issue_latency=80 l2_hit_latency=18 mandatoryQueue=system.sqc_cntrl0.mandatoryQueue number_of_TBEs=256 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null probeToSQC=system.sqc_cntrl0.probeToSQC recycle_latency=10 requestFromSQC=system.sqc_cntrl0.requestFromSQC @@ -3797,17 +4364,22 @@ coreid=99 dcache=system.sqc_cntrl0.L1cache dcache_hit_latency=1 deadlock_threshold=500000 +default_p_state=UNDEFINED eventq_index=0 +garnet_standalone=false icache=system.sqc_cntrl0.L1cache icache_hit_latency=1 is_cpu_sequencer=false max_outstanding_requests=16 no_retry_on_stall=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null ruby_system=system.ruby support_data_reqs=false support_inst_reqs=true system=system -using_network_tester=false using_ruby_tester=false version=6 slave=system.cpu1.CUs0.sqc_port system.cpu1.CUs1.sqc_port @@ -3825,8 +4397,13 @@ type=TLBCoalescer children=clk_domain clk_domain=system.sqc_coalescer.clk_domain coalescingWindow=1 +default_p_state=UNDEFINED disableCoalescing=false eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null probesPerCycle=2 master=system.sqc_tlb.slave[0] slave=system.cpu1.CUs0.sqc_tlb_port system.cpu1.CUs1.sqc_tlb_port @@ -3852,11 +4429,16 @@ accessDistance=false allocationPolicy=true assoc=32 clk_domain=system.sqc_tlb.clk_domain +default_p_state=UNDEFINED eventq_index=0 hitLatency=1 maxOutstandingReqs=64 missLatency1=5 missLatency2=750 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null size=32 master=system.l2_coalescer.slave[0] slave=system.sqc_coalescer.master[0] @@ -3878,9 +4460,14 @@ voltage=1.000000 [system.sys_port_proxy] type=RubyPortProxy clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 is_cpu_sequencer=true no_retry_on_stall=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null ruby_system=system.ruby support_data_reqs=true support_inst_reqs=true @@ -3897,10 +4484,15 @@ TCC_select_num_bits=0 buffer_size=0 clk_domain=system.clk_domain cluster_id=0 +default_p_state=UNDEFINED eventq_index=0 l2_request_latency=1 l2_response_latency=16 number_of_TBEs=2048 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null recycle_latency=10 responseFromTCC=system.tcc_cntrl0.responseFromTCC responseToTCC=system.tcc_cntrl0.responseToTCC @@ -3992,11 +4584,16 @@ TCC_select_num_bits=0 buffer_size=0 clk_domain=system.clk_domain cluster_id=0 +default_p_state=UNDEFINED directory=system.tccdir_cntrl0.directory directory_latency=6 eventq_index=0 issue_latency=120 number_of_TBEs=1024 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null probeFromNB=system.tccdir_cntrl0.probeFromNB probeToCore=system.tccdir_cntrl0.probeToCore recycle_latency=10 @@ -4141,11 +4738,16 @@ buffer_size=0 clk_domain=system.clk_domain cluster_id=0 coalescer=system.tcp_cntrl0.coalescer +default_p_state=UNDEFINED eventq_index=0 issue_latency=40 l2_hit_latency=18 mandatoryQueue=system.tcp_cntrl0.mandatoryQueue number_of_TBEs=2560 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null probeToTCP=system.tcp_cntrl0.probeToTCP recycle_latency=10 requestFromTCP=system.tcp_cntrl0.requestFromTCP @@ -4191,17 +4793,22 @@ coreid=99 dcache=system.tcp_cntrl0.L1cache dcache_hit_latency=1 deadlock_threshold=500000 +default_p_state=UNDEFINED eventq_index=0 +garnet_standalone=false icache=system.tcp_cntrl0.L1cache icache_hit_latency=1 is_cpu_sequencer=false max_outstanding_requests=2048 no_retry_on_stall=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null ruby_system=system.ruby support_data_reqs=true support_inst_reqs=false system=system -using_network_tester=false using_ruby_tester=false version=2 slave=system.cpu1.CUs0.memory_port[0] system.cpu1.CUs0.memory_port[1] system.cpu1.CUs0.memory_port[2] system.cpu1.CUs0.memory_port[3] system.cpu1.CUs0.memory_port[4] system.cpu1.CUs0.memory_port[5] system.cpu1.CUs0.memory_port[6] system.cpu1.CUs0.memory_port[7] system.cpu1.CUs0.memory_port[8] system.cpu1.CUs0.memory_port[9] system.cpu1.CUs0.memory_port[10] system.cpu1.CUs0.memory_port[11] system.cpu1.CUs0.memory_port[12] system.cpu1.CUs0.memory_port[13] system.cpu1.CUs0.memory_port[14] system.cpu1.CUs0.memory_port[15] system.cpu1.CUs0.memory_port[16] system.cpu1.CUs0.memory_port[17] system.cpu1.CUs0.memory_port[18] system.cpu1.CUs0.memory_port[19] system.cpu1.CUs0.memory_port[20] system.cpu1.CUs0.memory_port[21] system.cpu1.CUs0.memory_port[22] system.cpu1.CUs0.memory_port[23] system.cpu1.CUs0.memory_port[24] system.cpu1.CUs0.memory_port[25] system.cpu1.CUs0.memory_port[26] system.cpu1.CUs0.memory_port[27] system.cpu1.CUs0.memory_port[28] system.cpu1.CUs0.memory_port[29] system.cpu1.CUs0.memory_port[30] system.cpu1.CUs0.memory_port[31] system.cpu1.CUs0.memory_port[32] system.cpu1.CUs0.memory_port[33] system.cpu1.CUs0.memory_port[34] system.cpu1.CUs0.memory_port[35] system.cpu1.CUs0.memory_port[36] system.cpu1.CUs0.memory_port[37] system.cpu1.CUs0.memory_port[38] system.cpu1.CUs0.memory_port[39] system.cpu1.CUs0.memory_port[40] system.cpu1.CUs0.memory_port[41] system.cpu1.CUs0.memory_port[42] system.cpu1.CUs0.memory_port[43] system.cpu1.CUs0.memory_port[44] system.cpu1.CUs0.memory_port[45] system.cpu1.CUs0.memory_port[46] system.cpu1.CUs0.memory_port[47] system.cpu1.CUs0.memory_port[48] system.cpu1.CUs0.memory_port[49] system.cpu1.CUs0.memory_port[50] system.cpu1.CUs0.memory_port[51] system.cpu1.CUs0.memory_port[52] system.cpu1.CUs0.memory_port[53] system.cpu1.CUs0.memory_port[54] system.cpu1.CUs0.memory_port[55] system.cpu1.CUs0.memory_port[56] system.cpu1.CUs0.memory_port[57] system.cpu1.CUs0.memory_port[58] system.cpu1.CUs0.memory_port[59] system.cpu1.CUs0.memory_port[60] system.cpu1.CUs0.memory_port[61] system.cpu1.CUs0.memory_port[62] system.cpu1.CUs0.memory_port[63] @@ -4252,17 +4859,22 @@ coreid=99 dcache=system.tcp_cntrl0.L1cache dcache_hit_latency=1 deadlock_threshold=500000 +default_p_state=UNDEFINED eventq_index=0 +garnet_standalone=false icache=system.tcp_cntrl0.L1cache icache_hit_latency=1 is_cpu_sequencer=true max_outstanding_requests=16 no_retry_on_stall=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null ruby_system=system.ruby support_data_reqs=true support_inst_reqs=true system=system -using_network_tester=false using_ruby_tester=false version=3 @@ -4283,11 +4895,16 @@ buffer_size=0 clk_domain=system.clk_domain cluster_id=0 coalescer=system.tcp_cntrl1.coalescer +default_p_state=UNDEFINED eventq_index=0 issue_latency=40 l2_hit_latency=18 mandatoryQueue=system.tcp_cntrl1.mandatoryQueue number_of_TBEs=2560 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null probeToTCP=system.tcp_cntrl1.probeToTCP recycle_latency=10 requestFromTCP=system.tcp_cntrl1.requestFromTCP @@ -4333,17 +4950,22 @@ coreid=99 dcache=system.tcp_cntrl1.L1cache dcache_hit_latency=1 deadlock_threshold=500000 +default_p_state=UNDEFINED eventq_index=0 +garnet_standalone=false icache=system.tcp_cntrl1.L1cache icache_hit_latency=1 is_cpu_sequencer=false max_outstanding_requests=2048 no_retry_on_stall=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null ruby_system=system.ruby support_data_reqs=true support_inst_reqs=false system=system -using_network_tester=false using_ruby_tester=false version=4 slave=system.cpu1.CUs1.memory_port[0] system.cpu1.CUs1.memory_port[1] system.cpu1.CUs1.memory_port[2] system.cpu1.CUs1.memory_port[3] system.cpu1.CUs1.memory_port[4] system.cpu1.CUs1.memory_port[5] system.cpu1.CUs1.memory_port[6] system.cpu1.CUs1.memory_port[7] system.cpu1.CUs1.memory_port[8] system.cpu1.CUs1.memory_port[9] system.cpu1.CUs1.memory_port[10] system.cpu1.CUs1.memory_port[11] system.cpu1.CUs1.memory_port[12] system.cpu1.CUs1.memory_port[13] system.cpu1.CUs1.memory_port[14] system.cpu1.CUs1.memory_port[15] system.cpu1.CUs1.memory_port[16] system.cpu1.CUs1.memory_port[17] system.cpu1.CUs1.memory_port[18] system.cpu1.CUs1.memory_port[19] system.cpu1.CUs1.memory_port[20] system.cpu1.CUs1.memory_port[21] system.cpu1.CUs1.memory_port[22] system.cpu1.CUs1.memory_port[23] system.cpu1.CUs1.memory_port[24] system.cpu1.CUs1.memory_port[25] system.cpu1.CUs1.memory_port[26] system.cpu1.CUs1.memory_port[27] system.cpu1.CUs1.memory_port[28] system.cpu1.CUs1.memory_port[29] system.cpu1.CUs1.memory_port[30] system.cpu1.CUs1.memory_port[31] system.cpu1.CUs1.memory_port[32] system.cpu1.CUs1.memory_port[33] system.cpu1.CUs1.memory_port[34] system.cpu1.CUs1.memory_port[35] system.cpu1.CUs1.memory_port[36] system.cpu1.CUs1.memory_port[37] system.cpu1.CUs1.memory_port[38] system.cpu1.CUs1.memory_port[39] system.cpu1.CUs1.memory_port[40] system.cpu1.CUs1.memory_port[41] system.cpu1.CUs1.memory_port[42] system.cpu1.CUs1.memory_port[43] system.cpu1.CUs1.memory_port[44] system.cpu1.CUs1.memory_port[45] system.cpu1.CUs1.memory_port[46] system.cpu1.CUs1.memory_port[47] system.cpu1.CUs1.memory_port[48] system.cpu1.CUs1.memory_port[49] system.cpu1.CUs1.memory_port[50] system.cpu1.CUs1.memory_port[51] system.cpu1.CUs1.memory_port[52] system.cpu1.CUs1.memory_port[53] system.cpu1.CUs1.memory_port[54] system.cpu1.CUs1.memory_port[55] system.cpu1.CUs1.memory_port[56] system.cpu1.CUs1.memory_port[57] system.cpu1.CUs1.memory_port[58] system.cpu1.CUs1.memory_port[59] system.cpu1.CUs1.memory_port[60] system.cpu1.CUs1.memory_port[61] system.cpu1.CUs1.memory_port[62] system.cpu1.CUs1.memory_port[63] @@ -4394,17 +5016,22 @@ coreid=99 dcache=system.tcp_cntrl1.L1cache dcache_hit_latency=1 deadlock_threshold=500000 +default_p_state=UNDEFINED eventq_index=0 +garnet_standalone=false icache=system.tcp_cntrl1.L1cache icache_hit_latency=1 is_cpu_sequencer=true max_outstanding_requests=16 no_retry_on_stall=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null ruby_system=system.ruby support_data_reqs=true support_inst_reqs=true system=system -using_network_tester=false using_ruby_tester=false version=5 diff --git a/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_RfO/simerr b/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_RfO/simerr index 1e2b8911e..4afc5c233 100755 --- a/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_RfO/simerr +++ b/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_RfO/simerr @@ -2,4 +2,5 @@ warn: system.ruby.network adopting orphan SimObject param 'int_links' warn: system.ruby.network adopting orphan SimObject param 'ext_links' warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (512 Mbytes) warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files! diff --git a/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_RfO/simout b/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_RfO/simout index 62281f3ae..c30fce800 100755 --- a/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_RfO/simout +++ b/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_RfO/simout @@ -1,12 +1,14 @@ +Redirecting stdout to build/HSAIL_X86/tests/opt/quick/se/04.gpu/x86/linux/gpu-ruby-GPU_RfO/simout +Redirecting stderr to build/HSAIL_X86/tests/opt/quick/se/04.gpu/x86/linux/gpu-ruby-GPU_RfO/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 10 2016 12:22:56 -gem5 started Mar 10 2016 12:23:20 -gem5 executing on phenom, pid 9635 -command line: build/HSAIL_X86/gem5.opt -d build/HSAIL_X86/tests/opt/quick/se/04.gpu/x86/linux/gpu-ruby-GPU_RfO -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/HSAIL_X86/tests/opt/quick/se/04.gpu/x86/linux/gpu-ruby-GPU_RfO +gem5 compiled Oct 13 2016 21:24:38 +gem5 started Oct 13 2016 21:24:54 +gem5 executing on e108600-lin, pid 29892 +command line: /work/curdun01/gem5-external.hg/build/HSAIL_X86/gem5.opt -d build/HSAIL_X86/tests/opt/quick/se/04.gpu/x86/linux/gpu-ruby-GPU_RfO -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/04.gpu/x86/linux/gpu-ruby-GPU_RfO -Using GPU kernel code file(s) /home/stever/hg/m5sim.org/gem5/tests/test-progs/gpu-hello/bin/x86/linux/gpu-hello-kernel.asm +Using GPU kernel code file(s) /arm/projectscratch/randd/systems/dist/test-progs/gpu-hello/bin/x86/linux/gpu-hello-kernel.asm Global frequency set at 1000000000000 ticks per second Forcing maxCoalescedReqs to 32 (TLB assoc.) Forcing maxCoalescedReqs to 32 (TLB assoc.) @@ -18,4 +20,4 @@ info: Entering event queue @ 0. Starting simulation... keys = 0x7b2bc0, &keys = 0x798998, keys[0] = 23 the gpu says: elloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloe -Exiting @ tick 663454500 because target called exit() +Exiting @ tick 668137500 because target called exit() diff --git a/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_RfO/stats.txt b/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_RfO/stats.txt index bde6c8cac..be5cb8048 100644 --- a/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_RfO/stats.txt +++ b/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_RfO/stats.txt @@ -1,27 +1,27 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000663 # Number of seconds simulated -sim_ticks 663454500 # Number of ticks simulated -final_tick 663454500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000668 # Number of seconds simulated +sim_ticks 668137500 # Number of ticks simulated +final_tick 668137500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 237471 # Simulator instruction rate (inst/s) -host_op_rate 488329 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2352682974 # Simulator tick rate (ticks/s) -host_mem_usage 1358064 # Number of bytes of host memory used -host_seconds 0.28 # Real time elapsed on the host +host_inst_rate 112893 # Simulator instruction rate (inst/s) +host_op_rate 232149 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1126339333 # Simulator tick rate (ticks/s) +host_mem_usage 1312868 # Number of bytes of host memory used +host_seconds 0.59 # Real time elapsed on the host sim_insts 66963 # Number of instructions simulated sim_ops 137705 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states +system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states system.mem_ctrls.bytes_read::dir_cntrl0 99264 # Number of bytes read from this memory system.mem_ctrls.bytes_read::total 99264 # Number of bytes read from this memory system.mem_ctrls.num_reads::dir_cntrl0 1551 # Number of read requests responded to by this memory system.mem_ctrls.num_reads::total 1551 # Number of read requests responded to by this memory -system.mem_ctrls.bw_read::dir_cntrl0 149616892 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_read::total 149616892 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_total::dir_cntrl0 149616892 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.bw_total::total 149616892 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_read::dir_cntrl0 148568221 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 148568221 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::dir_cntrl0 148568221 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 148568221 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrls.readReqs 1551 # Number of read requests accepted system.mem_ctrls.writeReqs 0 # Number of write requests accepted system.mem_ctrls.readBursts 1551 # Number of DRAM read bursts, including those serviced by the write queue @@ -68,7 +68,7 @@ system.mem_ctrls.perBankWrBursts::14 0 # Pe system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrls.totGap 663221000 # Total gap between requests +system.mem_ctrls.totGap 667904000 # Total gap between requests system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) @@ -87,10 +87,10 @@ system.mem_ctrls.rdQLenPdf::0 1542 # Wh system.mem_ctrls.rdQLenPdf::1 2 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::2 1 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::3 1 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::4 2 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::5 2 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::6 1 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::4 1 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::6 2 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::7 1 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see @@ -179,33 +179,33 @@ system.mem_ctrls.wrQLenPdf::60 0 # Wh system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrls.bytesPerActivate::samples 485 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::mean 204.008247 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::gmean 145.772769 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::stdev 192.306659 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::0-127 178 36.70% 36.70% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::128-255 156 32.16% 68.87% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::256-383 70 14.43% 83.30% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::384-511 40 8.25% 91.55% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::512-639 15 3.09% 94.64% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::640-767 10 2.06% 96.70% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::768-895 9 1.86% 98.56% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::samples 484 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 203.636364 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 145.087483 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 194.740960 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 177 36.57% 36.57% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 167 34.50% 71.07% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 64 13.22% 84.30% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 29 5.99% 90.29% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 20 4.13% 94.42% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 10 2.07% 96.49% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 10 2.07% 98.55% # Bytes accessed per row activation system.mem_ctrls.bytesPerActivate::896-1023 2 0.41% 98.97% # Bytes accessed per row activation system.mem_ctrls.bytesPerActivate::1024-1151 5 1.03% 100.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::total 485 # Bytes accessed per row activation -system.mem_ctrls.totQLat 15500495 # Total ticks spent queuing -system.mem_ctrls.totMemAccLat 44581745 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.bytesPerActivate::total 484 # Bytes accessed per row activation +system.mem_ctrls.totQLat 31097995 # Total ticks spent queuing +system.mem_ctrls.totMemAccLat 60179245 # Total ticks spent from burst creation until serviced by the DRAM system.mem_ctrls.totBusLat 7755000 # Total ticks spent in databus transfers -system.mem_ctrls.avgQLat 9993.87 # Average queueing delay per DRAM burst +system.mem_ctrls.avgQLat 20050.29 # Average queueing delay per DRAM burst system.mem_ctrls.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.mem_ctrls.avgMemAccLat 28743.87 # Average memory access latency per DRAM burst -system.mem_ctrls.avgRdBW 149.62 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgMemAccLat 38800.29 # Average memory access latency per DRAM burst +system.mem_ctrls.avgRdBW 148.57 # Average DRAM read bandwidth in MiByte/s system.mem_ctrls.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.mem_ctrls.avgRdBWSys 149.62 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 148.57 # Average system read bandwidth in MiByte/s system.mem_ctrls.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrls.busUtil 1.17 # Data bus utilization in percentage -system.mem_ctrls.busUtilRead 1.17 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtil 1.16 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 1.16 # Data bus utilization in percentage for reads system.mem_ctrls.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing system.mem_ctrls.avgWrQLen 0.00 # Average write queue length when enqueuing @@ -213,38 +213,48 @@ system.mem_ctrls.readRowHits 1062 # Nu system.mem_ctrls.writeRowHits 0 # Number of row buffer hits during writes system.mem_ctrls.readRowHitRate 68.47 # Row buffer hit rate for reads system.mem_ctrls.writeRowHitRate nan # Row buffer hit rate for writes -system.mem_ctrls.avgGap 427608.64 # Average gap between requests +system.mem_ctrls.avgGap 430627.98 # Average gap between requests system.mem_ctrls.pageHitRate 68.47 # Row buffer hit rate, read and write combined -system.mem_ctrls_0.actEnergy 1391040 # Energy for activate commands per rank (pJ) -system.mem_ctrls_0.preEnergy 759000 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_0.readEnergy 5335200 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.actEnergy 1320900 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 694485 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 4890900 # Energy for read commands per rank (pJ) system.mem_ctrls_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.mem_ctrls_0.refreshEnergy 43227600 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_0.actBackEnergy 335485755 # Energy for active background per rank (pJ) -system.mem_ctrls_0.preBackEnergy 102969000 # Energy for precharge background per rank (pJ) -system.mem_ctrls_0.totalEnergy 489167595 # Total energy per rank (pJ) -system.mem_ctrls_0.averagePower 738.822020 # Core power per rank (mW) -system.mem_ctrls_0.memoryStateTime::IDLE 170399250 # Time in different power states -system.mem_ctrls_0.memoryStateTime::REF 22100000 # Time in different power states -system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT 470741750 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrls_1.actEnergy 2275560 # Energy for activate commands per rank (pJ) -system.mem_ctrls_1.preEnergy 1241625 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_1.readEnergy 6723600 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.refreshEnergy 51629760.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 18618480 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 1670400 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.actPowerDownEnergy 210199470 # Energy for active power-down per rank (pJ) +system.mem_ctrls_0.prePowerDownEnergy 42511680 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls_0.selfRefreshEnergy 15622140 # Energy for self refresh per rank (pJ) +system.mem_ctrls_0.totalEnergy 347158215 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 519.590975 # Core power per rank (mW) +system.mem_ctrls_0.totalIdleTime 622801252 # Total Idle time Per DRAM Rank +system.mem_ctrls_0.memoryStateTime::IDLE 2030000 # Time in different power states +system.mem_ctrls_0.memoryStateTime::REF 21876000 # Time in different power states +system.mem_ctrls_0.memoryStateTime::SREF 51287000 # Time in different power states +system.mem_ctrls_0.memoryStateTime::PRE_PDN 110705750 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 21255248 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT_PDN 460983502 # Time in different power states +system.mem_ctrls_1.actEnergy 2170560 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 1142295 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 6183240 # Energy for read commands per rank (pJ) system.mem_ctrls_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.mem_ctrls_1.refreshEnergy 43227600 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_1.actBackEnergy 371983995 # Energy for active background per rank (pJ) -system.mem_ctrls_1.preBackEnergy 70953000 # Energy for precharge background per rank (pJ) -system.mem_ctrls_1.totalEnergy 496405380 # Total energy per rank (pJ) -system.mem_ctrls_1.averagePower 749.753724 # Core power per rank (mW) -system.mem_ctrls_1.memoryStateTime::IDLE 115859750 # Time in different power states -system.mem_ctrls_1.memoryStateTime::REF 22100000 # Time in different power states -system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT 524145250 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls_1.refreshEnergy 52244400.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 21589320 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 1299360 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.actPowerDownEnergy 243172830 # Energy for active power-down per rank (pJ) +system.mem_ctrls_1.prePowerDownEnergy 28283040 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls_1.selfRefreshEnergy 3067740 # Energy for self refresh per rank (pJ) +system.mem_ctrls_1.totalEnergy 359152785 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 537.543223 # Core power per rank (mW) +system.mem_ctrls_1.totalIdleTime 616852750 # Total Idle time Per DRAM Rank +system.mem_ctrls_1.memoryStateTime::IDLE 980000 # Time in different power states +system.mem_ctrls_1.memoryStateTime::REF 22106000 # Time in different power states +system.mem_ctrls_1.memoryStateTime::SREF 10481250 # Time in different power states +system.mem_ctrls_1.memoryStateTime::PRE_PDN 73643500 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 27629000 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT_PDN 533297750 # Time in different power states system.ruby.clk_domain.clock 500 # Clock period in ticks -system.ruby.phys_mem.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states +system.ruby.phys_mem.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states system.ruby.phys_mem.bytes_read::cpu0.inst 696760 # Number of bytes read from this memory system.ruby.phys_mem.bytes_read::cpu0.data 119832 # Number of bytes read from this memory system.ruby.phys_mem.bytes_read::cpu1.CUs0.ComputeUnit 3280 # Number of bytes read from this memory @@ -267,26 +277,26 @@ system.ruby.phys_mem.num_writes::cpu0.data 10422 # system.ruby.phys_mem.num_writes::cpu1.CUs0.ComputeUnit 256 # Number of write requests responded to by this memory system.ruby.phys_mem.num_writes::cpu1.CUs1.ComputeUnit 256 # Number of write requests responded to by this memory system.ruby.phys_mem.num_writes::total 10934 # Number of write requests responded to by this memory -system.ruby.phys_mem.bw_read::cpu0.inst 1050200127 # Total read bandwidth from this memory (bytes/s) -system.ruby.phys_mem.bw_read::cpu0.data 180618264 # Total read bandwidth from this memory (bytes/s) -system.ruby.phys_mem.bw_read::cpu1.CUs0.ComputeUnit 4943821 # Total read bandwidth from this memory (bytes/s) -system.ruby.phys_mem.bw_read::cpu1.CUs1.ComputeUnit 4943821 # Total read bandwidth from this memory (bytes/s) -system.ruby.phys_mem.bw_read::total 1240706032 # Total read bandwidth from this memory (bytes/s) -system.ruby.phys_mem.bw_inst_read::cpu0.inst 1050200127 # Instruction read bandwidth from this memory (bytes/s) -system.ruby.phys_mem.bw_inst_read::cpu1.CUs0.ComputeUnit 3014525 # Instruction read bandwidth from this memory (bytes/s) -system.ruby.phys_mem.bw_inst_read::cpu1.CUs1.ComputeUnit 3014525 # Instruction read bandwidth from this memory (bytes/s) -system.ruby.phys_mem.bw_inst_read::total 1056229176 # Instruction read bandwidth from this memory (bytes/s) -system.ruby.phys_mem.bw_write::cpu0.data 109678961 # Write bandwidth from this memory (bytes/s) -system.ruby.phys_mem.bw_write::cpu1.CUs0.ComputeUnit 385859 # Write bandwidth from this memory (bytes/s) -system.ruby.phys_mem.bw_write::cpu1.CUs1.ComputeUnit 385859 # Write bandwidth from this memory (bytes/s) -system.ruby.phys_mem.bw_write::total 110450679 # Write bandwidth from this memory (bytes/s) -system.ruby.phys_mem.bw_total::cpu0.inst 1050200127 # Total bandwidth to/from this memory (bytes/s) -system.ruby.phys_mem.bw_total::cpu0.data 290297225 # Total bandwidth to/from this memory (bytes/s) -system.ruby.phys_mem.bw_total::cpu1.CUs0.ComputeUnit 5329680 # Total bandwidth to/from this memory (bytes/s) -system.ruby.phys_mem.bw_total::cpu1.CUs1.ComputeUnit 5329680 # Total bandwidth to/from this memory (bytes/s) -system.ruby.phys_mem.bw_total::total 1351156711 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states -system.ruby.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states +system.ruby.phys_mem.bw_read::cpu0.inst 1042839236 # Total read bandwidth from this memory (bytes/s) +system.ruby.phys_mem.bw_read::cpu0.data 179352304 # Total read bandwidth from this memory (bytes/s) +system.ruby.phys_mem.bw_read::cpu1.CUs0.ComputeUnit 4909169 # Total read bandwidth from this memory (bytes/s) +system.ruby.phys_mem.bw_read::cpu1.CUs1.ComputeUnit 4909169 # Total read bandwidth from this memory (bytes/s) +system.ruby.phys_mem.bw_read::total 1232009878 # Total read bandwidth from this memory (bytes/s) +system.ruby.phys_mem.bw_inst_read::cpu0.inst 1042839236 # Instruction read bandwidth from this memory (bytes/s) +system.ruby.phys_mem.bw_inst_read::cpu1.CUs0.ComputeUnit 2993396 # Instruction read bandwidth from this memory (bytes/s) +system.ruby.phys_mem.bw_inst_read::cpu1.CUs1.ComputeUnit 2993396 # Instruction read bandwidth from this memory (bytes/s) +system.ruby.phys_mem.bw_inst_read::total 1048826028 # Instruction read bandwidth from this memory (bytes/s) +system.ruby.phys_mem.bw_write::cpu0.data 108910217 # Write bandwidth from this memory (bytes/s) +system.ruby.phys_mem.bw_write::cpu1.CUs0.ComputeUnit 383155 # Write bandwidth from this memory (bytes/s) +system.ruby.phys_mem.bw_write::cpu1.CUs1.ComputeUnit 383155 # Write bandwidth from this memory (bytes/s) +system.ruby.phys_mem.bw_write::total 109676526 # Write bandwidth from this memory (bytes/s) +system.ruby.phys_mem.bw_total::cpu0.inst 1042839236 # Total bandwidth to/from this memory (bytes/s) +system.ruby.phys_mem.bw_total::cpu0.data 288262521 # Total bandwidth to/from this memory (bytes/s) +system.ruby.phys_mem.bw_total::cpu1.CUs0.ComputeUnit 5292324 # Total bandwidth to/from this memory (bytes/s) +system.ruby.phys_mem.bw_total::cpu1.CUs1.ComputeUnit 5292324 # Total bandwidth to/from this memory (bytes/s) +system.ruby.phys_mem.bw_total::total 1341686404 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states +system.ruby.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states system.ruby.outstanding_req_hist_seqr::bucket_size 1 system.ruby.outstanding_req_hist_seqr::max_bucket 9 system.ruby.outstanding_req_hist_seqr::samples 114203 @@ -306,26 +316,26 @@ system.ruby.outstanding_req_hist_coalsr::total 27 system.ruby.latency_hist_seqr::bucket_size 64 system.ruby.latency_hist_seqr::max_bucket 639 system.ruby.latency_hist_seqr::samples 114203 -system.ruby.latency_hist_seqr::mean 4.784165 -system.ruby.latency_hist_seqr::gmean 2.131364 -system.ruby.latency_hist_seqr::stdev 23.846473 -system.ruby.latency_hist_seqr | 112668 98.66% 98.66% | 0 0.00% 98.66% | 0 0.00% 98.66% | 1506 1.32% 99.97% | 19 0.02% 99.99% | 10 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.latency_hist_seqr::mean 4.823332 +system.ruby.latency_hist_seqr::gmean 2.131609 +system.ruby.latency_hist_seqr::stdev 24.449444 +system.ruby.latency_hist_seqr | 112668 98.66% 98.66% | 0 0.00% 98.66% | 0 0.00% 98.66% | 1490 1.30% 99.96% | 18 0.02% 99.98% | 18 0.02% 99.99% | 2 0.00% 99.99% | 0 0.00% 99.99% | 0 0.00% 99.99% | 7 0.01% 100.00% system.ruby.latency_hist_seqr::total 114203 system.ruby.latency_hist_coalsr::bucket_size 64 system.ruby.latency_hist_coalsr::max_bucket 639 system.ruby.latency_hist_coalsr::samples 27 -system.ruby.latency_hist_coalsr::mean 141.296296 -system.ruby.latency_hist_coalsr::gmean 21.202698 -system.ruby.latency_hist_coalsr::stdev 140.217089 -system.ruby.latency_hist_coalsr | 13 48.15% 48.15% | 0 0.00% 48.15% | 0 0.00% 48.15% | 10 37.04% 85.19% | 1 3.70% 88.89% | 3 11.11% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.latency_hist_coalsr::mean 171 +system.ruby.latency_hist_coalsr::gmean 22.942606 +system.ruby.latency_hist_coalsr::stdev 184.818206 +system.ruby.latency_hist_coalsr | 13 48.15% 48.15% | 0 0.00% 48.15% | 0 0.00% 48.15% | 7 25.93% 74.07% | 2 7.41% 81.48% | 1 3.70% 85.19% | 1 3.70% 88.89% | 1 3.70% 92.59% | 2 7.41% 100.00% | 0 0.00% 100.00% system.ruby.latency_hist_coalsr::total 27 system.ruby.hit_latency_hist_seqr::bucket_size 64 system.ruby.hit_latency_hist_seqr::max_bucket 639 system.ruby.hit_latency_hist_seqr::samples 1535 -system.ruby.hit_latency_hist_seqr::mean 208.448208 -system.ruby.hit_latency_hist_seqr::gmean 208.002202 -system.ruby.hit_latency_hist_seqr::stdev 15.833423 -system.ruby.hit_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1506 98.11% 98.11% | 19 1.24% 99.35% | 10 0.65% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.hit_latency_hist_seqr::mean 211.362215 +system.ruby.hit_latency_hist_seqr::gmean 209.793806 +system.ruby.hit_latency_hist_seqr::stdev 34.965177 +system.ruby.hit_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1490 97.07% 97.07% | 18 1.17% 98.24% | 18 1.17% 99.41% | 2 0.13% 99.54% | 0 0.00% 99.54% | 0 0.00% 99.54% | 7 0.46% 100.00% system.ruby.hit_latency_hist_seqr::total 1535 system.ruby.miss_latency_hist_seqr::bucket_size 4 system.ruby.miss_latency_hist_seqr::max_bucket 39 @@ -338,10 +348,10 @@ system.ruby.miss_latency_hist_seqr::total 112668 system.ruby.miss_latency_hist_coalsr::bucket_size 64 system.ruby.miss_latency_hist_coalsr::max_bucket 639 system.ruby.miss_latency_hist_coalsr::samples 27 -system.ruby.miss_latency_hist_coalsr::mean 141.296296 -system.ruby.miss_latency_hist_coalsr::gmean 21.202698 -system.ruby.miss_latency_hist_coalsr::stdev 140.217089 -system.ruby.miss_latency_hist_coalsr | 13 48.15% 48.15% | 0 0.00% 48.15% | 0 0.00% 48.15% | 10 37.04% 85.19% | 1 3.70% 88.89% | 3 11.11% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.miss_latency_hist_coalsr::mean 171 +system.ruby.miss_latency_hist_coalsr::gmean 22.942606 +system.ruby.miss_latency_hist_coalsr::stdev 184.818206 +system.ruby.miss_latency_hist_coalsr | 13 48.15% 48.15% | 0 0.00% 48.15% | 0 0.00% 48.15% | 7 25.93% 74.07% | 2 7.41% 81.48% | 1 3.70% 85.19% | 1 3.70% 88.89% | 1 3.70% 92.59% | 2 7.41% 100.00% | 0 0.00% 100.00% system.ruby.miss_latency_hist_coalsr::total 27 system.ruby.L1Cache.incomplete_times_seqr 112609 system.ruby.L2Cache.incomplete_times_seqr 59 @@ -369,25 +379,25 @@ system.cp_cntrl0.L2cache.num_data_array_reads 120 system.cp_cntrl0.L2cache.num_data_array_writes 11982 # number of data array writes system.cp_cntrl0.L2cache.num_tag_array_reads 12059 # number of tag array reads system.cp_cntrl0.L2cache.num_tag_array_writes 1649 # number of tag array writes -system.cp_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states -system.cp_cntrl0.sequencer1.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states -system.cp_cntrl0.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states +system.cp_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states +system.cp_cntrl0.sequencer1.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states +system.cp_cntrl0.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states system.cpu0.clk_domain.clock 500 # Clock period in ticks -system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states system.cpu0.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu0.interrupts.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states -system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states +system.cpu0.interrupts.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states +system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states system.cpu0.workload.num_syscalls 21 # Number of system calls system.cpu0.numPwrStateTransitions 2 # Number of power state transitions system.cpu0.pwrStateClkGateDist::samples 1 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::mean 2615501 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::mean 2825501 # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::1000-5e+10 1 100.00% 100.00% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::min_value 2615501 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::max_value 2615501 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::min_value 2825501 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::max_value 2825501 # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::total 1 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateResidencyTicks::ON 660838999 # Cumulative time (in ticks) in various power states -system.cpu0.pwrStateResidencyTicks::CLK_GATED 2615501 # Cumulative time (in ticks) in various power states -system.cpu0.numCycles 1326909 # number of cpu cycles simulated +system.cpu0.pwrStateResidencyTicks::ON 665311999 # Cumulative time (in ticks) in various power states +system.cpu0.pwrStateResidencyTicks::CLK_GATED 2825501 # Cumulative time (in ticks) in various power states +system.cpu0.numCycles 1336275 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.committedInsts 66963 # Number of instructions committed @@ -407,10 +417,10 @@ system.cpu0.num_cc_register_writes 42183 # nu system.cpu0.num_mem_refs 27198 # number of memory refs system.cpu0.num_load_insts 16684 # Number of load instructions system.cpu0.num_store_insts 10514 # Number of store instructions -system.cpu0.num_idle_cycles 5231.003992 # Number of idle cycles -system.cpu0.num_busy_cycles 1321677.996008 # Number of busy cycles -system.cpu0.not_idle_fraction 0.996058 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.003942 # Percentage of idle cycles +system.cpu0.num_idle_cycles 5651.003992 # Number of idle cycles +system.cpu0.num_busy_cycles 1330623.996008 # Number of busy cycles +system.cpu0.not_idle_fraction 0.995771 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.004229 # Percentage of idle cycles system.cpu0.Branches 16199 # Number of branches fetched system.cpu0.op_class::No_OpClass 615 0.45% 0.45% # Class of executed instruction system.cpu0.op_class::IntAlu 108791 79.00% 79.45% # Class of executed instruction @@ -449,10 +459,10 @@ system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Cl system.cpu0.op_class::total 137705 # Class of executed instruction system.cpu1.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.cpu1.clk_domain.clock 1000 # Clock period in ticks -system.cpu1.CUs0.localDataStore.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states +system.cpu1.CUs0.localDataStore.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states system.cpu1.CUs0.wavefronts00.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability system.cpu1.CUs0.wavefronts00.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies -system.cpu1.CUs0.wavefronts00.timesBlockedDueRAWDependencies 307 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs0.wavefronts00.timesBlockedDueRAWDependencies 498 # number of times the wf's instructions are blocked due to RAW dependencies system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::samples 39 # number of executed instructions with N source register operands system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::mean 0.794872 # number of executed instructions with N source register operands system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::stdev 0.863880 # number of executed instructions with N source register operands @@ -644,7 +654,7 @@ system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::max_value 0 system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands system.cpu1.CUs0.wavefronts08.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability system.cpu1.CUs0.wavefronts08.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies -system.cpu1.CUs0.wavefronts08.timesBlockedDueRAWDependencies 279 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs0.wavefronts08.timesBlockedDueRAWDependencies 470 # number of times the wf's instructions are blocked due to RAW dependencies system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::samples 34 # number of executed instructions with N source register operands system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::mean 0.852941 # number of executed instructions with N source register operands system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::stdev 0.857493 # number of executed instructions with N source register operands @@ -836,7 +846,7 @@ system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::max_value 0 system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands system.cpu1.CUs0.wavefronts16.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability system.cpu1.CUs0.wavefronts16.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies -system.cpu1.CUs0.wavefronts16.timesBlockedDueRAWDependencies 282 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs0.wavefronts16.timesBlockedDueRAWDependencies 473 # number of times the wf's instructions are blocked due to RAW dependencies system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::samples 34 # number of executed instructions with N source register operands system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::mean 0.852941 # number of executed instructions with N source register operands system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::stdev 0.857493 # number of executed instructions with N source register operands @@ -1028,7 +1038,7 @@ system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::max_value 0 system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands system.cpu1.CUs0.wavefronts24.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability system.cpu1.CUs0.wavefronts24.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies -system.cpu1.CUs0.wavefronts24.timesBlockedDueRAWDependencies 276 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs0.wavefronts24.timesBlockedDueRAWDependencies 467 # number of times the wf's instructions are blocked due to RAW dependencies system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::samples 34 # number of executed instructions with N source register operands system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::mean 0.852941 # number of executed instructions with N source register operands system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::stdev 0.857493 # number of executed instructions with N source register operands @@ -1218,7 +1228,7 @@ system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::overflows 0 system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands -system.cpu1.CUs0.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states +system.cpu1.CUs0.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::samples 43 # For each instruction fetch request recieved record how many instructions you got from it system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::mean 5.813953 # For each instruction fetch request recieved record how many instructions you got from it system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::stdev 2.683777 # For each instruction fetch request recieved record how many instructions you got from it @@ -1259,7 +1269,7 @@ system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::overflows 0 system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::min_value 2 # For each instruction fetch request recieved record how many instructions you got from it system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::max_value 8 # For each instruction fetch request recieved record how many instructions you got from it system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::total 43 # For each instruction fetch request recieved record how many instructions you got from it -system.cpu1.CUs0.ExecStage.num_cycles_with_no_issue 3261 # number of cycles the CU issues nothing +system.cpu1.CUs0.ExecStage.num_cycles_with_no_issue 3471 # number of cycles the CU issues nothing system.cpu1.CUs0.ExecStage.num_cycles_with_instr_issued 99 # number of cycles the CU issued at least one instruction system.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::ALU0 30 # Number of cycles at least one instruction of specific type issued system.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::ALU1 29 # Number of cycles at least one instruction of specific type issued @@ -1267,19 +1277,19 @@ system.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::ALU2 29 system.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::ALU3 29 # Number of cycles at least one instruction of specific type issued system.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::GM 18 # Number of cycles at least one instruction of specific type issued system.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::LM 6 # Number of cycles at least one instruction of specific type issued -system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU0 769 # Number of cycles no instruction of specific type issued -system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU1 357 # Number of cycles no instruction of specific type issued -system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU2 375 # Number of cycles no instruction of specific type issued -system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU3 332 # Number of cycles no instruction of specific type issued +system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU0 970 # Number of cycles no instruction of specific type issued +system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU1 548 # Number of cycles no instruction of specific type issued +system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU2 566 # Number of cycles no instruction of specific type issued +system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU3 523 # Number of cycles no instruction of specific type issued system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::GM 398 # Number of cycles no instruction of specific type issued system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::LM 22 # Number of cycles no instruction of specific type issued -system.cpu1.CUs0.ExecStage.spc::samples 3360 # Execution units active per cycle (Exec unit=SIMD,MemPipe) -system.cpu1.CUs0.ExecStage.spc::mean 0.041964 # Execution units active per cycle (Exec unit=SIMD,MemPipe) -system.cpu1.CUs0.ExecStage.spc::stdev 0.257708 # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs0.ExecStage.spc::samples 3570 # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs0.ExecStage.spc::mean 0.039496 # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs0.ExecStage.spc::stdev 0.250206 # Execution units active per cycle (Exec unit=SIMD,MemPipe) system.cpu1.CUs0.ExecStage.spc::underflows 0 0.00% 0.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) -system.cpu1.CUs0.ExecStage.spc::0 3261 97.05% 97.05% # Execution units active per cycle (Exec unit=SIMD,MemPipe) -system.cpu1.CUs0.ExecStage.spc::1 59 1.76% 98.81% # Execution units active per cycle (Exec unit=SIMD,MemPipe) -system.cpu1.CUs0.ExecStage.spc::2 38 1.13% 99.94% # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs0.ExecStage.spc::0 3471 97.23% 97.23% # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs0.ExecStage.spc::1 59 1.65% 98.88% # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs0.ExecStage.spc::2 38 1.06% 99.94% # Execution units active per cycle (Exec unit=SIMD,MemPipe) system.cpu1.CUs0.ExecStage.spc::3 2 0.06% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) system.cpu1.CUs0.ExecStage.spc::4 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) system.cpu1.CUs0.ExecStage.spc::5 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) @@ -1287,11 +1297,11 @@ system.cpu1.CUs0.ExecStage.spc::6 0 0.00% 100.00% # Ex system.cpu1.CUs0.ExecStage.spc::overflows 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) system.cpu1.CUs0.ExecStage.spc::min_value 0 # Execution units active per cycle (Exec unit=SIMD,MemPipe) system.cpu1.CUs0.ExecStage.spc::max_value 3 # Execution units active per cycle (Exec unit=SIMD,MemPipe) -system.cpu1.CUs0.ExecStage.spc::total 3360 # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs0.ExecStage.spc::total 3570 # Execution units active per cycle (Exec unit=SIMD,MemPipe) system.cpu1.CUs0.ExecStage.num_transitions_active_to_idle 93 # number of CU transitions from active to idle system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::samples 93 # duration of idle periods in cycles -system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::mean 34.967742 # duration of idle periods in cycles -system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::stdev 149.478110 # duration of idle periods in cycles +system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::mean 37.225806 # duration of idle periods in cycles +system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::stdev 154.644552 # duration of idle periods in cycles system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::underflows 0 0.00% 0.00% # duration of idle periods in cycles system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::0-4 74 79.57% 79.57% # duration of idle periods in cycles system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::5-9 7 7.53% 87.10% # duration of idle periods in cycles @@ -1311,13 +1321,13 @@ system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::70-74 0 0.00 system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::75 0 0.00% 92.47% # duration of idle periods in cycles system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::overflows 7 7.53% 100.00% # duration of idle periods in cycles system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::min_value 1 # duration of idle periods in cycles -system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::max_value 1285 # duration of idle periods in cycles +system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::max_value 1291 # duration of idle periods in cycles system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::total 93 # duration of idle periods in cycles system.cpu1.CUs0.GlobalMemPipeline.load_vrf_bank_conflict_cycles 0 # total number of cycles GM data are delayed before updating the VRF system.cpu1.CUs0.LocalMemPipeline.load_vrf_bank_conflict_cycles 0 # total number of cycles LDS data are delayed before updating the VRF system.cpu1.CUs0.tlb_requests 769 # number of uncoalesced requests -system.cpu1.CUs0.tlb_cycles -452453001000 # total number of cycles for all uncoalesced requests -system.cpu1.CUs0.avg_translation_latency -588365410.923277 # Avg. translation latency for data translations +system.cpu1.CUs0.tlb_cycles -455223738000 # total number of cycles for all uncoalesced requests +system.cpu1.CUs0.avg_translation_latency -591968449.934981 # Avg. translation latency for data translations system.cpu1.CUs0.TLB_hits_distribution::page_table 769 # TLB hits distribution (0 for page table, x for Lx-TLB system.cpu1.CUs0.TLB_hits_distribution::L1_TLB 0 # TLB hits distribution (0 for page table, x for Lx-TLB system.cpu1.CUs0.TLB_hits_distribution::L2_TLB 0 # TLB hits distribution (0 for page table, x for Lx-TLB @@ -1393,8 +1403,8 @@ system.cpu1.CUs0.local_mem_instr_cnt 6 # dy system.cpu1.CUs0.wg_blocked_due_lds_alloc 0 # Workgroup blocked due to LDS capacity system.cpu1.CUs0.num_instr_executed 141 # number of instructions executed system.cpu1.CUs0.inst_exec_rate::samples 141 # Instruction Execution Rate: Number of executed vector instructions per cycle -system.cpu1.CUs0.inst_exec_rate::mean 86.382979 # Instruction Execution Rate: Number of executed vector instructions per cycle -system.cpu1.CUs0.inst_exec_rate::stdev 229.706697 # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs0.inst_exec_rate::mean 92.127660 # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs0.inst_exec_rate::stdev 237.147810 # Instruction Execution Rate: Number of executed vector instructions per cycle system.cpu1.CUs0.inst_exec_rate::underflows 0 0.00% 0.00% # Instruction Execution Rate: Number of executed vector instructions per cycle system.cpu1.CUs0.inst_exec_rate::0-1 0 0.00% 0.00% # Instruction Execution Rate: Number of executed vector instructions per cycle system.cpu1.CUs0.inst_exec_rate::2-3 12 8.51% 8.51% # Instruction Execution Rate: Number of executed vector instructions per cycle @@ -1404,12 +1414,12 @@ system.cpu1.CUs0.inst_exec_rate::8-9 3 2.13% 69.50% # In system.cpu1.CUs0.inst_exec_rate::10 3 2.13% 71.63% # Instruction Execution Rate: Number of executed vector instructions per cycle system.cpu1.CUs0.inst_exec_rate::overflows 40 28.37% 100.00% # Instruction Execution Rate: Number of executed vector instructions per cycle system.cpu1.CUs0.inst_exec_rate::min_value 2 # Instruction Execution Rate: Number of executed vector instructions per cycle -system.cpu1.CUs0.inst_exec_rate::max_value 1291 # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs0.inst_exec_rate::max_value 1297 # Instruction Execution Rate: Number of executed vector instructions per cycle system.cpu1.CUs0.inst_exec_rate::total 141 # Instruction Execution Rate: Number of executed vector instructions per cycle -system.cpu1.CUs0.num_vec_ops_executed 6769 # number of vec ops executed (e.g. VSZ/inst) -system.cpu1.CUs0.num_total_cycles 3360 # number of cycles the CU ran for -system.cpu1.CUs0.vpc 2.014583 # Vector Operations per cycle (this CU only) -system.cpu1.CUs0.ipc 0.041964 # Instructions per cycle (this CU only) +system.cpu1.CUs0.num_vec_ops_executed 6769 # number of vec ops executed (e.g. WF size/inst) +system.cpu1.CUs0.num_total_cycles 3570 # number of cycles the CU ran for +system.cpu1.CUs0.vpc 1.896078 # Vector Operations per cycle (this CU only) +system.cpu1.CUs0.ipc 0.039496 # Instructions per cycle (this CU only) system.cpu1.CUs0.warp_execution_dist::samples 141 # number of lanes active per instruction (oval all instructions) system.cpu1.CUs0.warp_execution_dist::mean 48.007092 # number of lanes active per instruction (oval all instructions) system.cpu1.CUs0.warp_execution_dist::stdev 23.719942 # number of lanes active per instruction (oval all instructions) @@ -1487,10 +1497,10 @@ system.cpu1.CUs0.times_wg_blocked_due_vgpr_alloc 0 system.cpu1.CUs0.num_CAS_ops 0 # number of compare and swap operations system.cpu1.CUs0.num_failed_CAS_ops 0 # number of compare and swap operations that failed system.cpu1.CUs0.num_completed_wfs 4 # number of completed wavefronts -system.cpu1.CUs1.localDataStore.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states +system.cpu1.CUs1.localDataStore.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states system.cpu1.CUs1.wavefronts00.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability system.cpu1.CUs1.wavefronts00.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies -system.cpu1.CUs1.wavefronts00.timesBlockedDueRAWDependencies 401 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs1.wavefronts00.timesBlockedDueRAWDependencies 591 # number of times the wf's instructions are blocked due to RAW dependencies system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::samples 39 # number of executed instructions with N source register operands system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::mean 0.794872 # number of executed instructions with N source register operands system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::stdev 0.863880 # number of executed instructions with N source register operands @@ -1682,7 +1692,7 @@ system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::max_value 0 system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands system.cpu1.CUs1.wavefronts08.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability system.cpu1.CUs1.wavefronts08.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies -system.cpu1.CUs1.wavefronts08.timesBlockedDueRAWDependencies 372 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs1.wavefronts08.timesBlockedDueRAWDependencies 562 # number of times the wf's instructions are blocked due to RAW dependencies system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::samples 34 # number of executed instructions with N source register operands system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::mean 0.852941 # number of executed instructions with N source register operands system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::stdev 0.857493 # number of executed instructions with N source register operands @@ -1874,7 +1884,7 @@ system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::max_value 0 system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands system.cpu1.CUs1.wavefronts16.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability system.cpu1.CUs1.wavefronts16.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies -system.cpu1.CUs1.wavefronts16.timesBlockedDueRAWDependencies 371 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs1.wavefronts16.timesBlockedDueRAWDependencies 561 # number of times the wf's instructions are blocked due to RAW dependencies system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::samples 34 # number of executed instructions with N source register operands system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::mean 0.852941 # number of executed instructions with N source register operands system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::stdev 0.857493 # number of executed instructions with N source register operands @@ -2066,7 +2076,7 @@ system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::max_value 0 system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands system.cpu1.CUs1.wavefronts24.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability system.cpu1.CUs1.wavefronts24.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies -system.cpu1.CUs1.wavefronts24.timesBlockedDueRAWDependencies 361 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs1.wavefronts24.timesBlockedDueRAWDependencies 551 # number of times the wf's instructions are blocked due to RAW dependencies system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::samples 34 # number of executed instructions with N source register operands system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::mean 0.852941 # number of executed instructions with N source register operands system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::stdev 0.857493 # number of executed instructions with N source register operands @@ -2256,7 +2266,7 @@ system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::overflows 0 system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands -system.cpu1.CUs1.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states +system.cpu1.CUs1.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::samples 43 # For each instruction fetch request recieved record how many instructions you got from it system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::mean 5.813953 # For each instruction fetch request recieved record how many instructions you got from it system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::stdev 2.683777 # For each instruction fetch request recieved record how many instructions you got from it @@ -2297,7 +2307,7 @@ system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::overflows 0 system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::min_value 2 # For each instruction fetch request recieved record how many instructions you got from it system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::max_value 8 # For each instruction fetch request recieved record how many instructions you got from it system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::total 43 # For each instruction fetch request recieved record how many instructions you got from it -system.cpu1.CUs1.ExecStage.num_cycles_with_no_issue 3261 # number of cycles the CU issues nothing +system.cpu1.CUs1.ExecStage.num_cycles_with_no_issue 3471 # number of cycles the CU issues nothing system.cpu1.CUs1.ExecStage.num_cycles_with_instr_issued 99 # number of cycles the CU issued at least one instruction system.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::ALU0 30 # Number of cycles at least one instruction of specific type issued system.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::ALU1 29 # Number of cycles at least one instruction of specific type issued @@ -2305,19 +2315,19 @@ system.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::ALU2 29 system.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::ALU3 29 # Number of cycles at least one instruction of specific type issued system.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::GM 18 # Number of cycles at least one instruction of specific type issued system.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::LM 6 # Number of cycles at least one instruction of specific type issued -system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::ALU0 777 # Number of cycles no instruction of specific type issued -system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::ALU1 472 # Number of cycles no instruction of specific type issued -system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::ALU2 444 # Number of cycles no instruction of specific type issued -system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::ALU3 416 # Number of cycles no instruction of specific type issued +system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::ALU0 973 # Number of cycles no instruction of specific type issued +system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::ALU1 662 # Number of cycles no instruction of specific type issued +system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::ALU2 634 # Number of cycles no instruction of specific type issued +system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::ALU3 606 # Number of cycles no instruction of specific type issued system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::GM 404 # Number of cycles no instruction of specific type issued system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::LM 22 # Number of cycles no instruction of specific type issued -system.cpu1.CUs1.ExecStage.spc::samples 3360 # Execution units active per cycle (Exec unit=SIMD,MemPipe) -system.cpu1.CUs1.ExecStage.spc::mean 0.041964 # Execution units active per cycle (Exec unit=SIMD,MemPipe) -system.cpu1.CUs1.ExecStage.spc::stdev 0.256550 # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs1.ExecStage.spc::samples 3570 # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs1.ExecStage.spc::mean 0.039496 # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs1.ExecStage.spc::stdev 0.249084 # Execution units active per cycle (Exec unit=SIMD,MemPipe) system.cpu1.CUs1.ExecStage.spc::underflows 0 0.00% 0.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) -system.cpu1.CUs1.ExecStage.spc::0 3261 97.05% 97.05% # Execution units active per cycle (Exec unit=SIMD,MemPipe) -system.cpu1.CUs1.ExecStage.spc::1 58 1.73% 98.78% # Execution units active per cycle (Exec unit=SIMD,MemPipe) -system.cpu1.CUs1.ExecStage.spc::2 40 1.19% 99.97% # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs1.ExecStage.spc::0 3471 97.23% 97.23% # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs1.ExecStage.spc::1 58 1.62% 98.85% # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs1.ExecStage.spc::2 40 1.12% 99.97% # Execution units active per cycle (Exec unit=SIMD,MemPipe) system.cpu1.CUs1.ExecStage.spc::3 1 0.03% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) system.cpu1.CUs1.ExecStage.spc::4 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) system.cpu1.CUs1.ExecStage.spc::5 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) @@ -2325,11 +2335,11 @@ system.cpu1.CUs1.ExecStage.spc::6 0 0.00% 100.00% # Ex system.cpu1.CUs1.ExecStage.spc::overflows 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) system.cpu1.CUs1.ExecStage.spc::min_value 0 # Execution units active per cycle (Exec unit=SIMD,MemPipe) system.cpu1.CUs1.ExecStage.spc::max_value 3 # Execution units active per cycle (Exec unit=SIMD,MemPipe) -system.cpu1.CUs1.ExecStage.spc::total 3360 # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs1.ExecStage.spc::total 3570 # Execution units active per cycle (Exec unit=SIMD,MemPipe) system.cpu1.CUs1.ExecStage.num_transitions_active_to_idle 94 # number of CU transitions from active to idle system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::samples 94 # duration of idle periods in cycles -system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::mean 33.585106 # duration of idle periods in cycles -system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::stdev 147.747562 # duration of idle periods in cycles +system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::mean 35.776596 # duration of idle periods in cycles +system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::stdev 153.908027 # duration of idle periods in cycles system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::underflows 0 0.00% 0.00% # duration of idle periods in cycles system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::0-4 75 79.79% 79.79% # duration of idle periods in cycles system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::5-9 8 8.51% 88.30% # duration of idle periods in cycles @@ -2349,13 +2359,13 @@ system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::70-74 0 0.00 system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::75 0 0.00% 92.55% # duration of idle periods in cycles system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::overflows 7 7.45% 100.00% # duration of idle periods in cycles system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::min_value 1 # duration of idle periods in cycles -system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::max_value 1293 # duration of idle periods in cycles +system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::max_value 1299 # duration of idle periods in cycles system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::total 94 # duration of idle periods in cycles system.cpu1.CUs1.GlobalMemPipeline.load_vrf_bank_conflict_cycles 0 # total number of cycles GM data are delayed before updating the VRF system.cpu1.CUs1.LocalMemPipeline.load_vrf_bank_conflict_cycles 0 # total number of cycles LDS data are delayed before updating the VRF system.cpu1.CUs1.tlb_requests 769 # number of uncoalesced requests -system.cpu1.CUs1.tlb_cycles -452459838000 # total number of cycles for all uncoalesced requests -system.cpu1.CUs1.avg_translation_latency -588374301.690507 # Avg. translation latency for data translations +system.cpu1.CUs1.tlb_cycles -455230572000 # total number of cycles for all uncoalesced requests +system.cpu1.CUs1.avg_translation_latency -591977336.801040 # Avg. translation latency for data translations system.cpu1.CUs1.TLB_hits_distribution::page_table 769 # TLB hits distribution (0 for page table, x for Lx-TLB system.cpu1.CUs1.TLB_hits_distribution::L1_TLB 0 # TLB hits distribution (0 for page table, x for Lx-TLB system.cpu1.CUs1.TLB_hits_distribution::L2_TLB 0 # TLB hits distribution (0 for page table, x for Lx-TLB @@ -2431,8 +2441,8 @@ system.cpu1.CUs1.local_mem_instr_cnt 6 # dy system.cpu1.CUs1.wg_blocked_due_lds_alloc 0 # Workgroup blocked due to LDS capacity system.cpu1.CUs1.num_instr_executed 141 # number of instructions executed system.cpu1.CUs1.inst_exec_rate::samples 141 # Instruction Execution Rate: Number of executed vector instructions per cycle -system.cpu1.CUs1.inst_exec_rate::mean 85.553191 # Instruction Execution Rate: Number of executed vector instructions per cycle -system.cpu1.CUs1.inst_exec_rate::stdev 230.829913 # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs1.inst_exec_rate::mean 91.269504 # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs1.inst_exec_rate::stdev 240.230451 # Instruction Execution Rate: Number of executed vector instructions per cycle system.cpu1.CUs1.inst_exec_rate::underflows 0 0.00% 0.00% # Instruction Execution Rate: Number of executed vector instructions per cycle system.cpu1.CUs1.inst_exec_rate::0-1 0 0.00% 0.00% # Instruction Execution Rate: Number of executed vector instructions per cycle system.cpu1.CUs1.inst_exec_rate::2-3 13 9.22% 9.22% # Instruction Execution Rate: Number of executed vector instructions per cycle @@ -2442,12 +2452,12 @@ system.cpu1.CUs1.inst_exec_rate::8-9 6 4.26% 73.76% # In system.cpu1.CUs1.inst_exec_rate::10 0 0.00% 73.76% # Instruction Execution Rate: Number of executed vector instructions per cycle system.cpu1.CUs1.inst_exec_rate::overflows 37 26.24% 100.00% # Instruction Execution Rate: Number of executed vector instructions per cycle system.cpu1.CUs1.inst_exec_rate::min_value 2 # Instruction Execution Rate: Number of executed vector instructions per cycle -system.cpu1.CUs1.inst_exec_rate::max_value 1299 # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs1.inst_exec_rate::max_value 1305 # Instruction Execution Rate: Number of executed vector instructions per cycle system.cpu1.CUs1.inst_exec_rate::total 141 # Instruction Execution Rate: Number of executed vector instructions per cycle -system.cpu1.CUs1.num_vec_ops_executed 6762 # number of vec ops executed (e.g. VSZ/inst) -system.cpu1.CUs1.num_total_cycles 3360 # number of cycles the CU ran for -system.cpu1.CUs1.vpc 2.012500 # Vector Operations per cycle (this CU only) -system.cpu1.CUs1.ipc 0.041964 # Instructions per cycle (this CU only) +system.cpu1.CUs1.num_vec_ops_executed 6762 # number of vec ops executed (e.g. WF size/inst) +system.cpu1.CUs1.num_total_cycles 3570 # number of cycles the CU ran for +system.cpu1.CUs1.vpc 1.894118 # Vector Operations per cycle (this CU only) +system.cpu1.CUs1.ipc 0.039496 # Instructions per cycle (this CU only) system.cpu1.CUs1.warp_execution_dist::samples 141 # number of lanes active per instruction (oval all instructions) system.cpu1.CUs1.warp_execution_dist::mean 47.957447 # number of lanes active per instruction (oval all instructions) system.cpu1.CUs1.warp_execution_dist::stdev 23.818022 # number of lanes active per instruction (oval all instructions) @@ -2525,9 +2535,9 @@ system.cpu1.CUs1.times_wg_blocked_due_vgpr_alloc 0 system.cpu1.CUs1.num_CAS_ops 0 # number of compare and swap operations system.cpu1.CUs1.num_failed_CAS_ops 0 # number of compare and swap operations that failed system.cpu1.CUs1.num_completed_wfs 4 # number of completed wavefronts -system.cpu1.CUs0.ldsBus.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states -system.cpu1.CUs1.ldsBus.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states -system.cpu2.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states +system.cpu1.CUs0.ldsBus.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states +system.cpu1.CUs1.ldsBus.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states +system.cpu2.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states system.cpu2.num_kernel_launched 1 # number of kernel launched system.dir_cntrl0.L3CacheMemory.demand_hits 0 # Number of cache demand hits system.dir_cntrl0.L3CacheMemory.demand_misses 0 # Number of cache demand misses @@ -2535,10 +2545,10 @@ system.dir_cntrl0.L3CacheMemory.demand_accesses 0 system.dir_cntrl0.L3CacheMemory.num_data_array_writes 1551 # number of data array writes system.dir_cntrl0.L3CacheMemory.num_tag_array_reads 1551 # number of tag array reads system.dir_cntrl0.L3CacheMemory.num_tag_array_writes 1551 # number of tag array writes -system.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states +system.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states system.dispatcher_coalescer.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.dispatcher_coalescer.clk_domain.clock 1000 # Clock period in ticks -system.dispatcher_coalescer.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states +system.dispatcher_coalescer.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states system.dispatcher_coalescer.uncoalesced_accesses 0 # Number of uncoalesced TLB accesses system.dispatcher_coalescer.coalesced_accesses 0 # Number of coalesced TLB accesses system.dispatcher_coalescer.queuing_cycles 0 # Number of cycles spent in queue @@ -2546,7 +2556,7 @@ system.dispatcher_coalescer.local_queuing_cycles 0 system.dispatcher_coalescer.local_latency nan # Avg. latency over all incoming pkts system.dispatcher_tlb.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.dispatcher_tlb.clk_domain.clock 1000 # Clock period in ticks -system.dispatcher_tlb.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states +system.dispatcher_tlb.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states system.dispatcher_tlb.local_TLB_accesses 0 # Number of TLB accesses system.dispatcher_tlb.local_TLB_hits 0 # Number of TLB hits system.dispatcher_tlb.local_TLB_misses 0 # Number of TLB misses @@ -2563,7 +2573,7 @@ system.dispatcher_tlb.local_latency nan # Av system.dispatcher_tlb.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks) system.l1_coalescer0.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.l1_coalescer0.clk_domain.clock 1000 # Clock period in ticks -system.l1_coalescer0.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states +system.l1_coalescer0.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states system.l1_coalescer0.uncoalesced_accesses 778 # Number of uncoalesced TLB accesses system.l1_coalescer0.coalesced_accesses 0 # Number of coalesced TLB accesses system.l1_coalescer0.queuing_cycles 0 # Number of cycles spent in queue @@ -2571,7 +2581,7 @@ system.l1_coalescer0.local_queuing_cycles 0 # N system.l1_coalescer0.local_latency 0 # Avg. latency over all incoming pkts system.l1_coalescer1.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.l1_coalescer1.clk_domain.clock 1000 # Clock period in ticks -system.l1_coalescer1.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states +system.l1_coalescer1.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states system.l1_coalescer1.uncoalesced_accesses 769 # Number of uncoalesced TLB accesses system.l1_coalescer1.coalesced_accesses 0 # Number of coalesced TLB accesses system.l1_coalescer1.queuing_cycles 0 # Number of cycles spent in queue @@ -2579,7 +2589,7 @@ system.l1_coalescer1.local_queuing_cycles 0 # N system.l1_coalescer1.local_latency 0 # Avg. latency over all incoming pkts system.l1_tlb0.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.l1_tlb0.clk_domain.clock 1000 # Clock period in ticks -system.l1_tlb0.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states +system.l1_tlb0.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states system.l1_tlb0.local_TLB_accesses 778 # Number of TLB accesses system.l1_tlb0.local_TLB_hits 774 # Number of TLB hits system.l1_tlb0.local_TLB_misses 4 # Number of TLB misses @@ -2596,7 +2606,7 @@ system.l1_tlb0.local_latency 0 # Av system.l1_tlb0.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks) system.l1_tlb1.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.l1_tlb1.clk_domain.clock 1000 # Clock period in ticks -system.l1_tlb1.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states +system.l1_tlb1.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states system.l1_tlb1.local_TLB_accesses 769 # Number of TLB accesses system.l1_tlb1.local_TLB_hits 766 # Number of TLB hits system.l1_tlb1.local_TLB_misses 3 # Number of TLB misses @@ -2613,7 +2623,7 @@ system.l1_tlb1.local_latency 0 # Av system.l1_tlb1.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks) system.l2_coalescer.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.l2_coalescer.clk_domain.clock 1000 # Clock period in ticks -system.l2_coalescer.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states +system.l2_coalescer.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states system.l2_coalescer.uncoalesced_accesses 8 # Number of uncoalesced TLB accesses system.l2_coalescer.coalesced_accesses 1 # Number of coalesced TLB accesses system.l2_coalescer.queuing_cycles 8000 # Number of cycles spent in queue @@ -2621,7 +2631,7 @@ system.l2_coalescer.local_queuing_cycles 1000 # Nu system.l2_coalescer.local_latency 125 # Avg. latency over all incoming pkts system.l2_tlb.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.l2_tlb.clk_domain.clock 1000 # Clock period in ticks -system.l2_tlb.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states +system.l2_tlb.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states system.l2_tlb.local_TLB_accesses 8 # Number of TLB accesses system.l2_tlb.local_TLB_hits 3 # Number of TLB hits system.l2_tlb.local_TLB_misses 5 # Number of TLB misses @@ -2638,7 +2648,7 @@ system.l2_tlb.local_latency 8625.125000 # Av system.l2_tlb.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks) system.l3_coalescer.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.l3_coalescer.clk_domain.clock 1000 # Clock period in ticks -system.l3_coalescer.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states +system.l3_coalescer.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states system.l3_coalescer.uncoalesced_accesses 5 # Number of uncoalesced TLB accesses system.l3_coalescer.coalesced_accesses 1 # Number of coalesced TLB accesses system.l3_coalescer.queuing_cycles 8000 # Number of cycles spent in queue @@ -2646,7 +2656,7 @@ system.l3_coalescer.local_queuing_cycles 1000 # Nu system.l3_coalescer.local_latency 200 # Avg. latency over all incoming pkts system.l3_tlb.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.l3_tlb.clk_domain.clock 1000 # Clock period in ticks -system.l3_tlb.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states +system.l3_tlb.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states system.l3_tlb.local_TLB_accesses 5 # Number of TLB accesses system.l3_tlb.local_TLB_hits 0 # Number of TLB hits system.l3_tlb.local_TLB_misses 5 # Number of TLB misses @@ -2661,7 +2671,7 @@ system.l3_tlb.unique_pages 5 # Nu system.l3_tlb.local_cycles 150000 # Number of cycles spent in queue for all incoming reqs system.l3_tlb.local_latency 30000 # Avg. latency over incoming coalesced reqs system.l3_tlb.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks) -system.piobus.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states +system.piobus.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states system.piobus.trans_dist::WriteReq 94 # Transaction distribution system.piobus.trans_dist::WriteResp 94 # Transaction distribution system.piobus.pkt_count_system.cp_cntrl0.sequencer.mem-master-port::system.cpu2.pio 188 # Packet count per connected master and slave (bytes) @@ -2672,8 +2682,8 @@ system.piobus.reqLayer0.occupancy 188000 # La system.piobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.piobus.respLayer0.occupancy 94000 # Layer occupancy (ticks) system.piobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.ruby.network.ext_links0.int_node.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states -system.ruby.network.ext_links0.int_node.percent_links_utilized 0.007952 +system.ruby.network.ext_links0.int_node.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states +system.ruby.network.ext_links0.int_node.percent_links_utilized 0.007896 system.ruby.network.ext_links0.int_node.msg_count.Control::0 1551 system.ruby.network.ext_links0.int_node.msg_count.Request_Control::0 1551 system.ruby.network.ext_links0.int_node.msg_count.Response_Data::2 1563 @@ -2684,8 +2694,8 @@ system.ruby.network.ext_links0.int_node.msg_bytes.Request_Control::0 1240 system.ruby.network.ext_links0.int_node.msg_bytes.Response_Data::2 112536 system.ruby.network.ext_links0.int_node.msg_bytes.Response_Control::2 12312 system.ruby.network.ext_links0.int_node.msg_bytes.Unblock_Control::4 12408 -system.ruby.network.ext_links1.int_node.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states -system.ruby.network.ext_links1.int_node.percent_links_utilized 0.009970 +system.ruby.network.ext_links1.int_node.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states +system.ruby.network.ext_links1.int_node.percent_links_utilized 0.009900 system.ruby.network.ext_links1.int_node.msg_count.Control::0 16 system.ruby.network.ext_links1.int_node.msg_count.Request_Control::0 1535 system.ruby.network.ext_links1.int_node.msg_count.Response_Data::2 1537 @@ -2704,7 +2714,7 @@ system.tcp_cntrl0.L1cache.num_data_array_writes 11 system.tcp_cntrl0.L1cache.num_tag_array_reads 26 # number of tag array reads system.tcp_cntrl0.L1cache.num_tag_array_writes 18 # number of tag array writes system.tcp_cntrl0.L1cache.num_data_array_stalls 2 # number of stalls caused by data array -system.tcp_cntrl0.coalescer.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states +system.tcp_cntrl0.coalescer.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states system.tcp_cntrl0.coalescer.gpu_tcp_ld_hits 2 # loads that hit in the TCP system.tcp_cntrl0.coalescer.gpu_tcp_ld_transfers 0 # TCP to TCP load transfers system.tcp_cntrl0.coalescer.gpu_tcc_ld_hits 0 # loads that hit in the TCC @@ -2721,10 +2731,10 @@ system.tcp_cntrl0.coalescer.cp_tcp_st_hits 0 # system.tcp_cntrl0.coalescer.cp_tcp_st_transfers 0 # TCP to TCP store transfers system.tcp_cntrl0.coalescer.cp_tcc_st_hits 0 # stores that hit in the TCC system.tcp_cntrl0.coalescer.cp_st_misses 0 # stores that miss in the GPU -system.tcp_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states -system.tcp_cntrl0.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states -system.ruby.network.ext_links2.int_node.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states -system.ruby.network.ext_links2.int_node.percent_links_utilized 0.000721 +system.tcp_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states +system.tcp_cntrl0.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states +system.ruby.network.ext_links2.int_node.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states +system.ruby.network.ext_links2.int_node.percent_links_utilized 0.000716 system.ruby.network.ext_links2.int_node.msg_count.Control::0 1535 system.ruby.network.ext_links2.int_node.msg_count.Control::1 14 system.ruby.network.ext_links2.int_node.msg_count.Request_Control::0 16 @@ -2752,7 +2762,7 @@ system.tcp_cntrl1.L1cache.num_tag_array_reads 25 system.tcp_cntrl1.L1cache.num_tag_array_writes 18 # number of tag array writes system.tcp_cntrl1.L1cache.num_tag_array_stalls 2 # number of stalls caused by tag array system.tcp_cntrl1.L1cache.num_data_array_stalls 2 # number of stalls caused by data array -system.tcp_cntrl1.coalescer.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states +system.tcp_cntrl1.coalescer.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states system.tcp_cntrl1.coalescer.gpu_tcp_ld_hits 3 # loads that hit in the TCP system.tcp_cntrl1.coalescer.gpu_tcp_ld_transfers 2 # TCP to TCP load transfers system.tcp_cntrl1.coalescer.gpu_tcc_ld_hits 0 # loads that hit in the TCC @@ -2769,8 +2779,8 @@ system.tcp_cntrl1.coalescer.cp_tcp_st_hits 0 # system.tcp_cntrl1.coalescer.cp_tcp_st_transfers 0 # TCP to TCP store transfers system.tcp_cntrl1.coalescer.cp_tcc_st_hits 0 # stores that hit in the TCC system.tcp_cntrl1.coalescer.cp_st_misses 0 # stores that miss in the GPU -system.tcp_cntrl1.sequencer.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states -system.tcp_cntrl1.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states +system.tcp_cntrl1.sequencer.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states +system.tcp_cntrl1.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states system.sqc_cntrl0.L1cache.demand_hits 0 # Number of cache demand hits system.sqc_cntrl0.L1cache.demand_misses 0 # Number of cache demand misses system.sqc_cntrl0.L1cache.demand_accesses 0 # Number of cache demand accesses @@ -2779,20 +2789,20 @@ system.sqc_cntrl0.L1cache.num_data_array_writes 5 system.sqc_cntrl0.L1cache.num_tag_array_reads 86 # number of tag array reads system.sqc_cntrl0.L1cache.num_tag_array_writes 5 # number of tag array writes system.sqc_cntrl0.L1cache.num_data_array_stalls 47 # number of stalls caused by data array -system.sqc_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states +system.sqc_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states system.sqc_cntrl0.sequencer.load_waiting_on_load 120 # Number of times a load aliased with a pending load -system.sqc_cntrl0.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states +system.sqc_cntrl0.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states system.tcc_cntrl0.L2cache.demand_hits 0 # Number of cache demand hits system.tcc_cntrl0.L2cache.demand_misses 0 # Number of cache demand misses system.tcc_cntrl0.L2cache.demand_accesses 0 # Number of cache demand accesses -system.tcc_cntrl0.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states +system.tcc_cntrl0.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states system.tccdir_cntrl0.directory.demand_hits 0 # Number of cache demand hits system.tccdir_cntrl0.directory.demand_misses 0 # Number of cache demand misses system.tccdir_cntrl0.directory.demand_accesses 0 # Number of cache demand accesses system.tccdir_cntrl0.directory.num_tag_array_reads 1554 # number of tag array reads system.tccdir_cntrl0.directory.num_tag_array_writes 27 # number of tag array writes -system.tccdir_cntrl0.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states -system.ruby.network.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states +system.tccdir_cntrl0.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states +system.ruby.network.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states system.ruby.network.msg_count.Control 3116 system.ruby.network.msg_count.Request_Control 3121 system.ruby.network.msg_count.Response_Data 3159 @@ -2805,7 +2815,7 @@ system.ruby.network.msg_byte.Response_Control 24624 system.ruby.network.msg_byte.Unblock_Control 24968 system.sqc_coalescer.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.sqc_coalescer.clk_domain.clock 1000 # Clock period in ticks -system.sqc_coalescer.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states +system.sqc_coalescer.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states system.sqc_coalescer.uncoalesced_accesses 86 # Number of uncoalesced TLB accesses system.sqc_coalescer.coalesced_accesses 60 # Number of coalesced TLB accesses system.sqc_coalescer.queuing_cycles 108000 # Number of cycles spent in queue @@ -2813,7 +2823,7 @@ system.sqc_coalescer.local_queuing_cycles 108000 # N system.sqc_coalescer.local_latency 1255.813953 # Avg. latency over all incoming pkts system.sqc_tlb.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.sqc_tlb.clk_domain.clock 1000 # Clock period in ticks -system.sqc_tlb.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states +system.sqc_tlb.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states system.sqc_tlb.local_TLB_accesses 60 # Number of TLB accesses system.sqc_tlb.local_TLB_hits 59 # Number of TLB hits system.sqc_tlb.local_TLB_misses 1 # Number of TLB misses @@ -2828,8 +2838,8 @@ system.sqc_tlb.unique_pages 1 # Nu system.sqc_tlb.local_cycles 60001 # Number of cycles spent in queue for all incoming reqs system.sqc_tlb.local_latency 1000.016667 # Avg. latency over incoming coalesced reqs system.sqc_tlb.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks) -system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 663454500 # Cumulative time (in ticks) in various power states -system.ruby.network.ext_links0.int_node.throttle0.link_utilization 0.005592 +system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 668137500 # Cumulative time (in ticks) in various power states +system.ruby.network.ext_links0.int_node.throttle0.link_utilization 0.005553 system.ruby.network.ext_links0.int_node.throttle0.msg_count.Request_Control::0 1551 system.ruby.network.ext_links0.int_node.throttle0.msg_count.Response_Data::2 12 system.ruby.network.ext_links0.int_node.throttle0.msg_count.Response_Control::2 1539 @@ -2838,22 +2848,22 @@ system.ruby.network.ext_links0.int_node.throttle0.msg_bytes.Request_Control::0 system.ruby.network.ext_links0.int_node.throttle0.msg_bytes.Response_Data::2 864 system.ruby.network.ext_links0.int_node.throttle0.msg_bytes.Response_Control::2 12312 system.ruby.network.ext_links0.int_node.throttle0.msg_bytes.Unblock_Control::4 12408 -system.ruby.network.ext_links0.int_node.throttle1.link_utilization 0.016287 +system.ruby.network.ext_links0.int_node.throttle1.link_utilization 0.016173 system.ruby.network.ext_links0.int_node.throttle1.msg_count.Control::0 16 system.ruby.network.ext_links0.int_node.throttle1.msg_count.Response_Data::2 1535 system.ruby.network.ext_links0.int_node.throttle1.msg_bytes.Control::0 128 system.ruby.network.ext_links0.int_node.throttle1.msg_bytes.Response_Data::2 110520 -system.ruby.network.ext_links0.int_node.throttle2.link_utilization 0.001977 +system.ruby.network.ext_links0.int_node.throttle2.link_utilization 0.001963 system.ruby.network.ext_links0.int_node.throttle2.msg_count.Control::0 1535 system.ruby.network.ext_links0.int_node.throttle2.msg_count.Response_Data::2 16 system.ruby.network.ext_links0.int_node.throttle2.msg_bytes.Control::0 12280 system.ruby.network.ext_links0.int_node.throttle2.msg_bytes.Response_Data::2 1152 -system.ruby.network.ext_links1.int_node.throttle0.link_utilization 0.016287 +system.ruby.network.ext_links1.int_node.throttle0.link_utilization 0.016173 system.ruby.network.ext_links1.int_node.throttle0.msg_count.Control::0 16 system.ruby.network.ext_links1.int_node.throttle0.msg_count.Response_Data::2 1535 system.ruby.network.ext_links1.int_node.throttle0.msg_bytes.Control::0 128 system.ruby.network.ext_links1.int_node.throttle0.msg_bytes.Response_Data::2 110520 -system.ruby.network.ext_links1.int_node.throttle1.link_utilization 0.003653 +system.ruby.network.ext_links1.int_node.throttle1.link_utilization 0.003627 system.ruby.network.ext_links1.int_node.throttle1.msg_count.Request_Control::0 1535 system.ruby.network.ext_links1.int_node.throttle1.msg_count.Response_Data::2 2 system.ruby.network.ext_links1.int_node.throttle1.msg_count.Response_Control::2 14 @@ -2862,7 +2872,7 @@ system.ruby.network.ext_links1.int_node.throttle1.msg_bytes.Request_Control::0 system.ruby.network.ext_links1.int_node.throttle1.msg_bytes.Response_Data::2 144 system.ruby.network.ext_links1.int_node.throttle1.msg_bytes.Response_Control::2 112 system.ruby.network.ext_links1.int_node.throttle1.msg_bytes.Unblock_Control::4 12280 -system.ruby.network.ext_links2.int_node.throttle0.link_utilization 0.000084 +system.ruby.network.ext_links2.int_node.throttle0.link_utilization 0.000083 system.ruby.network.ext_links2.int_node.throttle0.msg_count.Control::1 8 system.ruby.network.ext_links2.int_node.throttle0.msg_count.Response_Data::3 7 system.ruby.network.ext_links2.int_node.throttle0.msg_bytes.Control::1 64 @@ -2873,7 +2883,7 @@ system.ruby.network.ext_links2.int_node.throttle1.msg_count.Response_Data::3 system.ruby.network.ext_links2.int_node.throttle1.msg_bytes.Control::1 48 system.ruby.network.ext_links2.int_node.throttle1.msg_bytes.Response_Data::3 504 system.ruby.network.ext_links2.int_node.throttle2.link_utilization 0 -system.ruby.network.ext_links2.int_node.throttle3.link_utilization 0.002170 +system.ruby.network.ext_links2.int_node.throttle3.link_utilization 0.002155 system.ruby.network.ext_links2.int_node.throttle3.msg_count.Control::0 1535 system.ruby.network.ext_links2.int_node.throttle3.msg_count.Request_Control::1 19 system.ruby.network.ext_links2.int_node.throttle3.msg_count.Response_Data::2 16 @@ -2887,7 +2897,7 @@ system.ruby.network.ext_links2.int_node.throttle3.msg_bytes.Unblock_Control::5 system.ruby.network.ext_links2.int_node.throttle4.link_utilization 0.000053 system.ruby.network.ext_links2.int_node.throttle4.msg_count.Response_Data::3 5 system.ruby.network.ext_links2.int_node.throttle4.msg_bytes.Response_Data::3 360 -system.ruby.network.ext_links2.int_node.throttle5.link_utilization 0.001939 +system.ruby.network.ext_links2.int_node.throttle5.link_utilization 0.001926 system.ruby.network.ext_links2.int_node.throttle5.msg_count.Request_Control::0 16 system.ruby.network.ext_links2.int_node.throttle5.msg_count.Response_Data::2 10 system.ruby.network.ext_links2.int_node.throttle5.msg_count.Response_Control::2 1525 @@ -2951,48 +2961,48 @@ system.ruby.Directory_Controller.CoreUnblock 1551 0.00% 0.00% system.ruby.Directory_Controller.U.RdBlkS 1039 0.00% 0.00% system.ruby.Directory_Controller.U.RdBlkM 335 0.00% 0.00% system.ruby.Directory_Controller.U.RdBlk 177 0.00% 0.00% -system.ruby.Directory_Controller.BS_M.MemData 30 0.00% 0.00% -system.ruby.Directory_Controller.BM_M.MemData 11 0.00% 0.00% -system.ruby.Directory_Controller.B_M.MemData 1 0.00% 0.00% -system.ruby.Directory_Controller.BS_PM.CPUPrbResp 30 0.00% 0.00% -system.ruby.Directory_Controller.BS_PM.ProbeAcksComplete 30 0.00% 0.00% -system.ruby.Directory_Controller.BS_PM.MemData 1009 0.00% 0.00% -system.ruby.Directory_Controller.BM_PM.CPUPrbResp 11 0.00% 0.00% -system.ruby.Directory_Controller.BM_PM.ProbeAcksComplete 11 0.00% 0.00% -system.ruby.Directory_Controller.BM_PM.MemData 324 0.00% 0.00% -system.ruby.Directory_Controller.B_PM.CPUPrbResp 1 0.00% 0.00% -system.ruby.Directory_Controller.B_PM.ProbeAcksComplete 1 0.00% 0.00% -system.ruby.Directory_Controller.B_PM.MemData 176 0.00% 0.00% -system.ruby.Directory_Controller.BS_Pm.CPUPrbResp 1009 0.00% 0.00% -system.ruby.Directory_Controller.BS_Pm.ProbeAcksComplete 1009 0.00% 0.00% -system.ruby.Directory_Controller.BM_Pm.CPUPrbResp 324 0.00% 0.00% -system.ruby.Directory_Controller.BM_Pm.ProbeAcksComplete 324 0.00% 0.00% -system.ruby.Directory_Controller.B_Pm.CPUPrbResp 176 0.00% 0.00% -system.ruby.Directory_Controller.B_Pm.ProbeAcksComplete 176 0.00% 0.00% +system.ruby.Directory_Controller.BS_M.MemData 36 0.00% 0.00% +system.ruby.Directory_Controller.BM_M.MemData 13 0.00% 0.00% +system.ruby.Directory_Controller.B_M.MemData 12 0.00% 0.00% +system.ruby.Directory_Controller.BS_PM.CPUPrbResp 36 0.00% 0.00% +system.ruby.Directory_Controller.BS_PM.ProbeAcksComplete 36 0.00% 0.00% +system.ruby.Directory_Controller.BS_PM.MemData 1003 0.00% 0.00% +system.ruby.Directory_Controller.BM_PM.CPUPrbResp 14 0.00% 0.00% +system.ruby.Directory_Controller.BM_PM.ProbeAcksComplete 13 0.00% 0.00% +system.ruby.Directory_Controller.BM_PM.MemData 322 0.00% 0.00% +system.ruby.Directory_Controller.B_PM.CPUPrbResp 12 0.00% 0.00% +system.ruby.Directory_Controller.B_PM.ProbeAcksComplete 12 0.00% 0.00% +system.ruby.Directory_Controller.B_PM.MemData 165 0.00% 0.00% +system.ruby.Directory_Controller.BS_Pm.CPUPrbResp 1003 0.00% 0.00% +system.ruby.Directory_Controller.BS_Pm.ProbeAcksComplete 1003 0.00% 0.00% +system.ruby.Directory_Controller.BM_Pm.CPUPrbResp 321 0.00% 0.00% +system.ruby.Directory_Controller.BM_Pm.ProbeAcksComplete 322 0.00% 0.00% +system.ruby.Directory_Controller.B_Pm.CPUPrbResp 165 0.00% 0.00% +system.ruby.Directory_Controller.B_Pm.ProbeAcksComplete 165 0.00% 0.00% system.ruby.Directory_Controller.B.CoreUnblock 1551 0.00% 0.00% -system.ruby.LD.latency_hist_seqr::bucket_size 32 -system.ruby.LD.latency_hist_seqr::max_bucket 319 +system.ruby.LD.latency_hist_seqr::bucket_size 64 +system.ruby.LD.latency_hist_seqr::max_bucket 639 system.ruby.LD.latency_hist_seqr::samples 16335 -system.ruby.LD.latency_hist_seqr::mean 4.217447 -system.ruby.LD.latency_hist_seqr::gmean 2.103537 -system.ruby.LD.latency_hist_seqr::stdev 21.286370 -system.ruby.LD.latency_hist_seqr | 16160 98.93% 98.93% | 0 0.00% 98.93% | 0 0.00% 98.93% | 0 0.00% 98.93% | 0 0.00% 98.93% | 0 0.00% 98.93% | 166 1.02% 99.94% | 9 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.latency_hist_seqr::mean 4.314539 +system.ruby.LD.latency_hist_seqr::gmean 2.104196 +system.ruby.LD.latency_hist_seqr::stdev 22.794494 +system.ruby.LD.latency_hist_seqr | 16160 98.93% 98.93% | 0 0.00% 98.93% | 0 0.00% 98.93% | 166 1.02% 99.94% | 6 0.04% 99.98% | 1 0.01% 99.99% | 0 0.00% 99.99% | 0 0.00% 99.99% | 0 0.00% 99.99% | 2 0.01% 100.00% system.ruby.LD.latency_hist_seqr::total 16335 system.ruby.LD.latency_hist_coalsr::bucket_size 64 system.ruby.LD.latency_hist_coalsr::max_bucket 639 system.ruby.LD.latency_hist_coalsr::samples 9 -system.ruby.LD.latency_hist_coalsr::mean 133 -system.ruby.LD.latency_hist_coalsr::gmean 19.809210 -system.ruby.LD.latency_hist_coalsr::stdev 158.221364 -system.ruby.LD.latency_hist_coalsr | 5 55.56% 55.56% | 0 0.00% 55.56% | 0 0.00% 55.56% | 2 22.22% 77.78% | 0 0.00% 77.78% | 2 22.22% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.latency_hist_coalsr::mean 219.555556 +system.ruby.LD.latency_hist_coalsr::gmean 24.880500 +system.ruby.LD.latency_hist_coalsr::stdev 259.591078 +system.ruby.LD.latency_hist_coalsr | 5 55.56% 55.56% | 0 0.00% 55.56% | 0 0.00% 55.56% | 0 0.00% 55.56% | 0 0.00% 55.56% | 0 0.00% 55.56% | 1 11.11% 66.67% | 1 11.11% 77.78% | 2 22.22% 100.00% | 0 0.00% 100.00% system.ruby.LD.latency_hist_coalsr::total 9 -system.ruby.LD.hit_latency_hist_seqr::bucket_size 32 -system.ruby.LD.hit_latency_hist_seqr::max_bucket 319 +system.ruby.LD.hit_latency_hist_seqr::bucket_size 64 +system.ruby.LD.hit_latency_hist_seqr::max_bucket 639 system.ruby.LD.hit_latency_hist_seqr::samples 175 -system.ruby.LD.hit_latency_hist_seqr::mean 208.468571 -system.ruby.LD.hit_latency_hist_seqr::gmean 208.231054 -system.ruby.LD.hit_latency_hist_seqr::stdev 10.632194 -system.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 166 94.86% 94.86% | 9 5.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.hit_latency_hist_seqr::mean 217.531429 +system.ruby.LD.hit_latency_hist_seqr::gmean 214.409561 +system.ruby.LD.hit_latency_hist_seqr::stdev 50.482703 +system.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 166 94.86% 94.86% | 6 3.43% 98.29% | 1 0.57% 98.86% | 0 0.00% 98.86% | 0 0.00% 98.86% | 0 0.00% 98.86% | 2 1.14% 100.00% system.ruby.LD.hit_latency_hist_seqr::total 175 system.ruby.LD.miss_latency_hist_seqr::bucket_size 4 system.ruby.LD.miss_latency_hist_seqr::max_bucket 39 @@ -3005,34 +3015,34 @@ system.ruby.LD.miss_latency_hist_seqr::total 16160 system.ruby.LD.miss_latency_hist_coalsr::bucket_size 64 system.ruby.LD.miss_latency_hist_coalsr::max_bucket 639 system.ruby.LD.miss_latency_hist_coalsr::samples 9 -system.ruby.LD.miss_latency_hist_coalsr::mean 133 -system.ruby.LD.miss_latency_hist_coalsr::gmean 19.809210 -system.ruby.LD.miss_latency_hist_coalsr::stdev 158.221364 -system.ruby.LD.miss_latency_hist_coalsr | 5 55.56% 55.56% | 0 0.00% 55.56% | 0 0.00% 55.56% | 2 22.22% 77.78% | 0 0.00% 77.78% | 2 22.22% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.miss_latency_hist_coalsr::mean 219.555556 +system.ruby.LD.miss_latency_hist_coalsr::gmean 24.880500 +system.ruby.LD.miss_latency_hist_coalsr::stdev 259.591078 +system.ruby.LD.miss_latency_hist_coalsr | 5 55.56% 55.56% | 0 0.00% 55.56% | 0 0.00% 55.56% | 0 0.00% 55.56% | 0 0.00% 55.56% | 0 0.00% 55.56% | 1 11.11% 66.67% | 1 11.11% 77.78% | 2 22.22% 100.00% | 0 0.00% 100.00% system.ruby.LD.miss_latency_hist_coalsr::total 9 system.ruby.ST.latency_hist_seqr::bucket_size 64 system.ruby.ST.latency_hist_seqr::max_bucket 639 system.ruby.ST.latency_hist_seqr::samples 10412 -system.ruby.ST.latency_hist_seqr::mean 8.385709 -system.ruby.ST.latency_hist_seqr::gmean 2.308923 -system.ruby.ST.latency_hist_seqr::stdev 35.862445 -system.ruby.ST.latency_hist_seqr | 10090 96.91% 96.91% | 0 0.00% 96.91% | 0 0.00% 96.91% | 316 3.03% 99.94% | 3 0.03% 99.97% | 3 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.latency_hist_seqr::mean 8.469939 +system.ruby.ST.latency_hist_seqr::gmean 2.309412 +system.ruby.ST.latency_hist_seqr::stdev 36.833690 +system.ruby.ST.latency_hist_seqr | 10090 96.91% 96.91% | 0 0.00% 96.91% | 0 0.00% 96.91% | 314 3.02% 99.92% | 1 0.01% 99.93% | 5 0.05% 99.98% | 0 0.00% 99.98% | 0 0.00% 99.98% | 0 0.00% 99.98% | 2 0.02% 100.00% system.ruby.ST.latency_hist_seqr::total 10412 system.ruby.ST.latency_hist_coalsr::bucket_size 32 system.ruby.ST.latency_hist_coalsr::max_bucket 319 system.ruby.ST.latency_hist_coalsr::samples 16 -system.ruby.ST.latency_hist_coalsr::mean 124.937500 -system.ruby.ST.latency_hist_coalsr::gmean 15.775436 -system.ruby.ST.latency_hist_coalsr::stdev 128.013264 -system.ruby.ST.latency_hist_coalsr | 8 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 8 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.latency_hist_coalsr::mean 125.375000 +system.ruby.ST.latency_hist_coalsr::gmean 15.802815 +system.ruby.ST.latency_hist_coalsr::stdev 128.476133 +system.ruby.ST.latency_hist_coalsr | 8 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 7 43.75% 93.75% | 1 6.25% 100.00% | 0 0.00% 100.00% system.ruby.ST.latency_hist_coalsr::total 16 system.ruby.ST.hit_latency_hist_seqr::bucket_size 64 system.ruby.ST.hit_latency_hist_seqr::max_bucket 639 system.ruby.ST.hit_latency_hist_seqr::samples 322 -system.ruby.ST.hit_latency_hist_seqr::mean 208.484472 -system.ruby.ST.hit_latency_hist_seqr::gmean 208.014366 -system.ruby.ST.hit_latency_hist_seqr::stdev 16.327683 -system.ruby.ST.hit_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 316 98.14% 98.14% | 3 0.93% 99.07% | 3 0.93% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.hit_latency_hist_seqr::mean 211.208075 +system.ruby.ST.hit_latency_hist_seqr::gmean 209.444324 +system.ruby.ST.hit_latency_hist_seqr::stdev 38.157121 +system.ruby.ST.hit_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 314 97.52% 97.52% | 1 0.31% 97.83% | 5 1.55% 99.38% | 0 0.00% 99.38% | 0 0.00% 99.38% | 0 0.00% 99.38% | 2 0.62% 100.00% system.ruby.ST.hit_latency_hist_seqr::total 322 system.ruby.ST.miss_latency_hist_seqr::bucket_size 1 system.ruby.ST.miss_latency_hist_seqr::max_bucket 9 @@ -3044,42 +3054,42 @@ system.ruby.ST.miss_latency_hist_seqr::total 10090 system.ruby.ST.miss_latency_hist_coalsr::bucket_size 32 system.ruby.ST.miss_latency_hist_coalsr::max_bucket 319 system.ruby.ST.miss_latency_hist_coalsr::samples 16 -system.ruby.ST.miss_latency_hist_coalsr::mean 124.937500 -system.ruby.ST.miss_latency_hist_coalsr::gmean 15.775436 -system.ruby.ST.miss_latency_hist_coalsr::stdev 128.013264 -system.ruby.ST.miss_latency_hist_coalsr | 8 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 8 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.miss_latency_hist_coalsr::mean 125.375000 +system.ruby.ST.miss_latency_hist_coalsr::gmean 15.802815 +system.ruby.ST.miss_latency_hist_coalsr::stdev 128.476133 +system.ruby.ST.miss_latency_hist_coalsr | 8 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 7 43.75% 93.75% | 1 6.25% 100.00% | 0 0.00% 100.00% system.ruby.ST.miss_latency_hist_coalsr::total 16 system.ruby.ATOMIC.latency_hist_coalsr::bucket_size 64 system.ruby.ATOMIC.latency_hist_coalsr::max_bucket 639 system.ruby.ATOMIC.latency_hist_coalsr::samples 2 -system.ruby.ATOMIC.latency_hist_coalsr::mean 309.500000 -system.ruby.ATOMIC.latency_hist_coalsr::gmean 306.568100 -system.ruby.ATOMIC.latency_hist_coalsr::stdev 60.104076 +system.ruby.ATOMIC.latency_hist_coalsr::mean 317.500000 +system.ruby.ATOMIC.latency_hist_coalsr::gmean 314.366029 +system.ruby.ATOMIC.latency_hist_coalsr::stdev 62.932504 system.ruby.ATOMIC.latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 50.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ATOMIC.latency_hist_coalsr::total 2 system.ruby.ATOMIC.miss_latency_hist_coalsr::bucket_size 64 system.ruby.ATOMIC.miss_latency_hist_coalsr::max_bucket 639 system.ruby.ATOMIC.miss_latency_hist_coalsr::samples 2 -system.ruby.ATOMIC.miss_latency_hist_coalsr::mean 309.500000 -system.ruby.ATOMIC.miss_latency_hist_coalsr::gmean 306.568100 -system.ruby.ATOMIC.miss_latency_hist_coalsr::stdev 60.104076 +system.ruby.ATOMIC.miss_latency_hist_coalsr::mean 317.500000 +system.ruby.ATOMIC.miss_latency_hist_coalsr::gmean 314.366029 +system.ruby.ATOMIC.miss_latency_hist_coalsr::stdev 62.932504 system.ruby.ATOMIC.miss_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 50.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ATOMIC.miss_latency_hist_coalsr::total 2 system.ruby.IFETCH.latency_hist_seqr::bucket_size 64 system.ruby.IFETCH.latency_hist_seqr::max_bucket 639 system.ruby.IFETCH.latency_hist_seqr::samples 87095 -system.ruby.IFETCH.latency_hist_seqr::mean 4.462070 -system.ruby.IFETCH.latency_hist_seqr::gmean 2.116390 -system.ruby.IFETCH.latency_hist_seqr::stdev 22.434900 -system.ruby.IFETCH.latency_hist_seqr | 86061 98.81% 98.81% | 0 0.00% 98.81% | 0 0.00% 98.81% | 1011 1.16% 99.97% | 16 0.02% 99.99% | 7 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.latency_hist_seqr::mean 4.485148 +system.ruby.IFETCH.latency_hist_seqr::gmean 2.116532 +system.ruby.IFETCH.latency_hist_seqr::stdev 22.815865 +system.ruby.IFETCH.latency_hist_seqr | 86061 98.81% 98.81% | 0 0.00% 98.81% | 0 0.00% 98.81% | 1006 1.16% 99.97% | 11 0.01% 99.98% | 12 0.01% 99.99% | 2 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 3 0.00% 100.00% system.ruby.IFETCH.latency_hist_seqr::total 87095 system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 64 system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 639 system.ruby.IFETCH.hit_latency_hist_seqr::samples 1034 -system.ruby.IFETCH.hit_latency_hist_seqr::mean 208.442940 -system.ruby.IFETCH.hit_latency_hist_seqr::gmean 207.967489 -system.ruby.IFETCH.hit_latency_hist_seqr::stdev 16.443135 -system.ruby.IFETCH.hit_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1011 97.78% 97.78% | 16 1.55% 99.32% | 7 0.68% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.hit_latency_hist_seqr::mean 210.386847 +system.ruby.IFETCH.hit_latency_hist_seqr::gmean 209.145816 +system.ruby.IFETCH.hit_latency_hist_seqr::stdev 30.434753 +system.ruby.IFETCH.hit_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1006 97.29% 97.29% | 11 1.06% 98.36% | 12 1.16% 99.52% | 2 0.19% 99.71% | 0 0.00% 99.71% | 0 0.00% 99.71% | 3 0.29% 100.00% system.ruby.IFETCH.hit_latency_hist_seqr::total 1034 system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 4 system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 39 @@ -3156,18 +3166,18 @@ system.ruby.L2Cache.miss_mach_latency_hist_seqr::total 59 system.ruby.Directory.hit_mach_latency_hist_seqr::bucket_size 64 system.ruby.Directory.hit_mach_latency_hist_seqr::max_bucket 639 system.ruby.Directory.hit_mach_latency_hist_seqr::samples 1535 -system.ruby.Directory.hit_mach_latency_hist_seqr::mean 208.448208 -system.ruby.Directory.hit_mach_latency_hist_seqr::gmean 208.002202 -system.ruby.Directory.hit_mach_latency_hist_seqr::stdev 15.833423 -system.ruby.Directory.hit_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1506 98.11% 98.11% | 19 1.24% 99.35% | 10 0.65% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.hit_mach_latency_hist_seqr::mean 211.362215 +system.ruby.Directory.hit_mach_latency_hist_seqr::gmean 209.793806 +system.ruby.Directory.hit_mach_latency_hist_seqr::stdev 34.965177 +system.ruby.Directory.hit_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1490 97.07% 97.07% | 18 1.17% 98.24% | 18 1.17% 99.41% | 2 0.13% 99.54% | 0 0.00% 99.54% | 0 0.00% 99.54% | 7 0.46% 100.00% system.ruby.Directory.hit_mach_latency_hist_seqr::total 1535 system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::bucket_size 64 system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::max_bucket 639 system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::samples 3 -system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::mean 345.333333 -system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::gmean 345.301362 -system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::stdev 5.773503 -system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 3 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::mean 478.666667 +system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::gmean 470.839796 +system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::stdev 101.159939 +system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 33.33% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 2 66.67% 100.00% | 0 0.00% 100.00% system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::total 3 system.ruby.TCP.miss_mach_latency_hist_coalsr::bucket_size 1 system.ruby.TCP.miss_mach_latency_hist_coalsr::max_bucket 9 @@ -3177,13 +3187,13 @@ system.ruby.TCP.miss_mach_latency_hist_coalsr::gmean 1.377009 system.ruby.TCP.miss_mach_latency_hist_coalsr::stdev 0.877058 system.ruby.TCP.miss_mach_latency_hist_coalsr | 0 0.00% 0.00% | 8 61.54% 61.54% | 4 30.77% 92.31% | 0 0.00% 92.31% | 1 7.69% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.TCP.miss_mach_latency_hist_coalsr::total 13 -system.ruby.TCCdir.miss_mach_latency_hist_coalsr::bucket_size 32 -system.ruby.TCCdir.miss_mach_latency_hist_coalsr::max_bucket 319 +system.ruby.TCCdir.miss_mach_latency_hist_coalsr::bucket_size 64 +system.ruby.TCCdir.miss_mach_latency_hist_coalsr::max_bucket 639 system.ruby.TCCdir.miss_mach_latency_hist_coalsr::samples 11 -system.ruby.TCCdir.miss_mach_latency_hist_coalsr::mean 250.818182 -system.ruby.TCCdir.miss_mach_latency_hist_coalsr::gmean 250.757089 -system.ruby.TCCdir.miss_mach_latency_hist_coalsr::stdev 5.896070 -system.ruby.TCCdir.miss_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 10 90.91% 90.91% | 1 9.09% 100.00% | 0 0.00% 100.00% +system.ruby.TCCdir.miss_mach_latency_hist_coalsr::mean 287.363636 +system.ruby.TCCdir.miss_mach_latency_hist_coalsr::gmean 279.637814 +system.ruby.TCCdir.miss_mach_latency_hist_coalsr::stdev 78.345737 +system.ruby.TCCdir.miss_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 7 63.64% 63.64% | 2 18.18% 81.82% | 0 0.00% 81.82% | 1 9.09% 90.91% | 1 9.09% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.TCCdir.miss_mach_latency_hist_coalsr::total 11 system.ruby.LD.L1Cache.miss_type_mach_latency_hist_seqr::bucket_size 1 system.ruby.LD.L1Cache.miss_type_mach_latency_hist_seqr::max_bucket 9 @@ -3199,20 +3209,21 @@ system.ruby.LD.L2Cache.miss_type_mach_latency_hist_seqr::mean 20 system.ruby.LD.L2Cache.miss_type_mach_latency_hist_seqr::gmean 20.000000 system.ruby.LD.L2Cache.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 5 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.L2Cache.miss_type_mach_latency_hist_seqr::total 5 -system.ruby.LD.Directory.hit_type_mach_latency_hist_seqr::bucket_size 32 -system.ruby.LD.Directory.hit_type_mach_latency_hist_seqr::max_bucket 319 +system.ruby.LD.Directory.hit_type_mach_latency_hist_seqr::bucket_size 64 +system.ruby.LD.Directory.hit_type_mach_latency_hist_seqr::max_bucket 639 system.ruby.LD.Directory.hit_type_mach_latency_hist_seqr::samples 175 -system.ruby.LD.Directory.hit_type_mach_latency_hist_seqr::mean 208.468571 -system.ruby.LD.Directory.hit_type_mach_latency_hist_seqr::gmean 208.231054 -system.ruby.LD.Directory.hit_type_mach_latency_hist_seqr::stdev 10.632194 -system.ruby.LD.Directory.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 166 94.86% 94.86% | 9 5.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.Directory.hit_type_mach_latency_hist_seqr::mean 217.531429 +system.ruby.LD.Directory.hit_type_mach_latency_hist_seqr::gmean 214.409561 +system.ruby.LD.Directory.hit_type_mach_latency_hist_seqr::stdev 50.482703 +system.ruby.LD.Directory.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 166 94.86% 94.86% | 6 3.43% 98.29% | 1 0.57% 98.86% | 0 0.00% 98.86% | 0 0.00% 98.86% | 0 0.00% 98.86% | 2 1.14% 100.00% system.ruby.LD.Directory.hit_type_mach_latency_hist_seqr::total 175 system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::bucket_size 64 system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::max_bucket 639 system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::samples 2 -system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::mean 342 -system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::gmean 342.000000 -system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 2 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::mean 537 +system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::gmean 536.976722 +system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::stdev 7.071068 +system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 2 100.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::total 2 system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::bucket_size 1 system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::max_bucket 9 @@ -3222,13 +3233,13 @@ system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::gmean 2.297397 system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::stdev 0.894427 system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 4 80.00% 80.00% | 0 0.00% 80.00% | 1 20.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::total 5 -system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::bucket_size 32 -system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::max_bucket 319 +system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::bucket_size 64 +system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::max_bucket 639 system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::samples 2 -system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::mean 250.500000 -system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::gmean 250.487525 -system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::stdev 3.535534 -system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 2 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::mean 445 +system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::gmean 444.959549 +system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::stdev 8.485281 +system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 50.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::total 2 system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::bucket_size 1 system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::max_bucket 9 @@ -3240,10 +3251,10 @@ system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::total 10090 system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::bucket_size 64 system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::max_bucket 639 system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::samples 322 -system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::mean 208.484472 -system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::gmean 208.014366 -system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::stdev 16.327683 -system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 316 98.14% 98.14% | 3 0.93% 99.07% | 3 0.93% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::mean 211.208075 +system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::gmean 209.444324 +system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::stdev 38.157121 +system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 314 97.52% 97.52% | 1 0.31% 97.83% | 5 1.55% 99.38% | 0 0.00% 99.38% | 0 0.00% 99.38% | 0 0.00% 99.38% | 2 0.62% 100.00% system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::total 322 system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::bucket_size 1 system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::max_bucket 9 @@ -3255,24 +3266,24 @@ system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::total 8 system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::bucket_size 32 system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::max_bucket 319 system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::samples 8 -system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::mean 248.875000 -system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::gmean 248.864382 -system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::stdev 2.474874 -system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 8 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::mean 249.750000 +system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::gmean 249.728954 +system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::stdev 3.494894 +system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 7 87.50% 87.50% | 1 12.50% 100.00% | 0 0.00% 100.00% system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::total 8 system.ruby.ATOMIC.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::bucket_size 64 system.ruby.ATOMIC.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::max_bucket 639 system.ruby.ATOMIC.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::samples 1 -system.ruby.ATOMIC.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::mean 352 -system.ruby.ATOMIC.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::gmean 352.000000 +system.ruby.ATOMIC.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::mean 362 +system.ruby.ATOMIC.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::gmean 362.000000 system.ruby.ATOMIC.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::stdev nan system.ruby.ATOMIC.L1Cache_wCC.miss_type_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ATOMIC.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::total 1 system.ruby.ATOMIC.TCCdir.miss_type_mach_latency_hist_coalsr::bucket_size 32 system.ruby.ATOMIC.TCCdir.miss_type_mach_latency_hist_coalsr::max_bucket 319 system.ruby.ATOMIC.TCCdir.miss_type_mach_latency_hist_coalsr::samples 1 -system.ruby.ATOMIC.TCCdir.miss_type_mach_latency_hist_coalsr::mean 267 -system.ruby.ATOMIC.TCCdir.miss_type_mach_latency_hist_coalsr::gmean 267.000000 +system.ruby.ATOMIC.TCCdir.miss_type_mach_latency_hist_coalsr::mean 273 +system.ruby.ATOMIC.TCCdir.miss_type_mach_latency_hist_coalsr::gmean 273 system.ruby.ATOMIC.TCCdir.miss_type_mach_latency_hist_coalsr::stdev nan system.ruby.ATOMIC.TCCdir.miss_type_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% system.ruby.ATOMIC.TCCdir.miss_type_mach_latency_hist_coalsr::total 1 @@ -3293,10 +3304,10 @@ system.ruby.IFETCH.L2Cache.miss_type_mach_latency_hist_seqr::total 54 system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::bucket_size 64 system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::max_bucket 639 system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::samples 1034 -system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::mean 208.442940 -system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::gmean 207.967489 -system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::stdev 16.443135 -system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1011 97.78% 97.78% | 16 1.55% 99.32% | 7 0.68% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::mean 210.386847 +system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::gmean 209.145816 +system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::stdev 30.434753 +system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1006 97.29% 97.29% | 11 1.06% 98.36% | 12 1.16% 99.52% | 2 0.19% 99.71% | 0 0.00% 99.71% | 0 0.00% 99.71% | 3 0.29% 100.00% system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::total 1034 system.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist_seqr::bucket_size 1 system.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist_seqr::max_bucket 9 @@ -3331,8 +3342,8 @@ system.ruby.SQC_Controller.TCC_AckS 5 0.00% 0.00% system.ruby.SQC_Controller.I.Fetch 5 0.00% 0.00% system.ruby.SQC_Controller.S.Fetch 81 0.00% 0.00% system.ruby.SQC_Controller.I_S.TCC_AckS 5 0.00% 0.00% -system.ruby.TCCdir_Controller.RdBlk 54 0.00% 0.00% -system.ruby.TCCdir_Controller.RdBlkM 36 0.00% 0.00% +system.ruby.TCCdir_Controller.RdBlk 93 0.00% 0.00% +system.ruby.TCCdir_Controller.RdBlkM 37 0.00% 0.00% system.ruby.TCCdir_Controller.RdBlkS 5 0.00% 0.00% system.ruby.TCCdir_Controller.CPUPrbResp 14 0.00% 0.00% system.ruby.TCCdir_Controller.ProbeAcksComplete 13 0.00% 0.00% @@ -3357,7 +3368,7 @@ system.ruby.TCCdir_Controller.CP_O.CPUPrbResp 9 0.00% 0.00% system.ruby.TCCdir_Controller.CP_O.ProbeAcksComplete 9 0.00% 0.00% system.ruby.TCCdir_Controller.I_M.RdBlkM 22 0.00% 0.00% system.ruby.TCCdir_Controller.I_M.NB_AckM 9 0.00% 0.00% -system.ruby.TCCdir_Controller.I_ES.RdBlk 41 0.00% 0.00% +system.ruby.TCCdir_Controller.I_ES.RdBlk 79 0.00% 0.00% system.ruby.TCCdir_Controller.I_ES.NB_AckS 2 0.00% 0.00% system.ruby.TCCdir_Controller.I_S.NB_AckS 5 0.00% 0.00% system.ruby.TCCdir_Controller.BBS_S.CPUPrbResp 2 0.00% 0.00% @@ -3366,9 +3377,9 @@ system.ruby.TCCdir_Controller.BBM_M.CPUPrbResp 1 0.00% 0.00 system.ruby.TCCdir_Controller.BBM_M.ProbeAcksComplete 1 0.00% 0.00% system.ruby.TCCdir_Controller.BB_M.CoreUnblock 1 0.00% 0.00% system.ruby.TCCdir_Controller.BB_S.LastCoreUnblock 2 0.00% 0.00% -system.ruby.TCCdir_Controller.BBB_S.RdBlk 9 0.00% 0.00% +system.ruby.TCCdir_Controller.BBB_S.RdBlk 10 0.00% 0.00% system.ruby.TCCdir_Controller.BBB_S.CoreUnblock 7 0.00% 0.00% -system.ruby.TCCdir_Controller.BBB_M.RdBlkM 4 0.00% 0.00% +system.ruby.TCCdir_Controller.BBB_M.RdBlkM 5 0.00% 0.00% system.ruby.TCCdir_Controller.BBB_M.CoreUnblock 9 0.00% 0.00% system.ruby.TCP_Controller.Load | 4 44.44% 44.44% | 5 55.56% 100.00% system.ruby.TCP_Controller.Load::total 9 diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini index 0109ebfd6..5f60d059c 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini @@ -173,7 +173,7 @@ useIndirect=true [system.cpu0.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=4 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -531,7 +531,7 @@ pipelined=false [system.cpu0.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=1 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -734,7 +734,7 @@ useIndirect=true [system.cpu1.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=4 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -1092,7 +1092,7 @@ pipelined=false [system.cpu1.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=1 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -1272,7 +1272,7 @@ useIndirect=true [system.cpu2.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=4 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -1630,7 +1630,7 @@ pipelined=false [system.cpu2.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=1 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -1810,7 +1810,7 @@ useIndirect=true [system.cpu3.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=4 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -2168,7 +2168,7 @@ pipelined=false [system.cpu3.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=1 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -2247,7 +2247,7 @@ transition_latency=100000000 [system.l2c] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -2321,27 +2321,27 @@ system=system [system.physmem] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -2361,6 +2361,7 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 @@ -2370,7 +2371,7 @@ p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 page_policy=open_adaptive power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 @@ -2392,9 +2393,9 @@ tRTW=2500 tWR=15000 tWTR=7500 tXAW=30000 -tXP=0 +tXP=6000 tXPDLL=0 -tXS=0 +tXS=270000 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout index 64591e1c0..a478b858e 100755 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sp gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:30:06 -gem5 started Jul 21 2016 14:30:37 -gem5 executing on e108600-lin, pid 38681 +gem5 compiled Oct 13 2016 20:43:27 +gem5 started Oct 13 2016 20:47:19 +gem5 executing on e108600-lin, pid 17423 command line: /work/curdun01/gem5-external.hg/build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp Global frequency set at 1000000000000 ticks per second @@ -13,73 +13,73 @@ info: Entering event queue @ 0. Starting simulation... Init done [Iteration 1, Thread 1] Got lock [Iteration 1, Thread 1] Critical section done, previously next=0, now next=1 -[Iteration 1, Thread 2] Got lock -[Iteration 1, Thread 2] Critical section done, previously next=1, now next=2 [Iteration 1, Thread 3] Got lock -[Iteration 1, Thread 3] Critical section done, previously next=2, now next=3 +[Iteration 1, Thread 3] Critical section done, previously next=1, now next=3 +[Iteration 1, Thread 2] Got lock +[Iteration 1, Thread 2] Critical section done, previously next=3, now next=2 Iteration 1 completed -[Iteration 2, Thread 1] Got lock -[Iteration 2, Thread 1] Critical section done, previously next=0, now next=1 [Iteration 2, Thread 2] Got lock -[Iteration 2, Thread 2] Critical section done, previously next=1, now next=2 +[Iteration 2, Thread 2] Critical section done, previously next=0, now next=2 [Iteration 2, Thread 3] Got lock [Iteration 2, Thread 3] Critical section done, previously next=2, now next=3 +[Iteration 2, Thread 1] Got lock +[Iteration 2, Thread 1] Critical section done, previously next=3, now next=1 Iteration 2 completed [Iteration 3, Thread 3] Got lock [Iteration 3, Thread 3] Critical section done, previously next=0, now next=3 -[Iteration 3, Thread 2] Got lock -[Iteration 3, Thread 2] Critical section done, previously next=3, now next=2 [Iteration 3, Thread 1] Got lock -[Iteration 3, Thread 1] Critical section done, previously next=2, now next=1 +[Iteration 3, Thread 1] Critical section done, previously next=3, now next=1 +[Iteration 3, Thread 2] Got lock +[Iteration 3, Thread 2] Critical section done, previously next=1, now next=2 Iteration 3 completed -[Iteration 4, Thread 1] Got lock -[Iteration 4, Thread 1] Critical section done, previously next=0, now next=1 [Iteration 4, Thread 2] Got lock -[Iteration 4, Thread 2] Critical section done, previously next=1, now next=2 +[Iteration 4, Thread 2] Critical section done, previously next=0, now next=2 +[Iteration 4, Thread 1] Got lock +[Iteration 4, Thread 1] Critical section done, previously next=2, now next=1 [Iteration 4, Thread 3] Got lock -[Iteration 4, Thread 3] Critical section done, previously next=2, now next=3 +[Iteration 4, Thread 3] Critical section done, previously next=1, now next=3 Iteration 4 completed +[Iteration 5, Thread 2] Got lock +[Iteration 5, Thread 2] Critical section done, previously next=0, now next=2 [Iteration 5, Thread 1] Got lock -[Iteration 5, Thread 1] Critical section done, previously next=0, now next=1 +[Iteration 5, Thread 1] Critical section done, previously next=2, now next=1 [Iteration 5, Thread 3] Got lock [Iteration 5, Thread 3] Critical section done, previously next=1, now next=3 -[Iteration 5, Thread 2] Got lock -[Iteration 5, Thread 2] Critical section done, previously next=3, now next=2 Iteration 5 completed -[Iteration 6, Thread 2] Got lock -[Iteration 6, Thread 2] Critical section done, previously next=0, now next=2 -[Iteration 6, Thread 1] Got lock -[Iteration 6, Thread 1] Critical section done, previously next=2, now next=1 [Iteration 6, Thread 3] Got lock -[Iteration 6, Thread 3] Critical section done, previously next=1, now next=3 +[Iteration 6, Thread 3] Critical section done, previously next=0, now next=3 +[Iteration 6, Thread 1] Got lock +[Iteration 6, Thread 1] Critical section done, previously next=3, now next=1 +[Iteration 6, Thread 2] Got lock +[Iteration 6, Thread 2] Critical section done, previously next=1, now next=2 Iteration 6 completed -[Iteration 7, Thread 3] Got lock -[Iteration 7, Thread 3] Critical section done, previously next=0, now next=3 [Iteration 7, Thread 1] Got lock -[Iteration 7, Thread 1] Critical section done, previously next=3, now next=1 +[Iteration 7, Thread 1] Critical section done, previously next=0, now next=1 +[Iteration 7, Thread 3] Got lock +[Iteration 7, Thread 3] Critical section done, previously next=1, now next=3 [Iteration 7, Thread 2] Got lock -[Iteration 7, Thread 2] Critical section done, previously next=1, now next=2 +[Iteration 7, Thread 2] Critical section done, previously next=3, now next=2 Iteration 7 completed -[Iteration 8, Thread 3] Got lock -[Iteration 8, Thread 3] Critical section done, previously next=0, now next=3 [Iteration 8, Thread 1] Got lock -[Iteration 8, Thread 1] Critical section done, previously next=3, now next=1 +[Iteration 8, Thread 1] Critical section done, previously next=0, now next=1 +[Iteration 8, Thread 3] Got lock +[Iteration 8, Thread 3] Critical section done, previously next=1, now next=3 [Iteration 8, Thread 2] Got lock -[Iteration 8, Thread 2] Critical section done, previously next=1, now next=2 +[Iteration 8, Thread 2] Critical section done, previously next=3, now next=2 Iteration 8 completed [Iteration 9, Thread 2] Got lock [Iteration 9, Thread 2] Critical section done, previously next=0, now next=2 -[Iteration 9, Thread 1] Got lock -[Iteration 9, Thread 1] Critical section done, previously next=2, now next=1 [Iteration 9, Thread 3] Got lock -[Iteration 9, Thread 3] Critical section done, previously next=1, now next=3 +[Iteration 9, Thread 3] Critical section done, previously next=2, now next=3 +[Iteration 9, Thread 1] Got lock +[Iteration 9, Thread 1] Critical section done, previously next=3, now next=1 Iteration 9 completed +[Iteration 10, Thread 1] Got lock +[Iteration 10, Thread 1] Critical section done, previously next=0, now next=1 [Iteration 10, Thread 3] Got lock -[Iteration 10, Thread 3] Critical section done, previously next=0, now next=3 +[Iteration 10, Thread 3] Critical section done, previously next=1, now next=3 [Iteration 10, Thread 2] Got lock [Iteration 10, Thread 2] Critical section done, previously next=3, now next=2 -[Iteration 10, Thread 1] Got lock -[Iteration 10, Thread 1] Critical section done, previously next=2, now next=1 Iteration 10 completed PASSED :-) -Exiting @ tick 124523000 because target called exit() +Exiting @ tick 124830000 because target called exit() diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt index 10d3d1f6f..d8e803150 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt @@ -1,91 +1,91 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000124 # Number of seconds simulated -sim_ticks 123936000 # Number of ticks simulated -final_tick 123936000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000125 # Number of seconds simulated +sim_ticks 124830000 # Number of ticks simulated +final_tick 124830000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 188054 # Simulator instruction rate (inst/s) -host_op_rate 188053 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 20091950 # Simulator tick rate (ticks/s) -host_mem_usage 268856 # Number of bytes of host memory used -host_seconds 6.17 # Real time elapsed on the host -sim_insts 1159992 # Number of instructions simulated -sim_ops 1159992 # Number of ops (including micro ops) simulated +host_inst_rate 147575 # Simulator instruction rate (inst/s) +host_op_rate 147575 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 15906234 # Simulator tick rate (ticks/s) +host_mem_usage 266768 # Number of bytes of host memory used +host_seconds 7.85 # Real time elapsed on the host +sim_insts 1158143 # Number of instructions simulated +sim_ops 1158143 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 123936000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu0.inst 24064 # Number of bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 124830000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu0.inst 24000 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.data 10880 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 5696 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 1344 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 5888 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 1408 # Number of bytes read from this memory system.physmem.bytes_read::cpu2.inst 896 # Number of bytes read from this memory system.physmem.bytes_read::cpu2.data 960 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.inst 640 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.inst 896 # Number of bytes read from this memory system.physmem.bytes_read::cpu3.data 896 # Number of bytes read from this memory -system.physmem.bytes_read::total 45376 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 24064 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 5696 # Number of instructions bytes read from this memory +system.physmem.bytes_read::total 45824 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 24000 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 5888 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::cpu2.inst 896 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu3.inst 640 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 31296 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu0.inst 376 # Number of read requests responded to by this memory +system.physmem.bytes_inst_read::cpu3.inst 896 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 31680 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu0.inst 375 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.data 170 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 89 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 21 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 92 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 22 # Number of read requests responded to by this memory system.physmem.num_reads::cpu2.inst 14 # Number of read requests responded to by this memory system.physmem.num_reads::cpu2.data 15 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.inst 10 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.inst 14 # Number of read requests responded to by this memory system.physmem.num_reads::cpu3.data 14 # Number of read requests responded to by this memory -system.physmem.num_reads::total 709 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu0.inst 194164730 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 87787245 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 45959205 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 10844307 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 7229538 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 7745933 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.inst 5163956 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.data 7229538 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 366124451 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 194164730 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 45959205 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 7229538 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu3.inst 5163956 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 252517428 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 194164730 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 87787245 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 45959205 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 10844307 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 7229538 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 7745933 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.inst 5163956 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.data 7229538 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 366124451 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 709 # Number of read requests accepted +system.physmem.num_reads::total 716 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu0.inst 192261476 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 87158536 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 47168149 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 11279340 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 7177762 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 7690459 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.inst 7177762 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.data 7177762 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 367091244 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 192261476 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 47168149 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 7177762 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu3.inst 7177762 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 253785148 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 192261476 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 87158536 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 47168149 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 11279340 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 7177762 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 7690459 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.inst 7177762 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.data 7177762 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 367091244 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 716 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 709 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 716 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 45376 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 45824 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 45376 # Total read bytes from the system interface side +system.physmem.bytesReadSys 45824 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 120 # Per bank write bursts system.physmem.perBankRdBursts::1 44 # Per bank write bursts -system.physmem.perBankRdBursts::2 31 # Per bank write bursts -system.physmem.perBankRdBursts::3 62 # Per bank write bursts +system.physmem.perBankRdBursts::2 33 # Per bank write bursts +system.physmem.perBankRdBursts::3 63 # Per bank write bursts system.physmem.perBankRdBursts::4 69 # Per bank write bursts system.physmem.perBankRdBursts::5 28 # Per bank write bursts system.physmem.perBankRdBursts::6 19 # Per bank write bursts -system.physmem.perBankRdBursts::7 28 # Per bank write bursts +system.physmem.perBankRdBursts::7 27 # Per bank write bursts system.physmem.perBankRdBursts::8 7 # Per bank write bursts system.physmem.perBankRdBursts::9 31 # Per bank write bursts system.physmem.perBankRdBursts::10 23 # Per bank write bursts system.physmem.perBankRdBursts::11 13 # Per bank write bursts -system.physmem.perBankRdBursts::12 69 # Per bank write bursts -system.physmem.perBankRdBursts::13 45 # Per bank write bursts +system.physmem.perBankRdBursts::12 72 # Per bank write bursts +system.physmem.perBankRdBursts::13 47 # Per bank write bursts system.physmem.perBankRdBursts::14 19 # Per bank write bursts system.physmem.perBankRdBursts::15 101 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts @@ -106,14 +106,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 123701000 # Total gap between requests +system.physmem.totGap 124590000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 709 # Read request sizes (log2) +system.physmem.readPktSize::6 716 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -121,10 +121,10 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 430 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 203 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 55 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 16 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 416 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 218 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 59 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 18 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -217,211 +217,221 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 169 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 251.076923 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 166.451829 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 245.101340 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 63 37.28% 37.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 39 23.08% 60.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 28 16.57% 76.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 13 7.69% 84.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 8 4.73% 89.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 8 4.73% 94.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 3 1.78% 95.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1 0.59% 96.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 6 3.55% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 169 # Bytes accessed per row activation -system.physmem.totQLat 6766000 # Total ticks spent queuing -system.physmem.totMemAccLat 20059750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 3545000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9543.02 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 174 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 246.436782 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 161.758718 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 247.924177 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 67 38.51% 38.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 43 24.71% 63.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 26 14.94% 78.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 12 6.90% 85.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 7 4.02% 89.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 8 4.60% 93.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 3 1.72% 95.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2 1.15% 96.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 6 3.45% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 174 # Bytes accessed per row activation +system.physmem.totQLat 12446750 # Total ticks spent queuing +system.physmem.totMemAccLat 25871750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 3580000 # Total ticks spent in databus transfers +system.physmem.avgQLat 17383.73 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28293.02 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 366.12 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 36133.73 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 367.09 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 366.12 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 367.09 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 2.86 # Data bus utilization in percentage -system.physmem.busUtilRead 2.86 # Data bus utilization in percentage for reads +system.physmem.busUtil 2.87 # Data bus utilization in percentage +system.physmem.busUtilRead 2.87 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.23 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.26 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 528 # Number of row buffer hits during reads +system.physmem.readRowHits 530 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 74.47 # Row buffer hit rate for reads +system.physmem.readRowHitRate 74.02 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 174472.50 # Average gap between requests -system.physmem.pageHitRate 74.47 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 831600 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 453750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 2925000 # Energy for read commands per rank (pJ) +system.physmem.avgGap 174008.38 # Average gap between requests +system.physmem.pageHitRate 74.02 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 856800 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 432630 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 2877420 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 7628400 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 49377960 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 26918250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 88134960 # Total energy per rank (pJ) -system.physmem_0.averagePower 752.944352 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 47288500 # Time in different power states -system.physmem_0.memoryStateTime::REF 3900000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 68692500 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 408240 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 222750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 2184000 # Energy for read commands per rank (pJ) +system.physmem_0.refreshEnergy 9834240.000000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 6410790 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 304320 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 34392090 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 13115040 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 649140.000000 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 68872470 # Total energy per rank (pJ) +system.physmem_0.averagePower 551.730113 # Core power per rank (mW) +system.physmem_0.totalIdleTime 109416750 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 358500 # Time in different power states +system.physmem_0.memoryStateTime::REF 4166000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 403000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 34152000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 10318500 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 75432000 # Time in different power states +system.physmem_1.actEnergy 471240 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 227700 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 2234820 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 7628400 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 42901335 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 32591250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 85935975 # Total energy per rank (pJ) -system.physmem_1.averagePower 734.244489 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 54352750 # Time in different power states -system.physmem_1.memoryStateTime::REF 3900000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 59251250 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 123936000 # Cumulative time (in ticks) in various power states -system.cpu0.branchPred.lookups 98531 # Number of BP lookups -system.cpu0.branchPred.condPredicted 94014 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 1575 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 95788 # Number of BTB lookups +system.physmem_1.refreshEnergy 9834240.000000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 5188140 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 617280 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 32401650 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 11725440 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 3565380 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 66265890 # Total energy per rank (pJ) +system.physmem_1.averagePower 530.849075 # Core power per rank (mW) +system.physmem_1.totalIdleTime 111659250 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 1125500 # Time in different power states +system.physmem_1.memoryStateTime::REF 4172000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 10253750 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 30535250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 7679500 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 71064000 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 124830000 # Cumulative time (in ticks) in various power states +system.cpu0.branchPred.lookups 98509 # Number of BP lookups +system.cpu0.branchPred.condPredicted 93993 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 1599 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 95823 # Number of BTB lookups system.cpu0.branchPred.BTBHits 0 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu0.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 1142 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.usedRAS 1115 # Number of times the RAS was used to get a target. system.cpu0.branchPred.RASInCorrect 128 # Number of incorrect RAS predictions. -system.cpu0.branchPred.indirectLookups 95788 # Number of indirect predictor lookups. -system.cpu0.branchPred.indirectHits 88519 # Number of indirect target hits. -system.cpu0.branchPred.indirectMisses 7269 # Number of indirect misses. -system.cpu0.branchPredindirectMispredicted 1054 # Number of mispredicted indirect branches. +system.cpu0.branchPred.indirectLookups 95823 # Number of indirect predictor lookups. +system.cpu0.branchPred.indirectHits 88367 # Number of indirect target hits. +system.cpu0.branchPred.indirectMisses 7456 # Number of indirect misses. +system.cpu0.branchPredindirectMispredicted 1077 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.workload.num_syscalls 89 # Number of system calls -system.cpu0.pwrStateResidencyTicks::ON 123936000 # Cumulative time (in ticks) in various power states -system.cpu0.numCycles 247873 # number of cpu cycles simulated +system.cpu0.pwrStateResidencyTicks::ON 124830000 # Cumulative time (in ticks) in various power states +system.cpu0.numCycles 249661 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 23367 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 581451 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 98531 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 89661 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 193123 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 3449 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 66 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.icacheStallCycles 22650 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 581099 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 98509 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 89482 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 193985 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 3497 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 78 # Number of cycles fetch has spent waiting for tlb system.cpu0.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 2208 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingTrapStallCycles 2191 # Number of stall cycles due to pending traps system.cpu0.fetch.IcacheWaitRetryStallCycles 8 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 7997 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 861 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.CacheLines 7995 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 871 # Number of outstanding Icache misses that were squashed system.cpu0.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 220500 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 2.636966 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.261585 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::samples 220664 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 2.633411 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.264413 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 33425 15.16% 15.16% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 91538 41.51% 56.67% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 694 0.31% 56.99% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 1015 0.46% 57.45% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 497 0.23% 57.67% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 87060 39.48% 97.16% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 731 0.33% 97.49% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 514 0.23% 97.72% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 5026 2.28% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 33866 15.35% 15.35% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 91353 41.40% 56.75% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 668 0.30% 57.05% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 983 0.45% 57.49% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 516 0.23% 57.73% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 86959 39.41% 97.14% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 734 0.33% 97.47% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 482 0.22% 97.69% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 5103 2.31% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 220500 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.397506 # Number of branch fetches per cycle -system.cpu0.fetch.rate 2.345762 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 17843 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 18591 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 181526 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 816 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1724 # Number of cycles decode is squashing -system.cpu0.decode.DecodedInsts 563984 # Number of instructions handled by decode -system.cpu0.rename.SquashCycles 1724 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 18505 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 1935 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 15328 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 181668 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 1340 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 558880 # Number of instructions processed by rename +system.cpu0.fetch.rateDist::total 220664 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.394571 # Number of branch fetches per cycle +system.cpu0.fetch.rate 2.327552 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 17658 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 19166 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 181260 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 832 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1748 # Number of cycles decode is squashing +system.cpu0.decode.DecodedInsts 563638 # Number of instructions handled by decode +system.cpu0.rename.SquashCycles 1748 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 18349 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 2015 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 15764 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 181386 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 1402 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 558452 # Number of instructions processed by rename system.cpu0.rename.IQFullEvents 11 # Number of times rename has blocked due to IQ full system.cpu0.rename.LQFullEvents 11 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 869 # Number of times rename has blocked due to SQ full -system.cpu0.rename.RenamedOperands 382489 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 1113780 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 841332 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 2 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 363591 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 18898 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 1094 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 1121 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 5347 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 178321 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 90063 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 86944 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 86670 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 466208 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1118 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 462266 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 112 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 16406 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 13115 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 559 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 220500 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 2.096444 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.103875 # Number of insts issued each cycle +system.cpu0.rename.SQFullEvents 925 # Number of times rename has blocked due to SQ full +system.cpu0.rename.RenamedOperands 382172 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 1112707 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 840550 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 4 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 362927 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 19245 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1073 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 1102 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 5312 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 178069 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 89965 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 86828 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 86540 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 465662 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1094 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 461556 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 118 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 16666 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 13597 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 535 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 220664 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 2.091669 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.110492 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 36239 16.43% 16.43% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 4459 2.02% 18.46% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 88275 40.03% 58.49% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 87972 39.90% 98.39% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 1699 0.77% 99.16% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 988 0.45% 99.61% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 572 0.26% 99.87% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 195 0.09% 99.95% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 101 0.05% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 36803 16.68% 16.68% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 4402 1.99% 18.67% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 88094 39.92% 58.60% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 87764 39.77% 98.37% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 1699 0.77% 99.14% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 985 0.45% 99.58% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 568 0.26% 99.84% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 247 0.11% 99.95% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 102 0.05% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 220500 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 220664 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 126 38.77% 38.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 38.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 38.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 38.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 38.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 38.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 38.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 38.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 38.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 38.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 38.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 38.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 38.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 38.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 38.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 38.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 38.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 38.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 38.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 38.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 38.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 38.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 38.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 38.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 38.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 38.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 38.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 38.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 38.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 78 24.00% 62.77% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 121 37.23% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 129 39.09% 39.09% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 39.09% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 39.09% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 39.09% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 39.09% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 39.09% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 39.09% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 39.09% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 39.09% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 39.09% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 39.09% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 39.09% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 39.09% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 39.09% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 39.09% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 39.09% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 39.09% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 39.09% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 39.09% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 39.09% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 39.09% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 39.09% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 39.09% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 39.09% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 39.09% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 39.09% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 39.09% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 39.09% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 39.09% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 77 23.33% 62.42% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 124 37.58% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 195215 42.23% 42.23% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 194924 42.23% 42.23% # Type of FU issued system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.23% # Type of FU issued system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.23% # Type of FU issued system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.23% # Type of FU issued @@ -450,94 +460,94 @@ system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.23% # Ty system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.23% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.23% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.23% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 177740 38.45% 80.68% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 89311 19.32% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 177454 38.45% 80.68% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 89178 19.32% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 462266 # Type of FU issued -system.cpu0.iq.rate 1.864931 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 325 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.000703 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 1145469 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 483779 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 459725 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.FU_type_0::total 461556 # Type of FU issued +system.cpu0.iq.rate 1.848731 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 330 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.000715 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 1144224 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 483466 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 458888 # Number of integer instruction queue wakeup accesses system.cpu0.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 4 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_writes 8 # Number of floating instruction queue writes system.cpu0.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 462591 # Number of integer alu accesses +system.cpu0.iq.int_alu_accesses 461886 # Number of integer alu accesses system.cpu0.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 86430 # Number of loads that had data forwarded from stores +system.cpu0.iew.lsq.thread0.forwLoads 86265 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 2936 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 13 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 53 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 1864 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 3016 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 7 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 54 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 1932 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu0.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 11 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.cacheBlocked 12 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1724 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 1933 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 27 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 554898 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 123 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 178321 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 90063 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 1001 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 27 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewSquashCycles 1748 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 2015 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 29 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 554202 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 154 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 178069 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 89965 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 980 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 30 # Number of times the IQ has become full, causing a stall system.cpu0.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 53 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 229 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 1693 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 1922 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 460834 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 177384 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 1432 # Number of squashed instructions skipped in execute +system.cpu0.iew.memOrderViolationEvents 54 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 232 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 1714 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 1946 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 460023 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 177079 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 1533 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 87572 # number of nop insts executed -system.cpu0.iew.exec_refs 266499 # number of memory reference insts executed -system.cpu0.iew.exec_branches 91565 # Number of branches executed -system.cpu0.iew.exec_stores 89115 # Number of stores executed -system.cpu0.iew.exec_rate 1.859154 # Inst execution rate -system.cpu0.iew.wb_sent 460184 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 459725 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 272583 # num instructions producing a value -system.cpu0.iew.wb_consumers 276120 # num instructions consuming a value -system.cpu0.iew.wb_rate 1.854680 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.987190 # average fanout of values written-back -system.cpu0.commit.commitSquashedInsts 17076 # The number of squashed insts skipped by commit +system.cpu0.iew.exec_nop 87446 # number of nop insts executed +system.cpu0.iew.exec_refs 266047 # number of memory reference insts executed +system.cpu0.iew.exec_branches 91396 # Number of branches executed +system.cpu0.iew.exec_stores 88968 # Number of stores executed +system.cpu0.iew.exec_rate 1.842591 # Inst execution rate +system.cpu0.iew.wb_sent 459364 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 458888 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 272127 # num instructions producing a value +system.cpu0.iew.wb_consumers 275688 # num instructions consuming a value +system.cpu0.iew.wb_rate 1.838044 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.987083 # average fanout of values written-back +system.cpu0.commit.commitSquashedInsts 17379 # The number of squashed insts skipped by commit system.cpu0.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 1575 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 217161 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 2.476218 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 2.140669 # Number of insts commited each cycle +system.cpu0.commit.branchMispredicts 1599 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 217244 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 2.470687 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 2.142582 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 36214 16.68% 16.68% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 90367 41.61% 58.29% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 2049 0.94% 59.23% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 624 0.29% 59.52% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 510 0.23% 59.75% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 86212 39.70% 99.45% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 445 0.20% 99.66% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 289 0.13% 99.79% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 451 0.21% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 36715 16.90% 16.90% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 90144 41.49% 58.39% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 2018 0.93% 59.32% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 613 0.28% 59.61% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 486 0.22% 59.83% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 86051 39.61% 99.44% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 459 0.21% 99.65% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 294 0.14% 99.79% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 464 0.21% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 217161 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 537738 # Number of instructions committed -system.cpu0.commit.committedOps 537738 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 217244 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 536742 # Number of instructions committed +system.cpu0.commit.committedOps 536742 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 263584 # Number of memory references committed -system.cpu0.commit.loads 175385 # Number of loads committed +system.cpu0.commit.refs 263086 # Number of memory references committed +system.cpu0.commit.loads 175053 # Number of loads committed system.cpu0.commit.membars 84 # Number of memory barriers committed -system.cpu0.commit.branches 90086 # Number of branches committed +system.cpu0.commit.branches 89920 # Number of branches committed system.cpu0.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 361922 # Number of committed integer instructions. +system.cpu0.commit.int_insts 361258 # Number of committed integer instructions. system.cpu0.commit.function_calls 223 # Number of function calls committed. -system.cpu0.commit.op_class_0::No_OpClass 86818 16.15% 16.15% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 187252 34.82% 50.97% # Class of committed instruction +system.cpu0.commit.op_class_0::No_OpClass 86652 16.14% 16.14% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 186920 34.82% 50.97% # Class of committed instruction system.cpu0.commit.op_class_0::IntMult 0 0.00% 50.97% # Class of committed instruction system.cpu0.commit.op_class_0::IntDiv 0 0.00% 50.97% # Class of committed instruction system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 50.97% # Class of committed instruction @@ -566,2071 +576,2071 @@ system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 50.97% system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 50.97% # Class of committed instruction system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 50.97% # Class of committed instruction system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 50.97% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 175469 32.63% 83.60% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 88199 16.40% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 175137 32.63% 83.60% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 88033 16.40% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 537738 # Class of committed instruction -system.cpu0.commit.bw_lim_events 451 # number cycles where commit BW limit reached -system.cpu0.rob.rob_reads 770363 # The number of ROB reads -system.cpu0.rob.rob_writes 1113018 # The number of ROB writes -system.cpu0.timesIdled 321 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 27373 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.committedInsts 450836 # Number of Instructions Simulated -system.cpu0.committedOps 450836 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 0.549807 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 0.549807 # CPI: Total CPI of All Threads -system.cpu0.ipc 1.818819 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 1.818819 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 823745 # number of integer regfile reads -system.cpu0.int_regfile_writes 371341 # number of integer regfile writes +system.cpu0.commit.op_class_0::total 536742 # Class of committed instruction +system.cpu0.commit.bw_lim_events 464 # number cycles where commit BW limit reached +system.cpu0.rob.rob_reads 769740 # The number of ROB reads +system.cpu0.rob.rob_writes 1111721 # The number of ROB writes +system.cpu0.timesIdled 320 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 28997 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.committedInsts 450006 # Number of Instructions Simulated +system.cpu0.committedOps 450006 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 0.554795 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 0.554795 # CPI: Total CPI of All Threads +system.cpu0.ipc 1.802468 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 1.802468 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 822274 # number of integer regfile reads +system.cpu0.int_regfile_writes 370684 # number of integer regfile writes system.cpu0.fp_regfile_reads 192 # number of floating regfile reads -system.cpu0.misc_regfile_reads 268638 # number of misc regfile reads +system.cpu0.misc_regfile_reads 268168 # number of misc regfile reads system.cpu0.misc_regfile_writes 564 # number of misc regfile writes -system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 123936000 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 124830000 # Cumulative time (in ticks) in various power states system.cpu0.dcache.tags.replacements 2 # number of replacements -system.cpu0.dcache.tags.tagsinuse 142.669467 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 177790 # Total number of references to valid blocks. +system.cpu0.dcache.tags.tagsinuse 142.144997 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 177494 # Total number of references to valid blocks. system.cpu0.dcache.tags.sampled_refs 172 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 1033.662791 # Average number of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 1031.941860 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 142.669467 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.278651 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.278651 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 142.144997 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.277627 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.277627 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 170 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 143 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 0.332031 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 716504 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 716504 # Number of data accesses -system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 123936000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.ReadReq_hits::cpu0.data 90267 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 90267 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 87606 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 87606 # number of WriteReq hits -system.cpu0.dcache.SwapReq_hits::cpu0.data 22 # number of SwapReq hits -system.cpu0.dcache.SwapReq_hits::total 22 # number of SwapReq hits -system.cpu0.dcache.demand_hits::cpu0.data 177873 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 177873 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 177873 # number of overall hits -system.cpu0.dcache.overall_hits::total 177873 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 580 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 580 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 551 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 551 # number of WriteReq misses -system.cpu0.dcache.SwapReq_misses::cpu0.data 20 # number of SwapReq misses -system.cpu0.dcache.SwapReq_misses::total 20 # number of SwapReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1131 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1131 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1131 # number of overall misses -system.cpu0.dcache.overall_misses::total 1131 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 15004000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 15004000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 35761990 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 35761990 # number of WriteReq miss cycles -system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 487500 # number of SwapReq miss cycles -system.cpu0.dcache.SwapReq_miss_latency::total 487500 # number of SwapReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 50765990 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 50765990 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 50765990 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 50765990 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 90847 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 90847 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 88157 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 88157 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.tags.tag_accesses 715284 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 715284 # Number of data accesses +system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 124830000 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.ReadReq_hits::cpu0.data 90136 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 90136 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 87436 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 87436 # number of WriteReq hits +system.cpu0.dcache.SwapReq_hits::cpu0.data 24 # number of SwapReq hits +system.cpu0.dcache.SwapReq_hits::total 24 # number of SwapReq hits +system.cpu0.dcache.demand_hits::cpu0.data 177572 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 177572 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 177572 # number of overall hits +system.cpu0.dcache.overall_hits::total 177572 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 571 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 571 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 555 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 555 # number of WriteReq misses +system.cpu0.dcache.SwapReq_misses::cpu0.data 18 # number of SwapReq misses +system.cpu0.dcache.SwapReq_misses::total 18 # number of SwapReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1126 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1126 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1126 # number of overall misses +system.cpu0.dcache.overall_misses::total 1126 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 16338000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 16338000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 35699989 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 35699989 # number of WriteReq miss cycles +system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 501500 # number of SwapReq miss cycles +system.cpu0.dcache.SwapReq_miss_latency::total 501500 # number of SwapReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 52037989 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 52037989 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 52037989 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 52037989 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 90707 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 90707 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 87991 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 87991 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 179004 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 179004 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 179004 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 179004 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.006384 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.006384 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.006250 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.006250 # miss rate for WriteReq accesses -system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.476190 # miss rate for SwapReq accesses -system.cpu0.dcache.SwapReq_miss_rate::total 0.476190 # miss rate for SwapReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006318 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.006318 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006318 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.006318 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 25868.965517 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 25868.965517 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 64903.793103 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 64903.793103 # average WriteReq miss latency -system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 24375 # average SwapReq miss latency -system.cpu0.dcache.SwapReq_avg_miss_latency::total 24375 # average SwapReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 44885.932803 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 44885.932803 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 44885.932803 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 44885.932803 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 832 # number of cycles access was blocked +system.cpu0.dcache.demand_accesses::cpu0.data 178698 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 178698 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 178698 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 178698 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.006295 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.006295 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.006307 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.006307 # miss rate for WriteReq accesses +system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.428571 # miss rate for SwapReq accesses +system.cpu0.dcache.SwapReq_miss_rate::total 0.428571 # miss rate for SwapReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006301 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.006301 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006301 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.006301 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 28612.959720 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 28612.959720 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 64324.304505 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 64324.304505 # average WriteReq miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 27861.111111 # average SwapReq miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency::total 27861.111111 # average SwapReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 46214.910302 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 46214.910302 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 46214.910302 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 46214.910302 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 885 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 22 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 21 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 37.818182 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 42.142857 # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks system.cpu0.dcache.writebacks::total 1 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 378 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 378 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 383 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 383 # number of WriteReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 761 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 761 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 761 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 761 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 369 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 369 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 385 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 385 # number of WriteReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 754 # number of demand (read+write) MSHR hits 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40302.702703 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 40302.702703 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 40302.702703 # average overall mshr miss latency -system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 123936000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.tags.replacements 413 # number of replacements -system.cpu0.icache.tags.tagsinuse 250.106503 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 7058 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 712 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 9.912921 # Average number of references to valid blocks. +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 170 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 170 # number of WriteReq MSHR misses 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WriteReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 26861.111111 # average SwapReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 26861.111111 # average SwapReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 42125 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 42125 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 42125 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 42125 # average overall mshr miss latency +system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 124830000 # Cumulative time (in ticks) in various power states +system.cpu0.icache.tags.replacements 393 # number of replacements +system.cpu0.icache.tags.tagsinuse 248.700617 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 7078 # Total number of references to valid blocks. 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demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 7997 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 7997 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 7997 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.117419 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.117419 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.117419 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.117419 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.117419 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.117419 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 47117.678381 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 47117.678381 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 47117.678381 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 47117.678381 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 47117.678381 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 47117.678381 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 117 # number of cycles access was blocked +system.cpu0.icache.tags.occ_blocks::cpu0.inst 248.700617 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.485743 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.485743 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_task_id_blocks::1024 302 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 70 # Occupied blocks per task id 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47775500 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 7995 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 7995 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 7995 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 7995 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 7995 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 7995 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.114697 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.114697 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.114697 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.114697 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.114697 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.114697 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 52099.781897 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 52099.781897 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 52099.781897 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 52099.781897 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 52099.781897 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 52099.781897 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 151 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 4 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 29.250000 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 37.750000 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.writebacks::writebacks 413 # number of writebacks -system.cpu0.icache.writebacks::total 413 # number of writebacks -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 226 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 226 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 226 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 226 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 226 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 226 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 713 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 713 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 713 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 713 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 713 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 713 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 34164500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 34164500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 34164500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 34164500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 34164500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 34164500 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.089158 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.089158 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.089158 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.089158 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.089158 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.089158 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 47916.549790 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 47916.549790 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 47916.549790 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 47916.549790 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 47916.549790 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 47916.549790 # average overall mshr miss latency -system.cpu1.branchPred.lookups 73042 # Number of BP lookups -system.cpu1.branchPred.condPredicted 65659 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 2238 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 64943 # Number of BTB lookups +system.cpu0.icache.writebacks::writebacks 393 # number of writebacks +system.cpu0.icache.writebacks::total 393 # number of writebacks +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 221 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 221 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 221 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 221 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 221 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 221 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 696 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 696 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 696 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 696 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 696 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 696 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 36615000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 36615000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 36615000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 36615000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 36615000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 36615000 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.087054 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.087054 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.087054 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.087054 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.087054 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.087054 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 52607.758621 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 52607.758621 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 52607.758621 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 52607.758621 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 52607.758621 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 52607.758621 # average overall mshr miss latency +system.cpu1.branchPred.lookups 69942 # Number of BP lookups +system.cpu1.branchPred.condPredicted 62611 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 2168 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 62876 # Number of BTB lookups system.cpu1.branchPred.BTBHits 0 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu1.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 1989 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.usedRAS 1880 # Number of times the RAS was used to get a target. system.cpu1.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions. -system.cpu1.branchPred.indirectLookups 64943 # Number of indirect predictor lookups. -system.cpu1.branchPred.indirectHits 55241 # Number of indirect target hits. -system.cpu1.branchPred.indirectMisses 9702 # Number of indirect misses. -system.cpu1.branchPredindirectMispredicted 1128 # Number of mispredicted indirect branches. -system.cpu1.pwrStateResidencyTicks::ON 123936000 # Cumulative time (in ticks) in various power states -system.cpu1.numCycles 192502 # number of cpu cycles simulated +system.cpu1.branchPred.indirectLookups 62876 # Number of indirect predictor lookups. +system.cpu1.branchPred.indirectHits 52518 # Number of indirect target hits. +system.cpu1.branchPred.indirectMisses 10358 # Number of indirect misses. +system.cpu1.branchPredindirectMispredicted 1122 # Number of mispredicted indirect branches. +system.cpu1.pwrStateResidencyTicks::ON 124830000 # Cumulative time (in ticks) in various power states +system.cpu1.numCycles 191834 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 33710 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 406560 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 73042 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 57230 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 148689 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 4633 # Number of cycles fetch has spent squashing -system.cpu1.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.icacheStallCycles 35275 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 386727 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 69942 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 54398 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 146033 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 4493 # Number of cycles fetch has spent squashing +system.cpu1.fetch.MiscStallCycles 6 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu1.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from -system.cpu1.fetch.PendingTrapStallCycles 1669 # Number of stall cycles due to pending traps -system.cpu1.fetch.IcacheWaitRetryStallCycles 15 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 22180 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 918 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 186413 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 2.180964 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.381342 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.PendingTrapStallCycles 1374 # Number of stall cycles due to pending traps +system.cpu1.fetch.IcacheWaitRetryStallCycles 38 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 23469 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 905 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 184982 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 2.090620 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.368236 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 54977 29.49% 29.49% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 63721 34.18% 63.67% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 5493 2.95% 66.62% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 3499 1.88% 68.50% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 651 0.35% 68.85% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 47493 25.48% 94.32% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 995 0.53% 94.86% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 1355 0.73% 95.59% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 8229 4.41% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 58784 31.78% 31.78% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 61509 33.25% 65.03% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 6216 3.36% 68.39% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 3423 1.85% 70.24% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 694 0.38% 70.62% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 43897 23.73% 94.35% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 1064 0.58% 94.92% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 1288 0.70% 95.62% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 8107 4.38% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 186413 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.379435 # Number of branch fetches per cycle -system.cpu1.fetch.rate 2.111978 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 22012 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 48189 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 110683 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 3203 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 2316 # Number of cycles decode is squashing -system.cpu1.decode.DecodedInsts 375249 # Number of instructions handled by decode -system.cpu1.rename.SquashCycles 2316 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 23003 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 21046 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 13565 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 110960 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 15513 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 369118 # Number of instructions processed by rename -system.cpu1.rename.IQFullEvents 12808 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 18 # Number of times rename has blocked due to LQ full +system.cpu1.fetch.rateDist::total 184982 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.364596 # Number of branch fetches per cycle +system.cpu1.fetch.rate 2.015946 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 21795 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 53545 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 103882 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 3504 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 2246 # Number of cycles decode is squashing +system.cpu1.decode.DecodedInsts 357234 # Number of instructions handled by decode +system.cpu1.rename.SquashCycles 2246 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 22757 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 24349 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 13357 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 104467 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 17796 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 350958 # Number of instructions processed by rename +system.cpu1.rename.IQFullEvents 15108 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 17 # Number of times rename has blocked due to LQ full system.cpu1.rename.FullRegisterEvents 3 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 260404 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 717496 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 555302 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 32 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 234261 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 26143 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 1622 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 1759 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 20875 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 105786 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 51568 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 49714 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 45358 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 305985 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 5880 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 304555 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 84 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 23105 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 18122 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 1124 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 186413 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 1.633765 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.368784 # Number of insts issued each cycle +system.cpu1.rename.RenamedOperands 246923 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 678000 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 525614 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 22 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 220975 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 25948 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 1579 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 1706 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 23252 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 99419 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 48107 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 46982 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 41894 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 289725 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 6510 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 288968 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 96 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 22905 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 18076 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 1082 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 184982 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 1.562141 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.375121 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 59464 31.90% 31.90% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 19554 10.49% 42.39% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 50315 26.99% 69.38% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 50093 26.87% 96.25% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 3572 1.92% 98.17% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1698 0.91% 99.08% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 1008 0.54% 99.62% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 406 0.22% 99.84% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 303 0.16% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 62949 34.03% 34.03% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 21563 11.66% 45.69% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 46877 25.34% 71.03% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 46716 25.25% 96.28% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 3504 1.89% 98.18% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1701 0.92% 99.10% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 999 0.54% 99.64% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 396 0.21% 99.85% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 277 0.15% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 186413 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 184982 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 182 38.89% 38.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 38.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 38.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 38.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 38.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 38.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 38.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 38.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 38.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 38.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 38.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 38.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 38.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 38.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 38.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 38.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 38.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 38.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 38.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 38.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 38.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 38.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 38.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 38.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 38.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 38.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 38.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 38.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 38.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 58 12.39% 51.28% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 228 48.72% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 191 40.04% 40.04% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 40.04% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 40.04% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 40.04% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 40.04% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 40.04% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 40.04% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 40.04% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 40.04% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 40.04% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 40.04% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 40.04% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 40.04% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 40.04% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 40.04% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 40.04% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 40.04% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 40.04% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 40.04% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 40.04% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 40.04% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 40.04% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 40.04% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 40.04% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 40.04% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 40.04% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 40.04% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.04% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 40.04% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 60 12.58% 52.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 226 47.38% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 145063 47.63% 47.63% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 0 0.00% 47.63% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.63% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.63% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.63% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.63% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.63% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.63% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.63% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.63% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.63% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.63% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.63% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.63% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 47.63% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.63% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.63% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 47.63% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 47.63% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.63% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.63% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.63% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.63% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.63% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.63% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 47.63% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.63% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.63% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.63% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 108861 35.74% 83.38% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 50631 16.62% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 138690 47.99% 47.99% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 0 0.00% 47.99% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.99% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.99% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.99% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.99% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.99% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.99% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.99% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.99% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.99% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.99% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.99% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.99% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 47.99% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.99% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.99% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 47.99% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 47.99% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.99% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.99% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.99% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.99% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.99% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.99% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 47.99% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.99% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.99% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.99% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 103154 35.70% 83.69% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 47124 16.31% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 304555 # Type of FU issued -system.cpu1.iq.rate 1.582087 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 468 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.001537 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 796075 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 334945 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 300973 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.FU_type_0::total 288968 # Type of FU issued +system.cpu1.iq.rate 1.506344 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 477 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.001651 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 763491 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 319139 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 285378 # Number of integer instruction queue wakeup accesses system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 64 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_writes 44 # Number of floating instruction queue writes system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 305023 # Number of integer alu accesses +system.cpu1.iq.int_alu_accesses 289445 # Number of integer alu accesses system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 45252 # Number of loads that had data forwarded from stores +system.cpu1.iew.lsq.thread0.forwLoads 41785 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 4194 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 25 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 39 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 2536 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 4131 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 40 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 43 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 2566 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu1.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu1.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 2316 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 6366 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 55 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 362764 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 272 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 105786 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 51568 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 1528 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 40 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewSquashCycles 2246 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 7047 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 53 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 344310 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 276 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 99419 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 48107 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 1464 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 36 # Number of times the IQ has become full, causing a stall system.cpu1.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 39 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 443 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 2397 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 2840 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 302276 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 104291 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 2279 # Number of squashed instructions skipped in execute +system.cpu1.iew.memOrderViolationEvents 43 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 462 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 2268 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 2730 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 286645 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 97925 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 2323 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 50899 # number of nop insts executed -system.cpu1.iew.exec_refs 154635 # number of memory reference insts executed -system.cpu1.iew.exec_branches 61121 # Number of branches executed -system.cpu1.iew.exec_stores 50344 # Number of stores executed -system.cpu1.iew.exec_rate 1.570249 # Inst execution rate -system.cpu1.iew.wb_sent 301460 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 300973 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 172395 # num instructions producing a value -system.cpu1.iew.wb_consumers 179828 # num instructions consuming a value -system.cpu1.iew.wb_rate 1.563480 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.958666 # average fanout of values written-back -system.cpu1.commit.commitSquashedInsts 24140 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 4756 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 2238 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 181815 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 1.862272 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 2.110451 # Number of insts commited each cycle +system.cpu1.iew.exec_nop 48075 # number of nop insts executed +system.cpu1.iew.exec_refs 144750 # number of memory reference insts executed +system.cpu1.iew.exec_branches 58305 # Number of branches executed +system.cpu1.iew.exec_stores 46825 # Number of stores executed +system.cpu1.iew.exec_rate 1.494235 # Inst execution rate +system.cpu1.iew.wb_sent 285841 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 285378 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 162569 # num instructions producing a value +system.cpu1.iew.wb_consumers 170014 # num instructions consuming a value +system.cpu1.iew.wb_rate 1.487630 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.956209 # average fanout of values written-back +system.cpu1.commit.commitSquashedInsts 23932 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 5428 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 2168 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 180468 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 1.775063 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 2.087699 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 63682 35.03% 35.03% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 57506 31.63% 66.65% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 5445 2.99% 69.65% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 5412 2.98% 72.63% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1312 0.72% 73.35% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 45472 25.01% 98.36% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 770 0.42% 98.78% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 999 0.55% 99.33% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1217 0.67% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 67886 37.62% 37.62% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 54714 30.32% 67.93% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 5489 3.04% 70.98% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 6162 3.41% 74.39% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1291 0.72% 75.11% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 41971 23.26% 98.36% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 718 0.40% 98.76% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 1059 0.59% 99.35% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1178 0.65% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 181815 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 338589 # Number of instructions committed -system.cpu1.commit.committedOps 338589 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 180468 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 320342 # Number of instructions committed +system.cpu1.commit.committedOps 320342 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 150624 # Number of memory references committed -system.cpu1.commit.loads 101592 # Number of loads committed -system.cpu1.commit.membars 4041 # Number of memory barriers committed -system.cpu1.commit.branches 59040 # Number of branches committed +system.cpu1.commit.refs 140829 # Number of memory references committed +system.cpu1.commit.loads 95288 # Number of loads committed +system.cpu1.commit.membars 4715 # Number of memory barriers committed +system.cpu1.commit.branches 56221 # Number of branches committed system.cpu1.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 231783 # Number of committed integer instructions. +system.cpu1.commit.int_insts 219172 # Number of committed integer instructions. system.cpu1.commit.function_calls 322 # Number of function calls committed. -system.cpu1.commit.op_class_0::No_OpClass 49829 14.72% 14.72% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 134095 39.60% 54.32% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 0 0.00% 54.32% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 0 0.00% 54.32% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 54.32% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 54.32% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 54.32% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 54.32% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 54.32% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 54.32% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 54.32% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 54.32% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 54.32% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 54.32% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 54.32% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 54.32% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 54.32% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 54.32% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 54.32% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 54.32% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 54.32% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 54.32% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 54.32% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 54.32% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 54.32% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 54.32% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 54.32% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 54.32% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 54.32% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 54.32% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 105633 31.20% 85.52% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 49032 14.48% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::No_OpClass 47012 14.68% 14.68% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 127786 39.89% 54.57% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 0 0.00% 54.57% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 0 0.00% 54.57% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 54.57% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 54.57% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 54.57% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 54.57% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 54.57% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 54.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 54.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 54.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 54.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 54.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 54.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 54.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 54.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 54.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 54.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 54.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 54.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 54.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 54.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 54.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 54.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 54.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 54.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 54.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 54.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 54.57% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 100003 31.22% 85.78% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 45541 14.22% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 338589 # Class of committed instruction -system.cpu1.commit.bw_lim_events 1217 # number cycles where commit BW limit reached -system.cpu1.rob.rob_reads 542741 # The number of ROB reads -system.cpu1.rob.rob_writes 730091 # The number of ROB writes -system.cpu1.timesIdled 236 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 6089 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 47433 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 284719 # Number of Instructions Simulated -system.cpu1.committedOps 284719 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 0.676112 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 0.676112 # CPI: Total CPI of All Threads -system.cpu1.ipc 1.479044 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 1.479044 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 527704 # number of integer regfile reads -system.cpu1.int_regfile_writes 245054 # number of integer regfile writes +system.cpu1.commit.op_class_0::total 320342 # Class of committed instruction +system.cpu1.commit.bw_lim_events 1178 # number cycles where commit BW limit reached +system.cpu1.rob.rob_reads 522978 # The number of ROB reads +system.cpu1.rob.rob_writes 693117 # The number of ROB writes +system.cpu1.timesIdled 233 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 6852 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 49387 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 268615 # Number of Instructions Simulated +system.cpu1.committedOps 268615 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 0.714160 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 0.714160 # CPI: Total CPI of All Threads +system.cpu1.ipc 1.400247 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 1.400247 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 497951 # number of integer regfile reads +system.cpu1.int_regfile_writes 231611 # number of integer regfile writes system.cpu1.fp_regfile_writes 64 # number of floating regfile writes -system.cpu1.misc_regfile_reads 156484 # number of misc regfile reads +system.cpu1.misc_regfile_reads 146596 # number of misc regfile reads system.cpu1.misc_regfile_writes 648 # number of misc regfile writes -system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 123936000 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 124830000 # Cumulative time (in ticks) in various power states system.cpu1.dcache.tags.replacements 0 # number of replacements -system.cpu1.dcache.tags.tagsinuse 26.869792 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 56025 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 1931.896552 # Average number of references to valid blocks. +system.cpu1.dcache.tags.tagsinuse 26.433606 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 52423 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 30 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 1747.433333 # Average number of references to valid blocks. system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 26.869792 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.052480 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.052480 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 27 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 432447 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 432447 # Number of data accesses -system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 123936000 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.ReadReq_hits::cpu1.data 58508 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 58508 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 48814 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 48814 # number of WriteReq hits -system.cpu1.dcache.SwapReq_hits::cpu1.data 11 # number of SwapReq hits -system.cpu1.dcache.SwapReq_hits::total 11 # number of SwapReq hits -system.cpu1.dcache.demand_hits::cpu1.data 107322 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 107322 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 107322 # number of overall hits -system.cpu1.dcache.overall_hits::total 107322 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 507 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 507 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 149 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 149 # number of WriteReq misses -system.cpu1.dcache.SwapReq_misses::cpu1.data 58 # number of SwapReq misses -system.cpu1.dcache.SwapReq_misses::total 58 # number of SwapReq misses -system.cpu1.dcache.demand_misses::cpu1.data 656 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 656 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 656 # number of overall misses -system.cpu1.dcache.overall_misses::total 656 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 4815500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 4815500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3532500 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 3532500 # number of WriteReq miss cycles -system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 364000 # number of SwapReq miss cycles -system.cpu1.dcache.SwapReq_miss_latency::total 364000 # number of SwapReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 8348000 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 8348000 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 8348000 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 8348000 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 59015 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 59015 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 48963 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 48963 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_accesses::cpu1.data 69 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_accesses::total 69 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 107978 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 107978 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 107978 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 107978 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.008591 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.008591 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.003043 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.003043 # miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.840580 # miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_miss_rate::total 0.840580 # miss rate for SwapReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.006075 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.006075 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.006075 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.006075 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 9498.027613 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 9498.027613 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 23708.053691 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 23708.053691 # average WriteReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 6275.862069 # average SwapReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency::total 6275.862069 # average SwapReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 12725.609756 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 12725.609756 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 12725.609756 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 12725.609756 # average overall miss latency +system.cpu1.dcache.tags.occ_blocks::cpu1.data 26.433606 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.051628 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.051628 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 30 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 30 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.058594 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 406876 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 406876 # Number of data accesses +system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 124830000 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.ReadReq_hits::cpu1.data 55612 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 55612 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 45312 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 45312 # number of WriteReq hits +system.cpu1.dcache.SwapReq_hits::cpu1.data 12 # number of SwapReq hits +system.cpu1.dcache.SwapReq_hits::total 12 # number of SwapReq hits +system.cpu1.dcache.demand_hits::cpu1.data 100924 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 100924 # number of demand (read+write) hits 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ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 5584500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3659500 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 3659500 # number of WriteReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 374500 # number of SwapReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::total 374500 # number of SwapReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 9244000 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 9244000 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 9244000 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 9244000 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 56114 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 56114 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 45474 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 45474 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::cpu1.data 67 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::total 67 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 101588 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 101588 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 101588 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 101588 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.008946 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.008946 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.003562 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.003562 # miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.820896 # miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_miss_rate::total 0.820896 # miss rate for SwapReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.006536 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.006536 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.006536 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.006536 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 11124.501992 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 11124.501992 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 22589.506173 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 22589.506173 # average WriteReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 6809.090909 # average SwapReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::total 6809.090909 # average SwapReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 13921.686747 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 13921.686747 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 13921.686747 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 13921.686747 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 344 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 344 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 43 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 43 # number of WriteReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 387 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 387 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 387 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 387 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 163 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 163 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 106 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 106 # number of WriteReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 58 # number of SwapReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::total 58 # number of SwapReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 340 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 340 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 55 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 55 # number of WriteReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 395 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 395 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 395 # number of 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-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1494500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1494500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1455500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1455500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 306000 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::total 306000 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2950000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 2950000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2950000 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 2950000 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.002762 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.002762 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.002165 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.002165 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.840580 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.840580 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.002491 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.002491 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.002491 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.002491 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 9168.711656 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 9168.711656 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 13731.132075 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 13731.132075 # average WriteReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 5275.862069 # average SwapReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 5275.862069 # average SwapReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 10966.542751 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 10966.542751 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 10966.542751 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 10966.542751 # average overall mshr miss latency -system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 123936000 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2129000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2129000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1532000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1532000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 319500 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::total 319500 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3661000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 3661000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3661000 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 3661000 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.002887 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.002887 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.002353 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.002353 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.820896 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.820896 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.002648 # mshr miss rate for demand accesses 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97.753950 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 22636 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 690 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 32.805797 # Average number of references to valid blocks. system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 97.374754 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.190185 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.190185 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_task_id_blocks::1024 131 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 111 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id -system.cpu1.icache.tags.occ_task_id_percent::1024 0.255859 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 22867 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 22867 # Number of data accesses -system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 123936000 # Cumulative time (in ticks) in various power states -system.cpu1.icache.ReadReq_hits::cpu1.inst 21335 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 21335 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 21335 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 21335 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 21335 # number of overall hits -system.cpu1.icache.overall_hits::total 21335 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 845 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 845 # number of ReadReq misses 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-system.cpu1.icache.ReadReq_accesses::total 22180 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 22180 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 22180 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 22180 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 22180 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.038097 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.038097 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.038097 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.038097 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.038097 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.038097 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 22428.402367 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 22428.402367 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 22428.402367 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 22428.402367 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 22428.402367 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 22428.402367 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 141 # number of cycles access was blocked +system.cpu1.icache.tags.occ_blocks::cpu1.inst 97.753950 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.190926 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.190926 # Average percentage of cache occupancy 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(read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 22636 # number of overall hits +system.cpu1.icache.overall_hits::total 22636 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 833 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 833 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 833 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 833 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 833 # number of overall misses +system.cpu1.icache.overall_misses::total 833 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 20006500 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 20006500 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 20006500 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 20006500 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 20006500 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 20006500 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 23469 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 23469 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 23469 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 23469 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 23469 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 23469 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.035494 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.035494 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.035494 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.035494 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.035494 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.035494 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 24017.406963 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 24017.406963 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 24017.406963 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 24017.406963 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 24017.406963 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 24017.406963 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 207 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 4 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 6 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 35.250000 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 34.500000 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.writebacks::writebacks 556 # number of writebacks system.cpu1.icache.writebacks::total 556 # number of writebacks -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 158 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 158 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 158 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 158 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 158 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 158 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 687 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 687 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 687 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 687 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 687 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 687 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 14723000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 14723000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 14723000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 14723000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 14723000 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 14723000 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.030974 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.030974 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.030974 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.030974 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.030974 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.030974 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 21430.858806 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 21430.858806 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 21430.858806 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 21430.858806 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 21430.858806 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 21430.858806 # average overall mshr miss latency -system.cpu2.branchPred.lookups 66096 # Number of BP lookups -system.cpu2.branchPred.condPredicted 57926 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 2486 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 57464 # Number of BTB lookups +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 143 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 143 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 143 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 143 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 143 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 143 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 690 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 690 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 690 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 690 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 690 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 690 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 15540500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 15540500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 15540500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 15540500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 15540500 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 15540500 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.029400 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.029400 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.029400 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.029400 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.029400 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.029400 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 22522.463768 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 22522.463768 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 22522.463768 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 22522.463768 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 22522.463768 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 22522.463768 # average overall mshr miss latency +system.cpu2.branchPred.lookups 60250 # Number of BP lookups +system.cpu2.branchPred.condPredicted 52369 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 2399 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 52178 # Number of BTB lookups system.cpu2.branchPred.BTBHits 0 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu2.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 2115 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.usedRAS 1981 # Number of times the RAS was used to get a target. system.cpu2.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions. -system.cpu2.branchPred.indirectLookups 57464 # Number of indirect predictor lookups. -system.cpu2.branchPred.indirectHits 46751 # Number of indirect target hits. -system.cpu2.branchPred.indirectMisses 10713 # Number of indirect misses. -system.cpu2.branchPredindirectMispredicted 1349 # Number of mispredicted indirect branches. -system.cpu2.pwrStateResidencyTicks::ON 123936000 # Cumulative time (in ticks) in various power states -system.cpu2.numCycles 192112 # number of cpu cycles simulated +system.cpu2.branchPred.indirectLookups 52178 # Number of indirect predictor lookups. +system.cpu2.branchPred.indirectHits 41452 # Number of indirect target hits. +system.cpu2.branchPred.indirectMisses 10726 # Number of indirect misses. +system.cpu2.branchPredindirectMispredicted 1295 # Number of mispredicted indirect branches. +system.cpu2.pwrStateResidencyTicks::ON 124830000 # Cumulative time (in ticks) in various power states +system.cpu2.numCycles 191431 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 39817 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 356778 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 66096 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 48866 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 146191 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 5129 # Number of cycles fetch has spent squashing -system.cpu2.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.icacheStallCycles 42696 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 319764 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 60250 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 43433 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 142400 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 4955 # Number of cycles fetch has spent squashing +system.cpu2.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu2.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from -system.cpu2.fetch.PendingTrapStallCycles 1920 # Number of stall cycles due to pending traps -system.cpu2.fetch.IcacheWaitRetryStallCycles 3 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 28579 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 972 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.rateDist::samples 190509 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.872762 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.344982 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.PendingTrapStallCycles 2218 # Number of stall cycles due to pending traps +system.cpu2.fetch.CacheLines 31580 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 988 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.rateDist::samples 189804 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.684706 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.290533 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 72004 37.80% 37.80% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 58377 30.64% 68.44% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 8422 4.42% 72.86% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 3406 1.79% 74.65% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 670 0.35% 75.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 36267 19.04% 94.04% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 1053 0.55% 94.59% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 1474 0.77% 95.36% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 8836 4.64% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 80855 42.60% 42.60% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 54436 28.68% 71.28% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 9994 5.27% 76.54% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 3383 1.78% 78.33% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 680 0.36% 78.69% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 29156 15.36% 94.05% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 1157 0.61% 94.66% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 1395 0.73% 95.39% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 8748 4.61% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 190509 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.344049 # Number of branch fetches per cycle -system.cpu2.fetch.rate 1.857135 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 22990 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 70899 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 89451 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 4595 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 2564 # Number of cycles decode is squashing -system.cpu2.decode.DecodedInsts 324452 # Number of instructions handled by decode -system.cpu2.rename.SquashCycles 2564 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 24019 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 34614 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 13407 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 89996 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 25899 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 317685 # Number of instructions processed by rename -system.cpu2.rename.IQFullEvents 22128 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LQFullEvents 16 # Number of times rename has blocked due to LQ full +system.cpu2.fetch.rateDist::total 189804 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.314735 # Number of branch fetches per cycle +system.cpu2.fetch.rate 1.670388 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 22561 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 83775 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 75624 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 5357 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 2477 # Number of cycles decode is squashing +system.cpu2.decode.DecodedInsts 288545 # Number of instructions handled by decode +system.cpu2.rename.SquashCycles 2477 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 23562 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 41928 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 13956 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 76490 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 31381 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 281938 # Number of instructions processed by rename +system.cpu2.rename.IQFullEvents 27181 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LQFullEvents 13 # Number of times rename has blocked due to LQ full system.cpu2.rename.FullRegisterEvents 2 # Number of times there has been no free registers -system.cpu2.rename.RenamedOperands 221990 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 601950 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 469192 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 40 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 192480 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 29510 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 1686 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 1819 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 31415 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 86703 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 40578 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 41384 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 34173 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 258235 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 8782 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 258833 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 83 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 25653 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 20039 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 1265 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 190509 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.358639 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.384430 # Number of insts issued each cycle +system.cpu2.rename.RenamedOperands 195781 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 524561 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 411315 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 32 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 166026 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 29755 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 1653 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 1783 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 36818 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 74139 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 33614 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 35848 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 27180 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 226553 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 10243 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 228568 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 140 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 25915 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 20426 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 1250 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 189804 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.204232 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.376602 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 76931 40.38% 40.38% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 28046 14.72% 55.10% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 39341 20.65% 75.75% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 39028 20.49% 96.24% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 3604 1.89% 98.13% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 1759 0.92% 99.06% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 1073 0.56% 99.62% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 444 0.23% 99.85% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 283 0.15% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 85980 45.30% 45.30% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 32313 17.02% 62.32% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 32235 16.98% 79.31% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 31990 16.85% 96.16% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 3688 1.94% 98.10% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 1698 0.89% 99.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 1058 0.56% 99.56% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 511 0.27% 99.83% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 331 0.17% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 190509 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 189804 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 204 42.15% 42.15% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 42.15% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 42.15% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 42.15% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 42.15% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 42.15% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 42.15% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 42.15% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 42.15% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 42.15% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 42.15% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 42.15% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 42.15% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 42.15% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 42.15% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 42.15% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 42.15% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 42.15% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 42.15% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 42.15% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 42.15% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 42.15% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 42.15% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 42.15% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 42.15% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 42.15% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 42.15% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 42.15% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 42.15% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 51 10.54% 52.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 229 47.31% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 232 44.96% 44.96% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 44.96% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 44.96% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 44.96% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 44.96% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 44.96% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 44.96% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 44.96% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 44.96% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 44.96% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 44.96% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 44.96% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 44.96% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 44.96% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 44.96% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 44.96% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 44.96% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 44.96% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 44.96% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 44.96% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 44.96% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 44.96% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 44.96% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 44.96% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 44.96% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 44.96% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 44.96% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 44.96% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 44.96% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 58 11.24% 56.20% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 226 43.80% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 126867 49.02% 49.02% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 0 0.00% 49.02% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 49.02% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 49.02% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 49.02% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 49.02% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 49.02% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 49.02% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 49.02% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 49.02% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 49.02% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 49.02% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 49.02% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 49.02% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 49.02% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 49.02% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 49.02% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 49.02% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.02% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 49.02% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.02% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.02% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.02% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.02% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.02% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.02% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 49.02% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.02% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.02% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 92395 35.70% 84.71% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 39571 15.29% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 114651 50.16% 50.16% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 0 0.00% 50.16% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 50.16% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 50.16% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 50.16% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 50.16% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 50.16% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 50.16% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 50.16% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 50.16% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 50.16% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 50.16% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 50.16% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 50.16% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 50.16% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 50.16% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 50.16% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 50.16% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 50.16% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 50.16% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 50.16% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 50.16% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 50.16% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 50.16% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 50.16% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 50.16% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 50.16% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 50.16% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 50.16% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 81333 35.58% 85.74% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 32584 14.26% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 258833 # Type of FU issued -system.cpu2.iq.rate 1.347303 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 484 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.001870 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 708742 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 292626 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 254835 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.FU_type_0::total 228568 # Type of FU issued +system.cpu2.iq.rate 1.193997 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 516 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.002258 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 647596 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 262684 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 224391 # Number of integer instruction queue wakeup accesses system.cpu2.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 80 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_writes 64 # Number of floating instruction queue writes system.cpu2.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 259317 # Number of integer alu accesses +system.cpu2.iq.int_alu_accesses 229084 # Number of integer alu accesses system.cpu2.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 34129 # Number of loads that had data forwarded from stores +system.cpu2.iew.lsq.thread0.forwLoads 27120 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 4624 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 33 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 36 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 2677 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 4546 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 31 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 37 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 2695 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu2.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu2.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 2564 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 9290 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 55 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 309688 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 288 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 86703 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 40578 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 1561 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 34 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewSquashCycles 2477 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 10821 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 53 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 273857 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 388 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 74139 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 33614 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 1537 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 28 # Number of times the IQ has become full, causing a stall system.cpu2.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 36 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 443 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 2684 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 3127 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 256258 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 85016 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 2575 # Number of squashed instructions skipped in execute +system.cpu2.iew.memOrderViolationEvents 37 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 461 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 2611 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 3072 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 225860 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 72453 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 2708 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 42671 # number of nop insts executed -system.cpu2.iew.exec_refs 124288 # number of memory reference insts executed -system.cpu2.iew.exec_branches 53042 # Number of branches executed -system.cpu2.iew.exec_stores 39272 # Number of stores executed -system.cpu2.iew.exec_rate 1.333899 # Inst execution rate -system.cpu2.iew.wb_sent 255341 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 254835 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 142252 # num instructions producing a value -system.cpu2.iew.wb_consumers 149928 # num instructions consuming a value -system.cpu2.iew.wb_rate 1.326492 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.948802 # average fanout of values written-back -system.cpu2.commit.commitSquashedInsts 26847 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 7517 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 2486 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 185379 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.525604 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 2.006612 # Number of insts commited each cycle +system.cpu2.iew.exec_nop 37061 # number of nop insts executed +system.cpu2.iew.exec_refs 104703 # number of memory reference insts executed +system.cpu2.iew.exec_branches 47570 # Number of branches executed +system.cpu2.iew.exec_stores 32250 # Number of stores executed +system.cpu2.iew.exec_rate 1.179851 # Inst execution rate +system.cpu2.iew.wb_sent 224905 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 224391 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 122751 # num instructions producing a value +system.cpu2.iew.wb_consumers 130504 # num instructions consuming a value +system.cpu2.iew.wb_rate 1.172177 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.940592 # average fanout of values written-back +system.cpu2.commit.commitSquashedInsts 27003 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 8993 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 2399 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 184731 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.336127 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.921991 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 83888 45.25% 45.25% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 49216 26.55% 71.80% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 5545 2.99% 74.79% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 8151 4.40% 79.19% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 1274 0.69% 79.88% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 34338 18.52% 98.40% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 700 0.38% 98.78% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 1066 0.58% 99.35% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 1201 0.65% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 94349 51.07% 51.07% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 43685 23.65% 74.72% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 5440 2.94% 77.67% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 9609 5.20% 82.87% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 1281 0.69% 83.56% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 27371 14.82% 98.38% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 737 0.40% 98.78% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 1041 0.56% 99.34% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 1218 0.66% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 185379 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 282815 # Number of instructions committed -system.cpu2.commit.committedOps 282815 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 184731 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 246824 # Number of instructions committed +system.cpu2.commit.committedOps 246824 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 119980 # Number of memory references committed -system.cpu2.commit.loads 82079 # Number of loads committed -system.cpu2.commit.membars 6800 # Number of memory barriers committed -system.cpu2.commit.branches 50664 # Number of branches committed +system.cpu2.commit.refs 100512 # Number of memory references committed +system.cpu2.commit.loads 69593 # Number of loads committed +system.cpu2.commit.membars 8278 # Number of memory barriers committed +system.cpu2.commit.branches 45154 # Number of branches committed system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 192763 # Number of committed integer instructions. +system.cpu2.commit.int_insts 167790 # Number of committed integer instructions. system.cpu2.commit.function_calls 322 # Number of function calls committed. -system.cpu2.commit.op_class_0::No_OpClass 41451 14.66% 14.66% # Class of committed instruction -system.cpu2.commit.op_class_0::IntAlu 114584 40.52% 55.17% # Class of committed instruction -system.cpu2.commit.op_class_0::IntMult 0 0.00% 55.17% # Class of committed instruction -system.cpu2.commit.op_class_0::IntDiv 0 0.00% 55.17% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 55.17% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 55.17% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 55.17% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatMult 0 0.00% 55.17% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 55.17% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 55.17% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 55.17% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 55.17% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 55.17% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 55.17% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 55.17% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 55.17% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMult 0 0.00% 55.17% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 55.17% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShift 0 0.00% 55.17% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 55.17% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 55.17% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 55.17% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 55.17% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 55.17% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 55.17% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 55.17% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 55.17% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 55.17% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.17% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.17% # Class of committed instruction -system.cpu2.commit.op_class_0::MemRead 88879 31.43% 86.60% # Class of committed instruction -system.cpu2.commit.op_class_0::MemWrite 37901 13.40% 100.00% # Class of committed instruction +system.cpu2.commit.op_class_0::No_OpClass 35943 14.56% 14.56% # Class of committed instruction +system.cpu2.commit.op_class_0::IntAlu 102091 41.36% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::IntMult 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::IntDiv 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatMult 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMult 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShift 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::MemRead 77871 31.55% 87.47% # Class of committed instruction +system.cpu2.commit.op_class_0::MemWrite 30919 12.53% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu2.commit.op_class_0::total 282815 # Class of committed instruction -system.cpu2.commit.bw_lim_events 1201 # number cycles where commit BW limit reached -system.cpu2.rob.rob_reads 493254 # The number of ROB reads -system.cpu2.rob.rob_writes 624500 # The number of ROB writes -system.cpu2.timesIdled 220 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 1603 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 47823 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 234564 # Number of Instructions Simulated -system.cpu2.committedOps 234564 # Number of Ops (including micro ops) Simulated -system.cpu2.cpi 0.819017 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 0.819017 # CPI: Total CPI of All Threads -system.cpu2.ipc 1.220975 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 1.220975 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 437605 # number of integer regfile reads -system.cpu2.int_regfile_writes 204427 # number of integer regfile writes +system.cpu2.commit.op_class_0::total 246824 # Class of committed instruction +system.cpu2.commit.bw_lim_events 1218 # number cycles where commit BW limit reached +system.cpu2.rob.rob_reads 456754 # The number of ROB reads +system.cpu2.rob.rob_writes 552779 # The number of ROB writes +system.cpu2.timesIdled 204 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 1627 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 49789 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 202603 # Number of Instructions Simulated +system.cpu2.committedOps 202603 # Number of Ops (including micro ops) Simulated +system.cpu2.cpi 0.944858 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 0.944858 # CPI: Total CPI of All Threads +system.cpu2.ipc 1.058360 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 1.058360 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 379324 # number of integer regfile reads +system.cpu2.int_regfile_writes 178066 # number of integer regfile writes system.cpu2.fp_regfile_writes 64 # number of floating regfile writes -system.cpu2.misc_regfile_reads 126238 # number of misc regfile reads +system.cpu2.misc_regfile_reads 106600 # number of misc regfile reads system.cpu2.misc_regfile_writes 648 # number of misc regfile writes -system.cpu2.dcache.tags.pwrStateResidencyTicks::UNDEFINED 123936000 # Cumulative time (in ticks) in various power states +system.cpu2.dcache.tags.pwrStateResidencyTicks::UNDEFINED 124830000 # Cumulative time (in ticks) in various power states system.cpu2.dcache.tags.replacements 0 # number of replacements -system.cpu2.dcache.tags.tagsinuse 26.114184 # Cycle average of tags in use -system.cpu2.dcache.tags.total_refs 45075 # Total number of references to valid blocks. -system.cpu2.dcache.tags.sampled_refs 30 # Sample count of references to valid blocks. -system.cpu2.dcache.tags.avg_refs 1502.500000 # Average number of references to valid blocks. +system.cpu2.dcache.tags.tagsinuse 24.613342 # Cycle average of tags in use +system.cpu2.dcache.tags.total_refs 38229 # Total number of references to valid blocks. +system.cpu2.dcache.tags.sampled_refs 31 # Sample count of references to valid blocks. +system.cpu2.dcache.tags.avg_refs 1233.193548 # Average number of references to valid blocks. system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.dcache.tags.occ_blocks::cpu2.data 26.114184 # Average occupied blocks per requestor -system.cpu2.dcache.tags.occ_percent::cpu2.data 0.051004 # Average percentage of cache occupancy -system.cpu2.dcache.tags.occ_percent::total 0.051004 # Average percentage of cache occupancy -system.cpu2.dcache.tags.occ_task_id_blocks::1024 30 # Occupied blocks per task id +system.cpu2.dcache.tags.occ_blocks::cpu2.data 24.613342 # Average occupied blocks per requestor +system.cpu2.dcache.tags.occ_percent::cpu2.data 0.048073 # Average percentage of cache occupancy +system.cpu2.dcache.tags.occ_percent::total 0.048073 # Average percentage of cache occupancy +system.cpu2.dcache.tags.occ_task_id_blocks::1024 31 # Occupied blocks per task id +system.cpu2.dcache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id system.cpu2.dcache.tags.age_task_id_blocks_1024::1 30 # Occupied blocks per task id -system.cpu2.dcache.tags.occ_task_id_percent::1024 0.058594 # Percentage of cache occupancy per task id -system.cpu2.dcache.tags.tag_accesses 355312 # Number of tag accesses -system.cpu2.dcache.tags.data_accesses 355312 # Number of data accesses -system.cpu2.dcache.pwrStateResidencyTicks::UNDEFINED 123936000 # Cumulative time (in ticks) in various power states -system.cpu2.dcache.ReadReq_hits::cpu2.data 50364 # number of ReadReq hits -system.cpu2.dcache.ReadReq_hits::total 50364 # number of ReadReq hits -system.cpu2.dcache.WriteReq_hits::cpu2.data 37691 # number of WriteReq hits -system.cpu2.dcache.WriteReq_hits::total 37691 # number of WriteReq hits -system.cpu2.dcache.SwapReq_hits::cpu2.data 13 # number of SwapReq hits -system.cpu2.dcache.SwapReq_hits::total 13 # number of SwapReq hits -system.cpu2.dcache.demand_hits::cpu2.data 88055 # number of demand (read+write) hits -system.cpu2.dcache.demand_hits::total 88055 # number of demand (read+write) hits -system.cpu2.dcache.overall_hits::cpu2.data 88055 # number of overall hits -system.cpu2.dcache.overall_hits::total 88055 # number of overall hits -system.cpu2.dcache.ReadReq_misses::cpu2.data 498 # number of ReadReq misses -system.cpu2.dcache.ReadReq_misses::total 498 # number of ReadReq misses -system.cpu2.dcache.WriteReq_misses::cpu2.data 139 # number of WriteReq misses -system.cpu2.dcache.WriteReq_misses::total 139 # number of WriteReq misses -system.cpu2.dcache.SwapReq_misses::cpu2.data 58 # number of SwapReq misses -system.cpu2.dcache.SwapReq_misses::total 58 # number of SwapReq misses -system.cpu2.dcache.demand_misses::cpu2.data 637 # number of demand (read+write) misses -system.cpu2.dcache.demand_misses::total 637 # number of demand (read+write) misses -system.cpu2.dcache.overall_misses::cpu2.data 637 # number of overall misses -system.cpu2.dcache.overall_misses::total 637 # number of overall misses -system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 3990000 # number of ReadReq miss cycles -system.cpu2.dcache.ReadReq_miss_latency::total 3990000 # number of ReadReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 2835500 # number of WriteReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::total 2835500 # number of WriteReq miss cycles -system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 366500 # number of SwapReq miss cycles -system.cpu2.dcache.SwapReq_miss_latency::total 366500 # number of SwapReq miss cycles -system.cpu2.dcache.demand_miss_latency::cpu2.data 6825500 # number of demand (read+write) miss cycles -system.cpu2.dcache.demand_miss_latency::total 6825500 # number of demand (read+write) miss cycles -system.cpu2.dcache.overall_miss_latency::cpu2.data 6825500 # number of overall miss cycles -system.cpu2.dcache.overall_miss_latency::total 6825500 # number of overall miss cycles -system.cpu2.dcache.ReadReq_accesses::cpu2.data 50862 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.ReadReq_accesses::total 50862 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::cpu2.data 37830 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::total 37830 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_accesses::cpu2.data 71 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.demand_accesses::cpu2.data 88692 # number of demand (read+write) accesses -system.cpu2.dcache.demand_accesses::total 88692 # number of demand (read+write) accesses -system.cpu2.dcache.overall_accesses::cpu2.data 88692 # number of overall (read+write) accesses -system.cpu2.dcache.overall_accesses::total 88692 # number of overall (read+write) accesses -system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.009791 # miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_miss_rate::total 0.009791 # miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.003674 # miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_miss_rate::total 0.003674 # miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.816901 # miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_miss_rate::total 0.816901 # miss rate for SwapReq accesses -system.cpu2.dcache.demand_miss_rate::cpu2.data 0.007182 # miss rate for demand accesses -system.cpu2.dcache.demand_miss_rate::total 0.007182 # miss rate for demand accesses -system.cpu2.dcache.overall_miss_rate::cpu2.data 0.007182 # miss rate for overall accesses -system.cpu2.dcache.overall_miss_rate::total 0.007182 # miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 8012.048193 # average ReadReq miss latency -system.cpu2.dcache.ReadReq_avg_miss_latency::total 8012.048193 # average ReadReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 20399.280576 # average WriteReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::total 20399.280576 # average WriteReq miss latency -system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 6318.965517 # average SwapReq miss latency -system.cpu2.dcache.SwapReq_avg_miss_latency::total 6318.965517 # average SwapReq miss latency -system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 10715.070644 # average overall miss latency -system.cpu2.dcache.demand_avg_miss_latency::total 10715.070644 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 10715.070644 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::total 10715.070644 # average overall miss latency +system.cpu2.dcache.tags.occ_task_id_percent::1024 0.060547 # Percentage of cache occupancy per task id +system.cpu2.dcache.tags.tag_accesses 305153 # Number of tag accesses +system.cpu2.dcache.tags.data_accesses 305153 # Number of data accesses +system.cpu2.dcache.pwrStateResidencyTicks::UNDEFINED 124830000 # Cumulative time (in ticks) in various power states +system.cpu2.dcache.ReadReq_hits::cpu2.data 44839 # number of ReadReq hits +system.cpu2.dcache.ReadReq_hits::total 44839 # number of ReadReq hits +system.cpu2.dcache.WriteReq_hits::cpu2.data 30714 # number of WriteReq hits +system.cpu2.dcache.WriteReq_hits::total 30714 # number of WriteReq hits +system.cpu2.dcache.SwapReq_hits::cpu2.data 16 # number of SwapReq hits +system.cpu2.dcache.SwapReq_hits::total 16 # number of SwapReq hits +system.cpu2.dcache.demand_hits::cpu2.data 75553 # number of demand (read+write) hits +system.cpu2.dcache.demand_hits::total 75553 # number of demand (read+write) hits +system.cpu2.dcache.overall_hits::cpu2.data 75553 # number of overall hits +system.cpu2.dcache.overall_hits::total 75553 # number of overall hits +system.cpu2.dcache.ReadReq_misses::cpu2.data 467 # number of ReadReq misses +system.cpu2.dcache.ReadReq_misses::total 467 # number of ReadReq misses +system.cpu2.dcache.WriteReq_misses::cpu2.data 136 # number of WriteReq misses +system.cpu2.dcache.WriteReq_misses::total 136 # number of WriteReq misses +system.cpu2.dcache.SwapReq_misses::cpu2.data 53 # number of SwapReq misses +system.cpu2.dcache.SwapReq_misses::total 53 # number of SwapReq misses +system.cpu2.dcache.demand_misses::cpu2.data 603 # number of demand (read+write) misses +system.cpu2.dcache.demand_misses::total 603 # number of demand (read+write) misses +system.cpu2.dcache.overall_misses::cpu2.data 603 # number of overall misses +system.cpu2.dcache.overall_misses::total 603 # number of overall misses +system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 3772500 # number of ReadReq miss cycles +system.cpu2.dcache.ReadReq_miss_latency::total 3772500 # number of ReadReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 3722500 # number of WriteReq miss cycles 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WriteReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::cpu2.data 69 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::total 69 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.demand_accesses::cpu2.data 76156 # number of demand (read+write) accesses +system.cpu2.dcache.demand_accesses::total 76156 # number of demand (read+write) accesses +system.cpu2.dcache.overall_accesses::cpu2.data 76156 # number of overall (read+write) accesses +system.cpu2.dcache.overall_accesses::total 76156 # number of overall (read+write) accesses +system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.010308 # miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_miss_rate::total 0.010308 # miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.004408 # miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_miss_rate::total 0.004408 # miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.768116 # miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_miss_rate::total 0.768116 # miss rate for SwapReq accesses +system.cpu2.dcache.demand_miss_rate::cpu2.data 0.007918 # miss rate for demand accesses +system.cpu2.dcache.demand_miss_rate::total 0.007918 # miss rate for demand accesses +system.cpu2.dcache.overall_miss_rate::cpu2.data 0.007918 # miss rate for overall accesses +system.cpu2.dcache.overall_miss_rate::total 0.007918 # miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 8078.158458 # average ReadReq miss latency +system.cpu2.dcache.ReadReq_avg_miss_latency::total 8078.158458 # average ReadReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 27371.323529 # average WriteReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::total 27371.323529 # average WriteReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 6405.660377 # average SwapReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::total 6405.660377 # average SwapReq miss latency +system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 12429.519071 # average overall miss latency +system.cpu2.dcache.demand_avg_miss_latency::total 12429.519071 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 12429.519071 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::total 12429.519071 # average overall miss latency system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 331 # number of ReadReq MSHR hits -system.cpu2.dcache.ReadReq_mshr_hits::total 331 # number of ReadReq MSHR hits +system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 301 # number of ReadReq MSHR hits +system.cpu2.dcache.ReadReq_mshr_hits::total 301 # number of ReadReq MSHR hits system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 34 # number of WriteReq MSHR hits system.cpu2.dcache.WriteReq_mshr_hits::total 34 # number of WriteReq MSHR hits -system.cpu2.dcache.demand_mshr_hits::cpu2.data 365 # number of demand (read+write) MSHR hits -system.cpu2.dcache.demand_mshr_hits::total 365 # number of demand (read+write) MSHR hits -system.cpu2.dcache.overall_mshr_hits::cpu2.data 365 # number of overall MSHR hits -system.cpu2.dcache.overall_mshr_hits::total 365 # number of overall MSHR hits -system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 167 # number of ReadReq MSHR misses -system.cpu2.dcache.ReadReq_mshr_misses::total 167 # number of ReadReq MSHR misses -system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 105 # number of WriteReq MSHR misses -system.cpu2.dcache.WriteReq_mshr_misses::total 105 # number of WriteReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 58 # number of SwapReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses::total 58 # number of SwapReq MSHR misses -system.cpu2.dcache.demand_mshr_misses::cpu2.data 272 # number of demand (read+write) MSHR misses -system.cpu2.dcache.demand_mshr_misses::total 272 # number of demand (read+write) MSHR misses -system.cpu2.dcache.overall_mshr_misses::cpu2.data 272 # number of overall MSHR misses -system.cpu2.dcache.overall_mshr_misses::total 272 # number of overall MSHR misses -system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1193000 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1193000 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1388000 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1388000 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 308500 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::total 308500 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 2581000 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::total 2581000 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 2581000 # number of overall MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::total 2581000 # number of overall MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003283 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003283 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.002776 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.002776 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.816901 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.816901 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.003067 # mshr miss rate for demand accesses -system.cpu2.dcache.demand_mshr_miss_rate::total 0.003067 # mshr miss rate for demand accesses -system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.003067 # mshr miss rate for overall accesses -system.cpu2.dcache.overall_mshr_miss_rate::total 0.003067 # mshr miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 7143.712575 # average ReadReq mshr miss latency -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 7143.712575 # average ReadReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 13219.047619 # average WriteReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 13219.047619 # average WriteReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 5318.965517 # average SwapReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 5318.965517 # average SwapReq mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 9488.970588 # average overall mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::total 9488.970588 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 9488.970588 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::total 9488.970588 # average overall mshr miss latency -system.cpu2.icache.tags.pwrStateResidencyTicks::UNDEFINED 123936000 # Cumulative time (in ticks) in various power states -system.cpu2.icache.tags.replacements 578 # number of replacements -system.cpu2.icache.tags.tagsinuse 95.404705 # Cycle average of tags in use -system.cpu2.icache.tags.total_refs 27742 # Total number of references to valid blocks. -system.cpu2.icache.tags.sampled_refs 710 # Sample count of references to valid blocks. -system.cpu2.icache.tags.avg_refs 39.073239 # Average number of references to valid blocks. +system.cpu2.dcache.SwapReq_mshr_hits::cpu2.data 1 # number of SwapReq MSHR hits +system.cpu2.dcache.SwapReq_mshr_hits::total 1 # number of SwapReq MSHR hits +system.cpu2.dcache.demand_mshr_hits::cpu2.data 335 # number of demand (read+write) MSHR hits +system.cpu2.dcache.demand_mshr_hits::total 335 # number of demand (read+write) MSHR hits +system.cpu2.dcache.overall_mshr_hits::cpu2.data 335 # number of overall MSHR hits +system.cpu2.dcache.overall_mshr_hits::total 335 # number of overall MSHR hits +system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 166 # number of ReadReq MSHR misses +system.cpu2.dcache.ReadReq_mshr_misses::total 166 # number of ReadReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 102 # number of WriteReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses::total 102 # number of WriteReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 52 # number of SwapReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses::total 52 # number of SwapReq MSHR misses +system.cpu2.dcache.demand_mshr_misses::cpu2.data 268 # number of demand (read+write) MSHR misses +system.cpu2.dcache.demand_mshr_misses::total 268 # number of demand (read+write) MSHR misses +system.cpu2.dcache.overall_mshr_misses::cpu2.data 268 # number of overall MSHR misses +system.cpu2.dcache.overall_mshr_misses::total 268 # number of overall MSHR misses +system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1217000 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1217000 # number of ReadReq MSHR miss cycles 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ReadReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 19034.313725 # average WriteReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 19034.313725 # average WriteReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 5509.615385 # average SwapReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 5509.615385 # average SwapReq mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 11785.447761 # average overall mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::total 11785.447761 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 11785.447761 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::total 11785.447761 # average overall mshr miss latency +system.cpu2.icache.tags.pwrStateResidencyTicks::UNDEFINED 124830000 # Cumulative time (in ticks) in various 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12852000 # number of ReadReq miss cycles -system.cpu2.icache.demand_miss_latency::cpu2.inst 12852000 # number of demand (read+write) miss cycles -system.cpu2.icache.demand_miss_latency::total 12852000 # number of demand (read+write) miss cycles -system.cpu2.icache.overall_miss_latency::cpu2.inst 12852000 # number of overall miss cycles -system.cpu2.icache.overall_miss_latency::total 12852000 # number of overall miss cycles -system.cpu2.icache.ReadReq_accesses::cpu2.inst 28579 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.ReadReq_accesses::total 28579 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.demand_accesses::cpu2.inst 28579 # number of demand (read+write) accesses -system.cpu2.icache.demand_accesses::total 28579 # number of demand (read+write) accesses -system.cpu2.icache.overall_accesses::cpu2.inst 28579 # number of overall (read+write) accesses -system.cpu2.icache.overall_accesses::total 28579 # number of overall (read+write) accesses -system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.029287 # miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_miss_rate::total 0.029287 # miss rate for ReadReq accesses -system.cpu2.icache.demand_miss_rate::cpu2.inst 0.029287 # miss rate for demand accesses -system.cpu2.icache.demand_miss_rate::total 0.029287 # miss rate for demand accesses -system.cpu2.icache.overall_miss_rate::cpu2.inst 0.029287 # miss rate for overall accesses -system.cpu2.icache.overall_miss_rate::total 0.029287 # miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 15354.838710 # average ReadReq miss latency -system.cpu2.icache.ReadReq_avg_miss_latency::total 15354.838710 # average ReadReq miss latency -system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 15354.838710 # average overall miss latency -system.cpu2.icache.demand_avg_miss_latency::total 15354.838710 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 15354.838710 # average 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miss cycles -system.cpu2.icache.demand_mshr_miss_latency::total 10853000 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 10853000 # number of overall MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::total 10853000 # number of overall MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.024843 # mshr miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.024843 # mshr miss rate for ReadReq accesses -system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.024843 # mshr miss rate for demand accesses -system.cpu2.icache.demand_mshr_miss_rate::total 0.024843 # mshr miss rate for demand accesses -system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.024843 # mshr miss rate for overall accesses -system.cpu2.icache.overall_mshr_miss_rate::total 0.024843 # mshr miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 15285.915493 # average ReadReq mshr miss latency -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 15285.915493 # average ReadReq mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 15285.915493 # average overall mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::total 15285.915493 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 15285.915493 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::total 15285.915493 # average overall mshr miss latency -system.cpu3.branchPred.lookups 58058 # Number of BP lookups -system.cpu3.branchPred.condPredicted 50256 # Number of conditional branches predicted -system.cpu3.branchPred.condIncorrect 2406 # Number of conditional branches incorrect -system.cpu3.branchPred.BTBLookups 50211 # Number of BTB lookups +system.cpu2.icache.writebacks::writebacks 564 # number of writebacks +system.cpu2.icache.writebacks::total 564 # number of writebacks +system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 144 # number of ReadReq MSHR hits +system.cpu2.icache.ReadReq_mshr_hits::total 144 # number of ReadReq MSHR hits +system.cpu2.icache.demand_mshr_hits::cpu2.inst 144 # number of demand (read+write) MSHR hits +system.cpu2.icache.demand_mshr_hits::total 144 # number of demand (read+write) MSHR hits +system.cpu2.icache.overall_mshr_hits::cpu2.inst 144 # number of overall MSHR hits +system.cpu2.icache.overall_mshr_hits::total 144 # number of overall MSHR hits +system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 702 # number of ReadReq MSHR misses +system.cpu2.icache.ReadReq_mshr_misses::total 702 # number of ReadReq MSHR misses +system.cpu2.icache.demand_mshr_misses::cpu2.inst 702 # number of demand (read+write) MSHR misses +system.cpu2.icache.demand_mshr_misses::total 702 # number of demand (read+write) MSHR misses +system.cpu2.icache.overall_mshr_misses::cpu2.inst 702 # number of overall MSHR misses +system.cpu2.icache.overall_mshr_misses::total 702 # number of overall MSHR misses +system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 10591000 # number of ReadReq MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_latency::total 10591000 # number of ReadReq MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 10591000 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::total 10591000 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 10591000 # number of overall MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::total 10591000 # number of overall MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.022229 # mshr miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.022229 # mshr miss rate for ReadReq accesses +system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.022229 # mshr miss rate for demand accesses +system.cpu2.icache.demand_mshr_miss_rate::total 0.022229 # mshr miss rate for demand accesses +system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.022229 # mshr miss rate for overall accesses +system.cpu2.icache.overall_mshr_miss_rate::total 0.022229 # mshr miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 15086.894587 # average ReadReq mshr miss latency +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 15086.894587 # average ReadReq mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 15086.894587 # average overall mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::total 15086.894587 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 15086.894587 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::total 15086.894587 # average overall mshr miss latency +system.cpu3.branchPred.lookups 65607 # Number of BP lookups +system.cpu3.branchPred.condPredicted 57989 # Number of conditional branches predicted +system.cpu3.branchPred.condIncorrect 2329 # Number of conditional branches incorrect +system.cpu3.branchPred.BTBLookups 57945 # Number of BTB lookups system.cpu3.branchPred.BTBHits 0 # Number of BTB hits system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu3.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage -system.cpu3.branchPred.usedRAS 1984 # Number of times the RAS was used to get a target. +system.cpu3.branchPred.usedRAS 1972 # Number of times the RAS was used to get a target. system.cpu3.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions. -system.cpu3.branchPred.indirectLookups 50211 # Number of indirect predictor lookups. -system.cpu3.branchPred.indirectHits 39339 # Number of indirect target hits. -system.cpu3.branchPred.indirectMisses 10872 # Number of indirect misses. -system.cpu3.branchPredindirectMispredicted 1290 # Number of mispredicted indirect branches. -system.cpu3.pwrStateResidencyTicks::ON 123936000 # Cumulative time (in ticks) in various power states -system.cpu3.numCycles 191755 # number of cpu cycles simulated +system.cpu3.branchPred.indirectLookups 57945 # Number of indirect predictor lookups. +system.cpu3.branchPred.indirectHits 47394 # Number of indirect target hits. +system.cpu3.branchPred.indirectMisses 10551 # Number of indirect misses. +system.cpu3.branchPredindirectMispredicted 1239 # Number of mispredicted indirect branches. +system.cpu3.pwrStateResidencyTicks::ON 124830000 # Cumulative time (in ticks) in various power states +system.cpu3.numCycles 191064 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu3.fetch.icacheStallCycles 44345 # Number of cycles fetch is stalled on an Icache miss -system.cpu3.fetch.Insts 305380 # Number of instructions fetch has processed -system.cpu3.fetch.Branches 58058 # Number of branches that fetch encountered -system.cpu3.fetch.predictedBranches 41323 # Number of branches that fetch has predicted taken -system.cpu3.fetch.Cycles 141573 # Number of cycles fetch has run and was not squashing or blocked -system.cpu3.fetch.SquashCycles 4965 # Number of cycles fetch has spent squashing +system.cpu3.fetch.icacheStallCycles 38959 # Number of cycles fetch is stalled on an Icache miss +system.cpu3.fetch.Insts 355945 # Number of instructions fetch has processed +system.cpu3.fetch.Branches 65607 # Number of branches that fetch encountered +system.cpu3.fetch.predictedBranches 49366 # Number of branches that fetch has predicted taken +system.cpu3.fetch.Cycles 146283 # Number of cycles fetch has run and was not squashing or blocked +system.cpu3.fetch.SquashCycles 4811 # Number of cycles fetch has spent squashing system.cpu3.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu3.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from -system.cpu3.fetch.PendingTrapStallCycles 1720 # Number of stall cycles due to pending traps -system.cpu3.fetch.CacheLines 32940 # Number of cache lines fetched -system.cpu3.fetch.IcacheSquashes 916 # Number of outstanding Icache misses that were squashed -system.cpu3.fetch.rateDist::samples 190133 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::mean 1.606139 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::stdev 2.261267 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.PendingTrapStallCycles 1648 # Number of stall cycles due to pending traps +system.cpu3.fetch.CacheLines 27872 # Number of cache lines fetched +system.cpu3.fetch.IcacheSquashes 954 # Number of outstanding Icache misses that were squashed +system.cpu3.fetch.rateDist::samples 189308 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::mean 1.880243 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::stdev 2.334212 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::0 84706 44.55% 44.55% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::1 53051 27.90% 72.45% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::2 10689 5.62% 78.07% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::3 3433 1.81% 79.88% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::4 679 0.36% 80.24% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::5 26352 13.86% 94.10% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::6 1085 0.57% 94.67% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::7 1438 0.76% 95.42% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::8 8700 4.58% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::0 70601 37.29% 37.29% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::1 58551 30.93% 68.22% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::2 8289 4.38% 72.60% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::3 3543 1.87% 74.47% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::4 620 0.33% 74.80% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::5 36795 19.44% 94.24% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::6 1123 0.59% 94.83% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::7 1294 0.68% 95.51% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::8 8492 4.49% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::total 190133 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.branchRate 0.302772 # Number of branch fetches per cycle -system.cpu3.fetch.rate 1.592553 # Number of inst fetches per cycle -system.cpu3.decode.IdleCycles 22846 # Number of cycles decode is idle -system.cpu3.decode.BlockedCycles 89002 # Number of cycles decode is blocked -system.cpu3.decode.RunCycles 70141 # Number of cycles decode is running -system.cpu3.decode.UnblockCycles 5652 # Number of cycles decode is unblocking -system.cpu3.decode.SquashCycles 2482 # Number of cycles decode is squashing -system.cpu3.decode.DecodedInsts 273868 # Number of instructions handled by decode -system.cpu3.rename.SquashCycles 2482 # Number of cycles rename is squashing -system.cpu3.rename.IdleCycles 23847 # Number of cycles rename is idle -system.cpu3.rename.BlockCycles 45287 # Number of cycles rename is blocking -system.cpu3.rename.serializeStallCycles 13384 # count of cycles rename stalled for serializing inst -system.cpu3.rename.RunCycles 70737 # Number of cycles rename is running -system.cpu3.rename.UnblockCycles 34386 # Number of cycles rename is unblocking -system.cpu3.rename.RenamedInsts 267452 # Number of instructions processed by rename -system.cpu3.rename.IQFullEvents 29592 # Number of times rename has blocked due to IQ full -system.cpu3.rename.LQFullEvents 13 # Number of times rename has blocked due to LQ full -system.cpu3.rename.RenamedOperands 184677 # Number of destination operands rename has renamed -system.cpu3.rename.RenameLookups 492576 # Number of register rename lookups that rename has made -system.cpu3.rename.int_rename_lookups 387264 # Number of integer rename lookups -system.cpu3.rename.fp_rename_lookups 20 # Number of floating rename lookups -system.cpu3.rename.CommittedMaps 155405 # Number of HB maps that are committed -system.cpu3.rename.UndoneMaps 29272 # Number of HB maps that are undone due to squashing -system.cpu3.rename.serializingInsts 1682 # count of serializing insts renamed -system.cpu3.rename.tempSerializingInsts 1811 # count of temporary serializing insts renamed -system.cpu3.rename.skidInsts 39856 # count of insts added to the skid buffer -system.cpu3.memDep0.insertedLoads 69050 # Number of loads inserted to the mem dependence unit. -system.cpu3.memDep0.insertedStores 30771 # Number of stores inserted to the mem dependence unit. -system.cpu3.memDep0.conflictingLoads 33750 # Number of conflicting loads. -system.cpu3.memDep0.conflictingStores 24332 # Number of conflicting stores. -system.cpu3.iq.iqInstsAdded 213083 # Number of instructions added to the IQ (excludes non-spec) -system.cpu3.iq.iqNonSpecInstsAdded 11008 # Number of non-speculative instructions added to the IQ -system.cpu3.iq.iqInstsIssued 216315 # Number of instructions issued -system.cpu3.iq.iqSquashedInstsIssued 53 # Number of squashed instructions issued -system.cpu3.iq.iqSquashedInstsExamined 25213 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu3.iq.iqSquashedOperandsExamined 19048 # Number of squashed operands that are examined and possibly removed from graph -system.cpu3.iq.iqSquashedNonSpecRemoved 1289 # Number of squashed non-spec instructions that were removed -system.cpu3.iq.issued_per_cycle::samples 190133 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::mean 1.137704 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::stdev 1.357547 # Number of insts issued each cycle +system.cpu3.fetch.rateDist::total 189308 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.branchRate 0.343377 # Number of branch fetches per cycle +system.cpu3.fetch.rate 1.862962 # Number of inst fetches per cycle +system.cpu3.decode.IdleCycles 22011 # Number of cycles decode is idle +system.cpu3.decode.BlockedCycles 70196 # Number of cycles decode is blocked +system.cpu3.decode.RunCycles 90137 # Number of cycles decode is running +system.cpu3.decode.UnblockCycles 4549 # Number of cycles decode is unblocking +system.cpu3.decode.SquashCycles 2405 # Number of cycles decode is squashing +system.cpu3.decode.DecodedInsts 325577 # Number of instructions handled by decode +system.cpu3.rename.SquashCycles 2405 # Number of cycles rename is squashing +system.cpu3.rename.IdleCycles 23040 # Number of cycles rename is idle +system.cpu3.rename.BlockCycles 34162 # Number of cycles rename is blocking +system.cpu3.rename.serializeStallCycles 13425 # count of cycles rename stalled for serializing inst +system.cpu3.rename.RunCycles 90919 # Number of cycles rename is running +system.cpu3.rename.UnblockCycles 25347 # Number of cycles rename is unblocking +system.cpu3.rename.RenamedInsts 318974 # Number of instructions processed by rename +system.cpu3.rename.IQFullEvents 21885 # Number of times rename has blocked due to IQ full +system.cpu3.rename.LQFullEvents 17 # Number of times rename has blocked due to LQ full +system.cpu3.rename.RenamedOperands 222576 # Number of destination operands rename has renamed +system.cpu3.rename.RenameLookups 605183 # Number of register rename lookups that rename has made +system.cpu3.rename.int_rename_lookups 471258 # Number of integer rename lookups +system.cpu3.rename.fp_rename_lookups 38 # Number of floating rename lookups +system.cpu3.rename.CommittedMaps 194403 # Number of HB maps that are committed +system.cpu3.rename.UndoneMaps 28173 # Number of HB maps that are undone due to squashing +system.cpu3.rename.serializingInsts 1623 # count of serializing insts renamed +system.cpu3.rename.tempSerializingInsts 1757 # count of temporary serializing insts renamed +system.cpu3.rename.skidInsts 30798 # count of insts added to the skid buffer +system.cpu3.memDep0.insertedLoads 87479 # Number of loads inserted to the mem dependence unit. +system.cpu3.memDep0.insertedStores 41118 # Number of stores inserted to the mem dependence unit. +system.cpu3.memDep0.conflictingLoads 41854 # Number of conflicting loads. +system.cpu3.memDep0.conflictingStores 34728 # Number of conflicting stores. +system.cpu3.iq.iqInstsAdded 259350 # Number of instructions added to the IQ (excludes non-spec) +system.cpu3.iq.iqNonSpecInstsAdded 8662 # Number of non-speculative instructions added to the IQ +system.cpu3.iq.iqInstsIssued 260097 # Number of instructions issued +system.cpu3.iq.iqSquashedInstsIssued 100 # Number of squashed instructions issued +system.cpu3.iq.iqSquashedInstsExamined 24362 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu3.iq.iqSquashedOperandsExamined 19655 # Number of squashed operands that are examined and possibly removed from graph +system.cpu3.iq.iqSquashedNonSpecRemoved 1213 # Number of squashed non-spec instructions that were removed +system.cpu3.iq.issued_per_cycle::samples 189308 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::mean 1.373936 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::stdev 1.388628 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::0 89784 47.22% 47.22% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::1 34463 18.13% 65.35% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::2 29348 15.44% 80.78% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::3 29336 15.43% 96.21% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::4 3681 1.94% 98.15% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::5 1744 0.92% 99.07% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::6 1040 0.55% 99.61% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::7 432 0.23% 99.84% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::8 305 0.16% 100.00% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::0 75622 39.95% 39.95% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::1 27531 14.54% 54.49% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::2 39579 20.91% 75.40% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::3 39359 20.79% 96.19% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::4 3671 1.94% 98.13% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::5 1727 0.91% 99.04% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::6 1045 0.55% 99.59% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::7 450 0.24% 99.83% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::8 324 0.17% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::total 190133 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::total 189308 # Number of insts issued each cycle system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntAlu 189 39.38% 39.38% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntMult 0 0.00% 39.38% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntDiv 0 0.00% 39.38% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatAdd 0 0.00% 39.38% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCmp 0 0.00% 39.38% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCvt 0 0.00% 39.38% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatMult 0 0.00% 39.38% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatDiv 0 0.00% 39.38% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 39.38% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAdd 0 0.00% 39.38% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 39.38% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAlu 0 0.00% 39.38% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCmp 0 0.00% 39.38% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCvt 0 0.00% 39.38% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMisc 0 0.00% 39.38% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMult 0 0.00% 39.38% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 39.38% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShift 0 0.00% 39.38% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 39.38% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 39.38% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 39.38% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 39.38% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 39.38% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 39.38% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 39.38% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 39.38% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 39.38% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 39.38% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 39.38% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemRead 53 11.04% 50.42% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemWrite 238 49.58% 100.00% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntAlu 198 41.42% 41.42% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntMult 0 0.00% 41.42% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntDiv 0 0.00% 41.42% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatAdd 0 0.00% 41.42% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCmp 0 0.00% 41.42% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCvt 0 0.00% 41.42% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatMult 0 0.00% 41.42% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatDiv 0 0.00% 41.42% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 41.42% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAdd 0 0.00% 41.42% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 41.42% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAlu 0 0.00% 41.42% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCmp 0 0.00% 41.42% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCvt 0 0.00% 41.42% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMisc 0 0.00% 41.42% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMult 0 0.00% 41.42% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 41.42% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShift 0 0.00% 41.42% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 41.42% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 41.42% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 41.42% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 41.42% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 41.42% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 41.42% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 41.42% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 41.42% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 41.42% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 41.42% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 41.42% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemRead 48 10.04% 51.46% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemWrite 232 48.54% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu3.iq.FU_type_0::IntAlu 109511 50.63% 50.63% # Type of FU issued -system.cpu3.iq.FU_type_0::IntMult 0 0.00% 50.63% # Type of FU issued -system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 50.63% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 50.63% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 50.63% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 50.63% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 50.63% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 50.63% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 50.63% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 50.63% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 50.63% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 50.63% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 50.63% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 50.63% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 50.63% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 50.63% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 50.63% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 50.63% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 50.63% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 50.63% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 50.63% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 50.63% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 50.63% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 50.63% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 50.63% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 50.63% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 50.63% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 50.63% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 50.63% # Type of FU issued -system.cpu3.iq.FU_type_0::MemRead 77010 35.60% 86.23% # Type of FU issued -system.cpu3.iq.FU_type_0::MemWrite 29794 13.77% 100.00% # Type of FU issued +system.cpu3.iq.FU_type_0::IntAlu 126919 48.80% 48.80% # Type of FU issued +system.cpu3.iq.FU_type_0::IntMult 0 0.00% 48.80% # Type of FU issued +system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 48.80% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 48.80% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 48.80% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 48.80% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 48.80% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 48.80% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 48.80% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 48.80% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 48.80% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 48.80% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 48.80% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 48.80% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 48.80% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 48.80% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 48.80% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 48.80% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.80% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 48.80% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.80% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.80% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.80% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.80% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.80% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.80% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 48.80% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.80% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.80% # Type of FU issued +system.cpu3.iq.FU_type_0::MemRead 93130 35.81% 84.60% # Type of FU issued +system.cpu3.iq.FU_type_0::MemWrite 40048 15.40% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu3.iq.FU_type_0::total 216315 # Type of FU issued -system.cpu3.iq.rate 1.128080 # Inst issue rate -system.cpu3.iq.fu_busy_cnt 480 # FU busy when requested -system.cpu3.iq.fu_busy_rate 0.002219 # FU busy rate (busy events/executed inst) -system.cpu3.iq.int_inst_queue_reads 623296 # Number of integer instruction queue reads -system.cpu3.iq.int_inst_queue_writes 249298 # Number of integer instruction queue writes -system.cpu3.iq.int_inst_queue_wakeup_accesses 212257 # Number of integer instruction queue wakeup accesses +system.cpu3.iq.FU_type_0::total 260097 # Type of FU issued +system.cpu3.iq.rate 1.361308 # Inst issue rate +system.cpu3.iq.fu_busy_cnt 478 # FU busy when requested +system.cpu3.iq.fu_busy_rate 0.001838 # FU busy rate (busy events/executed inst) +system.cpu3.iq.int_inst_queue_reads 710080 # Number of integer instruction queue reads +system.cpu3.iq.int_inst_queue_writes 292336 # Number of integer instruction queue writes +system.cpu3.iq.int_inst_queue_wakeup_accesses 256163 # Number of integer instruction queue wakeup accesses system.cpu3.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads -system.cpu3.iq.fp_inst_queue_writes 40 # Number of floating instruction queue writes +system.cpu3.iq.fp_inst_queue_writes 76 # Number of floating instruction queue writes system.cpu3.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu3.iq.int_alu_accesses 216795 # Number of integer alu accesses +system.cpu3.iq.int_alu_accesses 260575 # Number of integer alu accesses system.cpu3.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu3.iew.lsq.thread0.forwLoads 24283 # Number of loads that had data forwarded from stores +system.cpu3.iew.lsq.thread0.forwLoads 34620 # Number of loads that had data forwarded from stores system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu3.iew.lsq.thread0.squashedLoads 4403 # Number of loads squashed -system.cpu3.iew.lsq.thread0.ignoredResponses 27 # Number of memory responses ignored because the instruction is squashed -system.cpu3.iew.lsq.thread0.memOrderViolation 34 # Number of memory ordering violations -system.cpu3.iew.lsq.thread0.squashedStores 2689 # Number of stores squashed +system.cpu3.iew.lsq.thread0.squashedLoads 4474 # Number of loads squashed +system.cpu3.iew.lsq.thread0.ignoredResponses 40 # Number of memory responses ignored because the instruction is squashed +system.cpu3.iew.lsq.thread0.memOrderViolation 38 # Number of memory ordering violations +system.cpu3.iew.lsq.thread0.squashedStores 2718 # Number of stores squashed system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu3.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu3.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu3.iew.iewSquashCycles 2482 # Number of cycles IEW is squashing -system.cpu3.iew.iewBlockCycles 11408 # Number of cycles IEW is blocking -system.cpu3.iew.iewUnblockCycles 53 # Number of cycles IEW is unblocking -system.cpu3.iew.iewDispatchedInsts 259073 # Number of instructions dispatched to IQ -system.cpu3.iew.iewDispSquashedInsts 473 # Number of squashed instructions skipped by dispatch -system.cpu3.iew.iewDispLoadInsts 69050 # Number of dispatched load instructions -system.cpu3.iew.iewDispStoreInsts 30771 # Number of dispatched store instructions -system.cpu3.iew.iewDispNonSpecInsts 1541 # Number of dispatched non-speculative instructions -system.cpu3.iew.iewIQFullEvents 26 # Number of times the IQ has become full, causing a stall +system.cpu3.iew.iewSquashCycles 2405 # Number of cycles IEW is squashing +system.cpu3.iew.iewBlockCycles 9114 # Number of cycles IEW is blocking +system.cpu3.iew.iewUnblockCycles 55 # Number of cycles IEW is unblocking +system.cpu3.iew.iewDispatchedInsts 311067 # Number of instructions dispatched to IQ +system.cpu3.iew.iewDispSquashedInsts 408 # Number of squashed instructions skipped by dispatch +system.cpu3.iew.iewDispLoadInsts 87479 # Number of dispatched load instructions +system.cpu3.iew.iewDispStoreInsts 41118 # Number of dispatched store instructions +system.cpu3.iew.iewDispNonSpecInsts 1508 # Number of dispatched non-speculative instructions +system.cpu3.iew.iewIQFullEvents 34 # Number of times the IQ has become full, causing a stall system.cpu3.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu3.iew.memOrderViolationEvents 34 # Number of memory order violations -system.cpu3.iew.predictedTakenIncorrect 490 # Number of branches that were predicted taken incorrectly -system.cpu3.iew.predictedNotTakenIncorrect 2580 # Number of branches that were predicted not taken incorrectly -system.cpu3.iew.branchMispredicts 3070 # Number of branch mispredicts detected at execute -system.cpu3.iew.iewExecutedInsts 213662 # Number of executed instructions -system.cpu3.iew.iewExecLoadInsts 67471 # Number of load instructions executed -system.cpu3.iew.iewExecSquashedInsts 2653 # Number of squashed instructions skipped in execute +system.cpu3.iew.memOrderViolationEvents 38 # Number of memory order violations +system.cpu3.iew.predictedTakenIncorrect 450 # Number of branches that were predicted taken incorrectly +system.cpu3.iew.predictedNotTakenIncorrect 2479 # Number of branches that were predicted not taken incorrectly +system.cpu3.iew.branchMispredicts 2929 # Number of branch mispredicts detected at execute +system.cpu3.iew.iewExecutedInsts 257518 # Number of executed instructions +system.cpu3.iew.iewExecLoadInsts 85797 # Number of load instructions executed +system.cpu3.iew.iewExecSquashedInsts 2579 # Number of squashed instructions skipped in execute system.cpu3.iew.exec_swp 0 # number of swp insts executed -system.cpu3.iew.exec_nop 34982 # number of nop insts executed -system.cpu3.iew.exec_refs 96956 # number of memory reference insts executed -system.cpu3.iew.exec_branches 45328 # Number of branches executed -system.cpu3.iew.exec_stores 29485 # Number of stores executed -system.cpu3.iew.exec_rate 1.114245 # Inst execution rate -system.cpu3.iew.wb_sent 212766 # cumulative count of insts sent to commit -system.cpu3.iew.wb_count 212257 # cumulative count of insts written-back -system.cpu3.iew.wb_producers 115033 # num instructions producing a value -system.cpu3.iew.wb_consumers 122695 # num instructions consuming a value -system.cpu3.iew.wb_rate 1.106918 # insts written-back per cycle -system.cpu3.iew.wb_fanout 0.937552 # average fanout of values written-back -system.cpu3.commit.commitSquashedInsts 26335 # The number of squashed insts skipped by commit -system.cpu3.commit.commitNonSpecStalls 9719 # The number of times commit has been forced to stall to communicate backwards -system.cpu3.commit.branchMispredicts 2406 # The number of times a branch was mispredicted -system.cpu3.commit.committed_per_cycle::samples 185183 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::mean 1.256660 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::stdev 1.878907 # Number of insts commited each cycle +system.cpu3.iew.exec_nop 43055 # number of nop insts executed +system.cpu3.iew.exec_refs 125534 # number of memory reference insts executed +system.cpu3.iew.exec_branches 53219 # Number of branches executed +system.cpu3.iew.exec_stores 39737 # Number of stores executed +system.cpu3.iew.exec_rate 1.347810 # Inst execution rate +system.cpu3.iew.wb_sent 256666 # cumulative count of insts sent to commit +system.cpu3.iew.wb_count 256163 # cumulative count of insts written-back +system.cpu3.iew.wb_producers 143359 # num instructions producing a value +system.cpu3.iew.wb_consumers 150866 # num instructions consuming a value +system.cpu3.iew.wb_rate 1.340718 # insts written-back per cycle +system.cpu3.iew.wb_fanout 0.950241 # average fanout of values written-back +system.cpu3.commit.commitSquashedInsts 25509 # The number of squashed insts skipped by commit +system.cpu3.commit.commitNonSpecStalls 7449 # The number of times commit has been forced to stall to communicate backwards +system.cpu3.commit.branchMispredicts 2329 # The number of times a branch was mispredicted +system.cpu3.commit.committed_per_cycle::samples 184454 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::mean 1.547985 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::stdev 2.017686 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::0 99076 53.50% 53.50% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::1 41559 22.44% 75.94% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::2 5388 2.91% 78.85% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::3 10319 5.57% 84.43% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::4 1252 0.68% 85.10% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::5 24567 13.27% 98.37% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::6 787 0.42% 98.79% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::7 1025 0.55% 99.35% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::8 1210 0.65% 100.00% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::0 82386 44.66% 44.66% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::1 49463 26.82% 71.48% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::2 5369 2.91% 74.39% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::3 8071 4.38% 78.77% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::4 1252 0.68% 79.45% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::5 34869 18.90% 98.35% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::6 786 0.43% 98.78% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::7 1015 0.55% 99.33% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::8 1243 0.67% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::total 185183 # Number of insts commited each cycle -system.cpu3.commit.committedInsts 232712 # Number of instructions committed -system.cpu3.commit.committedOps 232712 # Number of ops (including micro ops) committed +system.cpu3.commit.committed_per_cycle::total 184454 # Number of insts commited each cycle +system.cpu3.commit.committedInsts 285532 # Number of instructions committed +system.cpu3.commit.committedOps 285532 # Number of ops (including micro ops) committed system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu3.commit.refs 92729 # Number of memory references committed -system.cpu3.commit.loads 64647 # Number of loads committed -system.cpu3.commit.membars 9005 # Number of memory barriers committed -system.cpu3.commit.branches 43044 # Number of branches committed +system.cpu3.commit.refs 121405 # Number of memory references committed +system.cpu3.commit.loads 83005 # Number of loads committed +system.cpu3.commit.membars 6731 # Number of memory barriers committed +system.cpu3.commit.branches 51096 # Number of branches committed system.cpu3.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu3.commit.int_insts 157897 # Number of committed integer instructions. +system.cpu3.commit.int_insts 194617 # Number of committed integer instructions. system.cpu3.commit.function_calls 322 # Number of function calls committed. -system.cpu3.commit.op_class_0::No_OpClass 33834 14.54% 14.54% # Class of committed instruction -system.cpu3.commit.op_class_0::IntAlu 97144 41.74% 56.28% # Class of committed instruction -system.cpu3.commit.op_class_0::IntMult 0 0.00% 56.28% # Class of committed instruction -system.cpu3.commit.op_class_0::IntDiv 0 0.00% 56.28% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 56.28% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 56.28% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 56.28% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatMult 0 0.00% 56.28% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 56.28% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 56.28% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 56.28% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 56.28% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 56.28% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 56.28% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 56.28% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 56.28% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMult 0 0.00% 56.28% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 56.28% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdShift 0 0.00% 56.28% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 56.28% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 56.28% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 56.28% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 56.28% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 56.28% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 56.28% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 56.28% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMisc 0 0.00% 56.28% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 56.28% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 56.28% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 56.28% # Class of committed instruction -system.cpu3.commit.op_class_0::MemRead 73652 31.65% 87.93% # Class of committed instruction -system.cpu3.commit.op_class_0::MemWrite 28082 12.07% 100.00% # Class of committed instruction +system.cpu3.commit.op_class_0::No_OpClass 41882 14.67% 14.67% # Class of committed instruction +system.cpu3.commit.op_class_0::IntAlu 115514 40.46% 55.12% # Class of committed instruction +system.cpu3.commit.op_class_0::IntMult 0 0.00% 55.12% # Class of committed instruction +system.cpu3.commit.op_class_0::IntDiv 0 0.00% 55.12% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 55.12% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 55.12% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 55.12% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatMult 0 0.00% 55.12% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 55.12% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 55.12% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 55.12% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 55.12% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 55.12% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 55.12% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 55.12% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 55.12% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMult 0 0.00% 55.12% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 55.12% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdShift 0 0.00% 55.12% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 55.12% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 55.12% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 55.12% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 55.12% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 55.12% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 55.12% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 55.12% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMisc 0 0.00% 55.12% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 55.12% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.12% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.12% # Class of committed instruction +system.cpu3.commit.op_class_0::MemRead 89736 31.43% 86.55% # Class of committed instruction +system.cpu3.commit.op_class_0::MemWrite 38400 13.45% 100.00% # Class of committed instruction system.cpu3.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu3.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu3.commit.op_class_0::total 232712 # Class of committed instruction -system.cpu3.commit.bw_lim_events 1210 # number cycles where commit BW limit reached -system.cpu3.rob.rob_reads 442434 # The number of ROB reads -system.cpu3.rob.rob_writes 523106 # The number of ROB writes -system.cpu3.timesIdled 214 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu3.idleCycles 1622 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu3.quiesceCycles 48179 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu3.committedInsts 189873 # Number of Instructions Simulated -system.cpu3.committedOps 189873 # Number of Ops (including micro ops) Simulated -system.cpu3.cpi 1.009912 # CPI: Cycles Per Instruction -system.cpu3.cpi_total 1.009912 # CPI: Total CPI of All Threads -system.cpu3.ipc 0.990185 # IPC: Instructions Per Cycle -system.cpu3.ipc_total 0.990185 # IPC: Total IPC of All Threads -system.cpu3.int_regfile_reads 355771 # number of integer regfile reads -system.cpu3.int_regfile_writes 167240 # number of integer regfile writes +system.cpu3.commit.op_class_0::total 285532 # Class of committed instruction +system.cpu3.commit.bw_lim_events 1243 # number cycles where commit BW limit reached +system.cpu3.rob.rob_reads 493666 # The number of ROB reads +system.cpu3.rob.rob_writes 626988 # The number of ROB writes +system.cpu3.timesIdled 229 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu3.idleCycles 1756 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu3.quiesceCycles 50157 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu3.committedInsts 236919 # Number of Instructions Simulated +system.cpu3.committedOps 236919 # Number of Ops (including micro ops) Simulated +system.cpu3.cpi 0.806453 # CPI: Cycles Per Instruction +system.cpu3.cpi_total 0.806453 # CPI: Total CPI of All Threads +system.cpu3.ipc 1.239998 # IPC: Instructions Per Cycle +system.cpu3.ipc_total 1.239998 # IPC: Total IPC of All Threads +system.cpu3.int_regfile_reads 440410 # number of integer regfile reads +system.cpu3.int_regfile_writes 205469 # number of integer regfile writes system.cpu3.fp_regfile_writes 64 # number of floating regfile writes -system.cpu3.misc_regfile_reads 98845 # number of misc regfile reads +system.cpu3.misc_regfile_reads 127408 # number of misc regfile reads system.cpu3.misc_regfile_writes 648 # number of misc regfile writes -system.cpu3.dcache.tags.pwrStateResidencyTicks::UNDEFINED 123936000 # Cumulative time (in ticks) in various power states +system.cpu3.dcache.tags.pwrStateResidencyTicks::UNDEFINED 124830000 # Cumulative time (in ticks) in various power states system.cpu3.dcache.tags.replacements 0 # number of replacements -system.cpu3.dcache.tags.tagsinuse 24.519752 # Cycle average of tags in use -system.cpu3.dcache.tags.total_refs 35385 # Total number of references to valid blocks. -system.cpu3.dcache.tags.sampled_refs 30 # Sample count of references to valid blocks. -system.cpu3.dcache.tags.avg_refs 1179.500000 # Average number of references to valid blocks. +system.cpu3.dcache.tags.tagsinuse 25.184575 # Cycle average of tags in use +system.cpu3.dcache.tags.total_refs 45468 # Total number of references to valid blocks. +system.cpu3.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. +system.cpu3.dcache.tags.avg_refs 1567.862069 # Average number of references to valid blocks. system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.dcache.tags.occ_blocks::cpu3.data 24.519752 # Average occupied blocks per requestor -system.cpu3.dcache.tags.occ_percent::cpu3.data 0.047890 # Average percentage of cache occupancy -system.cpu3.dcache.tags.occ_percent::total 0.047890 # Average percentage of cache occupancy -system.cpu3.dcache.tags.occ_task_id_blocks::1024 30 # Occupied blocks per task id -system.cpu3.dcache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id +system.cpu3.dcache.tags.occ_blocks::cpu3.data 25.184575 # Average occupied blocks per requestor +system.cpu3.dcache.tags.occ_percent::cpu3.data 0.049189 # Average percentage of cache occupancy +system.cpu3.dcache.tags.occ_percent::total 0.049189 # Average percentage of cache occupancy +system.cpu3.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id system.cpu3.dcache.tags.age_task_id_blocks_1024::1 29 # Occupied blocks per task id -system.cpu3.dcache.tags.occ_task_id_percent::1024 0.058594 # Percentage of cache occupancy per task id -system.cpu3.dcache.tags.tag_accesses 285185 # Number of tag accesses -system.cpu3.dcache.tags.data_accesses 285185 # Number of data accesses -system.cpu3.dcache.pwrStateResidencyTicks::UNDEFINED 123936000 # Cumulative time (in ticks) in various power states -system.cpu3.dcache.ReadReq_hits::cpu3.data 42713 # number of ReadReq hits -system.cpu3.dcache.ReadReq_hits::total 42713 # number of ReadReq hits -system.cpu3.dcache.WriteReq_hits::cpu3.data 27877 # number of WriteReq hits -system.cpu3.dcache.WriteReq_hits::total 27877 # number of WriteReq hits -system.cpu3.dcache.SwapReq_hits::cpu3.data 16 # number of SwapReq hits -system.cpu3.dcache.SwapReq_hits::total 16 # number of SwapReq hits -system.cpu3.dcache.demand_hits::cpu3.data 70590 # number of demand (read+write) hits -system.cpu3.dcache.demand_hits::total 70590 # number of demand (read+write) hits -system.cpu3.dcache.overall_hits::cpu3.data 70590 # number of overall hits -system.cpu3.dcache.overall_hits::total 70590 # number of overall hits -system.cpu3.dcache.ReadReq_misses::cpu3.data 439 # number of ReadReq misses -system.cpu3.dcache.ReadReq_misses::total 439 # number of ReadReq misses -system.cpu3.dcache.WriteReq_misses::cpu3.data 137 # number of WriteReq misses -system.cpu3.dcache.WriteReq_misses::total 137 # number of WriteReq misses -system.cpu3.dcache.SwapReq_misses::cpu3.data 52 # number of SwapReq misses -system.cpu3.dcache.SwapReq_misses::total 52 # number of SwapReq misses -system.cpu3.dcache.demand_misses::cpu3.data 576 # number of demand (read+write) misses -system.cpu3.dcache.demand_misses::total 576 # number of demand (read+write) misses -system.cpu3.dcache.overall_misses::cpu3.data 576 # number of overall misses -system.cpu3.dcache.overall_misses::total 576 # number of overall misses -system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 3185500 # number of ReadReq miss cycles -system.cpu3.dcache.ReadReq_miss_latency::total 3185500 # number of ReadReq miss cycles -system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 2743000 # number of WriteReq miss cycles -system.cpu3.dcache.WriteReq_miss_latency::total 2743000 # number of WriteReq miss cycles -system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 334000 # number of SwapReq miss cycles -system.cpu3.dcache.SwapReq_miss_latency::total 334000 # number of SwapReq miss cycles -system.cpu3.dcache.demand_miss_latency::cpu3.data 5928500 # number of demand (read+write) miss cycles -system.cpu3.dcache.demand_miss_latency::total 5928500 # number of demand (read+write) miss cycles -system.cpu3.dcache.overall_miss_latency::cpu3.data 5928500 # number of overall miss cycles -system.cpu3.dcache.overall_miss_latency::total 5928500 # number of overall miss cycles -system.cpu3.dcache.ReadReq_accesses::cpu3.data 43152 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.ReadReq_accesses::total 43152 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses::cpu3.data 28014 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses::total 28014 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.SwapReq_accesses::cpu3.data 68 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.SwapReq_accesses::total 68 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.demand_accesses::cpu3.data 71166 # number of demand (read+write) accesses -system.cpu3.dcache.demand_accesses::total 71166 # number of demand (read+write) accesses -system.cpu3.dcache.overall_accesses::cpu3.data 71166 # number of overall (read+write) accesses -system.cpu3.dcache.overall_accesses::total 71166 # number of overall (read+write) accesses -system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.010173 # miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_miss_rate::total 0.010173 # miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.004890 # miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_miss_rate::total 0.004890 # miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.764706 # miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_miss_rate::total 0.764706 # miss rate for SwapReq accesses -system.cpu3.dcache.demand_miss_rate::cpu3.data 0.008094 # miss rate for demand accesses -system.cpu3.dcache.demand_miss_rate::total 0.008094 # miss rate for demand accesses -system.cpu3.dcache.overall_miss_rate::cpu3.data 0.008094 # miss rate for overall accesses -system.cpu3.dcache.overall_miss_rate::total 0.008094 # miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 7256.264237 # average ReadReq miss latency -system.cpu3.dcache.ReadReq_avg_miss_latency::total 7256.264237 # average ReadReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 20021.897810 # average WriteReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::total 20021.897810 # average WriteReq miss latency -system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 6423.076923 # average SwapReq miss latency -system.cpu3.dcache.SwapReq_avg_miss_latency::total 6423.076923 # average SwapReq miss latency -system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 10292.534722 # average overall miss latency -system.cpu3.dcache.demand_avg_miss_latency::total 10292.534722 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 10292.534722 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::total 10292.534722 # average overall miss latency +system.cpu3.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id +system.cpu3.dcache.tags.tag_accesses 358446 # Number of tag accesses +system.cpu3.dcache.tags.data_accesses 358446 # Number of data accesses +system.cpu3.dcache.pwrStateResidencyTicks::UNDEFINED 124830000 # Cumulative time (in ticks) in various power states +system.cpu3.dcache.ReadReq_hits::cpu3.data 50650 # number of ReadReq hits +system.cpu3.dcache.ReadReq_hits::total 50650 # number of ReadReq hits +system.cpu3.dcache.WriteReq_hits::cpu3.data 38188 # number of WriteReq hits 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demand (read+write) accesses +system.cpu3.dcache.overall_accesses::cpu3.data 89474 # number of overall (read+write) accesses +system.cpu3.dcache.overall_accesses::total 89474 # number of overall (read+write) accesses +system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.009698 # miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_miss_rate::total 0.009698 # miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.003653 # miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_miss_rate::total 0.003653 # miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.833333 # miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_miss_rate::total 0.833333 # miss rate for SwapReq accesses +system.cpu3.dcache.demand_miss_rate::cpu3.data 0.007108 # miss rate for demand accesses +system.cpu3.dcache.demand_miss_rate::total 0.007108 # miss rate for demand accesses +system.cpu3.dcache.overall_miss_rate::cpu3.data 0.007108 # miss rate for overall accesses +system.cpu3.dcache.overall_miss_rate::total 0.007108 # miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 7261.088710 # average ReadReq miss latency +system.cpu3.dcache.ReadReq_avg_miss_latency::total 7261.088710 # average ReadReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 20810.714286 # average WriteReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::total 20810.714286 # average WriteReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 5941.666667 # average SwapReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency::total 5941.666667 # average SwapReq miss latency +system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 10243.710692 # average overall miss latency +system.cpu3.dcache.demand_avg_miss_latency::total 10243.710692 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 10243.710692 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::total 10243.710692 # average overall miss latency system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 281 # number of ReadReq MSHR hits -system.cpu3.dcache.ReadReq_mshr_hits::total 281 # number of ReadReq MSHR hits -system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 33 # number of WriteReq MSHR hits -system.cpu3.dcache.WriteReq_mshr_hits::total 33 # number of WriteReq MSHR hits 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13370.192308 # average WriteReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 13370.192308 # average WriteReq mshr miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 5529.411765 # average SwapReq mshr miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 5529.411765 # average SwapReq mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 9444.656489 # average overall mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::total 9444.656489 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 9444.656489 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::total 9444.656489 # average overall mshr miss latency -system.cpu3.icache.tags.pwrStateResidencyTicks::UNDEFINED 123936000 # Cumulative time (in ticks) in various power states -system.cpu3.icache.tags.replacements 578 # number of replacements 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# number of WriteReq MSHR misses +system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 59 # number of SwapReq MSHR misses +system.cpu3.dcache.SwapReq_mshr_misses::total 59 # number of SwapReq MSHR misses +system.cpu3.dcache.demand_mshr_misses::cpu3.data 275 # number of demand (read+write) MSHR misses +system.cpu3.dcache.demand_mshr_misses::total 275 # number of demand (read+write) MSHR misses +system.cpu3.dcache.overall_mshr_misses::cpu3.data 275 # number of overall MSHR misses +system.cpu3.dcache.overall_mshr_misses::total 275 # number of overall MSHR misses +system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1125000 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1125000 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1450500 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1450500 # number of WriteReq MSHR miss cycles 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latency -system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13865.911800 # average overall miss latency -system.cpu3.icache.demand_avg_miss_latency::total 13865.911800 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13865.911800 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::total 13865.911800 # average overall miss latency -system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu3.icache.tags.occ_blocks::cpu3.inst 96.347148 # Average occupied blocks per requestor +system.cpu3.icache.tags.occ_percent::cpu3.inst 0.188178 # Average percentage of cache occupancy +system.cpu3.icache.tags.occ_percent::total 0.188178 # Average percentage of cache occupancy +system.cpu3.icache.tags.occ_task_id_blocks::1024 138 # Occupied blocks per task id +system.cpu3.icache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id +system.cpu3.icache.tags.age_task_id_blocks_1024::1 119 # Occupied blocks per task id +system.cpu3.icache.tags.occ_task_id_percent::1024 0.269531 # Percentage of cache occupancy per task id +system.cpu3.icache.tags.tag_accesses 28596 # Number of tag accesses +system.cpu3.icache.tags.data_accesses 28596 # Number of data accesses +system.cpu3.icache.pwrStateResidencyTicks::UNDEFINED 124830000 # Cumulative time (in ticks) in various power states +system.cpu3.icache.ReadReq_hits::cpu3.inst 27016 # number of ReadReq hits +system.cpu3.icache.ReadReq_hits::total 27016 # number of ReadReq hits +system.cpu3.icache.demand_hits::cpu3.inst 27016 # number of demand (read+write) hits +system.cpu3.icache.demand_hits::total 27016 # number of demand (read+write) hits +system.cpu3.icache.overall_hits::cpu3.inst 27016 # number of overall hits +system.cpu3.icache.overall_hits::total 27016 # number of overall hits +system.cpu3.icache.ReadReq_misses::cpu3.inst 856 # number of ReadReq misses +system.cpu3.icache.ReadReq_misses::total 856 # number of ReadReq misses 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-system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu3.icache.avg_blocked_cycles::no_mshrs 17 # average number of cycles each access was blocked system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu3.icache.writebacks::writebacks 578 # number of writebacks -system.cpu3.icache.writebacks::total 578 # number of writebacks -system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 126 # number of ReadReq MSHR hits -system.cpu3.icache.ReadReq_mshr_hits::total 126 # number of ReadReq MSHR hits -system.cpu3.icache.demand_mshr_hits::cpu3.inst 126 # number of demand (read+write) MSHR hits -system.cpu3.icache.demand_mshr_hits::total 126 # number of demand (read+write) MSHR hits -system.cpu3.icache.overall_mshr_hits::cpu3.inst 126 # number of overall MSHR hits -system.cpu3.icache.overall_mshr_hits::total 126 # number of overall MSHR hits -system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 713 # number of ReadReq MSHR misses -system.cpu3.icache.ReadReq_mshr_misses::total 713 # number of ReadReq MSHR misses -system.cpu3.icache.demand_mshr_misses::cpu3.inst 713 # number of demand (read+write) MSHR misses -system.cpu3.icache.demand_mshr_misses::total 713 # number of demand (read+write) MSHR misses -system.cpu3.icache.overall_mshr_misses::cpu3.inst 713 # number of overall MSHR misses -system.cpu3.icache.overall_mshr_misses::total 713 # number of overall MSHR misses -system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 10107000 # number of ReadReq MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_latency::total 10107000 # number of ReadReq MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 10107000 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::total 10107000 # number of demand (read+write) MSHR miss cycles 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system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 123936000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 578 # Transaction distribution -system.membus.trans_dist::UpgradeReq 196 # Transaction distribution -system.membus.trans_dist::ReadExReq 183 # Transaction distribution +system.membus.pwrStateResidencyTicks::UNDEFINED 124830000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 585 # Transaction distribution +system.membus.trans_dist::UpgradeReq 194 # Transaction distribution +system.membus.trans_dist::ReadExReq 190 # Transaction distribution system.membus.trans_dist::ReadExResp 131 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 578 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1666 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1666 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 45376 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 45376 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 248 # Total snoops (count) +system.membus.trans_dist::ReadSharedReq 585 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1685 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1685 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 45824 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 45824 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 253 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 957 # Request fanout histogram +system.membus.snoop_fanout::samples 969 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 957 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 969 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 957 # Request fanout histogram -system.membus.reqLayer0.occupancy 877500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 969 # Request fanout histogram +system.membus.reqLayer0.occupancy 889500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 3778750 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 3.0 # Layer utilization (%) -system.toL2Bus.snoop_filter.tot_requests 6322 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 1727 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 3289 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.respLayer1.occupancy 3809250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 3.1 # Layer utilization (%) +system.toL2Bus.snoop_filter.tot_requests 6292 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 1720 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 3250 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 123936000 # Cumulative time (in ticks) in various power states -system.toL2Bus.trans_dist::ReadResp 3509 # Transaction distribution -system.toL2Bus.trans_dist::ReadRespWithInvalidate 3 # Transaction distribution +system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 124830000 # Cumulative time (in ticks) in various power states +system.toL2Bus.trans_dist::ReadResp 3503 # Transaction distribution +system.toL2Bus.trans_dist::ReadRespWithInvalidate 8 # Transaction distribution system.toL2Bus.trans_dist::WritebackDirty 1 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 2125 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 2099 # Transaction distribution system.toL2Bus.trans_dist::CleanEvict 1 # Transaction distribution system.toL2Bus.trans_dist::UpgradeReq 284 # Transaction distribution system.toL2Bus.trans_dist::UpgradeResp 284 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 398 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 398 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 2823 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 690 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1838 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 602 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1930 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 372 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 1998 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 378 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 2004 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 362 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 9484 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 72000 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.trans_dist::ReadExReq 395 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 395 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 2812 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 700 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1784 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 599 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1936 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 373 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 1968 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 372 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 2034 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 380 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 9446 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 69632 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 11264 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 79552 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1664 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 82432 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 79744 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1728 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 81024 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 1664 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 82624 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 83840 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 332800 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 1032 # Total snoops (count) -system.toL2Bus.snoopTraffic 53504 # Total snoop traffic (bytes) -system.toL2Bus.snoop_fanout::samples 4195 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.291538 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 1.103863 # Request fanout histogram +system.toL2Bus.pkt_size::total 330496 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 1036 # Total snoops (count) +system.toL2Bus.snoopTraffic 53888 # Total snoop traffic (bytes) +system.toL2Bus.snoop_fanout::samples 4191 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.288475 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 1.109326 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 1306 31.13% 31.13% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 1176 28.03% 59.17% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 897 21.38% 80.55% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 816 19.45% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 1322 31.54% 31.54% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 1164 27.77% 59.32% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 879 20.97% 80.29% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 826 19.71% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::5 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram @@ -2870,24 +2880,24 @@ system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Re system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 4195 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 5296980 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 4.3 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1068997 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 0.9 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 528987 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 4191 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 5261968 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 4.2 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 1043496 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 0.8 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 528992 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 1032995 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 1037993 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.8 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 438456 # Layer occupancy (ticks) -system.toL2Bus.respLayer3.utilization 0.4 # Layer utilization (%) -system.toL2Bus.respLayer4.occupancy 1069486 # Layer occupancy (ticks) -system.toL2Bus.respLayer4.utilization 0.9 # Layer utilization (%) -system.toL2Bus.respLayer5.occupancy 439965 # Layer occupancy (ticks) -system.toL2Bus.respLayer5.utilization 0.4 # Layer utilization (%) -system.toL2Bus.respLayer6.occupancy 1070997 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 434459 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.utilization 0.3 # Layer utilization (%) +system.toL2Bus.respLayer4.occupancy 1056988 # Layer occupancy (ticks) +system.toL2Bus.respLayer4.utilization 0.8 # Layer utilization (%) +system.toL2Bus.respLayer5.occupancy 424982 # Layer occupancy (ticks) +system.toL2Bus.respLayer5.utilization 0.3 # Layer utilization (%) +system.toL2Bus.respLayer6.occupancy 1087497 # Layer occupancy (ticks) system.toL2Bus.respLayer6.utilization 0.9 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 415480 # Layer occupancy (ticks) -system.toL2Bus.respLayer7.utilization 0.3 # Layer utilization (%) +system.toL2Bus.respLayer7.occupancy 445966 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.utilization 0.4 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/60.gpu-randomtest/ref/x86/linux/gpu-randomtest-ruby-GPU_RfO/config.ini b/tests/quick/se/60.gpu-randomtest/ref/x86/linux/gpu-randomtest-ruby-GPU_RfO/config.ini index 5ac78b2ee..5e98acfda 100644 --- a/tests/quick/se/60.gpu-randomtest/ref/x86/linux/gpu-randomtest-ruby-GPU_RfO/config.ini +++ b/tests/quick/se/60.gpu-randomtest/ref/x86/linux/gpu-randomtest-ruby-GPU_RfO/config.ini @@ -14,6 +14,7 @@ children=clk_domain cp_cntrl0 cpu dir_cntrl0 dvfs_handler mem_ctrls ruby sqc_cnt boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 exit_on_work_items=false init_param=0 @@ -22,11 +23,15 @@ kernel_addr_check=true load_addr_mask=1099511627775 load_offset=0 mem_mode=timing -mem_ranges=0:268435455 +mem_ranges=0:268435455:0:0:0:0 memories=system.mem_ctrls mmap_using_noreserve=false multi_thread=false num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null readfile= symbolfile= thermal_components= @@ -58,11 +63,16 @@ L2cache=system.cp_cntrl0.L2cache buffer_size=0 clk_domain=system.clk_domain cluster_id=0 +default_p_state=UNDEFINED eventq_index=0 issue_latency=15 l2_hit_latency=18 mandatoryQueue=system.cp_cntrl0.mandatoryQueue number_of_TBEs=256 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null probeToCore=system.cp_cntrl0.probeToCore recycle_latency=10 requestFromCore=system.cp_cntrl0.requestFromCore @@ -220,17 +230,22 @@ coreid=0 dcache=system.cp_cntrl0.L1D0cache dcache_hit_latency=2 deadlock_threshold=500000 +default_p_state=UNDEFINED eventq_index=0 +garnet_standalone=false icache=system.cp_cntrl0.L1Icache icache_hit_latency=2 is_cpu_sequencer=true max_outstanding_requests=16 no_retry_on_stall=true +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null ruby_system=system.ruby support_data_reqs=true support_inst_reqs=true system=system -using_network_tester=false using_ruby_tester=true version=0 slave=system.cpu.cpuInstDataPort[0] @@ -242,17 +257,22 @@ coreid=1 dcache=system.cp_cntrl0.L1D1cache dcache_hit_latency=2 deadlock_threshold=500000 +default_p_state=UNDEFINED eventq_index=0 +garnet_standalone=false icache=system.cp_cntrl0.L1Icache icache_hit_latency=2 is_cpu_sequencer=true max_outstanding_requests=16 no_retry_on_stall=true +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null ruby_system=system.ruby support_data_reqs=true support_inst_reqs=true system=system -using_network_tester=false using_ruby_tester=true version=1 slave=system.cpu.cpuInstDataPort[1] @@ -278,8 +298,13 @@ check_flush=false checks_to_complete=100 clk_domain=system.clk_domain deadlock_threshold=50000 +default_p_state=UNDEFINED eventq_index=0 num_cpus=12 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null system=system wakeup_frequency=10 cpuDataPort=system.tcp_cntrl0.coalescer.slave[0] system.tcp_cntrl1.coalescer.slave[0] system.tcp_cntrl2.coalescer.slave[0] system.tcp_cntrl3.coalescer.slave[0] system.tcp_cntrl4.coalescer.slave[0] system.tcp_cntrl5.coalescer.slave[0] system.tcp_cntrl6.coalescer.slave[0] system.tcp_cntrl7.coalescer.slave[0] @@ -296,11 +321,16 @@ TCC_select_num_bits=0 buffer_size=0 clk_domain=system.clk_domain cluster_id=0 +default_p_state=UNDEFINED directory=system.dir_cntrl0.directory eventq_index=0 l3_hit_latency=15 noTCCdir=false number_of_TBEs=20480 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null probeToCore=system.dir_cntrl0.probeToCore recycle_latency=10 requestFromCores=system.dir_cntrl0.requestFromCores @@ -420,27 +450,27 @@ transition_latency=100000 [system.mem_ctrls] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -452,6 +482,7 @@ burst_length=8 channels=1 clk_domain=system.clk_domain conf_table_reported=true +default_p_state=UNDEFINED device_bus_width=8 device_rowbuffer_size=1024 device_size=536870912 @@ -459,12 +490,17 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 page_policy=open_adaptive -range=0:268435455 +power_model=Null +range=0:268435455:5:19:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10 @@ -486,9 +522,9 @@ tRTW=3 tWR=15 tWTR=8 tXAW=30 -tXP=0 +tXP=6 tXPDLL=0 -tXS=0 +tXS=270 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 @@ -502,12 +538,17 @@ access_backing_store=false all_instructions=false block_size_bytes=64 clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED eventq_index=0 hot_lines=false memory_size_bits=48 num_of_sequencers=12 number_of_virtual_networks=10 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 phys_mem=Null +power_model=Null randomization=true [system.ruby.clk_domain] @@ -520,18 +561,23 @@ voltage_domain=system.voltage_domain [system.ruby.network] type=SimpleNetwork -children=ext_links00 ext_links01 ext_links02 ext_links03 ext_links04 ext_links05 ext_links06 ext_links07 ext_links08 ext_links09 ext_links10 ext_links11 ext_links12 ext_links13 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_link_buffers20 int_link_buffers21 int_link_buffers22 int_link_buffers23 int_link_buffers24 int_link_buffers25 int_link_buffers26 int_link_buffers27 int_link_buffers28 int_link_buffers29 int_link_buffers30 int_link_buffers31 int_link_buffers32 int_link_buffers33 int_link_buffers34 int_link_buffers35 int_link_buffers36 int_link_buffers37 int_link_buffers38 int_link_buffers39 int_links0 int_links1 +children=ext_links00 ext_links01 ext_links02 ext_links03 ext_links04 ext_links05 ext_links06 ext_links07 ext_links08 ext_links09 ext_links10 ext_links11 ext_links12 ext_links13 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_link_buffers20 int_link_buffers21 int_link_buffers22 int_link_buffers23 int_link_buffers24 int_link_buffers25 int_link_buffers26 int_link_buffers27 int_link_buffers28 int_link_buffers29 int_link_buffers30 int_link_buffers31 int_link_buffers32 int_link_buffers33 int_link_buffers34 int_link_buffers35 int_link_buffers36 int_link_buffers37 int_link_buffers38 int_link_buffers39 int_link_buffers40 int_link_buffers41 int_link_buffers42 int_link_buffers43 int_link_buffers44 int_link_buffers45 int_link_buffers46 int_link_buffers47 int_link_buffers48 int_link_buffers49 int_link_buffers50 int_link_buffers51 int_link_buffers52 int_link_buffers53 int_link_buffers54 int_link_buffers55 int_link_buffers56 int_link_buffers57 int_link_buffers58 int_link_buffers59 int_link_buffers60 int_link_buffers61 int_link_buffers62 int_link_buffers63 int_link_buffers64 int_link_buffers65 int_link_buffers66 int_link_buffers67 int_link_buffers68 int_link_buffers69 int_link_buffers70 int_link_buffers71 int_link_buffers72 int_link_buffers73 int_link_buffers74 int_link_buffers75 int_link_buffers76 int_link_buffers77 int_link_buffers78 int_link_buffers79 int_links0 int_links1 int_links2 int_links3 adaptive_routing=false buffer_size=0 clk_domain=system.ruby.clk_domain control_msg_size=8 +default_p_state=UNDEFINED endpoint_bandwidth=1000 eventq_index=0 ext_links=system.ruby.network.ext_links00 system.ruby.network.ext_links01 system.ruby.network.ext_links02 system.ruby.network.ext_links03 system.ruby.network.ext_links04 system.ruby.network.ext_links05 system.ruby.network.ext_links06 system.ruby.network.ext_links07 system.ruby.network.ext_links08 system.ruby.network.ext_links09 system.ruby.network.ext_links10 system.ruby.network.ext_links11 system.ruby.network.ext_links12 system.ruby.network.ext_links13 -int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19 system.ruby.network.int_link_buffers20 system.ruby.network.int_link_buffers21 system.ruby.network.int_link_buffers22 system.ruby.network.int_link_buffers23 system.ruby.network.int_link_buffers24 system.ruby.network.int_link_buffers25 system.ruby.network.int_link_buffers26 system.ruby.network.int_link_buffers27 system.ruby.network.int_link_buffers28 system.ruby.network.int_link_buffers29 system.ruby.network.int_link_buffers30 system.ruby.network.int_link_buffers31 system.ruby.network.int_link_buffers32 system.ruby.network.int_link_buffers33 system.ruby.network.int_link_buffers34 system.ruby.network.int_link_buffers35 system.ruby.network.int_link_buffers36 system.ruby.network.int_link_buffers37 system.ruby.network.int_link_buffers38 system.ruby.network.int_link_buffers39 -int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 +int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19 system.ruby.network.int_link_buffers20 system.ruby.network.int_link_buffers21 system.ruby.network.int_link_buffers22 system.ruby.network.int_link_buffers23 system.ruby.network.int_link_buffers24 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system.ruby.network.int_link_buffers50 system.ruby.network.int_link_buffers51 system.ruby.network.int_link_buffers52 system.ruby.network.int_link_buffers53 system.ruby.network.int_link_buffers54 system.ruby.network.int_link_buffers55 system.ruby.network.int_link_buffers56 system.ruby.network.int_link_buffers57 system.ruby.network.int_link_buffers58 system.ruby.network.int_link_buffers59 system.ruby.network.int_link_buffers60 system.ruby.network.int_link_buffers61 system.ruby.network.int_link_buffers62 system.ruby.network.int_link_buffers63 system.ruby.network.int_link_buffers64 system.ruby.network.int_link_buffers65 system.ruby.network.int_link_buffers66 system.ruby.network.int_link_buffers67 system.ruby.network.int_link_buffers68 system.ruby.network.int_link_buffers69 system.ruby.network.int_link_buffers70 system.ruby.network.int_link_buffers71 system.ruby.network.int_link_buffers72 system.ruby.network.int_link_buffers73 system.ruby.network.int_link_buffers74 system.ruby.network.int_link_buffers75 system.ruby.network.int_link_buffers76 system.ruby.network.int_link_buffers77 system.ruby.network.int_link_buffers78 system.ruby.network.int_link_buffers79 +int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2 system.ruby.network.int_links3 netifs= number_of_virtual_networks=10 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null routers=system.ruby.network.ext_links00.int_node system.ruby.network.ext_links01.int_node system.ruby.network.ext_links02.int_node ruby_system=system.ruby topology=Crossbar @@ -553,8 +599,14 @@ weight=1 type=Switch children=port_buffers000 port_buffers001 port_buffers002 port_buffers003 port_buffers004 port_buffers005 port_buffers006 port_buffers007 port_buffers008 port_buffers009 port_buffers010 port_buffers011 port_buffers012 port_buffers013 port_buffers014 port_buffers015 port_buffers016 port_buffers017 port_buffers018 port_buffers019 port_buffers020 port_buffers021 port_buffers022 port_buffers023 port_buffers024 port_buffers025 port_buffers026 port_buffers027 port_buffers028 port_buffers029 port_buffers030 port_buffers031 port_buffers032 port_buffers033 port_buffers034 port_buffers035 port_buffers036 port_buffers037 port_buffers038 port_buffers039 port_buffers040 port_buffers041 port_buffers042 port_buffers043 port_buffers044 port_buffers045 port_buffers046 port_buffers047 port_buffers048 port_buffers049 port_buffers050 port_buffers051 port_buffers052 port_buffers053 port_buffers054 port_buffers055 port_buffers056 port_buffers057 port_buffers058 port_buffers059 port_buffers060 port_buffers061 port_buffers062 port_buffers063 port_buffers064 port_buffers065 port_buffers066 port_buffers067 port_buffers068 port_buffers069 port_buffers070 port_buffers071 port_buffers072 port_buffers073 port_buffers074 port_buffers075 port_buffers076 port_buffers077 port_buffers078 port_buffers079 port_buffers080 port_buffers081 port_buffers082 port_buffers083 port_buffers084 port_buffers085 port_buffers086 port_buffers087 port_buffers088 port_buffers089 port_buffers090 port_buffers091 port_buffers092 port_buffers093 port_buffers094 port_buffers095 port_buffers096 port_buffers097 port_buffers098 port_buffers099 port_buffers100 port_buffers101 port_buffers102 port_buffers103 port_buffers104 port_buffers105 port_buffers106 port_buffers107 port_buffers108 port_buffers109 port_buffers110 port_buffers111 port_buffers112 port_buffers113 port_buffers114 port_buffers115 port_buffers116 port_buffers117 port_buffers118 port_buffers119 port_buffers120 port_buffers121 port_buffers122 port_buffers123 port_buffers124 port_buffers125 port_buffers126 port_buffers127 port_buffers128 port_buffers129 port_buffers130 port_buffers131 port_buffers132 port_buffers133 port_buffers134 port_buffers135 port_buffers136 port_buffers137 port_buffers138 port_buffers139 port_buffers140 port_buffers141 port_buffers142 port_buffers143 port_buffers144 port_buffers145 port_buffers146 port_buffers147 port_buffers148 port_buffers149 port_buffers150 port_buffers151 port_buffers152 port_buffers153 port_buffers154 port_buffers155 port_buffers156 port_buffers157 port_buffers158 port_buffers159 clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED eventq_index=0 +latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 port_buffers=system.ruby.network.ext_links00.int_node.port_buffers000 system.ruby.network.ext_links00.int_node.port_buffers001 system.ruby.network.ext_links00.int_node.port_buffers002 system.ruby.network.ext_links00.int_node.port_buffers003 system.ruby.network.ext_links00.int_node.port_buffers004 system.ruby.network.ext_links00.int_node.port_buffers005 system.ruby.network.ext_links00.int_node.port_buffers006 system.ruby.network.ext_links00.int_node.port_buffers007 system.ruby.network.ext_links00.int_node.port_buffers008 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port_buffers003 port_buffers004 port_buffers005 port_buffers006 port_buffers007 port_buffers008 port_buffers009 port_buffers010 port_buffers011 port_buffers012 port_buffers013 port_buffers014 port_buffers015 port_buffers016 port_buffers017 port_buffers018 port_buffers019 port_buffers020 port_buffers021 port_buffers022 port_buffers023 port_buffers024 port_buffers025 port_buffers026 port_buffers027 port_buffers028 port_buffers029 port_buffers030 port_buffers031 port_buffers032 port_buffers033 port_buffers034 port_buffers035 port_buffers036 port_buffers037 port_buffers038 port_buffers039 port_buffers040 port_buffers041 port_buffers042 port_buffers043 port_buffers044 port_buffers045 port_buffers046 port_buffers047 port_buffers048 port_buffers049 port_buffers050 port_buffers051 port_buffers052 port_buffers053 port_buffers054 port_buffers055 port_buffers056 port_buffers057 port_buffers058 port_buffers059 port_buffers060 port_buffers061 port_buffers062 port_buffers063 port_buffers064 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port_buffers127 port_buffers128 port_buffers129 port_buffers130 port_buffers131 port_buffers132 port_buffers133 port_buffers134 port_buffers135 port_buffers136 port_buffers137 port_buffers138 port_buffers139 port_buffers140 port_buffers141 port_buffers142 port_buffers143 port_buffers144 port_buffers145 port_buffers146 port_buffers147 port_buffers148 port_buffers149 clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED eventq_index=0 +latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 port_buffers=system.ruby.network.ext_links01.int_node.port_buffers000 system.ruby.network.ext_links01.int_node.port_buffers001 system.ruby.network.ext_links01.int_node.port_buffers002 system.ruby.network.ext_links01.int_node.port_buffers003 system.ruby.network.ext_links01.int_node.port_buffers004 system.ruby.network.ext_links01.int_node.port_buffers005 system.ruby.network.ext_links01.int_node.port_buffers006 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+p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 port_buffers=system.ruby.network.ext_links02.int_node.port_buffers000 system.ruby.network.ext_links02.int_node.port_buffers001 system.ruby.network.ext_links02.int_node.port_buffers002 system.ruby.network.ext_links02.int_node.port_buffers003 system.ruby.network.ext_links02.int_node.port_buffers004 system.ruby.network.ext_links02.int_node.port_buffers005 system.ruby.network.ext_links02.int_node.port_buffers006 system.ruby.network.ext_links02.int_node.port_buffers007 system.ruby.network.ext_links02.int_node.port_buffers008 system.ruby.network.ext_links02.int_node.port_buffers009 system.ruby.network.ext_links02.int_node.port_buffers010 system.ruby.network.ext_links02.int_node.port_buffers011 system.ruby.network.ext_links02.int_node.port_buffers012 system.ruby.network.ext_links02.int_node.port_buffers013 system.ruby.network.ext_links02.int_node.port_buffers014 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ordered=true randomization=false +[system.ruby.network.int_link_buffers40] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers41] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers42] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers43] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers44] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers45] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers46] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers47] 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+[system.ruby.network.int_link_buffers70] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers71] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers72] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers73] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers74] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers75] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers76] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers77] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers78] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers79] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + [system.ruby.network.int_links0] type=SimpleIntLink bandwidth_factor=512 +dst_inport= +dst_node=system.ruby.network.ext_links01.int_node eventq_index=0 latency=1 link_id=0 -node_a=system.ruby.network.ext_links00.int_node -node_b=system.ruby.network.ext_links01.int_node +src_node=system.ruby.network.ext_links00.int_node +src_outport= weight=1 [system.ruby.network.int_links1] type=SimpleIntLink bandwidth_factor=512 +dst_inport= +dst_node=system.ruby.network.ext_links00.int_node eventq_index=0 latency=1 link_id=1 -node_a=system.ruby.network.ext_links00.int_node -node_b=system.ruby.network.ext_links02.int_node +src_node=system.ruby.network.ext_links01.int_node +src_outport= +weight=1 + +[system.ruby.network.int_links2] +type=SimpleIntLink +bandwidth_factor=512 +dst_inport= +dst_node=system.ruby.network.ext_links02.int_node +eventq_index=0 +latency=1 +link_id=2 +src_node=system.ruby.network.ext_links00.int_node +src_outport= +weight=1 + +[system.ruby.network.int_links3] +type=SimpleIntLink +bandwidth_factor=512 +dst_inport= +dst_node=system.ruby.network.ext_links00.int_node +eventq_index=0 +latency=1 +link_id=3 +src_node=system.ruby.network.ext_links02.int_node +src_outport= weight=1 [system.sqc_cntrl0] @@ -4236,11 +4608,16 @@ TCC_select_num_bits=0 buffer_size=0 clk_domain=system.clk_domain cluster_id=0 +default_p_state=UNDEFINED eventq_index=0 issue_latency=80 l2_hit_latency=18 mandatoryQueue=system.sqc_cntrl0.mandatoryQueue number_of_TBEs=256 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null probeToSQC=system.sqc_cntrl0.probeToSQC recycle_latency=10 requestFromSQC=system.sqc_cntrl0.requestFromSQC @@ -4323,17 +4700,22 @@ coreid=99 dcache=system.sqc_cntrl0.L1cache dcache_hit_latency=1 deadlock_threshold=500000 +default_p_state=UNDEFINED eventq_index=0 +garnet_standalone=false icache=system.sqc_cntrl0.L1cache icache_hit_latency=1 is_cpu_sequencer=false max_outstanding_requests=16 no_retry_on_stall=true +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null ruby_system=system.ruby support_data_reqs=false support_inst_reqs=true system=system -using_network_tester=false using_ruby_tester=true version=18 slave=system.cpu.cpuInstPort[0] @@ -4354,11 +4736,16 @@ TCC_select_num_bits=0 buffer_size=0 clk_domain=system.clk_domain cluster_id=0 +default_p_state=UNDEFINED eventq_index=0 issue_latency=80 l2_hit_latency=18 mandatoryQueue=system.sqc_cntrl1.mandatoryQueue number_of_TBEs=256 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null probeToSQC=system.sqc_cntrl1.probeToSQC recycle_latency=10 requestFromSQC=system.sqc_cntrl1.requestFromSQC @@ -4441,17 +4828,22 @@ coreid=99 dcache=system.sqc_cntrl1.L1cache dcache_hit_latency=1 deadlock_threshold=500000 +default_p_state=UNDEFINED eventq_index=0 +garnet_standalone=false icache=system.sqc_cntrl1.L1cache icache_hit_latency=1 is_cpu_sequencer=false max_outstanding_requests=16 no_retry_on_stall=true +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null ruby_system=system.ruby support_data_reqs=false support_inst_reqs=true system=system -using_network_tester=false using_ruby_tester=true version=19 slave=system.cpu.cpuInstPort[1] @@ -4467,9 +4859,14 @@ master=system.ruby.network.slave[34] [system.sys_port_proxy] type=RubyPortProxy clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 is_cpu_sequencer=true no_retry_on_stall=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null ruby_system=system.ruby support_data_reqs=true support_inst_reqs=true @@ -4486,10 +4883,15 @@ TCC_select_num_bits=0 buffer_size=0 clk_domain=system.clk_domain cluster_id=0 +default_p_state=UNDEFINED eventq_index=0 l2_request_latency=1 l2_response_latency=16 number_of_TBEs=2048 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null recycle_latency=10 responseFromTCC=system.tcc_cntrl0.responseFromTCC responseToTCC=system.tcc_cntrl0.responseToTCC @@ -4581,11 +4983,16 @@ TCC_select_num_bits=0 buffer_size=0 clk_domain=system.clk_domain cluster_id=0 +default_p_state=UNDEFINED directory=system.tccdir_cntrl0.directory directory_latency=6 eventq_index=0 issue_latency=120 number_of_TBEs=1024 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null probeFromNB=system.tccdir_cntrl0.probeFromNB probeToCore=system.tccdir_cntrl0.probeToCore recycle_latency=10 @@ -4730,11 +5137,16 @@ buffer_size=0 clk_domain=system.clk_domain cluster_id=0 coalescer=system.tcp_cntrl0.coalescer +default_p_state=UNDEFINED eventq_index=0 issue_latency=40 l2_hit_latency=18 mandatoryQueue=system.tcp_cntrl0.mandatoryQueue number_of_TBEs=2560 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null probeToTCP=system.tcp_cntrl0.probeToTCP recycle_latency=10 requestFromTCP=system.tcp_cntrl0.requestFromTCP @@ -4780,17 +5192,22 @@ coreid=99 dcache=system.tcp_cntrl0.L1cache dcache_hit_latency=1 deadlock_threshold=500000 +default_p_state=UNDEFINED eventq_index=0 +garnet_standalone=false icache=system.tcp_cntrl0.L1cache icache_hit_latency=1 is_cpu_sequencer=false max_outstanding_requests=2560 no_retry_on_stall=true +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null ruby_system=system.ruby support_data_reqs=true support_inst_reqs=false system=system -using_network_tester=false using_ruby_tester=true version=2 slave=system.cpu.cpuDataPort[0] @@ -4841,17 +5258,22 @@ coreid=99 dcache=system.tcp_cntrl0.L1cache dcache_hit_latency=1 deadlock_threshold=500000 +default_p_state=UNDEFINED eventq_index=0 +garnet_standalone=false icache=system.tcp_cntrl0.L1cache icache_hit_latency=1 is_cpu_sequencer=true max_outstanding_requests=16 no_retry_on_stall=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null ruby_system=system.ruby support_data_reqs=true support_inst_reqs=true system=system -using_network_tester=false using_ruby_tester=false version=3 @@ -4872,11 +5294,16 @@ buffer_size=0 clk_domain=system.clk_domain cluster_id=0 coalescer=system.tcp_cntrl1.coalescer +default_p_state=UNDEFINED eventq_index=0 issue_latency=40 l2_hit_latency=18 mandatoryQueue=system.tcp_cntrl1.mandatoryQueue number_of_TBEs=2560 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null probeToTCP=system.tcp_cntrl1.probeToTCP recycle_latency=10 requestFromTCP=system.tcp_cntrl1.requestFromTCP @@ -4922,17 +5349,22 @@ coreid=99 dcache=system.tcp_cntrl1.L1cache dcache_hit_latency=1 deadlock_threshold=500000 +default_p_state=UNDEFINED eventq_index=0 +garnet_standalone=false icache=system.tcp_cntrl1.L1cache icache_hit_latency=1 is_cpu_sequencer=false max_outstanding_requests=2560 no_retry_on_stall=true +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null ruby_system=system.ruby support_data_reqs=true support_inst_reqs=false system=system -using_network_tester=false using_ruby_tester=true version=4 slave=system.cpu.cpuDataPort[1] @@ -4983,17 +5415,22 @@ coreid=99 dcache=system.tcp_cntrl1.L1cache dcache_hit_latency=1 deadlock_threshold=500000 +default_p_state=UNDEFINED eventq_index=0 +garnet_standalone=false icache=system.tcp_cntrl1.L1cache icache_hit_latency=1 is_cpu_sequencer=true max_outstanding_requests=16 no_retry_on_stall=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null ruby_system=system.ruby support_data_reqs=true support_inst_reqs=true system=system -using_network_tester=false using_ruby_tester=false version=5 @@ -5014,11 +5451,16 @@ buffer_size=0 clk_domain=system.clk_domain cluster_id=0 coalescer=system.tcp_cntrl2.coalescer +default_p_state=UNDEFINED eventq_index=0 issue_latency=40 l2_hit_latency=18 mandatoryQueue=system.tcp_cntrl2.mandatoryQueue number_of_TBEs=2560 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null probeToTCP=system.tcp_cntrl2.probeToTCP recycle_latency=10 requestFromTCP=system.tcp_cntrl2.requestFromTCP @@ -5064,17 +5506,22 @@ coreid=99 dcache=system.tcp_cntrl2.L1cache dcache_hit_latency=1 deadlock_threshold=500000 +default_p_state=UNDEFINED eventq_index=0 +garnet_standalone=false icache=system.tcp_cntrl2.L1cache icache_hit_latency=1 is_cpu_sequencer=false max_outstanding_requests=2560 no_retry_on_stall=true +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null ruby_system=system.ruby support_data_reqs=true support_inst_reqs=false system=system -using_network_tester=false using_ruby_tester=true version=6 slave=system.cpu.cpuDataPort[2] @@ -5125,17 +5572,22 @@ coreid=99 dcache=system.tcp_cntrl2.L1cache dcache_hit_latency=1 deadlock_threshold=500000 +default_p_state=UNDEFINED eventq_index=0 +garnet_standalone=false icache=system.tcp_cntrl2.L1cache icache_hit_latency=1 is_cpu_sequencer=true max_outstanding_requests=16 no_retry_on_stall=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null ruby_system=system.ruby support_data_reqs=true support_inst_reqs=true system=system -using_network_tester=false using_ruby_tester=false version=7 @@ -5156,11 +5608,16 @@ buffer_size=0 clk_domain=system.clk_domain cluster_id=0 coalescer=system.tcp_cntrl3.coalescer +default_p_state=UNDEFINED eventq_index=0 issue_latency=40 l2_hit_latency=18 mandatoryQueue=system.tcp_cntrl3.mandatoryQueue number_of_TBEs=2560 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null probeToTCP=system.tcp_cntrl3.probeToTCP recycle_latency=10 requestFromTCP=system.tcp_cntrl3.requestFromTCP @@ -5206,17 +5663,22 @@ coreid=99 dcache=system.tcp_cntrl3.L1cache dcache_hit_latency=1 deadlock_threshold=500000 +default_p_state=UNDEFINED eventq_index=0 +garnet_standalone=false icache=system.tcp_cntrl3.L1cache icache_hit_latency=1 is_cpu_sequencer=false max_outstanding_requests=2560 no_retry_on_stall=true +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null ruby_system=system.ruby support_data_reqs=true support_inst_reqs=false system=system -using_network_tester=false using_ruby_tester=true version=8 slave=system.cpu.cpuDataPort[3] @@ -5267,17 +5729,22 @@ coreid=99 dcache=system.tcp_cntrl3.L1cache dcache_hit_latency=1 deadlock_threshold=500000 +default_p_state=UNDEFINED eventq_index=0 +garnet_standalone=false icache=system.tcp_cntrl3.L1cache icache_hit_latency=1 is_cpu_sequencer=true max_outstanding_requests=16 no_retry_on_stall=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null ruby_system=system.ruby support_data_reqs=true support_inst_reqs=true system=system -using_network_tester=false using_ruby_tester=false version=9 @@ -5298,11 +5765,16 @@ buffer_size=0 clk_domain=system.clk_domain cluster_id=0 coalescer=system.tcp_cntrl4.coalescer +default_p_state=UNDEFINED eventq_index=0 issue_latency=40 l2_hit_latency=18 mandatoryQueue=system.tcp_cntrl4.mandatoryQueue number_of_TBEs=2560 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null probeToTCP=system.tcp_cntrl4.probeToTCP recycle_latency=10 requestFromTCP=system.tcp_cntrl4.requestFromTCP @@ -5348,17 +5820,22 @@ coreid=99 dcache=system.tcp_cntrl4.L1cache dcache_hit_latency=1 deadlock_threshold=500000 +default_p_state=UNDEFINED eventq_index=0 +garnet_standalone=false icache=system.tcp_cntrl4.L1cache icache_hit_latency=1 is_cpu_sequencer=false max_outstanding_requests=2560 no_retry_on_stall=true +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null ruby_system=system.ruby support_data_reqs=true support_inst_reqs=false system=system -using_network_tester=false using_ruby_tester=true version=10 slave=system.cpu.cpuDataPort[4] @@ -5409,17 +5886,22 @@ coreid=99 dcache=system.tcp_cntrl4.L1cache dcache_hit_latency=1 deadlock_threshold=500000 +default_p_state=UNDEFINED eventq_index=0 +garnet_standalone=false icache=system.tcp_cntrl4.L1cache icache_hit_latency=1 is_cpu_sequencer=true max_outstanding_requests=16 no_retry_on_stall=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null ruby_system=system.ruby support_data_reqs=true support_inst_reqs=true system=system -using_network_tester=false using_ruby_tester=false version=11 @@ -5440,11 +5922,16 @@ buffer_size=0 clk_domain=system.clk_domain cluster_id=0 coalescer=system.tcp_cntrl5.coalescer +default_p_state=UNDEFINED eventq_index=0 issue_latency=40 l2_hit_latency=18 mandatoryQueue=system.tcp_cntrl5.mandatoryQueue number_of_TBEs=2560 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null probeToTCP=system.tcp_cntrl5.probeToTCP recycle_latency=10 requestFromTCP=system.tcp_cntrl5.requestFromTCP @@ -5490,17 +5977,22 @@ coreid=99 dcache=system.tcp_cntrl5.L1cache dcache_hit_latency=1 deadlock_threshold=500000 +default_p_state=UNDEFINED eventq_index=0 +garnet_standalone=false icache=system.tcp_cntrl5.L1cache icache_hit_latency=1 is_cpu_sequencer=false max_outstanding_requests=2560 no_retry_on_stall=true +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null ruby_system=system.ruby support_data_reqs=true support_inst_reqs=false system=system -using_network_tester=false using_ruby_tester=true version=12 slave=system.cpu.cpuDataPort[5] @@ -5551,17 +6043,22 @@ coreid=99 dcache=system.tcp_cntrl5.L1cache dcache_hit_latency=1 deadlock_threshold=500000 +default_p_state=UNDEFINED eventq_index=0 +garnet_standalone=false icache=system.tcp_cntrl5.L1cache icache_hit_latency=1 is_cpu_sequencer=true max_outstanding_requests=16 no_retry_on_stall=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null ruby_system=system.ruby support_data_reqs=true support_inst_reqs=true system=system -using_network_tester=false using_ruby_tester=false version=13 @@ -5582,11 +6079,16 @@ buffer_size=0 clk_domain=system.clk_domain cluster_id=0 coalescer=system.tcp_cntrl6.coalescer +default_p_state=UNDEFINED eventq_index=0 issue_latency=40 l2_hit_latency=18 mandatoryQueue=system.tcp_cntrl6.mandatoryQueue number_of_TBEs=2560 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null probeToTCP=system.tcp_cntrl6.probeToTCP recycle_latency=10 requestFromTCP=system.tcp_cntrl6.requestFromTCP @@ -5632,17 +6134,22 @@ coreid=99 dcache=system.tcp_cntrl6.L1cache dcache_hit_latency=1 deadlock_threshold=500000 +default_p_state=UNDEFINED eventq_index=0 +garnet_standalone=false icache=system.tcp_cntrl6.L1cache icache_hit_latency=1 is_cpu_sequencer=false max_outstanding_requests=2560 no_retry_on_stall=true +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null ruby_system=system.ruby support_data_reqs=true support_inst_reqs=false system=system -using_network_tester=false using_ruby_tester=true version=14 slave=system.cpu.cpuDataPort[6] @@ -5693,17 +6200,22 @@ coreid=99 dcache=system.tcp_cntrl6.L1cache dcache_hit_latency=1 deadlock_threshold=500000 +default_p_state=UNDEFINED eventq_index=0 +garnet_standalone=false icache=system.tcp_cntrl6.L1cache icache_hit_latency=1 is_cpu_sequencer=true max_outstanding_requests=16 no_retry_on_stall=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null ruby_system=system.ruby support_data_reqs=true support_inst_reqs=true system=system -using_network_tester=false using_ruby_tester=false version=15 @@ -5724,11 +6236,16 @@ buffer_size=0 clk_domain=system.clk_domain cluster_id=0 coalescer=system.tcp_cntrl7.coalescer +default_p_state=UNDEFINED eventq_index=0 issue_latency=40 l2_hit_latency=18 mandatoryQueue=system.tcp_cntrl7.mandatoryQueue number_of_TBEs=2560 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null probeToTCP=system.tcp_cntrl7.probeToTCP recycle_latency=10 requestFromTCP=system.tcp_cntrl7.requestFromTCP @@ -5774,17 +6291,22 @@ coreid=99 dcache=system.tcp_cntrl7.L1cache dcache_hit_latency=1 deadlock_threshold=500000 +default_p_state=UNDEFINED eventq_index=0 +garnet_standalone=false icache=system.tcp_cntrl7.L1cache icache_hit_latency=1 is_cpu_sequencer=false max_outstanding_requests=2560 no_retry_on_stall=true +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null ruby_system=system.ruby support_data_reqs=true support_inst_reqs=false system=system -using_network_tester=false using_ruby_tester=true version=16 slave=system.cpu.cpuDataPort[7] @@ -5835,17 +6357,22 @@ coreid=99 dcache=system.tcp_cntrl7.L1cache dcache_hit_latency=1 deadlock_threshold=500000 +default_p_state=UNDEFINED eventq_index=0 +garnet_standalone=false icache=system.tcp_cntrl7.L1cache icache_hit_latency=1 is_cpu_sequencer=true max_outstanding_requests=16 no_retry_on_stall=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null ruby_system=system.ruby support_data_reqs=true support_inst_reqs=true system=system -using_network_tester=false using_ruby_tester=false version=17 diff --git a/tests/quick/se/60.gpu-randomtest/ref/x86/linux/gpu-randomtest-ruby-GPU_RfO/simerr b/tests/quick/se/60.gpu-randomtest/ref/x86/linux/gpu-randomtest-ruby-GPU_RfO/simerr index 74f33c417..13060c953 100755 --- a/tests/quick/se/60.gpu-randomtest/ref/x86/linux/gpu-randomtest-ruby-GPU_RfO/simerr +++ b/tests/quick/se/60.gpu-randomtest/ref/x86/linux/gpu-randomtest-ruby-GPU_RfO/simerr @@ -6,7 +6,5 @@ warn: rounding error > tolerance 1.250000 rounded to 1 warn: rounding error > tolerance 1.250000 rounded to 1 -warn: rounding error > tolerance - 1.250000 rounded to 1 warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes) warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files! diff --git a/tests/quick/se/60.gpu-randomtest/ref/x86/linux/gpu-randomtest-ruby-GPU_RfO/simout b/tests/quick/se/60.gpu-randomtest/ref/x86/linux/gpu-randomtest-ruby-GPU_RfO/simout index bb54d1884..c3cb1df0a 100755 --- a/tests/quick/se/60.gpu-randomtest/ref/x86/linux/gpu-randomtest-ruby-GPU_RfO/simout +++ b/tests/quick/se/60.gpu-randomtest/ref/x86/linux/gpu-randomtest-ruby-GPU_RfO/simout @@ -1,11 +1,13 @@ +Redirecting stdout to build/HSAIL_X86/tests/opt/quick/se/60.gpu-randomtest/x86/linux/gpu-randomtest-ruby-GPU_RfO/simout +Redirecting stderr to build/HSAIL_X86/tests/opt/quick/se/60.gpu-randomtest/x86/linux/gpu-randomtest-ruby-GPU_RfO/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 21 2016 14:58:44 -gem5 started Jan 21 2016 14:59:07 -gem5 executing on zizzer, pid 26197 -command line: build/HSAIL_X86/gem5.opt -d build/HSAIL_X86/tests/opt/quick/se/60.gpu-randomtest/x86/linux/gpu-randomtest-ruby-GPU_RfO -re /z/atgutier/gem5/gem5-commit/tests/run.py build/HSAIL_X86/tests/opt/quick/se/60.gpu-randomtest/x86/linux/gpu-randomtest-ruby-GPU_RfO +gem5 compiled Oct 13 2016 21:24:38 +gem5 started Oct 13 2016 21:24:54 +gem5 executing on e108600-lin, pid 29891 +command line: /work/curdun01/gem5-external.hg/build/HSAIL_X86/gem5.opt -d build/HSAIL_X86/tests/opt/quick/se/60.gpu-randomtest/x86/linux/gpu-randomtest-ruby-GPU_RfO -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/60.gpu-randomtest/x86/linux/gpu-randomtest-ruby-GPU_RfO Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 14181 because Ruby Tester completed +Exiting @ tick 13821 because Ruby Tester completed diff --git a/tests/quick/se/60.gpu-randomtest/ref/x86/linux/gpu-randomtest-ruby-GPU_RfO/stats.txt b/tests/quick/se/60.gpu-randomtest/ref/x86/linux/gpu-randomtest-ruby-GPU_RfO/stats.txt index 40be86e31..7dd43386c 100644 --- a/tests/quick/se/60.gpu-randomtest/ref/x86/linux/gpu-randomtest-ruby-GPU_RfO/stats.txt +++ b/tests/quick/se/60.gpu-randomtest/ref/x86/linux/gpu-randomtest-ruby-GPU_RfO/stats.txt @@ -1,44 +1,44 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000014 # Number of seconds simulated -sim_ticks 14181 # Number of ticks simulated -final_tick 14181 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 13821 # Number of ticks simulated +final_tick 13821 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 238683 # Simulator tick rate (ticks/s) -host_mem_usage 530468 # Number of bytes of host memory used +host_tick_rate 213268 # Simulator tick rate (ticks/s) +host_mem_usage 483832 # Number of bytes of host memory used host_seconds 0.06 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks -system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states -system.mem_ctrls.bytes_read::dir_cntrl0 16576 # Number of bytes read from this memory -system.mem_ctrls.bytes_read::total 16576 # Number of bytes read from this memory -system.mem_ctrls.bytes_written::dir_cntrl0 576 # Number of bytes written to this memory -system.mem_ctrls.bytes_written::total 576 # Number of bytes written to this memory -system.mem_ctrls.num_reads::dir_cntrl0 259 # Number of read requests responded to by this memory -system.mem_ctrls.num_reads::total 259 # Number of read requests responded to by this memory -system.mem_ctrls.num_writes::dir_cntrl0 9 # Number of write requests responded to by this memory -system.mem_ctrls.num_writes::total 9 # Number of write requests responded to by this memory -system.mem_ctrls.bw_read::dir_cntrl0 1168887949 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_read::total 1168887949 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::dir_cntrl0 40617728 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::total 40617728 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_total::dir_cntrl0 1209505677 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.bw_total::total 1209505677 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.readReqs 259 # Number of read requests accepted -system.mem_ctrls.writeReqs 9 # Number of write requests accepted -system.mem_ctrls.readBursts 259 # Number of DRAM read bursts, including those serviced by the write queue -system.mem_ctrls.writeBursts 9 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrls.bytesReadDRAM 15936 # Total number of bytes read from DRAM -system.mem_ctrls.bytesReadWrQ 640 # Total number of bytes read from write queue +system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states +system.mem_ctrls.bytes_read::dir_cntrl0 16384 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 16384 # Number of bytes read from this memory +system.mem_ctrls.bytes_written::dir_cntrl0 896 # Number of bytes written to this memory +system.mem_ctrls.bytes_written::total 896 # Number of bytes written to this memory +system.mem_ctrls.num_reads::dir_cntrl0 256 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 256 # Number of read requests responded to by this memory +system.mem_ctrls.num_writes::dir_cntrl0 14 # Number of write requests responded to by this memory +system.mem_ctrls.num_writes::total 14 # Number of write requests responded to by this memory +system.mem_ctrls.bw_read::dir_cntrl0 1185442443 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 1185442443 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::dir_cntrl0 64828884 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::total 64828884 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::dir_cntrl0 1250271326 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 1250271326 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.readReqs 256 # Number of read requests accepted +system.mem_ctrls.writeReqs 14 # Number of write requests accepted +system.mem_ctrls.readBursts 256 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 14 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.bytesReadDRAM 15488 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 896 # Total number of bytes read from write queue system.mem_ctrls.bytesWritten 0 # Total number of bytes written to DRAM -system.mem_ctrls.bytesReadSys 16576 # Total read bytes from the system interface side -system.mem_ctrls.bytesWrittenSys 576 # Total written bytes from the system interface side -system.mem_ctrls.servicedByWrQ 10 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.bytesReadSys 16384 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 896 # Total written bytes from the system interface side +system.mem_ctrls.servicedByWrQ 14 # Number of DRAM read bursts serviced by the write queue system.mem_ctrls.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.mem_ctrls.perBankRdBursts::0 100 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::1 71 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::2 66 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::0 99 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 69 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 62 # Per bank write bursts system.mem_ctrls.perBankRdBursts::3 12 # Per bank write bursts system.mem_ctrls.perBankRdBursts::4 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::5 0 # Per bank write bursts @@ -70,24 +70,24 @@ system.mem_ctrls.perBankWrBursts::14 0 # Pe system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrls.totGap 13941 # Total gap between requests +system.mem_ctrls.totGap 13710 # Total gap between requests system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::6 259 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 256 # Read request sizes (log2) system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::6 9 # Write request sizes (log2) -system.mem_ctrls.rdQLenPdf::0 214 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::1 27 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::2 7 # What read queue length does an incoming req see +system.mem_ctrls.writePktSize::6 14 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 199 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 36 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::2 6 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::3 1 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -126,11 +126,11 @@ system.mem_ctrls.wrQLenPdf::5 1 # Wh system.mem_ctrls.wrQLenPdf::6 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::9 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::10 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::11 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::12 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::10 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::11 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::14 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::15 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::16 0 # What write queue length does an incoming req see @@ -189,206 +189,214 @@ system.mem_ctrls.bytesPerActivate::512-639 3 20.00% 20.00% # system.mem_ctrls.bytesPerActivate::896-1023 1 6.67% 26.67% # Bytes accessed per row activation system.mem_ctrls.bytesPerActivate::1024-1151 11 73.33% 100.00% # Bytes accessed per row activation system.mem_ctrls.bytesPerActivate::total 15 # Bytes accessed per row activation -system.mem_ctrls.totQLat 973 # Total ticks spent queuing -system.mem_ctrls.totMemAccLat 5704 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrls.totBusLat 1245 # Total ticks spent in databus transfers -system.mem_ctrls.avgQLat 3.91 # Average queueing delay per DRAM burst +system.mem_ctrls.totQLat 2184 # Total ticks spent queuing +system.mem_ctrls.totMemAccLat 6782 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.totBusLat 1210 # Total ticks spent in databus transfers +system.mem_ctrls.avgQLat 9.02 # Average queueing delay per DRAM burst system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst -system.mem_ctrls.avgMemAccLat 22.91 # Average memory access latency per DRAM burst -system.mem_ctrls.avgRdBW 1123.76 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgMemAccLat 28.02 # Average memory access latency per DRAM burst +system.mem_ctrls.avgRdBW 1120.61 # Average DRAM read bandwidth in MiByte/s system.mem_ctrls.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.mem_ctrls.avgRdBWSys 1168.89 # Average system read bandwidth in MiByte/s -system.mem_ctrls.avgWrBWSys 40.62 # Average system write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 1185.44 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 64.83 # Average system write bandwidth in MiByte/s system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrls.busUtil 8.78 # Data bus utilization in percentage -system.mem_ctrls.busUtilRead 8.78 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtil 8.75 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 8.75 # Data bus utilization in percentage for reads system.mem_ctrls.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.mem_ctrls.avgRdQLen 1.17 # Average read queue length when enqueuing -system.mem_ctrls.avgWrQLen 2.63 # Average write queue length when enqueuing -system.mem_ctrls.readRowHits 230 # Number of row buffer hits during reads +system.mem_ctrls.avgRdQLen 1.20 # Average read queue length when enqueuing +system.mem_ctrls.avgWrQLen 3.35 # Average write queue length when enqueuing +system.mem_ctrls.readRowHits 223 # Number of row buffer hits during reads system.mem_ctrls.writeRowHits 0 # Number of row buffer hits during writes -system.mem_ctrls.readRowHitRate 92.37 # Row buffer hit rate for reads +system.mem_ctrls.readRowHitRate 92.15 # Row buffer hit rate for reads system.mem_ctrls.writeRowHitRate 0.00 # Row buffer hit rate for writes -system.mem_ctrls.avgGap 52.02 # Average gap between requests -system.mem_ctrls.pageHitRate 89.15 # Row buffer hit rate, read and write combined -system.mem_ctrls_0.actEnergy 83160 # Energy for activate commands per rank (pJ) -system.mem_ctrls_0.preEnergy 46200 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_0.readEnergy 1872000 # Energy for read commands per rank (pJ) +system.mem_ctrls.avgGap 50.78 # Average gap between requests +system.mem_ctrls.pageHitRate 87.11 # Row buffer hit rate, read and write combined +system.mem_ctrls_0.actEnergy 135660 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 57960 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 2764608 # Energy for read commands per rank (pJ) system.mem_ctrls_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.mem_ctrls_0.refreshEnergy 508560 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_0.actBackEnergy 5437116 # Energy for active background per rank (pJ) -system.mem_ctrls_0.preBackEnergy 58200 # Energy for precharge background per rank (pJ) -system.mem_ctrls_0.totalEnergy 8005236 # Total energy per rank (pJ) -system.mem_ctrls_0.averagePower 994.933632 # Core power per rank (mW) -system.mem_ctrls_0.memoryStateTime::IDLE 83 # Time in different power states +system.mem_ctrls_0.refreshEnergy 614640.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 2757888 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 44928 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.actPowerDownEnergy 3490680 # Energy for active power-down per rank (pJ) +system.mem_ctrls_0.prePowerDownEnergy 384 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls_0.totalEnergy 9866748 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 713.895377 # Core power per rank (mW) +system.mem_ctrls_0.totalIdleTime 7568 # Total Idle time Per DRAM Rank +system.mem_ctrls_0.memoryStateTime::IDLE 89 # Time in different power states system.mem_ctrls_0.memoryStateTime::REF 260 # Time in different power states -system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT 7717 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls_0.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls_0.memoryStateTime::PRE_PDN 1 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 5816 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT_PDN 7655 # Time in different power states system.mem_ctrls_1.actEnergy 0 # Energy for activate commands per rank (pJ) system.mem_ctrls_1.preEnergy 0 # Energy for precharge commands per rank (pJ) system.mem_ctrls_1.readEnergy 0 # Energy for read commands per rank (pJ) system.mem_ctrls_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.mem_ctrls_1.refreshEnergy 508560 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_1.actBackEnergy 168264 # Energy for active background per rank (pJ) -system.mem_ctrls_1.preBackEnergy 4671600 # Energy for precharge background per rank (pJ) -system.mem_ctrls_1.totalEnergy 5348424 # Total energy per rank (pJ) -system.mem_ctrls_1.averagePower 665.889442 # Core power per rank (mW) +system.mem_ctrls_1.refreshEnergy 614640.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 112176 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 2995200 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls_1.prePowerDownEnergy 2217600 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls_1.totalEnergy 5939616 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 429.752985 # Core power per rank (mW) +system.mem_ctrls_1.totalIdleTime 0 # Total Idle time Per DRAM Rank system.mem_ctrls_1.memoryStateTime::IDLE 7786 # Time in different power states system.mem_ctrls_1.memoryStateTime::REF 260 # Time in different power states -system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_1.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls_1.memoryStateTime::PRE_PDN 5775 # Time in different power states system.mem_ctrls_1.memoryStateTime::ACT 0 # Time in different power states system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states system.ruby.clk_domain.clock 1 # Clock period in ticks -system.ruby.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states +system.ruby.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states system.ruby.outstanding_req_hist_seqr::bucket_size 2 system.ruby.outstanding_req_hist_seqr::max_bucket 19 system.ruby.outstanding_req_hist_seqr::samples 63 -system.ruby.outstanding_req_hist_seqr::mean 12.920635 -system.ruby.outstanding_req_hist_seqr::gmean 11.694862 -system.ruby.outstanding_req_hist_seqr::stdev 4.228557 -system.ruby.outstanding_req_hist_seqr | 1 1.59% 1.59% | 2 3.17% 4.76% | 2 3.17% 7.94% | 5 7.94% 15.87% | 4 6.35% 22.22% | 3 4.76% 26.98% | 5 7.94% 34.92% | 14 22.22% 57.14% | 27 42.86% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist_seqr::mean 12.873016 +system.ruby.outstanding_req_hist_seqr::gmean 11.658152 +system.ruby.outstanding_req_hist_seqr::stdev 4.202503 +system.ruby.outstanding_req_hist_seqr | 1 1.59% 1.59% | 2 3.17% 4.76% | 2 3.17% 7.94% | 5 7.94% 15.87% | 4 6.35% 22.22% | 3 4.76% 26.98% | 5 7.94% 34.92% | 16 25.40% 60.32% | 25 39.68% 100.00% | 0 0.00% 100.00% system.ruby.outstanding_req_hist_seqr::total 63 system.ruby.outstanding_req_hist_coalsr::bucket_size 2 system.ruby.outstanding_req_hist_coalsr::max_bucket 19 -system.ruby.outstanding_req_hist_coalsr::samples 885 -system.ruby.outstanding_req_hist_coalsr::mean 2.610169 -system.ruby.outstanding_req_hist_coalsr::gmean 2.223354 -system.ruby.outstanding_req_hist_coalsr::stdev 1.538535 -system.ruby.outstanding_req_hist_coalsr | 219 24.75% 24.75% | 478 54.01% 78.76% | 135 15.25% 94.01% | 43 4.86% 98.87% | 9 1.02% 99.89% | 1 0.11% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.outstanding_req_hist_coalsr::total 885 +system.ruby.outstanding_req_hist_coalsr::samples 872 +system.ruby.outstanding_req_hist_coalsr::mean 2.547018 +system.ruby.outstanding_req_hist_coalsr::gmean 2.158955 +system.ruby.outstanding_req_hist_coalsr::stdev 1.537168 +system.ruby.outstanding_req_hist_coalsr | 236 27.06% 27.06% | 460 52.75% 79.82% | 126 14.45% 94.27% | 40 4.59% 98.85% | 9 1.03% 99.89% | 1 0.11% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist_coalsr::total 872 system.ruby.latency_hist_seqr::bucket_size 1024 system.ruby.latency_hist_seqr::max_bucket 10239 system.ruby.latency_hist_seqr::samples 48 -system.ruby.latency_hist_seqr::mean 3351.354167 -system.ruby.latency_hist_seqr::gmean 1865.352879 -system.ruby.latency_hist_seqr::stdev 1934.275107 -system.ruby.latency_hist_seqr | 11 22.92% 22.92% | 3 6.25% 29.17% | 3 6.25% 35.42% | 7 14.58% 50.00% | 18 37.50% 87.50% | 6 12.50% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.latency_hist_seqr::mean 3315.854167 +system.ruby.latency_hist_seqr::gmean 1841.298781 +system.ruby.latency_hist_seqr::stdev 1907.716848 +system.ruby.latency_hist_seqr | 11 22.92% 22.92% | 3 6.25% 29.17% | 3 6.25% 35.42% | 7 14.58% 50.00% | 20 41.67% 91.67% | 4 8.33% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.latency_hist_seqr::total 48 system.ruby.latency_hist_coalsr::bucket_size 128 system.ruby.latency_hist_coalsr::max_bucket 1279 -system.ruby.latency_hist_coalsr::samples 872 -system.ruby.latency_hist_coalsr::mean 222.089450 -system.ruby.latency_hist_coalsr::gmean 114.436171 -system.ruby.latency_hist_coalsr::stdev 241.512900 -system.ruby.latency_hist_coalsr | 580 66.51% 66.51% | 30 3.44% 69.95% | 110 12.61% 82.57% | 39 4.47% 87.04% | 33 3.78% 90.83% | 20 2.29% 93.12% | 33 3.78% 96.90% | 23 2.64% 99.54% | 4 0.46% 100.00% | 0 0.00% 100.00% -system.ruby.latency_hist_coalsr::total 872 +system.ruby.latency_hist_coalsr::samples 858 +system.ruby.latency_hist_coalsr::mean 215.358974 +system.ruby.latency_hist_coalsr::gmean 107.894342 +system.ruby.latency_hist_coalsr::stdev 237.470134 +system.ruby.latency_hist_coalsr | 573 66.78% 66.78% | 36 4.20% 70.98% | 111 12.94% 83.92% | 37 4.31% 88.23% | 24 2.80% 91.03% | 19 2.21% 93.24% | 32 3.73% 96.97% | 23 2.68% 99.65% | 3 0.35% 100.00% | 0 0.00% 100.00% +system.ruby.latency_hist_coalsr::total 858 system.ruby.hit_latency_hist_seqr::bucket_size 1024 system.ruby.hit_latency_hist_seqr::max_bucket 10239 system.ruby.hit_latency_hist_seqr::samples 42 -system.ruby.hit_latency_hist_seqr::mean 3684.428571 -system.ruby.hit_latency_hist_seqr::gmean 2778.454716 -system.ruby.hit_latency_hist_seqr::stdev 1783.107224 -system.ruby.hit_latency_hist_seqr | 7 16.67% 16.67% | 3 7.14% 23.81% | 1 2.38% 26.19% | 7 16.67% 42.86% | 18 42.86% 85.71% | 6 14.29% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.hit_latency_hist_seqr::mean 3644.142857 +system.ruby.hit_latency_hist_seqr::gmean 2737.850881 +system.ruby.hit_latency_hist_seqr::stdev 1757.652877 +system.ruby.hit_latency_hist_seqr | 7 16.67% 16.67% | 3 7.14% 23.81% | 1 2.38% 26.19% | 7 16.67% 42.86% | 20 47.62% 90.48% | 4 9.52% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.hit_latency_hist_seqr::total 42 system.ruby.miss_latency_hist_seqr::bucket_size 512 system.ruby.miss_latency_hist_seqr::max_bucket 5119 system.ruby.miss_latency_hist_seqr::samples 6 -system.ruby.miss_latency_hist_seqr::mean 1019.833333 -system.ruby.miss_latency_hist_seqr::gmean 114.673945 -system.ruby.miss_latency_hist_seqr::stdev 1281.644790 -system.ruby.miss_latency_hist_seqr | 3 50.00% 50.00% | 1 16.67% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 2 33.33% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.miss_latency_hist_seqr::mean 1017.833333 +system.ruby.miss_latency_hist_seqr::gmean 114.584426 +system.ruby.miss_latency_hist_seqr::stdev 1278.753677 +system.ruby.miss_latency_hist_seqr | 3 50.00% 50.00% | 1 16.67% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 1 16.67% 83.33% | 1 16.67% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.miss_latency_hist_seqr::total 6 system.ruby.miss_latency_hist_coalsr::bucket_size 128 system.ruby.miss_latency_hist_coalsr::max_bucket 1279 -system.ruby.miss_latency_hist_coalsr::samples 872 -system.ruby.miss_latency_hist_coalsr::mean 222.089450 -system.ruby.miss_latency_hist_coalsr::gmean 114.436171 -system.ruby.miss_latency_hist_coalsr::stdev 241.512900 -system.ruby.miss_latency_hist_coalsr | 580 66.51% 66.51% | 30 3.44% 69.95% | 110 12.61% 82.57% | 39 4.47% 87.04% | 33 3.78% 90.83% | 20 2.29% 93.12% | 33 3.78% 96.90% | 23 2.64% 99.54% | 4 0.46% 100.00% | 0 0.00% 100.00% -system.ruby.miss_latency_hist_coalsr::total 872 +system.ruby.miss_latency_hist_coalsr::samples 858 +system.ruby.miss_latency_hist_coalsr::mean 215.358974 +system.ruby.miss_latency_hist_coalsr::gmean 107.894342 +system.ruby.miss_latency_hist_coalsr::stdev 237.470134 +system.ruby.miss_latency_hist_coalsr | 573 66.78% 66.78% | 36 4.20% 70.98% | 111 12.94% 83.92% | 37 4.31% 88.23% | 24 2.80% 91.03% | 19 2.21% 93.24% | 32 3.73% 96.97% | 23 2.68% 99.65% | 3 0.35% 100.00% | 0 0.00% 100.00% +system.ruby.miss_latency_hist_coalsr::total 858 system.ruby.L1Cache.incomplete_times_seqr 6 system.cp_cntrl0.L1D0cache.demand_hits 0 # Number of cache demand hits system.cp_cntrl0.L1D0cache.demand_misses 45 # Number of cache demand misses system.cp_cntrl0.L1D0cache.demand_accesses 45 # Number of cache demand accesses system.cp_cntrl0.L1D0cache.num_data_array_writes 43 # number of data array writes -system.cp_cntrl0.L1D0cache.num_tag_array_reads 154 # number of tag array reads +system.cp_cntrl0.L1D0cache.num_tag_array_reads 155 # number of tag array reads system.cp_cntrl0.L1D0cache.num_tag_array_writes 41 # number of tag array writes system.cp_cntrl0.L1D1cache.demand_hits 0 # Number of cache demand hits -system.cp_cntrl0.L1D1cache.demand_misses 43 # Number of cache demand misses -system.cp_cntrl0.L1D1cache.demand_accesses 43 # Number of cache demand accesses -system.cp_cntrl0.L1D1cache.num_data_array_writes 41 # number of data array writes -system.cp_cntrl0.L1D1cache.num_tag_array_reads 73 # number of tag array reads -system.cp_cntrl0.L1D1cache.num_tag_array_writes 41 # number of tag array writes +system.cp_cntrl0.L1D1cache.demand_misses 45 # Number of cache demand misses +system.cp_cntrl0.L1D1cache.demand_accesses 45 # Number of cache demand accesses +system.cp_cntrl0.L1D1cache.num_data_array_writes 42 # number of data array writes +system.cp_cntrl0.L1D1cache.num_tag_array_reads 74 # number of tag array reads +system.cp_cntrl0.L1D1cache.num_tag_array_writes 42 # number of tag array writes system.cp_cntrl0.L1Icache.demand_hits 0 # Number of cache demand hits system.cp_cntrl0.L1Icache.demand_misses 3 # Number of cache demand misses system.cp_cntrl0.L1Icache.demand_accesses 3 # Number of cache demand accesses system.cp_cntrl0.L1Icache.num_tag_array_reads 3 # number of tag array reads system.cp_cntrl0.L2cache.demand_hits 0 # Number of cache demand hits -system.cp_cntrl0.L2cache.demand_misses 91 # Number of cache demand misses -system.cp_cntrl0.L2cache.demand_accesses 91 # Number of cache demand accesses +system.cp_cntrl0.L2cache.demand_misses 93 # Number of cache demand misses +system.cp_cntrl0.L2cache.demand_accesses 93 # Number of cache demand accesses system.cp_cntrl0.L2cache.num_data_array_reads 81 # number of data array reads -system.cp_cntrl0.L2cache.num_data_array_writes 84 # number of data array writes -system.cp_cntrl0.L2cache.num_tag_array_reads 380 # number of tag array reads -system.cp_cntrl0.L2cache.num_tag_array_writes 371 # number of tag array writes -system.cp_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states -system.cp_cntrl0.sequencer.store_waiting_on_load 2 # Number of times a store aliased with a pending load -system.cp_cntrl0.sequencer.store_waiting_on_store 3 # Number of times a store aliased with a pending store -system.cp_cntrl0.sequencer1.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states -system.cp_cntrl0.sequencer1.store_waiting_on_load 1 # Number of times a store aliased with a pending load +system.cp_cntrl0.L2cache.num_data_array_writes 85 # number of data array writes +system.cp_cntrl0.L2cache.num_tag_array_reads 372 # number of tag array reads +system.cp_cntrl0.L2cache.num_tag_array_writes 362 # number of tag array writes +system.cp_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states +system.cp_cntrl0.sequencer.store_waiting_on_load 1 # Number of times a store aliased with a pending load +system.cp_cntrl0.sequencer.store_waiting_on_store 4 # Number of times a store aliased with a pending store +system.cp_cntrl0.sequencer1.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states system.cp_cntrl0.sequencer1.store_waiting_on_store 4 # Number of times a store aliased with a pending store -system.cp_cntrl0.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states -system.cp_cntrl0.fully_busy_cycles 2 # cycles for which number of transistions == max transitions -system.cpu.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states +system.cp_cntrl0.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states +system.cpu.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states system.dir_cntrl0.L3CacheMemory.demand_hits 0 # Number of cache demand hits system.dir_cntrl0.L3CacheMemory.demand_misses 0 # Number of cache demand misses system.dir_cntrl0.L3CacheMemory.demand_accesses 0 # Number of cache demand accesses -system.dir_cntrl0.L3CacheMemory.num_data_array_writes 374 # number of data array writes -system.dir_cntrl0.L3CacheMemory.num_tag_array_reads 378 # number of tag array reads -system.dir_cntrl0.L3CacheMemory.num_tag_array_writes 378 # number of tag array writes -system.dir_cntrl0.L3CacheMemory.num_tag_array_stalls 10169 # number of stalls caused by tag array -system.dir_cntrl0.L3CacheMemory.num_data_array_stalls 5502 # number of stalls caused by data array -system.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states -system.ruby.network.ext_links00.int_node.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states -system.ruby.network.ext_links00.int_node.percent_links_utilized 0.199210 -system.ruby.network.ext_links00.int_node.msg_count.Control::0 308 -system.ruby.network.ext_links00.int_node.msg_count.Request_Control::0 385 -system.ruby.network.ext_links00.int_node.msg_count.Response_Data::2 393 -system.ruby.network.ext_links00.int_node.msg_count.Response_Control::2 227 -system.ruby.network.ext_links00.int_node.msg_count.Writeback_Data::2 66 -system.ruby.network.ext_links00.int_node.msg_count.Writeback_Control::2 70 -system.ruby.network.ext_links00.int_node.msg_count.Unblock_Control::4 303 -system.ruby.network.ext_links00.int_node.msg_bytes.Control::0 2464 -system.ruby.network.ext_links00.int_node.msg_bytes.Request_Control::0 3080 -system.ruby.network.ext_links00.int_node.msg_bytes.Response_Data::2 28296 -system.ruby.network.ext_links00.int_node.msg_bytes.Response_Control::2 1816 -system.ruby.network.ext_links00.int_node.msg_bytes.Writeback_Data::2 4752 -system.ruby.network.ext_links00.int_node.msg_bytes.Writeback_Control::2 560 -system.ruby.network.ext_links00.int_node.msg_bytes.Unblock_Control::4 2424 -system.ruby.network.ext_links01.int_node.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states -system.ruby.network.ext_links01.int_node.percent_links_utilized 0.120981 -system.ruby.network.ext_links01.int_node.msg_count.Control::0 227 -system.ruby.network.ext_links01.int_node.msg_count.Request_Control::0 153 +system.dir_cntrl0.L3CacheMemory.num_data_array_writes 365 # number of data array writes +system.dir_cntrl0.L3CacheMemory.num_tag_array_reads 372 # number of tag array reads +system.dir_cntrl0.L3CacheMemory.num_tag_array_writes 369 # number of tag array writes +system.dir_cntrl0.L3CacheMemory.num_tag_array_stalls 9126 # number of stalls caused by tag array +system.dir_cntrl0.L3CacheMemory.num_data_array_stalls 4922 # number of stalls caused by data array +system.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states +system.ruby.network.ext_links00.int_node.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states +system.ruby.network.ext_links00.int_node.percent_links_utilized 0.199915 +system.ruby.network.ext_links00.int_node.msg_count.Control::0 300 +system.ruby.network.ext_links00.int_node.msg_count.Request_Control::0 372 +system.ruby.network.ext_links00.int_node.msg_count.Response_Data::2 383 +system.ruby.network.ext_links00.int_node.msg_count.Response_Control::2 217 +system.ruby.network.ext_links00.int_node.msg_count.Writeback_Data::2 67 +system.ruby.network.ext_links00.int_node.msg_count.Writeback_Control::2 71 +system.ruby.network.ext_links00.int_node.msg_count.Unblock_Control::4 295 +system.ruby.network.ext_links00.int_node.msg_bytes.Control::0 2400 +system.ruby.network.ext_links00.int_node.msg_bytes.Request_Control::0 2976 +system.ruby.network.ext_links00.int_node.msg_bytes.Response_Data::2 27576 +system.ruby.network.ext_links00.int_node.msg_bytes.Response_Control::2 1736 +system.ruby.network.ext_links00.int_node.msg_bytes.Writeback_Data::2 4824 +system.ruby.network.ext_links00.int_node.msg_bytes.Writeback_Control::2 568 +system.ruby.network.ext_links00.int_node.msg_bytes.Unblock_Control::4 2360 +system.ruby.network.ext_links01.int_node.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states +system.ruby.network.ext_links01.int_node.percent_links_utilized 0.123680 +system.ruby.network.ext_links01.int_node.msg_count.Control::0 216 +system.ruby.network.ext_links01.int_node.msg_count.Request_Control::0 155 system.ruby.network.ext_links01.int_node.msg_count.Response_Data::2 95 -system.ruby.network.ext_links01.int_node.msg_count.Response_Control::2 217 -system.ruby.network.ext_links01.int_node.msg_count.Writeback_Data::2 66 -system.ruby.network.ext_links01.int_node.msg_count.Writeback_Control::2 70 -system.ruby.network.ext_links01.int_node.msg_count.Unblock_Control::4 80 -system.ruby.network.ext_links01.int_node.msg_bytes.Control::0 1816 -system.ruby.network.ext_links01.int_node.msg_bytes.Request_Control::0 1224 +system.ruby.network.ext_links01.int_node.msg_count.Response_Control::2 207 +system.ruby.network.ext_links01.int_node.msg_count.Writeback_Data::2 67 +system.ruby.network.ext_links01.int_node.msg_count.Writeback_Control::2 71 +system.ruby.network.ext_links01.int_node.msg_count.Unblock_Control::4 81 +system.ruby.network.ext_links01.int_node.msg_bytes.Control::0 1728 +system.ruby.network.ext_links01.int_node.msg_bytes.Request_Control::0 1240 system.ruby.network.ext_links01.int_node.msg_bytes.Response_Data::2 6840 -system.ruby.network.ext_links01.int_node.msg_bytes.Response_Control::2 1736 -system.ruby.network.ext_links01.int_node.msg_bytes.Writeback_Data::2 4752 -system.ruby.network.ext_links01.int_node.msg_bytes.Writeback_Control::2 560 -system.ruby.network.ext_links01.int_node.msg_bytes.Unblock_Control::4 640 +system.ruby.network.ext_links01.int_node.msg_bytes.Response_Control::2 1656 +system.ruby.network.ext_links01.int_node.msg_bytes.Writeback_Data::2 4824 +system.ruby.network.ext_links01.int_node.msg_bytes.Writeback_Control::2 568 +system.ruby.network.ext_links01.int_node.msg_bytes.Unblock_Control::4 648 system.tcp_cntrl0.L1cache.demand_hits 0 # Number of cache demand hits system.tcp_cntrl0.L1cache.demand_misses 0 # Number of cache demand misses system.tcp_cntrl0.L1cache.demand_accesses 0 # Number of cache demand accesses -system.tcp_cntrl0.L1cache.num_data_array_reads 14 # number of data array reads -system.tcp_cntrl0.L1cache.num_data_array_writes 116 # number of data array writes -system.tcp_cntrl0.L1cache.num_tag_array_reads 314 # number of tag array reads -system.tcp_cntrl0.L1cache.num_tag_array_writes 305 # number of tag array writes -system.tcp_cntrl0.L1cache.num_tag_array_stalls 38 # number of stalls caused by tag array -system.tcp_cntrl0.coalescer.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states +system.tcp_cntrl0.L1cache.num_data_array_reads 16 # number of data array reads +system.tcp_cntrl0.L1cache.num_data_array_writes 112 # number of data array writes +system.tcp_cntrl0.L1cache.num_tag_array_reads 309 # number of tag array reads +system.tcp_cntrl0.L1cache.num_tag_array_writes 300 # number of tag array writes +system.tcp_cntrl0.L1cache.num_tag_array_stalls 28 # number of stalls caused by tag array +system.tcp_cntrl0.coalescer.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states system.tcp_cntrl0.coalescer.gpu_tcp_ld_hits 0 # loads that hit in the TCP -system.tcp_cntrl0.coalescer.gpu_tcp_ld_transfers 5 # TCP to TCP load transfers +system.tcp_cntrl0.coalescer.gpu_tcp_ld_transfers 9 # TCP to TCP load transfers system.tcp_cntrl0.coalescer.gpu_tcc_ld_hits 0 # loads that hit in the TCC -system.tcp_cntrl0.coalescer.gpu_ld_misses 0 # loads that miss in the GPU +system.tcp_cntrl0.coalescer.gpu_ld_misses 1 # loads that miss in the GPU system.tcp_cntrl0.coalescer.gpu_tcp_st_hits 9 # stores that hit in the TCP -system.tcp_cntrl0.coalescer.gpu_tcp_st_transfers 79 # TCP to TCP store transfers +system.tcp_cntrl0.coalescer.gpu_tcp_st_transfers 74 # TCP to TCP store transfers system.tcp_cntrl0.coalescer.gpu_tcc_st_hits 0 # stores that hit in the TCC -system.tcp_cntrl0.coalescer.gpu_st_misses 21 # stores that miss in the GPU +system.tcp_cntrl0.coalescer.gpu_st_misses 19 # stores that miss in the GPU system.tcp_cntrl0.coalescer.cp_tcp_ld_hits 0 # loads that hit in the TCP system.tcp_cntrl0.coalescer.cp_tcp_ld_transfers 0 # TCP to TCP load transfers system.tcp_cntrl0.coalescer.cp_tcc_ld_hits 0 # loads that hit in the TCC @@ -397,45 +405,45 @@ system.tcp_cntrl0.coalescer.cp_tcp_st_hits 0 # system.tcp_cntrl0.coalescer.cp_tcp_st_transfers 0 # TCP to TCP store transfers system.tcp_cntrl0.coalescer.cp_tcc_st_hits 0 # stores that hit in the TCC system.tcp_cntrl0.coalescer.cp_st_misses 0 # stores that miss in the GPU -system.tcp_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states -system.tcp_cntrl0.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states -system.ruby.network.ext_links02.int_node.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states -system.ruby.network.ext_links02.int_node.percent_links_utilized 0.173894 -system.ruby.network.ext_links02.int_node.msg_count.Control::0 81 -system.ruby.network.ext_links02.int_node.msg_count.Control::1 814 -system.ruby.network.ext_links02.int_node.msg_count.Request_Control::0 232 -system.ruby.network.ext_links02.int_node.msg_count.Request_Control::1 846 -system.ruby.network.ext_links02.int_node.msg_count.Response_Data::2 298 -system.ruby.network.ext_links02.int_node.msg_count.Response_Data::3 1644 +system.tcp_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states +system.tcp_cntrl0.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states +system.ruby.network.ext_links02.int_node.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states +system.ruby.network.ext_links02.int_node.percent_links_utilized 0.172944 +system.ruby.network.ext_links02.int_node.msg_count.Control::0 84 +system.ruby.network.ext_links02.int_node.msg_count.Control::1 789 +system.ruby.network.ext_links02.int_node.msg_count.Request_Control::0 217 +system.ruby.network.ext_links02.int_node.msg_count.Request_Control::1 823 +system.ruby.network.ext_links02.int_node.msg_count.Response_Data::2 288 +system.ruby.network.ext_links02.int_node.msg_count.Response_Data::3 1594 system.ruby.network.ext_links02.int_node.msg_count.Response_Control::2 10 system.ruby.network.ext_links02.int_node.msg_count.Response_Control::3 2 -system.ruby.network.ext_links02.int_node.msg_count.Unblock_Control::4 223 -system.ruby.network.ext_links02.int_node.msg_count.Unblock_Control::5 831 -system.ruby.network.ext_links02.int_node.msg_bytes.Control::0 648 -system.ruby.network.ext_links02.int_node.msg_bytes.Control::1 6512 -system.ruby.network.ext_links02.int_node.msg_bytes.Request_Control::0 1856 -system.ruby.network.ext_links02.int_node.msg_bytes.Request_Control::1 6768 -system.ruby.network.ext_links02.int_node.msg_bytes.Response_Data::2 21456 -system.ruby.network.ext_links02.int_node.msg_bytes.Response_Data::3 118368 +system.ruby.network.ext_links02.int_node.msg_count.Unblock_Control::4 214 +system.ruby.network.ext_links02.int_node.msg_count.Unblock_Control::5 810 +system.ruby.network.ext_links02.int_node.msg_bytes.Control::0 672 +system.ruby.network.ext_links02.int_node.msg_bytes.Control::1 6312 +system.ruby.network.ext_links02.int_node.msg_bytes.Request_Control::0 1736 +system.ruby.network.ext_links02.int_node.msg_bytes.Request_Control::1 6584 +system.ruby.network.ext_links02.int_node.msg_bytes.Response_Data::2 20736 +system.ruby.network.ext_links02.int_node.msg_bytes.Response_Data::3 114768 system.ruby.network.ext_links02.int_node.msg_bytes.Response_Control::2 80 system.ruby.network.ext_links02.int_node.msg_bytes.Response_Control::3 16 -system.ruby.network.ext_links02.int_node.msg_bytes.Unblock_Control::4 1784 -system.ruby.network.ext_links02.int_node.msg_bytes.Unblock_Control::5 6648 +system.ruby.network.ext_links02.int_node.msg_bytes.Unblock_Control::4 1712 +system.ruby.network.ext_links02.int_node.msg_bytes.Unblock_Control::5 6480 system.tcp_cntrl1.L1cache.demand_hits 0 # Number of cache demand hits system.tcp_cntrl1.L1cache.demand_misses 0 # Number of cache demand misses system.tcp_cntrl1.L1cache.demand_accesses 0 # Number of cache demand accesses -system.tcp_cntrl1.L1cache.num_data_array_reads 10 # number of data array reads +system.tcp_cntrl1.L1cache.num_data_array_reads 11 # number of data array reads system.tcp_cntrl1.L1cache.num_data_array_writes 108 # number of data array writes -system.tcp_cntrl1.L1cache.num_tag_array_reads 300 # number of tag array reads -system.tcp_cntrl1.L1cache.num_tag_array_writes 289 # number of tag array writes -system.tcp_cntrl1.L1cache.num_tag_array_stalls 44 # number of stalls caused by tag array -system.tcp_cntrl1.coalescer.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states +system.tcp_cntrl1.L1cache.num_tag_array_reads 298 # number of tag array reads +system.tcp_cntrl1.L1cache.num_tag_array_writes 285 # number of tag array writes +system.tcp_cntrl1.L1cache.num_tag_array_stalls 43 # number of stalls caused by tag array +system.tcp_cntrl1.coalescer.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states system.tcp_cntrl1.coalescer.gpu_tcp_ld_hits 1 # loads that hit in the TCP -system.tcp_cntrl1.coalescer.gpu_tcp_ld_transfers 4 # TCP to TCP load transfers +system.tcp_cntrl1.coalescer.gpu_tcp_ld_transfers 8 # TCP to TCP load transfers system.tcp_cntrl1.coalescer.gpu_tcc_ld_hits 0 # loads that hit in the TCC -system.tcp_cntrl1.coalescer.gpu_ld_misses 1 # loads that miss in the GPU -system.tcp_cntrl1.coalescer.gpu_tcp_st_hits 9 # stores that hit in the TCP -system.tcp_cntrl1.coalescer.gpu_tcp_st_transfers 74 # TCP to TCP store transfers +system.tcp_cntrl1.coalescer.gpu_ld_misses 0 # loads that miss in the GPU +system.tcp_cntrl1.coalescer.gpu_tcp_st_hits 11 # stores that hit in the TCP +system.tcp_cntrl1.coalescer.gpu_tcp_st_transfers 69 # TCP to TCP store transfers system.tcp_cntrl1.coalescer.gpu_tcc_st_hits 0 # stores that hit in the TCC system.tcp_cntrl1.coalescer.gpu_st_misses 20 # stores that miss in the GPU system.tcp_cntrl1.coalescer.cp_tcp_ld_hits 0 # loads that hit in the TCP @@ -446,24 +454,23 @@ system.tcp_cntrl1.coalescer.cp_tcp_st_hits 0 # system.tcp_cntrl1.coalescer.cp_tcp_st_transfers 0 # TCP to TCP store transfers system.tcp_cntrl1.coalescer.cp_tcc_st_hits 0 # stores that hit in the TCC system.tcp_cntrl1.coalescer.cp_st_misses 0 # stores that miss in the GPU -system.tcp_cntrl1.sequencer.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states -system.tcp_cntrl1.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states +system.tcp_cntrl1.sequencer.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states +system.tcp_cntrl1.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states system.tcp_cntrl2.L1cache.demand_hits 0 # Number of cache demand hits system.tcp_cntrl2.L1cache.demand_misses 0 # Number of cache demand misses system.tcp_cntrl2.L1cache.demand_accesses 0 # Number of cache demand accesses -system.tcp_cntrl2.L1cache.num_data_array_reads 19 # number of data array reads -system.tcp_cntrl2.L1cache.num_data_array_writes 108 # number of data array writes -system.tcp_cntrl2.L1cache.num_tag_array_reads 302 # number of tag array reads -system.tcp_cntrl2.L1cache.num_tag_array_writes 292 # number of tag array writes -system.tcp_cntrl2.L1cache.num_tag_array_stalls 36 # number of stalls caused by tag array -system.tcp_cntrl2.L1cache.num_data_array_stalls 3 # number of stalls caused by data array -system.tcp_cntrl2.coalescer.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states -system.tcp_cntrl2.coalescer.gpu_tcp_ld_hits 1 # loads that hit in the TCP -system.tcp_cntrl2.coalescer.gpu_tcp_ld_transfers 9 # TCP to TCP load transfers +system.tcp_cntrl2.L1cache.num_data_array_reads 11 # number of data array reads +system.tcp_cntrl2.L1cache.num_data_array_writes 106 # number of data array writes +system.tcp_cntrl2.L1cache.num_tag_array_reads 286 # number of tag array reads +system.tcp_cntrl2.L1cache.num_tag_array_writes 275 # number of tag array writes +system.tcp_cntrl2.L1cache.num_tag_array_stalls 42 # number of stalls caused by tag array +system.tcp_cntrl2.coalescer.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states +system.tcp_cntrl2.coalescer.gpu_tcp_ld_hits 2 # loads that hit in the TCP +system.tcp_cntrl2.coalescer.gpu_tcp_ld_transfers 8 # TCP to TCP load transfers system.tcp_cntrl2.coalescer.gpu_tcc_ld_hits 0 # loads that hit in the TCC -system.tcp_cntrl2.coalescer.gpu_ld_misses 0 # loads that miss in the GPU -system.tcp_cntrl2.coalescer.gpu_tcp_st_hits 7 # stores that hit in the TCP -system.tcp_cntrl2.coalescer.gpu_tcp_st_transfers 72 # TCP to TCP store transfers +system.tcp_cntrl2.coalescer.gpu_ld_misses 1 # loads that miss in the GPU +system.tcp_cntrl2.coalescer.gpu_tcp_st_hits 9 # stores that hit in the TCP +system.tcp_cntrl2.coalescer.gpu_tcp_st_transfers 69 # TCP to TCP store transfers system.tcp_cntrl2.coalescer.gpu_tcc_st_hits 0 # stores that hit in the TCC system.tcp_cntrl2.coalescer.gpu_st_misses 18 # stores that miss in the GPU system.tcp_cntrl2.coalescer.cp_tcp_ld_hits 0 # loads that hit in the TCP @@ -474,26 +481,26 @@ system.tcp_cntrl2.coalescer.cp_tcp_st_hits 0 # system.tcp_cntrl2.coalescer.cp_tcp_st_transfers 0 # TCP to TCP store transfers system.tcp_cntrl2.coalescer.cp_tcc_st_hits 0 # stores that hit in the TCC system.tcp_cntrl2.coalescer.cp_st_misses 0 # stores that miss in the GPU -system.tcp_cntrl2.sequencer.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states -system.tcp_cntrl2.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states +system.tcp_cntrl2.sequencer.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states +system.tcp_cntrl2.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states system.tcp_cntrl3.L1cache.demand_hits 0 # Number of cache demand hits system.tcp_cntrl3.L1cache.demand_misses 0 # Number of cache demand misses system.tcp_cntrl3.L1cache.demand_accesses 0 # Number of cache demand accesses -system.tcp_cntrl3.L1cache.num_data_array_reads 7 # number of data array reads -system.tcp_cntrl3.L1cache.num_data_array_writes 104 # number of data array writes -system.tcp_cntrl3.L1cache.num_tag_array_reads 272 # number of tag array reads -system.tcp_cntrl3.L1cache.num_tag_array_writes 262 # number of tag array writes -system.tcp_cntrl3.L1cache.num_tag_array_stalls 16 # number of stalls caused by tag array +system.tcp_cntrl3.L1cache.num_data_array_reads 8 # number of data array reads +system.tcp_cntrl3.L1cache.num_data_array_writes 95 # number of data array writes +system.tcp_cntrl3.L1cache.num_tag_array_reads 260 # number of tag array reads +system.tcp_cntrl3.L1cache.num_tag_array_writes 253 # number of tag array writes +system.tcp_cntrl3.L1cache.num_tag_array_stalls 29 # number of stalls caused by tag array system.tcp_cntrl3.L1cache.num_data_array_stalls 3 # number of stalls caused by data array -system.tcp_cntrl3.coalescer.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states +system.tcp_cntrl3.coalescer.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states system.tcp_cntrl3.coalescer.gpu_tcp_ld_hits 0 # loads that hit in the TCP -system.tcp_cntrl3.coalescer.gpu_tcp_ld_transfers 13 # TCP to TCP load transfers +system.tcp_cntrl3.coalescer.gpu_tcp_ld_transfers 12 # TCP to TCP load transfers system.tcp_cntrl3.coalescer.gpu_tcc_ld_hits 0 # loads that hit in the TCC system.tcp_cntrl3.coalescer.gpu_ld_misses 0 # loads that miss in the GPU -system.tcp_cntrl3.coalescer.gpu_tcp_st_hits 10 # stores that hit in the TCP -system.tcp_cntrl3.coalescer.gpu_tcp_st_transfers 63 # TCP to TCP store transfers +system.tcp_cntrl3.coalescer.gpu_tcp_st_hits 7 # stores that hit in the TCP +system.tcp_cntrl3.coalescer.gpu_tcp_st_transfers 59 # TCP to TCP store transfers system.tcp_cntrl3.coalescer.gpu_tcc_st_hits 0 # stores that hit in the TCC -system.tcp_cntrl3.coalescer.gpu_st_misses 18 # stores that miss in the GPU +system.tcp_cntrl3.coalescer.gpu_st_misses 17 # stores that miss in the GPU system.tcp_cntrl3.coalescer.cp_tcp_ld_hits 0 # loads that hit in the TCP system.tcp_cntrl3.coalescer.cp_tcp_ld_transfers 0 # TCP to TCP load transfers system.tcp_cntrl3.coalescer.cp_tcc_ld_hits 0 # loads that hit in the TCC @@ -502,23 +509,24 @@ system.tcp_cntrl3.coalescer.cp_tcp_st_hits 0 # system.tcp_cntrl3.coalescer.cp_tcp_st_transfers 0 # TCP to TCP store transfers system.tcp_cntrl3.coalescer.cp_tcc_st_hits 0 # stores that hit in the TCC system.tcp_cntrl3.coalescer.cp_st_misses 0 # stores that miss in the GPU -system.tcp_cntrl3.sequencer.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states -system.tcp_cntrl3.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states +system.tcp_cntrl3.sequencer.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states +system.tcp_cntrl3.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states system.tcp_cntrl4.L1cache.demand_hits 0 # Number of cache demand hits system.tcp_cntrl4.L1cache.demand_misses 0 # Number of cache demand misses system.tcp_cntrl4.L1cache.demand_accesses 0 # Number of cache demand accesses -system.tcp_cntrl4.L1cache.num_data_array_reads 14 # number of data array reads -system.tcp_cntrl4.L1cache.num_data_array_writes 115 # number of data array writes -system.tcp_cntrl4.L1cache.num_tag_array_reads 317 # number of tag array reads -system.tcp_cntrl4.L1cache.num_tag_array_writes 309 # number of tag array writes -system.tcp_cntrl4.L1cache.num_tag_array_stalls 29 # number of stalls caused by tag array -system.tcp_cntrl4.coalescer.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states -system.tcp_cntrl4.coalescer.gpu_tcp_ld_hits 0 # loads that hit in the TCP -system.tcp_cntrl4.coalescer.gpu_tcp_ld_transfers 4 # TCP to TCP load transfers +system.tcp_cntrl4.L1cache.num_data_array_reads 16 # number of data array reads +system.tcp_cntrl4.L1cache.num_data_array_writes 117 # number of data array writes +system.tcp_cntrl4.L1cache.num_tag_array_reads 309 # number of tag array reads +system.tcp_cntrl4.L1cache.num_tag_array_writes 299 # number of tag array writes +system.tcp_cntrl4.L1cache.num_tag_array_stalls 31 # number of stalls caused by tag array +system.tcp_cntrl4.L1cache.num_data_array_stalls 4 # number of stalls caused by data array +system.tcp_cntrl4.coalescer.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states +system.tcp_cntrl4.coalescer.gpu_tcp_ld_hits 1 # loads that hit in the TCP +system.tcp_cntrl4.coalescer.gpu_tcp_ld_transfers 5 # TCP to TCP load transfers system.tcp_cntrl4.coalescer.gpu_tcc_ld_hits 0 # loads that hit in the TCC system.tcp_cntrl4.coalescer.gpu_ld_misses 0 # loads that miss in the GPU -system.tcp_cntrl4.coalescer.gpu_tcp_st_hits 6 # stores that hit in the TCP -system.tcp_cntrl4.coalescer.gpu_tcp_st_transfers 76 # TCP to TCP store transfers +system.tcp_cntrl4.coalescer.gpu_tcp_st_hits 9 # stores that hit in the TCP +system.tcp_cntrl4.coalescer.gpu_tcp_st_transfers 72 # TCP to TCP store transfers system.tcp_cntrl4.coalescer.gpu_tcc_st_hits 0 # stores that hit in the TCC system.tcp_cntrl4.coalescer.gpu_st_misses 26 # stores that miss in the GPU system.tcp_cntrl4.coalescer.cp_tcp_ld_hits 0 # loads that hit in the TCP @@ -529,25 +537,25 @@ system.tcp_cntrl4.coalescer.cp_tcp_st_hits 0 # system.tcp_cntrl4.coalescer.cp_tcp_st_transfers 0 # TCP to TCP store transfers system.tcp_cntrl4.coalescer.cp_tcc_st_hits 0 # stores that hit in the TCC system.tcp_cntrl4.coalescer.cp_st_misses 0 # stores that miss in the GPU -system.tcp_cntrl4.sequencer.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states -system.tcp_cntrl4.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states +system.tcp_cntrl4.sequencer.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states +system.tcp_cntrl4.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states system.tcp_cntrl5.L1cache.demand_hits 0 # Number of cache demand hits system.tcp_cntrl5.L1cache.demand_misses 0 # Number of cache demand misses system.tcp_cntrl5.L1cache.demand_accesses 0 # Number of cache demand accesses -system.tcp_cntrl5.L1cache.num_data_array_reads 10 # number of data array reads -system.tcp_cntrl5.L1cache.num_data_array_writes 107 # number of data array writes -system.tcp_cntrl5.L1cache.num_tag_array_reads 295 # number of tag array reads -system.tcp_cntrl5.L1cache.num_tag_array_writes 287 # number of tag array writes -system.tcp_cntrl5.L1cache.num_tag_array_stalls 31 # number of stalls caused by tag array -system.tcp_cntrl5.coalescer.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states +system.tcp_cntrl5.L1cache.num_data_array_reads 9 # number of data array reads +system.tcp_cntrl5.L1cache.num_data_array_writes 101 # number of data array writes +system.tcp_cntrl5.L1cache.num_tag_array_reads 276 # number of tag array reads +system.tcp_cntrl5.L1cache.num_tag_array_writes 266 # number of tag array writes +system.tcp_cntrl5.L1cache.num_tag_array_stalls 22 # number of stalls caused by tag array +system.tcp_cntrl5.coalescer.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states system.tcp_cntrl5.coalescer.gpu_tcp_ld_hits 0 # loads that hit in the TCP -system.tcp_cntrl5.coalescer.gpu_tcp_ld_transfers 6 # TCP to TCP load transfers +system.tcp_cntrl5.coalescer.gpu_tcp_ld_transfers 3 # TCP to TCP load transfers system.tcp_cntrl5.coalescer.gpu_tcc_ld_hits 0 # loads that hit in the TCC system.tcp_cntrl5.coalescer.gpu_ld_misses 0 # loads that miss in the GPU system.tcp_cntrl5.coalescer.gpu_tcp_st_hits 8 # stores that hit in the TCP -system.tcp_cntrl5.coalescer.gpu_tcp_st_transfers 69 # TCP to TCP store transfers +system.tcp_cntrl5.coalescer.gpu_tcp_st_transfers 67 # TCP to TCP store transfers system.tcp_cntrl5.coalescer.gpu_tcc_st_hits 0 # stores that hit in the TCC -system.tcp_cntrl5.coalescer.gpu_st_misses 23 # stores that miss in the GPU +system.tcp_cntrl5.coalescer.gpu_st_misses 22 # stores that miss in the GPU system.tcp_cntrl5.coalescer.cp_tcp_ld_hits 0 # loads that hit in the TCP system.tcp_cntrl5.coalescer.cp_tcp_ld_transfers 0 # TCP to TCP load transfers system.tcp_cntrl5.coalescer.cp_tcc_ld_hits 0 # loads that hit in the TCC @@ -556,25 +564,25 @@ system.tcp_cntrl5.coalescer.cp_tcp_st_hits 0 # system.tcp_cntrl5.coalescer.cp_tcp_st_transfers 0 # TCP to TCP store transfers system.tcp_cntrl5.coalescer.cp_tcc_st_hits 0 # stores that hit in the TCC system.tcp_cntrl5.coalescer.cp_st_misses 0 # stores that miss in the GPU -system.tcp_cntrl5.sequencer.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states -system.tcp_cntrl5.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states +system.tcp_cntrl5.sequencer.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states +system.tcp_cntrl5.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states system.tcp_cntrl6.L1cache.demand_hits 0 # Number of cache demand hits system.tcp_cntrl6.L1cache.demand_misses 0 # Number of cache demand misses system.tcp_cntrl6.L1cache.demand_accesses 0 # Number of cache demand accesses -system.tcp_cntrl6.L1cache.num_data_array_reads 13 # number of data array reads -system.tcp_cntrl6.L1cache.num_data_array_writes 123 # number of data array writes -system.tcp_cntrl6.L1cache.num_tag_array_reads 342 # number of tag array reads -system.tcp_cntrl6.L1cache.num_tag_array_writes 335 # number of tag array writes -system.tcp_cntrl6.L1cache.num_tag_array_stalls 49 # number of stalls caused by tag array -system.tcp_cntrl6.coalescer.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states +system.tcp_cntrl6.L1cache.num_data_array_reads 15 # number of data array reads +system.tcp_cntrl6.L1cache.num_data_array_writes 120 # number of data array writes +system.tcp_cntrl6.L1cache.num_tag_array_reads 336 # number of tag array reads +system.tcp_cntrl6.L1cache.num_tag_array_writes 330 # number of tag array writes +system.tcp_cntrl6.L1cache.num_tag_array_stalls 44 # number of stalls caused by tag array +system.tcp_cntrl6.coalescer.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states system.tcp_cntrl6.coalescer.gpu_tcp_ld_hits 1 # loads that hit in the TCP -system.tcp_cntrl6.coalescer.gpu_tcp_ld_transfers 11 # TCP to TCP load transfers +system.tcp_cntrl6.coalescer.gpu_tcp_ld_transfers 8 # TCP to TCP load transfers system.tcp_cntrl6.coalescer.gpu_tcc_ld_hits 0 # loads that hit in the TCC system.tcp_cntrl6.coalescer.gpu_ld_misses 1 # loads that miss in the GPU -system.tcp_cntrl6.coalescer.gpu_tcp_st_hits 5 # stores that hit in the TCP +system.tcp_cntrl6.coalescer.gpu_tcp_st_hits 4 # stores that hit in the TCP system.tcp_cntrl6.coalescer.gpu_tcp_st_transfers 86 # TCP to TCP store transfers system.tcp_cntrl6.coalescer.gpu_tcc_st_hits 0 # stores that hit in the TCC -system.tcp_cntrl6.coalescer.gpu_st_misses 19 # stores that miss in the GPU +system.tcp_cntrl6.coalescer.gpu_st_misses 20 # stores that miss in the GPU system.tcp_cntrl6.coalescer.cp_tcp_ld_hits 0 # loads that hit in the TCP system.tcp_cntrl6.coalescer.cp_tcp_ld_transfers 0 # TCP to TCP load transfers system.tcp_cntrl6.coalescer.cp_tcc_ld_hits 0 # loads that hit in the TCC @@ -583,25 +591,25 @@ system.tcp_cntrl6.coalescer.cp_tcp_st_hits 0 # system.tcp_cntrl6.coalescer.cp_tcp_st_transfers 0 # TCP to TCP store transfers system.tcp_cntrl6.coalescer.cp_tcc_st_hits 0 # stores that hit in the TCC system.tcp_cntrl6.coalescer.cp_st_misses 0 # stores that miss in the GPU -system.tcp_cntrl6.sequencer.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states -system.tcp_cntrl6.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states +system.tcp_cntrl6.sequencer.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states +system.tcp_cntrl6.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states system.tcp_cntrl7.L1cache.demand_hits 0 # Number of cache demand hits system.tcp_cntrl7.L1cache.demand_misses 0 # Number of cache demand misses system.tcp_cntrl7.L1cache.demand_accesses 0 # Number of cache demand accesses -system.tcp_cntrl7.L1cache.num_data_array_reads 10 # number of data array reads -system.tcp_cntrl7.L1cache.num_data_array_writes 97 # number of data array writes -system.tcp_cntrl7.L1cache.num_tag_array_reads 263 # number of tag array reads -system.tcp_cntrl7.L1cache.num_tag_array_writes 256 # number of tag array writes +system.tcp_cntrl7.L1cache.num_data_array_reads 13 # number of data array reads +system.tcp_cntrl7.L1cache.num_data_array_writes 101 # number of data array writes +system.tcp_cntrl7.L1cache.num_tag_array_reads 275 # number of tag array reads +system.tcp_cntrl7.L1cache.num_tag_array_writes 266 # number of tag array writes system.tcp_cntrl7.L1cache.num_tag_array_stalls 11 # number of stalls caused by tag array -system.tcp_cntrl7.coalescer.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states -system.tcp_cntrl7.coalescer.gpu_tcp_ld_hits 1 # loads that hit in the TCP -system.tcp_cntrl7.coalescer.gpu_tcp_ld_transfers 10 # TCP to TCP load transfers +system.tcp_cntrl7.coalescer.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states +system.tcp_cntrl7.coalescer.gpu_tcp_ld_hits 2 # loads that hit in the TCP +system.tcp_cntrl7.coalescer.gpu_tcp_ld_transfers 9 # TCP to TCP load transfers system.tcp_cntrl7.coalescer.gpu_tcc_ld_hits 0 # loads that hit in the TCC -system.tcp_cntrl7.coalescer.gpu_ld_misses 1 # loads that miss in the GPU -system.tcp_cntrl7.coalescer.gpu_tcp_st_hits 6 # stores that hit in the TCP -system.tcp_cntrl7.coalescer.gpu_tcp_st_transfers 63 # TCP to TCP store transfers +system.tcp_cntrl7.coalescer.gpu_ld_misses 0 # loads that miss in the GPU +system.tcp_cntrl7.coalescer.gpu_tcp_st_hits 7 # stores that hit in the TCP +system.tcp_cntrl7.coalescer.gpu_tcp_st_transfers 66 # TCP to TCP store transfers system.tcp_cntrl7.coalescer.gpu_tcc_st_hits 0 # stores that hit in the TCC -system.tcp_cntrl7.coalescer.gpu_st_misses 16 # stores that miss in the GPU +system.tcp_cntrl7.coalescer.gpu_st_misses 18 # stores that miss in the GPU system.tcp_cntrl7.coalescer.cp_tcp_ld_hits 0 # loads that hit in the TCP system.tcp_cntrl7.coalescer.cp_tcp_ld_transfers 0 # TCP to TCP load transfers system.tcp_cntrl7.coalescer.cp_tcc_ld_hits 0 # loads that hit in the TCC @@ -610,633 +618,625 @@ system.tcp_cntrl7.coalescer.cp_tcp_st_hits 0 # system.tcp_cntrl7.coalescer.cp_tcp_st_transfers 0 # TCP to TCP store transfers system.tcp_cntrl7.coalescer.cp_tcc_st_hits 0 # stores that hit in the TCC system.tcp_cntrl7.coalescer.cp_st_misses 0 # stores that miss in the GPU -system.tcp_cntrl7.sequencer.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states -system.tcp_cntrl7.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states +system.tcp_cntrl7.sequencer.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states +system.tcp_cntrl7.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states system.sqc_cntrl0.L1cache.demand_hits 0 # Number of cache demand hits system.sqc_cntrl0.L1cache.demand_misses 0 # Number of cache demand misses system.sqc_cntrl0.L1cache.demand_accesses 0 # Number of cache demand accesses system.sqc_cntrl0.L1cache.num_data_array_reads 12 # number of data array reads system.sqc_cntrl0.L1cache.num_data_array_writes 12 # number of data array writes -system.sqc_cntrl0.L1cache.num_tag_array_reads 22 # number of tag array reads -system.sqc_cntrl0.L1cache.num_tag_array_writes 22 # number of tag array writes -system.sqc_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states -system.sqc_cntrl0.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states +system.sqc_cntrl0.L1cache.num_tag_array_reads 23 # number of tag array reads +system.sqc_cntrl0.L1cache.num_tag_array_writes 23 # number of tag array writes +system.sqc_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states +system.sqc_cntrl0.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states system.sqc_cntrl1.L1cache.demand_hits 0 # Number of cache demand hits system.sqc_cntrl1.L1cache.demand_misses 0 # Number of cache demand misses system.sqc_cntrl1.L1cache.demand_accesses 0 # Number of cache demand accesses -system.sqc_cntrl1.L1cache.num_data_array_reads 15 # number of data array reads -system.sqc_cntrl1.L1cache.num_data_array_writes 15 # number of data array writes -system.sqc_cntrl1.L1cache.num_tag_array_reads 29 # number of tag array reads -system.sqc_cntrl1.L1cache.num_tag_array_writes 29 # number of tag array writes -system.sqc_cntrl1.sequencer.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states -system.sqc_cntrl1.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states +system.sqc_cntrl1.L1cache.num_data_array_reads 12 # number of data array reads +system.sqc_cntrl1.L1cache.num_data_array_writes 12 # number of data array writes +system.sqc_cntrl1.L1cache.num_tag_array_reads 23 # number of tag array reads +system.sqc_cntrl1.L1cache.num_tag_array_writes 23 # number of tag array writes +system.sqc_cntrl1.sequencer.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states +system.sqc_cntrl1.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states system.tcc_cntrl0.L2cache.demand_hits 0 # Number of cache demand hits system.tcc_cntrl0.L2cache.demand_misses 0 # Number of cache demand misses system.tcc_cntrl0.L2cache.demand_accesses 0 # Number of cache demand accesses -system.tcc_cntrl0.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states +system.tcc_cntrl0.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states system.tccdir_cntrl0.directory.demand_hits 0 # Number of cache demand hits system.tccdir_cntrl0.directory.demand_misses 0 # Number of cache demand misses system.tccdir_cntrl0.directory.demand_accesses 0 # Number of cache demand accesses -system.tccdir_cntrl0.directory.num_tag_array_reads 917 # number of tag array reads -system.tccdir_cntrl0.directory.num_tag_array_writes 902 # number of tag array writes -system.tccdir_cntrl0.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states -system.ruby.network.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states -system.ruby.network.msg_count.Control 1430 -system.ruby.network.msg_count.Request_Control 1616 -system.ruby.network.msg_count.Response_Data 2430 -system.ruby.network.msg_count.Response_Control 456 -system.ruby.network.msg_count.Writeback_Data 132 -system.ruby.network.msg_count.Writeback_Control 140 -system.ruby.network.msg_count.Unblock_Control 1437 -system.ruby.network.msg_byte.Control 11440 -system.ruby.network.msg_byte.Request_Control 12928 -system.ruby.network.msg_byte.Response_Data 174960 -system.ruby.network.msg_byte.Response_Control 3648 -system.ruby.network.msg_byte.Writeback_Data 9504 -system.ruby.network.msg_byte.Writeback_Control 1120 -system.ruby.network.msg_byte.Unblock_Control 11496 -system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 14181 # Cumulative time (in ticks) in various power states -system.ruby.network.ext_links00.int_node.throttle0.link_utilization 0.250555 -system.ruby.network.ext_links00.int_node.throttle0.msg_count.Request_Control::0 385 +system.tccdir_cntrl0.directory.num_tag_array_reads 896 # number of tag array reads +system.tccdir_cntrl0.directory.num_tag_array_writes 882 # number of tag array writes +system.tccdir_cntrl0.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states +system.ruby.network.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states +system.ruby.network.msg_count.Control 1389 +system.ruby.network.msg_count.Request_Control 1567 +system.ruby.network.msg_count.Response_Data 2360 +system.ruby.network.msg_count.Response_Control 436 +system.ruby.network.msg_count.Writeback_Data 134 +system.ruby.network.msg_count.Writeback_Control 142 +system.ruby.network.msg_count.Unblock_Control 1400 +system.ruby.network.msg_byte.Control 11112 +system.ruby.network.msg_byte.Request_Control 12536 +system.ruby.network.msg_byte.Response_Data 169920 +system.ruby.network.msg_byte.Response_Control 3488 +system.ruby.network.msg_byte.Writeback_Data 9648 +system.ruby.network.msg_byte.Writeback_Control 1136 +system.ruby.network.msg_byte.Unblock_Control 11200 +system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 13821 # Cumulative time (in ticks) in various power states +system.ruby.network.ext_links00.int_node.throttle0.link_utilization 0.254594 +system.ruby.network.ext_links00.int_node.throttle0.msg_count.Request_Control::0 372 system.ruby.network.ext_links00.int_node.throttle0.msg_count.Response_Data::2 85 -system.ruby.network.ext_links00.int_node.throttle0.msg_count.Response_Control::2 227 -system.ruby.network.ext_links00.int_node.throttle0.msg_count.Writeback_Data::2 66 -system.ruby.network.ext_links00.int_node.throttle0.msg_count.Unblock_Control::4 303 -system.ruby.network.ext_links00.int_node.throttle0.msg_bytes.Request_Control::0 3080 +system.ruby.network.ext_links00.int_node.throttle0.msg_count.Response_Control::2 217 +system.ruby.network.ext_links00.int_node.throttle0.msg_count.Writeback_Data::2 67 +system.ruby.network.ext_links00.int_node.throttle0.msg_count.Unblock_Control::4 295 +system.ruby.network.ext_links00.int_node.throttle0.msg_bytes.Request_Control::0 2976 system.ruby.network.ext_links00.int_node.throttle0.msg_bytes.Response_Data::2 6120 -system.ruby.network.ext_links00.int_node.throttle0.msg_bytes.Response_Control::2 1816 -system.ruby.network.ext_links00.int_node.throttle0.msg_bytes.Writeback_Data::2 4752 -system.ruby.network.ext_links00.int_node.throttle0.msg_bytes.Unblock_Control::4 2424 -system.ruby.network.ext_links00.int_node.throttle1.link_utilization 0.113047 -system.ruby.network.ext_links00.int_node.throttle1.msg_count.Control::0 227 -system.ruby.network.ext_links00.int_node.throttle1.msg_count.Response_Data::2 81 -system.ruby.network.ext_links00.int_node.throttle1.msg_count.Writeback_Control::2 70 -system.ruby.network.ext_links00.int_node.throttle1.msg_bytes.Control::0 1816 -system.ruby.network.ext_links00.int_node.throttle1.msg_bytes.Response_Data::2 5832 -system.ruby.network.ext_links00.int_node.throttle1.msg_bytes.Writeback_Control::2 560 -system.ruby.network.ext_links00.int_node.throttle2.link_utilization 0.234028 -system.ruby.network.ext_links00.int_node.throttle2.msg_count.Control::0 81 -system.ruby.network.ext_links00.int_node.throttle2.msg_count.Response_Data::2 227 -system.ruby.network.ext_links00.int_node.throttle2.msg_bytes.Control::0 648 -system.ruby.network.ext_links00.int_node.throttle2.msg_bytes.Response_Data::2 16344 -system.ruby.network.ext_links01.int_node.throttle0.link_utilization 0.113047 -system.ruby.network.ext_links01.int_node.throttle0.msg_count.Control::0 227 -system.ruby.network.ext_links01.int_node.throttle0.msg_count.Response_Data::2 81 -system.ruby.network.ext_links01.int_node.throttle0.msg_count.Writeback_Control::2 70 -system.ruby.network.ext_links01.int_node.throttle0.msg_bytes.Control::0 1816 -system.ruby.network.ext_links01.int_node.throttle0.msg_bytes.Response_Data::2 5832 -system.ruby.network.ext_links01.int_node.throttle0.msg_bytes.Writeback_Control::2 560 -system.ruby.network.ext_links01.int_node.throttle1.link_utilization 0.128914 -system.ruby.network.ext_links01.int_node.throttle1.msg_count.Request_Control::0 153 -system.ruby.network.ext_links01.int_node.throttle1.msg_count.Response_Data::2 14 -system.ruby.network.ext_links01.int_node.throttle1.msg_count.Response_Control::2 217 -system.ruby.network.ext_links01.int_node.throttle1.msg_count.Writeback_Data::2 66 -system.ruby.network.ext_links01.int_node.throttle1.msg_count.Unblock_Control::4 80 -system.ruby.network.ext_links01.int_node.throttle1.msg_bytes.Request_Control::0 1224 -system.ruby.network.ext_links01.int_node.throttle1.msg_bytes.Response_Data::2 1008 -system.ruby.network.ext_links01.int_node.throttle1.msg_bytes.Response_Control::2 1736 -system.ruby.network.ext_links01.int_node.throttle1.msg_bytes.Writeback_Data::2 4752 -system.ruby.network.ext_links01.int_node.throttle1.msg_bytes.Unblock_Control::4 640 -system.ruby.network.ext_links02.int_node.throttle0.link_utilization 0.115361 -system.ruby.network.ext_links02.int_node.throttle0.msg_count.Control::1 102 -system.ruby.network.ext_links02.int_node.throttle0.msg_count.Response_Data::3 105 -system.ruby.network.ext_links02.int_node.throttle0.msg_bytes.Control::1 816 -system.ruby.network.ext_links02.int_node.throttle0.msg_bytes.Response_Data::3 7560 -system.ruby.network.ext_links02.int_node.throttle1.link_utilization 0.108750 -system.ruby.network.ext_links02.int_node.throttle1.msg_count.Control::1 96 -system.ruby.network.ext_links02.int_node.throttle1.msg_count.Response_Data::3 99 -system.ruby.network.ext_links02.int_node.throttle1.msg_bytes.Control::1 768 -system.ruby.network.ext_links02.int_node.throttle1.msg_bytes.Response_Data::3 7128 -system.ruby.network.ext_links02.int_node.throttle2.link_utilization 0.109742 -system.ruby.network.ext_links02.int_node.throttle2.msg_count.Control::1 105 -system.ruby.network.ext_links02.int_node.throttle2.msg_count.Response_Data::3 99 -system.ruby.network.ext_links02.int_node.throttle2.msg_bytes.Control::1 840 -system.ruby.network.ext_links02.int_node.throttle2.msg_bytes.Response_Data::3 7128 -system.ruby.network.ext_links02.int_node.throttle3.link_utilization 0.102690 +system.ruby.network.ext_links00.int_node.throttle0.msg_bytes.Response_Control::2 1736 +system.ruby.network.ext_links00.int_node.throttle0.msg_bytes.Writeback_Data::2 4824 +system.ruby.network.ext_links00.int_node.throttle0.msg_bytes.Unblock_Control::4 2360 +system.ruby.network.ext_links00.int_node.throttle1.link_utilization 0.115879 +system.ruby.network.ext_links00.int_node.throttle1.msg_count.Control::0 216 +system.ruby.network.ext_links00.int_node.throttle1.msg_count.Response_Data::2 82 +system.ruby.network.ext_links00.int_node.throttle1.msg_count.Writeback_Control::2 71 +system.ruby.network.ext_links00.int_node.throttle1.msg_bytes.Control::0 1728 +system.ruby.network.ext_links00.int_node.throttle1.msg_bytes.Response_Data::2 5904 +system.ruby.network.ext_links00.int_node.throttle1.msg_bytes.Writeback_Control::2 568 +system.ruby.network.ext_links00.int_node.throttle2.link_utilization 0.229271 +system.ruby.network.ext_links00.int_node.throttle2.msg_count.Control::0 84 +system.ruby.network.ext_links00.int_node.throttle2.msg_count.Response_Data::2 216 +system.ruby.network.ext_links00.int_node.throttle2.msg_bytes.Control::0 672 +system.ruby.network.ext_links00.int_node.throttle2.msg_bytes.Response_Data::2 15552 +system.ruby.network.ext_links01.int_node.throttle0.link_utilization 0.115879 +system.ruby.network.ext_links01.int_node.throttle0.msg_count.Control::0 216 +system.ruby.network.ext_links01.int_node.throttle0.msg_count.Response_Data::2 82 +system.ruby.network.ext_links01.int_node.throttle0.msg_count.Writeback_Control::2 71 +system.ruby.network.ext_links01.int_node.throttle0.msg_bytes.Control::0 1728 +system.ruby.network.ext_links01.int_node.throttle0.msg_bytes.Response_Data::2 5904 +system.ruby.network.ext_links01.int_node.throttle0.msg_bytes.Writeback_Control::2 568 +system.ruby.network.ext_links01.int_node.throttle1.link_utilization 0.131480 +system.ruby.network.ext_links01.int_node.throttle1.msg_count.Request_Control::0 155 +system.ruby.network.ext_links01.int_node.throttle1.msg_count.Response_Data::2 13 +system.ruby.network.ext_links01.int_node.throttle1.msg_count.Response_Control::2 207 +system.ruby.network.ext_links01.int_node.throttle1.msg_count.Writeback_Data::2 67 +system.ruby.network.ext_links01.int_node.throttle1.msg_count.Unblock_Control::4 81 +system.ruby.network.ext_links01.int_node.throttle1.msg_bytes.Request_Control::0 1240 +system.ruby.network.ext_links01.int_node.throttle1.msg_bytes.Response_Data::2 936 +system.ruby.network.ext_links01.int_node.throttle1.msg_bytes.Response_Control::2 1656 +system.ruby.network.ext_links01.int_node.throttle1.msg_bytes.Writeback_Data::2 4824 +system.ruby.network.ext_links01.int_node.throttle1.msg_bytes.Unblock_Control::4 648 +system.ruby.network.ext_links02.int_node.throttle0.link_utilization 0.116105 +system.ruby.network.ext_links02.int_node.throttle0.msg_count.Control::1 100 +system.ruby.network.ext_links02.int_node.throttle0.msg_count.Response_Data::3 103 +system.ruby.network.ext_links02.int_node.throttle0.msg_bytes.Control::1 800 +system.ruby.network.ext_links02.int_node.throttle0.msg_bytes.Response_Data::3 7416 +system.ruby.network.ext_links02.int_node.throttle1.link_utilization 0.109661 +system.ruby.network.ext_links02.int_node.throttle1.msg_count.Control::1 97 +system.ruby.network.ext_links02.int_node.throttle1.msg_count.Response_Data::3 97 +system.ruby.network.ext_links02.int_node.throttle1.msg_bytes.Control::1 776 +system.ruby.network.ext_links02.int_node.throttle1.msg_bytes.Response_Data::3 6984 +system.ruby.network.ext_links02.int_node.throttle2.link_utilization 0.108078 +system.ruby.network.ext_links02.int_node.throttle2.msg_count.Control::1 92 +system.ruby.network.ext_links02.int_node.throttle2.msg_count.Response_Data::3 96 +system.ruby.network.ext_links02.int_node.throttle2.msg_bytes.Control::1 736 +system.ruby.network.ext_links02.int_node.throttle2.msg_bytes.Response_Data::3 6912 +system.ruby.network.ext_links02.int_node.throttle3.link_utilization 0.099260 system.ruby.network.ext_links02.int_node.throttle3.msg_count.Control::1 86 -system.ruby.network.ext_links02.int_node.throttle3.msg_count.Response_Data::3 94 +system.ruby.network.ext_links02.int_node.throttle3.msg_count.Response_Data::3 88 system.ruby.network.ext_links02.int_node.throttle3.msg_bytes.Control::1 688 -system.ruby.network.ext_links02.int_node.throttle3.msg_bytes.Response_Data::3 6768 -system.ruby.network.ext_links02.int_node.throttle4.link_utilization 0.116573 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-system.ruby.network.ext_links02.int_node.throttle6.link_utilization 0.128473 -system.ruby.network.ext_links02.int_node.throttle6.msg_count.Control::1 113 -system.ruby.network.ext_links02.int_node.throttle6.msg_count.Response_Data::3 117 -system.ruby.network.ext_links02.int_node.throttle6.msg_bytes.Control::1 904 -system.ruby.network.ext_links02.int_node.throttle6.msg_bytes.Response_Data::3 8424 -system.ruby.network.ext_links02.int_node.throttle7.link_utilization 0.098944 -system.ruby.network.ext_links02.int_node.throttle7.msg_count.Control::1 88 -system.ruby.network.ext_links02.int_node.throttle7.msg_count.Response_Data::3 90 -system.ruby.network.ext_links02.int_node.throttle7.msg_bytes.Control::1 704 -system.ruby.network.ext_links02.int_node.throttle7.msg_bytes.Response_Data::3 6480 +system.ruby.network.ext_links02.int_node.throttle4.msg_bytes.Response_Data::3 7416 +system.ruby.network.ext_links02.int_node.throttle5.link_utilization 0.103556 +system.ruby.network.ext_links02.int_node.throttle5.msg_count.Control::1 88 +system.ruby.network.ext_links02.int_node.throttle5.msg_count.Response_Data::3 92 +system.ruby.network.ext_links02.int_node.throttle5.msg_bytes.Control::1 704 +system.ruby.network.ext_links02.int_node.throttle5.msg_bytes.Response_Data::3 6624 +system.ruby.network.ext_links02.int_node.throttle6.link_utilization 0.129558 +system.ruby.network.ext_links02.int_node.throttle6.msg_count.Control::1 111 +system.ruby.network.ext_links02.int_node.throttle6.msg_count.Response_Data::3 115 +system.ruby.network.ext_links02.int_node.throttle6.msg_bytes.Control::1 888 +system.ruby.network.ext_links02.int_node.throttle6.msg_bytes.Response_Data::3 8280 +system.ruby.network.ext_links02.int_node.throttle7.link_utilization 0.104687 +system.ruby.network.ext_links02.int_node.throttle7.msg_count.Control::1 89 +system.ruby.network.ext_links02.int_node.throttle7.msg_count.Response_Data::3 93 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56376 system.ruby.network.ext_links02.int_node.throttle9.msg_bytes.Response_Control::3 16 -system.ruby.network.ext_links02.int_node.throttle9.msg_bytes.Unblock_Control::5 6648 -system.ruby.network.ext_links02.int_node.throttle10.link_utilization 0.013002 -system.ruby.network.ext_links02.int_node.throttle10.msg_count.Control::1 10 +system.ruby.network.ext_links02.int_node.throttle9.msg_bytes.Unblock_Control::5 6480 +system.ruby.network.ext_links02.int_node.throttle10.link_utilization 0.013453 +system.ruby.network.ext_links02.int_node.throttle10.msg_count.Control::1 11 system.ruby.network.ext_links02.int_node.throttle10.msg_count.Response_Data::3 12 -system.ruby.network.ext_links02.int_node.throttle10.msg_bytes.Control::1 80 +system.ruby.network.ext_links02.int_node.throttle10.msg_bytes.Control::1 88 system.ruby.network.ext_links02.int_node.throttle10.msg_bytes.Response_Data::3 864 -system.ruby.network.ext_links02.int_node.throttle11.link_utilization 0.016417 -system.ruby.network.ext_links02.int_node.throttle11.msg_count.Control::1 14 -system.ruby.network.ext_links02.int_node.throttle11.msg_count.Response_Data::3 15 -system.ruby.network.ext_links02.int_node.throttle11.msg_bytes.Control::1 112 -system.ruby.network.ext_links02.int_node.throttle11.msg_bytes.Response_Data::3 1080 -system.ruby.network.ext_links02.int_node.throttle12.link_utilization 0.121642 -system.ruby.network.ext_links02.int_node.throttle12.msg_count.Request_Control::0 232 -system.ruby.network.ext_links02.int_node.throttle12.msg_count.Response_Data::2 71 +system.ruby.network.ext_links02.int_node.throttle11.link_utilization 0.013453 +system.ruby.network.ext_links02.int_node.throttle11.msg_count.Control::1 11 +system.ruby.network.ext_links02.int_node.throttle11.msg_count.Response_Data::3 12 +system.ruby.network.ext_links02.int_node.throttle11.msg_bytes.Control::1 88 +system.ruby.network.ext_links02.int_node.throttle11.msg_bytes.Response_Data::3 864 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36624 0.00% 0.00% -system.ruby.CorePair_Controller.PrbInvData 223 0.00% 0.00% +system.ruby.CorePair_Controller.NB_AckM 78 0.00% 0.00% +system.ruby.CorePair_Controller.NB_AckWB 71 0.00% 0.00% +system.ruby.CorePair_Controller.L1D0_Repl 11 0.00% 0.00% +system.ruby.CorePair_Controller.L2_Repl 35555 0.00% 0.00% +system.ruby.CorePair_Controller.PrbInvData 212 0.00% 0.00% system.ruby.CorePair_Controller.PrbShrData 4 0.00% 0.00% system.ruby.CorePair_Controller.I.C0_Load_L1miss 1 0.00% 0.00% -system.ruby.CorePair_Controller.I.C1_Load_L1miss 1 0.00% 0.00% +system.ruby.CorePair_Controller.I.C1_Load_L1miss 2 0.00% 0.00% system.ruby.CorePair_Controller.I.Ifetch0_L1miss 2 0.00% 0.00% system.ruby.CorePair_Controller.I.Ifetch1_L1miss 1 0.00% 0.00% system.ruby.CorePair_Controller.I.C0_Store_L1miss 41 0.00% 0.00% -system.ruby.CorePair_Controller.I.C1_Store_L1miss 37 0.00% 0.00% -system.ruby.CorePair_Controller.I.PrbInvData 209 0.00% 0.00% -system.ruby.CorePair_Controller.I.PrbShrData 3 0.00% 0.00% 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system.ruby.CorePair_Controller.I_M0.NB_AckM 35 0.00% 0.00% system.ruby.CorePair_Controller.I_M0.L1D0_Repl 11 0.00% 0.00% -system.ruby.CorePair_Controller.I_M0.L2_Repl 16208 0.00% 0.00% +system.ruby.CorePair_Controller.I_M0.L2_Repl 15350 0.00% 0.00% system.ruby.CorePair_Controller.I_M1.C0_Store_L1miss 3 0.00% 0.00% -system.ruby.CorePair_Controller.I_M1.NB_AckM 34 0.00% 0.00% -system.ruby.CorePair_Controller.I_M1.L2_Repl 14782 0.00% 0.00% +system.ruby.CorePair_Controller.I_M1.NB_AckM 35 0.00% 0.00% +system.ruby.CorePair_Controller.I_M1.L2_Repl 14410 0.00% 0.00% system.ruby.CorePair_Controller.I_M0M1.NB_AckM 5 0.00% 0.00% -system.ruby.CorePair_Controller.I_M0M1.L2_Repl 3020 0.00% 0.00% +system.ruby.CorePair_Controller.I_M0M1.L2_Repl 3283 0.00% 0.00% system.ruby.CorePair_Controller.I_M1M0.NB_AckM 3 0.00% 0.00% -system.ruby.CorePair_Controller.I_M1M0.L2_Repl 1059 0.00% 0.00% +system.ruby.CorePair_Controller.I_M1M0.L2_Repl 1200 0.00% 0.00% system.ruby.CorePair_Controller.I_E0S.NB_AckS 1 0.00% 0.00% -system.ruby.CorePair_Controller.I_E0S.L1D0_Repl 8 0.00% 0.00% -system.ruby.CorePair_Controller.I_E0S.L2_Repl 493 0.00% 0.00% +system.ruby.CorePair_Controller.I_E0S.L2_Repl 404 0.00% 0.00% system.ruby.CorePair_Controller.I_E1S.NB_AckS 1 0.00% 0.00% -system.ruby.CorePair_Controller.I_E1S.L2_Repl 638 0.00% 0.00% +system.ruby.CorePair_Controller.I_E1S.L2_Repl 392 0.00% 0.00% system.ruby.CorePair_Controller.ES_I.NB_AckWB 2 0.00% 0.00% -system.ruby.CorePair_Controller.MO_I.NB_AckWB 64 0.00% 0.00% -system.ruby.CorePair_Controller.MO_I.PrbInvData 5 0.00% 0.00% -system.ruby.CorePair_Controller.S0.C1_Store_L1miss 31 0.00% 0.00% +system.ruby.CorePair_Controller.MO_I.NB_AckWB 65 0.00% 0.00% +system.ruby.CorePair_Controller.MO_I.PrbInvData 4 0.00% 0.00% +system.ruby.CorePair_Controller.S0.C1_Store_L1miss 29 0.00% 0.00% system.ruby.CorePair_Controller.S0.NB_AckS 1 0.00% 0.00% -system.ruby.CorePair_Controller.S0.L2_Repl 352 0.00% 0.00% +system.ruby.CorePair_Controller.S0.L2_Repl 444 0.00% 0.00% system.ruby.CorePair_Controller.S1.NB_AckS 1 0.00% 0.00% system.ruby.CorePair_Controller.I_C.NB_AckWB 4 0.00% 0.00% -system.ruby.Directory_Controller.RdBlkS 3 0.00% 0.00% -system.ruby.Directory_Controller.RdBlkM 309 0.00% 0.00% +system.ruby.Directory_Controller.RdBlkS 4 0.00% 0.00% +system.ruby.Directory_Controller.RdBlkM 297 0.00% 0.00% system.ruby.Directory_Controller.RdBlk 6 0.00% 0.00% -system.ruby.Directory_Controller.VicDirty 68 0.00% 0.00% +system.ruby.Directory_Controller.VicDirty 69 0.00% 0.00% system.ruby.Directory_Controller.VicClean 2 0.00% 0.00% -system.ruby.Directory_Controller.CPUData 66 0.00% 0.00% +system.ruby.Directory_Controller.CPUData 67 0.00% 0.00% system.ruby.Directory_Controller.StaleWB 4 0.00% 0.00% -system.ruby.Directory_Controller.CPUPrbResp 308 0.00% 0.00% -system.ruby.Directory_Controller.ProbeAcksComplete 308 0.00% 0.00% -system.ruby.Directory_Controller.L3Hit 49 0.00% 0.00% -system.ruby.Directory_Controller.MemData 259 0.00% 0.00% -system.ruby.Directory_Controller.WBAck 9 0.00% 0.00% -system.ruby.Directory_Controller.CoreUnblock 303 0.00% 0.00% -system.ruby.Directory_Controller.U.RdBlkS 3 0.00% 0.00% -system.ruby.Directory_Controller.U.RdBlkM 300 0.00% 0.00% -system.ruby.Directory_Controller.U.RdBlk 5 0.00% 0.00% -system.ruby.Directory_Controller.U.VicDirty 68 0.00% 0.00% +system.ruby.Directory_Controller.CPUPrbResp 298 0.00% 0.00% +system.ruby.Directory_Controller.ProbeAcksComplete 298 0.00% 0.00% +system.ruby.Directory_Controller.L3Hit 45 0.00% 0.00% +system.ruby.Directory_Controller.MemData 256 0.00% 0.00% +system.ruby.Directory_Controller.WBAck 14 0.00% 0.00% +system.ruby.Directory_Controller.CoreUnblock 295 0.00% 0.00% +system.ruby.Directory_Controller.U.RdBlkS 4 0.00% 0.00% +system.ruby.Directory_Controller.U.RdBlkM 291 0.00% 0.00% +system.ruby.Directory_Controller.U.RdBlk 6 0.00% 0.00% +system.ruby.Directory_Controller.U.VicDirty 69 0.00% 0.00% system.ruby.Directory_Controller.U.VicClean 2 0.00% 0.00% -system.ruby.Directory_Controller.U.WBAck 9 0.00% 0.00% -system.ruby.Directory_Controller.BL.RdBlkM 1 0.00% 0.00% -system.ruby.Directory_Controller.BL.CPUData 66 0.00% 0.00% +system.ruby.Directory_Controller.U.WBAck 14 0.00% 0.00% +system.ruby.Directory_Controller.BL.CPUData 67 0.00% 0.00% system.ruby.Directory_Controller.BL.StaleWB 4 0.00% 0.00% -system.ruby.Directory_Controller.BM_M.MemData 8 0.00% 0.00% +system.ruby.Directory_Controller.BM_M.MemData 9 0.00% 0.00% system.ruby.Directory_Controller.BS_PM.L3Hit 1 0.00% 0.00% -system.ruby.Directory_Controller.BS_PM.MemData 2 0.00% 0.00% +system.ruby.Directory_Controller.BS_PM.MemData 3 0.00% 0.00% system.ruby.Directory_Controller.BM_PM.RdBlkM 1 0.00% 0.00% -system.ruby.Directory_Controller.BM_PM.CPUPrbResp 12 0.00% 0.00% -system.ruby.Directory_Controller.BM_PM.ProbeAcksComplete 8 0.00% 0.00% -system.ruby.Directory_Controller.BM_PM.L3Hit 46 0.00% 0.00% -system.ruby.Directory_Controller.BM_PM.MemData 246 0.00% 0.00% -system.ruby.Directory_Controller.B_PM.L3Hit 2 0.00% 0.00% +system.ruby.Directory_Controller.BM_PM.CPUPrbResp 13 0.00% 0.00% +system.ruby.Directory_Controller.BM_PM.ProbeAcksComplete 9 0.00% 0.00% +system.ruby.Directory_Controller.BM_PM.L3Hit 41 0.00% 0.00% +system.ruby.Directory_Controller.BM_PM.MemData 241 0.00% 0.00% +system.ruby.Directory_Controller.B_PM.L3Hit 3 0.00% 0.00% system.ruby.Directory_Controller.B_PM.MemData 3 0.00% 0.00% system.ruby.Directory_Controller.BS_Pm.CPUPrbResp 3 0.00% 0.00% system.ruby.Directory_Controller.BS_Pm.ProbeAcksComplete 3 0.00% 0.00% system.ruby.Directory_Controller.BM_Pm.RdBlkM 3 0.00% 0.00% -system.ruby.Directory_Controller.BM_Pm.CPUPrbResp 288 0.00% 0.00% -system.ruby.Directory_Controller.BM_Pm.ProbeAcksComplete 292 0.00% 0.00% +system.ruby.Directory_Controller.BM_Pm.CPUPrbResp 277 0.00% 0.00% +system.ruby.Directory_Controller.BM_Pm.ProbeAcksComplete 281 0.00% 0.00% system.ruby.Directory_Controller.B_Pm.CPUPrbResp 5 0.00% 0.00% system.ruby.Directory_Controller.B_Pm.ProbeAcksComplete 5 0.00% 0.00% -system.ruby.Directory_Controller.B.RdBlkM 4 0.00% 0.00% -system.ruby.Directory_Controller.B.RdBlk 1 0.00% 0.00% -system.ruby.Directory_Controller.B.CoreUnblock 303 0.00% 0.00% +system.ruby.Directory_Controller.B.RdBlkM 2 0.00% 0.00% +system.ruby.Directory_Controller.B.CoreUnblock 295 0.00% 0.00% system.ruby.LD.latency_hist_seqr::bucket_size 1024 system.ruby.LD.latency_hist_seqr::max_bucket 10239 system.ruby.LD.latency_hist_seqr::samples 1 -system.ruby.LD.latency_hist_seqr::mean 5324 -system.ruby.LD.latency_hist_seqr::gmean 5324.000000 +system.ruby.LD.latency_hist_seqr::mean 5256 +system.ruby.LD.latency_hist_seqr::gmean 5256.000000 system.ruby.LD.latency_hist_seqr::stdev nan system.ruby.LD.latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.latency_hist_seqr::total 1 -system.ruby.LD.latency_hist_coalsr::bucket_size 128 -system.ruby.LD.latency_hist_coalsr::max_bucket 1279 -system.ruby.LD.latency_hist_coalsr::samples 69 -system.ruby.LD.latency_hist_coalsr::mean 111.289855 -system.ruby.LD.latency_hist_coalsr::gmean 81.460116 -system.ruby.LD.latency_hist_coalsr::stdev 88.701101 -system.ruby.LD.latency_hist_coalsr | 63 91.30% 91.30% | 2 2.90% 94.20% | 2 2.90% 97.10% | 1 1.45% 98.55% | 0 0.00% 98.55% | 1 1.45% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.latency_hist_coalsr::total 69 +system.ruby.LD.latency_hist_coalsr::bucket_size 64 +system.ruby.LD.latency_hist_coalsr::max_bucket 639 +system.ruby.LD.latency_hist_coalsr::samples 72 +system.ruby.LD.latency_hist_coalsr::mean 101.402778 +system.ruby.LD.latency_hist_coalsr::gmean 68.071118 +system.ruby.LD.latency_hist_coalsr::stdev 67.272969 +system.ruby.LD.latency_hist_coalsr | 7 9.72% 9.72% | 60 83.33% 93.06% | 1 1.39% 94.44% | 0 0.00% 94.44% | 3 4.17% 98.61% | 0 0.00% 98.61% | 0 0.00% 98.61% | 1 1.39% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.latency_hist_coalsr::total 72 system.ruby.LD.hit_latency_hist_seqr::bucket_size 1024 system.ruby.LD.hit_latency_hist_seqr::max_bucket 10239 system.ruby.LD.hit_latency_hist_seqr::samples 1 -system.ruby.LD.hit_latency_hist_seqr::mean 5324 -system.ruby.LD.hit_latency_hist_seqr::gmean 5324.000000 +system.ruby.LD.hit_latency_hist_seqr::mean 5256 +system.ruby.LD.hit_latency_hist_seqr::gmean 5256.000000 system.ruby.LD.hit_latency_hist_seqr::stdev nan system.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.hit_latency_hist_seqr::total 1 -system.ruby.LD.miss_latency_hist_coalsr::bucket_size 128 -system.ruby.LD.miss_latency_hist_coalsr::max_bucket 1279 -system.ruby.LD.miss_latency_hist_coalsr::samples 69 -system.ruby.LD.miss_latency_hist_coalsr::mean 111.289855 -system.ruby.LD.miss_latency_hist_coalsr::gmean 81.460116 -system.ruby.LD.miss_latency_hist_coalsr::stdev 88.701101 -system.ruby.LD.miss_latency_hist_coalsr | 63 91.30% 91.30% | 2 2.90% 94.20% | 2 2.90% 97.10% | 1 1.45% 98.55% | 0 0.00% 98.55% | 1 1.45% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.miss_latency_hist_coalsr::total 69 +system.ruby.LD.miss_latency_hist_coalsr::bucket_size 64 +system.ruby.LD.miss_latency_hist_coalsr::max_bucket 639 +system.ruby.LD.miss_latency_hist_coalsr::samples 72 +system.ruby.LD.miss_latency_hist_coalsr::mean 101.402778 +system.ruby.LD.miss_latency_hist_coalsr::gmean 68.071118 +system.ruby.LD.miss_latency_hist_coalsr::stdev 67.272969 +system.ruby.LD.miss_latency_hist_coalsr | 7 9.72% 9.72% | 60 83.33% 93.06% | 1 1.39% 94.44% | 0 0.00% 94.44% | 3 4.17% 98.61% | 0 0.00% 98.61% | 0 0.00% 98.61% | 1 1.39% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.miss_latency_hist_coalsr::total 72 system.ruby.ST.latency_hist_seqr::bucket_size 1024 system.ruby.ST.latency_hist_seqr::max_bucket 10239 system.ruby.ST.latency_hist_seqr::samples 46 -system.ruby.ST.latency_hist_seqr::mean 3269.239130 -system.ruby.ST.latency_hist_seqr::gmean 1783.447677 -system.ruby.ST.latency_hist_seqr::stdev 1934.416354 -system.ruby.ST.latency_hist_seqr | 11 23.91% 23.91% | 3 6.52% 30.43% | 3 6.52% 36.96% | 7 15.22% 52.17% | 18 39.13% 91.30% | 4 8.70% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.latency_hist_seqr::mean 3234.260870 +system.ruby.ST.latency_hist_seqr::gmean 1760.149244 +system.ruby.ST.latency_hist_seqr::stdev 1907.255858 +system.ruby.ST.latency_hist_seqr | 11 23.91% 23.91% | 3 6.52% 30.43% | 3 6.52% 36.96% | 7 15.22% 52.17% | 20 43.48% 95.65% | 2 4.35% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ST.latency_hist_seqr::total 46 system.ruby.ST.latency_hist_coalsr::bucket_size 128 system.ruby.ST.latency_hist_coalsr::max_bucket 1279 -system.ruby.ST.latency_hist_coalsr::samples 803 -system.ruby.ST.latency_hist_coalsr::mean 231.610212 -system.ruby.ST.latency_hist_coalsr::gmean 117.827816 -system.ruby.ST.latency_hist_coalsr::stdev 248.057845 -system.ruby.ST.latency_hist_coalsr | 517 64.38% 64.38% | 28 3.49% 67.87% | 108 13.45% 81.32% | 38 4.73% 86.05% | 33 4.11% 90.16% | 19 2.37% 92.53% | 33 4.11% 96.64% | 23 2.86% 99.50% | 4 0.50% 100.00% | 0 0.00% 100.00% -system.ruby.ST.latency_hist_coalsr::total 803 +system.ruby.ST.latency_hist_coalsr::samples 786 +system.ruby.ST.latency_hist_coalsr::mean 225.797710 +system.ruby.ST.latency_hist_coalsr::gmean 112.544056 +system.ruby.ST.latency_hist_coalsr::stdev 244.652456 +system.ruby.ST.latency_hist_coalsr | 506 64.38% 64.38% | 35 4.45% 68.83% | 108 13.74% 82.57% | 36 4.58% 87.15% | 24 3.05% 90.20% | 19 2.42% 92.62% | 32 4.07% 96.69% | 23 2.93% 99.62% | 3 0.38% 100.00% | 0 0.00% 100.00% +system.ruby.ST.latency_hist_coalsr::total 786 system.ruby.ST.hit_latency_hist_seqr::bucket_size 1024 system.ruby.ST.hit_latency_hist_seqr::max_bucket 10239 system.ruby.ST.hit_latency_hist_seqr::samples 40 -system.ruby.ST.hit_latency_hist_seqr::mean 3606.650000 -system.ruby.ST.hit_latency_hist_seqr::gmean 2691.718970 -system.ruby.ST.hit_latency_hist_seqr::stdev 1792.166924 -system.ruby.ST.hit_latency_hist_seqr | 7 17.50% 17.50% | 3 7.50% 25.00% | 1 2.50% 27.50% | 7 17.50% 45.00% | 18 45.00% 90.00% | 4 10.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.hit_latency_hist_seqr::mean 3566.725000 +system.ruby.ST.hit_latency_hist_seqr::gmean 2651.630943 +system.ruby.ST.hit_latency_hist_seqr::stdev 1765.919997 +system.ruby.ST.hit_latency_hist_seqr | 7 17.50% 17.50% | 3 7.50% 25.00% | 1 2.50% 27.50% | 7 17.50% 45.00% | 20 50.00% 95.00% | 2 5.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ST.hit_latency_hist_seqr::total 40 system.ruby.ST.miss_latency_hist_seqr::bucket_size 512 system.ruby.ST.miss_latency_hist_seqr::max_bucket 5119 system.ruby.ST.miss_latency_hist_seqr::samples 6 -system.ruby.ST.miss_latency_hist_seqr::mean 1019.833333 -system.ruby.ST.miss_latency_hist_seqr::gmean 114.673945 -system.ruby.ST.miss_latency_hist_seqr::stdev 1281.644790 -system.ruby.ST.miss_latency_hist_seqr | 3 50.00% 50.00% | 1 16.67% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 2 33.33% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.miss_latency_hist_seqr::mean 1017.833333 +system.ruby.ST.miss_latency_hist_seqr::gmean 114.584426 +system.ruby.ST.miss_latency_hist_seqr::stdev 1278.753677 +system.ruby.ST.miss_latency_hist_seqr | 3 50.00% 50.00% | 1 16.67% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 1 16.67% 83.33% | 1 16.67% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ST.miss_latency_hist_seqr::total 6 system.ruby.ST.miss_latency_hist_coalsr::bucket_size 128 system.ruby.ST.miss_latency_hist_coalsr::max_bucket 1279 -system.ruby.ST.miss_latency_hist_coalsr::samples 803 -system.ruby.ST.miss_latency_hist_coalsr::mean 231.610212 -system.ruby.ST.miss_latency_hist_coalsr::gmean 117.827816 -system.ruby.ST.miss_latency_hist_coalsr::stdev 248.057845 -system.ruby.ST.miss_latency_hist_coalsr | 517 64.38% 64.38% | 28 3.49% 67.87% | 108 13.45% 81.32% | 38 4.73% 86.05% | 33 4.11% 90.16% | 19 2.37% 92.53% | 33 4.11% 96.64% | 23 2.86% 99.50% | 4 0.50% 100.00% | 0 0.00% 100.00% -system.ruby.ST.miss_latency_hist_coalsr::total 803 +system.ruby.ST.miss_latency_hist_coalsr::samples 786 +system.ruby.ST.miss_latency_hist_coalsr::mean 225.797710 +system.ruby.ST.miss_latency_hist_coalsr::gmean 112.544056 +system.ruby.ST.miss_latency_hist_coalsr::stdev 244.652456 +system.ruby.ST.miss_latency_hist_coalsr | 506 64.38% 64.38% | 35 4.45% 68.83% | 108 13.74% 82.57% | 36 4.58% 87.15% | 24 3.05% 90.20% | 19 2.42% 92.62% | 32 4.07% 96.69% | 23 2.93% 99.62% | 3 0.38% 100.00% | 0 0.00% 100.00% +system.ruby.ST.miss_latency_hist_coalsr::total 786 system.ruby.IFETCH.latency_hist_seqr::bucket_size 1024 system.ruby.IFETCH.latency_hist_seqr::max_bucket 10239 system.ruby.IFETCH.latency_hist_seqr::samples 1 -system.ruby.IFETCH.latency_hist_seqr::mean 5156 -system.ruby.IFETCH.latency_hist_seqr::gmean 5156.000000 +system.ruby.IFETCH.latency_hist_seqr::mean 5129 +system.ruby.IFETCH.latency_hist_seqr::gmean 5129 system.ruby.IFETCH.latency_hist_seqr::stdev nan system.ruby.IFETCH.latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.latency_hist_seqr::total 1 system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 1024 system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 10239 system.ruby.IFETCH.hit_latency_hist_seqr::samples 1 -system.ruby.IFETCH.hit_latency_hist_seqr::mean 5156 -system.ruby.IFETCH.hit_latency_hist_seqr::gmean 5156.000000 +system.ruby.IFETCH.hit_latency_hist_seqr::mean 5129 +system.ruby.IFETCH.hit_latency_hist_seqr::gmean 5129 system.ruby.IFETCH.hit_latency_hist_seqr::stdev nan system.ruby.IFETCH.hit_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.hit_latency_hist_seqr::total 1 system.ruby.L1Cache.miss_mach_latency_hist_seqr::bucket_size 512 system.ruby.L1Cache.miss_mach_latency_hist_seqr::max_bucket 5119 system.ruby.L1Cache.miss_mach_latency_hist_seqr::samples 6 -system.ruby.L1Cache.miss_mach_latency_hist_seqr::mean 1019.833333 -system.ruby.L1Cache.miss_mach_latency_hist_seqr::gmean 114.673945 -system.ruby.L1Cache.miss_mach_latency_hist_seqr::stdev 1281.644790 -system.ruby.L1Cache.miss_mach_latency_hist_seqr | 3 50.00% 50.00% | 1 16.67% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 2 33.33% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache.miss_mach_latency_hist_seqr::mean 1017.833333 +system.ruby.L1Cache.miss_mach_latency_hist_seqr::gmean 114.584426 +system.ruby.L1Cache.miss_mach_latency_hist_seqr::stdev 1278.753677 +system.ruby.L1Cache.miss_mach_latency_hist_seqr | 3 50.00% 50.00% | 1 16.67% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 1 16.67% 83.33% | 1 16.67% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.L1Cache.miss_mach_latency_hist_seqr::total 6 system.ruby.Directory.hit_mach_latency_hist_seqr::bucket_size 1024 system.ruby.Directory.hit_mach_latency_hist_seqr::max_bucket 10239 system.ruby.Directory.hit_mach_latency_hist_seqr::samples 42 -system.ruby.Directory.hit_mach_latency_hist_seqr::mean 3684.428571 -system.ruby.Directory.hit_mach_latency_hist_seqr::gmean 2778.454716 -system.ruby.Directory.hit_mach_latency_hist_seqr::stdev 1783.107224 -system.ruby.Directory.hit_mach_latency_hist_seqr | 7 16.67% 16.67% | 3 7.14% 23.81% | 1 2.38% 26.19% | 7 16.67% 42.86% | 18 42.86% 85.71% | 6 14.29% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.hit_mach_latency_hist_seqr::mean 3644.142857 +system.ruby.Directory.hit_mach_latency_hist_seqr::gmean 2737.850881 +system.ruby.Directory.hit_mach_latency_hist_seqr::stdev 1757.652877 +system.ruby.Directory.hit_mach_latency_hist_seqr | 7 16.67% 16.67% | 3 7.14% 23.81% | 1 2.38% 26.19% | 7 16.67% 42.86% | 20 47.62% 90.48% | 4 9.52% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.Directory.hit_mach_latency_hist_seqr::total 42 system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::bucket_size 128 system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::max_bucket 1279 -system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::samples 644 -system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::mean 154.992236 -system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::gmean 124.686138 -system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::stdev 142.628867 -system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr | 516 80.12% 80.12% | 30 4.66% 84.78% | 42 6.52% 91.30% | 26 4.04% 95.34% | 17 2.64% 97.98% | 7 1.09% 99.07% | 4 0.62% 99.69% | 1 0.16% 99.84% | 1 0.16% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::total 644 +system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::samples 624 +system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::mean 148.483974 +system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::gmean 122.381501 +system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::stdev 128.958613 +system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr | 502 80.45% 80.45% | 36 5.77% 86.22% | 40 6.41% 92.63% | 24 3.85% 96.47% | 12 1.92% 98.40% | 6 0.96% 99.36% | 3 0.48% 99.84% | 1 0.16% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache_wCC.miss_mach_latency_hist_coalsr::total 624 system.ruby.TCP.miss_mach_latency_hist_coalsr::bucket_size 1 system.ruby.TCP.miss_mach_latency_hist_coalsr::max_bucket 9 -system.ruby.TCP.miss_mach_latency_hist_coalsr::samples 64 -system.ruby.TCP.miss_mach_latency_hist_coalsr::mean 1.109375 -system.ruby.TCP.miss_mach_latency_hist_coalsr::gmean 1.055645 -system.ruby.TCP.miss_mach_latency_hist_coalsr::stdev 0.537991 -system.ruby.TCP.miss_mach_latency_hist_coalsr | 0 0.00% 0.00% | 61 95.31% 95.31% | 1 1.56% 96.88% | 0 0.00% 96.88% | 2 3.12% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.TCP.miss_mach_latency_hist_coalsr::total 64 +system.ruby.TCP.miss_mach_latency_hist_coalsr::samples 71 +system.ruby.TCP.miss_mach_latency_hist_coalsr::mean 1.126761 +system.ruby.TCP.miss_mach_latency_hist_coalsr::gmean 1.060325 +system.ruby.TCP.miss_mach_latency_hist_coalsr::stdev 0.607796 +system.ruby.TCP.miss_mach_latency_hist_coalsr | 0 0.00% 0.00% | 68 95.77% 95.77% | 0 0.00% 95.77% | 0 0.00% 95.77% | 3 4.23% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.TCP.miss_mach_latency_hist_coalsr::total 71 system.ruby.TCCdir.miss_mach_latency_hist_coalsr::bucket_size 128 system.ruby.TCCdir.miss_mach_latency_hist_coalsr::max_bucket 1279 -system.ruby.TCCdir.miss_mach_latency_hist_coalsr::samples 164 -system.ruby.TCCdir.miss_mach_latency_hist_coalsr::mean 571.804878 -system.ruby.TCCdir.miss_mach_latency_hist_coalsr::gmean 508.667381 -system.ruby.TCCdir.miss_mach_latency_hist_coalsr::stdev 267.247131 -system.ruby.TCCdir.miss_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 68 41.46% 41.46% | 13 7.93% 49.39% | 16 9.76% 59.15% | 13 7.93% 67.07% | 29 17.68% 84.76% | 22 13.41% 98.17% | 3 1.83% 100.00% | 0 0.00% 100.00% -system.ruby.TCCdir.miss_mach_latency_hist_coalsr::total 164 +system.ruby.TCCdir.miss_mach_latency_hist_coalsr::samples 163 +system.ruby.TCCdir.miss_mach_latency_hist_coalsr::mean 564.687117 +system.ruby.TCCdir.miss_mach_latency_hist_coalsr::gmean 498.870659 +system.ruby.TCCdir.miss_mach_latency_hist_coalsr::stdev 272.472640 +system.ruby.TCCdir.miss_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 71 43.56% 43.56% | 13 7.98% 51.53% | 12 7.36% 58.90% | 13 7.98% 66.87% | 29 17.79% 84.66% | 22 13.50% 98.16% | 3 1.84% 100.00% | 0 0.00% 100.00% +system.ruby.TCCdir.miss_mach_latency_hist_coalsr::total 163 system.ruby.LD.Directory.hit_type_mach_latency_hist_seqr::bucket_size 1024 system.ruby.LD.Directory.hit_type_mach_latency_hist_seqr::max_bucket 10239 system.ruby.LD.Directory.hit_type_mach_latency_hist_seqr::samples 1 -system.ruby.LD.Directory.hit_type_mach_latency_hist_seqr::mean 5324 -system.ruby.LD.Directory.hit_type_mach_latency_hist_seqr::gmean 5324.000000 +system.ruby.LD.Directory.hit_type_mach_latency_hist_seqr::mean 5256 +system.ruby.LD.Directory.hit_type_mach_latency_hist_seqr::gmean 5256.000000 system.ruby.LD.Directory.hit_type_mach_latency_hist_seqr::stdev nan system.ruby.LD.Directory.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.Directory.hit_type_mach_latency_hist_seqr::total 1 -system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::bucket_size 128 -system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::max_bucket 1279 +system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::bucket_size 64 +system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::max_bucket 639 system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::samples 62 -system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::mean 107.322581 -system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::gmean 101.146340 -system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::stdev 70.212972 -system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr | 59 95.16% 95.16% | 2 3.23% 98.39% | 0 0.00% 98.39% | 0 0.00% 98.39% | 0 0.00% 98.39% | 1 1.61% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::mean 104.322581 +system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::gmean 100.218451 +system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::stdev 51.260433 +system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr | 0 0.00% 0.00% | 60 96.77% 96.77% | 1 1.61% 98.39% | 0 0.00% 98.39% | 0 0.00% 98.39% | 0 0.00% 98.39% | 0 0.00% 98.39% | 1 1.61% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::total 62 system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::bucket_size 1 system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::max_bucket 9 -system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::samples 4 -system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::mean 1 -system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::gmean 1 -system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr | 0 0.00% 0.00% | 4 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::total 4 -system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::bucket_size 64 -system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::max_bucket 639 +system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::samples 7 +system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::mean 1.428571 +system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::gmean 1.219014 +system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::stdev 1.133893 +system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr | 0 0.00% 0.00% | 6 85.71% 85.71% | 0 0.00% 85.71% | 0 0.00% 85.71% | 1 14.29% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.TCP.miss_type_mach_latency_hist_coalsr::total 7 +system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::bucket_size 32 +system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::max_bucket 319 system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::samples 3 -system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::mean 340.333333 -system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::gmean 328.169813 -system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::stdev 116.791838 -system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 2 66.67% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 1 33.33% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::mean 274.333333 +system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::gmean 273.844265 +system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::stdev 20.256686 +system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 2 66.67% 66.67% | 1 33.33% 100.00% system.ruby.LD.TCCdir.miss_type_mach_latency_hist_coalsr::total 3 system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::bucket_size 512 system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::max_bucket 5119 system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::samples 6 -system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::mean 1019.833333 -system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::gmean 114.673945 -system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::stdev 1281.644790 -system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr | 3 50.00% 50.00% | 1 16.67% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 2 33.33% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::mean 1017.833333 +system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::gmean 114.584426 +system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::stdev 1278.753677 +system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr | 3 50.00% 50.00% | 1 16.67% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 1 16.67% 83.33% | 1 16.67% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ST.L1Cache.miss_type_mach_latency_hist_seqr::total 6 system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::bucket_size 1024 system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::max_bucket 10239 system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::samples 40 -system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::mean 3606.650000 -system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::gmean 2691.718970 -system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::stdev 1792.166924 -system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr | 7 17.50% 17.50% | 3 7.50% 25.00% | 1 2.50% 27.50% | 7 17.50% 45.00% | 18 45.00% 90.00% | 4 10.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::mean 3566.725000 +system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::gmean 2651.630943 +system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::stdev 1765.919997 +system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr | 7 17.50% 17.50% | 3 7.50% 25.00% | 1 2.50% 27.50% | 7 17.50% 45.00% | 20 50.00% 95.00% | 2 5.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ST.Directory.hit_type_mach_latency_hist_seqr::total 40 system.ruby.ST.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::bucket_size 128 system.ruby.ST.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::max_bucket 1279 -system.ruby.ST.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::samples 582 -system.ruby.ST.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::mean 160.070447 -system.ruby.ST.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::gmean 127.496503 -system.ruby.ST.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::stdev 147.403962 -system.ruby.ST.L1Cache_wCC.miss_type_mach_latency_hist_coalsr | 457 78.52% 78.52% | 28 4.81% 83.33% | 42 7.22% 90.55% | 26 4.47% 95.02% | 17 2.92% 97.94% | 6 1.03% 98.97% | 4 0.69% 99.66% | 1 0.17% 99.83% | 1 0.17% 100.00% | 0 0.00% 100.00% -system.ruby.ST.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::total 582 +system.ruby.ST.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::samples 562 +system.ruby.ST.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::mean 153.355872 +system.ruby.ST.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::gmean 125.108856 +system.ruby.ST.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::stdev 133.952348 +system.ruby.ST.L1Cache_wCC.miss_type_mach_latency_hist_coalsr | 442 78.65% 78.65% | 35 6.23% 84.88% | 40 7.12% 91.99% | 23 4.09% 96.09% | 12 2.14% 98.22% | 6 1.07% 99.29% | 3 0.53% 99.82% | 1 0.18% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.L1Cache_wCC.miss_type_mach_latency_hist_coalsr::total 562 system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::bucket_size 1 system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::max_bucket 9 -system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::samples 60 -system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::mean 1.116667 -system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::gmean 1.059463 -system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::stdev 0.555151 -system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr | 0 0.00% 0.00% | 57 95.00% 95.00% | 1 1.67% 96.67% | 0 0.00% 96.67% | 2 3.33% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::total 60 +system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::samples 64 +system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::mean 1.093750 +system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::gmean 1.044274 +system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::stdev 0.526104 +system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr | 0 0.00% 0.00% | 62 96.88% 96.88% | 0 0.00% 96.88% | 0 0.00% 96.88% | 2 3.12% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.TCP.miss_type_mach_latency_hist_coalsr::total 64 system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::bucket_size 128 system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::max_bucket 1279 -system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::samples 161 -system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::mean 576.118012 -system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::gmean 512.838367 -system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::stdev 267.518863 -system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 66 40.99% 40.99% | 12 7.45% 48.45% | 16 9.94% 58.39% | 13 8.07% 66.46% | 29 18.01% 84.47% | 22 13.66% 98.14% | 3 1.86% 100.00% | 0 0.00% 100.00% -system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::total 161 +system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::samples 160 +system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::mean 570.131250 +system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::gmean 504.512629 +system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::stdev 272.059675 +system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr | 0 0.00% 0.00% | 0 0.00% 0.00% | 68 42.50% 42.50% | 13 8.12% 50.62% | 12 7.50% 58.12% | 13 8.12% 66.25% | 29 18.12% 84.38% | 22 13.75% 98.12% | 3 1.88% 100.00% | 0 0.00% 100.00% +system.ruby.ST.TCCdir.miss_type_mach_latency_hist_coalsr::total 160 system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::bucket_size 1024 system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::max_bucket 10239 system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::samples 1 -system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::mean 5156 -system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::gmean 5156.000000 +system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::mean 5129 +system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::gmean 5129 system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::stdev nan system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.Directory.hit_type_mach_latency_hist_seqr::total 1 -system.ruby.SQC_Controller.Fetch | 12 44.44% 44.44% | 15 55.56% 100.00% -system.ruby.SQC_Controller.Fetch::total 27 -system.ruby.SQC_Controller.TCC_AckS | 12 44.44% 44.44% | 15 55.56% 100.00% -system.ruby.SQC_Controller.TCC_AckS::total 27 -system.ruby.SQC_Controller.PrbInvData | 10 41.67% 41.67% | 14 58.33% 100.00% -system.ruby.SQC_Controller.PrbInvData::total 24 -system.ruby.SQC_Controller.I.Fetch | 12 44.44% 44.44% | 15 55.56% 100.00% -system.ruby.SQC_Controller.I.Fetch::total 27 -system.ruby.SQC_Controller.S.PrbInvData | 10 41.67% 41.67% | 14 58.33% 100.00% -system.ruby.SQC_Controller.S.PrbInvData::total 24 -system.ruby.SQC_Controller.I_S.TCC_AckS | 12 44.44% 44.44% | 15 55.56% 100.00% -system.ruby.SQC_Controller.I_S.TCC_AckS::total 27 -system.ruby.TCCdir_Controller.RdBlk 174 0.00% 0.00% -system.ruby.TCCdir_Controller.RdBlkM 2638 0.00% 0.00% -system.ruby.TCCdir_Controller.RdBlkS 195 0.00% 0.00% -system.ruby.TCCdir_Controller.CPUPrbResp 811 0.00% 0.00% -system.ruby.TCCdir_Controller.ProbeAcksComplete 751 0.00% 0.00% -system.ruby.TCCdir_Controller.CoreUnblock 829 0.00% 0.00% -system.ruby.TCCdir_Controller.LastCoreUnblock 2 0.00% 0.00% -system.ruby.TCCdir_Controller.NB_AckS 2 0.00% 0.00% -system.ruby.TCCdir_Controller.NB_AckE 2 0.00% 0.00% -system.ruby.TCCdir_Controller.NB_AckM 223 0.00% 0.00% -system.ruby.TCCdir_Controller.PrbInvData 112 0.00% 0.00% -system.ruby.TCCdir_Controller.PrbShrData 4 0.00% 0.00% +system.ruby.SQC_Controller.Fetch | 12 50.00% 50.00% | 12 50.00% 100.00% +system.ruby.SQC_Controller.Fetch::total 24 +system.ruby.SQC_Controller.TCC_AckS | 12 50.00% 50.00% | 12 50.00% 100.00% +system.ruby.SQC_Controller.TCC_AckS::total 24 +system.ruby.SQC_Controller.PrbInvData | 11 50.00% 50.00% | 11 50.00% 100.00% +system.ruby.SQC_Controller.PrbInvData::total 22 +system.ruby.SQC_Controller.I.Fetch | 12 50.00% 50.00% | 12 50.00% 100.00% +system.ruby.SQC_Controller.I.Fetch::total 24 +system.ruby.SQC_Controller.S.PrbInvData | 11 50.00% 50.00% | 11 50.00% 100.00% +system.ruby.SQC_Controller.S.PrbInvData::total 22 +system.ruby.SQC_Controller.I_S.TCC_AckS | 12 50.00% 50.00% | 12 50.00% 100.00% +system.ruby.SQC_Controller.I_S.TCC_AckS::total 24 +system.ruby.TCCdir_Controller.RdBlk 115 0.00% 0.00% +system.ruby.TCCdir_Controller.RdBlkM 2448 0.00% 0.00% +system.ruby.TCCdir_Controller.RdBlkS 103 0.00% 0.00% +system.ruby.TCCdir_Controller.CPUPrbResp 785 0.00% 0.00% +system.ruby.TCCdir_Controller.ProbeAcksComplete 730 0.00% 0.00% +system.ruby.TCCdir_Controller.CoreUnblock 807 0.00% 0.00% +system.ruby.TCCdir_Controller.LastCoreUnblock 3 0.00% 0.00% +system.ruby.TCCdir_Controller.NB_AckS 1 0.00% 0.00% +system.ruby.TCCdir_Controller.NB_AckE 3 0.00% 0.00% +system.ruby.TCCdir_Controller.NB_AckM 212 0.00% 0.00% +system.ruby.TCCdir_Controller.PrbInvData 119 0.00% 0.00% +system.ruby.TCCdir_Controller.PrbShrData 6 0.00% 0.00% system.ruby.TCCdir_Controller.I.RdBlk 3 0.00% 0.00% -system.ruby.TCCdir_Controller.I.RdBlkM 156 0.00% 0.00% +system.ruby.TCCdir_Controller.I.RdBlkM 154 0.00% 0.00% system.ruby.TCCdir_Controller.I.RdBlkS 1 0.00% 0.00% system.ruby.TCCdir_Controller.I.PrbInvData 9 0.00% 0.00% -system.ruby.TCCdir_Controller.S.RdBlkM 2 0.00% 0.00% -system.ruby.TCCdir_Controller.S.RdBlkS 1 0.00% 0.00% +system.ruby.TCCdir_Controller.S.RdBlkM 1 0.00% 0.00% system.ruby.TCCdir_Controller.E.RdBlkM 1 0.00% 0.00% -system.ruby.TCCdir_Controller.O.RdBlk 1 0.00% 0.00% -system.ruby.TCCdir_Controller.O.RdBlkM 70 0.00% 0.00% -system.ruby.TCCdir_Controller.O.PrbInvData 6 0.00% 0.00% +system.ruby.TCCdir_Controller.E.RdBlkS 1 0.00% 0.00% +system.ruby.TCCdir_Controller.O.RdBlk 2 0.00% 0.00% +system.ruby.TCCdir_Controller.O.RdBlkM 61 0.00% 0.00% +system.ruby.TCCdir_Controller.O.RdBlkS 1 0.00% 0.00% +system.ruby.TCCdir_Controller.O.PrbInvData 4 0.00% 0.00% +system.ruby.TCCdir_Controller.O.PrbShrData 1 0.00% 0.00% system.ruby.TCCdir_Controller.M.RdBlk 61 0.00% 0.00% -system.ruby.TCCdir_Controller.M.RdBlkM 521 0.00% 0.00% -system.ruby.TCCdir_Controller.M.RdBlkS 25 0.00% 0.00% -system.ruby.TCCdir_Controller.M.PrbInvData 59 0.00% 0.00% +system.ruby.TCCdir_Controller.M.RdBlkM 512 0.00% 0.00% +system.ruby.TCCdir_Controller.M.RdBlkS 20 0.00% 0.00% +system.ruby.TCCdir_Controller.M.PrbInvData 62 0.00% 0.00% system.ruby.TCCdir_Controller.M.PrbShrData 4 0.00% 0.00% -system.ruby.TCCdir_Controller.CP_I.RdBlk 9 0.00% 0.00% -system.ruby.TCCdir_Controller.CP_I.RdBlkM 15 0.00% 0.00% -system.ruby.TCCdir_Controller.CP_I.RdBlkS 7 0.00% 0.00% -system.ruby.TCCdir_Controller.CP_I.CPUPrbResp 71 0.00% 0.00% -system.ruby.TCCdir_Controller.CP_I.ProbeAcksComplete 65 0.00% 0.00% +system.ruby.TCCdir_Controller.CP_I.RdBlkM 17 0.00% 0.00% +system.ruby.TCCdir_Controller.CP_I.CPUPrbResp 70 0.00% 0.00% +system.ruby.TCCdir_Controller.CP_I.ProbeAcksComplete 66 0.00% 0.00% system.ruby.TCCdir_Controller.CP_O.RdBlkM 4 0.00% 0.00% -system.ruby.TCCdir_Controller.CP_O.CPUPrbResp 4 0.00% 0.00% -system.ruby.TCCdir_Controller.CP_O.ProbeAcksComplete 4 0.00% 0.00% +system.ruby.TCCdir_Controller.CP_O.CPUPrbResp 6 0.00% 0.00% +system.ruby.TCCdir_Controller.CP_O.ProbeAcksComplete 5 0.00% 0.00% +system.ruby.TCCdir_Controller.CP_OM.RdBlkM 14 0.00% 0.00% +system.ruby.TCCdir_Controller.CP_OM.CPUPrbResp 1 0.00% 0.00% +system.ruby.TCCdir_Controller.CP_OM.ProbeAcksComplete 1 0.00% 0.00% system.ruby.TCCdir_Controller.CP_IOM.RdBlkM 5 0.00% 0.00% system.ruby.TCCdir_Controller.CP_IOM.CPUPrbResp 2 0.00% 0.00% system.ruby.TCCdir_Controller.CP_IOM.ProbeAcksComplete 2 0.00% 0.00% -system.ruby.TCCdir_Controller.I_M.RdBlkM 897 0.00% 0.00% -system.ruby.TCCdir_Controller.I_M.RdBlkS 30 0.00% 0.00% -system.ruby.TCCdir_Controller.I_M.NB_AckM 156 0.00% 0.00% +system.ruby.TCCdir_Controller.I_M.RdBlk 26 0.00% 0.00% +system.ruby.TCCdir_Controller.I_M.RdBlkM 960 0.00% 0.00% +system.ruby.TCCdir_Controller.I_M.RdBlkS 3 0.00% 0.00% +system.ruby.TCCdir_Controller.I_M.NB_AckM 154 0.00% 0.00% system.ruby.TCCdir_Controller.I_M.PrbInvData 1 0.00% 0.00% -system.ruby.TCCdir_Controller.I_ES.RdBlkM 24 0.00% 0.00% -system.ruby.TCCdir_Controller.I_ES.RdBlkS 34 0.00% 0.00% -system.ruby.TCCdir_Controller.I_ES.NB_AckS 1 0.00% 0.00% -system.ruby.TCCdir_Controller.I_ES.NB_AckE 2 0.00% 0.00% -system.ruby.TCCdir_Controller.I_S.RdBlkM 11 0.00% 0.00% +system.ruby.TCCdir_Controller.I_ES.NB_AckE 3 0.00% 0.00% system.ruby.TCCdir_Controller.I_S.NB_AckS 1 0.00% 0.00% -system.ruby.TCCdir_Controller.BBS_S.RdBlkM 5 0.00% 0.00% -system.ruby.TCCdir_Controller.BBS_S.CPUPrbResp 1 0.00% 0.00% -system.ruby.TCCdir_Controller.BBS_S.ProbeAcksComplete 1 0.00% 0.00% -system.ruby.TCCdir_Controller.BBO_O.CPUPrbResp 1 0.00% 0.00% -system.ruby.TCCdir_Controller.BBO_O.ProbeAcksComplete 1 0.00% 0.00% -system.ruby.TCCdir_Controller.BBM_M.RdBlk 11 0.00% 0.00% -system.ruby.TCCdir_Controller.BBM_M.RdBlkM 104 0.00% 0.00% -system.ruby.TCCdir_Controller.BBM_M.RdBlkS 12 0.00% 0.00% -system.ruby.TCCdir_Controller.BBM_M.CPUPrbResp 520 0.00% 0.00% -system.ruby.TCCdir_Controller.BBM_M.ProbeAcksComplete 520 0.00% 0.00% -system.ruby.TCCdir_Controller.BBM_M.PrbInvData 14 0.00% 0.00% -system.ruby.TCCdir_Controller.BBM_O.RdBlkM 13 0.00% 0.00% -system.ruby.TCCdir_Controller.BBM_O.CPUPrbResp 86 0.00% 0.00% -system.ruby.TCCdir_Controller.BBM_O.ProbeAcksComplete 86 0.00% 0.00% -system.ruby.TCCdir_Controller.BB_M.RdBlk 20 0.00% 0.00% -system.ruby.TCCdir_Controller.BB_M.RdBlkM 181 0.00% 0.00% -system.ruby.TCCdir_Controller.BB_M.RdBlkS 15 0.00% 0.00% -system.ruby.TCCdir_Controller.BB_M.CoreUnblock 518 0.00% 0.00% -system.ruby.TCCdir_Controller.BB_M.PrbInvData 19 0.00% 0.00% -system.ruby.TCCdir_Controller.BB_O.RdBlkM 35 0.00% 0.00% -system.ruby.TCCdir_Controller.BB_O.CoreUnblock 84 0.00% 0.00% +system.ruby.TCCdir_Controller.BBO_O.RdBlkM 5 0.00% 0.00% +system.ruby.TCCdir_Controller.BBO_O.RdBlkS 1 0.00% 0.00% +system.ruby.TCCdir_Controller.BBO_O.CPUPrbResp 3 0.00% 0.00% +system.ruby.TCCdir_Controller.BBO_O.ProbeAcksComplete 3 0.00% 0.00% +system.ruby.TCCdir_Controller.BBM_M.RdBlk 6 0.00% 0.00% +system.ruby.TCCdir_Controller.BBM_M.RdBlkM 94 0.00% 0.00% +system.ruby.TCCdir_Controller.BBM_M.RdBlkS 5 0.00% 0.00% +system.ruby.TCCdir_Controller.BBM_M.CPUPrbResp 510 0.00% 0.00% +system.ruby.TCCdir_Controller.BBM_M.ProbeAcksComplete 510 0.00% 0.00% +system.ruby.TCCdir_Controller.BBM_M.PrbInvData 15 0.00% 0.00% +system.ruby.TCCdir_Controller.BBM_O.RdBlkM 6 0.00% 0.00% +system.ruby.TCCdir_Controller.BBM_O.RdBlkS 5 0.00% 0.00% +system.ruby.TCCdir_Controller.BBM_O.CPUPrbResp 81 0.00% 0.00% +system.ruby.TCCdir_Controller.BBM_O.ProbeAcksComplete 81 0.00% 0.00% +system.ruby.TCCdir_Controller.BB_M.RdBlk 13 0.00% 0.00% +system.ruby.TCCdir_Controller.BB_M.RdBlkM 176 0.00% 0.00% +system.ruby.TCCdir_Controller.BB_M.RdBlkS 5 0.00% 0.00% +system.ruby.TCCdir_Controller.BB_M.CoreUnblock 509 0.00% 0.00% +system.ruby.TCCdir_Controller.BB_M.PrbInvData 24 0.00% 0.00% +system.ruby.TCCdir_Controller.BB_O.RdBlkM 26 0.00% 0.00% +system.ruby.TCCdir_Controller.BB_O.RdBlkS 5 0.00% 0.00% +system.ruby.TCCdir_Controller.BB_O.CoreUnblock 81 0.00% 0.00% system.ruby.TCCdir_Controller.BB_O.PrbInvData 2 0.00% 0.00% -system.ruby.TCCdir_Controller.BB_OO.LastCoreUnblock 1 0.00% 0.00% -system.ruby.TCCdir_Controller.BB_S.RdBlkM 9 0.00% 0.00% -system.ruby.TCCdir_Controller.BB_S.LastCoreUnblock 1 0.00% 0.00% -system.ruby.TCCdir_Controller.BBS_M.RdBlk 9 0.00% 0.00% -system.ruby.TCCdir_Controller.BBS_M.RdBlkM 18 0.00% 0.00% -system.ruby.TCCdir_Controller.BBS_M.CPUPrbResp 4 0.00% 0.00% -system.ruby.TCCdir_Controller.BBS_M.ProbeAcksComplete 3 0.00% 0.00% -system.ruby.TCCdir_Controller.BBO_M.RdBlkM 20 0.00% 0.00% -system.ruby.TCCdir_Controller.BBO_M.CPUPrbResp 122 0.00% 0.00% -system.ruby.TCCdir_Controller.BBO_M.ProbeAcksComplete 69 0.00% 0.00% -system.ruby.TCCdir_Controller.S_M.RdBlk 28 0.00% 0.00% -system.ruby.TCCdir_Controller.S_M.RdBlkM 69 0.00% 0.00% -system.ruby.TCCdir_Controller.S_M.NB_AckM 3 0.00% 0.00% -system.ruby.TCCdir_Controller.O_M.RdBlk 20 0.00% 0.00% -system.ruby.TCCdir_Controller.O_M.RdBlkM 249 0.00% 0.00% -system.ruby.TCCdir_Controller.O_M.RdBlkS 51 0.00% 0.00% -system.ruby.TCCdir_Controller.O_M.NB_AckM 64 0.00% 0.00% +system.ruby.TCCdir_Controller.BB_OO.RdBlkM 14 0.00% 0.00% +system.ruby.TCCdir_Controller.BB_OO.CoreUnblock 1 0.00% 0.00% +system.ruby.TCCdir_Controller.BB_OO.LastCoreUnblock 3 0.00% 0.00% +system.ruby.TCCdir_Controller.BBS_M.CPUPrbResp 2 0.00% 0.00% +system.ruby.TCCdir_Controller.BBS_M.ProbeAcksComplete 2 0.00% 0.00% +system.ruby.TCCdir_Controller.BBO_M.RdBlkM 4 0.00% 0.00% +system.ruby.TCCdir_Controller.BBO_M.CPUPrbResp 110 0.00% 0.00% +system.ruby.TCCdir_Controller.BBO_M.ProbeAcksComplete 60 0.00% 0.00% +system.ruby.TCCdir_Controller.S_M.NB_AckM 2 0.00% 0.00% +system.ruby.TCCdir_Controller.O_M.RdBlkM 198 0.00% 0.00% +system.ruby.TCCdir_Controller.O_M.RdBlkS 48 0.00% 0.00% +system.ruby.TCCdir_Controller.O_M.NB_AckM 56 0.00% 0.00% system.ruby.TCCdir_Controller.O_M.PrbInvData 2 0.00% 0.00% -system.ruby.TCCdir_Controller.BBB_S.RdBlk 3 0.00% 0.00% -system.ruby.TCCdir_Controller.BBB_S.RdBlkM 23 0.00% 0.00% -system.ruby.TCCdir_Controller.BBB_S.RdBlkS 5 0.00% 0.00% -system.ruby.TCCdir_Controller.BBB_S.CoreUnblock 2 0.00% 0.00% -system.ruby.TCCdir_Controller.BBB_M.RdBlk 9 0.00% 0.00% -system.ruby.TCCdir_Controller.BBB_M.RdBlkM 206 0.00% 0.00% -system.ruby.TCCdir_Controller.BBB_M.RdBlkS 14 0.00% 0.00% -system.ruby.TCCdir_Controller.BBB_M.CoreUnblock 223 0.00% 0.00% -system.ruby.TCCdir_Controller.BBB_E.CoreUnblock 2 0.00% 0.00% -system.ruby.TCP_Controller.Load | 5 7.04% 7.04% | 6 8.45% 15.49% | 10 14.08% 29.58% | 13 18.31% 47.89% | 6 8.45% 56.34% | 6 8.45% 64.79% | 13 18.31% 83.10% | 12 16.90% 100.00% -system.ruby.TCP_Controller.Load::total 71 -system.ruby.TCP_Controller.Store | 109 13.39% 13.39% | 104 12.78% 26.17% | 98 12.04% 38.21% | 93 11.43% 49.63% | 109 13.39% 63.02% | 102 12.53% 75.55% | 113 13.88% 89.43% | 86 10.57% 100.00% -system.ruby.TCP_Controller.Store::total 814 -system.ruby.TCP_Controller.TCC_AckS | 5 7.94% 7.94% | 5 7.94% 15.87% | 9 14.29% 30.16% | 13 20.63% 50.79% | 4 6.35% 57.14% | 6 9.52% 66.67% | 11 17.46% 84.13% | 10 15.87% 100.00% -system.ruby.TCP_Controller.TCC_AckS::total 63 -system.ruby.TCP_Controller.TCC_AckE | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 50.00% 50.00% | 1 50.00% 100.00% -system.ruby.TCP_Controller.TCC_AckE::total 2 -system.ruby.TCP_Controller.TCC_AckM | 100 13.46% 13.46% | 94 12.65% 26.11% | 90 12.11% 38.22% | 81 10.90% 49.13% | 102 13.73% 62.85% | 92 12.38% 75.24% | 105 14.13% 89.37% | 79 10.63% 100.00% -system.ruby.TCP_Controller.TCC_AckM::total 743 -system.ruby.TCP_Controller.PrbInvData | 88 12.61% 12.61% | 87 12.46% 25.07% | 88 12.61% 37.68% | 79 11.32% 49.00% | 90 12.89% 61.89% | 86 12.32% 74.21% | 101 14.47% 88.68% | 79 11.32% 100.00% -system.ruby.TCP_Controller.PrbInvData::total 698 -system.ruby.TCP_Controller.PrbShrData | 14 15.22% 15.22% | 9 9.78% 25.00% | 17 18.48% 43.48% | 7 7.61% 51.09% | 14 15.22% 66.30% | 10 10.87% 77.17% | 12 13.04% 90.22% | 9 9.78% 100.00% +system.ruby.TCCdir_Controller.O_M.PrbShrData 1 0.00% 0.00% +system.ruby.TCCdir_Controller.BBB_S.CoreUnblock 1 0.00% 0.00% +system.ruby.TCCdir_Controller.BBB_M.RdBlk 4 0.00% 0.00% +system.ruby.TCCdir_Controller.BBB_M.RdBlkM 196 0.00% 0.00% +system.ruby.TCCdir_Controller.BBB_M.RdBlkS 8 0.00% 0.00% +system.ruby.TCCdir_Controller.BBB_M.CoreUnblock 212 0.00% 0.00% +system.ruby.TCCdir_Controller.BBB_E.CoreUnblock 3 0.00% 0.00% +system.ruby.TCP_Controller.Load | 10 13.70% 13.70% | 10 13.70% 27.40% | 11 15.07% 42.47% | 12 16.44% 58.90% | 6 8.22% 67.12% | 3 4.11% 71.23% | 10 13.70% 84.93% | 11 15.07% 100.00% +system.ruby.TCP_Controller.Load::total 73 +system.ruby.TCP_Controller.Store | 106 13.27% 13.27% | 102 12.77% 26.03% | 97 12.14% 38.17% | 86 10.76% 48.94% | 107 13.39% 62.33% | 98 12.27% 74.59% | 111 13.89% 88.49% | 92 11.51% 100.00% +system.ruby.TCP_Controller.Store::total 799 +system.ruby.TCP_Controller.TCC_AckS | 9 14.52% 14.52% | 8 12.90% 27.42% | 8 12.90% 40.32% | 12 19.35% 59.68% | 5 8.06% 67.74% | 3 4.84% 72.58% | 8 12.90% 85.48% | 9 14.52% 100.00% +system.ruby.TCP_Controller.TCC_AckS::total 62 +system.ruby.TCP_Controller.TCC_AckE | 1 33.33% 33.33% | 0 0.00% 33.33% | 1 33.33% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 1 33.33% 100.00% | 0 0.00% 100.00% +system.ruby.TCP_Controller.TCC_AckE::total 3 +system.ruby.TCP_Controller.TCC_AckM | 93 12.88% 12.88% | 89 12.33% 25.21% | 87 12.05% 37.26% | 76 10.53% 47.78% | 98 13.57% 61.36% | 89 12.33% 73.68% | 106 14.68% 88.37% | 84 11.63% 100.00% +system.ruby.TCP_Controller.TCC_AckM::total 722 +system.ruby.TCP_Controller.PrbInvData | 84 12.44% 12.44% | 87 12.89% 25.33% | 83 12.30% 37.63% | 78 11.56% 49.19% | 89 13.19% 62.37% | 79 11.70% 74.07% | 97 14.37% 88.44% | 78 11.56% 100.00% +system.ruby.TCP_Controller.PrbInvData::total 675 +system.ruby.TCP_Controller.PrbShrData | 16 17.39% 17.39% | 10 10.87% 28.26% | 9 9.78% 38.04% | 8 8.70% 46.74% | 15 16.30% 63.04% | 9 9.78% 72.83% | 14 15.22% 88.04% | 11 11.96% 100.00% system.ruby.TCP_Controller.PrbShrData::total 92 -system.ruby.TCP_Controller.I.Load | 5 7.46% 7.46% | 5 7.46% 14.93% | 9 13.43% 28.36% | 13 19.40% 47.76% | 6 8.96% 56.72% | 6 8.96% 65.67% | 12 17.91% 83.58% | 11 16.42% 100.00% -system.ruby.TCP_Controller.I.Load::total 67 -system.ruby.TCP_Controller.I.Store | 98 13.26% 13.26% | 95 12.86% 26.12% | 89 12.04% 38.16% | 82 11.10% 49.26% | 99 13.40% 62.65% | 93 12.58% 75.24% | 105 14.21% 89.45% | 78 10.55% 100.00% -system.ruby.TCP_Controller.I.Store::total 739 +system.ruby.TCP_Controller.I.Load | 10 15.15% 15.15% | 9 13.64% 28.79% | 9 13.64% 42.42% | 12 18.18% 60.61% | 5 7.58% 68.18% | 3 4.55% 72.73% | 9 13.64% 86.36% | 9 13.64% 100.00% +system.ruby.TCP_Controller.I.Load::total 66 +system.ruby.TCP_Controller.I.Store | 97 13.42% 13.42% | 91 12.59% 26.00% | 87 12.03% 38.04% | 79 10.93% 48.96% | 92 12.72% 61.69% | 89 12.31% 74.00% | 104 14.38% 88.38% | 84 11.62% 100.00% +system.ruby.TCP_Controller.I.Store::total 723 system.ruby.TCP_Controller.I.PrbInvData | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 50.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.TCP_Controller.I.PrbInvData::total 2 -system.ruby.TCP_Controller.S.Store | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 20.00% 20.00% | 1 20.00% 40.00% | 0 0.00% 40.00% | 2 40.00% 80.00% | 1 20.00% 100.00% -system.ruby.TCP_Controller.S.Store::total 5 -system.ruby.TCP_Controller.S.PrbInvData | 4 8.33% 8.33% | 4 8.33% 16.67% | 8 16.67% 33.33% | 9 18.75% 52.08% | 3 6.25% 58.33% | 4 8.33% 66.67% | 8 16.67% 83.33% | 8 16.67% 100.00% -system.ruby.TCP_Controller.S.PrbInvData::total 48 -system.ruby.TCP_Controller.S.PrbShrData | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.TCP_Controller.S.Store | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 33.33% 33.33% | 0 0.00% 33.33% | 2 66.67% 100.00% | 0 0.00% 100.00% +system.ruby.TCP_Controller.S.Store::total 3 +system.ruby.TCP_Controller.S.PrbInvData | 6 14.29% 14.29% | 7 16.67% 30.95% | 7 16.67% 47.62% | 7 16.67% 64.29% | 2 4.76% 69.05% | 1 2.38% 71.43% | 5 11.90% 83.33% | 7 16.67% 100.00% +system.ruby.TCP_Controller.S.PrbInvData::total 42 +system.ruby.TCP_Controller.S.PrbShrData | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.TCP_Controller.S.PrbShrData::total 1 system.ruby.TCP_Controller.E.PrbInvData | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% system.ruby.TCP_Controller.E.PrbInvData::total 1 -system.ruby.TCP_Controller.O.Store | 2 20.00% 20.00% | 0 0.00% 20.00% | 2 20.00% 40.00% | 0 0.00% 40.00% | 3 30.00% 70.00% | 1 10.00% 80.00% | 1 10.00% 90.00% | 1 10.00% 100.00% -system.ruby.TCP_Controller.O.Store::total 10 -system.ruby.TCP_Controller.O.PrbInvData | 9 13.64% 13.64% | 7 10.61% 24.24% | 12 18.18% 42.42% | 7 10.61% 53.03% | 10 15.15% 68.18% | 5 7.58% 75.76% | 10 15.15% 90.91% | 6 9.09% 100.00% -system.ruby.TCP_Controller.O.PrbInvData::total 66 -system.ruby.TCP_Controller.O.PrbShrData | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.TCP_Controller.O.PrbShrData::total 1 -system.ruby.TCP_Controller.M.Load | 0 0.00% 0.00% | 1 25.00% 25.00% | 1 25.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 1 25.00% 75.00% | 1 25.00% 100.00% -system.ruby.TCP_Controller.M.Load::total 4 -system.ruby.TCP_Controller.M.Store | 9 15.00% 15.00% | 9 15.00% 30.00% | 7 11.67% 41.67% | 10 16.67% 58.33% | 6 10.00% 68.33% | 8 13.33% 81.67% | 5 8.33% 90.00% | 6 10.00% 100.00% -system.ruby.TCP_Controller.M.Store::total 60 -system.ruby.TCP_Controller.M.PrbInvData | 75 12.93% 12.93% | 76 13.10% 26.03% | 67 11.55% 37.59% | 62 10.69% 48.28% | 76 13.10% 61.38% | 77 13.28% 74.66% | 82 14.14% 88.79% | 65 11.21% 100.00% -system.ruby.TCP_Controller.M.PrbInvData::total 580 -system.ruby.TCP_Controller.M.PrbShrData | 14 15.56% 15.56% | 8 8.89% 24.44% | 16 17.78% 42.22% | 7 7.78% 50.00% | 14 15.56% 65.56% | 10 11.11% 76.67% | 12 13.33% 90.00% | 9 10.00% 100.00% -system.ruby.TCP_Controller.M.PrbShrData::total 90 -system.ruby.TCP_Controller.I_M.TCC_AckM | 98 13.42% 13.42% | 94 12.88% 26.30% | 89 12.19% 38.49% | 80 10.96% 49.45% | 98 13.42% 62.88% | 91 12.47% 75.34% | 103 14.11% 89.45% | 77 10.55% 100.00% -system.ruby.TCP_Controller.I_M.TCC_AckM::total 730 -system.ruby.TCP_Controller.I_ES.TCC_AckS | 5 7.94% 7.94% | 5 7.94% 15.87% | 9 14.29% 30.16% | 13 20.63% 50.79% | 4 6.35% 57.14% | 6 9.52% 66.67% | 11 17.46% 84.13% | 10 15.87% 100.00% -system.ruby.TCP_Controller.I_ES.TCC_AckS::total 63 -system.ruby.TCP_Controller.I_ES.TCC_AckE | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 50.00% 50.00% | 1 50.00% 100.00% -system.ruby.TCP_Controller.I_ES.TCC_AckE::total 2 -system.ruby.TCP_Controller.S_M.TCC_AckM | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 25.00% 25.00% | 1 25.00% 50.00% | 0 0.00% 50.00% | 1 25.00% 75.00% | 1 25.00% 100.00% -system.ruby.TCP_Controller.S_M.TCC_AckM::total 4 -system.ruby.TCP_Controller.O_M.TCC_AckM | 2 22.22% 22.22% | 0 0.00% 22.22% | 1 11.11% 33.33% | 0 0.00% 33.33% | 3 33.33% 66.67% | 1 11.11% 77.78% | 1 11.11% 88.89% | 1 11.11% 100.00% -system.ruby.TCP_Controller.O_M.TCC_AckM::total 9 -system.ruby.TCP_Controller.O_M.PrbInvData | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.TCP_Controller.O_M.PrbInvData::total 1 +system.ruby.TCP_Controller.E.PrbShrData | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.TCP_Controller.E.PrbShrData::total 1 +system.ruby.TCP_Controller.O.Store | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 11.11% 11.11% | 0 0.00% 11.11% | 5 55.56% 66.67% | 1 11.11% 77.78% | 1 11.11% 88.89% | 1 11.11% 100.00% +system.ruby.TCP_Controller.O.Store::total 9 +system.ruby.TCP_Controller.O.PrbInvData | 9 16.07% 16.07% | 7 12.50% 28.57% | 8 14.29% 42.86% | 8 14.29% 57.14% | 7 12.50% 69.64% | 3 5.36% 75.00% | 9 16.07% 91.07% | 5 8.93% 100.00% +system.ruby.TCP_Controller.O.PrbInvData::total 56 +system.ruby.TCP_Controller.O.PrbShrData | 1 33.33% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 0 0.00% 33.33% | 1 33.33% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 1 33.33% 100.00% +system.ruby.TCP_Controller.O.PrbShrData::total 3 +system.ruby.TCP_Controller.M.Load | 0 0.00% 0.00% | 1 14.29% 14.29% | 2 28.57% 42.86% | 0 0.00% 42.86% | 1 14.29% 57.14% | 0 0.00% 57.14% | 1 14.29% 71.43% | 2 28.57% 100.00% +system.ruby.TCP_Controller.M.Load::total 7 +system.ruby.TCP_Controller.M.Store | 9 14.06% 14.06% | 11 17.19% 31.25% | 9 14.06% 45.31% | 7 10.94% 56.25% | 9 14.06% 70.31% | 8 12.50% 82.81% | 4 6.25% 89.06% | 7 10.94% 100.00% +system.ruby.TCP_Controller.M.Store::total 64 +system.ruby.TCP_Controller.M.PrbInvData | 69 12.02% 12.02% | 73 12.72% 24.74% | 68 11.85% 36.59% | 62 10.80% 47.39% | 79 13.76% 61.15% | 75 13.07% 74.22% | 82 14.29% 88.50% | 66 11.50% 100.00% +system.ruby.TCP_Controller.M.PrbInvData::total 574 +system.ruby.TCP_Controller.M.PrbShrData | 14 16.47% 16.47% | 10 11.76% 28.24% | 9 10.59% 38.82% | 8 9.41% 48.24% | 14 16.47% 64.71% | 6 7.06% 71.76% | 14 16.47% 88.24% | 10 11.76% 100.00% +system.ruby.TCP_Controller.M.PrbShrData::total 85 +system.ruby.TCP_Controller.I_M.TCC_AckM | 93 13.06% 13.06% | 89 12.50% 25.56% | 86 12.08% 37.64% | 76 10.67% 48.31% | 92 12.92% 61.24% | 89 12.50% 73.74% | 104 14.61% 88.34% | 83 11.66% 100.00% +system.ruby.TCP_Controller.I_M.TCC_AckM::total 712 +system.ruby.TCP_Controller.I_ES.TCC_AckS | 9 14.52% 14.52% | 8 12.90% 27.42% | 8 12.90% 40.32% | 12 19.35% 59.68% | 5 8.06% 67.74% | 3 4.84% 72.58% | 8 12.90% 85.48% | 9 14.52% 100.00% +system.ruby.TCP_Controller.I_ES.TCC_AckS::total 62 +system.ruby.TCP_Controller.I_ES.TCC_AckE | 1 33.33% 33.33% | 0 0.00% 33.33% | 1 33.33% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 1 33.33% 100.00% | 0 0.00% 100.00% +system.ruby.TCP_Controller.I_ES.TCC_AckE::total 3 +system.ruby.TCP_Controller.S_M.TCC_AckM | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 50.00% 50.00% | 0 0.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% +system.ruby.TCP_Controller.S_M.TCC_AckM::total 2 +system.ruby.TCP_Controller.O_M.TCC_AckM | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 12.50% 12.50% | 0 0.00% 12.50% | 5 62.50% 75.00% | 0 0.00% 75.00% | 1 12.50% 87.50% | 1 12.50% 100.00% +system.ruby.TCP_Controller.O_M.TCC_AckM::total 8 +system.ruby.TCP_Controller.O_M.PrbShrData | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 2 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.TCP_Controller.O_M.PrbShrData::total 2 ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/config.ini b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/config.ini index 6f23123b5..55d4b5c7c 100644 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/config.ini +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/config.ini @@ -14,6 +14,7 @@ children=clk_domain cpu dvfs_handler mem_ctrls ruby sys_port_proxy voltage_domai boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 exit_on_work_items=false init_param=0 @@ -22,11 +23,15 @@ kernel_addr_check=true load_addr_mask=1099511627775 load_offset=0 mem_mode=timing -mem_ranges=0:268435455 +mem_ranges=0:268435455:0:0:0:0 memories=system.mem_ctrls mmap_using_noreserve=false multi_thread=false num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null readfile= symbolfile= thermal_components= @@ -54,8 +59,13 @@ check_flush=false checks_to_complete=100 clk_domain=system.clk_domain deadlock_threshold=50000 +default_p_state=UNDEFINED eventq_index=0 num_cpus=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null system=system wakeup_frequency=10 cpuInstDataPort=system.ruby.l1_cntrl0.sequencer.slave[0] @@ -70,27 +80,27 @@ transition_latency=100000 [system.mem_ctrls] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -102,6 +112,7 @@ burst_length=8 channels=1 clk_domain=system.clk_domain conf_table_reported=true +default_p_state=UNDEFINED device_bus_width=8 device_rowbuffer_size=1024 device_size=536870912 @@ -109,12 +120,17 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 page_policy=open_adaptive -range=0:268435455 +power_model=Null +range=0:268435455:5:19:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10 @@ -136,9 +152,9 @@ tRTW=3 tWR=15 tWTR=8 tXAW=30 -tXP=0 +tXP=6 tXPDLL=0 -tXS=0 +tXS=270 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 @@ -152,12 +168,17 @@ access_backing_store=false all_instructions=false block_size_bytes=64 clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED eventq_index=0 hot_lines=false memory_size_bits=48 num_of_sequencers=1 number_of_virtual_networks=3 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 phys_mem=Null +power_model=Null randomization=true [system.ruby.clk_domain] @@ -174,10 +195,15 @@ children=directory requestToDir responseFromDir responseFromMemory responseToDir buffer_size=0 clk_domain=system.ruby.clk_domain cluster_id=0 +default_p_state=UNDEFINED directory=system.ruby.dir_cntrl0.directory directory_latency=6 eventq_index=0 number_of_TBEs=256 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null recycle_latency=10 requestToDir=system.ruby.dir_cntrl0.requestToDir responseFromDir=system.ruby.dir_cntrl0.responseFromDir @@ -236,6 +262,7 @@ L1Icache=system.ruby.l1_cntrl0.L1Icache buffer_size=0 clk_domain=system.ruby.clk_domain cluster_id=0 +default_p_state=UNDEFINED enable_prefetch=false eventq_index=0 l1_request_latency=2 @@ -244,6 +271,10 @@ l2_select_num_bits=0 mandatoryQueue=system.ruby.l1_cntrl0.mandatoryQueue number_of_TBEs=256 optionalQueue=system.ruby.l1_cntrl0.optionalQueue +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null prefetcher=system.ruby.l1_cntrl0.prefetcher recycle_latency=10 requestFromL1Cache=system.ruby.l1_cntrl0.requestFromL1Cache @@ -372,17 +403,22 @@ coreid=99 dcache=system.ruby.l1_cntrl0.L1Dcache dcache_hit_latency=1 deadlock_threshold=500000 +default_p_state=UNDEFINED eventq_index=0 +garnet_standalone=false icache=system.ruby.l1_cntrl0.L1Icache icache_hit_latency=1 is_cpu_sequencer=true max_outstanding_requests=16 no_retry_on_stall=true +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null ruby_system=system.ruby support_data_reqs=true support_inst_reqs=true system=system -using_network_tester=false using_ruby_tester=true version=0 slave=system.cpu.cpuInstDataPort[0] @@ -405,10 +441,15 @@ L2cache=system.ruby.l2_cntrl0.L2cache buffer_size=0 clk_domain=system.ruby.clk_domain cluster_id=0 +default_p_state=UNDEFINED eventq_index=0 l2_request_latency=2 l2_response_latency=2 number_of_TBEs=256 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null recycle_latency=10 responseFromL2Cache=system.ruby.l2_cntrl0.responseFromL2Cache responseToL2Cache=system.ruby.l2_cntrl0.responseToL2Cache @@ -499,18 +540,23 @@ eventq_index=0 [system.ruby.network] type=SimpleNetwork -children=ext_links0 ext_links1 ext_links2 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_links0 int_links1 int_links2 routers0 routers1 routers2 routers3 +children=ext_links0 ext_links1 ext_links2 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_link_buffers20 int_link_buffers21 int_link_buffers22 int_link_buffers23 int_link_buffers24 int_link_buffers25 int_link_buffers26 int_link_buffers27 int_link_buffers28 int_link_buffers29 int_link_buffers30 int_link_buffers31 int_link_buffers32 int_link_buffers33 int_link_buffers34 int_link_buffers35 int_links0 int_links1 int_links2 int_links3 int_links4 int_links5 routers0 routers1 routers2 routers3 adaptive_routing=false buffer_size=0 clk_domain=system.ruby.clk_domain control_msg_size=8 +default_p_state=UNDEFINED endpoint_bandwidth=1000 eventq_index=0 ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1 system.ruby.network.ext_links2 -int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 -int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2 +int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19 system.ruby.network.int_link_buffers20 system.ruby.network.int_link_buffers21 system.ruby.network.int_link_buffers22 system.ruby.network.int_link_buffers23 system.ruby.network.int_link_buffers24 system.ruby.network.int_link_buffers25 system.ruby.network.int_link_buffers26 system.ruby.network.int_link_buffers27 system.ruby.network.int_link_buffers28 system.ruby.network.int_link_buffers29 system.ruby.network.int_link_buffers30 system.ruby.network.int_link_buffers31 system.ruby.network.int_link_buffers32 system.ruby.network.int_link_buffers33 system.ruby.network.int_link_buffers34 system.ruby.network.int_link_buffers35 +int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2 system.ruby.network.int_links3 system.ruby.network.int_links4 system.ruby.network.int_links5 netifs= number_of_virtual_networks=3 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null routers=system.ruby.network.routers0 system.ruby.network.routers1 system.ruby.network.routers2 system.ruby.network.routers3 ruby_system=system.ruby topology=Crossbar @@ -673,42 +719,216 @@ eventq_index=0 ordered=true randomization=false +[system.ruby.network.int_link_buffers18] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers19] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers20] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers21] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers22] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers23] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers24] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers25] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers26] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers27] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers28] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers29] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers30] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers31] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers32] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers33] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers34] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers35] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + [system.ruby.network.int_links0] type=SimpleIntLink bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers3 eventq_index=0 latency=1 link_id=3 -node_a=system.ruby.network.routers0 -node_b=system.ruby.network.routers3 +src_node=system.ruby.network.routers0 +src_outport= weight=1 [system.ruby.network.int_links1] type=SimpleIntLink bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers3 eventq_index=0 latency=1 link_id=4 -node_a=system.ruby.network.routers1 -node_b=system.ruby.network.routers3 +src_node=system.ruby.network.routers1 +src_outport= weight=1 [system.ruby.network.int_links2] type=SimpleIntLink bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers3 eventq_index=0 latency=1 link_id=5 -node_a=system.ruby.network.routers2 -node_b=system.ruby.network.routers3 +src_node=system.ruby.network.routers2 +src_outport= +weight=1 + +[system.ruby.network.int_links3] +type=SimpleIntLink +bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers0 +eventq_index=0 +latency=1 +link_id=6 +src_node=system.ruby.network.routers3 +src_outport= +weight=1 + +[system.ruby.network.int_links4] +type=SimpleIntLink +bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers1 +eventq_index=0 +latency=1 +link_id=7 +src_node=system.ruby.network.routers3 +src_outport= +weight=1 + +[system.ruby.network.int_links5] +type=SimpleIntLink +bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers2 +eventq_index=0 +latency=1 +link_id=8 +src_node=system.ruby.network.routers3 +src_outport= weight=1 [system.ruby.network.routers0] type=Switch children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED eventq_index=0 +latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 port_buffers=system.ruby.network.routers0.port_buffers00 system.ruby.network.routers0.port_buffers01 system.ruby.network.routers0.port_buffers02 system.ruby.network.routers0.port_buffers03 system.ruby.network.routers0.port_buffers04 system.ruby.network.routers0.port_buffers05 system.ruby.network.routers0.port_buffers06 system.ruby.network.routers0.port_buffers07 system.ruby.network.routers0.port_buffers08 system.ruby.network.routers0.port_buffers09 system.ruby.network.routers0.port_buffers10 system.ruby.network.routers0.port_buffers11 +power_model=Null router_id=0 virt_nets=3 @@ -800,8 +1020,14 @@ randomization=false type=Switch children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED eventq_index=0 +latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 port_buffers=system.ruby.network.routers1.port_buffers00 system.ruby.network.routers1.port_buffers01 system.ruby.network.routers1.port_buffers02 system.ruby.network.routers1.port_buffers03 system.ruby.network.routers1.port_buffers04 system.ruby.network.routers1.port_buffers05 system.ruby.network.routers1.port_buffers06 system.ruby.network.routers1.port_buffers07 system.ruby.network.routers1.port_buffers08 system.ruby.network.routers1.port_buffers09 system.ruby.network.routers1.port_buffers10 system.ruby.network.routers1.port_buffers11 +power_model=Null router_id=1 virt_nets=3 @@ -893,8 +1119,14 @@ randomization=false type=Switch children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED eventq_index=0 +latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 port_buffers=system.ruby.network.routers2.port_buffers00 system.ruby.network.routers2.port_buffers01 system.ruby.network.routers2.port_buffers02 system.ruby.network.routers2.port_buffers03 system.ruby.network.routers2.port_buffers04 system.ruby.network.routers2.port_buffers05 system.ruby.network.routers2.port_buffers06 system.ruby.network.routers2.port_buffers07 system.ruby.network.routers2.port_buffers08 system.ruby.network.routers2.port_buffers09 system.ruby.network.routers2.port_buffers10 system.ruby.network.routers2.port_buffers11 +power_model=Null router_id=2 virt_nets=3 @@ -986,8 +1218,14 @@ randomization=false type=Switch children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17 clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED eventq_index=0 +latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 port_buffers=system.ruby.network.routers3.port_buffers00 system.ruby.network.routers3.port_buffers01 system.ruby.network.routers3.port_buffers02 system.ruby.network.routers3.port_buffers03 system.ruby.network.routers3.port_buffers04 system.ruby.network.routers3.port_buffers05 system.ruby.network.routers3.port_buffers06 system.ruby.network.routers3.port_buffers07 system.ruby.network.routers3.port_buffers08 system.ruby.network.routers3.port_buffers09 system.ruby.network.routers3.port_buffers10 system.ruby.network.routers3.port_buffers11 system.ruby.network.routers3.port_buffers12 system.ruby.network.routers3.port_buffers13 system.ruby.network.routers3.port_buffers14 system.ruby.network.routers3.port_buffers15 system.ruby.network.routers3.port_buffers16 system.ruby.network.routers3.port_buffers17 +power_model=Null router_id=3 virt_nets=3 @@ -1120,9 +1358,14 @@ randomization=false [system.sys_port_proxy] type=RubyPortProxy clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 is_cpu_sequencer=true no_retry_on_stall=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null ruby_system=system.ruby support_data_reqs=true support_inst_reqs=true diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/simerr b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/simerr index c2086c0ba..cee0dfc57 100755 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/simerr +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/simerr @@ -4,7 +4,5 @@ warn: rounding error > tolerance 1.250000 rounded to 1 warn: rounding error > tolerance 1.250000 rounded to 1 -warn: rounding error > tolerance - 1.250000 rounded to 1 warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes) warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files! diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/simout b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/simout index db9c26437..8e5796606 100755 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/simout +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/simout @@ -1,11 +1,13 @@ +Redirecting stdout to build/ALPHA_MESI_Two_Level/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MESI_Two_Level/simout +Redirecting stderr to build/ALPHA_MESI_Two_Level/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MESI_Two_Level/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 21 2016 14:01:33 -gem5 started Jan 21 2016 14:02:10 -gem5 executing on zizzer, pid 44718 -command line: build/ALPHA_MESI_Two_Level/gem5.opt -d build/ALPHA_MESI_Two_Level/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MESI_Two_Level -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ALPHA_MESI_Two_Level/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MESI_Two_Level +gem5 compiled Oct 13 2016 20:28:06 +gem5 started Oct 13 2016 20:28:31 +gem5 executing on e108600-lin, pid 8234 +command line: /work/curdun01/gem5-external.hg/build/ALPHA_MESI_Two_Level/gem5.opt -d build/ALPHA_MESI_Two_Level/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MESI_Two_Level -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/60.rubytest/alpha/linux/rubytest-ruby-MESI_Two_Level Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 43191 because Ruby Tester completed +Exiting @ tick 44021 because Ruby Tester completed diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/stats.txt b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/stats.txt index da6a7f59a..ed12265fc 100644 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/stats.txt +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/stats.txt @@ -1,45 +1,45 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000043 # Number of seconds simulated -sim_ticks 43191 # Number of ticks simulated -final_tick 43191 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000044 # Number of seconds simulated +sim_ticks 44021 # Number of ticks simulated +final_tick 44021 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 648785 # Simulator tick rate (ticks/s) -host_mem_usage 451080 # Number of bytes of host memory used -host_seconds 0.07 # Real time elapsed on the host +host_tick_rate 728057 # Simulator tick rate (ticks/s) +host_mem_usage 409368 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks -system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 43191 # Cumulative time (in ticks) in various power states -system.mem_ctrls.bytes_read::ruby.dir_cntrl0 57728 # Number of bytes read from this memory -system.mem_ctrls.bytes_read::total 57728 # Number of bytes read from this memory -system.mem_ctrls.bytes_written::ruby.dir_cntrl0 51904 # Number of bytes written to this memory -system.mem_ctrls.bytes_written::total 51904 # Number of bytes written to this memory -system.mem_ctrls.num_reads::ruby.dir_cntrl0 902 # Number of read requests responded to by this memory -system.mem_ctrls.num_reads::total 902 # Number of read requests responded to by this memory -system.mem_ctrls.num_writes::ruby.dir_cntrl0 811 # Number of write requests responded to by this memory -system.mem_ctrls.num_writes::total 811 # Number of write requests responded to by this memory -system.mem_ctrls.bw_read::ruby.dir_cntrl0 1336574749 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_read::total 1336574749 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::ruby.dir_cntrl0 1201731842 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::total 1201731842 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_total::ruby.dir_cntrl0 2538306592 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.bw_total::total 2538306592 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.readReqs 902 # Number of read requests accepted -system.mem_ctrls.writeReqs 811 # Number of write requests accepted -system.mem_ctrls.readBursts 902 # Number of DRAM read bursts, including those serviced by the write queue -system.mem_ctrls.writeBursts 811 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrls.bytesReadDRAM 47168 # Total number of bytes read from DRAM -system.mem_ctrls.bytesReadWrQ 10560 # Total number of bytes read from write queue -system.mem_ctrls.bytesWritten 41728 # Total number of bytes written to DRAM -system.mem_ctrls.bytesReadSys 57728 # Total read bytes from the system interface side -system.mem_ctrls.bytesWrittenSys 51904 # Total written bytes from the system interface side -system.mem_ctrls.servicedByWrQ 165 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrls.mergedWrBursts 130 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 44021 # Cumulative time (in ticks) in various power states +system.mem_ctrls.bytes_read::ruby.dir_cntrl0 55424 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 55424 # Number of bytes read from this memory +system.mem_ctrls.bytes_written::ruby.dir_cntrl0 49920 # Number of bytes written to this memory +system.mem_ctrls.bytes_written::total 49920 # Number of bytes written to this memory +system.mem_ctrls.num_reads::ruby.dir_cntrl0 866 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 866 # Number of read requests responded to by this memory +system.mem_ctrls.num_writes::ruby.dir_cntrl0 780 # Number of write requests responded to by this memory +system.mem_ctrls.num_writes::total 780 # Number of write requests responded to by this memory +system.mem_ctrls.bw_read::ruby.dir_cntrl0 1259035460 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 1259035460 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::ruby.dir_cntrl0 1134004225 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::total 1134004225 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::ruby.dir_cntrl0 2393039686 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 2393039686 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.readReqs 866 # Number of read requests accepted +system.mem_ctrls.writeReqs 780 # Number of write requests accepted +system.mem_ctrls.readBursts 866 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 780 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.bytesReadDRAM 45760 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 9664 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 40640 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 55424 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 49920 # Total written bytes from the system interface side +system.mem_ctrls.servicedByWrQ 151 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 116 # Number of DRAM write bursts merged with an existing one system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.mem_ctrls.perBankRdBursts::0 232 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::1 230 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::2 227 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::3 48 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::0 210 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 228 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 223 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 54 # Per bank write bursts system.mem_ctrls.perBankRdBursts::4 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::5 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::6 0 # Per bank write bursts @@ -52,10 +52,10 @@ system.mem_ctrls.perBankRdBursts::12 0 # Pe system.mem_ctrls.perBankRdBursts::13 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::14 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::15 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::0 201 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::1 202 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 184 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 198 # Per bank write bursts system.mem_ctrls.perBankWrBursts::2 203 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::3 46 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 50 # Per bank write bursts system.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts @@ -70,24 +70,24 @@ system.mem_ctrls.perBankWrBursts::14 0 # Pe system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrls.totGap 43109 # Total gap between requests +system.mem_ctrls.totGap 44002 # Total gap between requests system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::6 902 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 866 # Read request sizes (log2) system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::6 811 # Write request sizes (log2) -system.mem_ctrls.rdQLenPdf::0 456 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::1 281 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see +system.mem_ctrls.writePktSize::6 780 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 430 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 284 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::2 1 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -132,24 +132,24 @@ system.mem_ctrls.wrQLenPdf::11 1 # Wh system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::15 5 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::16 6 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::17 24 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::18 41 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::19 42 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::20 41 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::21 43 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::22 42 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::23 42 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::24 41 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::25 43 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::26 50 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::27 45 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 6 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 7 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 29 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 40 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 41 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 40 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 40 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 40 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 40 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::24 40 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 41 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 40 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 48 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::28 41 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::29 40 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::30 40 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::31 40 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::32 40 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 39 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 39 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 39 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::32 39 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see @@ -181,140 +181,146 @@ system.mem_ctrls.wrQLenPdf::60 0 # Wh system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrls.bytesPerActivate::samples 94 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::mean 928 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::gmean 868.246553 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::stdev 227.729324 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::0-127 1 1.06% 1.06% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::128-255 2 2.13% 3.19% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::256-383 3 3.19% 6.38% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::384-511 1 1.06% 7.45% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::512-639 4 4.26% 11.70% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::640-767 3 3.19% 14.89% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::768-895 2 2.13% 17.02% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::896-1023 3 3.19% 20.21% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::1024-1151 75 79.79% 100.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::total 94 # Bytes accessed per row activation -system.mem_ctrls.rdPerTurnAround::samples 40 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::mean 18.125000 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::gmean 17.875881 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::stdev 3.480256 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::14-15 4 10.00% 10.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::16-17 17 42.50% 52.50% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::18-19 12 30.00% 82.50% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::20-21 2 5.00% 87.50% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::22-23 3 7.50% 95.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::24-25 1 2.50% 97.50% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::34-35 1 2.50% 100.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::total 40 # Reads before turning the bus around for writes -system.mem_ctrls.wrPerTurnAround::samples 40 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::mean 16.300000 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::gmean 16.280005 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::stdev 0.853349 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::16 35 87.50% 87.50% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::17 1 2.50% 90.00% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::18 1 2.50% 92.50% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::19 3 7.50% 100.00% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::total 40 # Writes before turning the bus around for reads -system.mem_ctrls.totQLat 8956 # Total ticks spent queuing -system.mem_ctrls.totMemAccLat 22959 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrls.totBusLat 3685 # Total ticks spent in databus transfers -system.mem_ctrls.avgQLat 12.15 # Average queueing delay per DRAM burst +system.mem_ctrls.bytesPerActivate::samples 93 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 915.268817 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 819.587468 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 267.362608 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 2 2.15% 2.15% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 5 5.38% 7.53% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 1 1.08% 8.60% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 3 3.23% 11.83% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 3 3.23% 15.05% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 4 4.30% 19.35% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 75 80.65% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 93 # Bytes accessed per row activation +system.mem_ctrls.rdPerTurnAround::samples 39 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::mean 17.897436 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::gmean 17.675839 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::stdev 3.385689 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::14-15 5 12.82% 12.82% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::16-17 14 35.90% 48.72% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::18-19 15 38.46% 87.18% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::20-21 3 7.69% 94.87% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::22-23 1 2.56% 97.44% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::36-37 1 2.56% 100.00% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::total 39 # Reads before turning the bus around for writes +system.mem_ctrls.wrPerTurnAround::samples 39 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::mean 16.282051 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::gmean 16.268709 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::stdev 0.686284 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::16 33 84.62% 84.62% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::17 1 2.56% 87.18% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::18 5 12.82% 100.00% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::total 39 # Writes before turning the bus around for reads +system.mem_ctrls.totQLat 12989 # Total ticks spent queuing +system.mem_ctrls.totMemAccLat 26574 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.totBusLat 3575 # Total ticks spent in databus transfers +system.mem_ctrls.avgQLat 18.17 # Average queueing delay per DRAM burst system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst -system.mem_ctrls.avgMemAccLat 31.15 # Average memory access latency per DRAM burst -system.mem_ctrls.avgRdBW 1092.08 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrls.avgWrBW 966.13 # Average achieved write bandwidth in MiByte/s -system.mem_ctrls.avgRdBWSys 1336.57 # Average system read bandwidth in MiByte/s -system.mem_ctrls.avgWrBWSys 1201.73 # Average system write bandwidth in MiByte/s +system.mem_ctrls.avgMemAccLat 37.17 # Average memory access latency per DRAM burst +system.mem_ctrls.avgRdBW 1039.50 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 923.20 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 1259.04 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 1134.00 # Average system write bandwidth in MiByte/s system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrls.busUtil 16.08 # Data bus utilization in percentage -system.mem_ctrls.busUtilRead 8.53 # Data bus utilization in percentage for reads -system.mem_ctrls.busUtilWrite 7.55 # Data bus utilization in percentage for writes -system.mem_ctrls.avgRdQLen 1.63 # Average read queue length when enqueuing -system.mem_ctrls.avgWrQLen 25.46 # Average write queue length when enqueuing -system.mem_ctrls.readRowHits 647 # Number of row buffer hits during reads -system.mem_ctrls.writeRowHits 644 # Number of row buffer hits during writes -system.mem_ctrls.readRowHitRate 87.79 # Row buffer hit rate for reads -system.mem_ctrls.writeRowHitRate 94.57 # Row buffer hit rate for writes -system.mem_ctrls.avgGap 25.17 # Average gap between requests -system.mem_ctrls.pageHitRate 91.04 # Row buffer hit rate, read and write combined -system.mem_ctrls_0.actEnergy 665280 # Energy for activate commands per rank (pJ) -system.mem_ctrls_0.preEnergy 369600 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_0.readEnergy 8311680 # Energy for read commands per rank (pJ) -system.mem_ctrls_0.writeEnergy 6231168 # Energy for write commands per rank (pJ) -system.mem_ctrls_0.refreshEnergy 2542800 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_0.actBackEnergy 26706780 # Energy for active background per rank (pJ) -system.mem_ctrls_0.preBackEnergy 87000 # Energy for precharge background per rank (pJ) -system.mem_ctrls_0.totalEnergy 44914308 # Total energy per rank (pJ) -system.mem_ctrls_0.averagePower 1146.065527 # Core power per rank (mW) -system.mem_ctrls_0.memoryStateTime::IDLE 19 # Time in different power states +system.mem_ctrls.busUtil 15.33 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 8.12 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 7.21 # Data bus utilization in percentage for writes +system.mem_ctrls.avgRdQLen 1.66 # Average read queue length when enqueuing +system.mem_ctrls.avgWrQLen 25.56 # Average write queue length when enqueuing +system.mem_ctrls.readRowHits 627 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 627 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 87.69 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate 94.43 # Row buffer hit rate for writes +system.mem_ctrls.avgGap 26.73 # Average gap between requests +system.mem_ctrls.pageHitRate 90.94 # Row buffer hit rate, read and write combined +system.mem_ctrls_0.actEnergy 685440 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 359352 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 8168160 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 5303520 # Energy for write commands per rank (pJ) +system.mem_ctrls_0.refreshEnergy 3073200.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 8952648 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 72576 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.actPowerDownEnergy 11032464 # Energy for active power-down per rank (pJ) +system.mem_ctrls_0.prePowerDownEnergy 1920 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls_0.totalEnergy 37649280 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 855.257264 # Core power per rank (mW) +system.mem_ctrls_0.totalIdleTime 24199 # Total Idle time Per DRAM Rank +system.mem_ctrls_0.memoryStateTime::IDLE 49 # Time in different power states system.mem_ctrls_0.memoryStateTime::REF 1300 # Time in different power states -system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT 37885 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls_0.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls_0.memoryStateTime::PRE_PDN 5 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 18473 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT_PDN 24194 # Time in different power states system.mem_ctrls_1.actEnergy 0 # Energy for activate commands per rank (pJ) system.mem_ctrls_1.preEnergy 0 # Energy for precharge commands per rank (pJ) system.mem_ctrls_1.readEnergy 0 # Energy for read commands per rank (pJ) system.mem_ctrls_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.mem_ctrls_1.refreshEnergy 2542800 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_1.actBackEnergy 841320 # Energy for active background per rank (pJ) -system.mem_ctrls_1.preBackEnergy 22767600 # Energy for precharge background per rank (pJ) -system.mem_ctrls_1.totalEnergy 26151720 # Total energy per rank (pJ) -system.mem_ctrls_1.averagePower 667.544415 # Core power per rank (mW) -system.mem_ctrls_1.memoryStateTime::IDLE 37890 # Time in different power states -system.mem_ctrls_1.memoryStateTime::REF 1300 # Time in different power states -system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_1.refreshEnergy 1229280.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 224352 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 3002880 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls_1.prePowerDownEnergy 2889984 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls_1.selfRefreshEnergy 6763920 # Energy for self refresh per rank (pJ) +system.mem_ctrls_1.totalEnergy 14110416 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 320.538289 # Core power per rank (mW) +system.mem_ctrls_1.totalIdleTime 7526 # Total Idle time Per DRAM Rank +system.mem_ctrls_1.memoryStateTime::IDLE 7786 # Time in different power states +system.mem_ctrls_1.memoryStateTime::REF 526 # Time in different power states +system.mem_ctrls_1.memoryStateTime::SREF 28183 # Time in different power states +system.mem_ctrls_1.memoryStateTime::PRE_PDN 7526 # Time in different power states system.mem_ctrls_1.memoryStateTime::ACT 0 # Time in different power states system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 43191 # Cumulative time (in ticks) in various power states -system.cpu.pwrStateResidencyTicks::UNDEFINED 43191 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 44021 # Cumulative time (in ticks) in various power states +system.cpu.pwrStateResidencyTicks::UNDEFINED 44021 # Cumulative time (in ticks) in various power states system.ruby.clk_domain.clock 1 # Clock period in ticks -system.ruby.pwrStateResidencyTicks::UNDEFINED 43191 # Cumulative time (in ticks) in various power states +system.ruby.pwrStateResidencyTicks::UNDEFINED 44021 # Cumulative time (in ticks) in various power states system.ruby.delayHist::bucket_size 4 # delay histogram for all message system.ruby.delayHist::max_bucket 39 # delay histogram for all message -system.ruby.delayHist::samples 6720 # delay histogram for all message -system.ruby.delayHist::mean 2.675000 # delay histogram for all message -system.ruby.delayHist::stdev 5.399947 # delay histogram for all message -system.ruby.delayHist | 5144 76.55% 76.55% | 51 0.76% 77.31% | 1138 16.93% 94.24% | 8 0.12% 94.36% | 323 4.81% 99.17% | 6 0.09% 99.26% | 0 0.00% 99.26% | 43 0.64% 99.90% | 0 0.00% 99.90% | 7 0.10% 100.00% # delay histogram for all message -system.ruby.delayHist::total 6720 # delay histogram for all message +system.ruby.delayHist::samples 6525 # delay histogram for all message +system.ruby.delayHist::mean 2.632031 # delay histogram for all message +system.ruby.delayHist::stdev 5.481611 # delay histogram for all message +system.ruby.delayHist | 5040 77.24% 77.24% | 61 0.93% 78.18% | 1056 16.18% 94.36% | 7 0.11% 94.47% | 285 4.37% 98.84% | 1 0.02% 98.85% | 1 0.02% 98.87% | 70 1.07% 99.94% | 0 0.00% 99.94% | 4 0.06% 100.00% # delay histogram for all message +system.ruby.delayHist::total 6525 # delay histogram for all message system.ruby.outstanding_req_hist_seqr::bucket_size 2 system.ruby.outstanding_req_hist_seqr::max_bucket 19 -system.ruby.outstanding_req_hist_seqr::samples 1041 -system.ruby.outstanding_req_hist_seqr::mean 15.700288 -system.ruby.outstanding_req_hist_seqr::gmean 15.598621 -system.ruby.outstanding_req_hist_seqr::stdev 1.186661 -system.ruby.outstanding_req_hist_seqr | 1 0.10% 0.10% | 2 0.19% 0.29% | 2 0.19% 0.48% | 2 0.19% 0.67% | 4 0.38% 1.06% | 2 0.19% 1.25% | 5 0.48% 1.73% | 167 16.04% 17.77% | 856 82.23% 100.00% | 0 0.00% 100.00% -system.ruby.outstanding_req_hist_seqr::total 1041 +system.ruby.outstanding_req_hist_seqr::samples 1019 +system.ruby.outstanding_req_hist_seqr::mean 15.664377 +system.ruby.outstanding_req_hist_seqr::gmean 15.560778 +system.ruby.outstanding_req_hist_seqr::stdev 1.199712 +system.ruby.outstanding_req_hist_seqr | 1 0.10% 0.10% | 2 0.20% 0.29% | 2 0.20% 0.49% | 2 0.20% 0.69% | 4 0.39% 1.08% | 2 0.20% 1.28% | 5 0.49% 1.77% | 199 19.53% 21.30% | 802 78.70% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist_seqr::total 1019 system.ruby.latency_hist_seqr::bucket_size 128 system.ruby.latency_hist_seqr::max_bucket 1279 -system.ruby.latency_hist_seqr::samples 1025 -system.ruby.latency_hist_seqr::mean 658.597073 -system.ruby.latency_hist_seqr::gmean 361.484818 -system.ruby.latency_hist_seqr::stdev 297.350955 -system.ruby.latency_hist_seqr | 154 15.02% 15.02% | 24 2.34% 17.37% | 5 0.49% 17.85% | 4 0.39% 18.24% | 32 3.12% 21.37% | 302 29.46% 50.83% | 418 40.78% 91.61% | 49 4.78% 96.39% | 28 2.73% 99.12% | 9 0.88% 100.00% -system.ruby.latency_hist_seqr::total 1025 +system.ruby.latency_hist_seqr::samples 1004 +system.ruby.latency_hist_seqr::mean 684.454183 +system.ruby.latency_hist_seqr::gmean 346.202279 +system.ruby.latency_hist_seqr::stdev 321.934539 +system.ruby.latency_hist_seqr | 155 15.44% 15.44% | 28 2.79% 18.23% | 4 0.40% 18.63% | 3 0.30% 18.92% | 6 0.60% 19.52% | 263 26.20% 45.72% | 367 36.55% 82.27% | 113 11.25% 93.53% | 53 5.28% 98.80% | 12 1.20% 100.00% +system.ruby.latency_hist_seqr::total 1004 system.ruby.hit_latency_hist_seqr::bucket_size 1 system.ruby.hit_latency_hist_seqr::max_bucket 9 -system.ruby.hit_latency_hist_seqr::samples 89 +system.ruby.hit_latency_hist_seqr::samples 101 system.ruby.hit_latency_hist_seqr::mean 1 system.ruby.hit_latency_hist_seqr::gmean 1 -system.ruby.hit_latency_hist_seqr | 0 0.00% 0.00% | 89 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.hit_latency_hist_seqr::total 89 +system.ruby.hit_latency_hist_seqr | 0 0.00% 0.00% | 101 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.hit_latency_hist_seqr::total 101 system.ruby.miss_latency_hist_seqr::bucket_size 128 system.ruby.miss_latency_hist_seqr::max_bucket 1279 -system.ruby.miss_latency_hist_seqr::samples 936 -system.ruby.miss_latency_hist_seqr::mean 721.125000 -system.ruby.miss_latency_hist_seqr::gmean 632.888578 -system.ruby.miss_latency_hist_seqr::stdev 227.503250 -system.ruby.miss_latency_hist_seqr | 65 6.94% 6.94% | 24 2.56% 9.51% | 5 0.53% 10.04% | 4 0.43% 10.47% | 32 3.42% 13.89% | 302 32.26% 46.15% | 418 44.66% 90.81% | 49 5.24% 96.05% | 28 2.99% 99.04% | 9 0.96% 100.00% -system.ruby.miss_latency_hist_seqr::total 936 -system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 43191 # Cumulative time (in ticks) in various power states -system.ruby.l1_cntrl0.L1Dcache.demand_hits 89 # Number of cache demand hits -system.ruby.l1_cntrl0.L1Dcache.demand_misses 875 # Number of cache demand misses -system.ruby.l1_cntrl0.L1Dcache.demand_accesses 964 # Number of cache demand accesses +system.ruby.miss_latency_hist_seqr::samples 903 +system.ruby.miss_latency_hist_seqr::mean 760.898117 +system.ruby.miss_latency_hist_seqr::gmean 665.813242 +system.ruby.miss_latency_hist_seqr::stdev 238.941361 +system.ruby.miss_latency_hist_seqr | 54 5.98% 5.98% | 28 3.10% 9.08% | 4 0.44% 9.52% | 3 0.33% 9.86% | 6 0.66% 10.52% | 263 29.13% 39.65% | 367 40.64% 80.29% | 113 12.51% 92.80% | 53 5.87% 98.67% | 12 1.33% 100.00% +system.ruby.miss_latency_hist_seqr::total 903 +system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 44021 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl0.L1Dcache.demand_hits 101 # Number of cache demand hits +system.ruby.l1_cntrl0.L1Dcache.demand_misses 855 # Number of cache demand misses +system.ruby.l1_cntrl0.L1Dcache.demand_accesses 956 # Number of cache demand accesses system.ruby.l1_cntrl0.L1Icache.demand_hits 0 # Number of cache demand hits -system.ruby.l1_cntrl0.L1Icache.demand_misses 64 # Number of cache demand misses -system.ruby.l1_cntrl0.L1Icache.demand_accesses 64 # Number of cache demand accesses +system.ruby.l1_cntrl0.L1Icache.demand_misses 50 # Number of cache demand misses +system.ruby.l1_cntrl0.L1Icache.demand_accesses 50 # Number of cache demand accesses system.ruby.l1_cntrl0.prefetcher.miss_observed 0 # number of misses observed system.ruby.l1_cntrl0.prefetcher.allocated_streams 0 # number of streams allocated for prefetching system.ruby.l1_cntrl0.prefetcher.prefetches_requested 0 # number of prefetch requests made @@ -324,340 +330,346 @@ system.ruby.l1_cntrl0.prefetcher.hits 0 # nu system.ruby.l1_cntrl0.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched system.ruby.l1_cntrl0.prefetcher.pages_crossed 0 # number of prefetches across pages system.ruby.l1_cntrl0.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed -system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 43191 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 44021 # Cumulative time (in ticks) in various power states system.ruby.l1_cntrl0.sequencer.store_waiting_on_load 4 # Number of times a store aliased with a pending load -system.ruby.l1_cntrl0.sequencer.store_waiting_on_store 80 # Number of times a store aliased with a pending store -system.ruby.l1_cntrl0.sequencer.load_waiting_on_store 6 # Number of times a load aliased with a pending store -system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 43191 # Cumulative time (in ticks) in various power states -system.ruby.l2_cntrl0.L2cache.demand_hits 34 # Number of cache demand hits -system.ruby.l2_cntrl0.L2cache.demand_misses 904 # Number of cache demand misses -system.ruby.l2_cntrl0.L2cache.demand_accesses 938 # Number of cache demand accesses -system.ruby.l2_cntrl0.pwrStateResidencyTicks::UNDEFINED 43191 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl0.sequencer.store_waiting_on_store 86 # Number of times a store aliased with a pending store +system.ruby.l1_cntrl0.sequencer.load_waiting_on_store 8 # Number of times a load aliased with a pending store +system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 44021 # Cumulative time (in ticks) in various power states +system.ruby.l2_cntrl0.L2cache.demand_hits 39 # Number of cache demand hits +system.ruby.l2_cntrl0.L2cache.demand_misses 866 # Number of cache demand misses +system.ruby.l2_cntrl0.L2cache.demand_accesses 905 # Number of cache demand accesses +system.ruby.l2_cntrl0.pwrStateResidencyTicks::UNDEFINED 44021 # Cumulative time (in ticks) in various power states system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 43191 # Cumulative time (in ticks) in various power states -system.ruby.network.routers0.percent_links_utilized 11.804543 -system.ruby.network.routers0.msg_count.Control::0 939 -system.ruby.network.routers0.msg_count.Request_Control::2 278 -system.ruby.network.routers0.msg_count.Response_Data::1 936 -system.ruby.network.routers0.msg_count.Response_Control::1 873 -system.ruby.network.routers0.msg_count.Response_Control::2 873 -system.ruby.network.routers0.msg_count.Writeback_Data::0 785 -system.ruby.network.routers0.msg_count.Writeback_Data::1 213 -system.ruby.network.routers0.msg_count.Writeback_Control::0 25 -system.ruby.network.routers0.msg_bytes.Control::0 7512 -system.ruby.network.routers0.msg_bytes.Request_Control::2 2224 -system.ruby.network.routers0.msg_bytes.Response_Data::1 67392 -system.ruby.network.routers0.msg_bytes.Response_Control::1 6984 -system.ruby.network.routers0.msg_bytes.Response_Control::2 6984 -system.ruby.network.routers0.msg_bytes.Writeback_Data::0 56520 -system.ruby.network.routers0.msg_bytes.Writeback_Data::1 15336 -system.ruby.network.routers0.msg_bytes.Writeback_Control::0 200 -system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 43191 # Cumulative time (in ticks) in various power states -system.ruby.network.routers1.percent_links_utilized 21.822255 -system.ruby.network.routers1.msg_count.Control::0 1842 -system.ruby.network.routers1.msg_count.Request_Control::2 279 -system.ruby.network.routers1.msg_count.Response_Data::1 2649 -system.ruby.network.routers1.msg_count.Response_Control::1 1859 -system.ruby.network.routers1.msg_count.Response_Control::2 873 -system.ruby.network.routers1.msg_count.Writeback_Data::0 785 -system.ruby.network.routers1.msg_count.Writeback_Data::1 213 -system.ruby.network.routers1.msg_count.Writeback_Control::0 25 -system.ruby.network.routers1.msg_bytes.Control::0 14736 -system.ruby.network.routers1.msg_bytes.Request_Control::2 2232 -system.ruby.network.routers1.msg_bytes.Response_Data::1 190728 -system.ruby.network.routers1.msg_bytes.Response_Control::1 14872 -system.ruby.network.routers1.msg_bytes.Response_Control::2 6984 -system.ruby.network.routers1.msg_bytes.Writeback_Data::0 56520 -system.ruby.network.routers1.msg_bytes.Writeback_Data::1 15336 -system.ruby.network.routers1.msg_bytes.Writeback_Control::0 200 -system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 43191 # Cumulative time (in ticks) in various power states -system.ruby.network.routers2.percent_links_utilized 10.015976 -system.ruby.network.routers2.msg_count.Control::0 902 -system.ruby.network.routers2.msg_count.Response_Data::1 1713 -system.ruby.network.routers2.msg_count.Response_Control::1 985 -system.ruby.network.routers2.msg_bytes.Control::0 7216 -system.ruby.network.routers2.msg_bytes.Response_Data::1 123336 -system.ruby.network.routers2.msg_bytes.Response_Control::1 7880 -system.ruby.network.routers3.pwrStateResidencyTicks::UNDEFINED 43191 # Cumulative time (in ticks) in various power states -system.ruby.network.routers3.percent_links_utilized 14.547012 -system.ruby.network.routers3.msg_count.Control::0 1841 -system.ruby.network.routers3.msg_count.Request_Control::2 278 -system.ruby.network.routers3.msg_count.Response_Data::1 2649 -system.ruby.network.routers3.msg_count.Response_Control::1 1858 -system.ruby.network.routers3.msg_count.Response_Control::2 873 -system.ruby.network.routers3.msg_count.Writeback_Data::0 785 -system.ruby.network.routers3.msg_count.Writeback_Data::1 213 -system.ruby.network.routers3.msg_count.Writeback_Control::0 25 -system.ruby.network.routers3.msg_bytes.Control::0 14728 -system.ruby.network.routers3.msg_bytes.Request_Control::2 2224 -system.ruby.network.routers3.msg_bytes.Response_Data::1 190728 -system.ruby.network.routers3.msg_bytes.Response_Control::1 14864 -system.ruby.network.routers3.msg_bytes.Response_Control::2 6984 -system.ruby.network.routers3.msg_bytes.Writeback_Data::0 56520 -system.ruby.network.routers3.msg_bytes.Writeback_Data::1 15336 -system.ruby.network.routers3.msg_bytes.Writeback_Control::0 200 -system.ruby.network.pwrStateResidencyTicks::UNDEFINED 43191 # Cumulative time (in ticks) in various power states -system.ruby.network.msg_count.Control 5524 -system.ruby.network.msg_count.Request_Control 835 -system.ruby.network.msg_count.Response_Data 7947 -system.ruby.network.msg_count.Response_Control 8194 -system.ruby.network.msg_count.Writeback_Data 2994 -system.ruby.network.msg_count.Writeback_Control 75 -system.ruby.network.msg_byte.Control 44192 -system.ruby.network.msg_byte.Request_Control 6680 -system.ruby.network.msg_byte.Response_Data 572184 -system.ruby.network.msg_byte.Response_Control 65552 -system.ruby.network.msg_byte.Writeback_Data 215568 -system.ruby.network.msg_byte.Writeback_Control 600 -system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 43191 # Cumulative time (in ticks) in various power states -system.ruby.network.routers0.throttle0.link_utilization 11.009238 -system.ruby.network.routers0.throttle0.msg_count.Request_Control::2 278 -system.ruby.network.routers0.throttle0.msg_count.Response_Data::1 936 -system.ruby.network.routers0.throttle0.msg_count.Response_Control::1 808 -system.ruby.network.routers0.throttle0.msg_bytes.Request_Control::2 2224 -system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::1 67392 -system.ruby.network.routers0.throttle0.msg_bytes.Response_Control::1 6464 -system.ruby.network.routers0.throttle1.link_utilization 12.599847 -system.ruby.network.routers0.throttle1.msg_count.Control::0 939 -system.ruby.network.routers0.throttle1.msg_count.Response_Control::1 65 -system.ruby.network.routers0.throttle1.msg_count.Response_Control::2 873 -system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::0 785 -system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::1 213 -system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::0 25 -system.ruby.network.routers0.throttle1.msg_bytes.Control::0 7512 -system.ruby.network.routers0.throttle1.msg_bytes.Response_Control::1 520 -system.ruby.network.routers0.throttle1.msg_bytes.Response_Control::2 6984 -system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::0 56520 -system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::1 15336 -system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::0 200 -system.ruby.network.routers1.throttle0.link_utilization 23.037207 -system.ruby.network.routers1.throttle0.msg_count.Control::0 939 -system.ruby.network.routers1.throttle0.msg_count.Response_Data::1 902 -system.ruby.network.routers1.throttle0.msg_count.Response_Control::1 963 -system.ruby.network.routers1.throttle0.msg_count.Response_Control::2 873 -system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::0 785 -system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::1 213 -system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::0 25 -system.ruby.network.routers1.throttle0.msg_bytes.Control::0 7512 -system.ruby.network.routers1.throttle0.msg_bytes.Response_Data::1 64944 -system.ruby.network.routers1.throttle0.msg_bytes.Response_Control::1 7704 -system.ruby.network.routers1.throttle0.msg_bytes.Response_Control::2 6984 -system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::0 56520 -system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::1 15336 -system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::0 200 -system.ruby.network.routers1.throttle1.link_utilization 20.607302 -system.ruby.network.routers1.throttle1.msg_count.Control::0 903 -system.ruby.network.routers1.throttle1.msg_count.Request_Control::2 279 -system.ruby.network.routers1.throttle1.msg_count.Response_Data::1 1747 -system.ruby.network.routers1.throttle1.msg_count.Response_Control::1 896 -system.ruby.network.routers1.throttle1.msg_bytes.Control::0 7224 -system.ruby.network.routers1.throttle1.msg_bytes.Request_Control::2 2232 -system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::1 125784 -system.ruby.network.routers1.throttle1.msg_bytes.Response_Control::1 7168 -system.ruby.network.routers2.throttle0.link_utilization 9.594591 -system.ruby.network.routers2.throttle0.msg_count.Control::0 902 -system.ruby.network.routers2.throttle0.msg_count.Response_Data::1 811 -system.ruby.network.routers2.throttle0.msg_count.Response_Control::1 87 -system.ruby.network.routers2.throttle0.msg_bytes.Control::0 7216 -system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::1 58392 -system.ruby.network.routers2.throttle0.msg_bytes.Response_Control::1 696 -system.ruby.network.routers2.throttle1.link_utilization 10.437360 -system.ruby.network.routers2.throttle1.msg_count.Response_Data::1 902 -system.ruby.network.routers2.throttle1.msg_count.Response_Control::1 898 -system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::1 64944 -system.ruby.network.routers2.throttle1.msg_bytes.Response_Control::1 7184 -system.ruby.network.routers3.throttle0.link_utilization 11.009238 -system.ruby.network.routers3.throttle0.msg_count.Request_Control::2 278 -system.ruby.network.routers3.throttle0.msg_count.Response_Data::1 936 -system.ruby.network.routers3.throttle0.msg_count.Response_Control::1 808 -system.ruby.network.routers3.throttle0.msg_bytes.Request_Control::2 2224 -system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::1 67392 -system.ruby.network.routers3.throttle0.msg_bytes.Response_Control::1 6464 -system.ruby.network.routers3.throttle1.link_utilization 23.037207 -system.ruby.network.routers3.throttle1.msg_count.Control::0 939 -system.ruby.network.routers3.throttle1.msg_count.Response_Data::1 902 -system.ruby.network.routers3.throttle1.msg_count.Response_Control::1 963 -system.ruby.network.routers3.throttle1.msg_count.Response_Control::2 873 -system.ruby.network.routers3.throttle1.msg_count.Writeback_Data::0 785 -system.ruby.network.routers3.throttle1.msg_count.Writeback_Data::1 213 -system.ruby.network.routers3.throttle1.msg_count.Writeback_Control::0 25 -system.ruby.network.routers3.throttle1.msg_bytes.Control::0 7512 -system.ruby.network.routers3.throttle1.msg_bytes.Response_Data::1 64944 -system.ruby.network.routers3.throttle1.msg_bytes.Response_Control::1 7704 -system.ruby.network.routers3.throttle1.msg_bytes.Response_Control::2 6984 -system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::0 56520 -system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::1 15336 -system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::0 200 -system.ruby.network.routers3.throttle2.link_utilization 9.594591 -system.ruby.network.routers3.throttle2.msg_count.Control::0 902 -system.ruby.network.routers3.throttle2.msg_count.Response_Data::1 811 -system.ruby.network.routers3.throttle2.msg_count.Response_Control::1 87 -system.ruby.network.routers3.throttle2.msg_bytes.Control::0 7216 -system.ruby.network.routers3.throttle2.msg_bytes.Response_Data::1 58392 -system.ruby.network.routers3.throttle2.msg_bytes.Response_Control::1 696 +system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 44021 # Cumulative time (in ticks) in various power states +system.ruby.network.routers0.percent_links_utilized 11.308239 +system.ruby.network.routers0.msg_count.Control::0 905 +system.ruby.network.routers0.msg_count.Request_Control::2 268 +system.ruby.network.routers0.msg_count.Response_Data::1 902 +system.ruby.network.routers0.msg_count.Response_Control::1 853 +system.ruby.network.routers0.msg_count.Response_Control::2 852 +system.ruby.network.routers0.msg_count.Writeback_Data::0 769 +system.ruby.network.routers0.msg_count.Writeback_Data::1 218 +system.ruby.network.routers0.msg_count.Writeback_Control::0 33 +system.ruby.network.routers0.msg_bytes.Control::0 7240 +system.ruby.network.routers0.msg_bytes.Request_Control::2 2144 +system.ruby.network.routers0.msg_bytes.Response_Data::1 64944 +system.ruby.network.routers0.msg_bytes.Response_Control::1 6824 +system.ruby.network.routers0.msg_bytes.Response_Control::2 6816 +system.ruby.network.routers0.msg_bytes.Writeback_Data::0 55368 +system.ruby.network.routers0.msg_bytes.Writeback_Data::1 15696 +system.ruby.network.routers0.msg_bytes.Writeback_Control::0 264 +system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 44021 # Cumulative time (in ticks) in various power states +system.ruby.network.routers1.percent_links_utilized 20.738398 +system.ruby.network.routers1.msg_count.Control::0 1771 +system.ruby.network.routers1.msg_count.Request_Control::2 268 +system.ruby.network.routers1.msg_count.Response_Data::1 2546 +system.ruby.network.routers1.msg_count.Response_Control::1 1796 +system.ruby.network.routers1.msg_count.Response_Control::2 852 +system.ruby.network.routers1.msg_count.Writeback_Data::0 769 +system.ruby.network.routers1.msg_count.Writeback_Data::1 218 +system.ruby.network.routers1.msg_count.Writeback_Control::0 33 +system.ruby.network.routers1.msg_bytes.Control::0 14168 +system.ruby.network.routers1.msg_bytes.Request_Control::2 2144 +system.ruby.network.routers1.msg_bytes.Response_Data::1 183312 +system.ruby.network.routers1.msg_bytes.Response_Control::1 14368 +system.ruby.network.routers1.msg_bytes.Response_Control::2 6816 +system.ruby.network.routers1.msg_bytes.Writeback_Data::0 55368 +system.ruby.network.routers1.msg_bytes.Writeback_Data::1 15696 +system.ruby.network.routers1.msg_bytes.Writeback_Control::0 264 +system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 44021 # Cumulative time (in ticks) in various power states +system.ruby.network.routers2.percent_links_utilized 9.432430 +system.ruby.network.routers2.msg_count.Control::0 866 +system.ruby.network.routers2.msg_count.Response_Data::1 1645 +system.ruby.network.routers2.msg_count.Response_Control::1 943 +system.ruby.network.routers2.msg_bytes.Control::0 6928 +system.ruby.network.routers2.msg_bytes.Response_Data::1 118440 +system.ruby.network.routers2.msg_bytes.Response_Control::1 7544 +system.ruby.network.routers3.pwrStateResidencyTicks::UNDEFINED 44021 # Cumulative time (in ticks) in various power states +system.ruby.network.routers3.percent_links_utilized 13.825598 +system.ruby.network.routers3.msg_count.Control::0 1771 +system.ruby.network.routers3.msg_count.Request_Control::2 268 +system.ruby.network.routers3.msg_count.Response_Data::1 2546 +system.ruby.network.routers3.msg_count.Response_Control::1 1796 +system.ruby.network.routers3.msg_count.Response_Control::2 852 +system.ruby.network.routers3.msg_count.Writeback_Data::0 769 +system.ruby.network.routers3.msg_count.Writeback_Data::1 218 +system.ruby.network.routers3.msg_count.Writeback_Control::0 33 +system.ruby.network.routers3.msg_bytes.Control::0 14168 +system.ruby.network.routers3.msg_bytes.Request_Control::2 2144 +system.ruby.network.routers3.msg_bytes.Response_Data::1 183312 +system.ruby.network.routers3.msg_bytes.Response_Control::1 14368 +system.ruby.network.routers3.msg_bytes.Response_Control::2 6816 +system.ruby.network.routers3.msg_bytes.Writeback_Data::0 55368 +system.ruby.network.routers3.msg_bytes.Writeback_Data::1 15696 +system.ruby.network.routers3.msg_bytes.Writeback_Control::0 264 +system.ruby.network.pwrStateResidencyTicks::UNDEFINED 44021 # Cumulative time (in ticks) in various power states +system.ruby.network.msg_count.Control 5313 +system.ruby.network.msg_count.Request_Control 804 +system.ruby.network.msg_count.Response_Data 7639 +system.ruby.network.msg_count.Response_Control 7944 +system.ruby.network.msg_count.Writeback_Data 2961 +system.ruby.network.msg_count.Writeback_Control 99 +system.ruby.network.msg_byte.Control 42504 +system.ruby.network.msg_byte.Request_Control 6432 +system.ruby.network.msg_byte.Response_Data 550008 +system.ruby.network.msg_byte.Response_Control 63552 +system.ruby.network.msg_byte.Writeback_Data 213192 +system.ruby.network.msg_byte.Writeback_Control 792 +system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 44021 # Cumulative time (in ticks) in various power states +system.ruby.network.routers0.throttle0.link_utilization 10.437064 +system.ruby.network.routers0.throttle0.msg_count.Request_Control::2 268 +system.ruby.network.routers0.throttle0.msg_count.Response_Data::1 902 +system.ruby.network.routers0.throttle0.msg_count.Response_Control::1 803 +system.ruby.network.routers0.throttle0.msg_bytes.Request_Control::2 2144 +system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::1 64944 +system.ruby.network.routers0.throttle0.msg_bytes.Response_Control::1 6424 +system.ruby.network.routers0.throttle1.link_utilization 12.179414 +system.ruby.network.routers0.throttle1.msg_count.Control::0 905 +system.ruby.network.routers0.throttle1.msg_count.Response_Control::1 50 +system.ruby.network.routers0.throttle1.msg_count.Response_Control::2 852 +system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::0 769 +system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::1 218 +system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::0 33 +system.ruby.network.routers0.throttle1.msg_bytes.Control::0 7240 +system.ruby.network.routers0.throttle1.msg_bytes.Response_Control::1 400 +system.ruby.network.routers0.throttle1.msg_bytes.Response_Control::2 6816 +system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::0 55368 +system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::1 15696 +system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::0 264 +system.ruby.network.routers1.throttle0.link_utilization 21.989505 +system.ruby.network.routers1.throttle0.msg_count.Control::0 905 +system.ruby.network.routers1.throttle0.msg_count.Response_Data::1 864 +system.ruby.network.routers1.throttle0.msg_count.Response_Control::1 911 +system.ruby.network.routers1.throttle0.msg_count.Response_Control::2 852 +system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::0 769 +system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::1 218 +system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::0 33 +system.ruby.network.routers1.throttle0.msg_bytes.Control::0 7240 +system.ruby.network.routers1.throttle0.msg_bytes.Response_Data::1 62208 +system.ruby.network.routers1.throttle0.msg_bytes.Response_Control::1 7288 +system.ruby.network.routers1.throttle0.msg_bytes.Response_Control::2 6816 +system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::0 55368 +system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::1 15696 +system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::0 264 +system.ruby.network.routers1.throttle1.link_utilization 19.487290 +system.ruby.network.routers1.throttle1.msg_count.Control::0 866 +system.ruby.network.routers1.throttle1.msg_count.Request_Control::2 268 +system.ruby.network.routers1.throttle1.msg_count.Response_Data::1 1682 +system.ruby.network.routers1.throttle1.msg_count.Response_Control::1 885 +system.ruby.network.routers1.throttle1.msg_bytes.Control::0 6928 +system.ruby.network.routers1.throttle1.msg_bytes.Request_Control::2 2144 +system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::1 121104 +system.ruby.network.routers1.throttle1.msg_bytes.Response_Control::1 7080 +system.ruby.network.routers2.throttle0.link_utilization 9.050226 +system.ruby.network.routers2.throttle0.msg_count.Control::0 866 +system.ruby.network.routers2.throttle0.msg_count.Response_Data::1 780 +system.ruby.network.routers2.throttle0.msg_count.Response_Control::1 82 +system.ruby.network.routers2.throttle0.msg_bytes.Control::0 6928 +system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::1 56160 +system.ruby.network.routers2.throttle0.msg_bytes.Response_Control::1 656 +system.ruby.network.routers2.throttle1.link_utilization 9.814634 +system.ruby.network.routers2.throttle1.msg_count.Response_Data::1 865 +system.ruby.network.routers2.throttle1.msg_count.Response_Control::1 861 +system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::1 62280 +system.ruby.network.routers2.throttle1.msg_bytes.Response_Control::1 6888 +system.ruby.network.routers3.throttle0.link_utilization 10.437064 +system.ruby.network.routers3.throttle0.msg_count.Request_Control::2 268 +system.ruby.network.routers3.throttle0.msg_count.Response_Data::1 902 +system.ruby.network.routers3.throttle0.msg_count.Response_Control::1 803 +system.ruby.network.routers3.throttle0.msg_bytes.Request_Control::2 2144 +system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::1 64944 +system.ruby.network.routers3.throttle0.msg_bytes.Response_Control::1 6424 +system.ruby.network.routers3.throttle1.link_utilization 21.989505 +system.ruby.network.routers3.throttle1.msg_count.Control::0 905 +system.ruby.network.routers3.throttle1.msg_count.Response_Data::1 864 +system.ruby.network.routers3.throttle1.msg_count.Response_Control::1 911 +system.ruby.network.routers3.throttle1.msg_count.Response_Control::2 852 +system.ruby.network.routers3.throttle1.msg_count.Writeback_Data::0 769 +system.ruby.network.routers3.throttle1.msg_count.Writeback_Data::1 218 +system.ruby.network.routers3.throttle1.msg_count.Writeback_Control::0 33 +system.ruby.network.routers3.throttle1.msg_bytes.Control::0 7240 +system.ruby.network.routers3.throttle1.msg_bytes.Response_Data::1 62208 +system.ruby.network.routers3.throttle1.msg_bytes.Response_Control::1 7288 +system.ruby.network.routers3.throttle1.msg_bytes.Response_Control::2 6816 +system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::0 55368 +system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::1 15696 +system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::0 264 +system.ruby.network.routers3.throttle2.link_utilization 9.050226 +system.ruby.network.routers3.throttle2.msg_count.Control::0 866 +system.ruby.network.routers3.throttle2.msg_count.Response_Data::1 780 +system.ruby.network.routers3.throttle2.msg_count.Response_Control::1 82 +system.ruby.network.routers3.throttle2.msg_bytes.Control::0 6928 +system.ruby.network.routers3.throttle2.msg_bytes.Response_Data::1 56160 +system.ruby.network.routers3.throttle2.msg_bytes.Response_Control::1 656 system.ruby.delayVCHist.vnet_0::bucket_size 4 # delay histogram for vnet_0 system.ruby.delayVCHist.vnet_0::max_bucket 39 # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0::samples 2620 # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0::mean 5.712977 # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0::stdev 7.142048 # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0 | 1406 53.66% 53.66% | 9 0.34% 54.01% | 823 31.41% 85.42% | 4 0.15% 85.57% | 323 12.33% 97.90% | 5 0.19% 98.09% | 0 0.00% 98.09% | 43 1.64% 99.73% | 0 0.00% 99.73% | 7 0.27% 100.00% # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0::total 2620 # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_1::bucket_size 4 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::max_bucket 39 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::samples 3822 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::mean 0.787023 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::stdev 2.428600 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1 | 3460 90.53% 90.53% | 42 1.10% 91.63% | 315 8.24% 99.87% | 4 0.10% 99.97% | 0 0.00% 99.97% | 1 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::total 3822 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_0::samples 2559 # delay histogram for vnet_0 +system.ruby.delayVCHist.vnet_0::mean 5.696757 # delay histogram for vnet_0 +system.ruby.delayVCHist.vnet_0::stdev 7.319490 # delay histogram for vnet_0 +system.ruby.delayVCHist.vnet_0 | 1396 54.55% 54.55% | 8 0.31% 54.87% | 792 30.95% 85.81% | 2 0.08% 85.89% | 285 11.14% 97.03% | 1 0.04% 97.07% | 1 0.04% 97.11% | 70 2.74% 99.84% | 0 0.00% 99.84% | 4 0.16% 100.00% # delay histogram for vnet_0 +system.ruby.delayVCHist.vnet_0::total 2559 # delay histogram for vnet_0 +system.ruby.delayVCHist.vnet_1::bucket_size 2 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::max_bucket 19 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::samples 3698 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::mean 0.702001 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::stdev 2.286109 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1 | 3361 90.89% 90.89% | 15 0.41% 91.29% | 10 0.27% 91.56% | 43 1.16% 92.73% | 218 5.90% 98.62% | 46 1.24% 99.86% | 3 0.08% 99.95% | 2 0.05% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::total 3698 # delay histogram for vnet_1 system.ruby.delayVCHist.vnet_2::bucket_size 1 # delay histogram for vnet_2 system.ruby.delayVCHist.vnet_2::max_bucket 9 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::samples 278 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2 | 278 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::total 278 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::samples 268 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2 | 268 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::total 268 # delay histogram for vnet_2 system.ruby.LD.latency_hist_seqr::bucket_size 128 system.ruby.LD.latency_hist_seqr::max_bucket 1279 -system.ruby.LD.latency_hist_seqr::samples 37 -system.ruby.LD.latency_hist_seqr::mean 621.135135 -system.ruby.LD.latency_hist_seqr::gmean 207.168110 -system.ruby.LD.latency_hist_seqr::stdev 333.448910 -system.ruby.LD.latency_hist_seqr | 8 21.62% 21.62% | 0 0.00% 21.62% | 0 0.00% 21.62% | 0 0.00% 21.62% | 0 0.00% 21.62% | 13 35.14% 56.76% | 14 37.84% 94.59% | 2 5.41% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.latency_hist_seqr::total 37 +system.ruby.LD.latency_hist_seqr::samples 50 +system.ruby.LD.latency_hist_seqr::mean 631.160000 +system.ruby.LD.latency_hist_seqr::gmean 197.121649 +system.ruby.LD.latency_hist_seqr::stdev 346.030868 +system.ruby.LD.latency_hist_seqr | 11 22.00% 22.00% | 0 0.00% 22.00% | 0 0.00% 22.00% | 0 0.00% 22.00% | 1 2.00% 24.00% | 12 24.00% 48.00% | 21 42.00% 90.00% | 5 10.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.latency_hist_seqr::total 50 system.ruby.LD.hit_latency_hist_seqr::bucket_size 1 system.ruby.LD.hit_latency_hist_seqr::max_bucket 9 -system.ruby.LD.hit_latency_hist_seqr::samples 7 +system.ruby.LD.hit_latency_hist_seqr::samples 10 system.ruby.LD.hit_latency_hist_seqr::mean 1 system.ruby.LD.hit_latency_hist_seqr::gmean 1 -system.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 7 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.hit_latency_hist_seqr::total 7 +system.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 10 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.hit_latency_hist_seqr::total 10 system.ruby.LD.miss_latency_hist_seqr::bucket_size 128 system.ruby.LD.miss_latency_hist_seqr::max_bucket 1279 -system.ruby.LD.miss_latency_hist_seqr::samples 30 -system.ruby.LD.miss_latency_hist_seqr::mean 765.833333 -system.ruby.LD.miss_latency_hist_seqr::gmean 719.114834 -system.ruby.LD.miss_latency_hist_seqr::stdev 153.429099 -system.ruby.LD.miss_latency_hist_seqr | 1 3.33% 3.33% | 0 0.00% 3.33% | 0 0.00% 3.33% | 0 0.00% 3.33% | 0 0.00% 3.33% | 13 43.33% 46.67% | 14 46.67% 93.33% | 2 6.67% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.miss_latency_hist_seqr::total 30 +system.ruby.LD.miss_latency_hist_seqr::samples 40 +system.ruby.LD.miss_latency_hist_seqr::mean 788.700000 +system.ruby.LD.miss_latency_hist_seqr::gmean 738.614626 +system.ruby.LD.miss_latency_hist_seqr::stdev 152.194242 +system.ruby.LD.miss_latency_hist_seqr | 1 2.50% 2.50% | 0 0.00% 2.50% | 0 0.00% 2.50% | 0 0.00% 2.50% | 1 2.50% 5.00% | 12 30.00% 35.00% | 21 52.50% 87.50% | 5 12.50% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.miss_latency_hist_seqr::total 40 system.ruby.ST.latency_hist_seqr::bucket_size 128 system.ruby.ST.latency_hist_seqr::max_bucket 1279 -system.ruby.ST.latency_hist_seqr::samples 925 -system.ruby.ST.latency_hist_seqr::mean 697.631351 -system.ruby.ST.latency_hist_seqr::gmean 404.802159 -system.ruby.ST.latency_hist_seqr::stdev 266.794551 -system.ruby.ST.latency_hist_seqr | 101 10.92% 10.92% | 7 0.76% 11.68% | 4 0.43% 12.11% | 4 0.43% 12.54% | 32 3.46% 16.00% | 289 31.24% 47.24% | 404 43.68% 90.92% | 47 5.08% 96.00% | 28 3.03% 99.03% | 9 0.97% 100.00% -system.ruby.ST.latency_hist_seqr::total 925 +system.ruby.ST.latency_hist_seqr::samples 904 +system.ruby.ST.latency_hist_seqr::mean 719.136062 +system.ruby.ST.latency_hist_seqr::gmean 383.374715 +system.ruby.ST.latency_hist_seqr::stdev 298.133155 +system.ruby.ST.latency_hist_seqr | 114 12.61% 12.61% | 8 0.88% 13.50% | 4 0.44% 13.94% | 3 0.33% 14.27% | 5 0.55% 14.82% | 251 27.77% 42.59% | 346 38.27% 80.86% | 108 11.95% 92.81% | 53 5.86% 98.67% | 12 1.33% 100.00% +system.ruby.ST.latency_hist_seqr::total 904 system.ruby.ST.hit_latency_hist_seqr::bucket_size 1 system.ruby.ST.hit_latency_hist_seqr::max_bucket 9 -system.ruby.ST.hit_latency_hist_seqr::samples 82 +system.ruby.ST.hit_latency_hist_seqr::samples 91 system.ruby.ST.hit_latency_hist_seqr::mean 1 system.ruby.ST.hit_latency_hist_seqr::gmean 1 -system.ruby.ST.hit_latency_hist_seqr | 0 0.00% 0.00% | 82 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.hit_latency_hist_seqr::total 82 +system.ruby.ST.hit_latency_hist_seqr | 0 0.00% 0.00% | 91 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.hit_latency_hist_seqr::total 91 system.ruby.ST.miss_latency_hist_seqr::bucket_size 128 system.ruby.ST.miss_latency_hist_seqr::max_bucket 1279 -system.ruby.ST.miss_latency_hist_seqr::samples 843 -system.ruby.ST.miss_latency_hist_seqr::mean 765.393832 -system.ruby.ST.miss_latency_hist_seqr::gmean 725.861277 -system.ruby.ST.miss_latency_hist_seqr::stdev 162.026380 -system.ruby.ST.miss_latency_hist_seqr | 19 2.25% 2.25% | 7 0.83% 3.08% | 4 0.47% 3.56% | 4 0.47% 4.03% | 32 3.80% 7.83% | 289 34.28% 42.11% | 404 47.92% 90.04% | 47 5.58% 95.61% | 28 3.32% 98.93% | 9 1.07% 100.00% -system.ruby.ST.miss_latency_hist_seqr::total 843 -system.ruby.IFETCH.latency_hist_seqr::bucket_size 64 -system.ruby.IFETCH.latency_hist_seqr::max_bucket 639 -system.ruby.IFETCH.latency_hist_seqr::samples 63 -system.ruby.IFETCH.latency_hist_seqr::mean 107.476190 -system.ruby.IFETCH.latency_hist_seqr::gmean 95.146533 -system.ruby.IFETCH.latency_hist_seqr::stdev 52.448702 -system.ruby.IFETCH.latency_hist_seqr | 11 17.46% 17.46% | 34 53.97% 71.43% | 15 23.81% 95.24% | 2 3.17% 98.41% | 0 0.00% 98.41% | 1 1.59% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.latency_hist_seqr::total 63 -system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 64 -system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 639 -system.ruby.IFETCH.miss_latency_hist_seqr::samples 63 -system.ruby.IFETCH.miss_latency_hist_seqr::mean 107.476190 -system.ruby.IFETCH.miss_latency_hist_seqr::gmean 95.146533 -system.ruby.IFETCH.miss_latency_hist_seqr::stdev 52.448702 -system.ruby.IFETCH.miss_latency_hist_seqr | 11 17.46% 17.46% | 34 53.97% 71.43% | 15 23.81% 95.24% | 2 3.17% 98.41% | 0 0.00% 98.41% | 1 1.59% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.miss_latency_hist_seqr::total 63 -system.ruby.Directory_Controller.Fetch 902 0.00% 0.00% -system.ruby.Directory_Controller.Data 811 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 902 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 811 0.00% 0.00% -system.ruby.Directory_Controller.CleanReplacement 87 0.00% 0.00% -system.ruby.Directory_Controller.I.Fetch 902 0.00% 0.00% -system.ruby.Directory_Controller.M.Data 811 0.00% 0.00% -system.ruby.Directory_Controller.M.CleanReplacement 87 0.00% 0.00% -system.ruby.Directory_Controller.IM.Memory_Data 902 0.00% 0.00% -system.ruby.Directory_Controller.MI.Memory_Ack 811 0.00% 0.00% -system.ruby.L1Cache_Controller.Load 37 0.00% 0.00% -system.ruby.L1Cache_Controller.Ifetch 67 0.00% 0.00% -system.ruby.L1Cache_Controller.Store 927 0.00% 0.00% -system.ruby.L1Cache_Controller.Inv 278 0.00% 0.00% -system.ruby.L1Cache_Controller.L1_Replacement 12331 0.00% 0.00% -system.ruby.L1Cache_Controller.Data_Exclusive 30 0.00% 0.00% -system.ruby.L1Cache_Controller.Data_all_Acks 906 0.00% 0.00% -system.ruby.L1Cache_Controller.WB_Ack 808 0.00% 0.00% -system.ruby.L1Cache_Controller.NP.Load 30 0.00% 0.00% -system.ruby.L1Cache_Controller.NP.Ifetch 64 0.00% 0.00% -system.ruby.L1Cache_Controller.NP.Store 845 0.00% 0.00% -system.ruby.L1Cache_Controller.I.L1_Replacement 121 0.00% 0.00% -system.ruby.L1Cache_Controller.S.Inv 54 0.00% 0.00% -system.ruby.L1Cache_Controller.S.L1_Replacement 3 0.00% 0.00% -system.ruby.L1Cache_Controller.E.Inv 5 0.00% 0.00% -system.ruby.L1Cache_Controller.E.L1_Replacement 25 0.00% 0.00% -system.ruby.L1Cache_Controller.M.Load 7 0.00% 0.00% -system.ruby.L1Cache_Controller.M.Store 82 0.00% 0.00% -system.ruby.L1Cache_Controller.M.Inv 57 0.00% 0.00% -system.ruby.L1Cache_Controller.M.L1_Replacement 785 0.00% 0.00% -system.ruby.L1Cache_Controller.IS.Inv 6 0.00% 0.00% -system.ruby.L1Cache_Controller.IS.L1_Replacement 386 0.00% 0.00% -system.ruby.L1Cache_Controller.IS.Data_Exclusive 30 0.00% 0.00% -system.ruby.L1Cache_Controller.IS.Data_all_Acks 57 0.00% 0.00% -system.ruby.L1Cache_Controller.IM.L1_Replacement 11011 0.00% 0.00% -system.ruby.L1Cache_Controller.IM.Data_all_Acks 843 0.00% 0.00% -system.ruby.L1Cache_Controller.IS_I.Data_all_Acks 6 0.00% 0.00% -system.ruby.L1Cache_Controller.M_I.Ifetch 3 0.00% 0.00% -system.ruby.L1Cache_Controller.M_I.Inv 156 0.00% 0.00% -system.ruby.L1Cache_Controller.M_I.WB_Ack 652 0.00% 0.00% -system.ruby.L1Cache_Controller.SINK_WB_ACK.WB_Ack 156 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_GET_INSTR 64 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_GETS 30 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_GETX 844 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_PUTX 653 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_PUTX_old 267 0.00% 0.00% -system.ruby.L2Cache_Controller.L2_Replacement 603 0.00% 0.00% -system.ruby.L2Cache_Controller.L2_Replacement_clean 569 0.00% 0.00% -system.ruby.L2Cache_Controller.Mem_Data 902 0.00% 0.00% -system.ruby.L2Cache_Controller.Mem_Ack 898 0.00% 0.00% -system.ruby.L2Cache_Controller.WB_Data 208 0.00% 0.00% -system.ruby.L2Cache_Controller.WB_Data_clean 5 0.00% 0.00% -system.ruby.L2Cache_Controller.Ack_all 65 0.00% 0.00% -system.ruby.L2Cache_Controller.Exclusive_Unblock 873 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.L1_GET_INSTR 61 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.L1_GETS 29 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.L1_GETX 814 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.L1_PUTX_old 134 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.L1_GETX 3 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.L2_Replacement_clean 60 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L1_GET_INSTR 3 0.00% 0.00% +system.ruby.ST.miss_latency_hist_seqr::samples 813 +system.ruby.ST.miss_latency_hist_seqr::mean 799.517835 +system.ruby.ST.miss_latency_hist_seqr::gmean 746.124556 +system.ruby.ST.miss_latency_hist_seqr::stdev 185.954617 +system.ruby.ST.miss_latency_hist_seqr | 23 2.83% 2.83% | 8 0.98% 3.81% | 4 0.49% 4.31% | 3 0.37% 4.67% | 5 0.62% 5.29% | 251 30.87% 36.16% | 346 42.56% 78.72% | 108 13.28% 92.00% | 53 6.52% 98.52% | 12 1.48% 100.00% +system.ruby.ST.miss_latency_hist_seqr::total 813 +system.ruby.IFETCH.latency_hist_seqr::bucket_size 32 +system.ruby.IFETCH.latency_hist_seqr::max_bucket 319 +system.ruby.IFETCH.latency_hist_seqr::samples 50 +system.ruby.IFETCH.latency_hist_seqr::mean 110.700000 +system.ruby.IFETCH.latency_hist_seqr::gmean 96.182985 +system.ruby.IFETCH.latency_hist_seqr::stdev 52.466607 +system.ruby.IFETCH.latency_hist_seqr | 1 2.00% 2.00% | 9 18.00% 20.00% | 11 22.00% 42.00% | 9 18.00% 60.00% | 13 26.00% 86.00% | 5 10.00% 96.00% | 0 0.00% 96.00% | 2 4.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.latency_hist_seqr::total 50 +system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 32 +system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 319 +system.ruby.IFETCH.miss_latency_hist_seqr::samples 50 +system.ruby.IFETCH.miss_latency_hist_seqr::mean 110.700000 +system.ruby.IFETCH.miss_latency_hist_seqr::gmean 96.182985 +system.ruby.IFETCH.miss_latency_hist_seqr::stdev 52.466607 +system.ruby.IFETCH.miss_latency_hist_seqr | 1 2.00% 2.00% | 9 18.00% 20.00% | 11 22.00% 42.00% | 9 18.00% 60.00% | 13 26.00% 86.00% | 5 10.00% 96.00% | 0 0.00% 96.00% | 2 4.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.miss_latency_hist_seqr::total 50 +system.ruby.Directory_Controller.Fetch 866 0.00% 0.00% +system.ruby.Directory_Controller.Data 780 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 865 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 779 0.00% 0.00% +system.ruby.Directory_Controller.CleanReplacement 82 0.00% 0.00% +system.ruby.Directory_Controller.I.Fetch 866 0.00% 0.00% +system.ruby.Directory_Controller.M.Data 780 0.00% 0.00% +system.ruby.Directory_Controller.M.CleanReplacement 82 0.00% 0.00% +system.ruby.Directory_Controller.IM.Memory_Data 865 0.00% 0.00% +system.ruby.Directory_Controller.MI.Memory_Ack 779 0.00% 0.00% +system.ruby.L1Cache_Controller.Load 51 0.00% 0.00% +system.ruby.L1Cache_Controller.Ifetch 55 0.00% 0.00% +system.ruby.L1Cache_Controller.Store 905 0.00% 0.00% +system.ruby.L1Cache_Controller.Inv 268 0.00% 0.00% +system.ruby.L1Cache_Controller.L1_Replacement 11918 0.00% 0.00% +system.ruby.L1Cache_Controller.Data_Exclusive 39 0.00% 0.00% +system.ruby.L1Cache_Controller.Data_all_Acks 863 0.00% 0.00% +system.ruby.L1Cache_Controller.Ack_all 1 0.00% 0.00% +system.ruby.L1Cache_Controller.WB_Ack 802 0.00% 0.00% +system.ruby.L1Cache_Controller.NP.Load 41 0.00% 0.00% +system.ruby.L1Cache_Controller.NP.Ifetch 50 0.00% 0.00% +system.ruby.L1Cache_Controller.NP.Store 813 0.00% 0.00% +system.ruby.L1Cache_Controller.I.L1_Replacement 92 0.00% 0.00% +system.ruby.L1Cache_Controller.S.Store 1 0.00% 0.00% +system.ruby.L1Cache_Controller.S.Inv 37 0.00% 0.00% +system.ruby.L1Cache_Controller.S.L1_Replacement 5 0.00% 0.00% +system.ruby.L1Cache_Controller.E.Inv 6 0.00% 0.00% +system.ruby.L1Cache_Controller.E.L1_Replacement 33 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Load 10 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Store 91 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Inv 43 0.00% 0.00% +system.ruby.L1Cache_Controller.M.L1_Replacement 769 0.00% 0.00% +system.ruby.L1Cache_Controller.IS.Inv 7 0.00% 0.00% +system.ruby.L1Cache_Controller.IS.L1_Replacement 452 0.00% 0.00% +system.ruby.L1Cache_Controller.IS.Data_Exclusive 39 0.00% 0.00% +system.ruby.L1Cache_Controller.IS.Data_all_Acks 44 0.00% 0.00% +system.ruby.L1Cache_Controller.IM.L1_Replacement 10567 0.00% 0.00% +system.ruby.L1Cache_Controller.IM.Data_all_Acks 812 0.00% 0.00% +system.ruby.L1Cache_Controller.SM.Ack_all 1 0.00% 0.00% +system.ruby.L1Cache_Controller.IS_I.Data_all_Acks 7 0.00% 0.00% +system.ruby.L1Cache_Controller.M_I.Ifetch 5 0.00% 0.00% +system.ruby.L1Cache_Controller.M_I.Inv 175 0.00% 0.00% +system.ruby.L1Cache_Controller.M_I.WB_Ack 627 0.00% 0.00% +system.ruby.L1Cache_Controller.SINK_WB_ACK.WB_Ack 175 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_GET_INSTR 50 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_GETS 41 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_GETX 813 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_UPGRADE 1 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_PUTX 627 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_PUTX_old 314 0.00% 0.00% +system.ruby.L2Cache_Controller.L2_Replacement 568 0.00% 0.00% +system.ruby.L2Cache_Controller.L2_Replacement_clean 551 0.00% 0.00% +system.ruby.L2Cache_Controller.Mem_Data 864 0.00% 0.00% +system.ruby.L2Cache_Controller.Mem_Ack 861 0.00% 0.00% +system.ruby.L2Cache_Controller.WB_Data 212 0.00% 0.00% +system.ruby.L2Cache_Controller.WB_Data_clean 6 0.00% 0.00% +system.ruby.L2Cache_Controller.Ack_all 50 0.00% 0.00% +system.ruby.L2Cache_Controller.Exclusive_Unblock 852 0.00% 0.00% +system.ruby.L2Cache_Controller.NP.L1_GET_INSTR 44 0.00% 0.00% +system.ruby.L2Cache_Controller.NP.L1_GETS 39 0.00% 0.00% +system.ruby.L2Cache_Controller.NP.L1_GETX 783 0.00% 0.00% +system.ruby.L2Cache_Controller.NP.L1_PUTX_old 163 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.L1_GETS 1 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.L1_GETX 4 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.L1_UPGRADE 1 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.L2_Replacement_clean 44 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L1_GET_INSTR 6 0.00% 0.00% system.ruby.L2Cache_Controller.M.L1_GETS 1 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L1_GETX 27 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L2_Replacement 603 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L2_Replacement_clean 18 0.00% 0.00% -system.ruby.L2Cache_Controller.MT.L1_PUTX 653 0.00% 0.00% -system.ruby.L2Cache_Controller.MT.L2_Replacement_clean 219 0.00% 0.00% -system.ruby.L2Cache_Controller.M_I.L1_PUTX_old 22 0.00% 0.00% -system.ruby.L2Cache_Controller.M_I.Mem_Ack 898 0.00% 0.00% -system.ruby.L2Cache_Controller.MCT_I.L1_PUTX_old 111 0.00% 0.00% -system.ruby.L2Cache_Controller.MCT_I.WB_Data 208 0.00% 0.00% -system.ruby.L2Cache_Controller.MCT_I.WB_Data_clean 5 0.00% 0.00% -system.ruby.L2Cache_Controller.MCT_I.Ack_all 5 0.00% 0.00% -system.ruby.L2Cache_Controller.I_I.Ack_all 60 0.00% 0.00% -system.ruby.L2Cache_Controller.ISS.L2_Replacement_clean 6 0.00% 0.00% -system.ruby.L2Cache_Controller.ISS.Mem_Data 29 0.00% 0.00% -system.ruby.L2Cache_Controller.IS.L2_Replacement_clean 121 0.00% 0.00% -system.ruby.L2Cache_Controller.IS.Mem_Data 60 0.00% 0.00% -system.ruby.L2Cache_Controller.IM.L2_Replacement_clean 125 0.00% 0.00% -system.ruby.L2Cache_Controller.IM.Mem_Data 813 0.00% 0.00% -system.ruby.L2Cache_Controller.SS_MB.Exclusive_Unblock 3 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_MB.L2_Replacement_clean 20 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_MB.Exclusive_Unblock 870 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L1_GETX 26 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L2_Replacement 568 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L2_Replacement_clean 26 0.00% 0.00% +system.ruby.L2Cache_Controller.MT.L1_PUTX 627 0.00% 0.00% +system.ruby.L2Cache_Controller.MT.L2_Replacement_clean 224 0.00% 0.00% +system.ruby.L2Cache_Controller.M_I.L1_PUTX_old 12 0.00% 0.00% +system.ruby.L2Cache_Controller.M_I.Mem_Ack 861 0.00% 0.00% +system.ruby.L2Cache_Controller.MCT_I.L1_PUTX_old 139 0.00% 0.00% +system.ruby.L2Cache_Controller.MCT_I.WB_Data 212 0.00% 0.00% +system.ruby.L2Cache_Controller.MCT_I.WB_Data_clean 6 0.00% 0.00% +system.ruby.L2Cache_Controller.MCT_I.Ack_all 6 0.00% 0.00% +system.ruby.L2Cache_Controller.I_I.Ack_all 44 0.00% 0.00% +system.ruby.L2Cache_Controller.ISS.L2_Replacement_clean 3 0.00% 0.00% +system.ruby.L2Cache_Controller.ISS.Mem_Data 38 0.00% 0.00% +system.ruby.L2Cache_Controller.IS.L2_Replacement_clean 96 0.00% 0.00% +system.ruby.L2Cache_Controller.IS.Mem_Data 44 0.00% 0.00% +system.ruby.L2Cache_Controller.IM.L2_Replacement_clean 132 0.00% 0.00% +system.ruby.L2Cache_Controller.IM.Mem_Data 782 0.00% 0.00% +system.ruby.L2Cache_Controller.SS_MB.Exclusive_Unblock 5 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_MB.L2_Replacement_clean 26 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_MB.Exclusive_Unblock 847 0.00% 0.00% ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/config.ini b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/config.ini index 41e35786f..fd5963bf9 100644 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/config.ini +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/config.ini @@ -14,6 +14,7 @@ children=clk_domain cpu dvfs_handler mem_ctrls ruby sys_port_proxy voltage_domai boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 exit_on_work_items=false init_param=0 @@ -22,11 +23,15 @@ kernel_addr_check=true load_addr_mask=1099511627775 load_offset=0 mem_mode=timing -mem_ranges=0:268435455 +mem_ranges=0:268435455:0:0:0:0 memories=system.mem_ctrls mmap_using_noreserve=false multi_thread=false num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null readfile= symbolfile= thermal_components= @@ -54,8 +59,13 @@ check_flush=false checks_to_complete=100 clk_domain=system.clk_domain deadlock_threshold=50000 +default_p_state=UNDEFINED eventq_index=0 num_cpus=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null system=system wakeup_frequency=10 cpuInstDataPort=system.ruby.l1_cntrl0.sequencer.slave[0] @@ -70,27 +80,27 @@ transition_latency=100000 [system.mem_ctrls] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -102,6 +112,7 @@ burst_length=8 channels=1 clk_domain=system.clk_domain conf_table_reported=true +default_p_state=UNDEFINED device_bus_width=8 device_rowbuffer_size=1024 device_size=536870912 @@ -109,12 +120,17 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 page_policy=open_adaptive -range=0:268435455 +power_model=Null +range=0:268435455:5:19:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10 @@ -136,9 +152,9 @@ tRTW=3 tWR=15 tWTR=8 tXAW=30 -tXP=0 +tXP=6 tXPDLL=0 -tXS=0 +tXS=270 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 @@ -152,12 +168,17 @@ access_backing_store=false all_instructions=false block_size_bytes=64 clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED eventq_index=0 hot_lines=false memory_size_bits=48 num_of_sequencers=1 number_of_virtual_networks=3 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 phys_mem=Null +power_model=Null randomization=true [system.ruby.clk_domain] @@ -174,11 +195,16 @@ children=directory forwardFromDir requestToDir responseFromDir responseFromMemor buffer_size=0 clk_domain=system.ruby.clk_domain cluster_id=0 +default_p_state=UNDEFINED directory=system.ruby.dir_cntrl0.directory directory_latency=6 eventq_index=0 forwardFromDir=system.ruby.dir_cntrl0.forwardFromDir number_of_TBEs=256 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null recycle_latency=10 requestToDir=system.ruby.dir_cntrl0.requestToDir responseFromDir=system.ruby.dir_cntrl0.responseFromDir @@ -245,10 +271,15 @@ L1Icache=system.ruby.l1_cntrl0.L1Icache buffer_size=0 clk_domain=system.ruby.clk_domain cluster_id=0 +default_p_state=UNDEFINED eventq_index=0 l2_select_num_bits=0 mandatoryQueue=system.ruby.l1_cntrl0.mandatoryQueue number_of_TBEs=256 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null recycle_latency=10 requestFromL1Cache=system.ruby.l1_cntrl0.requestFromL1Cache requestToL1Cache=system.ruby.l1_cntrl0.requestToL1Cache @@ -358,17 +389,22 @@ coreid=99 dcache=system.ruby.l1_cntrl0.L1Dcache dcache_hit_latency=1 deadlock_threshold=500000 +default_p_state=UNDEFINED eventq_index=0 +garnet_standalone=false icache=system.ruby.l1_cntrl0.L1Icache icache_hit_latency=1 is_cpu_sequencer=true max_outstanding_requests=16 no_retry_on_stall=true +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null ruby_system=system.ruby support_data_reqs=true support_inst_reqs=true system=system -using_network_tester=false using_ruby_tester=true version=0 slave=system.cpu.cpuInstDataPort[0] @@ -391,8 +427,13 @@ L2cache=system.ruby.l2_cntrl0.L2cache buffer_size=0 clk_domain=system.ruby.clk_domain cluster_id=0 +default_p_state=UNDEFINED eventq_index=0 number_of_TBEs=256 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null recycle_latency=10 request_latency=2 responseFromL2Cache=system.ruby.l2_cntrl0.responseFromL2Cache @@ -491,18 +532,23 @@ eventq_index=0 [system.ruby.network] type=SimpleNetwork -children=ext_links0 ext_links1 ext_links2 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_links0 int_links1 int_links2 routers0 routers1 routers2 routers3 +children=ext_links0 ext_links1 ext_links2 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_link_buffers20 int_link_buffers21 int_link_buffers22 int_link_buffers23 int_link_buffers24 int_link_buffers25 int_link_buffers26 int_link_buffers27 int_link_buffers28 int_link_buffers29 int_link_buffers30 int_link_buffers31 int_link_buffers32 int_link_buffers33 int_link_buffers34 int_link_buffers35 int_links0 int_links1 int_links2 int_links3 int_links4 int_links5 routers0 routers1 routers2 routers3 adaptive_routing=false buffer_size=0 clk_domain=system.ruby.clk_domain control_msg_size=8 +default_p_state=UNDEFINED endpoint_bandwidth=1000 eventq_index=0 ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1 system.ruby.network.ext_links2 -int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 -int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2 +int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19 system.ruby.network.int_link_buffers20 system.ruby.network.int_link_buffers21 system.ruby.network.int_link_buffers22 system.ruby.network.int_link_buffers23 system.ruby.network.int_link_buffers24 system.ruby.network.int_link_buffers25 system.ruby.network.int_link_buffers26 system.ruby.network.int_link_buffers27 system.ruby.network.int_link_buffers28 system.ruby.network.int_link_buffers29 system.ruby.network.int_link_buffers30 system.ruby.network.int_link_buffers31 system.ruby.network.int_link_buffers32 system.ruby.network.int_link_buffers33 system.ruby.network.int_link_buffers34 system.ruby.network.int_link_buffers35 +int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2 system.ruby.network.int_links3 system.ruby.network.int_links4 system.ruby.network.int_links5 netifs= number_of_virtual_networks=3 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null routers=system.ruby.network.routers0 system.ruby.network.routers1 system.ruby.network.routers2 system.ruby.network.routers3 ruby_system=system.ruby topology=Crossbar @@ -665,42 +711,216 @@ eventq_index=0 ordered=true randomization=false +[system.ruby.network.int_link_buffers18] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers19] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers20] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers21] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers22] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers23] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers24] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers25] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers26] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers27] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers28] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers29] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers30] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers31] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers32] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers33] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers34] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers35] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + [system.ruby.network.int_links0] type=SimpleIntLink bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers3 eventq_index=0 latency=1 link_id=3 -node_a=system.ruby.network.routers0 -node_b=system.ruby.network.routers3 +src_node=system.ruby.network.routers0 +src_outport= weight=1 [system.ruby.network.int_links1] type=SimpleIntLink bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers3 eventq_index=0 latency=1 link_id=4 -node_a=system.ruby.network.routers1 -node_b=system.ruby.network.routers3 +src_node=system.ruby.network.routers1 +src_outport= weight=1 [system.ruby.network.int_links2] type=SimpleIntLink bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers3 eventq_index=0 latency=1 link_id=5 -node_a=system.ruby.network.routers2 -node_b=system.ruby.network.routers3 +src_node=system.ruby.network.routers2 +src_outport= +weight=1 + +[system.ruby.network.int_links3] +type=SimpleIntLink +bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers0 +eventq_index=0 +latency=1 +link_id=6 +src_node=system.ruby.network.routers3 +src_outport= +weight=1 + +[system.ruby.network.int_links4] +type=SimpleIntLink +bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers1 +eventq_index=0 +latency=1 +link_id=7 +src_node=system.ruby.network.routers3 +src_outport= +weight=1 + +[system.ruby.network.int_links5] +type=SimpleIntLink +bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers2 +eventq_index=0 +latency=1 +link_id=8 +src_node=system.ruby.network.routers3 +src_outport= weight=1 [system.ruby.network.routers0] type=Switch children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED eventq_index=0 +latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 port_buffers=system.ruby.network.routers0.port_buffers00 system.ruby.network.routers0.port_buffers01 system.ruby.network.routers0.port_buffers02 system.ruby.network.routers0.port_buffers03 system.ruby.network.routers0.port_buffers04 system.ruby.network.routers0.port_buffers05 system.ruby.network.routers0.port_buffers06 system.ruby.network.routers0.port_buffers07 system.ruby.network.routers0.port_buffers08 system.ruby.network.routers0.port_buffers09 system.ruby.network.routers0.port_buffers10 system.ruby.network.routers0.port_buffers11 +power_model=Null router_id=0 virt_nets=3 @@ -792,8 +1012,14 @@ randomization=false type=Switch children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED eventq_index=0 +latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 port_buffers=system.ruby.network.routers1.port_buffers00 system.ruby.network.routers1.port_buffers01 system.ruby.network.routers1.port_buffers02 system.ruby.network.routers1.port_buffers03 system.ruby.network.routers1.port_buffers04 system.ruby.network.routers1.port_buffers05 system.ruby.network.routers1.port_buffers06 system.ruby.network.routers1.port_buffers07 system.ruby.network.routers1.port_buffers08 system.ruby.network.routers1.port_buffers09 system.ruby.network.routers1.port_buffers10 system.ruby.network.routers1.port_buffers11 +power_model=Null router_id=1 virt_nets=3 @@ -885,8 +1111,14 @@ randomization=false type=Switch children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED eventq_index=0 +latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 port_buffers=system.ruby.network.routers2.port_buffers00 system.ruby.network.routers2.port_buffers01 system.ruby.network.routers2.port_buffers02 system.ruby.network.routers2.port_buffers03 system.ruby.network.routers2.port_buffers04 system.ruby.network.routers2.port_buffers05 system.ruby.network.routers2.port_buffers06 system.ruby.network.routers2.port_buffers07 system.ruby.network.routers2.port_buffers08 system.ruby.network.routers2.port_buffers09 system.ruby.network.routers2.port_buffers10 system.ruby.network.routers2.port_buffers11 +power_model=Null router_id=2 virt_nets=3 @@ -978,8 +1210,14 @@ randomization=false type=Switch children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17 clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED eventq_index=0 +latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 port_buffers=system.ruby.network.routers3.port_buffers00 system.ruby.network.routers3.port_buffers01 system.ruby.network.routers3.port_buffers02 system.ruby.network.routers3.port_buffers03 system.ruby.network.routers3.port_buffers04 system.ruby.network.routers3.port_buffers05 system.ruby.network.routers3.port_buffers06 system.ruby.network.routers3.port_buffers07 system.ruby.network.routers3.port_buffers08 system.ruby.network.routers3.port_buffers09 system.ruby.network.routers3.port_buffers10 system.ruby.network.routers3.port_buffers11 system.ruby.network.routers3.port_buffers12 system.ruby.network.routers3.port_buffers13 system.ruby.network.routers3.port_buffers14 system.ruby.network.routers3.port_buffers15 system.ruby.network.routers3.port_buffers16 system.ruby.network.routers3.port_buffers17 +power_model=Null router_id=3 virt_nets=3 @@ -1112,9 +1350,14 @@ randomization=false [system.sys_port_proxy] type=RubyPortProxy clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 is_cpu_sequencer=true no_retry_on_stall=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null ruby_system=system.ruby support_data_reqs=true support_inst_reqs=true diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simerr b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simerr index c2086c0ba..cee0dfc57 100755 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simerr +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simerr @@ -4,7 +4,5 @@ warn: rounding error > tolerance 1.250000 rounded to 1 warn: rounding error > tolerance 1.250000 rounded to 1 -warn: rounding error > tolerance - 1.250000 rounded to 1 warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes) warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files! diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simout b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simout index bb50cd40f..354aa7d14 100755 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simout +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simout @@ -1,11 +1,13 @@ +Redirecting stdout to build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simout +Redirecting stderr to build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 21 2016 14:06:59 -gem5 started Jan 21 2016 14:07:35 -gem5 executing on zizzer, pid 50073 -command line: build/ALPHA_MOESI_CMP_directory/gem5.opt -d build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_directory -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_directory +gem5 compiled Oct 13 2016 20:30:58 +gem5 started Oct 13 2016 20:31:25 +gem5 executing on e108600-lin, pid 17788 +command line: /work/curdun01/gem5-external.hg/build/ALPHA_MOESI_CMP_directory/gem5.opt -d build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_directory -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_directory Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 54211 because Ruby Tester completed +Exiting @ tick 57351 because Ruby Tester completed diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt index ade451317..c3a7f3ee2 100644 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt @@ -1,45 +1,45 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000054 # Number of seconds simulated -sim_ticks 54211 # Number of ticks simulated -final_tick 54211 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000057 # Number of seconds simulated +sim_ticks 57351 # Number of ticks simulated +final_tick 57351 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 528623 # Simulator tick rate (ticks/s) -host_mem_usage 452196 # Number of bytes of host memory used -host_seconds 0.10 # Real time elapsed on the host +host_tick_rate 527309 # Simulator tick rate (ticks/s) +host_mem_usage 410220 # Number of bytes of host memory used +host_seconds 0.11 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks -system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 54211 # Cumulative time (in ticks) in various power states -system.mem_ctrls.bytes_read::ruby.dir_cntrl0 54016 # Number of bytes read from this memory -system.mem_ctrls.bytes_read::total 54016 # Number of bytes read from this memory -system.mem_ctrls.bytes_written::ruby.dir_cntrl0 48256 # Number of bytes written to this memory -system.mem_ctrls.bytes_written::total 48256 # Number of bytes written to this memory -system.mem_ctrls.num_reads::ruby.dir_cntrl0 844 # Number of read requests responded to by this memory -system.mem_ctrls.num_reads::total 844 # Number of read requests responded to by this memory -system.mem_ctrls.num_writes::ruby.dir_cntrl0 754 # Number of write requests responded to by this memory -system.mem_ctrls.num_writes::total 754 # Number of write requests responded to by this memory -system.mem_ctrls.bw_read::ruby.dir_cntrl0 996402944 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_read::total 996402944 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::ruby.dir_cntrl0 890151445 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::total 890151445 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_total::ruby.dir_cntrl0 1886554389 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.bw_total::total 1886554389 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.readReqs 844 # Number of read requests accepted -system.mem_ctrls.writeReqs 754 # Number of write requests accepted -system.mem_ctrls.readBursts 844 # Number of DRAM read bursts, including those serviced by the write queue -system.mem_ctrls.writeBursts 754 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrls.bytesReadDRAM 46720 # Total number of bytes read from DRAM -system.mem_ctrls.bytesReadWrQ 7296 # Total number of bytes read from write queue -system.mem_ctrls.bytesWritten 42112 # Total number of bytes written to DRAM -system.mem_ctrls.bytesReadSys 54016 # Total read bytes from the system interface side -system.mem_ctrls.bytesWrittenSys 48256 # Total written bytes from the system interface side -system.mem_ctrls.servicedByWrQ 114 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrls.mergedWrBursts 77 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 57351 # Cumulative time (in ticks) in various power states +system.mem_ctrls.bytes_read::ruby.dir_cntrl0 56384 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 56384 # Number of bytes read from this memory +system.mem_ctrls.bytes_written::ruby.dir_cntrl0 50624 # Number of bytes written to this memory +system.mem_ctrls.bytes_written::total 50624 # Number of bytes written to this memory +system.mem_ctrls.num_reads::ruby.dir_cntrl0 881 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 881 # Number of read requests responded to by this memory +system.mem_ctrls.num_writes::ruby.dir_cntrl0 791 # Number of write requests responded to by this memory +system.mem_ctrls.num_writes::total 791 # Number of write requests responded to by this memory +system.mem_ctrls.bw_read::ruby.dir_cntrl0 983138916 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 983138916 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::ruby.dir_cntrl0 882704748 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::total 882704748 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::ruby.dir_cntrl0 1865843664 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 1865843664 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.readReqs 881 # Number of read requests accepted +system.mem_ctrls.writeReqs 791 # Number of write requests accepted +system.mem_ctrls.readBursts 881 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 791 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.bytesReadDRAM 48256 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 8128 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 42816 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 56384 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 50624 # Total written bytes from the system interface side +system.mem_ctrls.servicedByWrQ 127 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 95 # Number of DRAM write bursts merged with an existing one system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.mem_ctrls.perBankRdBursts::0 210 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::1 227 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::2 250 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::3 43 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::0 222 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 247 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 228 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 57 # Per bank write bursts system.mem_ctrls.perBankRdBursts::4 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::5 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::6 0 # Per bank write bursts @@ -52,10 +52,10 @@ system.mem_ctrls.perBankRdBursts::12 0 # Pe system.mem_ctrls.perBankRdBursts::13 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::14 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::15 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::0 189 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::1 208 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::2 219 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::3 42 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 195 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 221 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 201 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 52 # Per bank write bursts system.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts @@ -70,23 +70,23 @@ system.mem_ctrls.perBankWrBursts::14 0 # Pe system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrls.totGap 54170 # Total gap between requests +system.mem_ctrls.totGap 57270 # Total gap between requests system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::6 844 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 881 # Read request sizes (log2) system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::6 754 # Write request sizes (log2) -system.mem_ctrls.rdQLenPdf::0 587 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::1 140 # What read queue length does an incoming req see +system.mem_ctrls.writePktSize::6 791 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 553 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 198 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::2 3 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -132,26 +132,26 @@ system.mem_ctrls.wrQLenPdf::11 1 # Wh system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::15 21 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::16 23 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::17 37 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::18 40 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::19 38 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::20 38 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::21 39 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::22 38 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::23 38 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::24 39 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::25 41 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::26 39 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::27 38 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 25 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 26 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 31 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 45 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 40 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 43 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 40 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 39 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 39 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::24 40 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 39 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 42 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 39 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::28 38 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::29 38 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 39 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::30 38 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::31 38 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::32 38 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::33 2 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::34 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see @@ -181,360 +181,370 @@ system.mem_ctrls.wrQLenPdf::60 0 # Wh system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrls.bytesPerActivate::samples 97 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::mean 888.742268 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::gmean 795.135498 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::stdev 283.200947 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::128-255 8 8.25% 8.25% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::256-383 2 2.06% 10.31% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::384-511 3 3.09% 13.40% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::512-639 2 2.06% 15.46% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::640-767 4 4.12% 19.59% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::768-895 1 1.03% 20.62% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::896-1023 2 2.06% 22.68% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::1024-1151 75 77.32% 100.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::total 97 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::samples 103 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 877.359223 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 782.793653 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 281.638652 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 2 1.94% 1.94% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 4 3.88% 5.83% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 6 5.83% 11.65% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 6 5.83% 17.48% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 4 3.88% 21.36% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 3 2.91% 24.27% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 2 1.94% 26.21% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 76 73.79% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 103 # Bytes accessed per row activation system.mem_ctrls.rdPerTurnAround::samples 38 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::mean 19.052632 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::gmean 18.749953 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::stdev 3.938359 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::14-15 2 5.26% 5.26% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::16-17 13 34.21% 39.47% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::18-19 9 23.68% 63.16% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::20-21 8 21.05% 84.21% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::22-23 4 10.53% 94.74% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::mean 19.447368 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::gmean 19.196443 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::stdev 3.599530 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::14-15 1 2.63% 2.63% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::16-17 9 23.68% 26.32% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::18-19 10 26.32% 52.63% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::20-21 13 34.21% 86.84% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::22-23 3 7.89% 94.74% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::24-25 1 2.63% 97.37% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::38-39 1 2.63% 100.00% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::36-37 1 2.63% 100.00% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::total 38 # Reads before turning the bus around for writes system.mem_ctrls.wrPerTurnAround::samples 38 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::mean 17.315789 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::gmean 17.271887 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::stdev 1.254296 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::16 16 42.11% 42.11% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::17 2 5.26% 47.37% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::18 13 34.21% 81.58% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::19 6 15.79% 97.37% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::mean 17.605263 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::gmean 17.559134 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::stdev 1.284828 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::16 13 34.21% 34.21% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::17 1 2.63% 36.84% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::18 13 34.21% 71.05% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::19 10 26.32% 97.37% # Writes before turning the bus around for reads system.mem_ctrls.wrPerTurnAround::20 1 2.63% 100.00% # Writes before turning the bus around for reads system.mem_ctrls.wrPerTurnAround::total 38 # Writes before turning the bus around for reads -system.mem_ctrls.totQLat 6080 # Total ticks spent queuing -system.mem_ctrls.totMemAccLat 19950 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrls.totBusLat 3650 # Total ticks spent in databus transfers -system.mem_ctrls.avgQLat 8.33 # Average queueing delay per DRAM burst +system.mem_ctrls.totQLat 10814 # Total ticks spent queuing +system.mem_ctrls.totMemAccLat 25140 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.totBusLat 3770 # Total ticks spent in databus transfers +system.mem_ctrls.avgQLat 14.34 # Average queueing delay per DRAM burst system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst -system.mem_ctrls.avgMemAccLat 27.33 # Average memory access latency per DRAM burst -system.mem_ctrls.avgRdBW 861.82 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrls.avgWrBW 776.82 # Average achieved write bandwidth in MiByte/s -system.mem_ctrls.avgRdBWSys 996.40 # Average system read bandwidth in MiByte/s -system.mem_ctrls.avgWrBWSys 890.15 # Average system write bandwidth in MiByte/s +system.mem_ctrls.avgMemAccLat 33.34 # Average memory access latency per DRAM burst +system.mem_ctrls.avgRdBW 841.42 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 746.56 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 983.14 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 882.70 # Average system write bandwidth in MiByte/s system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrls.busUtil 12.80 # Data bus utilization in percentage -system.mem_ctrls.busUtilRead 6.73 # Data bus utilization in percentage for reads -system.mem_ctrls.busUtilWrite 6.07 # Data bus utilization in percentage for writes -system.mem_ctrls.avgRdQLen 1.34 # Average read queue length when enqueuing -system.mem_ctrls.avgWrQLen 24.81 # Average write queue length when enqueuing -system.mem_ctrls.readRowHits 637 # Number of row buffer hits during reads -system.mem_ctrls.writeRowHits 650 # Number of row buffer hits during writes -system.mem_ctrls.readRowHitRate 87.26 # Row buffer hit rate for reads -system.mem_ctrls.writeRowHitRate 96.01 # Row buffer hit rate for writes -system.mem_ctrls.avgGap 33.90 # Average gap between requests -system.mem_ctrls.pageHitRate 91.47 # Row buffer hit rate, read and write combined -system.mem_ctrls_0.actEnergy 650160 # Energy for activate commands per rank (pJ) -system.mem_ctrls_0.preEnergy 361200 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_0.readEnergy 7725120 # Energy for read commands per rank (pJ) -system.mem_ctrls_0.writeEnergy 5723136 # Energy for write commands per rank (pJ) -system.mem_ctrls_0.refreshEnergy 3051360 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_0.actBackEnergy 32013252 # Energy for active background per rank (pJ) -system.mem_ctrls_0.preBackEnergy 103800 # Energy for precharge background per rank (pJ) -system.mem_ctrls_0.totalEnergy 49628028 # Total energy per rank (pJ) -system.mem_ctrls_0.averagePower 1056.454956 # Core power per rank (mW) -system.mem_ctrls_0.memoryStateTime::IDLE 19 # Time in different power states -system.mem_ctrls_0.memoryStateTime::REF 1560 # Time in different power states -system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT 45411 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls.busUtil 12.41 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 6.57 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 5.83 # Data bus utilization in percentage for writes +system.mem_ctrls.avgRdQLen 1.47 # Average read queue length when enqueuing +system.mem_ctrls.avgWrQLen 24.63 # Average write queue length when enqueuing +system.mem_ctrls.readRowHits 656 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 661 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 87.00 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate 94.97 # Row buffer hit rate for writes +system.mem_ctrls.avgGap 34.25 # Average gap between requests +system.mem_ctrls.pageHitRate 90.83 # Row buffer hit rate, read and write combined +system.mem_ctrls_0.actEnergy 756840 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 397992 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 8613696 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 5587488 # Energy for write commands per rank (pJ) +system.mem_ctrls_0.refreshEnergy 4302480.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 11006472 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 91776 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.actPowerDownEnergy 15034776 # Energy for active power-down per rank (pJ) +system.mem_ctrls_0.prePowerDownEnergy 1536 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls_0.totalEnergy 45793056 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 798.470053 # Core power per rank (mW) +system.mem_ctrls_0.totalIdleTime 32938 # Total Idle time Per DRAM Rank +system.mem_ctrls_0.memoryStateTime::IDLE 43 # Time in different power states +system.mem_ctrls_0.memoryStateTime::REF 1820 # Time in different power states +system.mem_ctrls_0.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls_0.memoryStateTime::PRE_PDN 4 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 22513 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT_PDN 32971 # Time in different power states system.mem_ctrls_1.actEnergy 0 # Energy for activate commands per rank (pJ) system.mem_ctrls_1.preEnergy 0 # Energy for precharge commands per rank (pJ) system.mem_ctrls_1.readEnergy 0 # Energy for read commands per rank (pJ) system.mem_ctrls_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.mem_ctrls_1.refreshEnergy 3051360 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_1.actBackEnergy 1009584 # Energy for active background per rank (pJ) -system.mem_ctrls_1.preBackEnergy 27291600 # Energy for precharge background per rank (pJ) -system.mem_ctrls_1.totalEnergy 31352544 # Total energy per rank (pJ) -system.mem_ctrls_1.averagePower 667.615178 # Core power per rank (mW) -system.mem_ctrls_1.memoryStateTime::IDLE 45416 # Time in different power states -system.mem_ctrls_1.memoryStateTime::REF 1560 # Time in different power states -system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_1.refreshEnergy 1229280.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 224352 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 3002880 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls_1.prePowerDownEnergy 2889984 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls_1.selfRefreshEnergy 9963120 # Energy for self refresh per rank (pJ) +system.mem_ctrls_1.totalEnergy 17309616 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 301.818905 # Core power per rank (mW) +system.mem_ctrls_1.totalIdleTime 7526 # Total Idle time Per DRAM Rank +system.mem_ctrls_1.memoryStateTime::IDLE 7786 # Time in different power states +system.mem_ctrls_1.memoryStateTime::REF 526 # Time in different power states +system.mem_ctrls_1.memoryStateTime::SREF 41513 # Time in different power states +system.mem_ctrls_1.memoryStateTime::PRE_PDN 7526 # Time in different power states system.mem_ctrls_1.memoryStateTime::ACT 0 # Time in different power states system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 54211 # Cumulative time (in ticks) in various power states -system.cpu.pwrStateResidencyTicks::UNDEFINED 54211 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 57351 # Cumulative time (in ticks) in various power states +system.cpu.pwrStateResidencyTicks::UNDEFINED 57351 # Cumulative time (in ticks) in various power states system.ruby.clk_domain.clock 1 # Clock period in ticks -system.ruby.pwrStateResidencyTicks::UNDEFINED 54211 # Cumulative time (in ticks) in various power states +system.ruby.pwrStateResidencyTicks::UNDEFINED 57351 # Cumulative time (in ticks) in various power states system.ruby.outstanding_req_hist_seqr::bucket_size 2 system.ruby.outstanding_req_hist_seqr::max_bucket 19 -system.ruby.outstanding_req_hist_seqr::samples 985 -system.ruby.outstanding_req_hist_seqr::mean 15.747208 -system.ruby.outstanding_req_hist_seqr::gmean 15.641156 -system.ruby.outstanding_req_hist_seqr::stdev 1.199617 -system.ruby.outstanding_req_hist_seqr | 1 0.10% 0.10% | 2 0.20% 0.30% | 2 0.20% 0.51% | 2 0.20% 0.71% | 4 0.41% 1.12% | 2 0.20% 1.32% | 3 0.30% 1.62% | 110 11.17% 12.79% | 859 87.21% 100.00% | 0 0.00% 100.00% -system.ruby.outstanding_req_hist_seqr::total 985 +system.ruby.outstanding_req_hist_seqr::samples 1014 +system.ruby.outstanding_req_hist_seqr::mean 15.673570 +system.ruby.outstanding_req_hist_seqr::gmean 15.569970 +system.ruby.outstanding_req_hist_seqr::stdev 1.195975 +system.ruby.outstanding_req_hist_seqr | 1 0.10% 0.10% | 2 0.20% 0.30% | 2 0.20% 0.49% | 2 0.20% 0.69% | 4 0.39% 1.08% | 2 0.20% 1.28% | 3 0.30% 1.58% | 194 19.13% 20.71% | 804 79.29% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist_seqr::total 1014 system.ruby.latency_hist_seqr::bucket_size 256 system.ruby.latency_hist_seqr::max_bucket 2559 -system.ruby.latency_hist_seqr::samples 970 -system.ruby.latency_hist_seqr::mean 876.382474 -system.ruby.latency_hist_seqr::gmean 454.463576 -system.ruby.latency_hist_seqr::stdev 370.932806 -system.ruby.latency_hist_seqr | 146 15.05% 15.05% | 6 0.62% 15.67% | 4 0.41% 16.08% | 388 40.00% 56.08% | 418 43.09% 99.18% | 8 0.82% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.latency_hist_seqr::total 970 +system.ruby.latency_hist_seqr::samples 999 +system.ruby.latency_hist_seqr::mean 900.097097 +system.ruby.latency_hist_seqr::gmean 478.512857 +system.ruby.latency_hist_seqr::stdev 377.349343 +system.ruby.latency_hist_seqr | 145 14.51% 14.51% | 9 0.90% 15.42% | 4 0.40% 15.82% | 380 38.04% 53.85% | 412 41.24% 95.10% | 49 4.90% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.latency_hist_seqr::total 999 system.ruby.hit_latency_hist_seqr::bucket_size 1 system.ruby.hit_latency_hist_seqr::max_bucket 9 -system.ruby.hit_latency_hist_seqr::samples 92 +system.ruby.hit_latency_hist_seqr::samples 90 system.ruby.hit_latency_hist_seqr::mean 1 system.ruby.hit_latency_hist_seqr::gmean 1 -system.ruby.hit_latency_hist_seqr | 0 0.00% 0.00% | 92 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.hit_latency_hist_seqr::total 92 +system.ruby.hit_latency_hist_seqr | 0 0.00% 0.00% | 90 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.hit_latency_hist_seqr::total 90 system.ruby.miss_latency_hist_seqr::bucket_size 256 system.ruby.miss_latency_hist_seqr::max_bucket 2559 -system.ruby.miss_latency_hist_seqr::samples 878 -system.ruby.miss_latency_hist_seqr::mean 968.108200 -system.ruby.miss_latency_hist_seqr::gmean 862.901849 -system.ruby.miss_latency_hist_seqr::stdev 251.425992 -system.ruby.miss_latency_hist_seqr | 54 6.15% 6.15% | 6 0.68% 6.83% | 4 0.46% 7.29% | 388 44.19% 51.48% | 418 47.61% 99.09% | 8 0.91% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.miss_latency_hist_seqr::total 878 -system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 54211 # Cumulative time (in ticks) in various power states -system.ruby.l1_cntrl0.L1Dcache.demand_hits 90 # Number of cache demand hits -system.ruby.l1_cntrl0.L1Dcache.demand_misses 836 # Number of cache demand misses -system.ruby.l1_cntrl0.L1Dcache.demand_accesses 926 # Number of cache demand accesses +system.ruby.miss_latency_hist_seqr::samples 909 +system.ruby.miss_latency_hist_seqr::mean 989.116612 +system.ruby.miss_latency_hist_seqr::gmean 881.514808 +system.ruby.miss_latency_hist_seqr::stdev 261.625282 +system.ruby.miss_latency_hist_seqr | 55 6.05% 6.05% | 9 0.99% 7.04% | 4 0.44% 7.48% | 380 41.80% 49.28% | 412 45.32% 94.61% | 49 5.39% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.miss_latency_hist_seqr::total 909 +system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 57351 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl0.L1Dcache.demand_hits 88 # Number of cache demand hits +system.ruby.l1_cntrl0.L1Dcache.demand_misses 859 # Number of cache demand misses +system.ruby.l1_cntrl0.L1Dcache.demand_accesses 947 # Number of cache demand accesses system.ruby.l1_cntrl0.L1Icache.demand_hits 2 # Number of cache demand hits -system.ruby.l1_cntrl0.L1Icache.demand_misses 44 # Number of cache demand misses -system.ruby.l1_cntrl0.L1Icache.demand_accesses 46 # Number of cache demand accesses -system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 54211 # Cumulative time (in ticks) in various power states -system.ruby.l1_cntrl0.sequencer.store_waiting_on_load 7 # Number of times a store aliased with a pending load -system.ruby.l1_cntrl0.sequencer.store_waiting_on_store 75 # Number of times a store aliased with a pending store -system.ruby.l1_cntrl0.sequencer.load_waiting_on_store 2 # Number of times a load aliased with a pending store -system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 54211 # Cumulative time (in ticks) in various power states -system.ruby.l2_cntrl0.L2cache.demand_hits 36 # Number of cache demand hits -system.ruby.l2_cntrl0.L2cache.demand_misses 844 # Number of cache demand misses -system.ruby.l2_cntrl0.L2cache.demand_accesses 880 # Number of cache demand accesses -system.ruby.l2_cntrl0.pwrStateResidencyTicks::UNDEFINED 54211 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl0.L1Icache.demand_misses 50 # Number of cache demand misses +system.ruby.l1_cntrl0.L1Icache.demand_accesses 52 # Number of cache demand accesses +system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 57351 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl0.sequencer.store_waiting_on_load 2 # Number of times a store aliased with a pending load +system.ruby.l1_cntrl0.sequencer.store_waiting_on_store 89 # Number of times a store aliased with a pending store +system.ruby.l1_cntrl0.sequencer.load_waiting_on_store 5 # Number of times a load aliased with a pending store +system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 57351 # Cumulative time (in ticks) in various power states +system.ruby.l2_cntrl0.L2cache.demand_hits 28 # Number of cache demand hits +system.ruby.l2_cntrl0.L2cache.demand_misses 881 # Number of cache demand misses +system.ruby.l2_cntrl0.L2cache.demand_accesses 909 # Number of cache demand accesses +system.ruby.l2_cntrl0.pwrStateResidencyTicks::UNDEFINED 57351 # Cumulative time (in ticks) in various power states system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 54211 # Cumulative time (in ticks) in various power states -system.ruby.network.routers0.percent_links_utilized 8.888879 -system.ruby.network.routers0.msg_count.Request_Control::0 880 -system.ruby.network.routers0.msg_count.Response_Data::2 843 -system.ruby.network.routers0.msg_count.ResponseL2hit_Data::2 35 -system.ruby.network.routers0.msg_count.Writeback_Data::2 874 -system.ruby.network.routers0.msg_count.Writeback_Control::0 1749 -system.ruby.network.routers0.msg_count.Unblock_Control::2 878 -system.ruby.network.routers0.msg_bytes.Request_Control::0 7040 -system.ruby.network.routers0.msg_bytes.Response_Data::2 60696 -system.ruby.network.routers0.msg_bytes.ResponseL2hit_Data::2 2520 -system.ruby.network.routers0.msg_bytes.Writeback_Data::2 62928 -system.ruby.network.routers0.msg_bytes.Writeback_Control::0 13992 -system.ruby.network.routers0.msg_bytes.Unblock_Control::2 7024 -system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 54211 # Cumulative time (in ticks) in various power states -system.ruby.network.routers1.percent_links_utilized 16.994245 -system.ruby.network.routers1.msg_count.Request_Control::0 880 -system.ruby.network.routers1.msg_count.Request_Control::1 844 -system.ruby.network.routers1.msg_count.Response_Data::2 1686 -system.ruby.network.routers1.msg_count.ResponseL2hit_Data::2 36 -system.ruby.network.routers1.msg_count.Writeback_Data::2 1628 -system.ruby.network.routers1.msg_count.Writeback_Control::0 1749 -system.ruby.network.routers1.msg_count.Writeback_Control::1 1509 -system.ruby.network.routers1.msg_count.Unblock_Control::2 1720 -system.ruby.network.routers1.msg_bytes.Request_Control::0 7040 -system.ruby.network.routers1.msg_bytes.Request_Control::1 6752 -system.ruby.network.routers1.msg_bytes.Response_Data::2 121392 -system.ruby.network.routers1.msg_bytes.ResponseL2hit_Data::2 2592 -system.ruby.network.routers1.msg_bytes.Writeback_Data::2 117216 -system.ruby.network.routers1.msg_bytes.Writeback_Control::0 13992 -system.ruby.network.routers1.msg_bytes.Writeback_Control::1 12072 -system.ruby.network.routers1.msg_bytes.Unblock_Control::2 13760 -system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 54211 # Cumulative time (in ticks) in various power states -system.ruby.network.routers2.percent_links_utilized 8.101677 -system.ruby.network.routers2.msg_count.Request_Control::1 844 -system.ruby.network.routers2.msg_count.Response_Data::2 843 -system.ruby.network.routers2.msg_count.Writeback_Data::2 754 -system.ruby.network.routers2.msg_count.Writeback_Control::1 1509 -system.ruby.network.routers2.msg_count.Unblock_Control::2 842 -system.ruby.network.routers2.msg_bytes.Request_Control::1 6752 -system.ruby.network.routers2.msg_bytes.Response_Data::2 60696 -system.ruby.network.routers2.msg_bytes.Writeback_Data::2 54288 -system.ruby.network.routers2.msg_bytes.Writeback_Control::1 12072 -system.ruby.network.routers2.msg_bytes.Unblock_Control::2 6736 -system.ruby.network.routers3.pwrStateResidencyTicks::UNDEFINED 54211 # Cumulative time (in ticks) in various power states -system.ruby.network.routers3.percent_links_utilized 11.328267 -system.ruby.network.routers3.msg_count.Request_Control::0 880 -system.ruby.network.routers3.msg_count.Request_Control::1 844 -system.ruby.network.routers3.msg_count.Response_Data::2 1686 -system.ruby.network.routers3.msg_count.ResponseL2hit_Data::2 36 -system.ruby.network.routers3.msg_count.Writeback_Data::2 1628 -system.ruby.network.routers3.msg_count.Writeback_Control::0 1749 -system.ruby.network.routers3.msg_count.Writeback_Control::1 1509 -system.ruby.network.routers3.msg_count.Unblock_Control::2 1720 -system.ruby.network.routers3.msg_bytes.Request_Control::0 7040 -system.ruby.network.routers3.msg_bytes.Request_Control::1 6752 -system.ruby.network.routers3.msg_bytes.Response_Data::2 121392 -system.ruby.network.routers3.msg_bytes.ResponseL2hit_Data::2 2592 -system.ruby.network.routers3.msg_bytes.Writeback_Data::2 117216 -system.ruby.network.routers3.msg_bytes.Writeback_Control::0 13992 -system.ruby.network.routers3.msg_bytes.Writeback_Control::1 12072 -system.ruby.network.routers3.msg_bytes.Unblock_Control::2 13760 -system.ruby.network.pwrStateResidencyTicks::UNDEFINED 54211 # Cumulative time (in ticks) in various power states -system.ruby.network.msg_count.Request_Control 5172 -system.ruby.network.msg_count.Response_Data 5058 -system.ruby.network.msg_count.ResponseL2hit_Data 107 -system.ruby.network.msg_count.Writeback_Data 4884 -system.ruby.network.msg_count.Writeback_Control 9774 -system.ruby.network.msg_count.Unblock_Control 5160 -system.ruby.network.msg_byte.Request_Control 41376 -system.ruby.network.msg_byte.Response_Data 364176 -system.ruby.network.msg_byte.ResponseL2hit_Data 7704 -system.ruby.network.msg_byte.Writeback_Data 351648 -system.ruby.network.msg_byte.Writeback_Control 78192 -system.ruby.network.msg_byte.Unblock_Control 41280 -system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 54211 # Cumulative time (in ticks) in various power states -system.ruby.network.routers0.throttle0.link_utilization 8.094298 -system.ruby.network.routers0.throttle0.msg_count.Response_Data::2 843 -system.ruby.network.routers0.throttle0.msg_count.ResponseL2hit_Data::2 35 -system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::0 874 -system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::2 60696 -system.ruby.network.routers0.throttle0.msg_bytes.ResponseL2hit_Data::2 2520 -system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::0 6992 -system.ruby.network.routers0.throttle1.link_utilization 9.683459 -system.ruby.network.routers0.throttle1.msg_count.Request_Control::0 880 -system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::2 874 -system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::0 875 -system.ruby.network.routers0.throttle1.msg_count.Unblock_Control::2 878 -system.ruby.network.routers0.throttle1.msg_bytes.Request_Control::0 7040 -system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::2 62928 -system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::0 7000 -system.ruby.network.routers0.throttle1.msg_bytes.Unblock_Control::2 7024 -system.ruby.network.routers1.throttle0.link_utilization 17.376547 -system.ruby.network.routers1.throttle0.msg_count.Request_Control::0 880 -system.ruby.network.routers1.throttle0.msg_count.Response_Data::2 843 -system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::2 874 -system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::0 875 -system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::1 754 -system.ruby.network.routers1.throttle0.msg_count.Unblock_Control::2 878 -system.ruby.network.routers1.throttle0.msg_bytes.Request_Control::0 7040 -system.ruby.network.routers1.throttle0.msg_bytes.Response_Data::2 60696 -system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::2 62928 -system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::0 7000 -system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::1 6032 -system.ruby.network.routers1.throttle0.msg_bytes.Unblock_Control::2 7024 -system.ruby.network.routers1.throttle1.link_utilization 16.611942 -system.ruby.network.routers1.throttle1.msg_count.Request_Control::1 844 -system.ruby.network.routers1.throttle1.msg_count.Response_Data::2 843 -system.ruby.network.routers1.throttle1.msg_count.ResponseL2hit_Data::2 36 -system.ruby.network.routers1.throttle1.msg_count.Writeback_Data::2 754 -system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::0 874 -system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::1 755 -system.ruby.network.routers1.throttle1.msg_count.Unblock_Control::2 842 -system.ruby.network.routers1.throttle1.msg_bytes.Request_Control::1 6752 -system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::2 60696 -system.ruby.network.routers1.throttle1.msg_bytes.ResponseL2hit_Data::2 2592 -system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Data::2 54288 -system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::0 6992 -system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::1 6040 -system.ruby.network.routers1.throttle1.msg_bytes.Unblock_Control::2 6736 -system.ruby.network.routers2.throttle0.link_utilization 8.510265 -system.ruby.network.routers2.throttle0.msg_count.Request_Control::1 844 -system.ruby.network.routers2.throttle0.msg_count.Writeback_Data::2 754 -system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::1 755 -system.ruby.network.routers2.throttle0.msg_count.Unblock_Control::2 842 -system.ruby.network.routers2.throttle0.msg_bytes.Request_Control::1 6752 -system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Data::2 54288 -system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::1 6040 -system.ruby.network.routers2.throttle0.msg_bytes.Unblock_Control::2 6736 -system.ruby.network.routers2.throttle1.link_utilization 7.693088 -system.ruby.network.routers2.throttle1.msg_count.Response_Data::2 843 -system.ruby.network.routers2.throttle1.msg_count.Writeback_Control::1 754 -system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::2 60696 -system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Control::1 6032 -system.ruby.network.routers3.throttle0.link_utilization 8.097987 -system.ruby.network.routers3.throttle0.msg_count.Response_Data::2 843 -system.ruby.network.routers3.throttle0.msg_count.ResponseL2hit_Data::2 36 -system.ruby.network.routers3.throttle0.msg_count.Writeback_Control::0 874 -system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::2 60696 -system.ruby.network.routers3.throttle0.msg_bytes.ResponseL2hit_Data::2 2592 -system.ruby.network.routers3.throttle0.msg_bytes.Writeback_Control::0 6992 -system.ruby.network.routers3.throttle1.link_utilization 17.376547 -system.ruby.network.routers3.throttle1.msg_count.Request_Control::0 880 -system.ruby.network.routers3.throttle1.msg_count.Response_Data::2 843 -system.ruby.network.routers3.throttle1.msg_count.Writeback_Data::2 874 -system.ruby.network.routers3.throttle1.msg_count.Writeback_Control::0 875 -system.ruby.network.routers3.throttle1.msg_count.Writeback_Control::1 754 -system.ruby.network.routers3.throttle1.msg_count.Unblock_Control::2 878 -system.ruby.network.routers3.throttle1.msg_bytes.Request_Control::0 7040 -system.ruby.network.routers3.throttle1.msg_bytes.Response_Data::2 60696 -system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::2 62928 -system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::0 7000 -system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::1 6032 -system.ruby.network.routers3.throttle1.msg_bytes.Unblock_Control::2 7024 -system.ruby.network.routers3.throttle2.link_utilization 8.510265 -system.ruby.network.routers3.throttle2.msg_count.Request_Control::1 844 -system.ruby.network.routers3.throttle2.msg_count.Writeback_Data::2 754 -system.ruby.network.routers3.throttle2.msg_count.Writeback_Control::1 755 -system.ruby.network.routers3.throttle2.msg_count.Unblock_Control::2 842 -system.ruby.network.routers3.throttle2.msg_bytes.Request_Control::1 6752 -system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Data::2 54288 -system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Control::1 6040 -system.ruby.network.routers3.throttle2.msg_bytes.Unblock_Control::2 6736 -system.ruby.LD.latency_hist_seqr::bucket_size 128 -system.ruby.LD.latency_hist_seqr::max_bucket 1279 -system.ruby.LD.latency_hist_seqr::samples 54 -system.ruby.LD.latency_hist_seqr::mean 874.574074 -system.ruby.LD.latency_hist_seqr::gmean 437.265598 -system.ruby.LD.latency_hist_seqr::stdev 350.325488 -system.ruby.LD.latency_hist_seqr | 7 12.96% 12.96% | 0 0.00% 12.96% | 0 0.00% 12.96% | 0 0.00% 12.96% | 0 0.00% 12.96% | 0 0.00% 12.96% | 5 9.26% 22.22% | 29 53.70% 75.93% | 9 16.67% 92.59% | 4 7.41% 100.00% -system.ruby.LD.latency_hist_seqr::total 54 +system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 57351 # Cumulative time (in ticks) in various power states +system.ruby.network.routers0.percent_links_utilized 8.691653 +system.ruby.network.routers0.msg_count.Request_Control::0 909 +system.ruby.network.routers0.msg_count.Response_Data::2 881 +system.ruby.network.routers0.msg_count.ResponseL2hit_Data::2 28 +system.ruby.network.routers0.msg_count.Writeback_Data::2 904 +system.ruby.network.routers0.msg_count.Writeback_Control::0 1808 +system.ruby.network.routers0.msg_count.Unblock_Control::2 908 +system.ruby.network.routers0.msg_bytes.Request_Control::0 7272 +system.ruby.network.routers0.msg_bytes.Response_Data::2 63432 +system.ruby.network.routers0.msg_bytes.ResponseL2hit_Data::2 2016 +system.ruby.network.routers0.msg_bytes.Writeback_Data::2 65088 +system.ruby.network.routers0.msg_bytes.Writeback_Control::0 14464 +system.ruby.network.routers0.msg_bytes.Unblock_Control::2 7264 +system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 57351 # Cumulative time (in ticks) in various power states +system.ruby.network.routers1.percent_links_utilized 16.709822 +system.ruby.network.routers1.msg_count.Request_Control::0 909 +system.ruby.network.routers1.msg_count.Request_Control::1 881 +system.ruby.network.routers1.msg_count.Response_Data::2 1762 +system.ruby.network.routers1.msg_count.ResponseL2hit_Data::2 28 +system.ruby.network.routers1.msg_count.Writeback_Data::2 1695 +system.ruby.network.routers1.msg_count.Writeback_Control::0 1808 +system.ruby.network.routers1.msg_count.Writeback_Control::1 1582 +system.ruby.network.routers1.msg_count.Unblock_Control::2 1788 +system.ruby.network.routers1.msg_bytes.Request_Control::0 7272 +system.ruby.network.routers1.msg_bytes.Request_Control::1 7048 +system.ruby.network.routers1.msg_bytes.Response_Data::2 126864 +system.ruby.network.routers1.msg_bytes.ResponseL2hit_Data::2 2016 +system.ruby.network.routers1.msg_bytes.Writeback_Data::2 122040 +system.ruby.network.routers1.msg_bytes.Writeback_Control::0 14464 +system.ruby.network.routers1.msg_bytes.Writeback_Control::1 12656 +system.ruby.network.routers1.msg_bytes.Unblock_Control::2 14304 +system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 57351 # Cumulative time (in ticks) in various power states +system.ruby.network.routers2.percent_links_utilized 8.016861 +system.ruby.network.routers2.msg_count.Request_Control::1 881 +system.ruby.network.routers2.msg_count.Response_Data::2 881 +system.ruby.network.routers2.msg_count.Writeback_Data::2 791 +system.ruby.network.routers2.msg_count.Writeback_Control::1 1582 +system.ruby.network.routers2.msg_count.Unblock_Control::2 880 +system.ruby.network.routers2.msg_bytes.Request_Control::1 7048 +system.ruby.network.routers2.msg_bytes.Response_Data::2 63432 +system.ruby.network.routers2.msg_bytes.Writeback_Data::2 56952 +system.ruby.network.routers2.msg_bytes.Writeback_Control::1 12656 +system.ruby.network.routers2.msg_bytes.Unblock_Control::2 7040 +system.ruby.network.routers3.pwrStateResidencyTicks::UNDEFINED 57351 # Cumulative time (in ticks) in various power states +system.ruby.network.routers3.percent_links_utilized 11.139881 +system.ruby.network.routers3.msg_count.Request_Control::0 909 +system.ruby.network.routers3.msg_count.Request_Control::1 881 +system.ruby.network.routers3.msg_count.Response_Data::2 1762 +system.ruby.network.routers3.msg_count.ResponseL2hit_Data::2 28 +system.ruby.network.routers3.msg_count.Writeback_Data::2 1695 +system.ruby.network.routers3.msg_count.Writeback_Control::0 1808 +system.ruby.network.routers3.msg_count.Writeback_Control::1 1582 +system.ruby.network.routers3.msg_count.Unblock_Control::2 1788 +system.ruby.network.routers3.msg_bytes.Request_Control::0 7272 +system.ruby.network.routers3.msg_bytes.Request_Control::1 7048 +system.ruby.network.routers3.msg_bytes.Response_Data::2 126864 +system.ruby.network.routers3.msg_bytes.ResponseL2hit_Data::2 2016 +system.ruby.network.routers3.msg_bytes.Writeback_Data::2 122040 +system.ruby.network.routers3.msg_bytes.Writeback_Control::0 14464 +system.ruby.network.routers3.msg_bytes.Writeback_Control::1 12656 +system.ruby.network.routers3.msg_bytes.Unblock_Control::2 14304 +system.ruby.network.pwrStateResidencyTicks::UNDEFINED 57351 # Cumulative time (in ticks) in various power states +system.ruby.network.msg_count.Request_Control 5370 +system.ruby.network.msg_count.Response_Data 5286 +system.ruby.network.msg_count.ResponseL2hit_Data 84 +system.ruby.network.msg_count.Writeback_Data 5085 +system.ruby.network.msg_count.Writeback_Control 10170 +system.ruby.network.msg_count.Unblock_Control 5364 +system.ruby.network.msg_byte.Request_Control 42960 +system.ruby.network.msg_byte.Response_Data 380592 +system.ruby.network.msg_byte.ResponseL2hit_Data 6048 +system.ruby.network.msg_byte.Writeback_Data 366120 +system.ruby.network.msg_byte.Writeback_Control 81360 +system.ruby.network.msg_byte.Unblock_Control 42912 +system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 57351 # Cumulative time (in ticks) in various power states +system.ruby.network.routers0.throttle0.link_utilization 7.917909 +system.ruby.network.routers0.throttle0.msg_count.Response_Data::2 881 +system.ruby.network.routers0.throttle0.msg_count.ResponseL2hit_Data::2 28 +system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::0 904 +system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::2 63432 +system.ruby.network.routers0.throttle0.msg_bytes.ResponseL2hit_Data::2 2016 +system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::0 7232 +system.ruby.network.routers0.throttle1.link_utilization 9.465397 +system.ruby.network.routers0.throttle1.msg_count.Request_Control::0 909 +system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::2 904 +system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::0 904 +system.ruby.network.routers0.throttle1.msg_count.Unblock_Control::2 908 +system.ruby.network.routers0.throttle1.msg_bytes.Request_Control::0 7272 +system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::2 65088 +system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::0 7232 +system.ruby.network.routers0.throttle1.msg_bytes.Unblock_Control::2 7264 +system.ruby.network.routers1.throttle0.link_utilization 17.067706 +system.ruby.network.routers1.throttle0.msg_count.Request_Control::0 909 +system.ruby.network.routers1.throttle0.msg_count.Response_Data::2 881 +system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::2 904 +system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::0 904 +system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::1 791 +system.ruby.network.routers1.throttle0.msg_count.Unblock_Control::2 908 +system.ruby.network.routers1.throttle0.msg_bytes.Request_Control::0 7272 +system.ruby.network.routers1.throttle0.msg_bytes.Response_Data::2 63432 +system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::2 65088 +system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::0 7232 +system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::1 6328 +system.ruby.network.routers1.throttle0.msg_bytes.Unblock_Control::2 7264 +system.ruby.network.routers1.throttle1.link_utilization 16.351938 +system.ruby.network.routers1.throttle1.msg_count.Request_Control::1 881 +system.ruby.network.routers1.throttle1.msg_count.Response_Data::2 881 +system.ruby.network.routers1.throttle1.msg_count.ResponseL2hit_Data::2 28 +system.ruby.network.routers1.throttle1.msg_count.Writeback_Data::2 791 +system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::0 904 +system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::1 791 +system.ruby.network.routers1.throttle1.msg_count.Unblock_Control::2 880 +system.ruby.network.routers1.throttle1.msg_bytes.Request_Control::1 7048 +system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::2 63432 +system.ruby.network.routers1.throttle1.msg_bytes.ResponseL2hit_Data::2 2016 +system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Data::2 56952 +system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::0 7232 +system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::1 6328 +system.ruby.network.routers1.throttle1.msg_bytes.Unblock_Control::2 7040 +system.ruby.network.routers2.throttle0.link_utilization 8.431414 +system.ruby.network.routers2.throttle0.msg_count.Request_Control::1 881 +system.ruby.network.routers2.throttle0.msg_count.Writeback_Data::2 791 +system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::1 791 +system.ruby.network.routers2.throttle0.msg_count.Unblock_Control::2 880 +system.ruby.network.routers2.throttle0.msg_bytes.Request_Control::1 7048 +system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Data::2 56952 +system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::1 6328 +system.ruby.network.routers2.throttle0.msg_bytes.Unblock_Control::2 7040 +system.ruby.network.routers2.throttle1.link_utilization 7.602309 +system.ruby.network.routers2.throttle1.msg_count.Response_Data::2 881 +system.ruby.network.routers2.throttle1.msg_count.Writeback_Control::1 791 +system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::2 63432 +system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Control::1 6328 +system.ruby.network.routers3.throttle0.link_utilization 7.920524 +system.ruby.network.routers3.throttle0.msg_count.Response_Data::2 881 +system.ruby.network.routers3.throttle0.msg_count.ResponseL2hit_Data::2 28 +system.ruby.network.routers3.throttle0.msg_count.Writeback_Control::0 904 +system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::2 63432 +system.ruby.network.routers3.throttle0.msg_bytes.ResponseL2hit_Data::2 2016 +system.ruby.network.routers3.throttle0.msg_bytes.Writeback_Control::0 7232 +system.ruby.network.routers3.throttle1.link_utilization 17.067706 +system.ruby.network.routers3.throttle1.msg_count.Request_Control::0 909 +system.ruby.network.routers3.throttle1.msg_count.Response_Data::2 881 +system.ruby.network.routers3.throttle1.msg_count.Writeback_Data::2 904 +system.ruby.network.routers3.throttle1.msg_count.Writeback_Control::0 904 +system.ruby.network.routers3.throttle1.msg_count.Writeback_Control::1 791 +system.ruby.network.routers3.throttle1.msg_count.Unblock_Control::2 908 +system.ruby.network.routers3.throttle1.msg_bytes.Request_Control::0 7272 +system.ruby.network.routers3.throttle1.msg_bytes.Response_Data::2 63432 +system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::2 65088 +system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::0 7232 +system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::1 6328 +system.ruby.network.routers3.throttle1.msg_bytes.Unblock_Control::2 7264 +system.ruby.network.routers3.throttle2.link_utilization 8.431414 +system.ruby.network.routers3.throttle2.msg_count.Request_Control::1 881 +system.ruby.network.routers3.throttle2.msg_count.Writeback_Data::2 791 +system.ruby.network.routers3.throttle2.msg_count.Writeback_Control::1 791 +system.ruby.network.routers3.throttle2.msg_count.Unblock_Control::2 880 +system.ruby.network.routers3.throttle2.msg_bytes.Request_Control::1 7048 +system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Data::2 56952 +system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Control::1 6328 +system.ruby.network.routers3.throttle2.msg_bytes.Unblock_Control::2 7040 +system.ruby.LD.latency_hist_seqr::bucket_size 256 +system.ruby.LD.latency_hist_seqr::max_bucket 2559 +system.ruby.LD.latency_hist_seqr::samples 48 +system.ruby.LD.latency_hist_seqr::mean 885.875000 +system.ruby.LD.latency_hist_seqr::gmean 375.211617 +system.ruby.LD.latency_hist_seqr::stdev 381.714030 +system.ruby.LD.latency_hist_seqr | 7 14.58% 14.58% | 0 0.00% 14.58% | 0 0.00% 14.58% | 21 43.75% 58.33% | 18 37.50% 95.83% | 2 4.17% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.latency_hist_seqr::total 48 system.ruby.LD.hit_latency_hist_seqr::bucket_size 1 system.ruby.LD.hit_latency_hist_seqr::max_bucket 9 -system.ruby.LD.hit_latency_hist_seqr::samples 6 +system.ruby.LD.hit_latency_hist_seqr::samples 7 system.ruby.LD.hit_latency_hist_seqr::mean 1 system.ruby.LD.hit_latency_hist_seqr::gmean 1 -system.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 6 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.hit_latency_hist_seqr::total 6 -system.ruby.LD.miss_latency_hist_seqr::bucket_size 128 -system.ruby.LD.miss_latency_hist_seqr::max_bucket 1279 -system.ruby.LD.miss_latency_hist_seqr::samples 48 -system.ruby.LD.miss_latency_hist_seqr::mean 983.770833 -system.ruby.LD.miss_latency_hist_seqr::gmean 935.057837 -system.ruby.LD.miss_latency_hist_seqr::stdev 169.695753 -system.ruby.LD.miss_latency_hist_seqr | 1 2.08% 2.08% | 0 0.00% 2.08% | 0 0.00% 2.08% | 0 0.00% 2.08% | 0 0.00% 2.08% | 0 0.00% 2.08% | 5 10.42% 12.50% | 29 60.42% 72.92% | 9 18.75% 91.67% | 4 8.33% 100.00% -system.ruby.LD.miss_latency_hist_seqr::total 48 +system.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 7 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.hit_latency_hist_seqr::total 7 +system.ruby.LD.miss_latency_hist_seqr::bucket_size 256 +system.ruby.LD.miss_latency_hist_seqr::max_bucket 2559 +system.ruby.LD.miss_latency_hist_seqr::samples 41 +system.ruby.LD.miss_latency_hist_seqr::mean 1036.951220 +system.ruby.LD.miss_latency_hist_seqr::gmean 1032.254678 +system.ruby.LD.miss_latency_hist_seqr::stdev 103.845065 +system.ruby.LD.miss_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 21 51.22% 51.22% | 18 43.90% 95.12% | 2 4.88% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.miss_latency_hist_seqr::total 41 system.ruby.ST.latency_hist_seqr::bucket_size 256 system.ruby.ST.latency_hist_seqr::max_bucket 2559 -system.ruby.ST.latency_hist_seqr::samples 870 -system.ruby.ST.latency_hist_seqr::mean 919.120690 -system.ruby.ST.latency_hist_seqr::gmean 509.527867 -system.ruby.ST.latency_hist_seqr::stdev 331.108106 -system.ruby.ST.latency_hist_seqr | 93 10.69% 10.69% | 6 0.69% 11.38% | 4 0.46% 11.84% | 354 40.69% 52.53% | 405 46.55% 99.08% | 8 0.92% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.latency_hist_seqr::total 870 +system.ruby.ST.latency_hist_seqr::samples 899 +system.ruby.ST.latency_hist_seqr::mean 947.919911 +system.ruby.ST.latency_hist_seqr::gmean 545.272647 +system.ruby.ST.latency_hist_seqr::stdev 331.026961 +system.ruby.ST.latency_hist_seqr | 89 9.90% 9.90% | 6 0.67% 10.57% | 4 0.44% 11.01% | 359 39.93% 50.95% | 394 43.83% 94.77% | 47 5.23% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.latency_hist_seqr::total 899 system.ruby.ST.hit_latency_hist_seqr::bucket_size 1 system.ruby.ST.hit_latency_hist_seqr::max_bucket 9 -system.ruby.ST.hit_latency_hist_seqr::samples 84 +system.ruby.ST.hit_latency_hist_seqr::samples 81 system.ruby.ST.hit_latency_hist_seqr::mean 1 system.ruby.ST.hit_latency_hist_seqr::gmean 1 -system.ruby.ST.hit_latency_hist_seqr | 0 0.00% 0.00% | 84 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.hit_latency_hist_seqr::total 84 +system.ruby.ST.hit_latency_hist_seqr | 0 0.00% 0.00% | 81 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.hit_latency_hist_seqr::total 81 system.ruby.ST.miss_latency_hist_seqr::bucket_size 256 system.ruby.ST.miss_latency_hist_seqr::max_bucket 2559 -system.ruby.ST.miss_latency_hist_seqr::samples 786 -system.ruby.ST.miss_latency_hist_seqr::mean 1017.240458 -system.ruby.ST.miss_latency_hist_seqr::gmean 991.935880 -system.ruby.ST.miss_latency_hist_seqr::stdev 146.709443 -system.ruby.ST.miss_latency_hist_seqr | 9 1.15% 1.15% | 6 0.76% 1.91% | 4 0.51% 2.42% | 354 45.04% 47.46% | 405 51.53% 98.98% | 8 1.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.miss_latency_hist_seqr::total 786 -system.ruby.IFETCH.latency_hist_seqr::bucket_size 32 -system.ruby.IFETCH.latency_hist_seqr::max_bucket 319 -system.ruby.IFETCH.latency_hist_seqr::samples 46 -system.ruby.IFETCH.latency_hist_seqr::mean 70.195652 -system.ruby.IFETCH.latency_hist_seqr::gmean 54.673545 -system.ruby.IFETCH.latency_hist_seqr::stdev 37.753363 -system.ruby.IFETCH.latency_hist_seqr | 4 8.70% 8.70% | 14 30.43% 39.13% | 21 45.65% 84.78% | 1 2.17% 86.96% | 4 8.70% 95.65% | 2 4.35% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.latency_hist_seqr::total 46 +system.ruby.ST.miss_latency_hist_seqr::samples 818 +system.ruby.ST.miss_latency_hist_seqr::mean 1041.685819 +system.ruby.ST.miss_latency_hist_seqr::gmean 1017.650590 +system.ruby.ST.miss_latency_hist_seqr::stdev 150.806361 +system.ruby.ST.miss_latency_hist_seqr | 8 0.98% 0.98% | 6 0.73% 1.71% | 4 0.49% 2.20% | 359 43.89% 46.09% | 394 48.17% 94.25% | 47 5.75% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.miss_latency_hist_seqr::total 818 +system.ruby.IFETCH.latency_hist_seqr::bucket_size 64 +system.ruby.IFETCH.latency_hist_seqr::max_bucket 639 +system.ruby.IFETCH.latency_hist_seqr::samples 52 +system.ruby.IFETCH.latency_hist_seqr::mean 86.442308 +system.ruby.IFETCH.latency_hist_seqr::gmean 62.630120 +system.ruby.IFETCH.latency_hist_seqr::stdev 84.743769 +system.ruby.IFETCH.latency_hist_seqr | 17 32.69% 32.69% | 31 59.62% 92.31% | 1 1.92% 94.23% | 0 0.00% 94.23% | 0 0.00% 94.23% | 2 3.85% 98.08% | 0 0.00% 98.08% | 1 1.92% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.latency_hist_seqr::total 52 system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 1 system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 9 system.ruby.IFETCH.hit_latency_hist_seqr::samples 2 @@ -542,102 +552,98 @@ system.ruby.IFETCH.hit_latency_hist_seqr::mean 1 system.ruby.IFETCH.hit_latency_hist_seqr::gmean 1 system.ruby.IFETCH.hit_latency_hist_seqr | 0 0.00% 0.00% | 2 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.hit_latency_hist_seqr::total 2 -system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 32 -system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 319 -system.ruby.IFETCH.miss_latency_hist_seqr::samples 44 -system.ruby.IFETCH.miss_latency_hist_seqr::mean 73.340909 -system.ruby.IFETCH.miss_latency_hist_seqr::gmean 65.579350 -system.ruby.IFETCH.miss_latency_hist_seqr::stdev 35.479403 -system.ruby.IFETCH.miss_latency_hist_seqr | 2 4.55% 4.55% | 14 31.82% 36.36% | 21 47.73% 84.09% | 1 2.27% 86.36% | 4 9.09% 95.45% | 2 4.55% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.miss_latency_hist_seqr::total 44 -system.ruby.Directory_Controller.GETX 761 0.00% 0.00% -system.ruby.Directory_Controller.GETS 83 0.00% 0.00% -system.ruby.Directory_Controller.PUTX 755 0.00% 0.00% -system.ruby.Directory_Controller.Unblock 77 0.00% 0.00% -system.ruby.Directory_Controller.Last_Unblock 5 0.00% 0.00% -system.ruby.Directory_Controller.Exclusive_Unblock 760 0.00% 0.00% -system.ruby.Directory_Controller.Dirty_Writeback 754 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 843 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 754 0.00% 0.00% -system.ruby.Directory_Controller.I.GETX 691 0.00% 0.00% -system.ruby.Directory_Controller.I.GETS 78 0.00% 0.00% -system.ruby.Directory_Controller.I.Memory_Ack 754 0.00% 0.00% -system.ruby.Directory_Controller.S.GETX 70 0.00% 0.00% -system.ruby.Directory_Controller.S.GETS 5 0.00% 0.00% -system.ruby.Directory_Controller.M.PUTX 755 0.00% 0.00% -system.ruby.Directory_Controller.IS.Unblock 77 0.00% 0.00% -system.ruby.Directory_Controller.IS.Memory_Data 78 0.00% 0.00% -system.ruby.Directory_Controller.SS.Last_Unblock 5 0.00% 0.00% -system.ruby.Directory_Controller.SS.Memory_Data 5 0.00% 0.00% -system.ruby.Directory_Controller.MM.Exclusive_Unblock 760 0.00% 0.00% -system.ruby.Directory_Controller.MM.Memory_Data 760 0.00% 0.00% -system.ruby.Directory_Controller.MI.Dirty_Writeback 754 0.00% 0.00% -system.ruby.L1Cache_Controller.Load 56 0.00% 0.00% -system.ruby.L1Cache_Controller.Ifetch 59 0.00% 0.00% -system.ruby.L1Cache_Controller.Store 880 0.00% 0.00% -system.ruby.L1Cache_Controller.L1_Replacement 80012 0.00% 0.00% -system.ruby.L1Cache_Controller.Data 83 0.00% 0.00% -system.ruby.L1Cache_Controller.Exclusive_Data 795 0.00% 0.00% -system.ruby.L1Cache_Controller.Writeback_Ack_Data 874 0.00% 0.00% -system.ruby.L1Cache_Controller.All_acks 786 0.00% 0.00% -system.ruby.L1Cache_Controller.Use_Timeout 795 0.00% 0.00% -system.ruby.L1Cache_Controller.I.Load 48 0.00% 0.00% -system.ruby.L1Cache_Controller.I.Ifetch 44 0.00% 0.00% -system.ruby.L1Cache_Controller.I.Store 788 0.00% 0.00% -system.ruby.L1Cache_Controller.S.L1_Replacement 81 0.00% 0.00% -system.ruby.L1Cache_Controller.M.Ifetch 2 0.00% 0.00% -system.ruby.L1Cache_Controller.M.Store 1 0.00% 0.00% -system.ruby.L1Cache_Controller.M.L1_Replacement 7 0.00% 0.00% -system.ruby.L1Cache_Controller.M_W.L1_Replacement 5 0.00% 0.00% -system.ruby.L1Cache_Controller.M_W.Use_Timeout 9 0.00% 0.00% -system.ruby.L1Cache_Controller.MM.Load 4 0.00% 0.00% -system.ruby.L1Cache_Controller.MM.Store 68 0.00% 0.00% -system.ruby.L1Cache_Controller.MM.L1_Replacement 787 0.00% 0.00% -system.ruby.L1Cache_Controller.MM_W.Load 2 0.00% 0.00% -system.ruby.L1Cache_Controller.MM_W.Store 15 0.00% 0.00% -system.ruby.L1Cache_Controller.MM_W.L1_Replacement 30902 0.00% 0.00% -system.ruby.L1Cache_Controller.MM_W.Use_Timeout 786 0.00% 0.00% -system.ruby.L1Cache_Controller.IM.L1_Replacement 45597 0.00% 0.00% -system.ruby.L1Cache_Controller.IM.Exclusive_Data 786 0.00% 0.00% -system.ruby.L1Cache_Controller.OM.L1_Replacement 45 0.00% 0.00% -system.ruby.L1Cache_Controller.OM.All_acks 786 0.00% 0.00% -system.ruby.L1Cache_Controller.IS.L1_Replacement 2588 0.00% 0.00% -system.ruby.L1Cache_Controller.IS.Data 83 0.00% 0.00% -system.ruby.L1Cache_Controller.IS.Exclusive_Data 9 0.00% 0.00% -system.ruby.L1Cache_Controller.SI.Writeback_Ack_Data 81 0.00% 0.00% -system.ruby.L1Cache_Controller.MI.Load 2 0.00% 0.00% -system.ruby.L1Cache_Controller.MI.Ifetch 13 0.00% 0.00% -system.ruby.L1Cache_Controller.MI.Store 8 0.00% 0.00% -system.ruby.L1Cache_Controller.MI.Writeback_Ack_Data 793 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_GETS 92 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_GETX 788 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_PUTX 794 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_PUTS_only 81 0.00% 0.00% -system.ruby.L2Cache_Controller.All_Acks 760 0.00% 0.00% -system.ruby.L2Cache_Controller.Data 843 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_WBCLEANDATA 81 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_WBDIRTYDATA 793 0.00% 0.00% -system.ruby.L2Cache_Controller.Writeback_Ack 754 0.00% 0.00% -system.ruby.L2Cache_Controller.Unblock 82 0.00% 0.00% -system.ruby.L2Cache_Controller.Exclusive_Unblock 795 0.00% 0.00% -system.ruby.L2Cache_Controller.L2_Replacement 836 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.L1_GETS 83 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.L1_GETX 761 0.00% 0.00% -system.ruby.L2Cache_Controller.ILS.L1_PUTS_only 81 0.00% 0.00% -system.ruby.L2Cache_Controller.ILX.L1_PUTX 794 0.00% 0.00% -system.ruby.L2Cache_Controller.S.L2_Replacement 81 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L1_GETS 9 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L1_GETX 27 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L2_Replacement 755 0.00% 0.00% -system.ruby.L2Cache_Controller.IW.L1_WBCLEANDATA 81 0.00% 0.00% -system.ruby.L2Cache_Controller.ILXW.L1_WBDIRTYDATA 793 0.00% 0.00% -system.ruby.L2Cache_Controller.IGS.Data 83 0.00% 0.00% -system.ruby.L2Cache_Controller.IGS.Unblock 82 0.00% 0.00% -system.ruby.L2Cache_Controller.IGM.Data 760 0.00% 0.00% -system.ruby.L2Cache_Controller.IGMO.All_Acks 760 0.00% 0.00% -system.ruby.L2Cache_Controller.IGMO.Exclusive_Unblock 760 0.00% 0.00% -system.ruby.L2Cache_Controller.MM.Exclusive_Unblock 26 0.00% 0.00% -system.ruby.L2Cache_Controller.OO.Exclusive_Unblock 9 0.00% 0.00% -system.ruby.L2Cache_Controller.MI.Writeback_Ack 754 0.00% 0.00% +system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 64 +system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 639 +system.ruby.IFETCH.miss_latency_hist_seqr::samples 50 +system.ruby.IFETCH.miss_latency_hist_seqr::mean 89.860000 +system.ruby.IFETCH.miss_latency_hist_seqr::gmean 73.901725 +system.ruby.IFETCH.miss_latency_hist_seqr::stdev 84.644758 +system.ruby.IFETCH.miss_latency_hist_seqr | 15 30.00% 30.00% | 31 62.00% 92.00% | 1 2.00% 94.00% | 0 0.00% 94.00% | 0 0.00% 94.00% | 2 4.00% 98.00% | 0 0.00% 98.00% | 1 2.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.miss_latency_hist_seqr::total 50 +system.ruby.Directory_Controller.GETX 796 0.00% 0.00% +system.ruby.Directory_Controller.GETS 85 0.00% 0.00% +system.ruby.Directory_Controller.PUTX 791 0.00% 0.00% +system.ruby.Directory_Controller.Unblock 81 0.00% 0.00% +system.ruby.Directory_Controller.Last_Unblock 3 0.00% 0.00% +system.ruby.Directory_Controller.Exclusive_Unblock 796 0.00% 0.00% +system.ruby.Directory_Controller.Dirty_Writeback 791 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 881 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 791 0.00% 0.00% +system.ruby.Directory_Controller.I.GETX 735 0.00% 0.00% +system.ruby.Directory_Controller.I.GETS 82 0.00% 0.00% +system.ruby.Directory_Controller.I.Memory_Ack 791 0.00% 0.00% +system.ruby.Directory_Controller.S.GETX 61 0.00% 0.00% +system.ruby.Directory_Controller.S.GETS 3 0.00% 0.00% +system.ruby.Directory_Controller.M.PUTX 791 0.00% 0.00% +system.ruby.Directory_Controller.IS.Unblock 81 0.00% 0.00% +system.ruby.Directory_Controller.IS.Memory_Data 82 0.00% 0.00% +system.ruby.Directory_Controller.SS.Last_Unblock 3 0.00% 0.00% +system.ruby.Directory_Controller.SS.Memory_Data 3 0.00% 0.00% +system.ruby.Directory_Controller.MM.Exclusive_Unblock 796 0.00% 0.00% +system.ruby.Directory_Controller.MM.Memory_Data 796 0.00% 0.00% +system.ruby.Directory_Controller.MI.Dirty_Writeback 791 0.00% 0.00% +system.ruby.L1Cache_Controller.Load 48 0.00% 0.00% +system.ruby.L1Cache_Controller.Ifetch 64 0.00% 0.00% +system.ruby.L1Cache_Controller.Store 905 0.00% 0.00% +system.ruby.L1Cache_Controller.L1_Replacement 84079 0.00% 0.00% +system.ruby.L1Cache_Controller.Data 85 0.00% 0.00% +system.ruby.L1Cache_Controller.Exclusive_Data 824 0.00% 0.00% +system.ruby.L1Cache_Controller.Writeback_Ack_Data 904 0.00% 0.00% +system.ruby.L1Cache_Controller.All_acks 818 0.00% 0.00% +system.ruby.L1Cache_Controller.Use_Timeout 823 0.00% 0.00% +system.ruby.L1Cache_Controller.I.Load 41 0.00% 0.00% +system.ruby.L1Cache_Controller.I.Ifetch 50 0.00% 0.00% +system.ruby.L1Cache_Controller.I.Store 818 0.00% 0.00% +system.ruby.L1Cache_Controller.S.Ifetch 2 0.00% 0.00% +system.ruby.L1Cache_Controller.S.L1_Replacement 82 0.00% 0.00% +system.ruby.L1Cache_Controller.M.L1_Replacement 5 0.00% 0.00% +system.ruby.L1Cache_Controller.M_W.Use_Timeout 6 0.00% 0.00% +system.ruby.L1Cache_Controller.MM.Load 7 0.00% 0.00% +system.ruby.L1Cache_Controller.MM.Store 70 0.00% 0.00% +system.ruby.L1Cache_Controller.MM.L1_Replacement 817 0.00% 0.00% +system.ruby.L1Cache_Controller.MM_W.Store 11 0.00% 0.00% +system.ruby.L1Cache_Controller.MM_W.L1_Replacement 31468 0.00% 0.00% +system.ruby.L1Cache_Controller.MM_W.Use_Timeout 817 0.00% 0.00% +system.ruby.L1Cache_Controller.IM.L1_Replacement 48874 0.00% 0.00% +system.ruby.L1Cache_Controller.IM.Exclusive_Data 818 0.00% 0.00% +system.ruby.L1Cache_Controller.OM.L1_Replacement 674 0.00% 0.00% +system.ruby.L1Cache_Controller.OM.All_acks 818 0.00% 0.00% +system.ruby.L1Cache_Controller.IS.L1_Replacement 2159 0.00% 0.00% +system.ruby.L1Cache_Controller.IS.Data 85 0.00% 0.00% +system.ruby.L1Cache_Controller.IS.Exclusive_Data 6 0.00% 0.00% +system.ruby.L1Cache_Controller.SI.Writeback_Ack_Data 82 0.00% 0.00% +system.ruby.L1Cache_Controller.MI.Ifetch 12 0.00% 0.00% +system.ruby.L1Cache_Controller.MI.Store 6 0.00% 0.00% +system.ruby.L1Cache_Controller.MI.Writeback_Ack_Data 822 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_GETS 91 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_GETX 818 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_PUTX 822 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_PUTS_only 82 0.00% 0.00% +system.ruby.L2Cache_Controller.All_Acks 796 0.00% 0.00% +system.ruby.L2Cache_Controller.Data 881 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_WBCLEANDATA 82 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_WBDIRTYDATA 822 0.00% 0.00% +system.ruby.L2Cache_Controller.Writeback_Ack 791 0.00% 0.00% +system.ruby.L2Cache_Controller.Unblock 84 0.00% 0.00% +system.ruby.L2Cache_Controller.Exclusive_Unblock 824 0.00% 0.00% +system.ruby.L2Cache_Controller.L2_Replacement 873 0.00% 0.00% +system.ruby.L2Cache_Controller.NP.L1_GETS 85 0.00% 0.00% +system.ruby.L2Cache_Controller.NP.L1_GETX 796 0.00% 0.00% +system.ruby.L2Cache_Controller.ILS.L1_PUTS_only 82 0.00% 0.00% +system.ruby.L2Cache_Controller.ILX.L1_PUTX 822 0.00% 0.00% +system.ruby.L2Cache_Controller.S.L2_Replacement 82 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L1_GETS 6 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L1_GETX 22 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L2_Replacement 791 0.00% 0.00% +system.ruby.L2Cache_Controller.IW.L1_WBCLEANDATA 82 0.00% 0.00% +system.ruby.L2Cache_Controller.ILXW.L1_WBDIRTYDATA 822 0.00% 0.00% +system.ruby.L2Cache_Controller.IGS.Data 85 0.00% 0.00% +system.ruby.L2Cache_Controller.IGS.Unblock 84 0.00% 0.00% +system.ruby.L2Cache_Controller.IGM.Data 796 0.00% 0.00% +system.ruby.L2Cache_Controller.IGMO.All_Acks 796 0.00% 0.00% +system.ruby.L2Cache_Controller.IGMO.Exclusive_Unblock 796 0.00% 0.00% +system.ruby.L2Cache_Controller.MM.Exclusive_Unblock 22 0.00% 0.00% +system.ruby.L2Cache_Controller.OO.Exclusive_Unblock 6 0.00% 0.00% +system.ruby.L2Cache_Controller.MI.Writeback_Ack 791 0.00% 0.00% ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/config.ini b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/config.ini index 0143ed036..baeaaa8d5 100644 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/config.ini +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/config.ini @@ -14,6 +14,7 @@ children=clk_domain cpu dvfs_handler mem_ctrls ruby sys_port_proxy voltage_domai boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 exit_on_work_items=false init_param=0 @@ -22,11 +23,15 @@ kernel_addr_check=true load_addr_mask=1099511627775 load_offset=0 mem_mode=timing -mem_ranges=0:268435455 +mem_ranges=0:268435455:0:0:0:0 memories=system.mem_ctrls mmap_using_noreserve=false multi_thread=false num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null readfile= symbolfile= thermal_components= @@ -54,8 +59,13 @@ check_flush=false checks_to_complete=100 clk_domain=system.clk_domain deadlock_threshold=50000 +default_p_state=UNDEFINED eventq_index=0 num_cpus=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null system=system wakeup_frequency=10 cpuInstDataPort=system.ruby.l1_cntrl0.sequencer.slave[0] @@ -70,27 +80,27 @@ transition_latency=100000 [system.mem_ctrls] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -102,6 +112,7 @@ burst_length=8 channels=1 clk_domain=system.clk_domain conf_table_reported=true +default_p_state=UNDEFINED device_bus_width=8 device_rowbuffer_size=1024 device_size=536870912 @@ -109,12 +120,17 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 page_policy=open_adaptive -range=0:268435455 +power_model=Null +range=0:268435455:5:19:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10 @@ -136,9 +152,9 @@ tRTW=3 tWR=15 tWTR=8 tXAW=30 -tXP=0 +tXP=6 tXPDLL=0 -tXS=0 +tXS=270 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 @@ -152,12 +168,17 @@ access_backing_store=false all_instructions=false block_size_bytes=64 clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED eventq_index=0 hot_lines=false memory_size_bits=48 num_of_sequencers=1 number_of_virtual_networks=6 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 phys_mem=Null +power_model=Null randomization=true [system.ruby.clk_domain] @@ -174,6 +195,7 @@ children=directory dmaRequestToDir dmaResponseFromDir persistentFromDir persiste buffer_size=0 clk_domain=system.ruby.clk_domain cluster_id=0 +default_p_state=UNDEFINED directory=system.ruby.dir_cntrl0.directory directory_latency=5 distributed_persistent=true @@ -183,8 +205,12 @@ eventq_index=0 fixed_timeout_latency=100 l2_select_num_bits=0 number_of_TBEs=256 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 persistentFromDir=system.ruby.dir_cntrl0.persistentFromDir persistentToDir=system.ruby.dir_cntrl0.persistentToDir +power_model=Null recycle_latency=10 reissue_wakeup_latency=10 requestFromDir=system.ruby.dir_cntrl0.requestFromDir @@ -286,6 +312,7 @@ N_tokens=2 buffer_size=0 clk_domain=system.ruby.clk_domain cluster_id=0 +default_p_state=UNDEFINED dynamic_timeout_enabled=true eventq_index=0 fixed_timeout_latency=300 @@ -295,8 +322,12 @@ l2_select_num_bits=0 mandatoryQueue=system.ruby.l1_cntrl0.mandatoryQueue no_mig_atomic=true number_of_TBEs=256 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 persistentFromL1Cache=system.ruby.l1_cntrl0.persistentFromL1Cache persistentToL1Cache=system.ruby.l1_cntrl0.persistentToL1Cache +power_model=Null recycle_latency=10 reissue_wakeup_latency=10 requestFromL1Cache=system.ruby.l1_cntrl0.requestFromL1Cache @@ -422,17 +453,22 @@ coreid=99 dcache=system.ruby.l1_cntrl0.L1Dcache dcache_hit_latency=1 deadlock_threshold=500000 +default_p_state=UNDEFINED eventq_index=0 +garnet_standalone=false icache=system.ruby.l1_cntrl0.L1Icache icache_hit_latency=1 is_cpu_sequencer=true max_outstanding_requests=16 no_retry_on_stall=true +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null ruby_system=system.ruby support_data_reqs=true support_inst_reqs=true system=system -using_network_tester=false using_ruby_tester=true version=0 slave=system.cpu.cpuInstDataPort[0] @@ -449,12 +485,17 @@ N_tokens=2 buffer_size=0 clk_domain=system.ruby.clk_domain cluster_id=0 +default_p_state=UNDEFINED eventq_index=0 filtering_enabled=true l2_request_latency=5 l2_response_latency=5 number_of_TBEs=256 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 persistentToL2Cache=system.ruby.l2_cntrl0.persistentToL2Cache +power_model=Null recycle_latency=10 responseFromL2Cache=system.ruby.l2_cntrl0.responseFromL2Cache responseToL2Cache=system.ruby.l2_cntrl0.responseToL2Cache @@ -551,18 +592,23 @@ eventq_index=0 [system.ruby.network] type=SimpleNetwork -children=ext_links0 ext_links1 ext_links2 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_link_buffers20 int_link_buffers21 int_link_buffers22 int_link_buffers23 int_link_buffers24 int_link_buffers25 int_link_buffers26 int_link_buffers27 int_link_buffers28 int_link_buffers29 int_link_buffers30 int_link_buffers31 int_link_buffers32 int_link_buffers33 int_link_buffers34 int_link_buffers35 int_links0 int_links1 int_links2 routers0 routers1 routers2 routers3 +children=ext_links0 ext_links1 ext_links2 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_link_buffers20 int_link_buffers21 int_link_buffers22 int_link_buffers23 int_link_buffers24 int_link_buffers25 int_link_buffers26 int_link_buffers27 int_link_buffers28 int_link_buffers29 int_link_buffers30 int_link_buffers31 int_link_buffers32 int_link_buffers33 int_link_buffers34 int_link_buffers35 int_link_buffers36 int_link_buffers37 int_link_buffers38 int_link_buffers39 int_link_buffers40 int_link_buffers41 int_link_buffers42 int_link_buffers43 int_link_buffers44 int_link_buffers45 int_link_buffers46 int_link_buffers47 int_link_buffers48 int_link_buffers49 int_link_buffers50 int_link_buffers51 int_link_buffers52 int_link_buffers53 int_link_buffers54 int_link_buffers55 int_link_buffers56 int_link_buffers57 int_link_buffers58 int_link_buffers59 int_link_buffers60 int_link_buffers61 int_link_buffers62 int_link_buffers63 int_link_buffers64 int_link_buffers65 int_link_buffers66 int_link_buffers67 int_link_buffers68 int_link_buffers69 int_link_buffers70 int_link_buffers71 int_links0 int_links1 int_links2 int_links3 int_links4 int_links5 routers0 routers1 routers2 routers3 adaptive_routing=false buffer_size=0 clk_domain=system.ruby.clk_domain control_msg_size=8 +default_p_state=UNDEFINED endpoint_bandwidth=1000 eventq_index=0 ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1 system.ruby.network.ext_links2 -int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19 system.ruby.network.int_link_buffers20 system.ruby.network.int_link_buffers21 system.ruby.network.int_link_buffers22 system.ruby.network.int_link_buffers23 system.ruby.network.int_link_buffers24 system.ruby.network.int_link_buffers25 system.ruby.network.int_link_buffers26 system.ruby.network.int_link_buffers27 system.ruby.network.int_link_buffers28 system.ruby.network.int_link_buffers29 system.ruby.network.int_link_buffers30 system.ruby.network.int_link_buffers31 system.ruby.network.int_link_buffers32 system.ruby.network.int_link_buffers33 system.ruby.network.int_link_buffers34 system.ruby.network.int_link_buffers35 -int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2 +int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19 system.ruby.network.int_link_buffers20 system.ruby.network.int_link_buffers21 system.ruby.network.int_link_buffers22 system.ruby.network.int_link_buffers23 system.ruby.network.int_link_buffers24 system.ruby.network.int_link_buffers25 system.ruby.network.int_link_buffers26 system.ruby.network.int_link_buffers27 system.ruby.network.int_link_buffers28 system.ruby.network.int_link_buffers29 system.ruby.network.int_link_buffers30 system.ruby.network.int_link_buffers31 system.ruby.network.int_link_buffers32 system.ruby.network.int_link_buffers33 system.ruby.network.int_link_buffers34 system.ruby.network.int_link_buffers35 system.ruby.network.int_link_buffers36 system.ruby.network.int_link_buffers37 system.ruby.network.int_link_buffers38 system.ruby.network.int_link_buffers39 system.ruby.network.int_link_buffers40 system.ruby.network.int_link_buffers41 system.ruby.network.int_link_buffers42 system.ruby.network.int_link_buffers43 system.ruby.network.int_link_buffers44 system.ruby.network.int_link_buffers45 system.ruby.network.int_link_buffers46 system.ruby.network.int_link_buffers47 system.ruby.network.int_link_buffers48 system.ruby.network.int_link_buffers49 system.ruby.network.int_link_buffers50 system.ruby.network.int_link_buffers51 system.ruby.network.int_link_buffers52 system.ruby.network.int_link_buffers53 system.ruby.network.int_link_buffers54 system.ruby.network.int_link_buffers55 system.ruby.network.int_link_buffers56 system.ruby.network.int_link_buffers57 system.ruby.network.int_link_buffers58 system.ruby.network.int_link_buffers59 system.ruby.network.int_link_buffers60 system.ruby.network.int_link_buffers61 system.ruby.network.int_link_buffers62 system.ruby.network.int_link_buffers63 system.ruby.network.int_link_buffers64 system.ruby.network.int_link_buffers65 system.ruby.network.int_link_buffers66 system.ruby.network.int_link_buffers67 system.ruby.network.int_link_buffers68 system.ruby.network.int_link_buffers69 system.ruby.network.int_link_buffers70 system.ruby.network.int_link_buffers71 +int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2 system.ruby.network.int_links3 system.ruby.network.int_links4 system.ruby.network.int_links5 netifs= number_of_virtual_networks=6 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null routers=system.ruby.network.routers0 system.ruby.network.routers1 system.ruby.network.routers2 system.ruby.network.routers3 ruby_system=system.ruby topology=Crossbar @@ -851,42 +897,342 @@ eventq_index=0 ordered=true randomization=false +[system.ruby.network.int_link_buffers36] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers37] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers38] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers39] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers40] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers41] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers42] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers43] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers44] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers45] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers46] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers47] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers48] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers49] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers50] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers51] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers52] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers53] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers54] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers55] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers56] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers57] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers58] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers59] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers60] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers61] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers62] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers63] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers64] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers65] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers66] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers67] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers68] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers69] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers70] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers71] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + [system.ruby.network.int_links0] type=SimpleIntLink bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers3 eventq_index=0 latency=1 link_id=3 -node_a=system.ruby.network.routers0 -node_b=system.ruby.network.routers3 +src_node=system.ruby.network.routers0 +src_outport= weight=1 [system.ruby.network.int_links1] type=SimpleIntLink bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers3 eventq_index=0 latency=1 link_id=4 -node_a=system.ruby.network.routers1 -node_b=system.ruby.network.routers3 +src_node=system.ruby.network.routers1 +src_outport= weight=1 [system.ruby.network.int_links2] type=SimpleIntLink bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers3 eventq_index=0 latency=1 link_id=5 -node_a=system.ruby.network.routers2 -node_b=system.ruby.network.routers3 +src_node=system.ruby.network.routers2 +src_outport= +weight=1 + +[system.ruby.network.int_links3] +type=SimpleIntLink +bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers0 +eventq_index=0 +latency=1 +link_id=6 +src_node=system.ruby.network.routers3 +src_outport= +weight=1 + +[system.ruby.network.int_links4] +type=SimpleIntLink +bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers1 +eventq_index=0 +latency=1 +link_id=7 +src_node=system.ruby.network.routers3 +src_outport= +weight=1 + +[system.ruby.network.int_links5] +type=SimpleIntLink +bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers2 +eventq_index=0 +latency=1 +link_id=8 +src_node=system.ruby.network.routers3 +src_outport= weight=1 [system.ruby.network.routers0] type=Switch children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17 port_buffers18 port_buffers19 port_buffers20 port_buffers21 port_buffers22 port_buffers23 clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED eventq_index=0 +latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 port_buffers=system.ruby.network.routers0.port_buffers00 system.ruby.network.routers0.port_buffers01 system.ruby.network.routers0.port_buffers02 system.ruby.network.routers0.port_buffers03 system.ruby.network.routers0.port_buffers04 system.ruby.network.routers0.port_buffers05 system.ruby.network.routers0.port_buffers06 system.ruby.network.routers0.port_buffers07 system.ruby.network.routers0.port_buffers08 system.ruby.network.routers0.port_buffers09 system.ruby.network.routers0.port_buffers10 system.ruby.network.routers0.port_buffers11 system.ruby.network.routers0.port_buffers12 system.ruby.network.routers0.port_buffers13 system.ruby.network.routers0.port_buffers14 system.ruby.network.routers0.port_buffers15 system.ruby.network.routers0.port_buffers16 system.ruby.network.routers0.port_buffers17 system.ruby.network.routers0.port_buffers18 system.ruby.network.routers0.port_buffers19 system.ruby.network.routers0.port_buffers20 system.ruby.network.routers0.port_buffers21 system.ruby.network.routers0.port_buffers22 system.ruby.network.routers0.port_buffers23 +power_model=Null router_id=0 virt_nets=6 @@ -1062,8 +1408,14 @@ randomization=false type=Switch children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17 port_buffers18 port_buffers19 port_buffers20 port_buffers21 port_buffers22 port_buffers23 clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED eventq_index=0 +latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 port_buffers=system.ruby.network.routers1.port_buffers00 system.ruby.network.routers1.port_buffers01 system.ruby.network.routers1.port_buffers02 system.ruby.network.routers1.port_buffers03 system.ruby.network.routers1.port_buffers04 system.ruby.network.routers1.port_buffers05 system.ruby.network.routers1.port_buffers06 system.ruby.network.routers1.port_buffers07 system.ruby.network.routers1.port_buffers08 system.ruby.network.routers1.port_buffers09 system.ruby.network.routers1.port_buffers10 system.ruby.network.routers1.port_buffers11 system.ruby.network.routers1.port_buffers12 system.ruby.network.routers1.port_buffers13 system.ruby.network.routers1.port_buffers14 system.ruby.network.routers1.port_buffers15 system.ruby.network.routers1.port_buffers16 system.ruby.network.routers1.port_buffers17 system.ruby.network.routers1.port_buffers18 system.ruby.network.routers1.port_buffers19 system.ruby.network.routers1.port_buffers20 system.ruby.network.routers1.port_buffers21 system.ruby.network.routers1.port_buffers22 system.ruby.network.routers1.port_buffers23 +power_model=Null router_id=1 virt_nets=6 @@ -1239,8 +1591,14 @@ randomization=false type=Switch children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17 port_buffers18 port_buffers19 port_buffers20 port_buffers21 port_buffers22 port_buffers23 clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED eventq_index=0 +latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 port_buffers=system.ruby.network.routers2.port_buffers00 system.ruby.network.routers2.port_buffers01 system.ruby.network.routers2.port_buffers02 system.ruby.network.routers2.port_buffers03 system.ruby.network.routers2.port_buffers04 system.ruby.network.routers2.port_buffers05 system.ruby.network.routers2.port_buffers06 system.ruby.network.routers2.port_buffers07 system.ruby.network.routers2.port_buffers08 system.ruby.network.routers2.port_buffers09 system.ruby.network.routers2.port_buffers10 system.ruby.network.routers2.port_buffers11 system.ruby.network.routers2.port_buffers12 system.ruby.network.routers2.port_buffers13 system.ruby.network.routers2.port_buffers14 system.ruby.network.routers2.port_buffers15 system.ruby.network.routers2.port_buffers16 system.ruby.network.routers2.port_buffers17 system.ruby.network.routers2.port_buffers18 system.ruby.network.routers2.port_buffers19 system.ruby.network.routers2.port_buffers20 system.ruby.network.routers2.port_buffers21 system.ruby.network.routers2.port_buffers22 system.ruby.network.routers2.port_buffers23 +power_model=Null router_id=2 virt_nets=6 @@ -1416,8 +1774,14 @@ randomization=false type=Switch children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17 port_buffers18 port_buffers19 port_buffers20 port_buffers21 port_buffers22 port_buffers23 port_buffers24 port_buffers25 port_buffers26 port_buffers27 port_buffers28 port_buffers29 port_buffers30 port_buffers31 port_buffers32 port_buffers33 port_buffers34 port_buffers35 clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED eventq_index=0 +latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 port_buffers=system.ruby.network.routers3.port_buffers00 system.ruby.network.routers3.port_buffers01 system.ruby.network.routers3.port_buffers02 system.ruby.network.routers3.port_buffers03 system.ruby.network.routers3.port_buffers04 system.ruby.network.routers3.port_buffers05 system.ruby.network.routers3.port_buffers06 system.ruby.network.routers3.port_buffers07 system.ruby.network.routers3.port_buffers08 system.ruby.network.routers3.port_buffers09 system.ruby.network.routers3.port_buffers10 system.ruby.network.routers3.port_buffers11 system.ruby.network.routers3.port_buffers12 system.ruby.network.routers3.port_buffers13 system.ruby.network.routers3.port_buffers14 system.ruby.network.routers3.port_buffers15 system.ruby.network.routers3.port_buffers16 system.ruby.network.routers3.port_buffers17 system.ruby.network.routers3.port_buffers18 system.ruby.network.routers3.port_buffers19 system.ruby.network.routers3.port_buffers20 system.ruby.network.routers3.port_buffers21 system.ruby.network.routers3.port_buffers22 system.ruby.network.routers3.port_buffers23 system.ruby.network.routers3.port_buffers24 system.ruby.network.routers3.port_buffers25 system.ruby.network.routers3.port_buffers26 system.ruby.network.routers3.port_buffers27 system.ruby.network.routers3.port_buffers28 system.ruby.network.routers3.port_buffers29 system.ruby.network.routers3.port_buffers30 system.ruby.network.routers3.port_buffers31 system.ruby.network.routers3.port_buffers32 system.ruby.network.routers3.port_buffers33 system.ruby.network.routers3.port_buffers34 system.ruby.network.routers3.port_buffers35 +power_model=Null router_id=3 virt_nets=6 @@ -1676,9 +2040,14 @@ randomization=false [system.sys_port_proxy] type=RubyPortProxy clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 is_cpu_sequencer=true no_retry_on_stall=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null ruby_system=system.ruby support_data_reqs=true support_inst_reqs=true diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simerr b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simerr index c2086c0ba..cee0dfc57 100755 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simerr +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simerr @@ -4,7 +4,5 @@ warn: rounding error > tolerance 1.250000 rounded to 1 warn: rounding error > tolerance 1.250000 rounded to 1 -warn: rounding error > tolerance - 1.250000 rounded to 1 warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes) warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files! diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simout b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simout index 583f49075..135163955 100755 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simout +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simout @@ -1,11 +1,13 @@ +Redirecting stdout to build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_token/simout +Redirecting stderr to build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_token/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 21 2016 14:12:23 -gem5 started Jan 21 2016 14:12:59 -gem5 executing on zizzer, pid 55402 -command line: build/ALPHA_MOESI_CMP_token/gem5.opt -d build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_token -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_token +gem5 compiled Oct 13 2016 20:33:48 +gem5 started Oct 13 2016 20:34:17 +gem5 executing on e108600-lin, pid 27528 +command line: /work/curdun01/gem5-external.hg/build/ALPHA_MOESI_CMP_token/gem5.opt -d build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_token -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_token Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 50141 because Ruby Tester completed +Exiting @ tick 53801 because Ruby Tester completed diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt index 22bd0b2f6..e0aa11056 100644 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt @@ -1,45 +1,45 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000050 # Number of seconds simulated -sim_ticks 50141 # Number of ticks simulated -final_tick 50141 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000054 # Number of seconds simulated +sim_ticks 53801 # Number of ticks simulated +final_tick 53801 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 922495 # Simulator tick rate (ticks/s) -host_mem_usage 453168 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host +host_tick_rate 784976 # Simulator tick rate (ticks/s) +host_mem_usage 409916 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks -system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 50141 # Cumulative time (in ticks) in various power states -system.mem_ctrls.bytes_read::ruby.dir_cntrl0 50624 # Number of bytes read from this memory -system.mem_ctrls.bytes_read::total 50624 # Number of bytes read from this memory -system.mem_ctrls.bytes_written::ruby.dir_cntrl0 46016 # Number of bytes written to this memory -system.mem_ctrls.bytes_written::total 46016 # Number of bytes written to this memory -system.mem_ctrls.num_reads::ruby.dir_cntrl0 791 # Number of read requests responded to by this memory -system.mem_ctrls.num_reads::total 791 # Number of read requests responded to by this memory -system.mem_ctrls.num_writes::ruby.dir_cntrl0 719 # Number of write requests responded to by this memory -system.mem_ctrls.num_writes::total 719 # Number of write requests responded to by this memory -system.mem_ctrls.bw_read::ruby.dir_cntrl0 1009632835 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_read::total 1009632835 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::ruby.dir_cntrl0 917731996 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::total 917731996 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_total::ruby.dir_cntrl0 1927364831 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.bw_total::total 1927364831 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.readReqs 791 # Number of read requests accepted -system.mem_ctrls.writeReqs 719 # Number of write requests accepted -system.mem_ctrls.readBursts 791 # Number of DRAM read bursts, including those serviced by the write queue -system.mem_ctrls.writeBursts 719 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrls.bytesReadDRAM 42944 # Total number of bytes read from DRAM -system.mem_ctrls.bytesReadWrQ 7680 # Total number of bytes read from write queue -system.mem_ctrls.bytesWritten 39296 # Total number of bytes written to DRAM -system.mem_ctrls.bytesReadSys 50624 # Total read bytes from the system interface side -system.mem_ctrls.bytesWrittenSys 46016 # Total written bytes from the system interface side -system.mem_ctrls.servicedByWrQ 120 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrls.mergedWrBursts 81 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 53801 # Cumulative time (in ticks) in various power states +system.mem_ctrls.bytes_read::ruby.dir_cntrl0 52672 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 52672 # Number of bytes read from this memory +system.mem_ctrls.bytes_written::ruby.dir_cntrl0 47552 # Number of bytes written to this memory +system.mem_ctrls.bytes_written::total 47552 # Number of bytes written to this memory +system.mem_ctrls.num_reads::ruby.dir_cntrl0 823 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 823 # Number of read requests responded to by this memory +system.mem_ctrls.num_writes::ruby.dir_cntrl0 743 # Number of write requests responded to by this memory +system.mem_ctrls.num_writes::total 743 # Number of write requests responded to by this memory +system.mem_ctrls.bw_read::ruby.dir_cntrl0 979015260 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 979015260 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::ruby.dir_cntrl0 883849743 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::total 883849743 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::ruby.dir_cntrl0 1862865003 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 1862865003 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.readReqs 824 # Number of read requests accepted +system.mem_ctrls.writeReqs 743 # Number of write requests accepted +system.mem_ctrls.readBursts 824 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 743 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.bytesReadDRAM 43776 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 8960 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 40320 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 52736 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 47552 # Total written bytes from the system interface side +system.mem_ctrls.servicedByWrQ 140 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 90 # Number of DRAM write bursts merged with an existing one system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.mem_ctrls.perBankRdBursts::0 208 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::1 221 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::2 189 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::3 53 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::0 217 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 193 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 224 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 50 # Per bank write bursts system.mem_ctrls.perBankRdBursts::4 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::5 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::6 0 # Per bank write bursts @@ -52,10 +52,10 @@ system.mem_ctrls.perBankRdBursts::12 0 # Pe system.mem_ctrls.perBankRdBursts::13 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::14 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::15 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::0 189 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::1 195 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::2 180 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::3 50 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 196 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 186 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 201 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 47 # Per bank write bursts system.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts @@ -70,24 +70,24 @@ system.mem_ctrls.perBankWrBursts::14 0 # Pe system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrls.totGap 50084 # Total gap between requests +system.mem_ctrls.totGap 53772 # Total gap between requests system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::6 791 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 824 # Read request sizes (log2) system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::6 719 # Write request sizes (log2) -system.mem_ctrls.rdQLenPdf::0 557 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::1 111 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::2 3 # What read queue length does an incoming req see +system.mem_ctrls.writePktSize::6 743 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 527 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 156 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::2 1 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -132,24 +132,24 @@ system.mem_ctrls.wrQLenPdf::11 1 # Wh system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::15 3 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 4 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::16 4 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::17 20 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::18 40 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::19 42 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::20 43 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 43 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 44 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::21 41 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::22 40 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::23 41 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::24 40 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::25 39 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::26 42 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::27 38 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::28 38 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::29 38 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::30 38 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::31 38 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::32 38 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 41 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 39 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::24 41 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 40 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 41 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 45 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::28 39 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 39 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 39 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 39 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::32 39 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see @@ -181,543 +181,531 @@ system.mem_ctrls.wrQLenPdf::60 0 # Wh system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrls.bytesPerActivate::samples 89 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::mean 910.382022 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::gmean 810.808230 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::stdev 274.216052 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::0-127 2 2.25% 2.25% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::128-255 5 5.62% 7.87% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::256-383 2 2.25% 10.11% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::384-511 1 1.12% 11.24% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::512-639 1 1.12% 12.36% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::640-767 2 2.25% 14.61% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::768-895 1 1.12% 15.73% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::896-1023 3 3.37% 19.10% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::1024-1151 72 80.90% 100.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::total 89 # Bytes accessed per row activation -system.mem_ctrls.rdPerTurnAround::samples 38 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::mean 17.394737 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::gmean 17.106045 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::stdev 3.831163 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::14-15 8 21.05% 21.05% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::16-17 18 47.37% 68.42% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::18-19 7 18.42% 86.84% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::20-21 3 7.89% 94.74% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::22-23 1 2.63% 97.37% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::36-37 1 2.63% 100.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::total 38 # Reads before turning the bus around for writes -system.mem_ctrls.wrPerTurnAround::samples 38 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::mean 16.157895 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::gmean 16.145372 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::stdev 0.678883 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::16 36 94.74% 94.74% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::19 2 5.26% 100.00% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::total 38 # Writes before turning the bus around for reads -system.mem_ctrls.totQLat 8848 # Total ticks spent queuing -system.mem_ctrls.totMemAccLat 21597 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrls.totBusLat 3355 # Total ticks spent in databus transfers -system.mem_ctrls.avgQLat 13.19 # Average queueing delay per DRAM burst +system.mem_ctrls.bytesPerActivate::samples 90 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 916.622222 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 830.573922 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 254.887972 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 1 1.11% 1.11% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 5 5.56% 6.67% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 1 1.11% 7.78% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 2 2.22% 10.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 3 3.33% 13.33% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 4 4.44% 17.78% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 4 4.44% 22.22% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 70 77.78% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 90 # Bytes accessed per row activation +system.mem_ctrls.rdPerTurnAround::samples 39 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::mean 17.282051 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::gmean 16.989006 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::stdev 3.886202 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::12-13 1 2.56% 2.56% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::14-15 8 20.51% 23.08% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::16-17 18 46.15% 69.23% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::18-19 8 20.51% 89.74% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::20-21 2 5.13% 94.87% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::22-23 1 2.56% 97.44% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::38-39 1 2.56% 100.00% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::total 39 # Reads before turning the bus around for writes +system.mem_ctrls.wrPerTurnAround::samples 39 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::mean 16.153846 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::gmean 16.145622 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::stdev 0.539906 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::16 36 92.31% 92.31% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::18 3 7.69% 100.00% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::total 39 # Writes before turning the bus around for reads +system.mem_ctrls.totQLat 11889 # Total ticks spent queuing +system.mem_ctrls.totMemAccLat 24885 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.totBusLat 3420 # Total ticks spent in databus transfers +system.mem_ctrls.avgQLat 17.38 # Average queueing delay per DRAM burst system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst -system.mem_ctrls.avgMemAccLat 32.19 # Average memory access latency per DRAM burst -system.mem_ctrls.avgRdBW 856.46 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrls.avgWrBW 783.71 # Average achieved write bandwidth in MiByte/s -system.mem_ctrls.avgRdBWSys 1009.63 # Average system read bandwidth in MiByte/s -system.mem_ctrls.avgWrBWSys 917.73 # Average system write bandwidth in MiByte/s +system.mem_ctrls.avgMemAccLat 36.38 # Average memory access latency per DRAM burst +system.mem_ctrls.avgRdBW 813.67 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 749.43 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 980.20 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 883.85 # Average system write bandwidth in MiByte/s system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrls.busUtil 12.81 # Data bus utilization in percentage -system.mem_ctrls.busUtilRead 6.69 # Data bus utilization in percentage for reads -system.mem_ctrls.busUtilWrite 6.12 # Data bus utilization in percentage for writes -system.mem_ctrls.avgRdQLen 1.30 # Average read queue length when enqueuing -system.mem_ctrls.avgWrQLen 25.17 # Average write queue length when enqueuing -system.mem_ctrls.readRowHits 582 # Number of row buffer hits during reads -system.mem_ctrls.writeRowHits 610 # Number of row buffer hits during writes -system.mem_ctrls.readRowHitRate 86.74 # Row buffer hit rate for reads -system.mem_ctrls.writeRowHitRate 95.61 # Row buffer hit rate for writes -system.mem_ctrls.avgGap 33.17 # Average gap between requests -system.mem_ctrls.pageHitRate 91.06 # Row buffer hit rate, read and write combined -system.mem_ctrls_0.actEnergy 642600 # Energy for activate commands per rank (pJ) -system.mem_ctrls_0.preEnergy 357000 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_0.readEnergy 7775040 # Energy for read commands per rank (pJ) -system.mem_ctrls_0.writeEnergy 6003072 # Energy for write commands per rank (pJ) -system.mem_ctrls_0.refreshEnergy 3051360 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_0.actBackEnergy 32001624 # Energy for active background per rank (pJ) -system.mem_ctrls_0.preBackEnergy 114000 # Energy for precharge background per rank (pJ) -system.mem_ctrls_0.totalEnergy 49944696 # Total energy per rank (pJ) -system.mem_ctrls_0.averagePower 1063.196015 # Core power per rank (mW) -system.mem_ctrls_0.memoryStateTime::IDLE 22 # Time in different power states +system.mem_ctrls.busUtil 12.21 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 6.36 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 5.85 # Data bus utilization in percentage for writes +system.mem_ctrls.avgRdQLen 1.38 # Average read queue length when enqueuing +system.mem_ctrls.avgWrQLen 25.30 # Average write queue length when enqueuing +system.mem_ctrls.readRowHits 599 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 622 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 87.57 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate 95.25 # Row buffer hit rate for writes +system.mem_ctrls.avgGap 34.32 # Average gap between requests +system.mem_ctrls.pageHitRate 91.32 # Row buffer hit rate, read and write combined +system.mem_ctrls_0.actEnergy 664020 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 347760 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 7814016 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 5261760 # Energy for write commands per rank (pJ) +system.mem_ctrls_0.refreshEnergy 3687840.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 10048872 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 77568 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.actPowerDownEnergy 14391360 # Energy for active power-down per rank (pJ) +system.mem_ctrls_0.prePowerDownEnergy 768 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls_0.totalEnergy 42293964 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 786.118548 # Core power per rank (mW) +system.mem_ctrls_0.totalIdleTime 31562 # Total Idle time Per DRAM Rank +system.mem_ctrls_0.memoryStateTime::IDLE 34 # Time in different power states system.mem_ctrls_0.memoryStateTime::REF 1560 # Time in different power states -system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT 45408 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls_0.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls_0.memoryStateTime::PRE_PDN 2 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 20645 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT_PDN 31560 # Time in different power states system.mem_ctrls_1.actEnergy 0 # Energy for activate commands per rank (pJ) system.mem_ctrls_1.preEnergy 0 # Energy for precharge commands per rank (pJ) system.mem_ctrls_1.readEnergy 0 # Energy for read commands per rank (pJ) system.mem_ctrls_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.mem_ctrls_1.refreshEnergy 3051360 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_1.actBackEnergy 1009584 # Energy for active background per rank (pJ) -system.mem_ctrls_1.preBackEnergy 27291600 # Energy for precharge background per rank (pJ) -system.mem_ctrls_1.totalEnergy 31352544 # Total energy per rank (pJ) -system.mem_ctrls_1.averagePower 667.615178 # Core power per rank (mW) -system.mem_ctrls_1.memoryStateTime::IDLE 45416 # Time in different power states -system.mem_ctrls_1.memoryStateTime::REF 1560 # Time in different power states -system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_1.refreshEnergy 1229280.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 224352 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 3002880 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls_1.prePowerDownEnergy 2889984 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls_1.selfRefreshEnergy 9111120 # Energy for self refresh per rank (pJ) +system.mem_ctrls_1.totalEnergy 16457616 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 305.897957 # Core power per rank (mW) +system.mem_ctrls_1.totalIdleTime 7526 # Total Idle time Per DRAM Rank +system.mem_ctrls_1.memoryStateTime::IDLE 7786 # Time in different power states +system.mem_ctrls_1.memoryStateTime::REF 526 # Time in different power states +system.mem_ctrls_1.memoryStateTime::SREF 37963 # Time in different power states +system.mem_ctrls_1.memoryStateTime::PRE_PDN 7526 # Time in different power states system.mem_ctrls_1.memoryStateTime::ACT 0 # Time in different power states system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 50141 # Cumulative time (in ticks) in various power states -system.cpu.pwrStateResidencyTicks::UNDEFINED 50141 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 53801 # Cumulative time (in ticks) in various power states +system.cpu.pwrStateResidencyTicks::UNDEFINED 53801 # Cumulative time (in ticks) in various power states system.ruby.clk_domain.clock 1 # Clock period in ticks -system.ruby.pwrStateResidencyTicks::UNDEFINED 50141 # Cumulative time (in ticks) in various power states +system.ruby.pwrStateResidencyTicks::UNDEFINED 53801 # Cumulative time (in ticks) in various power states system.ruby.outstanding_req_hist_seqr::bucket_size 2 system.ruby.outstanding_req_hist_seqr::max_bucket 19 -system.ruby.outstanding_req_hist_seqr::samples 961 -system.ruby.outstanding_req_hist_seqr::mean 15.762747 -system.ruby.outstanding_req_hist_seqr::gmean 15.654325 -system.ruby.outstanding_req_hist_seqr::stdev 1.209298 -system.ruby.outstanding_req_hist_seqr | 1 0.10% 0.10% | 2 0.21% 0.31% | 2 0.21% 0.52% | 2 0.21% 0.73% | 4 0.42% 1.14% | 2 0.21% 1.35% | 3 0.31% 1.66% | 91 9.47% 11.13% | 854 88.87% 100.00% | 0 0.00% 100.00% -system.ruby.outstanding_req_hist_seqr::total 961 +system.ruby.outstanding_req_hist_seqr::samples 973 +system.ruby.outstanding_req_hist_seqr::mean 15.744090 +system.ruby.outstanding_req_hist_seqr::gmean 15.636746 +system.ruby.outstanding_req_hist_seqr::stdev 1.206668 +system.ruby.outstanding_req_hist_seqr | 1 0.10% 0.10% | 2 0.21% 0.31% | 2 0.21% 0.51% | 2 0.21% 0.72% | 4 0.41% 1.13% | 2 0.21% 1.34% | 3 0.31% 1.64% | 112 11.51% 13.16% | 845 86.84% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist_seqr::total 973 system.ruby.latency_hist_seqr::bucket_size 256 system.ruby.latency_hist_seqr::max_bucket 2559 -system.ruby.latency_hist_seqr::samples 946 -system.ruby.latency_hist_seqr::mean 831.747357 -system.ruby.latency_hist_seqr::gmean 353.331206 -system.ruby.latency_hist_seqr::stdev 440.661399 -system.ruby.latency_hist_seqr | 208 21.99% 21.99% | 7 0.74% 22.73% | 5 0.53% 23.26% | 262 27.70% 50.95% | 409 43.23% 94.19% | 55 5.81% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.latency_hist_seqr::total 946 +system.ruby.latency_hist_seqr::samples 958 +system.ruby.latency_hist_seqr::mean 879.328810 +system.ruby.latency_hist_seqr::gmean 422.320646 +system.ruby.latency_hist_seqr::stdev 422.809847 +system.ruby.latency_hist_seqr | 182 19.00% 19.00% | 6 0.63% 19.62% | 4 0.42% 20.04% | 214 22.34% 42.38% | 516 53.86% 96.24% | 36 3.76% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.latency_hist_seqr::total 958 system.ruby.hit_latency_hist_seqr::bucket_size 256 system.ruby.hit_latency_hist_seqr::max_bucket 2559 -system.ruby.hit_latency_hist_seqr::samples 156 -system.ruby.hit_latency_hist_seqr::mean 161.115385 -system.ruby.hit_latency_hist_seqr::gmean 5.208817 -system.ruby.hit_latency_hist_seqr::stdev 361.858143 -system.ruby.hit_latency_hist_seqr | 132 84.62% 84.62% | 0 0.00% 84.62% | 0 0.00% 84.62% | 17 10.90% 95.51% | 6 3.85% 99.36% | 1 0.64% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.hit_latency_hist_seqr::total 156 +system.ruby.hit_latency_hist_seqr::samples 136 +system.ruby.hit_latency_hist_seqr::mean 190.117647 +system.ruby.hit_latency_hist_seqr::gmean 5.669159 +system.ruby.hit_latency_hist_seqr::stdev 399.173351 +system.ruby.hit_latency_hist_seqr | 112 82.35% 82.35% | 0 0.00% 82.35% | 0 0.00% 82.35% | 10 7.35% 89.71% | 13 9.56% 99.26% | 1 0.74% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.hit_latency_hist_seqr::total 136 system.ruby.miss_latency_hist_seqr::bucket_size 256 system.ruby.miss_latency_hist_seqr::max_bucket 2559 -system.ruby.miss_latency_hist_seqr::samples 790 -system.ruby.miss_latency_hist_seqr::mean 964.175949 -system.ruby.miss_latency_hist_seqr::gmean 812.519909 -system.ruby.miss_latency_hist_seqr::stdev 316.811320 -system.ruby.miss_latency_hist_seqr | 76 9.62% 9.62% | 7 0.89% 10.51% | 5 0.63% 11.14% | 245 31.01% 42.15% | 403 51.01% 93.16% | 54 6.84% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.miss_latency_hist_seqr::total 790 -system.ruby.Directory.incomplete_times_seqr 790 -system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 50141 # Cumulative time (in ticks) in various power states -system.ruby.l1_cntrl0.L1Dcache.demand_hits 105 # Number of cache demand hits -system.ruby.l1_cntrl0.L1Dcache.demand_misses 788 # Number of cache demand misses -system.ruby.l1_cntrl0.L1Dcache.demand_accesses 893 # Number of cache demand accesses -system.ruby.l1_cntrl0.L1Icache.demand_hits 1 # Number of cache demand hits -system.ruby.l1_cntrl0.L1Icache.demand_misses 54 # Number of cache demand misses -system.ruby.l1_cntrl0.L1Icache.demand_accesses 55 # Number of cache demand accesses -system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 50141 # Cumulative time (in ticks) in various power states -system.ruby.l1_cntrl0.sequencer.store_waiting_on_load 6 # Number of times a store aliased with a pending load -system.ruby.l1_cntrl0.sequencer.store_waiting_on_store 74 # Number of times a store aliased with a pending store -system.ruby.l1_cntrl0.sequencer.load_waiting_on_store 6 # Number of times a load aliased with a pending store -system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 50141 # Cumulative time (in ticks) in various power states -system.ruby.l2_cntrl0.L2cache.demand_hits 48 # Number of cache demand hits -system.ruby.l2_cntrl0.L2cache.demand_misses 793 # Number of cache demand misses -system.ruby.l2_cntrl0.L2cache.demand_accesses 841 # Number of cache demand accesses -system.ruby.l2_cntrl0.pwrStateResidencyTicks::UNDEFINED 50141 # Cumulative time (in ticks) in various power states +system.ruby.miss_latency_hist_seqr::samples 822 +system.ruby.miss_latency_hist_seqr::mean 993.358881 +system.ruby.miss_latency_hist_seqr::gmean 861.758158 +system.ruby.miss_latency_hist_seqr::stdev 300.791358 +system.ruby.miss_latency_hist_seqr | 70 8.52% 8.52% | 6 0.73% 9.25% | 4 0.49% 9.73% | 204 24.82% 34.55% | 503 61.19% 95.74% | 35 4.26% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.miss_latency_hist_seqr::total 822 +system.ruby.Directory.incomplete_times_seqr 822 +system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 53801 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl0.L1Dcache.demand_hits 92 # Number of cache demand hits +system.ruby.l1_cntrl0.L1Dcache.demand_misses 820 # Number of cache demand misses +system.ruby.l1_cntrl0.L1Dcache.demand_accesses 912 # Number of cache demand accesses +system.ruby.l1_cntrl0.L1Icache.demand_hits 0 # Number of cache demand hits +system.ruby.l1_cntrl0.L1Icache.demand_misses 48 # Number of cache demand misses +system.ruby.l1_cntrl0.L1Icache.demand_accesses 48 # Number of cache demand accesses +system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 53801 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl0.sequencer.store_waiting_on_load 4 # Number of times a store aliased with a pending load +system.ruby.l1_cntrl0.sequencer.store_waiting_on_store 91 # Number of times a store aliased with a pending store +system.ruby.l1_cntrl0.sequencer.load_waiting_on_store 7 # Number of times a load aliased with a pending store +system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 53801 # Cumulative time (in ticks) in various power states +system.ruby.l2_cntrl0.L2cache.demand_hits 43 # Number of cache demand hits +system.ruby.l2_cntrl0.L2cache.demand_misses 825 # Number of cache demand misses +system.ruby.l2_cntrl0.L2cache.demand_accesses 868 # Number of cache demand accesses +system.ruby.l2_cntrl0.pwrStateResidencyTicks::UNDEFINED 53801 # Cumulative time (in ticks) in various power states system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 50141 # Cumulative time (in ticks) in various power states -system.ruby.network.routers0.percent_links_utilized 8.090684 -system.ruby.network.routers0.msg_count.Request_Control::1 841 -system.ruby.network.routers0.msg_count.Response_Data::4 790 -system.ruby.network.routers0.msg_count.ResponseL2hit_Data::4 50 -system.ruby.network.routers0.msg_count.Response_Control::4 1 -system.ruby.network.routers0.msg_count.Writeback_Data::4 862 -system.ruby.network.routers0.msg_count.Persistent_Control::3 68 -system.ruby.network.routers0.msg_bytes.Request_Control::1 6728 -system.ruby.network.routers0.msg_bytes.Response_Data::4 56880 -system.ruby.network.routers0.msg_bytes.ResponseL2hit_Data::4 3600 -system.ruby.network.routers0.msg_bytes.Response_Control::4 8 -system.ruby.network.routers0.msg_bytes.Writeback_Data::4 62064 -system.ruby.network.routers0.msg_bytes.Persistent_Control::3 544 -system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 50141 # Cumulative time (in ticks) in various power states -system.ruby.network.routers1.percent_links_utilized 8.057777 -system.ruby.network.routers1.msg_count.Request_Control::1 841 -system.ruby.network.routers1.msg_count.Request_Control::2 793 -system.ruby.network.routers1.msg_count.ResponseL2hit_Data::4 50 -system.ruby.network.routers1.msg_count.Response_Control::4 1 -system.ruby.network.routers1.msg_count.Writeback_Data::4 1553 -system.ruby.network.routers1.msg_count.Writeback_Control::4 65 -system.ruby.network.routers1.msg_count.Persistent_Control::3 34 -system.ruby.network.routers1.msg_bytes.Request_Control::1 6728 -system.ruby.network.routers1.msg_bytes.Request_Control::2 6344 -system.ruby.network.routers1.msg_bytes.ResponseL2hit_Data::4 3600 -system.ruby.network.routers1.msg_bytes.Response_Control::4 8 -system.ruby.network.routers1.msg_bytes.Writeback_Data::4 111816 -system.ruby.network.routers1.msg_bytes.Writeback_Control::4 520 -system.ruby.network.routers1.msg_bytes.Persistent_Control::3 272 -system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 50141 # Cumulative time (in ticks) in various power states -system.ruby.network.routers2.percent_links_utilized 7.216150 -system.ruby.network.routers2.msg_count.Request_Control::2 793 -system.ruby.network.routers2.msg_count.Response_Data::4 790 -system.ruby.network.routers2.msg_count.Writeback_Data::4 719 -system.ruby.network.routers2.msg_count.Writeback_Control::4 65 -system.ruby.network.routers2.msg_count.Persistent_Control::3 34 -system.ruby.network.routers2.msg_bytes.Request_Control::2 6344 -system.ruby.network.routers2.msg_bytes.Response_Data::4 56880 -system.ruby.network.routers2.msg_bytes.Writeback_Data::4 51768 -system.ruby.network.routers2.msg_bytes.Writeback_Control::4 520 -system.ruby.network.routers2.msg_bytes.Persistent_Control::3 272 -system.ruby.network.routers3.pwrStateResidencyTicks::UNDEFINED 50141 # Cumulative time (in ticks) in various power states -system.ruby.network.routers3.percent_links_utilized 7.788370 -system.ruby.network.routers3.msg_count.Request_Control::1 841 -system.ruby.network.routers3.msg_count.Request_Control::2 793 -system.ruby.network.routers3.msg_count.Response_Data::4 790 -system.ruby.network.routers3.msg_count.ResponseL2hit_Data::4 50 -system.ruby.network.routers3.msg_count.Response_Control::4 1 -system.ruby.network.routers3.msg_count.Writeback_Data::4 1567 -system.ruby.network.routers3.msg_count.Writeback_Control::4 65 -system.ruby.network.routers3.msg_count.Persistent_Control::3 68 -system.ruby.network.routers3.msg_bytes.Request_Control::1 6728 -system.ruby.network.routers3.msg_bytes.Request_Control::2 6344 -system.ruby.network.routers3.msg_bytes.Response_Data::4 56880 -system.ruby.network.routers3.msg_bytes.ResponseL2hit_Data::4 3600 -system.ruby.network.routers3.msg_bytes.Response_Control::4 8 -system.ruby.network.routers3.msg_bytes.Writeback_Data::4 112824 -system.ruby.network.routers3.msg_bytes.Writeback_Control::4 520 -system.ruby.network.routers3.msg_bytes.Persistent_Control::3 544 -system.ruby.network.pwrStateResidencyTicks::UNDEFINED 50141 # Cumulative time (in ticks) in various power states -system.ruby.network.msg_count.Request_Control 4902 -system.ruby.network.msg_count.Response_Data 2370 -system.ruby.network.msg_count.ResponseL2hit_Data 150 -system.ruby.network.msg_count.Response_Control 3 -system.ruby.network.msg_count.Writeback_Data 4701 -system.ruby.network.msg_count.Writeback_Control 195 -system.ruby.network.msg_count.Persistent_Control 204 -system.ruby.network.msg_byte.Request_Control 39216 -system.ruby.network.msg_byte.Response_Data 170640 -system.ruby.network.msg_byte.ResponseL2hit_Data 10800 -system.ruby.network.msg_byte.Response_Control 24 -system.ruby.network.msg_byte.Writeback_Data 338472 -system.ruby.network.msg_byte.Writeback_Control 1560 -system.ruby.network.msg_byte.Persistent_Control 1632 -system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 50141 # Cumulative time (in ticks) in various power states -system.ruby.network.routers0.throttle0.link_utilization 7.698291 -system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 790 -system.ruby.network.routers0.throttle0.msg_count.ResponseL2hit_Data::4 50 -system.ruby.network.routers0.throttle0.msg_count.Response_Control::4 1 -system.ruby.network.routers0.throttle0.msg_count.Writeback_Data::4 14 -system.ruby.network.routers0.throttle0.msg_count.Persistent_Control::3 34 -system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 56880 -system.ruby.network.routers0.throttle0.msg_bytes.ResponseL2hit_Data::4 3600 -system.ruby.network.routers0.throttle0.msg_bytes.Response_Control::4 8 -system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Data::4 1008 -system.ruby.network.routers0.throttle0.msg_bytes.Persistent_Control::3 272 -system.ruby.network.routers0.throttle1.link_utilization 8.483078 -system.ruby.network.routers0.throttle1.msg_count.Request_Control::1 841 -system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::4 848 -system.ruby.network.routers0.throttle1.msg_count.Persistent_Control::3 34 -system.ruby.network.routers0.throttle1.msg_bytes.Request_Control::1 6728 -system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::4 61056 -system.ruby.network.routers0.throttle1.msg_bytes.Persistent_Control::3 272 -system.ruby.network.routers1.throttle0.link_utilization 8.357432 -system.ruby.network.routers1.throttle0.msg_count.Request_Control::1 841 -system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::4 834 -system.ruby.network.routers1.throttle0.msg_count.Persistent_Control::3 34 -system.ruby.network.routers1.throttle0.msg_bytes.Request_Control::1 6728 -system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::4 60048 -system.ruby.network.routers1.throttle0.msg_bytes.Persistent_Control::3 272 -system.ruby.network.routers1.throttle1.link_utilization 7.758122 -system.ruby.network.routers1.throttle1.msg_count.Request_Control::2 793 -system.ruby.network.routers1.throttle1.msg_count.ResponseL2hit_Data::4 50 -system.ruby.network.routers1.throttle1.msg_count.Response_Control::4 1 -system.ruby.network.routers1.throttle1.msg_count.Writeback_Data::4 719 -system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::4 65 -system.ruby.network.routers1.throttle1.msg_bytes.Request_Control::2 6344 -system.ruby.network.routers1.throttle1.msg_bytes.ResponseL2hit_Data::4 3600 -system.ruby.network.routers1.throttle1.msg_bytes.Response_Control::4 8 -system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Data::4 51768 -system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::4 520 -system.ruby.network.routers2.throttle0.link_utilization 7.342295 -system.ruby.network.routers2.throttle0.msg_count.Request_Control::2 793 -system.ruby.network.routers2.throttle0.msg_count.Writeback_Data::4 719 -system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::4 65 -system.ruby.network.routers2.throttle0.msg_count.Persistent_Control::3 34 -system.ruby.network.routers2.throttle0.msg_bytes.Request_Control::2 6344 -system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Data::4 51768 -system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::4 520 -system.ruby.network.routers2.throttle0.msg_bytes.Persistent_Control::3 272 -system.ruby.network.routers2.throttle1.link_utilization 7.090006 -system.ruby.network.routers2.throttle1.msg_count.Response_Data::4 790 -system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::4 56880 -system.ruby.network.routers3.throttle0.link_utilization 7.665384 -system.ruby.network.routers3.throttle0.msg_count.Response_Data::4 790 -system.ruby.network.routers3.throttle0.msg_count.ResponseL2hit_Data::4 50 -system.ruby.network.routers3.throttle0.msg_count.Response_Control::4 1 -system.ruby.network.routers3.throttle0.msg_count.Writeback_Data::4 14 -system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::4 56880 -system.ruby.network.routers3.throttle0.msg_bytes.ResponseL2hit_Data::4 3600 -system.ruby.network.routers3.throttle0.msg_bytes.Response_Control::4 8 -system.ruby.network.routers3.throttle0.msg_bytes.Writeback_Data::4 1008 -system.ruby.network.routers3.throttle1.link_utilization 8.357432 -system.ruby.network.routers3.throttle1.msg_count.Request_Control::1 841 -system.ruby.network.routers3.throttle1.msg_count.Writeback_Data::4 834 -system.ruby.network.routers3.throttle1.msg_count.Persistent_Control::3 34 -system.ruby.network.routers3.throttle1.msg_bytes.Request_Control::1 6728 -system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::4 60048 -system.ruby.network.routers3.throttle1.msg_bytes.Persistent_Control::3 272 -system.ruby.network.routers3.throttle2.link_utilization 7.342295 -system.ruby.network.routers3.throttle2.msg_count.Request_Control::2 793 -system.ruby.network.routers3.throttle2.msg_count.Writeback_Data::4 719 -system.ruby.network.routers3.throttle2.msg_count.Writeback_Control::4 65 -system.ruby.network.routers3.throttle2.msg_count.Persistent_Control::3 34 -system.ruby.network.routers3.throttle2.msg_bytes.Request_Control::2 6344 -system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Data::4 51768 -system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Control::4 520 -system.ruby.network.routers3.throttle2.msg_bytes.Persistent_Control::3 272 +system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 53801 # Cumulative time (in ticks) in various power states +system.ruby.network.routers0.percent_links_utilized 7.774948 +system.ruby.network.routers0.msg_count.Request_Control::1 868 +system.ruby.network.routers0.msg_count.Response_Data::4 823 +system.ruby.network.routers0.msg_count.ResponseL2hit_Data::4 44 +system.ruby.network.routers0.msg_count.Writeback_Data::4 888 +system.ruby.network.routers0.msg_count.Persistent_Control::3 76 +system.ruby.network.routers0.msg_bytes.Request_Control::1 6944 +system.ruby.network.routers0.msg_bytes.Response_Data::4 59256 +system.ruby.network.routers0.msg_bytes.ResponseL2hit_Data::4 3168 +system.ruby.network.routers0.msg_bytes.Writeback_Data::4 63936 +system.ruby.network.routers0.msg_bytes.Persistent_Control::3 608 +system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 53801 # Cumulative time (in ticks) in various power states +system.ruby.network.routers1.percent_links_utilized 7.735451 +system.ruby.network.routers1.msg_count.Request_Control::1 868 +system.ruby.network.routers1.msg_count.Request_Control::2 825 +system.ruby.network.routers1.msg_count.ResponseL2hit_Data::4 44 +system.ruby.network.routers1.msg_count.Writeback_Data::4 1605 +system.ruby.network.routers1.msg_count.Writeback_Control::4 75 +system.ruby.network.routers1.msg_count.Persistent_Control::3 38 +system.ruby.network.routers1.msg_bytes.Request_Control::1 6944 +system.ruby.network.routers1.msg_bytes.Request_Control::2 6600 +system.ruby.network.routers1.msg_bytes.ResponseL2hit_Data::4 3168 +system.ruby.network.routers1.msg_bytes.Writeback_Data::4 115560 +system.ruby.network.routers1.msg_bytes.Writeback_Control::4 600 +system.ruby.network.routers1.msg_bytes.Persistent_Control::3 304 +system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 53801 # Cumulative time (in ticks) in various power states +system.ruby.network.routers2.percent_links_utilized 6.985000 +system.ruby.network.routers2.msg_count.Request_Control::2 825 +system.ruby.network.routers2.msg_count.Response_Data::4 823 +system.ruby.network.routers2.msg_count.Writeback_Data::4 743 +system.ruby.network.routers2.msg_count.Writeback_Control::4 75 +system.ruby.network.routers2.msg_count.Persistent_Control::3 38 +system.ruby.network.routers2.msg_bytes.Request_Control::2 6600 +system.ruby.network.routers2.msg_bytes.Response_Data::4 59256 +system.ruby.network.routers2.msg_bytes.Writeback_Data::4 53496 +system.ruby.network.routers2.msg_bytes.Writeback_Control::4 600 +system.ruby.network.routers2.msg_bytes.Persistent_Control::3 304 +system.ruby.network.routers3.pwrStateResidencyTicks::UNDEFINED 53801 # Cumulative time (in ticks) in various power states +system.ruby.network.routers3.percent_links_utilized 7.498621 +system.ruby.network.routers3.msg_count.Request_Control::1 868 +system.ruby.network.routers3.msg_count.Request_Control::2 825 +system.ruby.network.routers3.msg_count.Response_Data::4 823 +system.ruby.network.routers3.msg_count.ResponseL2hit_Data::4 44 +system.ruby.network.routers3.msg_count.Writeback_Data::4 1618 +system.ruby.network.routers3.msg_count.Writeback_Control::4 75 +system.ruby.network.routers3.msg_count.Persistent_Control::3 76 +system.ruby.network.routers3.msg_bytes.Request_Control::1 6944 +system.ruby.network.routers3.msg_bytes.Request_Control::2 6600 +system.ruby.network.routers3.msg_bytes.Response_Data::4 59256 +system.ruby.network.routers3.msg_bytes.ResponseL2hit_Data::4 3168 +system.ruby.network.routers3.msg_bytes.Writeback_Data::4 116496 +system.ruby.network.routers3.msg_bytes.Writeback_Control::4 600 +system.ruby.network.routers3.msg_bytes.Persistent_Control::3 608 +system.ruby.network.pwrStateResidencyTicks::UNDEFINED 53801 # Cumulative time (in ticks) in various power states +system.ruby.network.msg_count.Request_Control 5079 +system.ruby.network.msg_count.Response_Data 2469 +system.ruby.network.msg_count.ResponseL2hit_Data 132 +system.ruby.network.msg_count.Writeback_Data 4854 +system.ruby.network.msg_count.Writeback_Control 225 +system.ruby.network.msg_count.Persistent_Control 228 +system.ruby.network.msg_byte.Request_Control 40632 +system.ruby.network.msg_byte.Response_Data 177768 +system.ruby.network.msg_byte.ResponseL2hit_Data 9504 +system.ruby.network.msg_byte.Writeback_Data 349488 +system.ruby.network.msg_byte.Writeback_Control 1800 +system.ruby.network.msg_byte.Persistent_Control 1824 +system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 53801 # Cumulative time (in ticks) in various power states +system.ruby.network.routers0.throttle0.link_utilization 7.389268 +system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 823 +system.ruby.network.routers0.throttle0.msg_count.ResponseL2hit_Data::4 44 +system.ruby.network.routers0.throttle0.msg_count.Writeback_Data::4 13 +system.ruby.network.routers0.throttle0.msg_count.Persistent_Control::3 38 +system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 59256 +system.ruby.network.routers0.throttle0.msg_bytes.ResponseL2hit_Data::4 3168 +system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Data::4 936 +system.ruby.network.routers0.throttle0.msg_bytes.Persistent_Control::3 304 +system.ruby.network.routers0.throttle1.link_utilization 8.160629 +system.ruby.network.routers0.throttle1.msg_count.Request_Control::1 868 +system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::4 875 +system.ruby.network.routers0.throttle1.msg_count.Persistent_Control::3 38 +system.ruby.network.routers0.throttle1.msg_bytes.Request_Control::1 6944 +system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::4 63000 +system.ruby.network.routers0.throttle1.msg_bytes.Persistent_Control::3 304 +system.ruby.network.routers1.throttle0.link_utilization 8.051895 +system.ruby.network.routers1.throttle0.msg_count.Request_Control::1 868 +system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::4 862 +system.ruby.network.routers1.throttle0.msg_count.Persistent_Control::3 38 +system.ruby.network.routers1.throttle0.msg_bytes.Request_Control::1 6944 +system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::4 62064 +system.ruby.network.routers1.throttle0.msg_bytes.Persistent_Control::3 304 +system.ruby.network.routers1.throttle1.link_utilization 7.419007 +system.ruby.network.routers1.throttle1.msg_count.Request_Control::2 825 +system.ruby.network.routers1.throttle1.msg_count.ResponseL2hit_Data::4 44 +system.ruby.network.routers1.throttle1.msg_count.Writeback_Data::4 743 +system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::4 75 +system.ruby.network.routers1.throttle1.msg_bytes.Request_Control::2 6600 +system.ruby.network.routers1.throttle1.msg_bytes.ResponseL2hit_Data::4 3168 +system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Data::4 53496 +system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::4 600 +system.ruby.network.routers2.throttle0.link_utilization 7.086300 +system.ruby.network.routers2.throttle0.msg_count.Request_Control::2 825 +system.ruby.network.routers2.throttle0.msg_count.Writeback_Data::4 743 +system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::4 75 +system.ruby.network.routers2.throttle0.msg_count.Persistent_Control::3 38 +system.ruby.network.routers2.throttle0.msg_bytes.Request_Control::2 6600 +system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Data::4 53496 +system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::4 600 +system.ruby.network.routers2.throttle0.msg_bytes.Persistent_Control::3 304 +system.ruby.network.routers2.throttle1.link_utilization 6.883701 +system.ruby.network.routers2.throttle1.msg_count.Response_Data::4 823 +system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::4 59256 +system.ruby.network.routers3.throttle0.link_utilization 7.357670 +system.ruby.network.routers3.throttle0.msg_count.Response_Data::4 823 +system.ruby.network.routers3.throttle0.msg_count.ResponseL2hit_Data::4 44 +system.ruby.network.routers3.throttle0.msg_count.Writeback_Data::4 13 +system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::4 59256 +system.ruby.network.routers3.throttle0.msg_bytes.ResponseL2hit_Data::4 3168 +system.ruby.network.routers3.throttle0.msg_bytes.Writeback_Data::4 936 +system.ruby.network.routers3.throttle1.link_utilization 8.051895 +system.ruby.network.routers3.throttle1.msg_count.Request_Control::1 868 +system.ruby.network.routers3.throttle1.msg_count.Writeback_Data::4 862 +system.ruby.network.routers3.throttle1.msg_count.Persistent_Control::3 38 +system.ruby.network.routers3.throttle1.msg_bytes.Request_Control::1 6944 +system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::4 62064 +system.ruby.network.routers3.throttle1.msg_bytes.Persistent_Control::3 304 +system.ruby.network.routers3.throttle2.link_utilization 7.086300 +system.ruby.network.routers3.throttle2.msg_count.Request_Control::2 825 +system.ruby.network.routers3.throttle2.msg_count.Writeback_Data::4 743 +system.ruby.network.routers3.throttle2.msg_count.Writeback_Control::4 75 +system.ruby.network.routers3.throttle2.msg_count.Persistent_Control::3 38 +system.ruby.network.routers3.throttle2.msg_bytes.Request_Control::2 6600 +system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Data::4 53496 +system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Control::4 600 +system.ruby.network.routers3.throttle2.msg_bytes.Persistent_Control::3 304 system.ruby.LD.latency_hist_seqr::bucket_size 256 system.ruby.LD.latency_hist_seqr::max_bucket 2559 -system.ruby.LD.latency_hist_seqr::samples 46 -system.ruby.LD.latency_hist_seqr::mean 817.543478 -system.ruby.LD.latency_hist_seqr::gmean 284.544942 -system.ruby.LD.latency_hist_seqr::stdev 462.655942 -system.ruby.LD.latency_hist_seqr | 11 23.91% 23.91% | 0 0.00% 23.91% | 0 0.00% 23.91% | 15 32.61% 56.52% | 16 34.78% 91.30% | 4 8.70% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.latency_hist_seqr::total 46 -system.ruby.LD.hit_latency_hist_seqr::bucket_size 128 -system.ruby.LD.hit_latency_hist_seqr::max_bucket 1279 -system.ruby.LD.hit_latency_hist_seqr::samples 10 -system.ruby.LD.hit_latency_hist_seqr::mean 101 -system.ruby.LD.hit_latency_hist_seqr::gmean 3.750098 -system.ruby.LD.hit_latency_hist_seqr::stdev 300.217329 -system.ruby.LD.hit_latency_hist_seqr | 9 90.00% 90.00% | 0 0.00% 90.00% | 0 0.00% 90.00% | 0 0.00% 90.00% | 0 0.00% 90.00% | 0 0.00% 90.00% | 0 0.00% 90.00% | 1 10.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.hit_latency_hist_seqr::total 10 +system.ruby.LD.latency_hist_seqr::samples 53 +system.ruby.LD.latency_hist_seqr::mean 911.113208 +system.ruby.LD.latency_hist_seqr::gmean 398.266031 +system.ruby.LD.latency_hist_seqr::stdev 447.197842 +system.ruby.LD.latency_hist_seqr | 10 18.87% 18.87% | 0 0.00% 18.87% | 0 0.00% 18.87% | 10 18.87% 37.74% | 28 52.83% 90.57% | 5 9.43% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.latency_hist_seqr::total 53 +system.ruby.LD.hit_latency_hist_seqr::bucket_size 256 +system.ruby.LD.hit_latency_hist_seqr::max_bucket 2559 +system.ruby.LD.hit_latency_hist_seqr::samples 9 +system.ruby.LD.hit_latency_hist_seqr::mean 152 +system.ruby.LD.hit_latency_hist_seqr::gmean 4.500121 +system.ruby.LD.hit_latency_hist_seqr::stdev 435.863798 +system.ruby.LD.hit_latency_hist_seqr | 8 88.89% 88.89% | 0 0.00% 88.89% | 0 0.00% 88.89% | 0 0.00% 88.89% | 0 0.00% 88.89% | 1 11.11% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.hit_latency_hist_seqr::total 9 system.ruby.LD.miss_latency_hist_seqr::bucket_size 256 system.ruby.LD.miss_latency_hist_seqr::max_bucket 2559 -system.ruby.LD.miss_latency_hist_seqr::samples 36 -system.ruby.LD.miss_latency_hist_seqr::mean 1016.583333 -system.ruby.LD.miss_latency_hist_seqr::gmean 947.115995 -system.ruby.LD.miss_latency_hist_seqr::stdev 254.139824 -system.ruby.LD.miss_latency_hist_seqr | 2 5.56% 5.56% | 0 0.00% 5.56% | 0 0.00% 5.56% | 14 38.89% 44.44% | 16 44.44% 88.89% | 4 11.11% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.miss_latency_hist_seqr::total 36 +system.ruby.LD.miss_latency_hist_seqr::samples 44 +system.ruby.LD.miss_latency_hist_seqr::mean 1066.386364 +system.ruby.LD.miss_latency_hist_seqr::gmean 996.352114 +system.ruby.LD.miss_latency_hist_seqr::stdev 247.421326 +system.ruby.LD.miss_latency_hist_seqr | 2 4.55% 4.55% | 0 0.00% 4.55% | 0 0.00% 4.55% | 10 22.73% 27.27% | 28 63.64% 90.91% | 4 9.09% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.miss_latency_hist_seqr::total 44 system.ruby.ST.latency_hist_seqr::bucket_size 256 system.ruby.ST.latency_hist_seqr::max_bucket 2559 -system.ruby.ST.latency_hist_seqr::samples 846 -system.ruby.ST.latency_hist_seqr::mean 881.170213 -system.ruby.ST.latency_hist_seqr::gmean 402.465808 -system.ruby.ST.latency_hist_seqr::stdev 407.456674 -system.ruby.ST.latency_hist_seqr | 144 17.02% 17.02% | 6 0.71% 17.73% | 5 0.59% 18.32% | 247 29.20% 47.52% | 393 46.45% 93.97% | 51 6.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.latency_hist_seqr::total 846 -system.ruby.ST.hit_latency_hist_seqr::bucket_size 256 -system.ruby.ST.hit_latency_hist_seqr::max_bucket 2559 -system.ruby.ST.hit_latency_hist_seqr::samples 138 -system.ruby.ST.hit_latency_hist_seqr::mean 173.615942 -system.ruby.ST.hit_latency_hist_seqr::gmean 5.002563 -system.ruby.ST.hit_latency_hist_seqr::stdev 375.029660 -system.ruby.ST.hit_latency_hist_seqr | 115 83.33% 83.33% | 0 0.00% 83.33% | 0 0.00% 83.33% | 16 11.59% 94.93% | 6 4.35% 99.28% | 1 0.72% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.hit_latency_hist_seqr::total 138 +system.ruby.ST.latency_hist_seqr::samples 858 +system.ruby.ST.latency_hist_seqr::mean 921.592075 +system.ruby.ST.latency_hist_seqr::gmean 471.652464 +system.ruby.ST.latency_hist_seqr::stdev 386.984382 +system.ruby.ST.latency_hist_seqr | 126 14.69% 14.69% | 5 0.58% 15.27% | 4 0.47% 15.73% | 204 23.78% 39.51% | 488 56.88% 96.39% | 31 3.61% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.latency_hist_seqr::total 858 +system.ruby.ST.hit_latency_hist_seqr::bucket_size 128 +system.ruby.ST.hit_latency_hist_seqr::max_bucket 1279 +system.ruby.ST.hit_latency_hist_seqr::samples 120 +system.ruby.ST.hit_latency_hist_seqr::mean 202.641667 +system.ruby.ST.hit_latency_hist_seqr::gmean 5.297334 +system.ruby.ST.hit_latency_hist_seqr::stdev 407.564189 +system.ruby.ST.hit_latency_hist_seqr | 97 80.83% 80.83% | 0 0.00% 80.83% | 0 0.00% 80.83% | 0 0.00% 80.83% | 0 0.00% 80.83% | 0 0.00% 80.83% | 0 0.00% 80.83% | 10 8.33% 89.17% | 12 10.00% 99.17% | 1 0.83% 100.00% +system.ruby.ST.hit_latency_hist_seqr::total 120 system.ruby.ST.miss_latency_hist_seqr::bucket_size 256 system.ruby.ST.miss_latency_hist_seqr::max_bucket 2559 -system.ruby.ST.miss_latency_hist_seqr::samples 708 -system.ruby.ST.miss_latency_hist_seqr::mean 1019.083333 -system.ruby.ST.miss_latency_hist_seqr::gmean 946.557722 -system.ruby.ST.miss_latency_hist_seqr::stdev 233.252272 -system.ruby.ST.miss_latency_hist_seqr | 29 4.10% 4.10% | 6 0.85% 4.94% | 5 0.71% 5.65% | 231 32.63% 38.28% | 387 54.66% 92.94% | 50 7.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.miss_latency_hist_seqr::total 708 +system.ruby.ST.miss_latency_hist_seqr::samples 738 +system.ruby.ST.miss_latency_hist_seqr::mean 1038.494580 +system.ruby.ST.miss_latency_hist_seqr::gmean 978.643470 +system.ruby.ST.miss_latency_hist_seqr::stdev 222.427518 +system.ruby.ST.miss_latency_hist_seqr | 29 3.93% 3.93% | 5 0.68% 4.61% | 4 0.54% 5.15% | 194 26.29% 31.44% | 475 64.36% 95.80% | 31 4.20% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.miss_latency_hist_seqr::total 738 system.ruby.IFETCH.latency_hist_seqr::bucket_size 32 system.ruby.IFETCH.latency_hist_seqr::max_bucket 319 -system.ruby.IFETCH.latency_hist_seqr::samples 54 -system.ruby.IFETCH.latency_hist_seqr::mean 69.555556 -system.ruby.IFETCH.latency_hist_seqr::gmean 55.256031 -system.ruby.IFETCH.latency_hist_seqr::stdev 50.686855 -system.ruby.IFETCH.latency_hist_seqr | 8 14.81% 14.81% | 15 27.78% 42.59% | 25 46.30% 88.89% | 0 0.00% 88.89% | 3 5.56% 94.44% | 0 0.00% 94.44% | 2 3.70% 98.15% | 0 0.00% 98.15% | 0 0.00% 98.15% | 1 1.85% 100.00% -system.ruby.IFETCH.latency_hist_seqr::total 54 +system.ruby.IFETCH.latency_hist_seqr::samples 47 +system.ruby.IFETCH.latency_hist_seqr::mean 71.957447 +system.ruby.IFETCH.latency_hist_seqr::gmean 60.044920 +system.ruby.IFETCH.latency_hist_seqr::stdev 50.481575 +system.ruby.IFETCH.latency_hist_seqr | 7 14.89% 14.89% | 14 29.79% 44.68% | 21 44.68% 89.36% | 0 0.00% 89.36% | 1 2.13% 91.49% | 2 4.26% 95.74% | 1 2.13% 97.87% | 0 0.00% 97.87% | 1 2.13% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.latency_hist_seqr::total 47 system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 4 system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 39 -system.ruby.IFETCH.hit_latency_hist_seqr::samples 8 -system.ruby.IFETCH.hit_latency_hist_seqr::mean 20.625000 -system.ruby.IFETCH.hit_latency_hist_seqr::gmean 15.768384 -system.ruby.IFETCH.hit_latency_hist_seqr::stdev 8.052285 -system.ruby.IFETCH.hit_latency_hist_seqr | 1 12.50% 12.50% | 0 0.00% 12.50% | 0 0.00% 12.50% | 0 0.00% 12.50% | 0 0.00% 12.50% | 1 12.50% 25.00% | 6 75.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.hit_latency_hist_seqr::total 8 +system.ruby.IFETCH.hit_latency_hist_seqr::samples 7 +system.ruby.IFETCH.hit_latency_hist_seqr::mean 24.428571 +system.ruby.IFETCH.hit_latency_hist_seqr::gmean 24.407244 +system.ruby.IFETCH.hit_latency_hist_seqr::stdev 1.133893 +system.ruby.IFETCH.hit_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 7 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.hit_latency_hist_seqr::total 7 system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 32 system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 319 -system.ruby.IFETCH.miss_latency_hist_seqr::samples 46 -system.ruby.IFETCH.miss_latency_hist_seqr::mean 78.065217 -system.ruby.IFETCH.miss_latency_hist_seqr::gmean 68.721309 -system.ruby.IFETCH.miss_latency_hist_seqr::stdev 50.161252 -system.ruby.IFETCH.miss_latency_hist_seqr | 0 0.00% 0.00% | 15 32.61% 32.61% | 25 54.35% 86.96% | 0 0.00% 86.96% | 3 6.52% 93.48% | 0 0.00% 93.48% | 2 4.35% 97.83% | 0 0.00% 97.83% | 0 0.00% 97.83% | 1 2.17% 100.00% -system.ruby.IFETCH.miss_latency_hist_seqr::total 46 +system.ruby.IFETCH.miss_latency_hist_seqr::samples 40 +system.ruby.IFETCH.miss_latency_hist_seqr::mean 80.275000 +system.ruby.IFETCH.miss_latency_hist_seqr::gmean 70.290048 +system.ruby.IFETCH.miss_latency_hist_seqr::stdev 50.290942 +system.ruby.IFETCH.miss_latency_hist_seqr | 0 0.00% 0.00% | 14 35.00% 35.00% | 21 52.50% 87.50% | 0 0.00% 87.50% | 1 2.50% 90.00% | 2 5.00% 95.00% | 1 2.50% 97.50% | 0 0.00% 97.50% | 1 2.50% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.miss_latency_hist_seqr::total 40 system.ruby.L1Cache.hit_mach_latency_hist_seqr::bucket_size 1 system.ruby.L1Cache.hit_mach_latency_hist_seqr::max_bucket 9 -system.ruby.L1Cache.hit_mach_latency_hist_seqr::samples 106 +system.ruby.L1Cache.hit_mach_latency_hist_seqr::samples 92 system.ruby.L1Cache.hit_mach_latency_hist_seqr::mean 1 system.ruby.L1Cache.hit_mach_latency_hist_seqr::gmean 1 -system.ruby.L1Cache.hit_mach_latency_hist_seqr | 0 0.00% 0.00% | 106 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache.hit_mach_latency_hist_seqr::total 106 +system.ruby.L1Cache.hit_mach_latency_hist_seqr | 0 0.00% 0.00% | 92 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache.hit_mach_latency_hist_seqr::total 92 system.ruby.L2Cache.hit_mach_latency_hist_seqr::bucket_size 256 system.ruby.L2Cache.hit_mach_latency_hist_seqr::max_bucket 2559 -system.ruby.L2Cache.hit_mach_latency_hist_seqr::samples 50 -system.ruby.L2Cache.hit_mach_latency_hist_seqr::mean 500.560000 -system.ruby.L2Cache.hit_mach_latency_hist_seqr::gmean 172.276482 -system.ruby.L2Cache.hit_mach_latency_hist_seqr::stdev 491.089092 -system.ruby.L2Cache.hit_mach_latency_hist_seqr | 26 52.00% 52.00% | 0 0.00% 52.00% | 0 0.00% 52.00% | 17 34.00% 86.00% | 6 12.00% 98.00% | 1 2.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L2Cache.hit_mach_latency_hist_seqr::total 50 +system.ruby.L2Cache.hit_mach_latency_hist_seqr::samples 44 +system.ruby.L2Cache.hit_mach_latency_hist_seqr::mean 585.545455 +system.ruby.L2Cache.hit_mach_latency_hist_seqr::gmean 213.332787 +system.ruby.L2Cache.hit_mach_latency_hist_seqr::stdev 513.546966 +system.ruby.L2Cache.hit_mach_latency_hist_seqr | 20 45.45% 45.45% | 0 0.00% 45.45% | 0 0.00% 45.45% | 10 22.73% 68.18% | 13 29.55% 97.73% | 1 2.27% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L2Cache.hit_mach_latency_hist_seqr::total 44 system.ruby.Directory.miss_mach_latency_hist_seqr::bucket_size 256 system.ruby.Directory.miss_mach_latency_hist_seqr::max_bucket 2559 -system.ruby.Directory.miss_mach_latency_hist_seqr::samples 790 -system.ruby.Directory.miss_mach_latency_hist_seqr::mean 964.175949 -system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 812.519909 -system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 316.811320 -system.ruby.Directory.miss_mach_latency_hist_seqr | 76 9.62% 9.62% | 7 0.89% 10.51% | 5 0.63% 11.14% | 245 31.01% 42.15% | 403 51.01% 93.16% | 54 6.84% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_mach_latency_hist_seqr::total 790 +system.ruby.Directory.miss_mach_latency_hist_seqr::samples 822 +system.ruby.Directory.miss_mach_latency_hist_seqr::mean 993.358881 +system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 861.758158 +system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 300.791358 +system.ruby.Directory.miss_mach_latency_hist_seqr | 70 8.52% 8.52% | 6 0.73% 9.25% | 4 0.49% 9.73% | 204 24.82% 34.55% | 503 61.19% 95.74% | 35 4.26% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_mach_latency_hist_seqr::total 822 system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::bucket_size 1 system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::max_bucket 9 -system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::samples 7 +system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::samples 6 system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::mean 1 system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::gmean 1 -system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 7 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::total 7 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::bucket_size 128 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::max_bucket 1279 +system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 6 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::total 6 +system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::bucket_size 256 +system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::max_bucket 2559 system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::samples 3 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::mean 334.333333 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::gmean 81.936099 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::stdev 537.513101 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr | 2 66.67% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 1 33.33% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::mean 454 +system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::gmean 91.132360 +system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::stdev 744.781847 +system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr | 2 66.67% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 1 33.33% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::total 3 system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size 256 system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket 2559 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples 36 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 1016.583333 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 947.115995 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 254.139824 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 2 5.56% 5.56% | 0 0.00% 5.56% | 0 0.00% 5.56% | 14 38.89% 44.44% | 16 44.44% 88.89% | 4 11.11% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total 36 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples 44 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 1066.386364 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 996.352114 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 247.421326 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 2 4.55% 4.55% | 0 0.00% 4.55% | 0 0.00% 4.55% | 10 22.73% 27.27% | 28 63.64% 90.91% | 4 9.09% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total 44 system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::bucket_size 1 system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::max_bucket 9 -system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::samples 98 +system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::samples 86 system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::mean 1 system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::gmean 1 -system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 98 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::total 98 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::bucket_size 256 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::max_bucket 2559 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::samples 40 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::mean 596.525000 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::gmean 258.353536 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::stdev 485.549015 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr | 17 42.50% 42.50% | 0 0.00% 42.50% | 0 0.00% 42.50% | 16 40.00% 82.50% | 6 15.00% 97.50% | 1 2.50% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::total 40 +system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 86 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::total 86 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::bucket_size 128 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::max_bucket 1279 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::samples 34 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::mean 712.676471 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::gmean 359.332613 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::stdev 474.361052 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr | 11 32.35% 32.35% | 0 0.00% 32.35% | 0 0.00% 32.35% | 0 0.00% 32.35% | 0 0.00% 32.35% | 0 0.00% 32.35% | 0 0.00% 32.35% | 10 29.41% 61.76% | 12 35.29% 97.06% | 1 2.94% 100.00% +system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::total 34 system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size 256 system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket 2559 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::samples 708 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 1019.083333 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 946.557722 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 233.252272 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 29 4.10% 4.10% | 6 0.85% 4.94% | 5 0.71% 5.65% | 231 32.63% 38.28% | 387 54.66% 92.94% | 50 7.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total 708 -system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::bucket_size 1 -system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::max_bucket 9 -system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::samples 1 -system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::mean 1 -system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::gmean 1 -system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::stdev nan -system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::total 1 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::samples 738 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 1038.494580 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 978.643470 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 222.427518 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 29 3.93% 3.93% | 5 0.68% 4.61% | 4 0.54% 5.15% | 194 26.29% 31.44% | 475 64.36% 95.80% | 31 4.20% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total 738 system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::bucket_size 4 system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::max_bucket 39 system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::samples 7 -system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::mean 23.428571 -system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::gmean 23.382968 -system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::stdev 1.511858 -system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 14.29% 14.29% | 6 85.71% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::mean 24.428571 +system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::gmean 24.407244 +system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::stdev 1.133893 +system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 7 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::total 7 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::bucket_size 32 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::max_bucket 319 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::samples 46 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 78.065217 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 68.721309 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 50.161252 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 15 32.61% 32.61% | 25 54.35% 86.96% | 0 0.00% 86.96% | 3 6.52% 93.48% | 0 0.00% 93.48% | 2 4.35% 97.83% | 0 0.00% 97.83% | 0 0.00% 97.83% | 1 2.17% 100.00% -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::total 46 -system.ruby.Directory_Controller.GETX 710 0.00% 0.00% +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::samples 40 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 80.275000 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 70.290048 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 50.290942 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 14 35.00% 35.00% | 21 52.50% 87.50% | 0 0.00% 87.50% | 1 2.50% 90.00% | 2 5.00% 95.00% | 1 2.50% 97.50% | 0 0.00% 97.50% | 1 2.50% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::total 40 +system.ruby.Directory_Controller.GETX 740 0.00% 0.00% system.ruby.Directory_Controller.GETS 85 0.00% 0.00% -system.ruby.Directory_Controller.Lockdown 17 0.00% 0.00% -system.ruby.Directory_Controller.Unlockdown 17 0.00% 0.00% -system.ruby.Directory_Controller.Data_Owner 1 0.00% 0.00% -system.ruby.Directory_Controller.Data_All_Tokens 718 0.00% 0.00% -system.ruby.Directory_Controller.Ack_Owner_All_Tokens 65 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 790 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 719 0.00% 0.00% -system.ruby.Directory_Controller.O.GETX 708 0.00% 0.00% -system.ruby.Directory_Controller.O.GETS 83 0.00% 0.00% -system.ruby.Directory_Controller.NO.GETX 2 0.00% 0.00% -system.ruby.Directory_Controller.NO.Lockdown 7 0.00% 0.00% -system.ruby.Directory_Controller.NO.Data_Owner 1 0.00% 0.00% -system.ruby.Directory_Controller.NO.Data_All_Tokens 718 0.00% 0.00% -system.ruby.Directory_Controller.NO.Ack_Owner_All_Tokens 65 0.00% 0.00% -system.ruby.Directory_Controller.L.Unlockdown 17 0.00% 0.00% -system.ruby.Directory_Controller.O_W.GETS 2 0.00% 0.00% -system.ruby.Directory_Controller.O_W.Memory_Ack 719 0.00% 0.00% -system.ruby.Directory_Controller.L_NO_W.Memory_Data 10 0.00% 0.00% -system.ruby.Directory_Controller.NO_W.Lockdown 10 0.00% 0.00% -system.ruby.Directory_Controller.NO_W.Memory_Data 780 0.00% 0.00% -system.ruby.L1Cache_Controller.Load 46 0.00% 0.00% -system.ruby.L1Cache_Controller.Ifetch 55 0.00% 0.00% -system.ruby.L1Cache_Controller.Store 847 0.00% 0.00% -system.ruby.L1Cache_Controller.L1_Replacement 22253 0.00% 0.00% +system.ruby.Directory_Controller.Lockdown 19 0.00% 0.00% +system.ruby.Directory_Controller.Unlockdown 19 0.00% 0.00% +system.ruby.Directory_Controller.Data_Owner 2 0.00% 0.00% +system.ruby.Directory_Controller.Data_All_Tokens 741 0.00% 0.00% +system.ruby.Directory_Controller.Ack_Owner_All_Tokens 73 0.00% 0.00% +system.ruby.Directory_Controller.Ack_All_Tokens 2 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 823 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 743 0.00% 0.00% +system.ruby.Directory_Controller.O.GETX 739 0.00% 0.00% +system.ruby.Directory_Controller.O.GETS 85 0.00% 0.00% +system.ruby.Directory_Controller.O.Ack_All_Tokens 2 0.00% 0.00% +system.ruby.Directory_Controller.NO.GETX 1 0.00% 0.00% +system.ruby.Directory_Controller.NO.Lockdown 4 0.00% 0.00% +system.ruby.Directory_Controller.NO.Data_Owner 2 0.00% 0.00% +system.ruby.Directory_Controller.NO.Data_All_Tokens 741 0.00% 0.00% +system.ruby.Directory_Controller.NO.Ack_Owner_All_Tokens 73 0.00% 0.00% +system.ruby.Directory_Controller.L.Unlockdown 19 0.00% 0.00% +system.ruby.Directory_Controller.O_W.Memory_Ack 743 0.00% 0.00% +system.ruby.Directory_Controller.L_NO_W.Memory_Data 15 0.00% 0.00% +system.ruby.Directory_Controller.NO_W.Lockdown 15 0.00% 0.00% +system.ruby.Directory_Controller.NO_W.Memory_Data 808 0.00% 0.00% +system.ruby.L1Cache_Controller.Load 53 0.00% 0.00% +system.ruby.L1Cache_Controller.Ifetch 48 0.00% 0.00% +system.ruby.L1Cache_Controller.Store 859 0.00% 0.00% +system.ruby.L1Cache_Controller.L1_Replacement 23142 0.00% 0.00% system.ruby.L1Cache_Controller.Data_Shared 10 0.00% 0.00% -system.ruby.L1Cache_Controller.Data_All_Tokens 844 0.00% 0.00% -system.ruby.L1Cache_Controller.Ack 1 0.00% 0.00% -system.ruby.L1Cache_Controller.Own_Lock_or_Unlock 34 0.00% 0.00% -system.ruby.L1Cache_Controller.Request_Timeout 61 0.00% 0.00% -system.ruby.L1Cache_Controller.Use_TimeoutNoStarvers 829 0.00% 0.00% -system.ruby.L1Cache_Controller.NP.Load 39 0.00% 0.00% -system.ruby.L1Cache_Controller.NP.Ifetch 54 0.00% 0.00% -system.ruby.L1Cache_Controller.NP.Store 747 0.00% 0.00% -system.ruby.L1Cache_Controller.NP.Data_All_Tokens 14 0.00% 0.00% +system.ruby.L1Cache_Controller.Data_All_Tokens 869 0.00% 0.00% +system.ruby.L1Cache_Controller.Own_Lock_or_Unlock 38 0.00% 0.00% +system.ruby.L1Cache_Controller.Request_Timeout 35 0.00% 0.00% +system.ruby.L1Cache_Controller.Use_TimeoutNoStarvers 855 0.00% 0.00% +system.ruby.L1Cache_Controller.NP.Load 47 0.00% 0.00% +system.ruby.L1Cache_Controller.NP.Ifetch 48 0.00% 0.00% +system.ruby.L1Cache_Controller.NP.Store 772 0.00% 0.00% +system.ruby.L1Cache_Controller.NP.Data_All_Tokens 13 0.00% 0.00% system.ruby.L1Cache_Controller.NP.Own_Lock_or_Unlock 14 0.00% 0.00% -system.ruby.L1Cache_Controller.S.Store 2 0.00% 0.00% -system.ruby.L1Cache_Controller.S.L1_Replacement 8 0.00% 0.00% -system.ruby.L1Cache_Controller.M.Ifetch 1 0.00% 0.00% -system.ruby.L1Cache_Controller.M.L1_Replacement 79 0.00% 0.00% +system.ruby.L1Cache_Controller.S.Load 1 0.00% 0.00% +system.ruby.L1Cache_Controller.S.Store 1 0.00% 0.00% +system.ruby.L1Cache_Controller.S.L1_Replacement 9 0.00% 0.00% +system.ruby.L1Cache_Controller.M.L1_Replacement 82 0.00% 0.00% system.ruby.L1Cache_Controller.M.Own_Lock_or_Unlock 3 0.00% 0.00% -system.ruby.L1Cache_Controller.MM.Load 7 0.00% 0.00% -system.ruby.L1Cache_Controller.MM.Store 79 0.00% 0.00% -system.ruby.L1Cache_Controller.MM.L1_Replacement 748 0.00% 0.00% -system.ruby.L1Cache_Controller.M_W.Store 1 0.00% 0.00% -system.ruby.L1Cache_Controller.M_W.L1_Replacement 551 0.00% 0.00% +system.ruby.L1Cache_Controller.MM.Load 4 0.00% 0.00% +system.ruby.L1Cache_Controller.MM.Store 69 0.00% 0.00% +system.ruby.L1Cache_Controller.MM.L1_Replacement 771 0.00% 0.00% +system.ruby.L1Cache_Controller.MM.Own_Lock_or_Unlock 2 0.00% 0.00% +system.ruby.L1Cache_Controller.M_W.L1_Replacement 624 0.00% 0.00% system.ruby.L1Cache_Controller.M_W.Own_Lock_or_Unlock 1 0.00% 0.00% -system.ruby.L1Cache_Controller.M_W.Use_TimeoutNoStarvers 80 0.00% 0.00% -system.ruby.L1Cache_Controller.MM_W.Store 18 0.00% 0.00% -system.ruby.L1Cache_Controller.MM_W.L1_Replacement 10451 0.00% 0.00% +system.ruby.L1Cache_Controller.M_W.Use_TimeoutNoStarvers 83 0.00% 0.00% +system.ruby.L1Cache_Controller.MM_W.Load 1 0.00% 0.00% +system.ruby.L1Cache_Controller.MM_W.Store 17 0.00% 0.00% +system.ruby.L1Cache_Controller.MM_W.L1_Replacement 10842 0.00% 0.00% system.ruby.L1Cache_Controller.MM_W.Own_Lock_or_Unlock 1 0.00% 0.00% -system.ruby.L1Cache_Controller.MM_W.Use_TimeoutNoStarvers 749 0.00% 0.00% -system.ruby.L1Cache_Controller.IM.L1_Replacement 9900 0.00% 0.00% -system.ruby.L1Cache_Controller.IM.Data_All_Tokens 746 0.00% 0.00% -system.ruby.L1Cache_Controller.IM.Ack 1 0.00% 0.00% -system.ruby.L1Cache_Controller.IM.Own_Lock_or_Unlock 10 0.00% 0.00% -system.ruby.L1Cache_Controller.IM.Request_Timeout 55 0.00% 0.00% -system.ruby.L1Cache_Controller.SM.Data_All_Tokens 2 0.00% 0.00% -system.ruby.L1Cache_Controller.IS.L1_Replacement 516 0.00% 0.00% +system.ruby.L1Cache_Controller.MM_W.Use_TimeoutNoStarvers 772 0.00% 0.00% +system.ruby.L1Cache_Controller.IM.L1_Replacement 10272 0.00% 0.00% +system.ruby.L1Cache_Controller.IM.Data_All_Tokens 771 0.00% 0.00% +system.ruby.L1Cache_Controller.IM.Own_Lock_or_Unlock 12 0.00% 0.00% +system.ruby.L1Cache_Controller.IM.Request_Timeout 25 0.00% 0.00% +system.ruby.L1Cache_Controller.SM.Data_All_Tokens 1 0.00% 0.00% +system.ruby.L1Cache_Controller.IS.L1_Replacement 542 0.00% 0.00% system.ruby.L1Cache_Controller.IS.Data_Shared 10 0.00% 0.00% -system.ruby.L1Cache_Controller.IS.Data_All_Tokens 82 0.00% 0.00% +system.ruby.L1Cache_Controller.IS.Data_All_Tokens 84 0.00% 0.00% system.ruby.L1Cache_Controller.IS.Own_Lock_or_Unlock 5 0.00% 0.00% -system.ruby.L1Cache_Controller.IS.Request_Timeout 6 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_GETS 93 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_GETX 748 0.00% 0.00% -system.ruby.L2Cache_Controller.L2_Replacement 770 0.00% 0.00% -system.ruby.L2Cache_Controller.Writeback_Shared_Data 1 0.00% 0.00% -system.ruby.L2Cache_Controller.Writeback_All_Tokens 833 0.00% 0.00% -system.ruby.L2Cache_Controller.Persistent_GETX 11 0.00% 0.00% +system.ruby.L1Cache_Controller.IS.Request_Timeout 10 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_GETS 95 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_GETX 773 0.00% 0.00% +system.ruby.L2Cache_Controller.L2_Replacement 805 0.00% 0.00% +system.ruby.L2Cache_Controller.Writeback_Shared_Data 2 0.00% 0.00% +system.ruby.L2Cache_Controller.Writeback_All_Tokens 860 0.00% 0.00% +system.ruby.L2Cache_Controller.Persistent_GETX 13 0.00% 0.00% system.ruby.L2Cache_Controller.Persistent_GETS 6 0.00% 0.00% -system.ruby.L2Cache_Controller.Own_Lock_or_Unlock 17 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.L1_GETS 83 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.L1_GETX 707 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.Writeback_Shared_Data 1 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.Writeback_All_Tokens 773 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.Own_Lock_or_Unlock 17 0.00% 0.00% -system.ruby.L2Cache_Controller.I.Writeback_All_Tokens 39 0.00% 0.00% -system.ruby.L2Cache_Controller.S.L1_GETX 1 0.00% 0.00% -system.ruby.L2Cache_Controller.O.L1_GETX 2 0.00% 0.00% -system.ruby.L2Cache_Controller.O.L2_Replacement 1 0.00% 0.00% +system.ruby.L2Cache_Controller.Own_Lock_or_Unlock 19 0.00% 0.00% +system.ruby.L2Cache_Controller.NP.L1_GETS 85 0.00% 0.00% +system.ruby.L2Cache_Controller.NP.L1_GETX 739 0.00% 0.00% +system.ruby.L2Cache_Controller.NP.Writeback_Shared_Data 2 0.00% 0.00% +system.ruby.L2Cache_Controller.NP.Writeback_All_Tokens 807 0.00% 0.00% +system.ruby.L2Cache_Controller.NP.Own_Lock_or_Unlock 19 0.00% 0.00% +system.ruby.L2Cache_Controller.I.Writeback_All_Tokens 33 0.00% 0.00% +system.ruby.L2Cache_Controller.S.L2_Replacement 2 0.00% 0.00% +system.ruby.L2Cache_Controller.O.L1_GETX 1 0.00% 0.00% +system.ruby.L2Cache_Controller.O.L2_Replacement 2 0.00% 0.00% system.ruby.L2Cache_Controller.O.Writeback_All_Tokens 7 0.00% 0.00% system.ruby.L2Cache_Controller.M.L1_GETS 10 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L1_GETX 38 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L2_Replacement 769 0.00% 0.00% -system.ruby.L2Cache_Controller.I_L.Writeback_All_Tokens 14 0.00% 0.00% -system.ruby.L2Cache_Controller.I_L.Persistent_GETX 11 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L1_GETX 33 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L2_Replacement 801 0.00% 0.00% +system.ruby.L2Cache_Controller.I_L.Writeback_All_Tokens 13 0.00% 0.00% +system.ruby.L2Cache_Controller.I_L.Persistent_GETX 13 0.00% 0.00% system.ruby.L2Cache_Controller.I_L.Persistent_GETS 6 0.00% 0.00% ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/config.ini b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/config.ini index d7e72749d..2dd4fa860 100644 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/config.ini +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/config.ini @@ -14,6 +14,7 @@ children=clk_domain cpu dvfs_handler mem_ctrls ruby sys_port_proxy voltage_domai boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 exit_on_work_items=false init_param=0 @@ -22,11 +23,15 @@ kernel_addr_check=true load_addr_mask=1099511627775 load_offset=0 mem_mode=timing -mem_ranges=0:268435455 +mem_ranges=0:268435455:0:0:0:0 memories=system.mem_ctrls mmap_using_noreserve=false multi_thread=false num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null readfile= symbolfile= thermal_components= @@ -54,8 +59,13 @@ check_flush=true checks_to_complete=100 clk_domain=system.clk_domain deadlock_threshold=50000 +default_p_state=UNDEFINED eventq_index=0 num_cpus=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null system=system wakeup_frequency=10 cpuInstDataPort=system.ruby.l1_cntrl0.sequencer.slave[0] @@ -70,27 +80,27 @@ transition_latency=100000 [system.mem_ctrls] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -102,6 +112,7 @@ burst_length=8 channels=1 clk_domain=system.clk_domain conf_table_reported=true +default_p_state=UNDEFINED device_bus_width=8 device_rowbuffer_size=1024 device_size=536870912 @@ -109,12 +120,17 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 page_policy=open_adaptive -range=0:268435455 +power_model=Null +range=0:268435455:5:19:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10 @@ -136,9 +152,9 @@ tRTW=3 tWR=15 tWTR=8 tXAW=30 -tXP=0 +tXP=6 tXPDLL=0 -tXS=0 +tXS=270 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 @@ -152,12 +168,17 @@ access_backing_store=false all_instructions=false block_size_bytes=64 clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED eventq_index=0 hot_lines=false memory_size_bits=48 num_of_sequencers=1 number_of_virtual_networks=6 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 phys_mem=Null +power_model=Null randomization=true [system.ruby.clk_domain] @@ -174,6 +195,7 @@ children=directory dmaRequestToDir dmaResponseFromDir forwardFromDir probeFilter buffer_size=0 clk_domain=system.ruby.clk_domain cluster_id=0 +default_p_state=UNDEFINED directory=system.ruby.dir_cntrl0.directory dmaRequestToDir=system.ruby.dir_cntrl0.dmaRequestToDir dmaResponseFromDir=system.ruby.dir_cntrl0.dmaResponseFromDir @@ -182,6 +204,10 @@ forwardFromDir=system.ruby.dir_cntrl0.forwardFromDir from_memory_controller_latency=2 full_bit_dir_enabled=false number_of_TBEs=256 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null probeFilter=system.ruby.dir_cntrl0.probeFilter probe_filter_enabled=false recycle_latency=10 @@ -309,6 +335,7 @@ buffer_size=0 cache_response_latency=10 clk_domain=system.ruby.clk_domain cluster_id=0 +default_p_state=UNDEFINED eventq_index=0 forwardToCache=system.ruby.l1_cntrl0.forwardToCache issue_latency=2 @@ -316,6 +343,10 @@ l2_cache_hit_latency=10 mandatoryQueue=system.ruby.l1_cntrl0.mandatoryQueue no_mig_atomic=true number_of_TBEs=256 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null recycle_latency=10 requestFromCache=system.ruby.l1_cntrl0.requestFromCache responseFromCache=system.ruby.l1_cntrl0.responseFromCache @@ -447,17 +478,22 @@ coreid=99 dcache=system.ruby.l1_cntrl0.L1Dcache dcache_hit_latency=1 deadlock_threshold=500000 +default_p_state=UNDEFINED eventq_index=0 +garnet_standalone=false icache=system.ruby.l1_cntrl0.L1Icache icache_hit_latency=1 is_cpu_sequencer=true max_outstanding_requests=16 no_retry_on_stall=true +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null ruby_system=system.ruby support_data_reqs=true support_inst_reqs=true system=system -using_network_tester=false using_ruby_tester=true version=0 slave=system.cpu.cpuInstDataPort[0] @@ -485,18 +521,23 @@ eventq_index=0 [system.ruby.network] type=SimpleNetwork -children=ext_links0 ext_links1 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_link_buffers20 int_link_buffers21 int_link_buffers22 int_link_buffers23 int_links0 int_links1 routers0 routers1 routers2 +children=ext_links0 ext_links1 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_link_buffers20 int_link_buffers21 int_link_buffers22 int_link_buffers23 int_link_buffers24 int_link_buffers25 int_link_buffers26 int_link_buffers27 int_link_buffers28 int_link_buffers29 int_link_buffers30 int_link_buffers31 int_link_buffers32 int_link_buffers33 int_link_buffers34 int_link_buffers35 int_link_buffers36 int_link_buffers37 int_link_buffers38 int_link_buffers39 int_link_buffers40 int_link_buffers41 int_link_buffers42 int_link_buffers43 int_link_buffers44 int_link_buffers45 int_link_buffers46 int_link_buffers47 int_links0 int_links1 int_links2 int_links3 routers0 routers1 routers2 adaptive_routing=false buffer_size=0 clk_domain=system.ruby.clk_domain control_msg_size=8 +default_p_state=UNDEFINED endpoint_bandwidth=1000 eventq_index=0 ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1 -int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19 system.ruby.network.int_link_buffers20 system.ruby.network.int_link_buffers21 system.ruby.network.int_link_buffers22 system.ruby.network.int_link_buffers23 -int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 +int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19 system.ruby.network.int_link_buffers20 system.ruby.network.int_link_buffers21 system.ruby.network.int_link_buffers22 system.ruby.network.int_link_buffers23 system.ruby.network.int_link_buffers24 system.ruby.network.int_link_buffers25 system.ruby.network.int_link_buffers26 system.ruby.network.int_link_buffers27 system.ruby.network.int_link_buffers28 system.ruby.network.int_link_buffers29 system.ruby.network.int_link_buffers30 system.ruby.network.int_link_buffers31 system.ruby.network.int_link_buffers32 system.ruby.network.int_link_buffers33 system.ruby.network.int_link_buffers34 system.ruby.network.int_link_buffers35 system.ruby.network.int_link_buffers36 system.ruby.network.int_link_buffers37 system.ruby.network.int_link_buffers38 system.ruby.network.int_link_buffers39 system.ruby.network.int_link_buffers40 system.ruby.network.int_link_buffers41 system.ruby.network.int_link_buffers42 system.ruby.network.int_link_buffers43 system.ruby.network.int_link_buffers44 system.ruby.network.int_link_buffers45 system.ruby.network.int_link_buffers46 system.ruby.network.int_link_buffers47 +int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2 system.ruby.network.int_links3 netifs= number_of_virtual_networks=6 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null routers=system.ruby.network.routers0 system.ruby.network.routers1 system.ruby.network.routers2 ruby_system=system.ruby topology=Crossbar @@ -691,32 +732,234 @@ eventq_index=0 ordered=true randomization=false +[system.ruby.network.int_link_buffers24] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers25] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers26] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers27] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers28] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers29] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers30] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers31] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers32] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers33] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers34] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers35] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers36] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers37] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers38] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers39] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers40] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers41] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers42] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers43] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers44] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers45] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers46] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers47] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + [system.ruby.network.int_links0] type=SimpleIntLink bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers2 eventq_index=0 latency=1 link_id=2 -node_a=system.ruby.network.routers0 -node_b=system.ruby.network.routers2 +src_node=system.ruby.network.routers0 +src_outport= weight=1 [system.ruby.network.int_links1] type=SimpleIntLink bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers2 eventq_index=0 latency=1 link_id=3 -node_a=system.ruby.network.routers1 -node_b=system.ruby.network.routers2 +src_node=system.ruby.network.routers1 +src_outport= +weight=1 + +[system.ruby.network.int_links2] +type=SimpleIntLink +bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers0 +eventq_index=0 +latency=1 +link_id=4 +src_node=system.ruby.network.routers2 +src_outport= +weight=1 + +[system.ruby.network.int_links3] +type=SimpleIntLink +bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers1 +eventq_index=0 +latency=1 +link_id=5 +src_node=system.ruby.network.routers2 +src_outport= weight=1 [system.ruby.network.routers0] type=Switch children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17 clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED eventq_index=0 +latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 port_buffers=system.ruby.network.routers0.port_buffers00 system.ruby.network.routers0.port_buffers01 system.ruby.network.routers0.port_buffers02 system.ruby.network.routers0.port_buffers03 system.ruby.network.routers0.port_buffers04 system.ruby.network.routers0.port_buffers05 system.ruby.network.routers0.port_buffers06 system.ruby.network.routers0.port_buffers07 system.ruby.network.routers0.port_buffers08 system.ruby.network.routers0.port_buffers09 system.ruby.network.routers0.port_buffers10 system.ruby.network.routers0.port_buffers11 system.ruby.network.routers0.port_buffers12 system.ruby.network.routers0.port_buffers13 system.ruby.network.routers0.port_buffers14 system.ruby.network.routers0.port_buffers15 system.ruby.network.routers0.port_buffers16 system.ruby.network.routers0.port_buffers17 +power_model=Null router_id=0 virt_nets=6 @@ -850,8 +1093,14 @@ randomization=false type=Switch children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17 clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED eventq_index=0 +latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 port_buffers=system.ruby.network.routers1.port_buffers00 system.ruby.network.routers1.port_buffers01 system.ruby.network.routers1.port_buffers02 system.ruby.network.routers1.port_buffers03 system.ruby.network.routers1.port_buffers04 system.ruby.network.routers1.port_buffers05 system.ruby.network.routers1.port_buffers06 system.ruby.network.routers1.port_buffers07 system.ruby.network.routers1.port_buffers08 system.ruby.network.routers1.port_buffers09 system.ruby.network.routers1.port_buffers10 system.ruby.network.routers1.port_buffers11 system.ruby.network.routers1.port_buffers12 system.ruby.network.routers1.port_buffers13 system.ruby.network.routers1.port_buffers14 system.ruby.network.routers1.port_buffers15 system.ruby.network.routers1.port_buffers16 system.ruby.network.routers1.port_buffers17 +power_model=Null router_id=1 virt_nets=6 @@ -985,8 +1234,14 @@ randomization=false type=Switch children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17 port_buffers18 port_buffers19 port_buffers20 port_buffers21 port_buffers22 port_buffers23 clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED eventq_index=0 +latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 port_buffers=system.ruby.network.routers2.port_buffers00 system.ruby.network.routers2.port_buffers01 system.ruby.network.routers2.port_buffers02 system.ruby.network.routers2.port_buffers03 system.ruby.network.routers2.port_buffers04 system.ruby.network.routers2.port_buffers05 system.ruby.network.routers2.port_buffers06 system.ruby.network.routers2.port_buffers07 system.ruby.network.routers2.port_buffers08 system.ruby.network.routers2.port_buffers09 system.ruby.network.routers2.port_buffers10 system.ruby.network.routers2.port_buffers11 system.ruby.network.routers2.port_buffers12 system.ruby.network.routers2.port_buffers13 system.ruby.network.routers2.port_buffers14 system.ruby.network.routers2.port_buffers15 system.ruby.network.routers2.port_buffers16 system.ruby.network.routers2.port_buffers17 system.ruby.network.routers2.port_buffers18 system.ruby.network.routers2.port_buffers19 system.ruby.network.routers2.port_buffers20 system.ruby.network.routers2.port_buffers21 system.ruby.network.routers2.port_buffers22 system.ruby.network.routers2.port_buffers23 +power_model=Null router_id=2 virt_nets=6 @@ -1161,9 +1416,14 @@ randomization=false [system.sys_port_proxy] type=RubyPortProxy clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 is_cpu_sequencer=true no_retry_on_stall=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null ruby_system=system.ruby support_data_reqs=true support_inst_reqs=true diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simerr b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simerr index c2086c0ba..cee0dfc57 100755 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simerr +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simerr @@ -4,7 +4,5 @@ warn: rounding error > tolerance 1.250000 rounded to 1 warn: rounding error > tolerance 1.250000 rounded to 1 -warn: rounding error > tolerance - 1.250000 rounded to 1 warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes) warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files! diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simout b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simout index cb4dc5a7d..23e165901 100755 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simout +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simout @@ -1,11 +1,13 @@ +Redirecting stdout to build/ALPHA_MOESI_hammer/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_hammer/simout +Redirecting stderr to build/ALPHA_MOESI_hammer/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_hammer/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 21 2016 13:56:08 -gem5 started Jan 21 2016 13:56:42 -gem5 executing on zizzer, pid 39357 -command line: build/ALPHA_MOESI_hammer/gem5.opt -d build/ALPHA_MOESI_hammer/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_hammer -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ALPHA_MOESI_hammer/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_hammer +gem5 compiled Oct 13 2016 20:24:36 +gem5 started Oct 13 2016 20:24:58 +gem5 executing on e108600-lin, pid 38873 +command line: /work/curdun01/gem5-external.hg/build/ALPHA_MOESI_hammer/gem5.opt -d build/ALPHA_MOESI_hammer/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_hammer -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_hammer Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 29561 because Ruby Tester completed +Exiting @ tick 31071 because Ruby Tester completed diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt index 7a535a15b..43510f355 100644 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt @@ -1,45 +1,45 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000030 # Number of seconds simulated -sim_ticks 29561 # Number of ticks simulated -final_tick 29561 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000031 # Number of seconds simulated +sim_ticks 31071 # Number of ticks simulated +final_tick 31071 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 585115 # Simulator tick rate (ticks/s) -host_mem_usage 452068 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host +host_tick_rate 307258 # Simulator tick rate (ticks/s) +host_mem_usage 409592 # Number of bytes of host memory used +host_seconds 0.10 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks -system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 29561 # Cumulative time (in ticks) in various power states -system.mem_ctrls.bytes_read::ruby.dir_cntrl0 56000 # Number of bytes read from this memory -system.mem_ctrls.bytes_read::total 56000 # Number of bytes read from this memory -system.mem_ctrls.bytes_written::ruby.dir_cntrl0 50560 # Number of bytes written to this memory -system.mem_ctrls.bytes_written::total 50560 # Number of bytes written to this memory -system.mem_ctrls.num_reads::ruby.dir_cntrl0 875 # Number of read requests responded to by this memory -system.mem_ctrls.num_reads::total 875 # Number of read requests responded to by this memory -system.mem_ctrls.num_writes::ruby.dir_cntrl0 790 # Number of write requests responded to by this memory -system.mem_ctrls.num_writes::total 790 # Number of write requests responded to by this memory -system.mem_ctrls.bw_read::ruby.dir_cntrl0 1894387876 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_read::total 1894387876 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::ruby.dir_cntrl0 1710361625 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::total 1710361625 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_total::ruby.dir_cntrl0 3604749501 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.bw_total::total 3604749501 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.readReqs 876 # Number of read requests accepted -system.mem_ctrls.writeReqs 790 # Number of write requests accepted -system.mem_ctrls.readBursts 876 # Number of DRAM read bursts, including those serviced by the write queue -system.mem_ctrls.writeBursts 790 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrls.bytesReadDRAM 46720 # Total number of bytes read from DRAM -system.mem_ctrls.bytesReadWrQ 9344 # Total number of bytes read from write queue -system.mem_ctrls.bytesWritten 41728 # Total number of bytes written to DRAM -system.mem_ctrls.bytesReadSys 56064 # Total read bytes from the system interface side -system.mem_ctrls.bytesWrittenSys 50560 # Total written bytes from the system interface side -system.mem_ctrls.servicedByWrQ 146 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrls.mergedWrBursts 108 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 31071 # Cumulative time (in ticks) in various power states +system.mem_ctrls.bytes_read::ruby.dir_cntrl0 55104 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 55104 # Number of bytes read from this memory +system.mem_ctrls.bytes_written::ruby.dir_cntrl0 50048 # Number of bytes written to this memory +system.mem_ctrls.bytes_written::total 50048 # Number of bytes written to this memory +system.mem_ctrls.num_reads::ruby.dir_cntrl0 861 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 861 # Number of read requests responded to by this memory +system.mem_ctrls.num_writes::ruby.dir_cntrl0 782 # Number of write requests responded to by this memory +system.mem_ctrls.num_writes::total 782 # Number of write requests responded to by this memory +system.mem_ctrls.bw_read::ruby.dir_cntrl0 1773486531 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 1773486531 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::ruby.dir_cntrl0 1610762447 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::total 1610762447 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::ruby.dir_cntrl0 3384248978 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 3384248978 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.readReqs 862 # Number of read requests accepted +system.mem_ctrls.writeReqs 782 # Number of write requests accepted +system.mem_ctrls.readBursts 862 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 782 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.bytesReadDRAM 45632 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 9536 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 41024 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 55168 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 50048 # Total written bytes from the system interface side +system.mem_ctrls.servicedByWrQ 149 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 111 # Number of DRAM write bursts merged with an existing one system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.mem_ctrls.perBankRdBursts::0 202 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::0 191 # Per bank write bursts system.mem_ctrls.perBankRdBursts::1 231 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::2 235 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::3 62 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 240 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 51 # Per bank write bursts system.mem_ctrls.perBankRdBursts::4 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::5 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::6 0 # Per bank write bursts @@ -52,10 +52,10 @@ system.mem_ctrls.perBankRdBursts::12 0 # Pe system.mem_ctrls.perBankRdBursts::13 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::14 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::15 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::0 184 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::1 201 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::2 215 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::3 52 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 172 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 202 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 220 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 47 # Per bank write bursts system.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts @@ -70,25 +70,25 @@ system.mem_ctrls.perBankWrBursts::14 0 # Pe system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrls.totGap 29529 # Total gap between requests +system.mem_ctrls.totGap 31040 # Total gap between requests system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::6 876 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 862 # Read request sizes (log2) system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::6 790 # Write request sizes (log2) -system.mem_ctrls.rdQLenPdf::0 418 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::1 290 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::2 22 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see +system.mem_ctrls.writePktSize::6 782 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 405 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 288 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::2 19 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::3 1 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::5 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -132,25 +132,25 @@ system.mem_ctrls.wrQLenPdf::11 1 # Wh system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::15 3 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::16 6 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 2 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::17 22 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::18 40 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::19 42 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 41 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::20 41 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::21 42 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::22 41 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::23 41 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 44 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::24 42 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::25 42 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::26 61 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::27 41 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 41 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 53 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 44 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::28 41 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::29 41 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::30 40 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::31 40 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::32 40 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::33 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see @@ -181,363 +181,372 @@ system.mem_ctrls.wrQLenPdf::60 0 # Wh system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrls.bytesPerActivate::samples 91 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::mean 952.967033 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::gmean 882.848619 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::stdev 223.022742 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::0-127 2 2.20% 2.20% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::128-255 2 2.20% 4.40% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::256-383 2 2.20% 6.59% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::512-639 1 1.10% 7.69% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::640-767 2 2.20% 9.89% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::896-1023 1 1.10% 10.99% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::1024-1151 81 89.01% 100.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::total 91 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::samples 90 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 943.644444 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 882.472849 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 228.764454 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 5 5.56% 5.56% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 1 1.11% 6.67% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 1 1.11% 7.78% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 3 3.33% 11.11% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 2 2.22% 13.33% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 78 86.67% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 90 # Bytes accessed per row activation system.mem_ctrls.rdPerTurnAround::samples 40 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::mean 17.800000 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::gmean 17.518113 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::stdev 3.824348 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::14-15 8 20.00% 20.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::16-17 16 40.00% 60.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::18-19 8 20.00% 80.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::20-21 6 15.00% 95.00% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::mean 17.425000 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::gmean 17.142863 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::stdev 3.754570 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::12-13 1 2.50% 2.50% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::14-15 10 25.00% 27.50% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::16-17 16 40.00% 67.50% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::18-19 6 15.00% 82.50% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::20-21 5 12.50% 95.00% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::22-23 1 2.50% 97.50% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::38-39 1 2.50% 100.00% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::36-37 1 2.50% 100.00% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::total 40 # Reads before turning the bus around for writes system.mem_ctrls.wrPerTurnAround::samples 40 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::mean 16.300000 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::gmean 16.268271 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::stdev 1.114013 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::16 36 90.00% 90.00% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::17 2 5.00% 95.00% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::21 2 5.00% 100.00% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::mean 16.025000 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::gmean 16.024268 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::stdev 0.158114 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::16 39 97.50% 97.50% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::17 1 2.50% 100.00% # Writes before turning the bus around for reads system.mem_ctrls.wrPerTurnAround::total 40 # Writes before turning the bus around for reads -system.mem_ctrls.totQLat 8835 # Total ticks spent queuing -system.mem_ctrls.totMemAccLat 22705 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrls.totBusLat 3650 # Total ticks spent in databus transfers -system.mem_ctrls.avgQLat 12.10 # Average queueing delay per DRAM burst +system.mem_ctrls.totQLat 12133 # Total ticks spent queuing +system.mem_ctrls.totMemAccLat 25680 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.totBusLat 3565 # Total ticks spent in databus transfers +system.mem_ctrls.avgQLat 17.02 # Average queueing delay per DRAM burst system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst -system.mem_ctrls.avgMemAccLat 31.10 # Average memory access latency per DRAM burst -system.mem_ctrls.avgRdBW 1580.46 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrls.avgWrBW 1411.59 # Average achieved write bandwidth in MiByte/s -system.mem_ctrls.avgRdBWSys 1896.55 # Average system read bandwidth in MiByte/s -system.mem_ctrls.avgWrBWSys 1710.36 # Average system write bandwidth in MiByte/s +system.mem_ctrls.avgMemAccLat 36.02 # Average memory access latency per DRAM burst +system.mem_ctrls.avgRdBW 1468.64 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 1320.33 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 1775.55 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 1610.76 # Average system write bandwidth in MiByte/s system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrls.busUtil 23.38 # Data bus utilization in percentage -system.mem_ctrls.busUtilRead 12.35 # Data bus utilization in percentage for reads -system.mem_ctrls.busUtilWrite 11.03 # Data bus utilization in percentage for writes -system.mem_ctrls.avgRdQLen 1.74 # Average read queue length when enqueuing -system.mem_ctrls.avgWrQLen 24.79 # Average write queue length when enqueuing -system.mem_ctrls.readRowHits 640 # Number of row buffer hits during reads -system.mem_ctrls.writeRowHits 647 # Number of row buffer hits during writes -system.mem_ctrls.readRowHitRate 87.67 # Row buffer hit rate for reads -system.mem_ctrls.writeRowHitRate 94.87 # Row buffer hit rate for writes -system.mem_ctrls.avgGap 17.72 # Average gap between requests -system.mem_ctrls.pageHitRate 91.15 # Row buffer hit rate, read and write combined -system.mem_ctrls_0.actEnergy 567000 # Energy for activate commands per rank (pJ) -system.mem_ctrls_0.preEnergy 315000 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_0.readEnergy 7176000 # Energy for read commands per rank (pJ) -system.mem_ctrls_0.writeEnergy 5432832 # Energy for write commands per rank (pJ) -system.mem_ctrls_0.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_0.actBackEnergy 16101360 # Energy for active background per rank (pJ) -system.mem_ctrls_0.preBackEnergy 48600 # Energy for precharge background per rank (pJ) -system.mem_ctrls_0.totalEnergy 31166472 # Total energy per rank (pJ) -system.mem_ctrls_0.averagePower 1319.439143 # Core power per rank (mW) +system.mem_ctrls.busUtil 21.79 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 11.47 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 10.32 # Data bus utilization in percentage for writes +system.mem_ctrls.avgRdQLen 1.76 # Average read queue length when enqueuing +system.mem_ctrls.avgWrQLen 25.13 # Average write queue length when enqueuing +system.mem_ctrls.readRowHits 625 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 635 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 87.66 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate 94.63 # Row buffer hit rate for writes +system.mem_ctrls.avgGap 18.88 # Average gap between requests +system.mem_ctrls.pageHitRate 91.04 # Row buffer hit rate, read and write combined +system.mem_ctrls_0.actEnergy 671160 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 347760 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 8145312 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 5353632 # Energy for write commands per rank (pJ) +system.mem_ctrls_0.refreshEnergy 1843920.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 8199792 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 36480 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.actPowerDownEnergy 5925264 # Energy for active power-down per rank (pJ) +system.mem_ctrls_0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls_0.totalEnergy 30523320 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 982.373274 # Core power per rank (mW) +system.mem_ctrls_0.totalIdleTime 12994 # Total Idle time Per DRAM Rank system.mem_ctrls_0.memoryStateTime::IDLE 11 # Time in different power states system.mem_ctrls_0.memoryStateTime::REF 780 # Time in different power states +system.mem_ctrls_0.memoryStateTime::SREF 0 # Time in different power states system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT 22844 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 17286 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT_PDN 12994 # Time in different power states system.mem_ctrls_1.actEnergy 0 # Energy for activate commands per rank (pJ) system.mem_ctrls_1.preEnergy 0 # Energy for precharge commands per rank (pJ) system.mem_ctrls_1.readEnergy 0 # Energy for read commands per rank (pJ) system.mem_ctrls_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.mem_ctrls_1.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_1.actBackEnergy 504792 # Energy for active background per rank (pJ) -system.mem_ctrls_1.preBackEnergy 13719600 # Energy for precharge background per rank (pJ) -system.mem_ctrls_1.totalEnergy 15750072 # Total energy per rank (pJ) -system.mem_ctrls_1.averagePower 667.262837 # Core power per rank (mW) -system.mem_ctrls_1.memoryStateTime::IDLE 22838 # Time in different power states -system.mem_ctrls_1.memoryStateTime::REF 780 # Time in different power states -system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_1.refreshEnergy 1229280.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 224352 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 3002880 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls_1.prePowerDownEnergy 2889984 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls_1.selfRefreshEnergy 3655920 # Energy for self refresh per rank (pJ) +system.mem_ctrls_1.totalEnergy 11002416 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 354.105629 # Core power per rank (mW) +system.mem_ctrls_1.totalIdleTime 7526 # Total Idle time Per DRAM Rank +system.mem_ctrls_1.memoryStateTime::IDLE 7786 # Time in different power states +system.mem_ctrls_1.memoryStateTime::REF 526 # Time in different power states +system.mem_ctrls_1.memoryStateTime::SREF 15233 # Time in different power states +system.mem_ctrls_1.memoryStateTime::PRE_PDN 7526 # Time in different power states system.mem_ctrls_1.memoryStateTime::ACT 0 # Time in different power states system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 29561 # Cumulative time (in ticks) in various power states -system.cpu.pwrStateResidencyTicks::UNDEFINED 29561 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 31071 # Cumulative time (in ticks) in various power states +system.cpu.pwrStateResidencyTicks::UNDEFINED 31071 # Cumulative time (in ticks) in various power states system.ruby.clk_domain.clock 1 # Clock period in ticks -system.ruby.pwrStateResidencyTicks::UNDEFINED 29561 # Cumulative time (in ticks) in various power states +system.ruby.pwrStateResidencyTicks::UNDEFINED 31071 # Cumulative time (in ticks) in various power states system.ruby.outstanding_req_hist_seqr::bucket_size 2 system.ruby.outstanding_req_hist_seqr::max_bucket 19 -system.ruby.outstanding_req_hist_seqr::samples 1027 -system.ruby.outstanding_req_hist_seqr::mean 15.566699 -system.ruby.outstanding_req_hist_seqr::gmean 15.456992 -system.ruby.outstanding_req_hist_seqr::stdev 1.265135 -system.ruby.outstanding_req_hist_seqr | 1 0.10% 0.10% | 2 0.19% 0.29% | 2 0.19% 0.49% | 3 0.29% 0.78% | 3 0.29% 1.07% | 6 0.58% 1.66% | 3 0.29% 1.95% | 271 26.39% 28.33% | 736 71.67% 100.00% | 0 0.00% 100.00% -system.ruby.outstanding_req_hist_seqr::total 1027 +system.ruby.outstanding_req_hist_seqr::samples 1010 +system.ruby.outstanding_req_hist_seqr::mean 15.556436 +system.ruby.outstanding_req_hist_seqr::gmean 15.445317 +system.ruby.outstanding_req_hist_seqr::stdev 1.273066 +system.ruby.outstanding_req_hist_seqr | 1 0.10% 0.10% | 2 0.20% 0.30% | 2 0.20% 0.50% | 3 0.30% 0.79% | 3 0.30% 1.09% | 6 0.59% 1.68% | 3 0.30% 1.98% | 272 26.93% 28.91% | 718 71.09% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist_seqr::total 1010 system.ruby.latency_hist_seqr::bucket_size 128 system.ruby.latency_hist_seqr::max_bucket 1279 -system.ruby.latency_hist_seqr::samples 1012 -system.ruby.latency_hist_seqr::mean 452.030632 -system.ruby.latency_hist_seqr::gmean 221.913062 -system.ruby.latency_hist_seqr::stdev 245.259624 -system.ruby.latency_hist_seqr | 227 22.43% 22.43% | 13 1.28% 23.72% | 6 0.59% 24.31% | 123 12.15% 36.46% | 525 51.88% 88.34% | 73 7.21% 95.55% | 35 3.46% 99.01% | 10 0.99% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.latency_hist_seqr::total 1012 -system.ruby.hit_latency_hist_seqr::bucket_size 64 -system.ruby.hit_latency_hist_seqr::max_bucket 639 -system.ruby.hit_latency_hist_seqr::samples 140 -system.ruby.hit_latency_hist_seqr::mean 75.100000 -system.ruby.hit_latency_hist_seqr::gmean 3.808266 -system.ruby.hit_latency_hist_seqr::stdev 173.693574 -system.ruby.hit_latency_hist_seqr | 117 83.57% 83.57% | 3 2.14% 85.71% | 1 0.71% 86.43% | 0 0.00% 86.43% | 0 0.00% 86.43% | 0 0.00% 86.43% | 4 2.86% 89.29% | 5 3.57% 92.86% | 8 5.71% 98.57% | 2 1.43% 100.00% -system.ruby.hit_latency_hist_seqr::total 140 +system.ruby.latency_hist_seqr::samples 995 +system.ruby.latency_hist_seqr::mean 482.717588 +system.ruby.latency_hist_seqr::gmean 245.065735 +system.ruby.latency_hist_seqr::stdev 262.743362 +system.ruby.latency_hist_seqr | 233 23.42% 23.42% | 9 0.90% 24.32% | 5 0.50% 24.82% | 58 5.83% 30.65% | 397 39.90% 70.55% | 236 23.72% 94.27% | 55 5.53% 99.80% | 2 0.20% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.latency_hist_seqr::total 995 +system.ruby.hit_latency_hist_seqr::bucket_size 128 +system.ruby.hit_latency_hist_seqr::max_bucket 1279 +system.ruby.hit_latency_hist_seqr::samples 135 +system.ruby.hit_latency_hist_seqr::mean 110.851852 +system.ruby.hit_latency_hist_seqr::gmean 6.261385 +system.ruby.hit_latency_hist_seqr::stdev 224.829770 +system.ruby.hit_latency_hist_seqr | 111 82.22% 82.22% | 0 0.00% 82.22% | 0 0.00% 82.22% | 3 2.22% 84.44% | 17 12.59% 97.04% | 3 2.22% 99.26% | 0 0.00% 99.26% | 1 0.74% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.hit_latency_hist_seqr::total 135 system.ruby.miss_latency_hist_seqr::bucket_size 128 system.ruby.miss_latency_hist_seqr::max_bucket 1279 -system.ruby.miss_latency_hist_seqr::samples 872 -system.ruby.miss_latency_hist_seqr::mean 512.547018 -system.ruby.miss_latency_hist_seqr::gmean 426.213857 -system.ruby.miss_latency_hist_seqr::stdev 196.222062 -system.ruby.miss_latency_hist_seqr | 107 12.27% 12.27% | 12 1.38% 13.65% | 6 0.69% 14.33% | 114 13.07% 27.41% | 515 59.06% 86.47% | 73 8.37% 94.84% | 35 4.01% 98.85% | 10 1.15% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.miss_latency_hist_seqr::total 872 -system.ruby.Directory.incomplete_times_seqr 872 +system.ruby.miss_latency_hist_seqr::samples 860 +system.ruby.miss_latency_hist_seqr::mean 541.091860 +system.ruby.miss_latency_hist_seqr::gmean 435.798434 +system.ruby.miss_latency_hist_seqr::stdev 216.457686 +system.ruby.miss_latency_hist_seqr | 122 14.19% 14.19% | 9 1.05% 15.23% | 5 0.58% 15.81% | 55 6.40% 22.21% | 380 44.19% 66.40% | 233 27.09% 93.49% | 55 6.40% 99.88% | 1 0.12% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.miss_latency_hist_seqr::total 860 +system.ruby.Directory.incomplete_times_seqr 860 system.ruby.dir_cntrl0.probeFilter.demand_hits 0 # Number of cache demand hits system.ruby.dir_cntrl0.probeFilter.demand_misses 0 # Number of cache demand misses system.ruby.dir_cntrl0.probeFilter.demand_accesses 0 # Number of cache demand accesses -system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 29561 # Cumulative time (in ticks) in various power states -system.ruby.l1_cntrl0.L1Dcache.demand_hits 96 # Number of cache demand hits -system.ruby.l1_cntrl0.L1Dcache.demand_misses 859 # Number of cache demand misses -system.ruby.l1_cntrl0.L1Dcache.demand_accesses 955 # Number of cache demand accesses -system.ruby.l1_cntrl0.L1Icache.demand_hits 3 # Number of cache demand hits -system.ruby.l1_cntrl0.L1Icache.demand_misses 54 # Number of cache demand misses -system.ruby.l1_cntrl0.L1Icache.demand_accesses 57 # Number of cache demand accesses -system.ruby.l1_cntrl0.L2cache.demand_hits 39 # Number of cache demand hits -system.ruby.l1_cntrl0.L2cache.demand_misses 874 # Number of cache demand misses -system.ruby.l1_cntrl0.L2cache.demand_accesses 913 # Number of cache demand accesses -system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 29561 # Cumulative time (in ticks) in various power states -system.ruby.l1_cntrl0.sequencer.store_waiting_on_load 8 # Number of times a store aliased with a pending load -system.ruby.l1_cntrl0.sequencer.store_waiting_on_store 72 # Number of times a store aliased with a pending store -system.ruby.l1_cntrl0.sequencer.load_waiting_on_store 4 # Number of times a load aliased with a pending store -system.ruby.l1_cntrl0.sequencer.load_waiting_on_load 3 # Number of times a load aliased with a pending load -system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 29561 # Cumulative time (in ticks) in various power states +system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 31071 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl0.L1Dcache.demand_hits 79 # Number of cache demand hits +system.ruby.l1_cntrl0.L1Dcache.demand_misses 852 # Number of cache demand misses +system.ruby.l1_cntrl0.L1Dcache.demand_accesses 931 # Number of cache demand accesses +system.ruby.l1_cntrl0.L1Icache.demand_hits 0 # Number of cache demand hits +system.ruby.l1_cntrl0.L1Icache.demand_misses 63 # Number of cache demand misses +system.ruby.l1_cntrl0.L1Icache.demand_accesses 63 # Number of cache demand accesses +system.ruby.l1_cntrl0.L2cache.demand_hits 54 # Number of cache demand hits +system.ruby.l1_cntrl0.L2cache.demand_misses 861 # Number of cache demand misses +system.ruby.l1_cntrl0.L2cache.demand_accesses 915 # Number of cache demand accesses +system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 31071 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl0.sequencer.store_waiting_on_load 3 # Number of times a store aliased with a pending load +system.ruby.l1_cntrl0.sequencer.store_waiting_on_store 84 # Number of times a store aliased with a pending store +system.ruby.l1_cntrl0.sequencer.load_waiting_on_store 7 # Number of times a load aliased with a pending store +system.ruby.l1_cntrl0.sequencer.load_waiting_on_load 1 # Number of times a load aliased with a pending load +system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 31071 # Cumulative time (in ticks) in various power states system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 29561 # Cumulative time (in ticks) in various power states -system.ruby.network.routers0.percent_links_utilized 15.685362 -system.ruby.network.routers0.msg_count.Request_Control::2 876 -system.ruby.network.routers0.msg_count.Response_Data::4 874 -system.ruby.network.routers0.msg_count.Writeback_Data::5 791 -system.ruby.network.routers0.msg_count.Writeback_Control::2 869 -system.ruby.network.routers0.msg_count.Writeback_Control::3 869 -system.ruby.network.routers0.msg_count.Writeback_Control::5 77 -system.ruby.network.routers0.msg_count.Unblock_Control::5 871 -system.ruby.network.routers0.msg_bytes.Request_Control::2 7008 -system.ruby.network.routers0.msg_bytes.Response_Data::4 62928 -system.ruby.network.routers0.msg_bytes.Writeback_Data::5 56952 -system.ruby.network.routers0.msg_bytes.Writeback_Control::2 6952 -system.ruby.network.routers0.msg_bytes.Writeback_Control::3 6952 -system.ruby.network.routers0.msg_bytes.Writeback_Control::5 616 -system.ruby.network.routers0.msg_bytes.Unblock_Control::5 6968 -system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 29561 # Cumulative time (in ticks) in various power states -system.ruby.network.routers1.percent_links_utilized 15.679443 -system.ruby.network.routers1.msg_count.Request_Control::2 876 -system.ruby.network.routers1.msg_count.Response_Data::4 874 -system.ruby.network.routers1.msg_count.Writeback_Data::5 791 -system.ruby.network.routers1.msg_count.Writeback_Control::2 869 -system.ruby.network.routers1.msg_count.Writeback_Control::3 869 -system.ruby.network.routers1.msg_count.Writeback_Control::5 77 -system.ruby.network.routers1.msg_count.Unblock_Control::5 871 -system.ruby.network.routers1.msg_bytes.Request_Control::2 7008 -system.ruby.network.routers1.msg_bytes.Response_Data::4 62928 -system.ruby.network.routers1.msg_bytes.Writeback_Data::5 56952 -system.ruby.network.routers1.msg_bytes.Writeback_Control::2 6952 -system.ruby.network.routers1.msg_bytes.Writeback_Control::3 6952 -system.ruby.network.routers1.msg_bytes.Writeback_Control::5 616 -system.ruby.network.routers1.msg_bytes.Unblock_Control::5 6968 -system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 29561 # Cumulative time (in ticks) in various power states -system.ruby.network.routers2.percent_links_utilized 15.682825 -system.ruby.network.routers2.msg_count.Request_Control::2 876 -system.ruby.network.routers2.msg_count.Response_Data::4 874 -system.ruby.network.routers2.msg_count.Writeback_Data::5 791 -system.ruby.network.routers2.msg_count.Writeback_Control::2 869 -system.ruby.network.routers2.msg_count.Writeback_Control::3 869 -system.ruby.network.routers2.msg_count.Writeback_Control::5 77 -system.ruby.network.routers2.msg_count.Unblock_Control::5 871 -system.ruby.network.routers2.msg_bytes.Request_Control::2 7008 -system.ruby.network.routers2.msg_bytes.Response_Data::4 62928 -system.ruby.network.routers2.msg_bytes.Writeback_Data::5 56952 -system.ruby.network.routers2.msg_bytes.Writeback_Control::2 6952 -system.ruby.network.routers2.msg_bytes.Writeback_Control::3 6952 -system.ruby.network.routers2.msg_bytes.Writeback_Control::5 616 -system.ruby.network.routers2.msg_bytes.Unblock_Control::5 6968 -system.ruby.network.pwrStateResidencyTicks::UNDEFINED 29561 # Cumulative time (in ticks) in various power states -system.ruby.network.msg_count.Request_Control 2628 -system.ruby.network.msg_count.Response_Data 2622 -system.ruby.network.msg_count.Writeback_Data 2373 -system.ruby.network.msg_count.Writeback_Control 5445 -system.ruby.network.msg_count.Unblock_Control 2613 -system.ruby.network.msg_byte.Request_Control 21024 -system.ruby.network.msg_byte.Response_Data 188784 -system.ruby.network.msg_byte.Writeback_Data 170856 -system.ruby.network.msg_byte.Writeback_Control 43560 -system.ruby.network.msg_byte.Unblock_Control 20904 -system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 29561 # Cumulative time (in ticks) in various power states -system.ruby.network.routers0.throttle0.link_utilization 14.774534 -system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 874 -system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 869 -system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 62928 -system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 6952 -system.ruby.network.routers0.throttle1.link_utilization 16.596191 -system.ruby.network.routers0.throttle1.msg_count.Request_Control::2 876 -system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::5 791 -system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::2 869 -system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::5 77 -system.ruby.network.routers0.throttle1.msg_count.Unblock_Control::5 871 -system.ruby.network.routers0.throttle1.msg_bytes.Request_Control::2 7008 -system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::5 56952 -system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::2 6952 -system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::5 616 -system.ruby.network.routers0.throttle1.msg_bytes.Unblock_Control::5 6968 -system.ruby.network.routers1.throttle0.link_utilization 16.584351 -system.ruby.network.routers1.throttle0.msg_count.Request_Control::2 876 -system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::5 791 -system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::2 869 -system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::5 77 -system.ruby.network.routers1.throttle0.msg_count.Unblock_Control::5 871 -system.ruby.network.routers1.throttle0.msg_bytes.Request_Control::2 7008 -system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::5 56952 -system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::2 6952 -system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::5 616 -system.ruby.network.routers1.throttle0.msg_bytes.Unblock_Control::5 6968 -system.ruby.network.routers1.throttle1.link_utilization 14.774534 -system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 874 -system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 869 -system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 62928 -system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 6952 -system.ruby.network.routers2.throttle0.link_utilization 14.774534 -system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 874 -system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 869 -system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 62928 -system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 6952 -system.ruby.network.routers2.throttle1.link_utilization 16.591117 -system.ruby.network.routers2.throttle1.msg_count.Request_Control::2 876 -system.ruby.network.routers2.throttle1.msg_count.Writeback_Data::5 791 -system.ruby.network.routers2.throttle1.msg_count.Writeback_Control::2 869 -system.ruby.network.routers2.throttle1.msg_count.Writeback_Control::5 77 -system.ruby.network.routers2.throttle1.msg_count.Unblock_Control::5 871 -system.ruby.network.routers2.throttle1.msg_bytes.Request_Control::2 7008 -system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Data::5 56952 -system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Control::2 6952 -system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Control::5 616 -system.ruby.network.routers2.throttle1.msg_bytes.Unblock_Control::5 6968 +system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 31071 # Cumulative time (in ticks) in various power states +system.ruby.network.routers0.percent_links_utilized 14.722732 +system.ruby.network.routers0.msg_count.Request_Control::2 863 +system.ruby.network.routers0.msg_count.Response_Data::4 861 +system.ruby.network.routers0.msg_count.Writeback_Data::5 783 +system.ruby.network.routers0.msg_count.Writeback_Control::2 855 +system.ruby.network.routers0.msg_count.Writeback_Control::3 856 +system.ruby.network.routers0.msg_count.Writeback_Control::5 71 +system.ruby.network.routers0.msg_count.Unblock_Control::5 859 +system.ruby.network.routers0.msg_bytes.Request_Control::2 6904 +system.ruby.network.routers0.msg_bytes.Response_Data::4 61992 +system.ruby.network.routers0.msg_bytes.Writeback_Data::5 56376 +system.ruby.network.routers0.msg_bytes.Writeback_Control::2 6840 +system.ruby.network.routers0.msg_bytes.Writeback_Control::3 6848 +system.ruby.network.routers0.msg_bytes.Writeback_Control::5 568 +system.ruby.network.routers0.msg_bytes.Unblock_Control::5 6872 +system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 31071 # Cumulative time (in ticks) in various power states +system.ruby.network.routers1.percent_links_utilized 14.717100 +system.ruby.network.routers1.msg_count.Request_Control::2 863 +system.ruby.network.routers1.msg_count.Response_Data::4 861 +system.ruby.network.routers1.msg_count.Writeback_Data::5 782 +system.ruby.network.routers1.msg_count.Writeback_Control::2 855 +system.ruby.network.routers1.msg_count.Writeback_Control::3 856 +system.ruby.network.routers1.msg_count.Writeback_Control::5 71 +system.ruby.network.routers1.msg_count.Unblock_Control::5 859 +system.ruby.network.routers1.msg_bytes.Request_Control::2 6904 +system.ruby.network.routers1.msg_bytes.Response_Data::4 61992 +system.ruby.network.routers1.msg_bytes.Writeback_Data::5 56304 +system.ruby.network.routers1.msg_bytes.Writeback_Control::2 6840 +system.ruby.network.routers1.msg_bytes.Writeback_Control::3 6848 +system.ruby.network.routers1.msg_bytes.Writeback_Control::5 568 +system.ruby.network.routers1.msg_bytes.Unblock_Control::5 6872 +system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 31071 # Cumulative time (in ticks) in various power states +system.ruby.network.routers2.percent_links_utilized 14.720318 +system.ruby.network.routers2.msg_count.Request_Control::2 863 +system.ruby.network.routers2.msg_count.Response_Data::4 861 +system.ruby.network.routers2.msg_count.Writeback_Data::5 783 +system.ruby.network.routers2.msg_count.Writeback_Control::2 855 +system.ruby.network.routers2.msg_count.Writeback_Control::3 856 +system.ruby.network.routers2.msg_count.Writeback_Control::5 71 +system.ruby.network.routers2.msg_count.Unblock_Control::5 859 +system.ruby.network.routers2.msg_bytes.Request_Control::2 6904 +system.ruby.network.routers2.msg_bytes.Response_Data::4 61992 +system.ruby.network.routers2.msg_bytes.Writeback_Data::5 56376 +system.ruby.network.routers2.msg_bytes.Writeback_Control::2 6840 +system.ruby.network.routers2.msg_bytes.Writeback_Control::3 6848 +system.ruby.network.routers2.msg_bytes.Writeback_Control::5 568 +system.ruby.network.routers2.msg_bytes.Unblock_Control::5 6872 +system.ruby.network.pwrStateResidencyTicks::UNDEFINED 31071 # Cumulative time (in ticks) in various power states +system.ruby.network.msg_count.Request_Control 2589 +system.ruby.network.msg_count.Response_Data 2583 +system.ruby.network.msg_count.Writeback_Data 2348 +system.ruby.network.msg_count.Writeback_Control 5346 +system.ruby.network.msg_count.Unblock_Control 2577 +system.ruby.network.msg_byte.Request_Control 20712 +system.ruby.network.msg_byte.Response_Data 185976 +system.ruby.network.msg_byte.Writeback_Data 169056 +system.ruby.network.msg_byte.Writeback_Control 42768 +system.ruby.network.msg_byte.Unblock_Control 20616 +system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 31071 # Cumulative time (in ticks) in various power states +system.ruby.network.routers0.throttle0.link_utilization 13.845708 +system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 861 +system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 856 +system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 61992 +system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 6848 +system.ruby.network.routers0.throttle1.link_utilization 15.599755 +system.ruby.network.routers0.throttle1.msg_count.Request_Control::2 863 +system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::5 783 +system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::2 855 +system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::5 71 +system.ruby.network.routers0.throttle1.msg_count.Unblock_Control::5 859 +system.ruby.network.routers0.throttle1.msg_bytes.Request_Control::2 6904 +system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::5 56376 +system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::2 6840 +system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::5 568 +system.ruby.network.routers0.throttle1.msg_bytes.Unblock_Control::5 6872 +system.ruby.network.routers1.throttle0.link_utilization 15.586882 +system.ruby.network.routers1.throttle0.msg_count.Request_Control::2 863 +system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::5 782 +system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::2 855 +system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::5 71 +system.ruby.network.routers1.throttle0.msg_count.Unblock_Control::5 859 +system.ruby.network.routers1.throttle0.msg_bytes.Request_Control::2 6904 +system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::5 56304 +system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::2 6840 +system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::5 568 +system.ruby.network.routers1.throttle0.msg_bytes.Unblock_Control::5 6872 +system.ruby.network.routers1.throttle1.link_utilization 13.847317 +system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 861 +system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 856 +system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 61992 +system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 6848 +system.ruby.network.routers2.throttle0.link_utilization 13.847317 +system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 861 +system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 856 +system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 61992 +system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 6848 +system.ruby.network.routers2.throttle1.link_utilization 15.593319 +system.ruby.network.routers2.throttle1.msg_count.Request_Control::2 863 +system.ruby.network.routers2.throttle1.msg_count.Writeback_Data::5 783 +system.ruby.network.routers2.throttle1.msg_count.Writeback_Control::2 855 +system.ruby.network.routers2.throttle1.msg_count.Writeback_Control::5 71 +system.ruby.network.routers2.throttle1.msg_count.Unblock_Control::5 859 +system.ruby.network.routers2.throttle1.msg_bytes.Request_Control::2 6904 +system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Data::5 56376 +system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Control::2 6840 +system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Control::5 568 +system.ruby.network.routers2.throttle1.msg_bytes.Unblock_Control::5 6872 system.ruby.LD.latency_hist_seqr::bucket_size 128 system.ruby.LD.latency_hist_seqr::max_bucket 1279 -system.ruby.LD.latency_hist_seqr::samples 43 -system.ruby.LD.latency_hist_seqr::mean 511.511628 -system.ruby.LD.latency_hist_seqr::gmean 293.373548 -system.ruby.LD.latency_hist_seqr::stdev 216.139767 -system.ruby.LD.latency_hist_seqr | 6 13.95% 13.95% | 0 0.00% 13.95% | 0 0.00% 13.95% | 7 16.28% 30.23% | 23 53.49% 83.72% | 5 11.63% 95.35% | 1 2.33% 97.67% | 1 2.33% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.latency_hist_seqr::total 43 -system.ruby.LD.hit_latency_hist_seqr::bucket_size 1 -system.ruby.LD.hit_latency_hist_seqr::max_bucket 9 -system.ruby.LD.hit_latency_hist_seqr::samples 4 -system.ruby.LD.hit_latency_hist_seqr::mean 1 -system.ruby.LD.hit_latency_hist_seqr::gmean 1 -system.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 4 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.hit_latency_hist_seqr::total 4 +system.ruby.LD.latency_hist_seqr::samples 37 +system.ruby.LD.latency_hist_seqr::mean 484.027027 +system.ruby.LD.latency_hist_seqr::gmean 206.042037 +system.ruby.LD.latency_hist_seqr::stdev 286.676016 +system.ruby.LD.latency_hist_seqr | 10 27.03% 27.03% | 0 0.00% 27.03% | 0 0.00% 27.03% | 0 0.00% 27.03% | 12 32.43% 59.46% | 13 35.14% 94.59% | 2 5.41% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.latency_hist_seqr::total 37 +system.ruby.LD.hit_latency_hist_seqr::bucket_size 64 +system.ruby.LD.hit_latency_hist_seqr::max_bucket 639 +system.ruby.LD.hit_latency_hist_seqr::samples 6 +system.ruby.LD.hit_latency_hist_seqr::mean 104 +system.ruby.LD.hit_latency_hist_seqr::gmean 4.461922 +system.ruby.LD.hit_latency_hist_seqr::stdev 246.465413 +system.ruby.LD.hit_latency_hist_seqr | 5 83.33% 83.33% | 0 0.00% 83.33% | 0 0.00% 83.33% | 0 0.00% 83.33% | 0 0.00% 83.33% | 0 0.00% 83.33% | 0 0.00% 83.33% | 0 0.00% 83.33% | 0 0.00% 83.33% | 1 16.67% 100.00% +system.ruby.LD.hit_latency_hist_seqr::total 6 system.ruby.LD.miss_latency_hist_seqr::bucket_size 128 system.ruby.LD.miss_latency_hist_seqr::max_bucket 1279 -system.ruby.LD.miss_latency_hist_seqr::samples 39 -system.ruby.LD.miss_latency_hist_seqr::mean 563.871795 -system.ruby.LD.miss_latency_hist_seqr::gmean 525.399638 -system.ruby.LD.miss_latency_hist_seqr::stdev 146.240462 -system.ruby.LD.miss_latency_hist_seqr | 2 5.13% 5.13% | 0 0.00% 5.13% | 0 0.00% 5.13% | 7 17.95% 23.08% | 23 58.97% 82.05% | 5 12.82% 94.87% | 1 2.56% 97.44% | 1 2.56% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.miss_latency_hist_seqr::total 39 +system.ruby.LD.miss_latency_hist_seqr::samples 31 +system.ruby.LD.miss_latency_hist_seqr::mean 557.580645 +system.ruby.LD.miss_latency_hist_seqr::gmean 432.617733 +system.ruby.LD.miss_latency_hist_seqr::stdev 232.424149 +system.ruby.LD.miss_latency_hist_seqr | 5 16.13% 16.13% | 0 0.00% 16.13% | 0 0.00% 16.13% | 0 0.00% 16.13% | 11 35.48% 51.61% | 13 41.94% 93.55% | 2 6.45% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.miss_latency_hist_seqr::total 31 system.ruby.ST.latency_hist_seqr::bucket_size 128 system.ruby.ST.latency_hist_seqr::max_bucket 1279 -system.ruby.ST.latency_hist_seqr::samples 910 -system.ruby.ST.latency_hist_seqr::mean 473.924176 -system.ruby.ST.latency_hist_seqr::gmean 243.035413 -system.ruby.ST.latency_hist_seqr::stdev 232.681347 -system.ruby.ST.latency_hist_seqr | 166 18.24% 18.24% | 11 1.21% 19.45% | 6 0.66% 20.11% | 116 12.75% 32.86% | 500 54.95% 87.80% | 68 7.47% 95.27% | 34 3.74% 99.01% | 9 0.99% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.latency_hist_seqr::total 910 -system.ruby.ST.hit_latency_hist_seqr::bucket_size 64 -system.ruby.ST.hit_latency_hist_seqr::max_bucket 639 -system.ruby.ST.hit_latency_hist_seqr::samples 126 -system.ruby.ST.hit_latency_hist_seqr::mean 74.587302 -system.ruby.ST.hit_latency_hist_seqr::gmean 3.636852 -system.ruby.ST.hit_latency_hist_seqr::stdev 172.646982 -system.ruby.ST.hit_latency_hist_seqr | 105 83.33% 83.33% | 3 2.38% 85.71% | 1 0.79% 86.51% | 0 0.00% 86.51% | 0 0.00% 86.51% | 0 0.00% 86.51% | 4 3.17% 89.68% | 5 3.97% 93.65% | 6 4.76% 98.41% | 2 1.59% 100.00% -system.ruby.ST.hit_latency_hist_seqr::total 126 +system.ruby.ST.latency_hist_seqr::samples 893 +system.ruby.ST.latency_hist_seqr::mean 513.324748 +system.ruby.ST.latency_hist_seqr::gmean 281.060775 +system.ruby.ST.latency_hist_seqr::stdev 242.626948 +system.ruby.ST.latency_hist_seqr | 160 17.92% 17.92% | 8 0.90% 18.81% | 5 0.56% 19.37% | 58 6.49% 25.87% | 385 43.11% 68.98% | 223 24.97% 93.95% | 53 5.94% 99.89% | 1 0.11% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.latency_hist_seqr::total 893 +system.ruby.ST.hit_latency_hist_seqr::bucket_size 128 +system.ruby.ST.hit_latency_hist_seqr::max_bucket 1279 +system.ruby.ST.hit_latency_hist_seqr::samples 116 +system.ruby.ST.hit_latency_hist_seqr::mean 114.353448 +system.ruby.ST.hit_latency_hist_seqr::gmean 5.688161 +system.ruby.ST.hit_latency_hist_seqr::stdev 222.966921 +system.ruby.ST.hit_latency_hist_seqr | 94 81.03% 81.03% | 0 0.00% 81.03% | 0 0.00% 81.03% | 3 2.59% 83.62% | 16 13.79% 97.41% | 3 2.59% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.hit_latency_hist_seqr::total 116 system.ruby.ST.miss_latency_hist_seqr::bucket_size 128 system.ruby.ST.miss_latency_hist_seqr::max_bucket 1279 -system.ruby.ST.miss_latency_hist_seqr::samples 784 -system.ruby.ST.miss_latency_hist_seqr::mean 538.103316 -system.ruby.ST.miss_latency_hist_seqr::gmean 477.489826 -system.ruby.ST.miss_latency_hist_seqr::stdev 168.250948 -system.ruby.ST.miss_latency_hist_seqr | 58 7.40% 7.40% | 10 1.28% 8.67% | 6 0.77% 9.44% | 107 13.65% 23.09% | 492 62.76% 85.84% | 68 8.67% 94.52% | 34 4.34% 98.85% | 9 1.15% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.miss_latency_hist_seqr::total 784 -system.ruby.IFETCH.latency_hist_seqr::bucket_size 16 -system.ruby.IFETCH.latency_hist_seqr::max_bucket 159 -system.ruby.IFETCH.latency_hist_seqr::samples 57 -system.ruby.IFETCH.latency_hist_seqr::mean 55 -system.ruby.IFETCH.latency_hist_seqr::gmean 40.845512 -system.ruby.IFETCH.latency_hist_seqr::stdev 30.808162 -system.ruby.IFETCH.latency_hist_seqr | 8 14.04% 14.04% | 6 10.53% 24.56% | 1 1.75% 26.32% | 27 47.37% 73.68% | 9 15.79% 89.47% | 3 5.26% 94.74% | 1 1.75% 96.49% | 0 0.00% 96.49% | 0 0.00% 96.49% | 2 3.51% 100.00% -system.ruby.IFETCH.latency_hist_seqr::total 57 +system.ruby.ST.miss_latency_hist_seqr::samples 777 +system.ruby.ST.miss_latency_hist_seqr::mean 572.888031 +system.ruby.ST.miss_latency_hist_seqr::gmean 503.124564 +system.ruby.ST.miss_latency_hist_seqr::stdev 181.530163 +system.ruby.ST.miss_latency_hist_seqr | 66 8.49% 8.49% | 8 1.03% 9.52% | 5 0.64% 10.17% | 55 7.08% 17.25% | 369 47.49% 64.74% | 220 28.31% 93.05% | 53 6.82% 99.87% | 1 0.13% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.miss_latency_hist_seqr::total 777 +system.ruby.IFETCH.latency_hist_seqr::bucket_size 32 +system.ruby.IFETCH.latency_hist_seqr::max_bucket 319 +system.ruby.IFETCH.latency_hist_seqr::samples 63 +system.ruby.IFETCH.latency_hist_seqr::mean 48.269841 +system.ruby.IFETCH.latency_hist_seqr::gmean 39.118214 +system.ruby.IFETCH.latency_hist_seqr::stdev 28.730790 +system.ruby.IFETCH.latency_hist_seqr | 25 39.68% 39.68% | 19 30.16% 69.84% | 18 28.57% 98.41% | 0 0.00% 98.41% | 0 0.00% 98.41% | 1 1.59% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.latency_hist_seqr::total 63 system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 2 system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 19 -system.ruby.IFETCH.hit_latency_hist_seqr::samples 8 -system.ruby.IFETCH.hit_latency_hist_seqr::mean 7.250000 -system.ruby.IFETCH.hit_latency_hist_seqr::gmean 4.475797 -system.ruby.IFETCH.hit_latency_hist_seqr::stdev 5.175492 -system.ruby.IFETCH.hit_latency_hist_seqr | 3 37.50% 37.50% | 0 0.00% 37.50% | 0 0.00% 37.50% | 0 0.00% 37.50% | 0 0.00% 37.50% | 5 62.50% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.hit_latency_hist_seqr::total 8 -system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 16 -system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 159 -system.ruby.IFETCH.miss_latency_hist_seqr::samples 49 -system.ruby.IFETCH.miss_latency_hist_seqr::mean 62.795918 -system.ruby.IFETCH.miss_latency_hist_seqr::gmean 58.603527 -system.ruby.IFETCH.miss_latency_hist_seqr::stdev 25.717196 -system.ruby.IFETCH.miss_latency_hist_seqr | 0 0.00% 0.00% | 6 12.24% 12.24% | 1 2.04% 14.29% | 27 55.10% 69.39% | 9 18.37% 87.76% | 3 6.12% 93.88% | 1 2.04% 95.92% | 0 0.00% 95.92% | 0 0.00% 95.92% | 2 4.08% 100.00% -system.ruby.IFETCH.miss_latency_hist_seqr::total 49 -system.ruby.FLUSH.latency_hist_seqr::bucket_size 64 -system.ruby.FLUSH.latency_hist_seqr::max_bucket 639 +system.ruby.IFETCH.hit_latency_hist_seqr::samples 11 +system.ruby.IFETCH.hit_latency_hist_seqr::mean 11 +system.ruby.IFETCH.hit_latency_hist_seqr::gmean 11.000000 +system.ruby.IFETCH.hit_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 11 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.hit_latency_hist_seqr::total 11 +system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 32 +system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 319 +system.ruby.IFETCH.miss_latency_hist_seqr::samples 52 +system.ruby.IFETCH.miss_latency_hist_seqr::mean 56.153846 +system.ruby.IFETCH.miss_latency_hist_seqr::gmean 51.160387 +system.ruby.IFETCH.miss_latency_hist_seqr::stdev 25.308593 +system.ruby.IFETCH.miss_latency_hist_seqr | 14 26.92% 26.92% | 19 36.54% 63.46% | 18 34.62% 98.08% | 0 0.00% 98.08% | 0 0.00% 98.08% | 1 1.92% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.miss_latency_hist_seqr::total 52 +system.ruby.FLUSH.latency_hist_seqr::bucket_size 128 +system.ruby.FLUSH.latency_hist_seqr::max_bucket 1279 system.ruby.FLUSH.latency_hist_seqr::samples 2 -system.ruby.FLUSH.latency_hist_seqr::mean 527 -system.ruby.FLUSH.latency_hist_seqr::gmean 526.885187 -system.ruby.FLUSH.latency_hist_seqr::stdev 15.556349 -system.ruby.FLUSH.latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 2 100.00% 100.00% | 0 0.00% 100.00% +system.ruby.FLUSH.latency_hist_seqr::mean 477.500000 +system.ruby.FLUSH.latency_hist_seqr::gmean 204.484718 +system.ruby.FLUSH.latency_hist_seqr::stdev 610.233152 +system.ruby.FLUSH.latency_hist_seqr | 1 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.FLUSH.latency_hist_seqr::total 2 -system.ruby.FLUSH.hit_latency_hist_seqr::bucket_size 64 -system.ruby.FLUSH.hit_latency_hist_seqr::max_bucket 639 +system.ruby.FLUSH.hit_latency_hist_seqr::bucket_size 128 +system.ruby.FLUSH.hit_latency_hist_seqr::max_bucket 1279 system.ruby.FLUSH.hit_latency_hist_seqr::samples 2 -system.ruby.FLUSH.hit_latency_hist_seqr::mean 527 -system.ruby.FLUSH.hit_latency_hist_seqr::gmean 526.885187 -system.ruby.FLUSH.hit_latency_hist_seqr::stdev 15.556349 -system.ruby.FLUSH.hit_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 2 100.00% 100.00% | 0 0.00% 100.00% +system.ruby.FLUSH.hit_latency_hist_seqr::mean 477.500000 +system.ruby.FLUSH.hit_latency_hist_seqr::gmean 204.484718 +system.ruby.FLUSH.hit_latency_hist_seqr::stdev 610.233152 +system.ruby.FLUSH.hit_latency_hist_seqr | 1 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.FLUSH.hit_latency_hist_seqr::total 2 -system.ruby.L1Cache.hit_mach_latency_hist_seqr::bucket_size 64 -system.ruby.L1Cache.hit_mach_latency_hist_seqr::max_bucket 639 -system.ruby.L1Cache.hit_mach_latency_hist_seqr::samples 101 -system.ruby.L1Cache.hit_mach_latency_hist_seqr::mean 11.415842 -system.ruby.L1Cache.hit_mach_latency_hist_seqr::gmean 1.132128 -system.ruby.L1Cache.hit_mach_latency_hist_seqr::stdev 73.663867 -system.ruby.L1Cache.hit_mach_latency_hist_seqr | 99 98.02% 98.02% | 0 0.00% 98.02% | 0 0.00% 98.02% | 0 0.00% 98.02% | 0 0.00% 98.02% | 0 0.00% 98.02% | 0 0.00% 98.02% | 0 0.00% 98.02% | 2 1.98% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache.hit_mach_latency_hist_seqr::total 101 -system.ruby.L2Cache.hit_mach_latency_hist_seqr::bucket_size 64 -system.ruby.L2Cache.hit_mach_latency_hist_seqr::max_bucket 639 -system.ruby.L2Cache.hit_mach_latency_hist_seqr::samples 39 -system.ruby.L2Cache.hit_mach_latency_hist_seqr::mean 240.025641 -system.ruby.L2Cache.hit_mach_latency_hist_seqr::gmean 88.122529 -system.ruby.L2Cache.hit_mach_latency_hist_seqr::stdev 239.543259 -system.ruby.L2Cache.hit_mach_latency_hist_seqr | 18 46.15% 46.15% | 3 7.69% 53.85% | 1 2.56% 56.41% | 0 0.00% 56.41% | 0 0.00% 56.41% | 0 0.00% 56.41% | 4 10.26% 66.67% | 5 12.82% 79.49% | 6 15.38% 94.87% | 2 5.13% 100.00% -system.ruby.L2Cache.hit_mach_latency_hist_seqr::total 39 +system.ruby.L1Cache.hit_mach_latency_hist_seqr::bucket_size 128 +system.ruby.L1Cache.hit_mach_latency_hist_seqr::max_bucket 1279 +system.ruby.L1Cache.hit_mach_latency_hist_seqr::samples 81 +system.ruby.L1Cache.hit_mach_latency_hist_seqr::mean 12.765432 +system.ruby.L1Cache.hit_mach_latency_hist_seqr::gmean 1.140390 +system.ruby.L1Cache.hit_mach_latency_hist_seqr::stdev 100.950269 +system.ruby.L1Cache.hit_mach_latency_hist_seqr | 80 98.77% 98.77% | 0 0.00% 98.77% | 0 0.00% 98.77% | 0 0.00% 98.77% | 0 0.00% 98.77% | 0 0.00% 98.77% | 0 0.00% 98.77% | 1 1.23% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache.hit_mach_latency_hist_seqr::total 81 +system.ruby.L2Cache.hit_mach_latency_hist_seqr::bucket_size 128 +system.ruby.L2Cache.hit_mach_latency_hist_seqr::max_bucket 1279 +system.ruby.L2Cache.hit_mach_latency_hist_seqr::samples 54 +system.ruby.L2Cache.hit_mach_latency_hist_seqr::mean 257.981481 +system.ruby.L2Cache.hit_mach_latency_hist_seqr::gmean 80.555654 +system.ruby.L2Cache.hit_mach_latency_hist_seqr::stdev 275.063320 +system.ruby.L2Cache.hit_mach_latency_hist_seqr | 31 57.41% 57.41% | 0 0.00% 57.41% | 0 0.00% 57.41% | 3 5.56% 62.96% | 17 31.48% 94.44% | 3 5.56% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L2Cache.hit_mach_latency_hist_seqr::total 54 system.ruby.Directory.miss_mach_latency_hist_seqr::bucket_size 128 system.ruby.Directory.miss_mach_latency_hist_seqr::max_bucket 1279 -system.ruby.Directory.miss_mach_latency_hist_seqr::samples 872 -system.ruby.Directory.miss_mach_latency_hist_seqr::mean 512.547018 -system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 426.213857 -system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 196.222062 -system.ruby.Directory.miss_mach_latency_hist_seqr | 107 12.27% 12.27% | 12 1.38% 13.65% | 6 0.69% 14.33% | 114 13.07% 27.41% | 515 59.06% 86.47% | 73 8.37% 94.84% | 35 4.01% 98.85% | 10 1.15% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_mach_latency_hist_seqr::total 872 +system.ruby.Directory.miss_mach_latency_hist_seqr::samples 860 +system.ruby.Directory.miss_mach_latency_hist_seqr::mean 541.091860 +system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 435.798434 +system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 216.457686 +system.ruby.Directory.miss_mach_latency_hist_seqr | 122 14.19% 14.19% | 9 1.05% 15.23% | 5 0.58% 15.81% | 55 6.40% 22.21% | 380 44.19% 66.40% | 233 27.09% 93.49% | 55 6.40% 99.88% | 1 0.12% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_mach_latency_hist_seqr::total 860 system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::bucket_size 1 system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::max_bucket 9 system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::samples 4 @@ -545,142 +554,146 @@ system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::mean 1 system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::gmean 1 system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 4 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::total 4 +system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::bucket_size 64 +system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::max_bucket 639 +system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::samples 2 +system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::mean 310 +system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::gmean 88.831301 +system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::stdev 420.021428 +system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr | 1 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 1 50.00% 100.00% +system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::total 2 system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size 128 system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket 1279 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples 39 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 563.871795 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 525.399638 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 146.240462 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 2 5.13% 5.13% | 0 0.00% 5.13% | 0 0.00% 5.13% | 7 17.95% 23.08% | 23 58.97% 82.05% | 5 12.82% 94.87% | 1 2.56% 97.44% | 1 2.56% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total 39 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples 31 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 557.580645 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 432.617733 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 232.424149 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 5 16.13% 16.13% | 0 0.00% 16.13% | 0 0.00% 16.13% | 0 0.00% 16.13% | 11 35.48% 51.61% | 13 41.94% 93.55% | 2 6.45% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total 31 system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::bucket_size 1 system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::max_bucket 9 -system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::samples 92 +system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::samples 75 system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::mean 1 system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::gmean 1 -system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 92 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::total 92 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::bucket_size 64 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::max_bucket 639 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::samples 34 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::mean 273.705882 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::gmean 119.669415 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::stdev 238.660724 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr | 13 38.24% 38.24% | 3 8.82% 47.06% | 1 2.94% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 4 11.76% 61.76% | 5 14.71% 76.47% | 6 17.65% 94.12% | 2 5.88% 100.00% -system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::total 34 +system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 75 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::total 75 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::bucket_size 128 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::max_bucket 1279 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::samples 41 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::mean 321.707317 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::gmean 136.778519 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::stdev 273.433835 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr | 19 46.34% 46.34% | 0 0.00% 46.34% | 0 0.00% 46.34% | 3 7.32% 53.66% | 16 39.02% 92.68% | 3 7.32% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::total 41 system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size 128 system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket 1279 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::samples 784 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 538.103316 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 477.489826 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 168.250948 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 58 7.40% 7.40% | 10 1.28% 8.67% | 6 0.77% 9.44% | 107 13.65% 23.09% | 492 62.76% 85.84% | 68 8.67% 94.52% | 34 4.34% 98.85% | 9 1.15% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total 784 -system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::bucket_size 1 -system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::max_bucket 9 -system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::samples 3 -system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::mean 1 -system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::gmean 1 -system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 3 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::total 3 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::samples 777 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 572.888031 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 503.124564 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 181.530163 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 66 8.49% 8.49% | 8 1.03% 9.52% | 5 0.64% 10.17% | 55 7.08% 17.25% | 369 47.49% 64.74% | 220 28.31% 93.05% | 53 6.82% 99.87% | 1 0.13% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total 777 system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::bucket_size 2 system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::max_bucket 19 -system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::samples 5 +system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::samples 11 system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::mean 11 system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::gmean 11.000000 -system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 5 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::total 5 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::bucket_size 16 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::max_bucket 159 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::samples 49 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 62.795918 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 58.603527 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 25.717196 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 6 12.24% 12.24% | 1 2.04% 14.29% | 27 55.10% 69.39% | 9 18.37% 87.76% | 3 6.12% 93.88% | 1 2.04% 95.92% | 0 0.00% 95.92% | 0 0.00% 95.92% | 2 4.08% 100.00% -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::total 49 -system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist_seqr::bucket_size 64 -system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist_seqr::max_bucket 639 +system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 11 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::total 11 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::bucket_size 32 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::max_bucket 319 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::samples 52 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 56.153846 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 51.160387 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 25.308593 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 14 26.92% 26.92% | 19 36.54% 63.46% | 18 34.62% 98.08% | 0 0.00% 98.08% | 0 0.00% 98.08% | 1 1.92% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::total 52 +system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist_seqr::bucket_size 128 +system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist_seqr::max_bucket 1279 system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist_seqr::samples 2 -system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist_seqr::mean 527 -system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist_seqr::gmean 526.885187 -system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist_seqr::stdev 15.556349 -system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 2 100.00% 100.00% | 0 0.00% 100.00% +system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist_seqr::mean 477.500000 +system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist_seqr::gmean 204.484718 +system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist_seqr::stdev 610.233152 +system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist_seqr | 1 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist_seqr::total 2 -system.ruby.Directory_Controller.GETX 785 0.00% 0.00% -system.ruby.Directory_Controller.GETS 90 0.00% 0.00% -system.ruby.Directory_Controller.PUT 1118 0.00% 0.00% -system.ruby.Directory_Controller.UnblockM 871 0.00% 0.00% -system.ruby.Directory_Controller.Writeback_Exclusive_Clean 77 0.00% 0.00% -system.ruby.Directory_Controller.Writeback_Exclusive_Dirty 790 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 874 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 790 0.00% 0.00% +system.ruby.Directory_Controller.GETX 778 0.00% 0.00% +system.ruby.Directory_Controller.GETS 84 0.00% 0.00% +system.ruby.Directory_Controller.PUT 1099 0.00% 0.00% +system.ruby.Directory_Controller.UnblockM 859 0.00% 0.00% +system.ruby.Directory_Controller.Writeback_Exclusive_Clean 71 0.00% 0.00% +system.ruby.Directory_Controller.Writeback_Exclusive_Dirty 782 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 861 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 782 0.00% 0.00% system.ruby.Directory_Controller.GETF 2 0.00% 0.00% system.ruby.Directory_Controller.PUTF 2 0.00% 0.00% -system.ruby.Directory_Controller.NO.PUT 867 0.00% 0.00% -system.ruby.Directory_Controller.E.GETX 785 0.00% 0.00% -system.ruby.Directory_Controller.E.GETS 89 0.00% 0.00% -system.ruby.Directory_Controller.E.GETF 2 0.00% 0.00% -system.ruby.Directory_Controller.NO_B.PUT 251 0.00% 0.00% -system.ruby.Directory_Controller.NO_B.UnblockM 871 0.00% 0.00% -system.ruby.Directory_Controller.NO_B_W.Memory_Data 872 0.00% 0.00% +system.ruby.Directory_Controller.NO.PUT 853 0.00% 0.00% +system.ruby.Directory_Controller.NO.GETF 1 0.00% 0.00% +system.ruby.Directory_Controller.E.GETX 778 0.00% 0.00% +system.ruby.Directory_Controller.E.GETS 83 0.00% 0.00% +system.ruby.Directory_Controller.E.GETF 1 0.00% 0.00% +system.ruby.Directory_Controller.NO_B.PUT 246 0.00% 0.00% +system.ruby.Directory_Controller.NO_B.UnblockM 859 0.00% 0.00% +system.ruby.Directory_Controller.NO_B_W.Memory_Data 860 0.00% 0.00% system.ruby.Directory_Controller.WB.GETS 1 0.00% 0.00% -system.ruby.Directory_Controller.WB.Writeback_Exclusive_Clean 77 0.00% 0.00% -system.ruby.Directory_Controller.WB.Writeback_Exclusive_Dirty 790 0.00% 0.00% -system.ruby.Directory_Controller.WB_E_W.Memory_Ack 790 0.00% 0.00% +system.ruby.Directory_Controller.WB.Writeback_Exclusive_Clean 71 0.00% 0.00% +system.ruby.Directory_Controller.WB.Writeback_Exclusive_Dirty 782 0.00% 0.00% +system.ruby.Directory_Controller.WB_E_W.Memory_Ack 782 0.00% 0.00% system.ruby.Directory_Controller.NO_F.PUTF 2 0.00% 0.00% -system.ruby.Directory_Controller.NO_F_W.Memory_Data 2 0.00% 0.00% -system.ruby.L1Cache_Controller.Load 44 0.00% 0.00% -system.ruby.L1Cache_Controller.Ifetch 59 0.00% 0.00% -system.ruby.L1Cache_Controller.Store 942 0.00% 0.00% -system.ruby.L1Cache_Controller.L2_Replacement 867 0.00% 0.00% -system.ruby.L1Cache_Controller.L1_to_L2 18224 0.00% 0.00% -system.ruby.L1Cache_Controller.Trigger_L2_to_L1D 34 0.00% 0.00% -system.ruby.L1Cache_Controller.Trigger_L2_to_L1I 5 0.00% 0.00% -system.ruby.L1Cache_Controller.Complete_L2_to_L1 39 0.00% 0.00% -system.ruby.L1Cache_Controller.Exclusive_Data 874 0.00% 0.00% -system.ruby.L1Cache_Controller.Writeback_Ack 869 0.00% 0.00% -system.ruby.L1Cache_Controller.All_acks_no_sharers 874 0.00% 0.00% +system.ruby.Directory_Controller.NO_F_W.Memory_Data 1 0.00% 0.00% +system.ruby.L1Cache_Controller.Load 39 0.00% 0.00% +system.ruby.L1Cache_Controller.Ifetch 64 0.00% 0.00% +system.ruby.L1Cache_Controller.Store 934 0.00% 0.00% +system.ruby.L1Cache_Controller.L2_Replacement 853 0.00% 0.00% +system.ruby.L1Cache_Controller.L1_to_L2 18403 0.00% 0.00% +system.ruby.L1Cache_Controller.Trigger_L2_to_L1D 44 0.00% 0.00% +system.ruby.L1Cache_Controller.Trigger_L2_to_L1I 11 0.00% 0.00% +system.ruby.L1Cache_Controller.Complete_L2_to_L1 55 0.00% 0.00% +system.ruby.L1Cache_Controller.Exclusive_Data 861 0.00% 0.00% +system.ruby.L1Cache_Controller.Writeback_Ack 855 0.00% 0.00% +system.ruby.L1Cache_Controller.All_acks_no_sharers 861 0.00% 0.00% system.ruby.L1Cache_Controller.Flush_line 2 0.00% 0.00% -system.ruby.L1Cache_Controller.I.Load 40 0.00% 0.00% -system.ruby.L1Cache_Controller.I.Ifetch 49 0.00% 0.00% -system.ruby.L1Cache_Controller.I.Store 785 0.00% 0.00% -system.ruby.L1Cache_Controller.I.Flush_line 2 0.00% 0.00% -system.ruby.L1Cache_Controller.M.Ifetch 2 0.00% 0.00% -system.ruby.L1Cache_Controller.M.Store 1 0.00% 0.00% -system.ruby.L1Cache_Controller.M.L2_Replacement 76 0.00% 0.00% -system.ruby.L1Cache_Controller.M.L1_to_L2 85 0.00% 0.00% -system.ruby.L1Cache_Controller.M.Trigger_L2_to_L1D 9 0.00% 0.00% +system.ruby.L1Cache_Controller.Block_Ack 1 0.00% 0.00% +system.ruby.L1Cache_Controller.I.Load 31 0.00% 0.00% +system.ruby.L1Cache_Controller.I.Ifetch 52 0.00% 0.00% +system.ruby.L1Cache_Controller.I.Store 778 0.00% 0.00% +system.ruby.L1Cache_Controller.I.Flush_line 1 0.00% 0.00% +system.ruby.L1Cache_Controller.M.L2_Replacement 71 0.00% 0.00% +system.ruby.L1Cache_Controller.M.L1_to_L2 81 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Trigger_L2_to_L1D 10 0.00% 0.00% system.ruby.L1Cache_Controller.MM.Load 4 0.00% 0.00% -system.ruby.L1Cache_Controller.MM.Ifetch 1 0.00% 0.00% -system.ruby.L1Cache_Controller.MM.Store 91 0.00% 0.00% -system.ruby.L1Cache_Controller.MM.L2_Replacement 791 0.00% 0.00% -system.ruby.L1Cache_Controller.MM.L1_to_L2 823 0.00% 0.00% -system.ruby.L1Cache_Controller.MM.Trigger_L2_to_L1D 25 0.00% 0.00% -system.ruby.L1Cache_Controller.MM.Trigger_L2_to_L1I 5 0.00% 0.00% -system.ruby.L1Cache_Controller.MR.Store 9 0.00% 0.00% -system.ruby.L1Cache_Controller.MR.L1_to_L2 116 0.00% 0.00% -system.ruby.L1Cache_Controller.MMR.Ifetch 5 0.00% 0.00% -system.ruby.L1Cache_Controller.MMR.Store 25 0.00% 0.00% -system.ruby.L1Cache_Controller.MMR.L1_to_L2 2 0.00% 0.00% -system.ruby.L1Cache_Controller.IM.L1_to_L2 10757 0.00% 0.00% -system.ruby.L1Cache_Controller.IM.Exclusive_Data 784 0.00% 0.00% -system.ruby.L1Cache_Controller.M_W.L1_to_L2 187 0.00% 0.00% -system.ruby.L1Cache_Controller.M_W.All_acks_no_sharers 88 0.00% 0.00% -system.ruby.L1Cache_Controller.MM_W.L1_to_L2 5531 0.00% 0.00% -system.ruby.L1Cache_Controller.MM_W.All_acks_no_sharers 784 0.00% 0.00% -system.ruby.L1Cache_Controller.IS.L1_to_L2 475 0.00% 0.00% -system.ruby.L1Cache_Controller.IS.Exclusive_Data 88 0.00% 0.00% +system.ruby.L1Cache_Controller.MM.Store 75 0.00% 0.00% +system.ruby.L1Cache_Controller.MM.L2_Replacement 782 0.00% 0.00% +system.ruby.L1Cache_Controller.MM.L1_to_L2 829 0.00% 0.00% +system.ruby.L1Cache_Controller.MM.Trigger_L2_to_L1D 34 0.00% 0.00% +system.ruby.L1Cache_Controller.MM.Trigger_L2_to_L1I 11 0.00% 0.00% +system.ruby.L1Cache_Controller.MR.Store 10 0.00% 0.00% +system.ruby.L1Cache_Controller.MR.L1_to_L2 114 0.00% 0.00% +system.ruby.L1Cache_Controller.MMR.Load 2 0.00% 0.00% +system.ruby.L1Cache_Controller.MMR.Ifetch 11 0.00% 0.00% +system.ruby.L1Cache_Controller.MMR.Store 31 0.00% 0.00% +system.ruby.L1Cache_Controller.MMR.L1_to_L2 14 0.00% 0.00% +system.ruby.L1Cache_Controller.MMR.Flush_line 1 0.00% 0.00% +system.ruby.L1Cache_Controller.IM.L1_to_L2 10904 0.00% 0.00% +system.ruby.L1Cache_Controller.IM.Exclusive_Data 777 0.00% 0.00% +system.ruby.L1Cache_Controller.M_W.L1_to_L2 223 0.00% 0.00% +system.ruby.L1Cache_Controller.M_W.All_acks_no_sharers 83 0.00% 0.00% +system.ruby.L1Cache_Controller.MM_W.L1_to_L2 5430 0.00% 0.00% +system.ruby.L1Cache_Controller.MM_W.All_acks_no_sharers 777 0.00% 0.00% +system.ruby.L1Cache_Controller.IS.L1_to_L2 455 0.00% 0.00% +system.ruby.L1Cache_Controller.IS.Exclusive_Data 83 0.00% 0.00% system.ruby.L1Cache_Controller.MI.Ifetch 1 0.00% 0.00% -system.ruby.L1Cache_Controller.MI.Writeback_Ack 867 0.00% 0.00% +system.ruby.L1Cache_Controller.MI.Store 1 0.00% 0.00% +system.ruby.L1Cache_Controller.MI.Writeback_Ack 853 0.00% 0.00% system.ruby.L1Cache_Controller.MT.Store 9 0.00% 0.00% -system.ruby.L1Cache_Controller.MT.L1_to_L2 118 0.00% 0.00% -system.ruby.L1Cache_Controller.MT.Complete_L2_to_L1 9 0.00% 0.00% -system.ruby.L1Cache_Controller.MMT.Ifetch 1 0.00% 0.00% -system.ruby.L1Cache_Controller.MMT.Store 22 0.00% 0.00% -system.ruby.L1Cache_Controller.MMT.L1_to_L2 130 0.00% 0.00% -system.ruby.L1Cache_Controller.MMT.Complete_L2_to_L1 30 0.00% 0.00% +system.ruby.L1Cache_Controller.MT.L1_to_L2 130 0.00% 0.00% +system.ruby.L1Cache_Controller.MT.Complete_L2_to_L1 10 0.00% 0.00% +system.ruby.L1Cache_Controller.MMT.Load 2 0.00% 0.00% +system.ruby.L1Cache_Controller.MMT.Store 30 0.00% 0.00% +system.ruby.L1Cache_Controller.MMT.L1_to_L2 223 0.00% 0.00% +system.ruby.L1Cache_Controller.MMT.Complete_L2_to_L1 45 0.00% 0.00% system.ruby.L1Cache_Controller.MI_F.Writeback_Ack 2 0.00% 0.00% -system.ruby.L1Cache_Controller.IM_F.Exclusive_Data 2 0.00% 0.00% -system.ruby.L1Cache_Controller.MM_WF.All_acks_no_sharers 2 0.00% 0.00% +system.ruby.L1Cache_Controller.MM_F.Block_Ack 1 0.00% 0.00% +system.ruby.L1Cache_Controller.IM_F.Exclusive_Data 1 0.00% 0.00% +system.ruby.L1Cache_Controller.MM_WF.All_acks_no_sharers 1 0.00% 0.00% ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/config.ini b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/config.ini index ffe5cd6c7..9f41aca8f 100644 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/config.ini +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/config.ini @@ -14,6 +14,7 @@ children=clk_domain cpu dvfs_handler mem_ctrls ruby sys_port_proxy voltage_domai boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 exit_on_work_items=false init_param=0 @@ -22,11 +23,15 @@ kernel_addr_check=true load_addr_mask=1099511627775 load_offset=0 mem_mode=timing -mem_ranges=0:268435455 +mem_ranges=0:268435455:0:0:0:0 memories=system.mem_ctrls mmap_using_noreserve=false multi_thread=false num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null readfile= symbolfile= thermal_components= @@ -54,8 +59,13 @@ check_flush=false checks_to_complete=100 clk_domain=system.clk_domain deadlock_threshold=50000 +default_p_state=UNDEFINED eventq_index=0 num_cpus=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null system=system wakeup_frequency=10 cpuInstDataPort=system.ruby.l1_cntrl0.sequencer.slave[0] @@ -70,27 +80,27 @@ transition_latency=100000 [system.mem_ctrls] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -102,6 +112,7 @@ burst_length=8 channels=1 clk_domain=system.clk_domain conf_table_reported=true +default_p_state=UNDEFINED device_bus_width=8 device_rowbuffer_size=1024 device_size=536870912 @@ -109,12 +120,17 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 page_policy=open_adaptive -range=0:268435455 +power_model=Null +range=0:268435455:5:19:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10 @@ -136,9 +152,9 @@ tRTW=3 tWR=15 tWTR=8 tXAW=30 -tXP=0 +tXP=6 tXPDLL=0 -tXS=0 +tXS=270 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 @@ -152,12 +168,17 @@ access_backing_store=false all_instructions=false block_size_bytes=64 clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED eventq_index=0 hot_lines=false memory_size_bits=48 num_of_sequencers=1 number_of_virtual_networks=5 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 phys_mem=Null +power_model=Null randomization=true [system.ruby.clk_domain] @@ -174,6 +195,7 @@ children=directory dmaRequestToDir dmaResponseFromDir forwardFromDir requestToDi buffer_size=0 clk_domain=system.ruby.clk_domain cluster_id=0 +default_p_state=UNDEFINED directory=system.ruby.dir_cntrl0.directory directory_latency=12 dmaRequestToDir=system.ruby.dir_cntrl0.dmaRequestToDir @@ -181,6 +203,10 @@ dmaResponseFromDir=system.ruby.dir_cntrl0.dmaResponseFromDir eventq_index=0 forwardFromDir=system.ruby.dir_cntrl0.forwardFromDir number_of_TBEs=256 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null recycle_latency=10 requestToDir=system.ruby.dir_cntrl0.requestToDir responseFromDir=system.ruby.dir_cntrl0.responseFromDir @@ -254,11 +280,16 @@ cacheMemory=system.ruby.l1_cntrl0.cacheMemory cache_response_latency=12 clk_domain=system.ruby.clk_domain cluster_id=0 +default_p_state=UNDEFINED eventq_index=0 forwardToCache=system.ruby.l1_cntrl0.forwardToCache issue_latency=2 mandatoryQueue=system.ruby.l1_cntrl0.mandatoryQueue number_of_TBEs=256 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null recycle_latency=10 requestFromCache=system.ruby.l1_cntrl0.requestFromCache responseFromCache=system.ruby.l1_cntrl0.responseFromCache @@ -340,17 +371,22 @@ coreid=99 dcache=system.ruby.l1_cntrl0.cacheMemory dcache_hit_latency=1 deadlock_threshold=500000 +default_p_state=UNDEFINED eventq_index=0 +garnet_standalone=false icache=system.ruby.l1_cntrl0.cacheMemory icache_hit_latency=1 is_cpu_sequencer=true max_outstanding_requests=16 no_retry_on_stall=true +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null ruby_system=system.ruby support_data_reqs=true support_inst_reqs=true system=system -using_network_tester=false using_ruby_tester=true version=0 slave=system.cpu.cpuInstDataPort[0] @@ -363,18 +399,23 @@ eventq_index=0 [system.ruby.network] type=SimpleNetwork -children=ext_links0 ext_links1 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_links0 int_links1 routers0 routers1 routers2 +children=ext_links0 ext_links1 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_link_buffers20 int_link_buffers21 int_link_buffers22 int_link_buffers23 int_link_buffers24 int_link_buffers25 int_link_buffers26 int_link_buffers27 int_link_buffers28 int_link_buffers29 int_link_buffers30 int_link_buffers31 int_link_buffers32 int_link_buffers33 int_link_buffers34 int_link_buffers35 int_link_buffers36 int_link_buffers37 int_link_buffers38 int_link_buffers39 int_links0 int_links1 int_links2 int_links3 routers0 routers1 routers2 adaptive_routing=false buffer_size=0 clk_domain=system.ruby.clk_domain control_msg_size=8 +default_p_state=UNDEFINED endpoint_bandwidth=1000 eventq_index=0 ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1 -int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19 -int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 +int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19 system.ruby.network.int_link_buffers20 system.ruby.network.int_link_buffers21 system.ruby.network.int_link_buffers22 system.ruby.network.int_link_buffers23 system.ruby.network.int_link_buffers24 system.ruby.network.int_link_buffers25 system.ruby.network.int_link_buffers26 system.ruby.network.int_link_buffers27 system.ruby.network.int_link_buffers28 system.ruby.network.int_link_buffers29 system.ruby.network.int_link_buffers30 system.ruby.network.int_link_buffers31 system.ruby.network.int_link_buffers32 system.ruby.network.int_link_buffers33 system.ruby.network.int_link_buffers34 system.ruby.network.int_link_buffers35 system.ruby.network.int_link_buffers36 system.ruby.network.int_link_buffers37 system.ruby.network.int_link_buffers38 system.ruby.network.int_link_buffers39 +int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2 system.ruby.network.int_links3 netifs= number_of_virtual_networks=5 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null routers=system.ruby.network.routers0 system.ruby.network.routers1 system.ruby.network.routers2 ruby_system=system.ruby topology=Crossbar @@ -541,32 +582,206 @@ eventq_index=0 ordered=true randomization=false +[system.ruby.network.int_link_buffers20] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers21] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers22] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers23] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers24] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers25] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers26] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers27] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers28] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers29] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers30] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers31] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers32] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers33] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers34] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers35] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers36] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers37] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers38] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers39] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + [system.ruby.network.int_links0] type=SimpleIntLink bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers2 eventq_index=0 latency=1 link_id=2 -node_a=system.ruby.network.routers0 -node_b=system.ruby.network.routers2 +src_node=system.ruby.network.routers0 +src_outport= weight=1 [system.ruby.network.int_links1] type=SimpleIntLink bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers2 eventq_index=0 latency=1 link_id=3 -node_a=system.ruby.network.routers1 -node_b=system.ruby.network.routers2 +src_node=system.ruby.network.routers1 +src_outport= +weight=1 + +[system.ruby.network.int_links2] +type=SimpleIntLink +bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers0 +eventq_index=0 +latency=1 +link_id=4 +src_node=system.ruby.network.routers2 +src_outport= +weight=1 + +[system.ruby.network.int_links3] +type=SimpleIntLink +bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers1 +eventq_index=0 +latency=1 +link_id=5 +src_node=system.ruby.network.routers2 +src_outport= weight=1 [system.ruby.network.routers0] type=Switch children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED eventq_index=0 +latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 port_buffers=system.ruby.network.routers0.port_buffers00 system.ruby.network.routers0.port_buffers01 system.ruby.network.routers0.port_buffers02 system.ruby.network.routers0.port_buffers03 system.ruby.network.routers0.port_buffers04 system.ruby.network.routers0.port_buffers05 system.ruby.network.routers0.port_buffers06 system.ruby.network.routers0.port_buffers07 system.ruby.network.routers0.port_buffers08 system.ruby.network.routers0.port_buffers09 system.ruby.network.routers0.port_buffers10 system.ruby.network.routers0.port_buffers11 system.ruby.network.routers0.port_buffers12 system.ruby.network.routers0.port_buffers13 system.ruby.network.routers0.port_buffers14 +power_model=Null router_id=0 virt_nets=5 @@ -679,8 +894,14 @@ randomization=false type=Switch children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED eventq_index=0 +latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 port_buffers=system.ruby.network.routers1.port_buffers00 system.ruby.network.routers1.port_buffers01 system.ruby.network.routers1.port_buffers02 system.ruby.network.routers1.port_buffers03 system.ruby.network.routers1.port_buffers04 system.ruby.network.routers1.port_buffers05 system.ruby.network.routers1.port_buffers06 system.ruby.network.routers1.port_buffers07 system.ruby.network.routers1.port_buffers08 system.ruby.network.routers1.port_buffers09 system.ruby.network.routers1.port_buffers10 system.ruby.network.routers1.port_buffers11 system.ruby.network.routers1.port_buffers12 system.ruby.network.routers1.port_buffers13 system.ruby.network.routers1.port_buffers14 +power_model=Null router_id=1 virt_nets=5 @@ -793,8 +1014,14 @@ randomization=false type=Switch children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17 port_buffers18 port_buffers19 clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED eventq_index=0 +latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 port_buffers=system.ruby.network.routers2.port_buffers00 system.ruby.network.routers2.port_buffers01 system.ruby.network.routers2.port_buffers02 system.ruby.network.routers2.port_buffers03 system.ruby.network.routers2.port_buffers04 system.ruby.network.routers2.port_buffers05 system.ruby.network.routers2.port_buffers06 system.ruby.network.routers2.port_buffers07 system.ruby.network.routers2.port_buffers08 system.ruby.network.routers2.port_buffers09 system.ruby.network.routers2.port_buffers10 system.ruby.network.routers2.port_buffers11 system.ruby.network.routers2.port_buffers12 system.ruby.network.routers2.port_buffers13 system.ruby.network.routers2.port_buffers14 system.ruby.network.routers2.port_buffers15 system.ruby.network.routers2.port_buffers16 system.ruby.network.routers2.port_buffers17 system.ruby.network.routers2.port_buffers18 system.ruby.network.routers2.port_buffers19 +power_model=Null router_id=2 virt_nets=5 @@ -941,9 +1168,14 @@ randomization=false [system.sys_port_proxy] type=RubyPortProxy clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 is_cpu_sequencer=true no_retry_on_stall=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null ruby_system=system.ruby support_data_reqs=true support_inst_reqs=true diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simerr b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simerr index c2086c0ba..cee0dfc57 100755 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simerr +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simerr @@ -4,7 +4,5 @@ warn: rounding error > tolerance 1.250000 rounded to 1 warn: rounding error > tolerance 1.250000 rounded to 1 -warn: rounding error > tolerance - 1.250000 rounded to 1 warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes) warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files! diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simout b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simout index e720ac2ac..cd24395f8 100755 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simout +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simout @@ -1,11 +1,13 @@ +Redirecting stdout to build/ALPHA/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby/simout +Redirecting stderr to build/ALPHA/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 21 2016 13:49:21 -gem5 started Jan 21 2016 13:50:27 -gem5 executing on zizzer, pid 34085 -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ALPHA/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby +gem5 compiled Oct 11 2016 00:00:58 +gem5 started Oct 13 2016 20:19:45 +gem5 executing on e108600-lin, pid 28072 +command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/60.rubytest/alpha/linux/rubytest-ruby Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 37741 because Ruby Tester completed +Exiting @ tick 39431 because Ruby Tester completed diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt index 4e47c8bcd..0fabd5bae 100644 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt @@ -1,45 +1,45 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000038 # Number of seconds simulated -sim_ticks 37741 # Number of ticks simulated -final_tick 37741 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000039 # Number of seconds simulated +sim_ticks 39431 # Number of ticks simulated +final_tick 39431 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 891959 # Simulator tick rate (ticks/s) -host_mem_usage 449872 # Number of bytes of host memory used +host_tick_rate 979592 # Simulator tick rate (ticks/s) +host_mem_usage 407616 # Number of bytes of host memory used host_seconds 0.04 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks -system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 37741 # Cumulative time (in ticks) in various power states -system.mem_ctrls.bytes_read::ruby.dir_cntrl0 60992 # Number of bytes read from this memory -system.mem_ctrls.bytes_read::total 60992 # Number of bytes read from this memory -system.mem_ctrls.bytes_written::ruby.dir_cntrl0 60800 # Number of bytes written to this memory -system.mem_ctrls.bytes_written::total 60800 # Number of bytes written to this memory -system.mem_ctrls.num_reads::ruby.dir_cntrl0 953 # Number of read requests responded to by this memory -system.mem_ctrls.num_reads::total 953 # Number of read requests responded to by this memory -system.mem_ctrls.num_writes::ruby.dir_cntrl0 950 # Number of write requests responded to by this memory -system.mem_ctrls.num_writes::total 950 # Number of write requests responded to by this memory -system.mem_ctrls.bw_read::ruby.dir_cntrl0 1616067407 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_read::total 1616067407 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::ruby.dir_cntrl0 1610980101 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::total 1610980101 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_total::ruby.dir_cntrl0 3227047508 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.bw_total::total 3227047508 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.readReqs 953 # Number of read requests accepted -system.mem_ctrls.writeReqs 950 # Number of write requests accepted -system.mem_ctrls.readBursts 953 # Number of DRAM read bursts, including those serviced by the write queue -system.mem_ctrls.writeBursts 950 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrls.bytesReadDRAM 52800 # Total number of bytes read from DRAM -system.mem_ctrls.bytesReadWrQ 8192 # Total number of bytes read from write queue -system.mem_ctrls.bytesWritten 51456 # Total number of bytes written to DRAM -system.mem_ctrls.bytesReadSys 60992 # Total read bytes from the system interface side -system.mem_ctrls.bytesWrittenSys 60800 # Total written bytes from the system interface side -system.mem_ctrls.servicedByWrQ 128 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrls.mergedWrBursts 117 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 39431 # Cumulative time (in ticks) in various power states +system.mem_ctrls.bytes_read::ruby.dir_cntrl0 60224 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 60224 # Number of bytes read from this memory +system.mem_ctrls.bytes_written::ruby.dir_cntrl0 60032 # Number of bytes written to this memory +system.mem_ctrls.bytes_written::total 60032 # Number of bytes written to this memory +system.mem_ctrls.num_reads::ruby.dir_cntrl0 941 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 941 # Number of read requests responded to by this memory +system.mem_ctrls.num_writes::ruby.dir_cntrl0 938 # Number of write requests responded to by this memory +system.mem_ctrls.num_writes::total 938 # Number of write requests responded to by this memory +system.mem_ctrls.bw_read::ruby.dir_cntrl0 1527326215 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 1527326215 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::ruby.dir_cntrl0 1522456950 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::total 1522456950 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::ruby.dir_cntrl0 3049783166 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 3049783166 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.readReqs 941 # Number of read requests accepted +system.mem_ctrls.writeReqs 938 # Number of write requests accepted +system.mem_ctrls.readBursts 941 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 938 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.bytesReadDRAM 50560 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 9664 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 49728 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 60224 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 60032 # Total written bytes from the system interface side +system.mem_ctrls.servicedByWrQ 151 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 134 # Number of DRAM write bursts merged with an existing one system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.mem_ctrls.perBankRdBursts::0 259 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::1 251 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::2 261 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::3 54 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 247 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 238 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 46 # Per bank write bursts system.mem_ctrls.perBankRdBursts::4 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::5 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::6 0 # Per bank write bursts @@ -52,10 +52,10 @@ system.mem_ctrls.perBankRdBursts::12 0 # Pe system.mem_ctrls.perBankRdBursts::13 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::14 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::15 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::0 255 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::1 246 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::2 250 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::3 53 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 258 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 243 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 232 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 44 # Per bank write bursts system.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts @@ -70,23 +70,23 @@ system.mem_ctrls.perBankWrBursts::14 0 # Pe system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrls.totGap 37680 # Total gap between requests +system.mem_ctrls.totGap 39357 # Total gap between requests system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::6 953 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 941 # Read request sizes (log2) system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::6 950 # Write request sizes (log2) -system.mem_ctrls.rdQLenPdf::0 469 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::1 355 # What read queue length does an incoming req see +system.mem_ctrls.writePktSize::6 938 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 461 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 328 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::2 1 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -133,24 +133,24 @@ system.mem_ctrls.wrQLenPdf::12 1 # Wh system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::15 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::16 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::17 33 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::18 51 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::19 51 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::20 51 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::21 53 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::22 51 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::23 51 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::24 51 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::25 51 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::26 70 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::27 51 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::28 51 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::29 50 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::30 50 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::31 50 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::32 50 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::33 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 2 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 36 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 47 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 48 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 49 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 49 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 52 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 49 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::24 49 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 49 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 51 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 67 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::28 48 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 48 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 48 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 48 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::32 48 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see @@ -181,340 +181,359 @@ system.mem_ctrls.wrQLenPdf::60 0 # Wh system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrls.bytesPerActivate::samples 107 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::mean 956.411215 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::gmean 902.763557 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::stdev 202.735209 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::0-127 1 0.93% 0.93% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::128-255 3 2.80% 3.74% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::256-383 1 0.93% 4.67% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::512-639 2 1.87% 6.54% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::640-767 4 3.74% 10.28% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::768-895 2 1.87% 12.15% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::896-1023 1 0.93% 13.08% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::1024-1151 93 86.92% 100.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::total 107 # Bytes accessed per row activation -system.mem_ctrls.rdPerTurnAround::samples 50 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::mean 16.240000 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::gmean 16.100110 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::stdev 2.766859 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::14-15 11 22.00% 22.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::16-17 37 74.00% 96.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::18-19 1 2.00% 98.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::34-35 1 2.00% 100.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::total 50 # Reads before turning the bus around for writes -system.mem_ctrls.wrPerTurnAround::samples 50 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::mean 16.080000 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::gmean 16.077788 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::stdev 0.274048 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::16 46 92.00% 92.00% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::17 4 8.00% 100.00% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::total 50 # Writes before turning the bus around for reads -system.mem_ctrls.totQLat 10350 # Total ticks spent queuing -system.mem_ctrls.totMemAccLat 26025 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrls.totBusLat 4125 # Total ticks spent in databus transfers -system.mem_ctrls.avgQLat 12.55 # Average queueing delay per DRAM burst +system.mem_ctrls.bytesPerActivate::samples 108 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 925.629630 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 827.187599 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 260.509945 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 4 3.70% 3.70% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 3 2.78% 6.48% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 2 1.85% 8.33% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 2 1.85% 10.19% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 1 0.93% 11.11% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 1 0.93% 12.04% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 1 0.93% 12.96% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 3 2.78% 15.74% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 91 84.26% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 108 # Bytes accessed per row activation +system.mem_ctrls.rdPerTurnAround::samples 48 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::mean 16.229167 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::gmean 16.080832 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::stdev 2.837736 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::14-15 10 20.83% 20.83% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::16-17 37 77.08% 97.92% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::34-35 1 2.08% 100.00% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::total 48 # Reads before turning the bus around for writes +system.mem_ctrls.wrPerTurnAround::samples 48 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::mean 16.187500 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::gmean 16.181743 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::stdev 0.445127 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::16 40 83.33% 83.33% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::17 7 14.58% 97.92% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::18 1 2.08% 100.00% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::total 48 # Writes before turning the bus around for reads +system.mem_ctrls.totQLat 14435 # Total ticks spent queuing +system.mem_ctrls.totMemAccLat 29445 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.totBusLat 3950 # Total ticks spent in databus transfers +system.mem_ctrls.avgQLat 18.27 # Average queueing delay per DRAM burst system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst -system.mem_ctrls.avgMemAccLat 31.55 # Average memory access latency per DRAM burst -system.mem_ctrls.avgRdBW 1399.01 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrls.avgWrBW 1363.40 # Average achieved write bandwidth in MiByte/s -system.mem_ctrls.avgRdBWSys 1616.07 # Average system read bandwidth in MiByte/s -system.mem_ctrls.avgWrBWSys 1610.98 # Average system write bandwidth in MiByte/s +system.mem_ctrls.avgMemAccLat 37.27 # Average memory access latency per DRAM burst +system.mem_ctrls.avgRdBW 1282.24 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 1261.14 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 1527.33 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 1522.46 # Average system write bandwidth in MiByte/s system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrls.busUtil 21.58 # Data bus utilization in percentage -system.mem_ctrls.busUtilRead 10.93 # Data bus utilization in percentage for reads -system.mem_ctrls.busUtilWrite 10.65 # Data bus utilization in percentage for writes -system.mem_ctrls.avgRdQLen 1.73 # Average read queue length when enqueuing -system.mem_ctrls.avgWrQLen 26.18 # Average write queue length when enqueuing -system.mem_ctrls.readRowHits 719 # Number of row buffer hits during reads -system.mem_ctrls.writeRowHits 799 # Number of row buffer hits during writes -system.mem_ctrls.readRowHitRate 87.15 # Row buffer hit rate for reads -system.mem_ctrls.writeRowHitRate 95.92 # Row buffer hit rate for writes -system.mem_ctrls.avgGap 19.80 # Average gap between requests -system.mem_ctrls.pageHitRate 91.56 # Row buffer hit rate, read and write combined -system.mem_ctrls_0.actEnergy 687960 # Energy for activate commands per rank (pJ) -system.mem_ctrls_0.preEnergy 382200 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_0.readEnergy 8548800 # Energy for read commands per rank (pJ) -system.mem_ctrls_0.writeEnergy 6822144 # Energy for write commands per rank (pJ) -system.mem_ctrls_0.refreshEnergy 2034240 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_0.actBackEnergy 21405780 # Energy for active background per rank (pJ) -system.mem_ctrls_0.preBackEnergy 65400 # Energy for precharge background per rank (pJ) -system.mem_ctrls_0.totalEnergy 39946524 # Total energy per rank (pJ) -system.mem_ctrls_0.averagePower 1272.020252 # Core power per rank (mW) -system.mem_ctrls_0.memoryStateTime::IDLE 11 # Time in different power states -system.mem_ctrls_0.memoryStateTime::REF 1040 # Time in different power states -system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT 30367 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls.busUtil 19.87 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 10.02 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 9.85 # Data bus utilization in percentage for writes +system.mem_ctrls.avgRdQLen 1.68 # Average read queue length when enqueuing +system.mem_ctrls.avgWrQLen 25.86 # Average write queue length when enqueuing +system.mem_ctrls.readRowHits 690 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 766 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 87.34 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate 95.27 # Row buffer hit rate for writes +system.mem_ctrls.avgGap 20.95 # Average gap between requests +system.mem_ctrls.pageHitRate 91.34 # Row buffer hit rate, read and write combined +system.mem_ctrls_0.actEnergy 792540 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 417312 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 9024960 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 6489504 # Energy for write commands per rank (pJ) +system.mem_ctrls_0.refreshEnergy 3073200.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 9767064 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 64896 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.actPowerDownEnergy 8135040 # Energy for active power-down per rank (pJ) +system.mem_ctrls_0.prePowerDownEnergy 1152 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls_0.totalEnergy 37765668 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 957.765920 # Core power per rank (mW) +system.mem_ctrls_0.totalIdleTime 17819 # Total Idle time Per DRAM Rank +system.mem_ctrls_0.memoryStateTime::IDLE 29 # Time in different power states +system.mem_ctrls_0.memoryStateTime::REF 1300 # Time in different power states +system.mem_ctrls_0.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls_0.memoryStateTime::PRE_PDN 3 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 20259 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT_PDN 17840 # Time in different power states system.mem_ctrls_1.actEnergy 0 # Energy for activate commands per rank (pJ) system.mem_ctrls_1.preEnergy 0 # Energy for precharge commands per rank (pJ) system.mem_ctrls_1.readEnergy 0 # Energy for read commands per rank (pJ) system.mem_ctrls_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.mem_ctrls_1.refreshEnergy 2034240 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_1.actBackEnergy 673056 # Energy for active background per rank (pJ) -system.mem_ctrls_1.preBackEnergy 18243600 # Energy for precharge background per rank (pJ) -system.mem_ctrls_1.totalEnergy 20950896 # Total energy per rank (pJ) -system.mem_ctrls_1.averagePower 667.438547 # Core power per rank (mW) -system.mem_ctrls_1.memoryStateTime::IDLE 30364 # Time in different power states -system.mem_ctrls_1.memoryStateTime::REF 1040 # Time in different power states -system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_1.refreshEnergy 1229280.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 224352 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 3002880 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls_1.prePowerDownEnergy 2889984 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls_1.selfRefreshEnergy 5662320 # Energy for self refresh per rank (pJ) +system.mem_ctrls_1.totalEnergy 13008816 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 329.913418 # Core power per rank (mW) +system.mem_ctrls_1.totalIdleTime 7526 # Total Idle time Per DRAM Rank +system.mem_ctrls_1.memoryStateTime::IDLE 7786 # Time in different power states +system.mem_ctrls_1.memoryStateTime::REF 526 # Time in different power states +system.mem_ctrls_1.memoryStateTime::SREF 23593 # Time in different power states +system.mem_ctrls_1.memoryStateTime::PRE_PDN 7526 # Time in different power states system.mem_ctrls_1.memoryStateTime::ACT 0 # Time in different power states system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 37741 # Cumulative time (in ticks) in various power states -system.cpu.pwrStateResidencyTicks::UNDEFINED 37741 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 39431 # Cumulative time (in ticks) in various power states +system.cpu.pwrStateResidencyTicks::UNDEFINED 39431 # Cumulative time (in ticks) in various power states system.ruby.clk_domain.clock 1 # Clock period in ticks -system.ruby.pwrStateResidencyTicks::UNDEFINED 37741 # Cumulative time (in ticks) in various power states +system.ruby.pwrStateResidencyTicks::UNDEFINED 39431 # Cumulative time (in ticks) in various power states system.ruby.delayHist::bucket_size 1 # delay histogram for all message system.ruby.delayHist::max_bucket 9 # delay histogram for all message -system.ruby.delayHist::samples 1903 # delay histogram for all message -system.ruby.delayHist::mean 0.196532 # delay histogram for all message -system.ruby.delayHist::stdev 1.062331 # delay histogram for all message -system.ruby.delayHist | 1839 96.64% 96.64% | 0 0.00% 96.64% | 2 0.11% 96.74% | 0 0.00% 96.74% | 1 0.05% 96.79% | 0 0.00% 96.79% | 61 3.21% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message -system.ruby.delayHist::total 1903 # delay histogram for all message +system.ruby.delayHist::samples 1878 # delay histogram for all message +system.ruby.delayHist::mean 0.221512 # delay histogram for all message +system.ruby.delayHist::stdev 1.129790 # delay histogram for all message +system.ruby.delayHist | 1808 96.27% 96.27% | 0 0.00% 96.27% | 1 0.05% 96.33% | 0 0.00% 96.33% | 0 0.00% 96.33% | 0 0.00% 96.33% | 69 3.67% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message +system.ruby.delayHist::total 1878 # delay histogram for all message system.ruby.outstanding_req_hist_seqr::bucket_size 2 system.ruby.outstanding_req_hist_seqr::max_bucket 19 -system.ruby.outstanding_req_hist_seqr::samples 1005 -system.ruby.outstanding_req_hist_seqr::mean 15.609950 -system.ruby.outstanding_req_hist_seqr::gmean 15.502410 -system.ruby.outstanding_req_hist_seqr::stdev 1.236521 -system.ruby.outstanding_req_hist_seqr | 1 0.10% 0.10% | 2 0.20% 0.30% | 2 0.20% 0.50% | 2 0.20% 0.70% | 4 0.40% 1.09% | 3 0.30% 1.39% | 4 0.40% 1.79% | 233 23.18% 24.98% | 754 75.02% 100.00% | 0 0.00% 100.00% -system.ruby.outstanding_req_hist_seqr::total 1005 +system.ruby.outstanding_req_hist_seqr::samples 997 +system.ruby.outstanding_req_hist_seqr::mean 15.607823 +system.ruby.outstanding_req_hist_seqr::gmean 15.499600 +system.ruby.outstanding_req_hist_seqr::stdev 1.240894 +system.ruby.outstanding_req_hist_seqr | 1 0.10% 0.10% | 2 0.20% 0.30% | 2 0.20% 0.50% | 2 0.20% 0.70% | 4 0.40% 1.10% | 2 0.20% 1.30% | 4 0.40% 1.71% | 227 22.77% 24.47% | 753 75.53% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist_seqr::total 997 system.ruby.latency_hist_seqr::bucket_size 128 system.ruby.latency_hist_seqr::max_bucket 1279 -system.ruby.latency_hist_seqr::samples 992 -system.ruby.latency_hist_seqr::mean 594.351815 -system.ruby.latency_hist_seqr::gmean 584.578373 -system.ruby.latency_hist_seqr::stdev 96.099439 -system.ruby.latency_hist_seqr | 2 0.20% 0.20% | 9 0.91% 1.11% | 6 0.60% 1.71% | 111 11.19% 12.90% | 654 65.93% 78.83% | 154 15.52% 94.35% | 49 4.94% 99.29% | 7 0.71% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.latency_hist_seqr::total 992 +system.ruby.latency_hist_seqr::samples 982 +system.ruby.latency_hist_seqr::mean 622.683299 +system.ruby.latency_hist_seqr::gmean 611.609969 +system.ruby.latency_hist_seqr::stdev 106.877832 +system.ruby.latency_hist_seqr | 2 0.20% 0.20% | 7 0.71% 0.92% | 6 0.61% 1.53% | 88 8.96% 10.49% | 458 46.64% 57.13% | 355 36.15% 93.28% | 33 3.36% 96.64% | 33 3.36% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.latency_hist_seqr::total 982 system.ruby.hit_latency_hist_seqr::bucket_size 128 system.ruby.hit_latency_hist_seqr::max_bucket 1279 -system.ruby.hit_latency_hist_seqr::samples 39 -system.ruby.hit_latency_hist_seqr::mean 492.692308 -system.ruby.hit_latency_hist_seqr::gmean 488.844837 -system.ruby.hit_latency_hist_seqr::stdev 62.931522 -system.ruby.hit_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 2.56% 2.56% | 22 56.41% 58.97% | 15 38.46% 97.44% | 1 2.56% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.hit_latency_hist_seqr::total 39 +system.ruby.hit_latency_hist_seqr::samples 42 +system.ruby.hit_latency_hist_seqr::mean 524.214286 +system.ruby.hit_latency_hist_seqr::gmean 519.360085 +system.ruby.hit_latency_hist_seqr::stdev 71.299963 +system.ruby.hit_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 17 40.48% 40.48% | 24 57.14% 97.62% | 1 2.38% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.hit_latency_hist_seqr::total 42 system.ruby.miss_latency_hist_seqr::bucket_size 128 system.ruby.miss_latency_hist_seqr::max_bucket 1279 -system.ruby.miss_latency_hist_seqr::samples 953 -system.ruby.miss_latency_hist_seqr::mean 598.512067 -system.ruby.miss_latency_hist_seqr::gmean 588.872583 -system.ruby.miss_latency_hist_seqr::stdev 94.945507 -system.ruby.miss_latency_hist_seqr | 2 0.21% 0.21% | 9 0.94% 1.15% | 5 0.52% 1.68% | 89 9.34% 11.02% | 639 67.05% 78.07% | 153 16.05% 94.12% | 49 5.14% 99.27% | 7 0.73% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.miss_latency_hist_seqr::total 953 -system.ruby.Directory.incomplete_times_seqr 953 -system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 37741 # Cumulative time (in ticks) in various power states -system.ruby.l1_cntrl0.cacheMemory.demand_hits 39 # Number of cache demand hits -system.ruby.l1_cntrl0.cacheMemory.demand_misses 955 # Number of cache demand misses -system.ruby.l1_cntrl0.cacheMemory.demand_accesses 994 # Number of cache demand accesses -system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 37741 # Cumulative time (in ticks) in various power states -system.ruby.l1_cntrl0.sequencer.store_waiting_on_load 7 # Number of times a store aliased with a pending load -system.ruby.l1_cntrl0.sequencer.store_waiting_on_store 129 # Number of times a store aliased with a pending store -system.ruby.l1_cntrl0.sequencer.load_waiting_on_store 6 # Number of times a load aliased with a pending store -system.ruby.l1_cntrl0.sequencer.load_waiting_on_load 1 # Number of times a load aliased with a pending load -system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 37741 # Cumulative time (in ticks) in various power states +system.ruby.miss_latency_hist_seqr::samples 940 +system.ruby.miss_latency_hist_seqr::mean 627.082979 +system.ruby.miss_latency_hist_seqr::gmean 616.094261 +system.ruby.miss_latency_hist_seqr::stdev 106.107284 +system.ruby.miss_latency_hist_seqr | 2 0.21% 0.21% | 7 0.74% 0.96% | 6 0.64% 1.60% | 71 7.55% 9.15% | 434 46.17% 55.32% | 354 37.66% 92.98% | 33 3.51% 96.49% | 33 3.51% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.miss_latency_hist_seqr::total 940 +system.ruby.Directory.incomplete_times_seqr 940 +system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 39431 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl0.cacheMemory.demand_hits 42 # Number of cache demand hits +system.ruby.l1_cntrl0.cacheMemory.demand_misses 941 # Number of cache demand misses +system.ruby.l1_cntrl0.cacheMemory.demand_accesses 983 # Number of cache demand accesses +system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 39431 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl0.sequencer.store_waiting_on_load 14 # Number of times a store aliased with a pending load +system.ruby.l1_cntrl0.sequencer.store_waiting_on_store 141 # Number of times a store aliased with a pending store +system.ruby.l1_cntrl0.sequencer.load_waiting_on_store 15 # Number of times a load aliased with a pending store +system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 39431 # Cumulative time (in ticks) in various power states system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 37741 # Cumulative time (in ticks) in various power states -system.ruby.network.routers0.percent_links_utilized 12.606979 -system.ruby.network.routers0.msg_count.Control::2 953 -system.ruby.network.routers0.msg_count.Data::2 951 -system.ruby.network.routers0.msg_count.Response_Data::4 953 -system.ruby.network.routers0.msg_count.Writeback_Control::3 950 -system.ruby.network.routers0.msg_bytes.Control::2 7624 -system.ruby.network.routers0.msg_bytes.Data::2 68472 -system.ruby.network.routers0.msg_bytes.Response_Data::4 68616 -system.ruby.network.routers0.msg_bytes.Writeback_Control::3 7600 -system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 37741 # Cumulative time (in ticks) in various power states -system.ruby.network.routers1.percent_links_utilized 12.605654 -system.ruby.network.routers1.msg_count.Control::2 953 -system.ruby.network.routers1.msg_count.Data::2 950 -system.ruby.network.routers1.msg_count.Response_Data::4 953 -system.ruby.network.routers1.msg_count.Writeback_Control::3 950 -system.ruby.network.routers1.msg_bytes.Control::2 7624 -system.ruby.network.routers1.msg_bytes.Data::2 68400 -system.ruby.network.routers1.msg_bytes.Response_Data::4 68616 -system.ruby.network.routers1.msg_bytes.Writeback_Control::3 7600 -system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 37741 # Cumulative time (in ticks) in various power states -system.ruby.network.routers2.percent_links_utilized 12.605654 -system.ruby.network.routers2.msg_count.Control::2 953 -system.ruby.network.routers2.msg_count.Data::2 950 -system.ruby.network.routers2.msg_count.Response_Data::4 953 -system.ruby.network.routers2.msg_count.Writeback_Control::3 950 -system.ruby.network.routers2.msg_bytes.Control::2 7624 -system.ruby.network.routers2.msg_bytes.Data::2 68400 -system.ruby.network.routers2.msg_bytes.Response_Data::4 68616 -system.ruby.network.routers2.msg_bytes.Writeback_Control::3 7600 -system.ruby.network.pwrStateResidencyTicks::UNDEFINED 37741 # Cumulative time (in ticks) in various power states -system.ruby.network.msg_count.Control 2859 -system.ruby.network.msg_count.Data 2851 -system.ruby.network.msg_count.Response_Data 2859 -system.ruby.network.msg_count.Writeback_Control 2850 -system.ruby.network.msg_byte.Control 22872 -system.ruby.network.msg_byte.Data 205272 -system.ruby.network.msg_byte.Response_Data 205848 -system.ruby.network.msg_byte.Writeback_Control 22800 -system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 37741 # Cumulative time (in ticks) in various power states -system.ruby.network.routers0.throttle0.link_utilization 12.621552 -system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 953 -system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 950 -system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 68616 -system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 7600 -system.ruby.network.routers0.throttle1.link_utilization 12.592406 -system.ruby.network.routers0.throttle1.msg_count.Control::2 953 -system.ruby.network.routers0.throttle1.msg_count.Data::2 951 -system.ruby.network.routers0.throttle1.msg_bytes.Control::2 7624 -system.ruby.network.routers0.throttle1.msg_bytes.Data::2 68472 -system.ruby.network.routers1.throttle0.link_utilization 12.589756 -system.ruby.network.routers1.throttle0.msg_count.Control::2 953 -system.ruby.network.routers1.throttle0.msg_count.Data::2 950 -system.ruby.network.routers1.throttle0.msg_bytes.Control::2 7624 -system.ruby.network.routers1.throttle0.msg_bytes.Data::2 68400 -system.ruby.network.routers1.throttle1.link_utilization 12.621552 -system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 953 -system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 950 -system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 68616 -system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 7600 -system.ruby.network.routers2.throttle0.link_utilization 12.621552 -system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 953 -system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 950 -system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 68616 -system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 7600 -system.ruby.network.routers2.throttle1.link_utilization 12.589756 -system.ruby.network.routers2.throttle1.msg_count.Control::2 953 -system.ruby.network.routers2.throttle1.msg_count.Data::2 950 -system.ruby.network.routers2.throttle1.msg_bytes.Control::2 7624 -system.ruby.network.routers2.throttle1.msg_bytes.Data::2 68400 +system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 39431 # Cumulative time (in ticks) in various power states +system.ruby.network.routers0.percent_links_utilized 11.905607 +system.ruby.network.routers0.msg_count.Control::2 941 +system.ruby.network.routers0.msg_count.Data::2 938 +system.ruby.network.routers0.msg_count.Response_Data::4 940 +system.ruby.network.routers0.msg_count.Writeback_Control::3 938 +system.ruby.network.routers0.msg_bytes.Control::2 7528 +system.ruby.network.routers0.msg_bytes.Data::2 67536 +system.ruby.network.routers0.msg_bytes.Response_Data::4 67680 +system.ruby.network.routers0.msg_bytes.Writeback_Control::3 7504 +system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 39431 # Cumulative time (in ticks) in various power states +system.ruby.network.routers1.percent_links_utilized 11.910045 +system.ruby.network.routers1.msg_count.Control::2 941 +system.ruby.network.routers1.msg_count.Data::2 938 +system.ruby.network.routers1.msg_count.Response_Data::4 941 +system.ruby.network.routers1.msg_count.Writeback_Control::3 938 +system.ruby.network.routers1.msg_bytes.Control::2 7528 +system.ruby.network.routers1.msg_bytes.Data::2 67536 +system.ruby.network.routers1.msg_bytes.Response_Data::4 67752 +system.ruby.network.routers1.msg_bytes.Writeback_Control::3 7504 +system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 39431 # Cumulative time (in ticks) in various power states +system.ruby.network.routers2.percent_links_utilized 11.907509 +system.ruby.network.routers2.msg_count.Control::2 941 +system.ruby.network.routers2.msg_count.Data::2 938 +system.ruby.network.routers2.msg_count.Response_Data::4 940 +system.ruby.network.routers2.msg_count.Writeback_Control::3 938 +system.ruby.network.routers2.msg_bytes.Control::2 7528 +system.ruby.network.routers2.msg_bytes.Data::2 67536 +system.ruby.network.routers2.msg_bytes.Response_Data::4 67680 +system.ruby.network.routers2.msg_bytes.Writeback_Control::3 7504 +system.ruby.network.pwrStateResidencyTicks::UNDEFINED 39431 # Cumulative time (in ticks) in various power states +system.ruby.network.msg_count.Control 2823 +system.ruby.network.msg_count.Data 2814 +system.ruby.network.msg_count.Response_Data 2821 +system.ruby.network.msg_count.Writeback_Control 2814 +system.ruby.network.msg_byte.Control 22584 +system.ruby.network.msg_byte.Data 202608 +system.ruby.network.msg_byte.Response_Data 203112 +system.ruby.network.msg_byte.Writeback_Control 22512 +system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 39431 # Cumulative time (in ticks) in various power states +system.ruby.network.routers0.throttle0.link_utilization 11.913215 +system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 940 +system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 938 +system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 67680 +system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 7504 +system.ruby.network.routers0.throttle1.link_utilization 11.897999 +system.ruby.network.routers0.throttle1.msg_count.Control::2 941 +system.ruby.network.routers0.throttle1.msg_count.Data::2 938 +system.ruby.network.routers0.throttle1.msg_bytes.Control::2 7528 +system.ruby.network.routers0.throttle1.msg_bytes.Data::2 67536 +system.ruby.network.routers1.throttle0.link_utilization 11.897999 +system.ruby.network.routers1.throttle0.msg_count.Control::2 941 +system.ruby.network.routers1.throttle0.msg_count.Data::2 938 +system.ruby.network.routers1.throttle0.msg_bytes.Control::2 7528 +system.ruby.network.routers1.throttle0.msg_bytes.Data::2 67536 +system.ruby.network.routers1.throttle1.link_utilization 11.922092 +system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 941 +system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 938 +system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 67752 +system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 7504 +system.ruby.network.routers2.throttle0.link_utilization 11.917020 +system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 940 +system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 938 +system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 67680 +system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 7504 +system.ruby.network.routers2.throttle1.link_utilization 11.897999 +system.ruby.network.routers2.throttle1.msg_count.Control::2 941 +system.ruby.network.routers2.throttle1.msg_count.Data::2 938 +system.ruby.network.routers2.throttle1.msg_bytes.Control::2 7528 +system.ruby.network.routers2.throttle1.msg_bytes.Data::2 67536 system.ruby.delayVCHist.vnet_1::bucket_size 1 # delay histogram for vnet_1 system.ruby.delayVCHist.vnet_1::max_bucket 9 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::samples 953 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1 | 953 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::total 953 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::samples 940 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1 | 940 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::total 940 # delay histogram for vnet_1 system.ruby.delayVCHist.vnet_2::bucket_size 1 # delay histogram for vnet_2 system.ruby.delayVCHist.vnet_2::max_bucket 9 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::samples 950 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::mean 0.393684 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::stdev 1.477888 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2 | 886 93.26% 93.26% | 0 0.00% 93.26% | 2 0.21% 93.47% | 0 0.00% 93.47% | 1 0.11% 93.58% | 0 0.00% 93.58% | 61 6.42% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::total 950 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::samples 938 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::mean 0.443497 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::stdev 1.567923 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2 | 868 92.54% 92.54% | 0 0.00% 92.54% | 1 0.11% 92.64% | 0 0.00% 92.64% | 0 0.00% 92.64% | 0 0.00% 92.64% | 69 7.36% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::total 938 # delay histogram for vnet_2 system.ruby.LD.latency_hist_seqr::bucket_size 128 system.ruby.LD.latency_hist_seqr::max_bucket 1279 -system.ruby.LD.latency_hist_seqr::samples 50 -system.ruby.LD.latency_hist_seqr::mean 620.660000 -system.ruby.LD.latency_hist_seqr::gmean 616.355454 -system.ruby.LD.latency_hist_seqr::stdev 75.297399 -system.ruby.LD.latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 3 6.00% 6.00% | 33 66.00% 72.00% | 10 20.00% 92.00% | 4 8.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.latency_hist_seqr::total 50 +system.ruby.LD.latency_hist_seqr::samples 51 +system.ruby.LD.latency_hist_seqr::mean 632.509804 +system.ruby.LD.latency_hist_seqr::gmean 625.135320 +system.ruby.LD.latency_hist_seqr::stdev 99.959466 +system.ruby.LD.latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 6 11.76% 11.76% | 20 39.22% 50.98% | 21 41.18% 92.16% | 2 3.92% 96.08% | 2 3.92% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.latency_hist_seqr::total 51 +system.ruby.LD.hit_latency_hist_seqr::bucket_size 64 +system.ruby.LD.hit_latency_hist_seqr::max_bucket 639 +system.ruby.LD.hit_latency_hist_seqr::samples 2 +system.ruby.LD.hit_latency_hist_seqr::mean 576 +system.ruby.LD.hit_latency_hist_seqr::gmean 575.579708 +system.ruby.LD.hit_latency_hist_seqr::stdev 31.112698 +system.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 50.00% 50.00% | 1 50.00% 100.00% +system.ruby.LD.hit_latency_hist_seqr::total 2 system.ruby.LD.miss_latency_hist_seqr::bucket_size 128 system.ruby.LD.miss_latency_hist_seqr::max_bucket 1279 -system.ruby.LD.miss_latency_hist_seqr::samples 50 -system.ruby.LD.miss_latency_hist_seqr::mean 620.660000 -system.ruby.LD.miss_latency_hist_seqr::gmean 616.355454 -system.ruby.LD.miss_latency_hist_seqr::stdev 75.297399 -system.ruby.LD.miss_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 3 6.00% 6.00% | 33 66.00% 72.00% | 10 20.00% 92.00% | 4 8.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.miss_latency_hist_seqr::total 50 +system.ruby.LD.miss_latency_hist_seqr::samples 49 +system.ruby.LD.miss_latency_hist_seqr::mean 634.816327 +system.ruby.LD.miss_latency_hist_seqr::gmean 627.246231 +system.ruby.LD.miss_latency_hist_seqr::stdev 101.240159 +system.ruby.LD.miss_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 6 12.24% 12.24% | 18 36.73% 48.98% | 21 42.86% 91.84% | 2 4.08% 95.92% | 2 4.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.miss_latency_hist_seqr::total 49 system.ruby.ST.latency_hist_seqr::bucket_size 128 system.ruby.ST.latency_hist_seqr::max_bucket 1279 -system.ruby.ST.latency_hist_seqr::samples 892 -system.ruby.ST.latency_hist_seqr::mean 591.263453 -system.ruby.ST.latency_hist_seqr::gmean 581.152835 -system.ruby.ST.latency_hist_seqr::stdev 96.524225 -system.ruby.ST.latency_hist_seqr | 2 0.22% 0.22% | 9 1.01% 1.23% | 6 0.67% 1.91% | 103 11.55% 13.45% | 591 66.26% 79.71% | 135 15.13% 94.84% | 39 4.37% 99.22% | 7 0.78% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.latency_hist_seqr::total 892 +system.ruby.ST.latency_hist_seqr::samples 882 +system.ruby.ST.latency_hist_seqr::mean 621.007937 +system.ruby.ST.latency_hist_seqr::gmean 609.588661 +system.ruby.ST.latency_hist_seqr::stdev 107.265659 +system.ruby.ST.latency_hist_seqr | 2 0.23% 0.23% | 7 0.79% 1.02% | 6 0.68% 1.70% | 78 8.84% 10.54% | 414 46.94% 57.48% | 318 36.05% 93.54% | 29 3.29% 96.83% | 28 3.17% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.latency_hist_seqr::total 882 system.ruby.ST.hit_latency_hist_seqr::bucket_size 128 system.ruby.ST.hit_latency_hist_seqr::max_bucket 1279 system.ruby.ST.hit_latency_hist_seqr::samples 38 -system.ruby.ST.hit_latency_hist_seqr::mean 491.526316 -system.ruby.ST.hit_latency_hist_seqr::gmean 487.637688 -system.ruby.ST.hit_latency_hist_seqr::stdev 63.347918 -system.ruby.ST.hit_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 2.63% 2.63% | 22 57.89% 60.53% | 14 36.84% 97.37% | 1 2.63% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.hit_latency_hist_seqr::mean 517.263158 +system.ruby.ST.hit_latency_hist_seqr::gmean 512.460135 +system.ruby.ST.hit_latency_hist_seqr::stdev 71.032419 +system.ruby.ST.hit_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 17 44.74% 44.74% | 20 52.63% 97.37% | 1 2.63% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ST.hit_latency_hist_seqr::total 38 system.ruby.ST.miss_latency_hist_seqr::bucket_size 128 system.ruby.ST.miss_latency_hist_seqr::max_bucket 1279 -system.ruby.ST.miss_latency_hist_seqr::samples 854 -system.ruby.ST.miss_latency_hist_seqr::mean 595.701405 -system.ruby.ST.miss_latency_hist_seqr::gmean 585.707367 -system.ruby.ST.miss_latency_hist_seqr::stdev 95.367967 -system.ruby.ST.miss_latency_hist_seqr | 2 0.23% 0.23% | 9 1.05% 1.29% | 5 0.59% 1.87% | 81 9.48% 11.36% | 577 67.56% 78.92% | 134 15.69% 94.61% | 39 4.57% 99.18% | 7 0.82% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.miss_latency_hist_seqr::total 854 +system.ruby.ST.miss_latency_hist_seqr::samples 844 +system.ruby.ST.miss_latency_hist_seqr::mean 625.678910 +system.ruby.ST.miss_latency_hist_seqr::gmean 614.370879 +system.ruby.ST.miss_latency_hist_seqr::stdev 106.283167 +system.ruby.ST.miss_latency_hist_seqr | 2 0.24% 0.24% | 7 0.83% 1.07% | 6 0.71% 1.78% | 61 7.23% 9.00% | 394 46.68% 55.69% | 317 37.56% 93.25% | 29 3.44% 96.68% | 28 3.32% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.miss_latency_hist_seqr::total 844 system.ruby.IFETCH.latency_hist_seqr::bucket_size 128 system.ruby.IFETCH.latency_hist_seqr::max_bucket 1279 -system.ruby.IFETCH.latency_hist_seqr::samples 50 -system.ruby.IFETCH.latency_hist_seqr::mean 623.140000 -system.ruby.IFETCH.latency_hist_seqr::gmean 615.727796 -system.ruby.IFETCH.latency_hist_seqr::stdev 99.820044 -system.ruby.IFETCH.latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 5 10.00% 10.00% | 30 60.00% 70.00% | 9 18.00% 88.00% | 6 12.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.latency_hist_seqr::total 50 +system.ruby.IFETCH.latency_hist_seqr::samples 49 +system.ruby.IFETCH.latency_hist_seqr::mean 642.612245 +system.ruby.IFETCH.latency_hist_seqr::gmean 634.549482 +system.ruby.IFETCH.latency_hist_seqr::stdev 106.327289 +system.ruby.IFETCH.latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 4 8.16% 8.16% | 24 48.98% 57.14% | 16 32.65% 89.80% | 2 4.08% 93.88% | 3 6.12% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.latency_hist_seqr::total 49 system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 64 system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 639 -system.ruby.IFETCH.hit_latency_hist_seqr::samples 1 -system.ruby.IFETCH.hit_latency_hist_seqr::mean 537 -system.ruby.IFETCH.hit_latency_hist_seqr::gmean 537.000000 -system.ruby.IFETCH.hit_latency_hist_seqr::stdev nan -system.ruby.IFETCH.hit_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.hit_latency_hist_seqr::total 1 +system.ruby.IFETCH.hit_latency_hist_seqr::samples 2 +system.ruby.IFETCH.hit_latency_hist_seqr::mean 604.500000 +system.ruby.IFETCH.hit_latency_hist_seqr::gmean 604.216848 +system.ruby.IFETCH.hit_latency_hist_seqr::stdev 26.162951 +system.ruby.IFETCH.hit_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 2 100.00% 100.00% +system.ruby.IFETCH.hit_latency_hist_seqr::total 2 system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 128 system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 1279 -system.ruby.IFETCH.miss_latency_hist_seqr::samples 49 -system.ruby.IFETCH.miss_latency_hist_seqr::mean 624.897959 -system.ruby.IFETCH.miss_latency_hist_seqr::gmean 617.449297 -system.ruby.IFETCH.miss_latency_hist_seqr::stdev 100.069402 -system.ruby.IFETCH.miss_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 5 10.20% 10.20% | 29 59.18% 69.39% | 9 18.37% 87.76% | 6 12.24% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.miss_latency_hist_seqr::total 49 +system.ruby.IFETCH.miss_latency_hist_seqr::samples 47 +system.ruby.IFETCH.miss_latency_hist_seqr::mean 644.234043 +system.ruby.IFETCH.miss_latency_hist_seqr::gmean 635.873481 +system.ruby.IFETCH.miss_latency_hist_seqr::stdev 108.241922 +system.ruby.IFETCH.miss_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 4 8.51% 8.51% | 22 46.81% 55.32% | 16 34.04% 89.36% | 2 4.26% 93.62% | 3 6.38% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.miss_latency_hist_seqr::total 47 system.ruby.Directory.miss_mach_latency_hist_seqr::bucket_size 128 system.ruby.Directory.miss_mach_latency_hist_seqr::max_bucket 1279 -system.ruby.Directory.miss_mach_latency_hist_seqr::samples 953 -system.ruby.Directory.miss_mach_latency_hist_seqr::mean 598.512067 -system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 588.872583 -system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 94.945507 -system.ruby.Directory.miss_mach_latency_hist_seqr | 2 0.21% 0.21% | 9 0.94% 1.15% | 5 0.52% 1.68% | 89 9.34% 11.02% | 639 67.05% 78.07% | 153 16.05% 94.12% | 49 5.14% 99.27% | 7 0.73% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_mach_latency_hist_seqr::total 953 +system.ruby.Directory.miss_mach_latency_hist_seqr::samples 940 +system.ruby.Directory.miss_mach_latency_hist_seqr::mean 627.082979 +system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 616.094261 +system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 106.107284 +system.ruby.Directory.miss_mach_latency_hist_seqr | 2 0.21% 0.21% | 7 0.74% 0.96% | 6 0.64% 1.60% | 71 7.55% 9.15% | 434 46.17% 55.32% | 354 37.66% 92.98% | 33 3.51% 96.49% | 33 3.51% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_mach_latency_hist_seqr::total 940 system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size 128 system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket 1279 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples 50 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 620.660000 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 616.355454 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 75.297399 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 3 6.00% 6.00% | 33 66.00% 72.00% | 10 20.00% 92.00% | 4 8.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total 50 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples 49 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 634.816327 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 627.246231 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 101.240159 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 6 12.24% 12.24% | 18 36.73% 48.98% | 21 42.86% 91.84% | 2 4.08% 95.92% | 2 4.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total 49 system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size 128 system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket 1279 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::samples 854 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 595.701405 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 585.707367 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 95.367967 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 2 0.23% 0.23% | 9 1.05% 1.29% | 5 0.59% 1.87% | 81 9.48% 11.36% | 577 67.56% 78.92% | 134 15.69% 94.61% | 39 4.57% 99.18% | 7 0.82% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total 854 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::samples 844 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 625.678910 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 614.370879 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 106.283167 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 2 0.24% 0.24% | 7 0.83% 1.07% | 6 0.71% 1.78% | 61 7.23% 9.00% | 394 46.68% 55.69% | 317 37.56% 93.25% | 29 3.44% 96.68% | 28 3.32% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total 844 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::bucket_size 128 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::max_bucket 1279 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::samples 49 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 624.897959 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 617.449297 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 100.069402 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 5 10.20% 10.20% | 29 59.18% 69.39% | 9 18.37% 87.76% | 6 12.24% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::total 49 -system.ruby.Directory_Controller.GETX 953 0.00% 0.00% -system.ruby.Directory_Controller.PUTX 950 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 953 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 950 0.00% 0.00% -system.ruby.Directory_Controller.I.GETX 953 0.00% 0.00% -system.ruby.Directory_Controller.M.PUTX 950 0.00% 0.00% -system.ruby.Directory_Controller.IM.Memory_Data 953 0.00% 0.00% -system.ruby.Directory_Controller.MI.Memory_Ack 950 0.00% 0.00% -system.ruby.L1Cache_Controller.Load 50 0.00% 0.00% -system.ruby.L1Cache_Controller.Ifetch 51 0.00% 0.00% -system.ruby.L1Cache_Controller.Store 893 0.00% 0.00% -system.ruby.L1Cache_Controller.Data 953 0.00% 0.00% -system.ruby.L1Cache_Controller.Replacement 952 0.00% 0.00% -system.ruby.L1Cache_Controller.Writeback_Ack 950 0.00% 0.00% -system.ruby.L1Cache_Controller.I.Load 50 0.00% 0.00% -system.ruby.L1Cache_Controller.I.Ifetch 50 0.00% 0.00% -system.ruby.L1Cache_Controller.I.Store 855 0.00% 0.00% -system.ruby.L1Cache_Controller.M.Ifetch 1 0.00% 0.00% +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::samples 47 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 644.234043 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 635.873481 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 108.241922 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 4 8.51% 8.51% | 22 46.81% 55.32% | 16 34.04% 89.36% | 2 4.26% 93.62% | 3 6.38% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::total 47 +system.ruby.Directory_Controller.GETX 941 0.00% 0.00% +system.ruby.Directory_Controller.PUTX 938 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 941 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 938 0.00% 0.00% +system.ruby.Directory_Controller.I.GETX 941 0.00% 0.00% +system.ruby.Directory_Controller.M.PUTX 938 0.00% 0.00% +system.ruby.Directory_Controller.IM.Memory_Data 941 0.00% 0.00% +system.ruby.Directory_Controller.MI.Memory_Ack 938 0.00% 0.00% +system.ruby.L1Cache_Controller.Load 51 0.00% 0.00% +system.ruby.L1Cache_Controller.Ifetch 49 0.00% 0.00% +system.ruby.L1Cache_Controller.Store 883 0.00% 0.00% +system.ruby.L1Cache_Controller.Data 940 0.00% 0.00% +system.ruby.L1Cache_Controller.Replacement 938 0.00% 0.00% +system.ruby.L1Cache_Controller.Writeback_Ack 938 0.00% 0.00% +system.ruby.L1Cache_Controller.I.Load 49 0.00% 0.00% +system.ruby.L1Cache_Controller.I.Ifetch 47 0.00% 0.00% +system.ruby.L1Cache_Controller.I.Store 845 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Load 2 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Ifetch 2 0.00% 0.00% system.ruby.L1Cache_Controller.M.Store 38 0.00% 0.00% -system.ruby.L1Cache_Controller.M.Replacement 952 0.00% 0.00% -system.ruby.L1Cache_Controller.MI.Writeback_Ack 950 0.00% 0.00% -system.ruby.L1Cache_Controller.IS.Data 99 0.00% 0.00% -system.ruby.L1Cache_Controller.IM.Data 854 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Replacement 938 0.00% 0.00% +system.ruby.L1Cache_Controller.MI.Writeback_Ack 938 0.00% 0.00% +system.ruby.L1Cache_Controller.IS.Data 96 0.00% 0.00% +system.ruby.L1Cache_Controller.IM.Data 844 0.00% 0.00% ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/config.ini b/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/config.ini index 07db75ab6..52ae02408 100644 --- a/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/config.ini +++ b/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/config.ini @@ -14,6 +14,7 @@ children=clk_domain cpu dvfs_handler membus monitor physmem boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 exit_on_work_items=false init_param=0 @@ -27,6 +28,10 @@ memories=system.physmem mmap_using_noreserve=false multi_thread=false num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null readfile= symbolfile= thermal_components= @@ -57,9 +62,15 @@ voltage=1.000000 [system.cpu] type=TrafficGen clk_domain=system.clk_domain -config_file=tests/quick/se/70.tgen/tgen-dram-ctrl.cfg +config_file=/work/curdun01/gem5-external.hg/tests/testing/../../tests/quick/se/70.tgen/tgen-dram-ctrl.cfg +default_p_state=UNDEFINED elastic_req=false eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +progress_check=1000000000 system=system port=system.monitor.slave @@ -74,9 +85,14 @@ transition_latency=100000000 [system.membus] type=NoncoherentXBar clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=1 frontend_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null response_latency=2 use_default_range=false width=16 @@ -88,6 +104,7 @@ type=CommMonitor bandwidth_bins=20 burst_length_bins=20 clk_domain=system.clk_domain +default_p_state=UNDEFINED disable_addr_dists=true disable_bandwidth_hists=false disable_burst_length_hists=false @@ -100,6 +117,10 @@ itt_bins=20 itt_max_bin=100000 latency_bins=20 outstanding_bins=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null read_addr_mask=18446744073709551615 sample_period=1000000000 system=system @@ -110,27 +131,27 @@ slave=system.cpu.port [system.physmem] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -142,6 +163,7 @@ burst_length=8 channels=1 clk_domain=system.clk_domain conf_table_reported=true +default_p_state=UNDEFINED device_bus_width=8 device_rowbuffer_size=1024 device_size=536870912 @@ -149,12 +171,17 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 page_policy=open_adaptive -range=0:134217727 +power_model=Null +range=0:134217727:0:0:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 @@ -176,9 +203,9 @@ tRTW=2500 tWR=15000 tWTR=7500 tXAW=30000 -tXP=0 +tXP=6000 tXPDLL=0 -tXS=0 +tXS=270000 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 diff --git a/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/simout b/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/simout index cf720d597..160888b39 100755 --- a/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/simout +++ b/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/simout @@ -1,10 +1,12 @@ +Redirecting stdout to build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-dram-ctrl/simout +Redirecting stderr to build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-dram-ctrl/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 21 2016 14:20:17 -gem5 started Jan 21 2016 14:20:32 -gem5 executing on zizzer, pid 63117 -command line: build/NULL/gem5.opt -d build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-dram-ctrl -re /z/atgutier/gem5/gem5-commit/tests/run.py build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-dram-ctrl +gem5 compiled Oct 13 2016 20:37:50 +gem5 started Oct 13 2016 20:38:05 +gem5 executing on e108600-lin, pid 342 +command line: /work/curdun01/gem5-external.hg/build/NULL/gem5.opt -d build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-dram-ctrl -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/70.tgen/null/none/tgen-dram-ctrl Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/stats.txt b/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/stats.txt index c0bb5bc83..5d77460fc 100644 --- a/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/stats.txt +++ b/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/stats.txt @@ -4,9 +4,9 @@ sim_seconds 0.100000 # Nu sim_ticks 100000000000 # Number of ticks simulated final_tick 100000000000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_tick_rate 10668065661 # Simulator tick rate (ticks/s) -host_mem_usage 263968 # Number of bytes of host memory used -host_seconds 9.37 # Real time elapsed on the host +host_tick_rate 5948382023 # Simulator tick rate (ticks/s) +host_mem_usage 222508 # Number of bytes of host memory used +host_seconds 16.81 # Real time elapsed on the host system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.pwrStateResidencyTicks::UNDEFINED 100000000000 # Cumulative time (in ticks) in various power states @@ -28,45 +28,45 @@ system.physmem.readReqs 1666397 # Nu system.physmem.writeReqs 1666879 # Number of write requests accepted system.physmem.readBursts 1666397 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 1666879 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 106648000 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 1408 # Total number of bytes read from write queue -system.physmem.bytesWritten 106676992 # Total number of bytes written to DRAM +system.physmem.bytesReadDRAM 106647808 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 1600 # Total number of bytes read from write queue +system.physmem.bytesWritten 106676416 # Total number of bytes written to DRAM system.physmem.bytesReadSys 106649408 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 106680256 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 22 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 30 # Number of DRAM write bursts merged with an existing one +system.physmem.servicedByWrQ 25 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 31 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 104030 # Per bank write bursts +system.physmem.perBankRdBursts::0 104029 # Per bank write bursts system.physmem.perBankRdBursts::1 103995 # Per bank write bursts system.physmem.perBankRdBursts::2 104918 # Per bank write bursts system.physmem.perBankRdBursts::3 104597 # Per bank write bursts system.physmem.perBankRdBursts::4 103869 # Per bank write bursts -system.physmem.perBankRdBursts::5 103934 # Per bank write bursts +system.physmem.perBankRdBursts::5 103933 # Per bank write bursts system.physmem.perBankRdBursts::6 103649 # Per bank write bursts -system.physmem.perBankRdBursts::7 104312 # Per bank write bursts +system.physmem.perBankRdBursts::7 104313 # Per bank write bursts system.physmem.perBankRdBursts::8 103869 # Per bank write bursts system.physmem.perBankRdBursts::9 104354 # Per bank write bursts -system.physmem.perBankRdBursts::10 103835 # Per bank write bursts -system.physmem.perBankRdBursts::11 104273 # Per bank write bursts -system.physmem.perBankRdBursts::12 104076 # Per bank write bursts +system.physmem.perBankRdBursts::10 103834 # Per bank write bursts +system.physmem.perBankRdBursts::11 104271 # Per bank write bursts +system.physmem.perBankRdBursts::12 104077 # Per bank write bursts system.physmem.perBankRdBursts::13 104035 # Per bank write bursts system.physmem.perBankRdBursts::14 104583 # Per bank write bursts system.physmem.perBankRdBursts::15 104046 # Per bank write bursts -system.physmem.perBankWrBursts::0 104357 # Per bank write bursts -system.physmem.perBankWrBursts::1 104091 # Per bank write bursts +system.physmem.perBankWrBursts::0 104356 # Per bank write bursts +system.physmem.perBankWrBursts::1 104090 # Per bank write bursts system.physmem.perBankWrBursts::2 104175 # Per bank write bursts system.physmem.perBankWrBursts::3 103885 # Per bank write bursts system.physmem.perBankWrBursts::4 104730 # Per bank write bursts -system.physmem.perBankWrBursts::5 104509 # Per bank write bursts -system.physmem.perBankWrBursts::6 104084 # Per bank write bursts -system.physmem.perBankWrBursts::7 104226 # Per bank write bursts -system.physmem.perBankWrBursts::8 104319 # Per bank write bursts +system.physmem.perBankWrBursts::5 104507 # Per bank write bursts +system.physmem.perBankWrBursts::6 104083 # Per bank write bursts +system.physmem.perBankWrBursts::7 104224 # Per bank write bursts +system.physmem.perBankWrBursts::8 104317 # Per bank write bursts system.physmem.perBankWrBursts::9 104219 # Per bank write bursts -system.physmem.perBankWrBursts::10 104227 # Per bank write bursts +system.physmem.perBankWrBursts::10 104226 # Per bank write bursts system.physmem.perBankWrBursts::11 103701 # Per bank write bursts -system.physmem.perBankWrBursts::12 104102 # Per bank write bursts +system.physmem.perBankWrBursts::12 104104 # Per bank write bursts system.physmem.perBankWrBursts::13 103984 # Per bank write bursts -system.physmem.perBankWrBursts::14 104296 # Per bank write bursts +system.physmem.perBankWrBursts::14 104295 # Per bank write bursts system.physmem.perBankWrBursts::15 103923 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry @@ -85,25 +85,25 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 1666879 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 753402 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 771059 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 83025 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 32311 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 12865 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 6959 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 3834 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1736 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 711 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 362 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 94 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 14 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 733345 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 766437 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 105881 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 41900 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 12740 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 3643 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1163 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 473 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 265 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 141 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 64 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 32 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 64 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 32 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 32 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 32 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 32 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 64 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 32 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see @@ -132,32 +132,32 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 12106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 15091 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 39564 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 91518 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 104735 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 104786 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 114835 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 116330 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 106236 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 102201 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 124996 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 116244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 105513 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 101800 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 100156 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 100074 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 99950 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 99852 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 3792 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 2888 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 2015 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 1235 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 621 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 234 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 58 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 10965 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 13956 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 32108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 80984 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 108644 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 106582 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 109181 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 116667 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 116376 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 107705 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 108162 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 128453 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 112926 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 102716 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 100795 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 100305 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 100289 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 100289 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 4132 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 2753 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1624 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 822 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 299 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 87 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 13 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see @@ -181,98 +181,106 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 3296341 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 64.715538 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 64.191659 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 23.992392 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 3288436 99.76% 99.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 5750 0.17% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 3296279 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 64.716502 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 64.191055 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 24.099997 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 3288385 99.76% 99.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 5777 0.18% 99.94% # Bytes accessed per row activation system.physmem.bytesPerActivate::256-383 32 0.00% 99.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 32 0.00% 99.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 32 0.00% 99.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 32 0.00% 99.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 32 0.00% 99.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 32 0.00% 99.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 1963 0.06% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 3296341 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 99183 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 16.800984 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 15.462609 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 106.039262 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 99182 100.00% 100.00% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::384-511 2 0.00% 99.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1 0.00% 99.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1 0.00% 99.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 64 0.00% 99.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 31 0.00% 99.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 1986 0.06% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 3296279 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 99671 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 16.718725 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 15.378386 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 105.780207 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 99670 100.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::32768-34815 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 99183 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 99183 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.805582 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.725629 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.745457 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 77723 78.36% 78.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 3827 3.86% 82.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 3399 3.43% 85.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 1646 1.66% 87.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 640 0.65% 87.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 10486 10.57% 98.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 1261 1.27% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 65 0.07% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 41 0.04% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 31 0.03% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 25 0.03% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 19 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 6 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 9 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30 4 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::31 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 99183 # Writes before turning the bus around for reads -system.physmem.totQLat 59888739257 # Total ticks spent queuing -system.physmem.totMemAccLat 91133270507 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 8331875000 # Total ticks spent in databus transfers -system.physmem.avgQLat 35939.53 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 99671 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 99670 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.723337 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.645091 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.734543 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 81521 81.79% 81.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 3623 3.63% 85.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 1868 1.87% 87.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 729 0.73% 88.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 852 0.85% 88.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 7918 7.94% 96.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 2886 2.90% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 125 0.13% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 64 0.06% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 33 0.03% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 22 0.02% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 19 0.02% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 8 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 2 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 99670 # Writes before turning the bus around for reads +system.physmem.totQLat 67244030509 # Total ticks spent queuing +system.physmem.totMemAccLat 98488505509 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 8331860000 # Total ticks spent in databus transfers +system.physmem.avgQLat 40353.55 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 54689.53 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 59103.55 # Average memory access latency per DRAM burst system.physmem.avgRdBW 1066.48 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1066.77 # Average achieved write bandwidth in MiByte/s +system.physmem.avgWrBW 1066.76 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 1066.49 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 1066.80 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 16.67 # Data bus utilization in percentage system.physmem.busUtilRead 8.33 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 8.33 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.70 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.41 # Average write queue length when enqueuing -system.physmem.readRowHits 32158 # Number of row buffer hits during reads -system.physmem.writeRowHits 4696 # Number of row buffer hits during writes +system.physmem.avgRdQLen 1.72 # Average read queue length when enqueuing +system.physmem.avgWrQLen 25.49 # Average write queue length when enqueuing +system.physmem.readRowHits 32189 # Number of row buffer hits during reads +system.physmem.writeRowHits 4714 # Number of row buffer hits during writes system.physmem.readRowHitRate 1.93 # Row buffer hit rate for reads system.physmem.writeRowHitRate 0.28 # Row buffer hit rate for writes system.physmem.avgGap 30000.50 # Average gap between requests system.physmem.pageHitRate 1.11 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 12463748640 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 6800656500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 6499693200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 5404585680 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 6531436080 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 67774130595 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 548449500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 106022700195 # Total energy per rank (pJ) -system.physmem_0.averagePower 1060.236875 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 533126864 # Time in different power states -system.physmem_0.memoryStateTime::REF 3339180000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 96126775636 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 12456264240 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 6796572750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 6497883600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 5396252400 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 6531436080 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 67770272835 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 551833500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 106000515405 # Total energy per rank (pJ) -system.physmem_1.averagePower 1060.015025 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 539825532 # Time in different power states -system.physmem_1.memoryStateTime::REF 3339180000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 96120321460 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_0.actEnergy 11770732680 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 6256266225 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 5949783420 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 4353725340 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 7874767680.000002 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 23951915280 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 170961120 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 21181523760 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 86810400 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 93287040 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 81689772945 # Total energy per rank (pJ) +system.physmem_0.averagePower 816.897729 # Core power per rank (mW) +system.physmem_0.totalIdleTime 47012409463 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 55286905 # Time in different power states +system.physmem_0.memoryStateTime::REF 3331216000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 351864100 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 225022822 # Time in different power states +system.physmem_0.memoryStateTime::ACT 49601087632 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 46435522541 # Time in different power states +system.physmem_1.actEnergy 11764756500 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 6253097400 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 5948112660 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 4347048960 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 7875382320.000002 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 23997343140 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 173667360 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 21132301410 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 86542080 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 94312680 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 81672564510 # Total energy per rank (pJ) +system.physmem_1.averagePower 816.725645 # Core power per rank (mW) +system.physmem_1.totalIdleTime 46910670248 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 62942667 # Time in different power states +system.physmem_1.memoryStateTime::REF 3331488000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 353836348 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 224863707 # Time in different power states +system.physmem_1.memoryStateTime::ACT 49694899085 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 46331970193 # Time in different power states system.pwrStateResidencyTicks::UNDEFINED 100000000000 # Cumulative time (in ticks) in various power states system.cpu.pwrStateResidencyTicks::UNDEFINED 100000000000 # Cumulative time (in ticks) in various power states system.cpu.numPackets 3333276 # Number of packets generated @@ -289,7 +297,7 @@ system.membus.pkt_size_system.monitor-master::system.physmem.port 213329664 system.membus.pkt_size::total 213329664 # Cumulative packet size per connected master and slave (bytes) system.membus.reqLayer0.occupancy 11679751447 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 11.7 # Layer utilization (%) -system.membus.respLayer0.occupancy 11025969759 # Layer occupancy (ticks) +system.membus.respLayer0.occupancy 11024098980 # Layer occupancy (ticks) system.membus.respLayer0.utilization 11.0 # Layer utilization (%) system.monitor.pwrStateResidencyTicks::UNDEFINED 100000000000 # Cumulative time (in ticks) in various power states system.monitor.readBurstLengthHist::samples 1666397 # Histogram of burst lengths of transmitted packets @@ -344,8 +352,8 @@ system.monitor.writeBurstLengthHist::76-79 0 0.00% 100.00% # system.monitor.writeBurstLengthHist::total 1666879 # Histogram of burst lengths of transmitted packets system.monitor.readBandwidthHist::samples 100 # Histogram of read bandwidth per sample period (bytes/s) system.monitor.readBandwidthHist::mean 1066494080 # Histogram of read bandwidth per sample period (bytes/s) -system.monitor.readBandwidthHist::gmean 1063154807.297242 # Histogram of read bandwidth per sample period (bytes/s) -system.monitor.readBandwidthHist::stdev 107909912.518316 # Histogram of read bandwidth per sample period (bytes/s) +system.monitor.readBandwidthHist::gmean 1063154829.648824 # Histogram of read bandwidth per sample period (bytes/s) +system.monitor.readBandwidthHist::stdev 107909695.124640 # Histogram of read bandwidth per sample period (bytes/s) system.monitor.readBandwidthHist::0-1.34218e+08 0 0.00% 0.00% # Histogram of read bandwidth per sample period (bytes/s) system.monitor.readBandwidthHist::1.34218e+08-2.68435e+08 0 0.00% 0.00% # Histogram of read bandwidth per sample period (bytes/s) system.monitor.readBandwidthHist::2.68435e+08-4.02653e+08 0 0.00% 0.00% # Histogram of read bandwidth per sample period (bytes/s) @@ -397,34 +405,34 @@ system.monitor.writeBandwidthHist::total 100 # Hi system.monitor.averageWriteBandwidth 1066802560 0.00% 0.00% # Average write bandwidth (bytes/s) system.monitor.totalWrittenBytes 106680256 # Number of bytes written system.monitor.readLatencyHist::samples 1666397 # Read request-response latency -system.monitor.readLatencyHist::mean 80828.757102 # Read request-response latency -system.monitor.readLatencyHist::gmean 75647.211665 # Read request-response latency -system.monitor.readLatencyHist::stdev 40158.670662 # Read request-response latency -system.monitor.readLatencyHist::0-32767 22 0.00% 0.00% # Read request-response latency -system.monitor.readLatencyHist::32768-65535 453126 27.19% 27.19% # Read request-response latency -system.monitor.readLatencyHist::65536-98303 1001111 60.08% 87.27% # Read request-response latency -system.monitor.readLatencyHist::98304-131071 83302 5.00% 92.27% # Read request-response latency -system.monitor.readLatencyHist::131072-163839 62543 3.75% 96.02% # Read request-response latency -system.monitor.readLatencyHist::163840-196607 26583 1.60% 97.62% # Read request-response latency -system.monitor.readLatencyHist::196608-229375 8788 0.53% 98.14% # Read request-response latency -system.monitor.readLatencyHist::229376-262143 7677 0.46% 98.61% # Read request-response latency -system.monitor.readLatencyHist::262144-294911 7849 0.47% 99.08% # Read request-response latency -system.monitor.readLatencyHist::294912-327679 7874 0.47% 99.55% # Read request-response latency -system.monitor.readLatencyHist::327680-360447 4044 0.24% 99.79% # Read request-response latency -system.monitor.readLatencyHist::360448-393215 1555 0.09% 99.88% # Read request-response latency -system.monitor.readLatencyHist::393216-425983 891 0.05% 99.94% # Read request-response latency -system.monitor.readLatencyHist::425984-458751 671 0.04% 99.98% # Read request-response latency -system.monitor.readLatencyHist::458752-491519 316 0.02% 100.00% # Read request-response latency -system.monitor.readLatencyHist::491520-524287 44 0.00% 100.00% # Read request-response latency -system.monitor.readLatencyHist::524288-557055 1 0.00% 100.00% # Read request-response latency -system.monitor.readLatencyHist::557056-589823 0 0.00% 100.00% # Read request-response latency +system.monitor.readLatencyHist::mean 85241.043010 # Read request-response latency +system.monitor.readLatencyHist::gmean 80106.557141 # Read request-response latency +system.monitor.readLatencyHist::stdev 40394.991557 # Read request-response latency +system.monitor.readLatencyHist::0-32767 25 0.00% 0.00% # Read request-response latency +system.monitor.readLatencyHist::32768-65535 443615 26.62% 26.62% # Read request-response latency +system.monitor.readLatencyHist::65536-98303 995882 59.76% 86.39% # Read request-response latency +system.monitor.readLatencyHist::98304-131071 85391 5.12% 91.51% # Read request-response latency +system.monitor.readLatencyHist::131072-163839 63740 3.83% 95.33% # Read request-response latency +system.monitor.readLatencyHist::163840-196607 33175 1.99% 97.33% # Read request-response latency +system.monitor.readLatencyHist::196608-229375 11329 0.68% 98.01% # Read request-response latency +system.monitor.readLatencyHist::229376-262143 8224 0.49% 98.50% # Read request-response latency +system.monitor.readLatencyHist::262144-294911 8145 0.49% 98.99% # Read request-response latency +system.monitor.readLatencyHist::294912-327679 8447 0.51% 99.49% # Read request-response latency +system.monitor.readLatencyHist::327680-360447 5871 0.35% 99.85% # Read request-response latency +system.monitor.readLatencyHist::360448-393215 1313 0.08% 99.93% # Read request-response latency +system.monitor.readLatencyHist::393216-425983 659 0.04% 99.97% # Read request-response latency +system.monitor.readLatencyHist::425984-458751 321 0.02% 99.98% # Read request-response latency +system.monitor.readLatencyHist::458752-491519 128 0.01% 99.99% # Read request-response latency +system.monitor.readLatencyHist::491520-524287 34 0.00% 99.99% # Read request-response latency +system.monitor.readLatencyHist::524288-557055 33 0.00% 100.00% # Read request-response latency +system.monitor.readLatencyHist::557056-589823 65 0.00% 100.00% # Read request-response latency system.monitor.readLatencyHist::589824-622591 0 0.00% 100.00% # Read request-response latency system.monitor.readLatencyHist::622592-655359 0 0.00% 100.00% # Read request-response latency system.monitor.readLatencyHist::total 1666397 # Read request-response latency system.monitor.writeLatencyHist::samples 1666878 # Write request-response latency -system.monitor.writeLatencyHist::mean 19652.383883 # Write request-response latency -system.monitor.writeLatencyHist::gmean 19632.845881 # Write request-response latency -system.monitor.writeLatencyHist::stdev 964.266043 # Write request-response latency +system.monitor.writeLatencyHist::mean 20414.077900 # Write request-response latency +system.monitor.writeLatencyHist::gmean 20330.210031 # Write request-response latency +system.monitor.writeLatencyHist::stdev 1962.397109 # Write request-response latency system.monitor.writeLatencyHist::0-2047 0 0.00% 0.00% # Write request-response latency system.monitor.writeLatencyHist::2048-4095 0 0.00% 0.00% # Write request-response latency system.monitor.writeLatencyHist::4096-6143 0 0.00% 0.00% # Write request-response latency @@ -434,13 +442,13 @@ system.monitor.writeLatencyHist::10240-12287 0 0.00% 0.00% system.monitor.writeLatencyHist::12288-14335 0 0.00% 0.00% # Write request-response latency system.monitor.writeLatencyHist::14336-16383 0 0.00% 0.00% # Write request-response latency system.monitor.writeLatencyHist::16384-18431 0 0.00% 0.00% # Write request-response latency -system.monitor.writeLatencyHist::18432-20479 1607382 96.43% 96.43% # Write request-response latency -system.monitor.writeLatencyHist::20480-22527 29447 1.77% 98.20% # Write request-response latency -system.monitor.writeLatencyHist::22528-24575 12825 0.77% 98.97% # Write request-response latency -system.monitor.writeLatencyHist::24576-26623 7107 0.43% 99.39% # Write request-response latency -system.monitor.writeLatencyHist::26624-28671 4858 0.29% 99.68% # Write request-response latency -system.monitor.writeLatencyHist::28672-30719 4531 0.27% 99.96% # Write request-response latency -system.monitor.writeLatencyHist::30720-32767 728 0.04% 100.00% # Write request-response latency +system.monitor.writeLatencyHist::18432-20479 1311621 78.69% 78.69% # Write request-response latency +system.monitor.writeLatencyHist::20480-22527 97272 5.84% 84.52% # Write request-response latency +system.monitor.writeLatencyHist::22528-24575 151281 9.08% 93.60% # Write request-response latency +system.monitor.writeLatencyHist::24576-26623 83768 5.03% 98.62% # Write request-response latency +system.monitor.writeLatencyHist::26624-28671 15604 0.94% 99.56% # Write request-response latency +system.monitor.writeLatencyHist::28672-30719 6292 0.38% 99.94% # Write request-response latency +system.monitor.writeLatencyHist::30720-32767 1040 0.06% 100.00% # Write request-response latency system.monitor.writeLatencyHist::32768-34815 0 0.00% 100.00% # Write request-response latency system.monitor.writeLatencyHist::34816-36863 0 0.00% 100.00% # Write request-response latency system.monitor.writeLatencyHist::36864-38911 0 0.00% 100.00% # Write request-response latency @@ -531,18 +539,18 @@ system.monitor.ittReqReq::min_value 28000 # Re system.monitor.ittReqReq::max_value 1041309 # Request-to-request inter transaction time system.monitor.ittReqReq::total 3333275 # Request-to-request inter transaction time system.monitor.outstandingReadsHist::samples 100 # Outstanding read transactions -system.monitor.outstandingReadsHist::mean 1.290000 # Outstanding read transactions +system.monitor.outstandingReadsHist::mean 1.310000 # Outstanding read transactions system.monitor.outstandingReadsHist::gmean 0 # Outstanding read transactions -system.monitor.outstandingReadsHist::stdev 1.216843 # Outstanding read transactions -system.monitor.outstandingReadsHist::0 22 22.00% 22.00% # Outstanding read transactions -system.monitor.outstandingReadsHist::1 46 46.00% 68.00% # Outstanding read transactions -system.monitor.outstandingReadsHist::2 23 23.00% 91.00% # Outstanding read transactions -system.monitor.outstandingReadsHist::3 5 5.00% 96.00% # Outstanding read transactions -system.monitor.outstandingReadsHist::4 1 1.00% 97.00% # Outstanding read transactions -system.monitor.outstandingReadsHist::5 2 2.00% 99.00% # Outstanding read transactions -system.monitor.outstandingReadsHist::6 0 0.00% 99.00% # Outstanding read transactions -system.monitor.outstandingReadsHist::7 0 0.00% 99.00% # Outstanding read transactions -system.monitor.outstandingReadsHist::8 1 1.00% 100.00% # Outstanding read transactions +system.monitor.outstandingReadsHist::stdev 0.991835 # Outstanding read transactions +system.monitor.outstandingReadsHist::0 20 20.00% 20.00% # Outstanding read transactions +system.monitor.outstandingReadsHist::1 44 44.00% 64.00% # Outstanding read transactions +system.monitor.outstandingReadsHist::2 24 24.00% 88.00% # Outstanding read transactions +system.monitor.outstandingReadsHist::3 9 9.00% 97.00% # Outstanding read transactions +system.monitor.outstandingReadsHist::4 3 3.00% 100.00% # Outstanding read transactions +system.monitor.outstandingReadsHist::5 0 0.00% 100.00% # Outstanding read transactions +system.monitor.outstandingReadsHist::6 0 0.00% 100.00% # Outstanding read transactions +system.monitor.outstandingReadsHist::7 0 0.00% 100.00% # Outstanding read transactions +system.monitor.outstandingReadsHist::8 0 0.00% 100.00% # Outstanding read transactions system.monitor.outstandingReadsHist::9 0 0.00% 100.00% # Outstanding read transactions system.monitor.outstandingReadsHist::10 0 0.00% 100.00% # Outstanding read transactions system.monitor.outstandingReadsHist::11 0 0.00% 100.00% # Outstanding read transactions @@ -556,11 +564,11 @@ system.monitor.outstandingReadsHist::18 0 0.00% 100.00% # Ou system.monitor.outstandingReadsHist::19 0 0.00% 100.00% # Outstanding read transactions system.monitor.outstandingReadsHist::total 100 # Outstanding read transactions system.monitor.outstandingWritesHist::samples 100 # Outstanding write transactions -system.monitor.outstandingWritesHist::mean 0.340000 # Outstanding write transactions +system.monitor.outstandingWritesHist::mean 0.380000 # Outstanding write transactions system.monitor.outstandingWritesHist::gmean 0 # Outstanding write transactions -system.monitor.outstandingWritesHist::stdev 0.476095 # Outstanding write transactions -system.monitor.outstandingWritesHist::0 66 66.00% 66.00% # Outstanding write transactions -system.monitor.outstandingWritesHist::1 34 34.00% 100.00% # Outstanding write transactions +system.monitor.outstandingWritesHist::stdev 0.487832 # Outstanding write transactions +system.monitor.outstandingWritesHist::0 62 62.00% 62.00% # Outstanding write transactions +system.monitor.outstandingWritesHist::1 38 38.00% 100.00% # Outstanding write transactions system.monitor.outstandingWritesHist::2 0 0.00% 100.00% # Outstanding write transactions system.monitor.outstandingWritesHist::3 0 0.00% 100.00% # Outstanding write transactions system.monitor.outstandingWritesHist::4 0 0.00% 100.00% # Outstanding write transactions |