diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2013-03-01 13:20:30 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2013-03-01 13:20:30 -0500 |
| commit | cb9e208a4c1b564556275d9b6ee0257da4208a88 (patch) | |
| tree | 6d1e5d4393ae0758da69261a11c37374c2a47a88 /tests/quick | |
| parent | 0facc8e1acb9b5261ac49f87ca489ba823c8e9f3 (diff) | |
| download | gem5-cb9e208a4c1b564556275d9b6ee0257da4208a88.tar.xz | |
stats: Update stats to reflect SimpleDRAM changes
This patch bumps the stats to reflect the slight change in how the
retry is handled, and also the pruning of some redundant stats.
Diffstat (limited to 'tests/quick')
27 files changed, 4240 insertions, 4754 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt index a5d2b415b..dd98a6573 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.870325 # Nu sim_ticks 1870325497500 # Number of ticks simulated final_tick 1870325497500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2356651 # Simulator instruction rate (inst/s) -host_op_rate 2356650 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 69796056257 # Simulator tick rate (ticks/s) -host_mem_usage 349376 # Number of bytes of host memory used -host_seconds 26.80 # Real time elapsed on the host +host_inst_rate 3609656 # Simulator instruction rate (inst/s) +host_op_rate 3609654 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 106905838632 # Simulator tick rate (ticks/s) +host_mem_usage 305660 # Number of bytes of host memory used +host_seconds 17.50 # Real time elapsed on the host sim_insts 63151114 # Number of instructions simulated sim_ops 63151114 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu0.inst 760896 # Number of bytes read from this memory @@ -99,26 +99,13 @@ system.physmem.readPktSize::3 0 # Ca system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes system.physmem.readPktSize::6 0 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 0 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 0 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 0 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 0 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 0 # Categorize write packet sizes system.physmem.rdQLenPdf::0 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 0 # What read queue length does an incoming req see @@ -151,7 +138,6 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see @@ -184,7 +170,6 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see system.physmem.totQLat 0 # Total cycles spent in queuing delays system.physmem.totMemAccLat 0 # Sum of mem lat for all requests system.physmem.totBusLat 0 # Total cycles spent in databus access diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt index 178493c15..2e73db07d 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.829331 # Nu sim_ticks 1829330593000 # Number of ticks simulated final_tick 1829330593000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1133415 # Simulator instruction rate (inst/s) -host_op_rate 1133413 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 34534714924 # Simulator tick rate (ticks/s) -host_mem_usage 347332 # Number of bytes of host memory used -host_seconds 52.97 # Real time elapsed on the host +host_inst_rate 3233953 # Simulator instruction rate (inst/s) +host_op_rate 3233951 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 98537371937 # Simulator tick rate (ticks/s) +host_mem_usage 303612 # Number of bytes of host memory used +host_seconds 18.56 # Real time elapsed on the host sim_insts 60037737 # Number of instructions simulated sim_ops 60037737 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 857856 # Number of bytes read from this memory @@ -89,26 +89,13 @@ system.physmem.readPktSize::3 0 # Ca system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes system.physmem.readPktSize::6 0 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 0 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 0 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 0 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 0 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 0 # Categorize write packet sizes system.physmem.rdQLenPdf::0 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 0 # What read queue length does an incoming req see @@ -141,7 +128,6 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see @@ -174,7 +160,6 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see system.physmem.totQLat 0 # Total cycles spent in queuing delays system.physmem.totMemAccLat 0 # Sum of mem lat for all requests system.physmem.totBusLat 0 # Total cycles spent in databus access @@ -608,69 +593,5 @@ system.cpu.dcache.cache_copies 0 # nu system.cpu.dcache.writebacks::writebacks 833491 # number of writebacks system.cpu.dcache.writebacks::total 833491 # number of writebacks system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 2042707 # number of replacements -system.cpu.dcache.tagsinuse 511.997802 # Cycle average of tags in use -system.cpu.dcache.total_refs 14038405 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 2043219 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 6.870729 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.997802 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999996 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999996 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 7807769 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7807769 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 5848199 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 5848199 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 183140 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 183140 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 199281 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 199281 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 13655968 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 13655968 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 13655968 # number of overall hits -system.cpu.dcache.overall_hits::total 13655968 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1721709 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1721709 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 304365 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 304365 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 17162 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 17162 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 2026074 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2026074 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2026074 # number of overall misses -system.cpu.dcache.overall_misses::total 2026074 # number of overall misses -system.cpu.dcache.ReadReq_accesses::cpu.data 9529478 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 9529478 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 6152564 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6152564 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200302 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 200302 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 199281 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 199281 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 15682042 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15682042 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 15682042 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15682042 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.180672 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.180672 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049470 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.049470 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085681 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.085681 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.129197 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.129197 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.129197 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.129197 # miss rate for overall accesses -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 833491 # number of writebacks -system.cpu.dcache.writebacks::total 833491 # number of writebacks -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt index e93e66fed..3e3128027 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt @@ -1,145 +1,132 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.952724 # Number of seconds simulated -sim_ticks 1952724269500 # Number of ticks simulated -final_tick 1952724269500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.954691 # Number of seconds simulated +sim_ticks 1954691371500 # Number of ticks simulated +final_tick 1954691371500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1678586 # Simulator instruction rate (inst/s) -host_op_rate 1678585 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 53851852439 # Simulator tick rate (ticks/s) -host_mem_usage 333452 # Number of bytes of host memory used -host_seconds 36.26 # Real time elapsed on the host -sim_insts 60867235 # Number of instructions simulated -sim_ops 60867235 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu0.inst 830208 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24725568 # Number of bytes read from this memory -system.physmem.bytes_read::tsunami.ide 2650880 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 35200 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 438144 # Number of bytes read from this memory -system.physmem.bytes_read::total 28680000 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 830208 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 35200 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 865408 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7698816 # Number of bytes written to this memory -system.physmem.bytes_written::total 7698816 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 12972 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 386337 # Number of read requests responded to by this memory -system.physmem.num_reads::tsunami.ide 41420 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 550 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 6846 # Number of read requests responded to by this memory -system.physmem.num_reads::total 448125 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 120294 # Number of write requests responded to by this memory -system.physmem.num_writes::total 120294 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 425154 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 12662089 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1357529 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 18026 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 224376 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14687173 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 425154 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 18026 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 443180 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3942603 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3942603 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3942603 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 425154 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 12662089 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1357529 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 18026 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 224376 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 18629776 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 448125 # Total number of read requests seen -system.physmem.writeReqs 120294 # Total number of write requests seen -system.physmem.cpureqs 598443 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 28680000 # Total number of bytes read from memory -system.physmem.bytesWritten 7698816 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 28680000 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7698816 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 68 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 6945 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 28344 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 28173 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 28017 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 27785 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 27951 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 27964 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 28022 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 27886 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 28437 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 28288 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 28341 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 28051 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 27575 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 27797 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 27570 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 27856 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 7821 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 7610 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 7567 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 7380 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 7470 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 7435 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 7506 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 7435 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 7992 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 7835 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 7874 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 7588 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 7131 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 7250 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 7029 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 7371 # Track writes on a per bank basis +host_inst_rate 798728 # Simulator instruction rate (inst/s) +host_op_rate 798728 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 26318676085 # Simulator tick rate (ticks/s) +host_mem_usage 332420 # Number of bytes of host memory used +host_seconds 74.27 # Real time elapsed on the host +sim_insts 59321614 # Number of instructions simulated +sim_ops 59321614 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu0.inst 829376 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24757440 # Number of bytes read from this memory +system.physmem.bytes_read::tsunami.ide 2650816 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 34176 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 389696 # Number of bytes read from this memory +system.physmem.bytes_read::total 28661504 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 829376 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 34176 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 863552 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7676992 # Number of bytes written to this memory +system.physmem.bytes_written::total 7676992 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 12959 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 386835 # Number of read requests responded to by this memory +system.physmem.num_reads::tsunami.ide 41419 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 534 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 6089 # Number of read requests responded to by this memory +system.physmem.num_reads::total 447836 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 119953 # Number of write requests responded to by this memory +system.physmem.num_writes::total 119953 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 424300 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12665652 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1356130 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 17484 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 199364 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 14662931 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 424300 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 17484 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 441784 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3927470 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3927470 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3927470 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 424300 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 12665652 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1356130 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 17484 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 199364 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 18590401 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 447836 # Total number of read requests seen +system.physmem.writeReqs 119953 # Total number of write requests seen +system.physmem.cpureqs 572898 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 28661504 # Total number of bytes read from memory +system.physmem.bytesWritten 7676992 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 28661504 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7676992 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 69 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 3161 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 28180 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 28120 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 28097 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 27826 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 27944 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 27900 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 27858 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 27869 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 28342 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 28141 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 28250 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 28016 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 27813 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 27987 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 27674 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 27750 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 7637 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 7504 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 7585 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 7374 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 7488 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 7379 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 7353 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 7437 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 7887 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 7685 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 7821 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 7507 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 7382 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 7492 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 7142 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 7280 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 1406 # Number of times wr buffer was full causing retry -system.physmem.totGap 1952670553500 # Total gap between requests +system.physmem.numWrRetry 1948 # Number of times wr buffer was full causing retry +system.physmem.totGap 1954684300500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 448125 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 0 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 121700 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 6945 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 407346 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 4785 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 3654 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 2222 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3126 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2960 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2693 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2681 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 2639 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 2601 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1535 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1459 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1410 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1352 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1370 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1401 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 1629 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 1508 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 906 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 771 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 9 # What read queue length does an incoming req see +system.physmem.readPktSize::6 447836 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 0 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 119953 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 407021 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 4814 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 3665 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 2219 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3122 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2946 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2699 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2701 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 2643 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 2593 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1538 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1461 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1424 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1368 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1347 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1387 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 1607 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 1512 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 904 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 783 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 13 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -151,226 +138,224 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 3696 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 3880 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4297 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 4344 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 4866 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 5206 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 5215 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 5216 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 5218 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 5230 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 5230 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 5230 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 5230 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 5230 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 5230 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 5230 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 5230 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5230 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5230 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5230 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5230 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5230 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5230 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 1535 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 1351 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 934 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 887 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 364 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 24 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 3709 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 3875 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4276 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 4328 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 4843 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 5193 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 5199 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 5202 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 5201 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 5215 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 5215 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 5215 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 5215 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 5215 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 5215 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 5215 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 5215 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5215 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5215 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5215 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5215 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5215 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5215 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 1507 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 1341 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 940 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 888 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 373 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 17 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 4798545467 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 13448530467 # Sum of mem lat for all requests -system.physmem.totBusLat 2240285000 # Total cycles spent in databus access -system.physmem.totBankLat 6409700000 # Total cycles spent in bank access -system.physmem.avgQLat 10709.68 # Average queueing delay per request -system.physmem.avgBankLat 14305.55 # Average bank access latency per request +system.physmem.wrQLenPdf::31 14 # What write queue length does an incoming req see +system.physmem.totQLat 4783798250 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 13397999500 # Sum of mem lat for all requests +system.physmem.totBusLat 2238835000 # Total cycles spent in databus access +system.physmem.totBankLat 6375366250 # Total cycles spent in bank access +system.physmem.avgQLat 10683.68 # Average queueing delay per request +system.physmem.avgBankLat 14238.13 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 30015.22 # Average memory access latency -system.physmem.avgRdBW 14.69 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 3.94 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 14.69 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 3.94 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 29921.81 # Average memory access latency +system.physmem.avgRdBW 14.66 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 3.93 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 14.66 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 3.93 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.15 # Data bus utilization in percentage system.physmem.avgRdQLen 0.01 # Average read queue length over time -system.physmem.avgWrQLen 10.11 # Average write queue length over time -system.physmem.readRowHits 419119 # Number of row buffer hits during reads -system.physmem.writeRowHits 92373 # Number of row buffer hits during writes -system.physmem.readRowHitRate 93.54 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 76.79 # Row buffer hit rate for writes -system.physmem.avgGap 3435266.16 # Average gap between requests -system.l2c.replacements 341268 # number of replacements -system.l2c.tagsinuse 65240.270273 # Cycle average of tags in use -system.l2c.total_refs 2443367 # Total number of references to valid blocks. -system.l2c.sampled_refs 406244 # Sample count of references to valid blocks. -system.l2c.avg_refs 6.014531 # Average number of references to valid blocks. -system.l2c.warmup_cycle 6941595752 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 55425.253207 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 4870.495631 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 4790.652765 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 116.277662 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 37.591009 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.845722 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.074318 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.073100 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.001774 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.000574 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.995488 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.inst 687318 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 665852 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 314877 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 108330 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1776377 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 794206 # number of Writeback hits -system.l2c.Writeback_hits::total 794206 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 172 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 530 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 702 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 40 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 22 # 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mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.014149 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.290583 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.006144 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.115812 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.170350 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 49176.032178 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 30735.648128 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 51613.825843 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 65764.211640 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 31635.606352 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10067.951269 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10056.895726 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10072.390740 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 35618.275824 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 44001.114264 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 36073.129790 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 50329.225948 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 32268.229136 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 52474.220000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 44763.268318 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 33081.002138 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 50329.225948 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 32268.229136 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 52474.220000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 44763.268318 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 33081.002138 # average overall mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 35536.568001 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 44509.775431 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 35973.485927 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 49176.032178 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 32169.195445 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 51613.825843 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 45167.559686 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 32931.588648 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 49176.032178 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 32169.195445 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 51613.825843 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 45167.559686 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 32931.588648 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -502,39 +487,39 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.replacements 41696 # number of replacements -system.iocache.tagsinuse 0.569993 # Cycle average of tags in use +system.iocache.replacements 41694 # number of replacements +system.iocache.tagsinuse 0.572561 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 41712 # Sample count of references to valid blocks. +system.iocache.sampled_refs 41710 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 1746698431000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::tsunami.ide 0.569993 # Average occupied blocks per requestor -system.iocache.occ_percent::tsunami.ide 0.035625 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.035625 # Average percentage of cache occupancy -system.iocache.ReadReq_misses::tsunami.ide 176 # number of ReadReq misses -system.iocache.ReadReq_misses::total 176 # number of ReadReq misses +system.iocache.warmup_cycle 1746701282000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::tsunami.ide 0.572561 # Average occupied blocks per requestor +system.iocache.occ_percent::tsunami.ide 0.035785 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.035785 # Average percentage of cache occupancy +system.iocache.ReadReq_misses::tsunami.ide 174 # number of ReadReq misses +system.iocache.ReadReq_misses::total 174 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses -system.iocache.demand_misses::tsunami.ide 41728 # number of demand (read+write) misses -system.iocache.demand_misses::total 41728 # number of demand (read+write) misses -system.iocache.overall_misses::tsunami.ide 41728 # number of overall misses -system.iocache.overall_misses::total 41728 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21268998 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21268998 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 10634917806 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 10634917806 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 10656186804 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 10656186804 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 10656186804 # number of overall miss cycles -system.iocache.overall_miss_latency::total 10656186804 # number of overall miss cycles -system.iocache.ReadReq_accesses::tsunami.ide 176 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 176 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::tsunami.ide 41726 # number of demand (read+write) misses +system.iocache.demand_misses::total 41726 # number of demand (read+write) misses +system.iocache.overall_misses::tsunami.ide 41726 # number of overall misses +system.iocache.overall_misses::total 41726 # number of overall misses +system.iocache.ReadReq_miss_latency::tsunami.ide 21042998 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21042998 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 10674900806 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 10674900806 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 10695943804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 10695943804 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 10695943804 # number of overall miss cycles +system.iocache.overall_miss_latency::total 10695943804 # number of overall miss cycles +system.iocache.ReadReq_accesses::tsunami.ide 174 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 174 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 41728 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 41728 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 41728 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 41728 # number of overall (read+write) accesses +system.iocache.demand_accesses::tsunami.ide 41726 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 41726 # number of demand (read+write) accesses +system.iocache.overall_accesses::tsunami.ide 41726 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 41726 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses @@ -543,40 +528,40 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 120846.579545 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 120846.579545 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 255942.380776 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 255942.380776 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 255372.574866 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 255372.574866 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 255372.574866 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 255372.574866 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 284837 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 120936.770115 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 120936.770115 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 256904.620861 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 256904.620861 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 256337.626516 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 256337.626516 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 256337.626516 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 256337.626516 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 286340 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 27190 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 27291 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 10.475800 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 10.492104 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 41520 # number of writebacks system.iocache.writebacks::total 41520 # number of writebacks -system.iocache.ReadReq_mshr_misses::tsunami.ide 176 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 176 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::tsunami.ide 174 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 174 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 41728 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 41728 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 41728 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 41728 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12116250 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 12116250 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8472911060 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 8472911060 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 8485027310 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 8485027310 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 8485027310 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 8485027310 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::tsunami.ide 41726 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 41726 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 41726 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 41726 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11994249 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 11994249 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8512910554 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 8512910554 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 8524904803 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 8524904803 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 8524904803 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 8524904803 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -585,14 +570,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68842.329545 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 68842.329545 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 203911.028591 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 203911.028591 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 203341.336992 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 203341.336992 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 203341.336992 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 203341.336992 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68932.465517 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 68932.465517 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 204873.665624 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 204873.665624 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 204306.782414 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 204306.782414 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 204306.782414 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 204306.782414 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -610,22 +595,22 @@ system.cpu0.dtb.fetch_hits 0 # IT system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 7490982 # DTB read hits -system.cpu0.dtb.read_misses 7443 # DTB read misses +system.cpu0.dtb.read_hits 8631552 # DTB read hits +system.cpu0.dtb.read_misses 7447 # DTB read misses system.cpu0.dtb.read_acv 210 # DTB read access violations -system.cpu0.dtb.read_accesses 490673 # DTB read accesses -system.cpu0.dtb.write_hits 5068153 # DTB write hits +system.cpu0.dtb.read_accesses 490676 # DTB read accesses +system.cpu0.dtb.write_hits 6044616 # DTB write hits system.cpu0.dtb.write_misses 813 # DTB write misses system.cpu0.dtb.write_acv 134 # DTB write access violations system.cpu0.dtb.write_accesses 187452 # DTB write accesses -system.cpu0.dtb.data_hits 12559135 # DTB hits -system.cpu0.dtb.data_misses 8256 # DTB misses +system.cpu0.dtb.data_hits 14676168 # DTB hits +system.cpu0.dtb.data_misses 8260 # DTB misses system.cpu0.dtb.data_acv 344 # DTB access violations -system.cpu0.dtb.data_accesses 678125 # DTB accesses -system.cpu0.itb.fetch_hits 3503456 # ITB hits +system.cpu0.dtb.data_accesses 678128 # DTB accesses +system.cpu0.itb.fetch_hits 3853435 # ITB hits system.cpu0.itb.fetch_misses 3871 # ITB misses system.cpu0.itb.fetch_acv 184 # ITB acv -system.cpu0.itb.fetch_accesses 3507327 # ITB accesses +system.cpu0.itb.fetch_accesses 3857306 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -638,55 +623,55 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 3904305293 # number of cpu cycles simulated +system.cpu0.numCycles 3908211536 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 47706703 # Number of instructions committed -system.cpu0.committedOps 47706703 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 44241786 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 211423 # Number of float alu accesses -system.cpu0.num_func_calls 1201591 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 5601417 # number of instructions that are conditional controls -system.cpu0.num_int_insts 44241786 # number of integer instructions -system.cpu0.num_fp_insts 211423 # number of float instructions -system.cpu0.num_int_register_reads 60797943 # number of times the integer registers were read -system.cpu0.num_int_register_writes 32968604 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 102697 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 104564 # number of times the floating registers were written -system.cpu0.num_mem_refs 12599388 # number of memory refs -system.cpu0.num_load_insts 7518173 # Number of load instructions -system.cpu0.num_store_insts 5081215 # Number of store instructions -system.cpu0.num_idle_cycles 3700976170.173713 # Number of idle cycles -system.cpu0.num_busy_cycles 203329122.826288 # Number of busy cycles -system.cpu0.not_idle_fraction 0.052078 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.947922 # Percentage of idle cycles +system.cpu0.committedInsts 54061829 # Number of instructions committed +system.cpu0.committedOps 54061829 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 50032862 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 294101 # Number of float alu accesses +system.cpu0.num_func_calls 1426501 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 6236445 # number of instructions that are conditional controls +system.cpu0.num_int_insts 50032862 # number of integer instructions +system.cpu0.num_fp_insts 294101 # number of float instructions +system.cpu0.num_int_register_reads 68513770 # number of times the integer registers were read +system.cpu0.num_int_register_writes 37070851 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 143419 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 146520 # number of times the floating registers were written +system.cpu0.num_mem_refs 14722187 # number of memory refs +system.cpu0.num_load_insts 8662865 # Number of load instructions +system.cpu0.num_store_insts 6059322 # Number of store instructions +system.cpu0.num_idle_cycles 3679287399.643625 # Number of idle cycles +system.cpu0.num_busy_cycles 228924136.356375 # Number of busy cycles +system.cpu0.not_idle_fraction 0.058575 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.941425 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6787 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 165132 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 56916 40.19% 40.19% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 131 0.09% 40.28% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1973 1.39% 41.67% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 418 0.30% 41.97% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 82194 58.03% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 141632 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 56372 49.08% 49.08% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 131 0.11% 49.20% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1973 1.72% 50.92% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 418 0.36% 51.28% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 55954 48.72% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 114848 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1900150859000 97.34% 97.34% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 92973000 0.00% 97.34% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 760723500 0.04% 97.38% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 310562000 0.02% 97.40% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 50837499000 2.60% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1952152616500 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.990442 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.quiesce 6369 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 202997 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 72749 40.62% 40.62% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 131 0.07% 40.70% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1975 1.10% 41.80% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 6 0.00% 41.80% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 104220 58.20% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 179081 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 71382 49.27% 49.27% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 131 0.09% 49.36% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1975 1.36% 50.73% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 6 0.00% 50.73% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 71376 49.27% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 144870 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1898301273000 97.14% 97.14% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 93023500 0.00% 97.15% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 762236500 0.04% 97.19% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 5235500 0.00% 97.19% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 54943969500 2.81% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1954105738000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.981209 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.680755 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.810890 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.684859 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.808964 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 8 3.60% 3.60% # number of syscalls executed system.cpu0.kern.syscall::3 19 8.56% 12.16% # number of syscalls executed system.cpu0.kern.syscall::4 4 1.80% 13.96% # number of syscalls executed @@ -718,37 +703,37 @@ system.cpu0.kern.syscall::144 2 0.90% 99.10% # nu system.cpu0.kern.syscall::147 2 0.90% 100.00% # number of syscalls executed system.cpu0.kern.syscall::total 222 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 500 0.33% 0.33% # number of callpals executed -system.cpu0.kern.callpal::wrmces 1 0.00% 0.33% # number of callpals executed -system.cpu0.kern.callpal::wrfen 1 0.00% 0.34% # number of callpals executed -system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.34% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3074 2.05% 2.39% # number of callpals executed -system.cpu0.kern.callpal::tbi 51 0.03% 2.42% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.00% 2.42% # number of callpals executed -system.cpu0.kern.callpal::swpipl 134771 89.88% 92.30% # number of callpals executed -system.cpu0.kern.callpal::rdps 6676 4.45% 96.75% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 96.75% # number of callpals executed -system.cpu0.kern.callpal::wrusp 3 0.00% 96.75% # number of callpals executed -system.cpu0.kern.callpal::rdusp 9 0.01% 96.76% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 96.76% # number of callpals executed -system.cpu0.kern.callpal::rti 4338 2.89% 99.66% # number of callpals executed -system.cpu0.kern.callpal::callsys 381 0.25% 99.91% # number of callpals executed -system.cpu0.kern.callpal::imb 136 0.09% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 149953 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 6892 # number of protection mode switches +system.cpu0.kern.callpal::wripir 88 0.05% 0.05% # number of callpals executed +system.cpu0.kern.callpal::wrmces 1 0.00% 0.05% # number of callpals executed +system.cpu0.kern.callpal::wrfen 1 0.00% 0.05% # number of callpals executed +system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.05% # number of callpals executed +system.cpu0.kern.callpal::swpctx 3896 2.07% 2.12% # number of callpals executed +system.cpu0.kern.callpal::tbi 51 0.03% 2.15% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.00% 2.15% # number of callpals executed +system.cpu0.kern.callpal::swpipl 172217 91.50% 93.65% # number of callpals executed +system.cpu0.kern.callpal::rdps 6678 3.55% 97.19% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 97.19% # number of callpals executed +system.cpu0.kern.callpal::wrusp 3 0.00% 97.20% # number of callpals executed +system.cpu0.kern.callpal::rdusp 9 0.00% 97.20% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 97.20% # number of callpals executed +system.cpu0.kern.callpal::rti 4751 2.52% 99.73% # number of callpals executed +system.cpu0.kern.callpal::callsys 381 0.20% 99.93% # number of callpals executed +system.cpu0.kern.callpal::imb 136 0.07% 100.00% # number of callpals executed +system.cpu0.kern.callpal::total 188224 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 7304 # number of protection mode switches system.cpu0.kern.mode_switch::user 1283 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches system.cpu0.kern.mode_good::kernel 1283 system.cpu0.kern.mode_good::user 1283 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.186158 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.175657 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.313884 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1948377502000 99.82% 99.82% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 3456174500 0.18% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.298824 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1950347295500 99.82% 99.82% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 3454635500 0.18% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3075 # number of times the context was actually changed +system.cpu0.kern.swap_context 3897 # number of times the context was actually changed system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -780,51 +765,51 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu0.icache.replacements 699703 # number of replacements -system.cpu0.icache.tagsinuse 509.161264 # Cycle average of tags in use -system.cpu0.icache.total_refs 47014995 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 700215 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 67.143656 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 32599184000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 509.161264 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.994456 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.994456 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 47014995 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 47014995 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 47014995 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 47014995 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 47014995 # number of overall hits -system.cpu0.icache.overall_hits::total 47014995 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 700308 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 700308 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 700308 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 700308 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 700308 # number of overall misses -system.cpu0.icache.overall_misses::total 700308 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 9851397000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 9851397000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 9851397000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 9851397000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 9851397000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 9851397000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 47715303 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 47715303 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 47715303 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 47715303 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 47715303 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 47715303 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014677 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.014677 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014677 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.014677 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014677 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.014677 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14067.234702 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14067.234702 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14067.234702 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14067.234702 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14067.234702 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14067.234702 # average overall miss latency +system.cpu0.icache.replacements 915312 # number of replacements +system.cpu0.icache.tagsinuse 509.170565 # Cycle average of tags in use +system.cpu0.icache.total_refs 53154487 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 915824 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 58.040068 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 32594703000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 509.170565 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.994474 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.994474 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 53154487 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 53154487 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 53154487 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 53154487 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 53154487 # number of overall hits +system.cpu0.icache.overall_hits::total 53154487 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 915946 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 915946 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 915946 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 915946 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 915946 # number of overall misses +system.cpu0.icache.overall_misses::total 915946 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 12645153500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 12645153500 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 12645153500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 12645153500 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 12645153500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 12645153500 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 54070433 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 54070433 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 54070433 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 54070433 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 54070433 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 54070433 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.016940 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.016940 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.016940 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.016940 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.016940 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.016940 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13805.566595 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13805.566595 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13805.566595 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13805.566595 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13805.566595 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13805.566595 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -833,112 +818,112 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 700308 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 700308 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 700308 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 700308 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 700308 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 700308 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 8450781000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 8450781000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 8450781000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 8450781000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 8450781000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 8450781000 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014677 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014677 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014677 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.014677 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014677 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.014677 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12067.234702 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12067.234702 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12067.234702 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12067.234702 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12067.234702 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12067.234702 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 915946 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 915946 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 915946 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 915946 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 915946 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 915946 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10813261500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 10813261500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10813261500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 10813261500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10813261500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 10813261500 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.016940 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.016940 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.016940 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.016940 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.016940 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.016940 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11805.566595 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11805.566595 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11805.566595 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11805.566595 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11805.566595 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11805.566595 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 1182211 # number of replacements -system.cpu0.dcache.tagsinuse 505.184188 # Cycle average of tags in use -system.cpu0.dcache.total_refs 11367781 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 1182629 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 9.612297 # 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miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.086551 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.002238 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.002238 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.092752 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.092752 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.092752 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.092752 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 21614.825841 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 21614.825841 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 28142.720441 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 28142.720441 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13115.798923 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13115.798923 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5834.883721 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5834.883721 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 23046.581213 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 23046.581213 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 23046.581213 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 23046.581213 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -947,62 +932,62 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 680601 # number of writebacks -system.cpu0.dcache.writebacks::total 680601 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 939643 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 939643 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 251886 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 251886 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13649 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13649 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5418 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 5418 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1191529 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1191529 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1191529 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1191529 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 19241816500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 19241816500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7138904000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7138904000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 121870500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 121870500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 30400000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 30400000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 26380720500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 26380720500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 26380720500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 26380720500 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1465344500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1465344500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2274931000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2274931000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3740275500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3740275500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.127856 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.127856 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051285 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051285 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088509 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088509 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.035260 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.035260 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.097183 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.097183 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.097183 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.097183 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 20477.794758 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 20477.794758 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 28341.805420 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 28341.805420 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8928.895890 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8928.895890 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5610.926541 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5610.926541 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 22140.225290 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 22140.225290 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 22140.225290 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 22140.225290 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 789805 # number of writebacks +system.cpu0.dcache.writebacks::total 789805 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1035921 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 1035921 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 291041 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 291041 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 16710 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 16710 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 430 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 430 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1326962 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1326962 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1326962 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1326962 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 20319410000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 20319410000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7608603500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7608603500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 185745000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 185745000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 1649000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 1649000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 27928013500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 27928013500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 27928013500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 27928013500 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1465455500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1465455500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2092162000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2092162000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3557617500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3557617500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.122521 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.122521 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.049738 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.049738 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.086551 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.086551 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.002238 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.002238 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.092752 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.092752 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.092752 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.092752 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 19614.825841 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 19614.825841 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 26142.720441 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 26142.720441 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11115.798923 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11115.798923 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3834.883721 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3834.883721 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 21046.581213 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21046.581213 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 21046.581213 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21046.581213 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1014,22 +999,22 @@ system.cpu1.dtb.fetch_hits 0 # IT system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 2417694 # DTB read hits +system.cpu1.dtb.read_hits 1047086 # DTB read hits system.cpu1.dtb.read_misses 2992 # DTB read misses system.cpu1.dtb.read_acv 0 # DTB read access violations system.cpu1.dtb.read_accesses 239363 # DTB read accesses -system.cpu1.dtb.write_hits 1754404 # DTB write hits +system.cpu1.dtb.write_hits 650181 # DTB write hits system.cpu1.dtb.write_misses 341 # DTB write misses system.cpu1.dtb.write_acv 29 # DTB write access violations system.cpu1.dtb.write_accesses 105247 # DTB write accesses -system.cpu1.dtb.data_hits 4172098 # DTB hits +system.cpu1.dtb.data_hits 1697267 # DTB hits system.cpu1.dtb.data_misses 3333 # DTB misses system.cpu1.dtb.data_acv 29 # DTB access violations system.cpu1.dtb.data_accesses 344610 # DTB accesses -system.cpu1.itb.fetch_hits 1961503 # ITB hits +system.cpu1.itb.fetch_hits 1487534 # ITB hits system.cpu1.itb.fetch_misses 1216 # ITB misses system.cpu1.itb.fetch_acv 0 # ITB acv -system.cpu1.itb.fetch_accesses 1962719 # ITB accesses +system.cpu1.itb.fetch_accesses 1488750 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -1042,51 +1027,51 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 3905448539 # number of cpu cycles simulated +system.cpu1.numCycles 3909382743 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 13160532 # Number of instructions committed -system.cpu1.committedOps 13160532 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 12141335 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 171917 # Number of float alu accesses -system.cpu1.num_func_calls 411397 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1307333 # number of instructions that are conditional controls -system.cpu1.num_int_insts 12141335 # number of integer instructions -system.cpu1.num_fp_insts 171917 # number of float instructions -system.cpu1.num_int_register_reads 16724790 # number of times the integer registers were read -system.cpu1.num_int_register_writes 8912820 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 89976 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 91834 # number of times the floating registers were written -system.cpu1.num_mem_refs 4195541 # number of memory refs -system.cpu1.num_load_insts 2431931 # Number of load instructions -system.cpu1.num_store_insts 1763610 # Number of store instructions -system.cpu1.num_idle_cycles 3855992964.998025 # Number of idle cycles -system.cpu1.num_busy_cycles 49455574.001975 # Number of busy cycles -system.cpu1.not_idle_fraction 0.012663 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.987337 # Percentage of idle cycles +system.cpu1.committedInsts 5259785 # Number of instructions committed +system.cpu1.committedOps 5259785 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 4928462 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 34031 # Number of float alu accesses +system.cpu1.num_func_calls 156703 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 508760 # number of instructions that are conditional controls +system.cpu1.num_int_insts 4928462 # number of integer instructions +system.cpu1.num_fp_insts 34031 # number of float instructions +system.cpu1.num_int_register_reads 6858583 # number of times the integer registers were read +system.cpu1.num_int_register_writes 3715950 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 22062 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 21862 # number of times the floating registers were written +system.cpu1.num_mem_refs 1706720 # number of memory refs +system.cpu1.num_load_insts 1053093 # Number of load instructions +system.cpu1.num_store_insts 653627 # Number of store instructions +system.cpu1.num_idle_cycles 3890042761.998010 # Number of idle cycles +system.cpu1.num_busy_cycles 19339981.001990 # Number of busy cycles +system.cpu1.not_idle_fraction 0.004947 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.995053 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2696 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 78331 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 26451 38.35% 38.35% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1967 2.85% 41.20% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 500 0.72% 41.92% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 40063 58.08% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 68981 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 25618 48.15% 48.15% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1967 3.70% 51.85% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 500 0.94% 52.79% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 25118 47.21% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 53203 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1909244973500 97.77% 97.77% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 705660500 0.04% 97.81% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 346600000 0.02% 97.83% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 42426277500 2.17% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1952723511500 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.968508 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 2297 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 35535 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 8961 31.73% 31.73% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1969 6.97% 38.70% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 88 0.31% 39.01% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 17223 60.99% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 28241 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 8951 45.05% 45.05% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1969 9.91% 54.95% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 88 0.44% 55.40% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 8863 44.60% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 19871 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1917858613000 98.12% 98.12% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 705516000 0.04% 98.15% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 59546500 0.00% 98.15% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 36066938000 1.85% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1954690613500 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.998884 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.626963 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.771270 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::31 0.514603 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.703622 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.syscall::3 11 10.58% 10.58% # number of syscalls executed system.cpu1.kern.syscall::6 10 9.62% 20.19% # number of syscalls executed system.cpu1.kern.syscall::15 1 0.96% 21.15% # number of syscalls executed @@ -1102,81 +1087,81 @@ system.cpu1.kern.syscall::74 10 9.62% 97.12% # nu system.cpu1.kern.syscall::132 3 2.88% 100.00% # number of syscalls executed system.cpu1.kern.syscall::total 104 # number of syscalls executed system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 418 0.59% 0.59% # number of callpals executed -system.cpu1.kern.callpal::wrmces 1 0.00% 0.59% # number of callpals executed -system.cpu1.kern.callpal::wrfen 1 0.00% 0.59% # number of callpals executed -system.cpu1.kern.callpal::swpctx 1983 2.78% 3.37% # number of callpals executed -system.cpu1.kern.callpal::tbi 3 0.00% 3.38% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.01% 3.39% # number of callpals executed -system.cpu1.kern.callpal::swpipl 62750 88.03% 91.41% # number of callpals executed -system.cpu1.kern.callpal::rdps 2168 3.04% 94.46% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 94.46% # number of callpals executed -system.cpu1.kern.callpal::wrusp 4 0.01% 94.46% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.00% 94.47% # number of callpals executed -system.cpu1.kern.callpal::rti 3763 5.28% 99.75% # number of callpals executed -system.cpu1.kern.callpal::callsys 136 0.19% 99.94% # number of callpals executed -system.cpu1.kern.callpal::imb 44 0.06% 100.00% # number of callpals executed +system.cpu1.kern.callpal::wripir 6 0.02% 0.02% # number of callpals executed +system.cpu1.kern.callpal::wrmces 1 0.00% 0.03% # number of callpals executed +system.cpu1.kern.callpal::wrfen 1 0.00% 0.03% # number of callpals executed +system.cpu1.kern.callpal::swpctx 337 1.17% 1.20% # number of callpals executed +system.cpu1.kern.callpal::tbi 3 0.01% 1.21% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.02% 1.23% # number of callpals executed +system.cpu1.kern.callpal::swpipl 23653 81.85% 83.08% # number of callpals executed +system.cpu1.kern.callpal::rdps 2170 7.51% 90.59% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 90.59% # number of callpals executed +system.cpu1.kern.callpal::wrusp 4 0.01% 90.61% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.01% 90.62% # number of callpals executed +system.cpu1.kern.callpal::rti 2530 8.75% 99.37% # number of callpals executed +system.cpu1.kern.callpal::callsys 136 0.47% 99.84% # number of callpals executed +system.cpu1.kern.callpal::imb 44 0.15% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 71284 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 2048 # number of protection mode switches -system.cpu1.kern.mode_switch::user 465 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2876 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 889 -system.cpu1.kern.mode_good::user 465 -system.cpu1.kern.mode_good::idle 424 -system.cpu1.kern.mode_switch_good::kernel 0.434082 # fraction of useful protection mode switches +system.cpu1.kern.callpal::total 28898 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 803 # number of protection mode switches +system.cpu1.kern.mode_switch::user 464 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2065 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 477 +system.cpu1.kern.mode_good::user 464 +system.cpu1.kern.mode_good::idle 13 +system.cpu1.kern.mode_switch_good::kernel 0.594022 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.147427 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.329931 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 17784732000 0.91% 0.91% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 1713538500 0.09% 1.00% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1933225237500 99.00% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 1984 # number of times the context was actually changed -system.cpu1.icache.replacements 314891 # number of replacements -system.cpu1.icache.tagsinuse 448.025093 # Cycle average of tags in use -system.cpu1.icache.total_refs 12848456 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 315403 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 40.736632 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 1950842738500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 448.025093 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.875049 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.875049 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 12848456 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 12848456 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 12848456 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 12848456 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 12848456 # number of overall hits -system.cpu1.icache.overall_hits::total 12848456 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 315439 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 315439 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 315439 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 315439 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 315439 # number of overall misses -system.cpu1.icache.overall_misses::total 315439 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4168917000 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 4168917000 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 4168917000 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 4168917000 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 4168917000 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 4168917000 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 13163895 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 13163895 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 13163895 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 13163895 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 13163895 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 13163895 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.023962 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.023962 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.023962 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.023962 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.023962 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.023962 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13216.238322 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13216.238322 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13216.238322 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13216.238322 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13216.238322 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13216.238322 # average overall miss latency +system.cpu1.kern.mode_switch_good::idle 0.006295 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.286315 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 3558805000 0.18% 0.18% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 1714794500 0.09% 0.27% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1949417010500 99.73% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 338 # number of times the context was actually changed +system.cpu1.icache.replacements 86368 # number of replacements +system.cpu1.icache.tagsinuse 420.702382 # Cycle average of tags in use +system.cpu1.icache.total_refs 5176232 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 86880 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 59.579098 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 1938927920500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::cpu1.inst 420.702382 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.821684 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.821684 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 5176232 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 5176232 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 5176232 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 5176232 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 5176232 # number of overall hits +system.cpu1.icache.overall_hits::total 5176232 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 86916 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 86916 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 86916 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 86916 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 86916 # number of overall misses +system.cpu1.icache.overall_misses::total 86916 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 1175951500 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 1175951500 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 1175951500 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 1175951500 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 1175951500 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 1175951500 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 5263148 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 5263148 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 5263148 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 5263148 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 5263148 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 5263148 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.016514 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.016514 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.016514 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.016514 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.016514 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.016514 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13529.747112 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13529.747112 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13529.747112 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13529.747112 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13529.747112 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13529.747112 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1185,112 +1170,112 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 315439 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 315439 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 315439 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 315439 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 315439 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 315439 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3538039000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 3538039000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3538039000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 3538039000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3538039000 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 3538039000 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.023962 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.023962 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.023962 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.023962 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.023962 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.023962 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11216.238322 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11216.238322 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11216.238322 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11216.238322 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11216.238322 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11216.238322 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 86916 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 86916 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 86916 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 86916 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 86916 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 86916 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 1002119500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 1002119500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 1002119500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 1002119500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 1002119500 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 1002119500 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016514 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.016514 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.016514 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.016514 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.016514 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.016514 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11529.747112 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11529.747112 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11529.747112 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11529.747112 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11529.747112 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11529.747112 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 165415 # number of replacements -system.cpu1.dcache.tagsinuse 486.567196 # Cycle average of tags in use -system.cpu1.dcache.total_refs 4004380 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 165927 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 24.133384 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 60834829000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 486.567196 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.950327 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.950327 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 2254351 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 2254351 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 1637565 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 1637565 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 47962 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 47962 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 50536 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 50536 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 3891916 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 3891916 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 3891916 # number of overall hits -system.cpu1.dcache.overall_hits::total 3891916 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 117672 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 117672 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 62334 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 62334 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 8861 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 8861 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 5817 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 5817 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 180006 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 180006 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 180006 # number of overall misses -system.cpu1.dcache.overall_misses::total 180006 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1427906500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 1427906500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1084822000 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 1084822000 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 81394000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 81394000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 42192000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 42192000 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 2512728500 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 2512728500 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 2512728500 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 2512728500 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 2372023 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 2372023 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 1699899 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 1699899 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 56823 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 56823 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 56353 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 56353 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 4071922 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 4071922 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 4071922 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 4071922 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.049608 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.049608 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.036669 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.036669 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.155940 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.155940 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.103224 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.103224 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.044207 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.044207 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.044207 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.044207 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12134.632708 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 12134.632708 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 17403.375365 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 17403.375365 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9185.644961 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9185.644961 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7253.223311 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7253.223311 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 13959.137473 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 13959.137473 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 13959.137473 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 13959.137473 # average overall miss latency +system.cpu1.dcache.replacements 52807 # number of replacements +system.cpu1.dcache.tagsinuse 417.673106 # Cycle average of tags in use +system.cpu1.dcache.total_refs 1641018 # Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 53319 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 30.777359 # Average number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 1938580812000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.occ_blocks::cpu1.data 417.673106 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.815768 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.815768 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 1001238 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 1001238 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 616220 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 616220 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 10806 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 10806 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 11203 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 11203 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 1617458 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 1617458 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 1617458 # number of overall hits +system.cpu1.dcache.overall_hits::total 1617458 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 37008 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 37008 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 20401 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 20401 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 956 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 956 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 500 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 500 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 57409 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 57409 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 57409 # number of overall misses +system.cpu1.dcache.overall_misses::total 57409 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 463706500 # 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number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 1674867 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.035645 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.035645 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.032046 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.032046 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.081279 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.081279 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.042724 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.042724 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.034277 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.034277 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.034277 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.034277 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12529.898941 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 12529.898941 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 26513.455223 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 26513.455223 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 11089.435146 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 11089.435146 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7388 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7388 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17499.129056 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 17499.129056 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17499.129056 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 17499.129056 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1299,62 +1284,62 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 113605 # number of writebacks -system.cpu1.dcache.writebacks::total 113605 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 117672 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 117672 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 62334 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 62334 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 8861 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 8861 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 5817 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 5817 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 180006 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 180006 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 180006 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 180006 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1192562500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1192562500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 960154000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 960154000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 63672000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 63672000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 30558000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 30558000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2152716500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 2152716500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2152716500 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 2152716500 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 19380500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 19380500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 712390500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 712390500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 731771000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 731771000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.049608 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.049608 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036669 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.036669 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.155940 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.155940 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.103224 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.103224 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.044207 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.044207 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.044207 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.044207 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10134.632708 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10134.632708 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15403.375365 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15403.375365 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7185.644961 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7185.644961 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5253.223311 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5253.223311 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 11959.137473 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 11959.137473 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 11959.137473 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 11959.137473 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 30630 # number of writebacks +system.cpu1.dcache.writebacks::total 30630 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 37008 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 37008 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 20401 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 20401 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 956 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 956 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 500 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 500 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 57409 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 57409 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 57409 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 57409 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 389690500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 389690500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 500099000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 500099000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 8689500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 8689500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 2694000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 2694000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 889789500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 889789500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 889789500 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 889789500 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 19380000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 19380000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 529600000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 529600000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 548980000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 548980000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035645 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035645 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.032046 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.032046 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.081279 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.081279 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.042724 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.042724 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.034277 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.034277 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.034277 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.034277 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10529.898941 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10529.898941 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 24513.455223 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 24513.455223 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 9089.435146 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 9089.435146 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5388 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5388 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15499.129056 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15499.129056 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15499.129056 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15499.129056 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt index 37fa2c1e1..10a028441 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt @@ -1,135 +1,122 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.910548 # Number of seconds simulated -sim_ticks 1910547559000 # Number of ticks simulated -final_tick 1910547559000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.913475 # Number of seconds simulated +sim_ticks 1913474690000 # Number of ticks simulated +final_tick 1913474690000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1284259 # Simulator instruction rate (inst/s) -host_op_rate 1284258 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 43720523895 # Simulator tick rate (ticks/s) -host_mem_usage 330356 # Number of bytes of host memory used -host_seconds 43.70 # Real time elapsed on the host -sim_insts 56120911 # Number of instructions simulated -sim_ops 56120911 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 850624 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24858368 # Number of bytes read from this memory -system.physmem.bytes_read::tsunami.ide 2652352 # Number of bytes read from this memory -system.physmem.bytes_read::total 28361344 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 850624 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 850624 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7404352 # Number of bytes written to this memory -system.physmem.bytes_written::total 7404352 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 13291 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388412 # Number of read requests responded to by this memory -system.physmem.num_reads::tsunami.ide 41443 # Number of read requests responded to by this memory -system.physmem.num_reads::total 443146 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 115693 # Number of write requests responded to by this memory -system.physmem.num_writes::total 115693 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 445225 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 13011122 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1388268 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14844616 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 445225 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 445225 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3875513 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3875513 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3875513 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 445225 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 13011122 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1388268 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 18720129 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 443146 # Total number of read requests seen -system.physmem.writeReqs 115693 # Total number of write requests seen -system.physmem.cpureqs 561589 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 28361344 # Total number of bytes read from memory -system.physmem.bytesWritten 7404352 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 28361344 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7404352 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 45 # Number of read reqs serviced by write Q +host_inst_rate 1324010 # Simulator instruction rate (inst/s) +host_op_rate 1324010 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 45134311907 # Simulator tick rate (ticks/s) +host_mem_usage 328328 # Number of bytes of host memory used +host_seconds 42.40 # Real time elapsed on the host +sim_insts 56131527 # Number of instructions simulated +sim_ops 56131527 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 850560 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24859456 # Number of bytes read from this memory +system.physmem.bytes_read::tsunami.ide 2652096 # Number of bytes read from this memory +system.physmem.bytes_read::total 28362112 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 850560 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 850560 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7404992 # Number of bytes written to this memory +system.physmem.bytes_written::total 7404992 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 13290 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388429 # Number of read requests responded to by this memory +system.physmem.num_reads::tsunami.ide 41439 # Number of read requests responded to by this memory +system.physmem.num_reads::total 443158 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 115703 # Number of write requests responded to by this memory +system.physmem.num_writes::total 115703 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 444511 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 12991787 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1386010 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 14822308 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 444511 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 444511 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3869919 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3869919 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3869919 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 444511 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 12991787 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1386010 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 18692227 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 443158 # Total number of read requests seen +system.physmem.writeReqs 115703 # Total number of write requests seen +system.physmem.cpureqs 560726 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 28362112 # Total number of bytes read from memory +system.physmem.bytesWritten 7404992 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 28362112 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7404992 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 61 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 130 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 27901 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 27706 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 27906 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 27707 # Track reads on a per bank basis system.physmem.perBankRdReqs::2 27556 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 27375 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 27383 # Track reads on a per bank basis system.physmem.perBankRdReqs::4 27676 # Track reads on a per bank basis system.physmem.perBankRdReqs::5 27765 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 27827 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 27615 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 28008 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 27828 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 27614 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 28005 # Track reads on a per bank basis system.physmem.perBankRdReqs::9 27777 # Track reads on a per bank basis system.physmem.perBankRdReqs::10 27792 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 27562 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 27598 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 27733 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 27646 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 27564 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 7483 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 7263 # Track writes on a per bank basis +system.physmem.perBankRdReqs::11 27558 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 27591 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 27731 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 27648 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 27560 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 7488 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 7264 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 7148 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 7032 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 7167 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 7214 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 7312 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 7182 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 7584 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 7040 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 7173 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 7213 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 7315 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 7181 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 7581 # Track writes on a per bank basis system.physmem.perBankWrReqs::9 7357 # Track writes on a per bank basis system.physmem.perBankWrReqs::10 7354 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 7067 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 7154 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 7184 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 7113 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 7079 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 7063 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 7148 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 7186 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 7115 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 7077 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 2065 # Number of times wr buffer was full causing retry -system.physmem.totGap 1910535659000 # Total gap between requests +system.physmem.numWrRetry 1735 # Number of times wr buffer was full causing retry +system.physmem.totGap 1913462790000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 443146 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 0 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 117758 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 130 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 402456 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 4645 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 3680 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 2219 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3123 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2964 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2721 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2721 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 2666 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 2589 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1544 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1454 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1412 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1360 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1368 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1379 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 1611 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 1491 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 926 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 759 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 13 # What read queue length does an incoming req see +system.physmem.readPktSize::6 443158 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 0 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 115703 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 402452 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 4725 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 3681 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 2218 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3124 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2960 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2702 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2703 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 2646 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 2585 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1528 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1461 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1423 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1368 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1353 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1388 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 1604 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 1473 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 916 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 777 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 10 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -141,20 +128,19 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 3510 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 3683 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4101 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 4153 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 4653 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 5001 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 5007 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 5012 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 5015 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 5030 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 5030 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 5030 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 5030 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 3531 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 3690 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 4152 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 4652 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 5003 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 5013 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 5015 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 5016 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 5031 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 5031 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 5031 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 5031 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 5030 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 5030 # What write queue length does an incoming req see system.physmem.wrQLenPdf::15 5030 # What write queue length does an incoming req see @@ -165,46 +151,45 @@ system.physmem.wrQLenPdf::19 5030 # Wh system.physmem.wrQLenPdf::20 5030 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 5030 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 5030 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 1521 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 1348 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 930 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 877 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 377 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 29 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 1500 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 1341 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 925 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 879 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 379 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 28 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 16 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 4718066660 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 13230246660 # Sum of mem lat for all requests -system.physmem.totBusLat 2215505000 # Total cycles spent in databus access -system.physmem.totBankLat 6296675000 # Total cycles spent in bank access -system.physmem.avgQLat 10647.84 # Average queueing delay per request -system.physmem.avgBankLat 14210.47 # Average bank access latency per request +system.physmem.totQLat 4718928250 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 13231418250 # Sum of mem lat for all requests +system.physmem.totBusLat 2215485000 # Total cycles spent in databus access +system.physmem.totBankLat 6297005000 # Total cycles spent in bank access +system.physmem.avgQLat 10649.88 # Average queueing delay per request +system.physmem.avgBankLat 14211.35 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 29858.31 # Average memory access latency -system.physmem.avgRdBW 14.84 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 3.88 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 14.84 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 3.88 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 29861.22 # Average memory access latency +system.physmem.avgRdBW 14.82 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 3.87 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 14.82 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 3.87 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.15 # Data bus utilization in percentage system.physmem.avgRdQLen 0.01 # Average read queue length over time -system.physmem.avgWrQLen 11.47 # Average write queue length over time -system.physmem.readRowHits 415807 # Number of row buffer hits during reads -system.physmem.writeRowHits 89941 # Number of row buffer hits during writes -system.physmem.readRowHitRate 93.84 # Row buffer hit rate for reads +system.physmem.avgWrQLen 9.64 # Average write queue length over time +system.physmem.readRowHits 415747 # Number of row buffer hits during reads +system.physmem.writeRowHits 89943 # Number of row buffer hits during writes +system.physmem.readRowHitRate 93.83 # Row buffer hit rate for reads system.physmem.writeRowHitRate 77.74 # Row buffer hit rate for writes -system.physmem.avgGap 3418758.64 # Average gap between requests +system.physmem.avgGap 3423861.73 # Average gap between requests system.iocache.replacements 41685 # number of replacements -system.iocache.tagsinuse 1.342284 # Cycle average of tags in use +system.iocache.tagsinuse 1.364719 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 1745701071000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::tsunami.ide 1.342284 # Average occupied blocks per requestor -system.iocache.occ_percent::tsunami.ide 0.083893 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.083893 # Average percentage of cache occupancy +system.iocache.warmup_cycle 1745699710000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::tsunami.ide 1.364719 # Average occupied blocks per requestor +system.iocache.occ_percent::tsunami.ide 0.085295 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.085295 # Average percentage of cache occupancy system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses @@ -215,12 +200,12 @@ system.iocache.overall_misses::tsunami.ide 41725 # system.iocache.overall_misses::total 41725 # number of overall misses system.iocache.ReadReq_miss_latency::tsunami.ide 20927998 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 20927998 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 10644331806 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 10644331806 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 10665259804 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 10665259804 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 10665259804 # number of overall miss cycles -system.iocache.overall_miss_latency::total 10665259804 # number of overall miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 10661973806 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 10661973806 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 10682901804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 10682901804 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 10682901804 # number of overall miss cycles +system.iocache.overall_miss_latency::total 10682901804 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) @@ -239,17 +224,17 @@ system.iocache.overall_miss_rate::tsunami.ide 1 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::tsunami.ide 120971.086705 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 120971.086705 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 256168.940268 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 256168.940268 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 255608.383559 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 255608.383559 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 255608.383559 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 255608.383559 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 285028 # number of cycles access was blocked +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 256593.516702 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 256593.516702 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 256031.199617 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 256031.199617 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 256031.199617 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 256031.199617 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 285723 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 27152 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 27146 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 10.497496 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 10.525418 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -263,14 +248,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 41725 system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11931250 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 11931250 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8482336109 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 8482336109 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 8494267359 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 8494267359 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 8494267359 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 8494267359 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11931249 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 11931249 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8499962078 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 8499962078 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 8511893327 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 8511893327 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 8511893327 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 8511893327 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -279,14 +264,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68966.763006 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 68966.763006 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 204137.853990 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 204137.853990 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 203577.408244 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 203577.408244 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 203577.408244 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 203577.408244 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68966.757225 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 68966.757225 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 204562.044619 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 204562.044619 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 203999.840072 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 203999.840072 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 203999.840072 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 203999.840072 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -304,22 +289,22 @@ system.cpu.dtb.fetch_hits 0 # IT system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9055197 # DTB read hits +system.cpu.dtb.read_hits 9056964 # DTB read hits system.cpu.dtb.read_misses 10329 # DTB read misses system.cpu.dtb.read_acv 210 # DTB read access violations system.cpu.dtb.read_accesses 728856 # DTB read accesses -system.cpu.dtb.write_hits 6350929 # DTB write hits +system.cpu.dtb.write_hits 6352252 # DTB write hits system.cpu.dtb.write_misses 1142 # DTB write misses system.cpu.dtb.write_acv 157 # DTB write access violations system.cpu.dtb.write_accesses 291931 # DTB write accesses -system.cpu.dtb.data_hits 15406126 # DTB hits +system.cpu.dtb.data_hits 15409216 # DTB hits system.cpu.dtb.data_misses 11471 # DTB misses system.cpu.dtb.data_acv 367 # DTB access violations system.cpu.dtb.data_accesses 1020787 # DTB accesses -system.cpu.itb.fetch_hits 4974131 # ITB hits +system.cpu.itb.fetch_hits 4974658 # ITB hits system.cpu.itb.fetch_misses 5006 # ITB misses system.cpu.itb.fetch_acv 184 # ITB acv -system.cpu.itb.fetch_accesses 4979137 # ITB accesses +system.cpu.itb.fetch_accesses 4979664 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -332,51 +317,51 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 3821095118 # number of cpu cycles simulated +system.cpu.numCycles 3826949380 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 56120911 # Number of instructions committed -system.cpu.committedOps 56120911 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 51995405 # Number of integer alu accesses +system.cpu.committedInsts 56131527 # Number of instructions committed +system.cpu.committedOps 56131527 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 52005592 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 324259 # Number of float alu accesses -system.cpu.num_func_calls 1481756 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 6462892 # number of instructions that are conditional controls -system.cpu.num_int_insts 51995405 # number of integer instructions +system.cpu.num_func_calls 1482234 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 6464100 # number of instructions that are conditional controls +system.cpu.num_int_insts 52005592 # number of integer instructions system.cpu.num_fp_insts 324259 # number of float instructions -system.cpu.num_int_register_reads 71234690 # number of times the integer registers were read -system.cpu.num_int_register_writes 38473511 # number of times the integer registers were written +system.cpu.num_int_register_reads 71250465 # number of times the integer registers were read +system.cpu.num_int_register_writes 38480970 # number of times the integer registers were written system.cpu.num_fp_register_reads 163543 # number of times the floating registers were read system.cpu.num_fp_register_writes 166418 # number of times the floating registers were written -system.cpu.num_mem_refs 15458726 # number of memory refs -system.cpu.num_load_insts 9092044 # Number of load instructions -system.cpu.num_store_insts 6366682 # Number of store instructions -system.cpu.num_idle_cycles 3587142255.998123 # Number of idle cycles -system.cpu.num_busy_cycles 233952862.001878 # Number of busy cycles -system.cpu.not_idle_fraction 0.061227 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.938773 # Percentage of idle cycles +system.cpu.num_mem_refs 15461819 # number of memory refs +system.cpu.num_load_insts 9093811 # Number of load instructions +system.cpu.num_store_insts 6368008 # Number of store instructions +system.cpu.num_idle_cycles 3593003741.998122 # Number of idle cycles +system.cpu.num_busy_cycles 233945638.001878 # Number of busy cycles +system.cpu.not_idle_fraction 0.061131 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.938869 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6380 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211970 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74891 40.89% 40.89% # number of times we switched to this ipl +system.cpu.kern.inst.quiesce 6379 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 212010 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74899 40.89% 40.89% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 131 0.07% 40.96% # number of times we switched to this ipl -system.cpu.kern.ipl_count::22 1930 1.05% 42.01% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 106204 57.99% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 183156 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73524 49.31% 49.31% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_count::22 1933 1.06% 42.01% # number of times we switched to this ipl +system.cpu.kern.ipl_count::31 106230 57.99% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 183193 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73532 49.31% 49.31% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::22 1930 1.29% 50.69% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73524 49.31% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 149109 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1855675111500 97.13% 97.13% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 91586500 0.00% 97.13% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 735892500 0.04% 97.17% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 54044234500 2.83% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1910546825000 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981747 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_good::22 1933 1.30% 50.69% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::31 73532 49.31% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 149128 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1858610780000 97.13% 97.13% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 91300500 0.00% 97.14% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 737276500 0.04% 97.18% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 54034599000 2.82% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1913473956000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981749 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.692290 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.814109 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.692196 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.814049 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -415,29 +400,29 @@ system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # nu system.cpu.kern.callpal::swpctx 4174 2.16% 2.17% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.19% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal::swpipl 175939 91.22% 93.42% # number of callpals executed -system.cpu.kern.callpal::rdps 6831 3.54% 96.96% # number of callpals executed +system.cpu.kern.callpal::swpipl 175970 91.22% 93.41% # number of callpals executed +system.cpu.kern.callpal::rdps 6834 3.54% 96.96% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.96% # number of callpals executed -system.cpu.kern.callpal::rdusp 9 0.00% 96.97% # number of callpals executed +system.cpu.kern.callpal::rdusp 9 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal::whami 2 0.00% 96.97% # number of callpals executed -system.cpu.kern.callpal::rti 5155 2.67% 99.64% # number of callpals executed +system.cpu.kern.callpal::rti 5158 2.67% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192879 # number of callpals executed +system.cpu.kern.callpal::total 192916 # number of callpals executed system.cpu.kern.mode_switch::kernel 5900 # number of protection mode switches -system.cpu.kern.mode_switch::user 1744 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2095 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1913 -system.cpu.kern.mode_good::user 1744 +system.cpu.kern.mode_switch::user 1742 # number of protection mode switches +system.cpu.kern.mode_switch::idle 2098 # number of protection mode switches +system.cpu.kern.mode_good::kernel 1911 +system.cpu.kern.mode_good::user 1742 system.cpu.kern.mode_good::idle 169 -system.cpu.kern.mode_switch_good::kernel 0.324237 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.323898 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.080668 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.392853 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 45393996500 2.38% 2.38% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 5132973000 0.27% 2.64% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1860019853500 97.36% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_switch_good::idle 0.080553 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 0.392402 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 45394142000 2.37% 2.37% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 5131394000 0.27% 2.64% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1862948418000 97.36% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4175 # number of times the context was actually changed system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -470,51 +455,51 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu.icache.replacements 927816 # number of replacements -system.cpu.icache.tagsinuse 509.100001 # Cycle average of tags in use -system.cpu.icache.total_refs 55204264 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 928327 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 59.466399 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 32331359000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 509.100001 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.994336 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.994336 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 55204264 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 55204264 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 55204264 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 55204264 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 55204264 # number of overall hits -system.cpu.icache.overall_hits::total 55204264 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 928486 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 928486 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 928486 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 928486 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 928486 # number of overall misses -system.cpu.icache.overall_misses::total 928486 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 12769098000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 12769098000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 12769098000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 12769098000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 12769098000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 12769098000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 56132750 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 56132750 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 56132750 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 56132750 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 56132750 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 56132750 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016541 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.016541 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.016541 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.016541 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.016541 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.016541 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13752.601547 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13752.601547 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13752.601547 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13752.601547 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13752.601547 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13752.601547 # average overall miss latency +system.cpu.icache.replacements 927958 # number of replacements +system.cpu.icache.tagsinuse 509.106403 # Cycle average of tags in use +system.cpu.icache.total_refs 55214738 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 928469 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 59.468585 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 32313596000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 509.106403 # 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average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13751.769277 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13751.769277 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13751.769277 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -523,126 +508,126 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 928486 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 928486 # 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Average occupied blocks per requestor +system.cpu.dcache.occ_blocks::cpu.data 511.980871 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999963 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999963 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 7805620 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7805620 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 5846988 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 5846988 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 182985 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 182985 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 199218 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 199218 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 13652608 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 13652608 # 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miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.120428 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049481 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.049481 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086167 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086167 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.091383 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.091383 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.091383 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.091383 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21412.279782 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 21412.279782 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27558.258918 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 27558.258918 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13321.027008 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13321.027008 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 22774.664079 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 22774.664079 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 22774.664079 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 22774.664079 # average overall miss latency +system.cpu.dcache.ReadReq_hits::cpu.data 7807394 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7807394 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 5848285 # 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number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 31253597000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 31253597000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 31253597000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 31253597000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 8876094 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 8876094 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6152672 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6152672 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200248 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 200248 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 199228 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 199228 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 15028766 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15028766 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15028766 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15028766 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120402 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.120402 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049472 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.049472 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086113 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086113 # 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average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 22761.556260 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 22761.556260 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 22761.556260 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -799,54 +784,54 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 834499 # number of writebacks -system.cpu.dcache.writebacks::total 834499 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1068716 # 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number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2010997000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2010997000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3435232500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 3435232500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120428 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120428 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049481 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049481 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086167 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086167 # 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number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 3435901000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120402 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120402 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049472 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049472 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086113 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086113 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091364 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.091364 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091364 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.091364 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19397.876860 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19397.876860 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25549.422282 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25549.422282 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11272.384598 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11272.384598 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20761.556260 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20761.556260 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20761.556260 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20761.556260 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt index 839e0acab..9a52baa4f 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.912097 # Nu sim_ticks 912096763500 # Number of ticks simulated final_tick 912096763500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1193297 # Simulator instruction rate (inst/s) -host_op_rate 1536367 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 17661410361 # Simulator tick rate (ticks/s) -host_mem_usage 435356 # Number of bytes of host memory used -host_seconds 51.64 # Real time elapsed on the host +host_inst_rate 1025890 # Simulator instruction rate (inst/s) +host_op_rate 1320831 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 15183699019 # Simulator tick rate (ticks/s) +host_mem_usage 392232 # Number of bytes of host memory used +host_seconds 60.07 # Real time elapsed on the host sim_insts 61625970 # Number of instructions simulated sim_ops 79343340 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 39321600 # Number of bytes read from this memory @@ -117,26 +117,13 @@ system.physmem.readPktSize::3 0 # Ca system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes system.physmem.readPktSize::6 0 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 0 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 0 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 0 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 0 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 0 # Categorize write packet sizes system.physmem.rdQLenPdf::0 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 0 # What read queue length does an incoming req see @@ -169,7 +156,6 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see @@ -202,7 +188,6 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see system.physmem.totQLat 0 # Total cycles spent in queuing delays system.physmem.totMemAccLat 0 # Sum of mem lat for all requests system.physmem.totBusLat 0 # Total cycles spent in databus access diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt index 9811be55f..9271f187d 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.332810 # Nu sim_ticks 2332810264000 # Number of ticks simulated final_tick 2332810264000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1101050 # Simulator instruction rate (inst/s) -host_op_rate 1415882 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 42519386287 # Simulator tick rate (ticks/s) -host_mem_usage 435224 # Number of bytes of host memory used -host_seconds 54.86 # Real time elapsed on the host +host_inst_rate 1712706 # Simulator instruction rate (inst/s) +host_op_rate 2202434 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 66139785958 # Simulator tick rate (ticks/s) +host_mem_usage 391204 # Number of bytes of host memory used +host_seconds 35.27 # Real time elapsed on the host sim_insts 60408639 # Number of instructions simulated sim_ops 77681819 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 111673344 # Number of bytes read from this memory @@ -100,26 +100,13 @@ system.physmem.readPktSize::3 0 # Ca system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes system.physmem.readPktSize::6 0 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 0 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 0 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 0 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 0 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 0 # Categorize write packet sizes system.physmem.rdQLenPdf::0 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 0 # What read queue length does an incoming req see @@ -152,7 +139,6 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see @@ -185,7 +171,6 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see system.physmem.totQLat 0 # Total cycles spent in queuing delays system.physmem.totMemAccLat 0 # Sum of mem lat for all requests system.physmem.totBusLat 0 # Total cycles spent in databus access diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt index 13c85b6d1..10f005f3e 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt @@ -1,159 +1,146 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.183003 # Number of seconds simulated -sim_ticks 1183003114000 # Number of ticks simulated -final_tick 1183003114000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.182958 # Number of seconds simulated +sim_ticks 1182958259000 # Number of ticks simulated +final_tick 1182958259000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 673901 # Simulator instruction rate (inst/s) -host_op_rate 858757 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 12970235901 # Simulator tick rate (ticks/s) -host_mem_usage 408748 # Number of bytes of host memory used -host_seconds 91.21 # Real time elapsed on the host -sim_insts 61465824 # Number of instructions simulated -sim_ops 78326377 # Number of ops (including micro ops) simulated +host_inst_rate 332432 # Simulator instruction rate (inst/s) +host_op_rate 423606 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6399087906 # Simulator tick rate (ticks/s) +host_mem_usage 408760 # Number of bytes of host memory used +host_seconds 184.86 # Real time elapsed on the host +sim_insts 61454647 # Number of instructions simulated +sim_ops 78309315 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 51904512 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 379748 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4530164 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 393380 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4709236 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 336668 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4964784 # Number of bytes read from this memory -system.physmem.bytes_read::total 62116388 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 379748 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 336668 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 716416 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4089728 # Number of bytes written to this memory +system.physmem.bytes_read::cpu1.inst 323164 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4815472 # Number of bytes read from this memory +system.physmem.bytes_read::total 62146212 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 393380 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 323164 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 716544 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4116096 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory -system.physmem.bytes_written::total 7117072 # Number of bytes written to this memory +system.physmem.bytes_written::total 7143440 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 6488064 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 12152 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 70856 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 12365 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 73654 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 4 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 5342 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 77601 # Number of read requests responded to by this memory -system.physmem.num_reads::total 6654023 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 63902 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu1.inst 5131 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 75268 # Number of read requests responded to by this memory +system.physmem.num_reads::total 6654489 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 64314 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory -system.physmem.num_writes::total 820738 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 43875212 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 821150 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 43876875 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.dtb.walker 54 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 162 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 321003 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 3829376 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 108 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 332539 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 3980898 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 216 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 284588 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 4196763 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 52507375 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 321003 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 284588 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 605591 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3457073 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 14370 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 2544663 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 6016106 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3457073 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 43875212 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 273183 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 4070703 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 52534577 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 332539 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 273183 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 605722 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3479494 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 14371 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 2544759 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 6038624 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3479494 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 43876875 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 54 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 162 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 321003 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 3843746 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 108 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 332539 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 3995269 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 216 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 284588 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 6741426 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 58523481 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 6654023 # Total number of read requests seen -system.physmem.writeReqs 820738 # Total number of write requests seen -system.physmem.cpureqs 272097 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 425857472 # Total number of bytes read from memory -system.physmem.bytesWritten 52527232 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 62116388 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7117072 # bytesWritten derated as per pkt->getSize() +system.physmem.bw_total::cpu1.inst 273183 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 6615462 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 58573201 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 6654489 # Total number of read requests seen +system.physmem.writeReqs 821150 # Total number of write requests seen +system.physmem.cpureqs 235683 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 425887296 # Total number of bytes read from memory +system.physmem.bytesWritten 52553600 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 62146212 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7143440 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 112 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 11760 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 422267 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 415727 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 415213 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 415818 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 415767 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 415004 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 415107 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 415928 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 415784 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 415110 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 415164 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 415654 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 415632 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 415090 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 415000 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 415646 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 51297 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 51187 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 50850 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 51382 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 51290 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 50625 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 50696 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 51406 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 51898 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 51190 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 51285 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 51758 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 51708 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 51260 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 51138 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 51768 # Track writes on a per bank basis +system.physmem.neitherReadNorWrite 11769 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 422283 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 415708 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 415257 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 415923 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 415836 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 415086 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 415138 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 415982 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 415774 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 415145 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 415183 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 415686 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 415664 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 415065 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 414968 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 415679 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 51312 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 51158 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 50892 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 51475 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 51354 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 50696 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 50735 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 51449 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 51887 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 51225 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 51295 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 51778 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 51726 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 51254 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 51118 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 51796 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 1182998675500 # Total gap between requests +system.physmem.totGap 1182953705000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 6825 # Categorize read packet sizes system.physmem.readPktSize::3 6488064 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 159134 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 756836 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 63902 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 11760 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 570635 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 408572 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 415826 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1537846 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1165216 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1169840 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1140716 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 29537 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 27577 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 48457 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 69066 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 48178 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 5864 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 5691 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 5515 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 5307 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 68 # What read queue length does an incoming req see +system.physmem.readPktSize::6 159600 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 756836 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 64314 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 571059 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 408588 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 415867 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1537787 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1165425 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1169620 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1140545 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 29607 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 27579 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 48460 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 69110 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 48185 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 5882 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 5724 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 5512 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 5352 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 75 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see @@ -169,61 +156,59 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 35513 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 35658 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 35664 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 35672 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 35674 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 35678 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 35678 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 35681 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 35681 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 35684 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 35684 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 35684 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 35684 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 35684 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 35684 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 35684 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 35684 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 35684 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 35684 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 35684 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 35684 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 35684 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 35684 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 172 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 27 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 21 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 13 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 35451 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 35680 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 35684 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 35689 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 35694 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 35695 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 35698 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 35700 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 35702 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 35702 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 35702 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 35702 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 35702 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 35702 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 35702 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 35702 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 35702 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 35702 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 35702 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 35702 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 35702 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 35702 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 35702 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 252 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 146986341539 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 189297882789 # Sum of mem lat for all requests -system.physmem.totBusLat 33269555000 # Total cycles spent in databus access -system.physmem.totBankLat 9041986250 # Total cycles spent in bank access -system.physmem.avgQLat 22090.22 # Average queueing delay per request -system.physmem.avgBankLat 1358.90 # Average bank access latency per request +system.physmem.wrQLenPdf::29 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.totQLat 147016739500 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 189339617000 # Sum of mem lat for all requests +system.physmem.totBusLat 33271885000 # Total cycles spent in databus access +system.physmem.totBankLat 9050992500 # Total cycles spent in bank access +system.physmem.avgQLat 22093.24 # Average queueing delay per request +system.physmem.avgBankLat 1360.16 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 28449.12 # Average memory access latency -system.physmem.avgRdBW 359.98 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 44.40 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 52.51 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 6.02 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 28453.39 # Average memory access latency +system.physmem.avgRdBW 360.02 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 44.43 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 52.53 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 6.04 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 3.16 # Data bus utilization in percentage system.physmem.avgRdQLen 0.16 # Average read queue length over time -system.physmem.avgWrQLen 12.54 # Average write queue length over time -system.physmem.readRowHits 6611960 # Number of row buffer hits during reads -system.physmem.writeRowHits 800133 # Number of row buffer hits during writes +system.physmem.avgWrQLen 12.52 # Average write queue length over time +system.physmem.readRowHits 6612346 # Number of row buffer hits during reads +system.physmem.writeRowHits 800481 # Number of row buffer hits during writes system.physmem.readRowHitRate 99.37 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 97.49 # Row buffer hit rate for writes -system.physmem.avgGap 158265.75 # Average gap between requests +system.physmem.writeRowHitRate 97.48 # Row buffer hit rate for writes +system.physmem.avgGap 158241.15 # Average gap between requests system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory @@ -242,237 +227,237 @@ system.realview.nvmem.bw_inst_read::total 57 # I system.realview.nvmem.bw_total::cpu0.inst 17 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.inst 41 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 57 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 69015 # number of replacements -system.l2c.tagsinuse 53041.665406 # Cycle average of tags in use -system.l2c.total_refs 1678594 # Total number of references to valid blocks. -system.l2c.sampled_refs 134211 # Sample count of references to valid blocks. -system.l2c.avg_refs 12.507127 # Average number of references to valid blocks. +system.l2c.replacements 69480 # number of replacements +system.l2c.tagsinuse 53041.287373 # Cycle average of tags in use +system.l2c.total_refs 1677464 # Total number of references to valid blocks. +system.l2c.sampled_refs 134656 # Sample count of references to valid blocks. +system.l2c.avg_refs 12.457403 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 40191.767552 # Average occupied blocks per requestor +system.l2c.occ_blocks::writebacks 40190.252096 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu0.dtb.walker 0.000406 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.itb.walker 0.003100 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 3723.993423 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 4235.450091 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.dtb.walker 2.742043 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 2826.235882 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 2061.472909 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.613278 # Average percentage of cache occupancy +system.l2c.occ_blocks::cpu0.itb.walker 0.001419 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 3727.107062 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 4236.234020 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.dtb.walker 2.741995 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 2823.629298 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 2061.321078 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.613255 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.056824 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.064628 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.inst 0.056871 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.064640 # Average percentage of cache occupancy system.l2c.occ_percent::cpu1.dtb.walker 0.000042 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.043125 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.031456 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.809352 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 3013 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 1662 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 349398 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 169915 # 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average ReadReq mshr uncacheable latency @@ -656,27 +641,27 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 5883553 # DTB read hits -system.cpu0.dtb.read_misses 2148 # DTB read misses -system.cpu0.dtb.write_hits 4842455 # DTB write hits -system.cpu0.dtb.write_misses 405 # DTB write misses +system.cpu0.dtb.read_hits 7073604 # DTB read hits +system.cpu0.dtb.read_misses 3763 # DTB read misses +system.cpu0.dtb.write_hits 5658971 # DTB write hits +system.cpu0.dtb.write_misses 806 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 1536 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 1807 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 91 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 143 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 203 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 5885701 # DTB read accesses -system.cpu0.dtb.write_accesses 4842860 # DTB write accesses +system.cpu0.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 7077367 # DTB read accesses +system.cpu0.dtb.write_accesses 5659777 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 10726008 # DTB hits -system.cpu0.dtb.misses 2553 # DTB misses -system.cpu0.dtb.accesses 10728561 # DTB accesses -system.cpu0.itb.inst_hits 24779849 # ITB inst hits -system.cpu0.itb.inst_misses 1350 # ITB inst misses +system.cpu0.dtb.hits 12732575 # DTB hits +system.cpu0.dtb.misses 4569 # DTB misses +system.cpu0.dtb.accesses 12737144 # DTB accesses +system.cpu0.itb.inst_hits 29573368 # ITB inst hits +system.cpu0.itb.inst_misses 2205 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -685,86 +670,86 @@ system.cpu0.itb.flush_tlb 4 # Nu system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1347 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1332 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 24781199 # ITB inst accesses -system.cpu0.itb.hits 24779849 # DTB hits -system.cpu0.itb.misses 1350 # DTB misses -system.cpu0.itb.accesses 24781199 # DTB accesses -system.cpu0.numCycles 2364565551 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 29575573 # ITB inst accesses +system.cpu0.itb.hits 29573368 # DTB hits +system.cpu0.itb.misses 2205 # DTB misses +system.cpu0.itb.accesses 29575573 # DTB accesses +system.cpu0.numCycles 2365916518 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 24381823 # Number of instructions committed -system.cpu0.committedOps 31476006 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 28075203 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 4364 # Number of float alu accesses -system.cpu0.num_func_calls 1070639 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 3752398 # number of instructions that are conditional controls -system.cpu0.num_int_insts 28075203 # number of integer instructions -system.cpu0.num_fp_insts 4364 # number of float instructions -system.cpu0.num_int_register_reads 160702802 # number of times the integer registers were read -system.cpu0.num_int_register_writes 30522196 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 3980 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 384 # number of times the floating registers were written -system.cpu0.num_mem_refs 11318426 # number of memory refs -system.cpu0.num_load_insts 6163151 # Number of load instructions -system.cpu0.num_store_insts 5155275 # Number of store instructions -system.cpu0.num_idle_cycles 2243464250.276980 # Number of idle cycles -system.cpu0.num_busy_cycles 121101300.723020 # Number of busy cycles -system.cpu0.not_idle_fraction 0.051215 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.948785 # Percentage of idle cycles +system.cpu0.committedInsts 28875412 # Number of instructions committed +system.cpu0.committedOps 37222765 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 33109279 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 3860 # Number of float alu accesses +system.cpu0.num_func_calls 1241807 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4373656 # number of instructions that are conditional controls +system.cpu0.num_int_insts 33109279 # number of integer instructions +system.cpu0.num_fp_insts 3860 # number of float instructions +system.cpu0.num_int_register_reads 190112848 # number of times the integer registers were read +system.cpu0.num_int_register_writes 36234022 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 3022 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 840 # number of times the floating registers were written +system.cpu0.num_mem_refs 13400902 # number of memory refs +system.cpu0.num_load_insts 7411207 # Number of load instructions +system.cpu0.num_store_insts 5989695 # Number of store instructions +system.cpu0.num_idle_cycles 2224988060.360119 # Number of idle cycles +system.cpu0.num_busy_cycles 140928457.639881 # Number of busy cycles +system.cpu0.not_idle_fraction 0.059566 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.940434 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 38919 # number of quiesce instructions executed -system.cpu0.icache.replacements 354669 # number of replacements -system.cpu0.icache.tagsinuse 509.601981 # Cycle average of tags in use -system.cpu0.icache.total_refs 24424650 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 355181 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 68.766770 # Average number of references to valid blocks. +system.cpu0.kern.inst.quiesce 46697 # number of quiesce instructions executed +system.cpu0.icache.replacements 425482 # number of replacements +system.cpu0.icache.tagsinuse 509.601890 # Cycle average of tags in use +system.cpu0.icache.total_refs 29147356 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 425994 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 68.421987 # Average number of references to valid blocks. system.cpu0.icache.warmup_cycle 74995953000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 509.601981 # Average occupied blocks per requestor +system.cpu0.icache.occ_blocks::cpu0.inst 509.601890 # Average occupied blocks per requestor system.cpu0.icache.occ_percent::cpu0.inst 0.995316 # Average percentage of cache occupancy system.cpu0.icache.occ_percent::total 0.995316 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 24424650 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 24424650 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 24424650 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 24424650 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 24424650 # number of overall hits -system.cpu0.icache.overall_hits::total 24424650 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 355182 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 355182 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 355182 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 355182 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 355182 # number of overall misses -system.cpu0.icache.overall_misses::total 355182 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 4877233500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 4877233500 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 4877233500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 4877233500 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 4877233500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 4877233500 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 24779832 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 24779832 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 24779832 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 24779832 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 24779832 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 24779832 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014334 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.014334 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014334 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.014334 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014334 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.014334 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13731.646029 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13731.646029 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13731.646029 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13731.646029 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13731.646029 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13731.646029 # average overall miss latency +system.cpu0.icache.ReadReq_hits::cpu0.inst 29147356 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 29147356 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 29147356 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 29147356 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 29147356 # number of overall hits +system.cpu0.icache.overall_hits::total 29147356 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 425995 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 425995 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 425995 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 425995 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 425995 # number of overall misses +system.cpu0.icache.overall_misses::total 425995 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5809941500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 5809941500 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 5809941500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 5809941500 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 5809941500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 5809941500 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 29573351 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 29573351 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 29573351 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 29573351 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 29573351 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 29573351 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014405 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.014405 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014405 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.014405 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014405 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.014405 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13638.520405 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13638.520405 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13638.520405 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13638.520405 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13638.520405 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13638.520405 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -773,120 +758,120 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 355182 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 355182 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 355182 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 355182 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 355182 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 355182 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4166869500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 4166869500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4166869500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 4166869500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4166869500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 4166869500 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 425995 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 425995 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 425995 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 425995 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 425995 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 425995 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4957951500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 4957951500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4957951500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 4957951500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4957951500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 4957951500 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 299599000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 299599000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 299599000 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 299599000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014334 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014334 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014334 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.014334 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014334 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.014334 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11731.646029 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11731.646029 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11731.646029 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11731.646029 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11731.646029 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11731.646029 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014405 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014405 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014405 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.014405 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014405 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.014405 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11638.520405 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11638.520405 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11638.520405 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11638.520405 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11638.520405 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11638.520405 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 279602 # number of replacements -system.cpu0.dcache.tagsinuse 452.516720 # Cycle average of tags in use -system.cpu0.dcache.total_refs 10326636 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 279931 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 36.889934 # Average number of references to valid blocks. +system.cpu0.dcache.replacements 331027 # number of replacements +system.cpu0.dcache.tagsinuse 453.640914 # Cycle average of tags in use +system.cpu0.dcache.total_refs 12276777 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 331539 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 37.029662 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 473552000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 452.516720 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.883822 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.883822 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 5477555 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 5477555 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 4571792 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 4571792 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 129360 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 129360 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 130225 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 130225 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 10049347 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 10049347 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 10049347 # number of overall hits -system.cpu0.dcache.overall_hits::total 10049347 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 191756 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 191756 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 126522 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 126522 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8645 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 8645 # 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number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 138005 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 137928 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 137928 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 10367625 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 10367625 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 10367625 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 10367625 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.033824 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.033824 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.026929 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.026929 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.062643 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.062643 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.055848 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.055848 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.030699 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.030699 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.030699 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.030699 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13969.414256 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 13969.414256 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 30114.486018 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 30114.486018 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 9098.380567 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9098.380567 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5920.550435 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5920.550435 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 20387.409749 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 20387.409749 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 20387.409749 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 20387.409749 # average overall miss latency +system.cpu0.dcache.occ_blocks::cpu0.data 453.640914 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.886017 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.886017 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 6603200 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6603200 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 5353855 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 5353855 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 147936 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 147936 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 149699 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 149699 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 11957055 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 11957055 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 11957055 # number of overall hits +system.cpu0.dcache.overall_hits::total 11957055 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 228068 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 228068 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 141674 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 141674 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9338 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 9338 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7490 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 7490 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 369742 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 369742 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 369742 # number of overall misses +system.cpu0.dcache.overall_misses::total 369742 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 3146768000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 3146768000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 4132891500 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 4132891500 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 88585500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 88585500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 44513500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 44513500 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 7279659500 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 7279659500 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 7279659500 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 7279659500 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 6831268 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 6831268 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5495529 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5495529 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 157274 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 157274 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 157189 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 157189 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 12326797 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 12326797 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 12326797 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 12326797 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.033386 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.033386 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.025780 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.025780 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059374 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059374 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.047650 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.047650 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.029995 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.029995 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029995 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.029995 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13797.498992 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 13797.498992 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 29171.841693 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 29171.841693 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 9486.560291 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9486.560291 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5943.057410 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5943.057410 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19688.484132 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 19688.484132 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 19688.484132 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 19688.484132 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -895,66 +880,66 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 257540 # number of writebacks -system.cpu0.dcache.writebacks::total 257540 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 191756 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 191756 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 126522 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 126522 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8645 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8645 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7700 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 7700 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 318278 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 318278 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 318278 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 318278 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2295207000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2295207000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 3557101000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 3557101000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 61365500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 61365500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 30208000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 30208000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.writebacks::writebacks 306714 # number of writebacks +system.cpu0.dcache.writebacks::total 306714 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 228068 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 228068 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 141674 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 141674 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9338 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9338 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7487 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 7487 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 369742 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 369742 # 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number of StoreCondReq MSHR miss cycles system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1000 # number of StoreCondFailReq MSHR miss cycles system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 5852308000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 5852308000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 5852308000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 5852308000 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 12211047000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 12211047000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1122364500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1122364500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 13333411500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 13333411500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033824 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033824 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.026929 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.026929 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.062643 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.062643 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.055826 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.055826 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.030699 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.030699 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.030699 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.030699 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11969.414256 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11969.414256 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 28114.486018 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 28114.486018 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7098.380567 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7098.380567 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3923.116883 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3923.116883 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6540175500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 6540175500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6540175500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 6540175500 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13562243000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13562243000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1128446000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1128446000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14690689000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14690689000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033386 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033386 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025780 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.025780 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059374 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059374 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.047631 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.047631 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029995 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.029995 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029995 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.029995 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11797.498992 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11797.498992 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 27171.841693 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 27171.841693 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7486.560291 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7486.560291 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3945.705890 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3945.705890 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18387.409749 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18387.409749 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 18387.409749 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18387.409749 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 17688.484132 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17688.484132 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 17688.484132 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17688.484132 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -964,27 +949,27 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 9504194 # DTB read hits -system.cpu1.dtb.read_misses 5263 # DTB read misses -system.cpu1.dtb.write_hits 6646220 # DTB write hits -system.cpu1.dtb.write_misses 1833 # DTB write misses +system.cpu1.dtb.read_hits 8309714 # DTB read hits +system.cpu1.dtb.read_misses 3643 # DTB read misses +system.cpu1.dtb.write_hits 5826503 # DTB write hits +system.cpu1.dtb.write_misses 1435 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 2237 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 1965 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 191 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 140 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 249 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 9509457 # DTB read accesses -system.cpu1.dtb.write_accesses 6648053 # DTB write accesses +system.cpu1.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 8313357 # DTB read accesses +system.cpu1.dtb.write_accesses 5827938 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 16150414 # DTB hits -system.cpu1.dtb.misses 7096 # DTB misses -system.cpu1.dtb.accesses 16157510 # DTB accesses -system.cpu1.itb.inst_hits 37994467 # ITB inst hits -system.cpu1.itb.inst_misses 3017 # ITB inst misses +system.cpu1.dtb.hits 14136217 # DTB hits +system.cpu1.dtb.misses 5078 # DTB misses +system.cpu1.dtb.accesses 14141295 # DTB accesses +system.cpu1.itb.inst_hits 33189716 # ITB inst hits +system.cpu1.itb.inst_misses 2171 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -993,86 +978,86 @@ system.cpu1.itb.flush_tlb 4 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1458 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1495 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 37997484 # ITB inst accesses -system.cpu1.itb.hits 37994467 # DTB hits -system.cpu1.itb.misses 3017 # DTB misses -system.cpu1.itb.accesses 37997484 # DTB accesses -system.cpu1.numCycles 2366006228 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 33191887 # ITB inst accesses +system.cpu1.itb.hits 33189716 # DTB hits +system.cpu1.itb.misses 2171 # DTB misses +system.cpu1.itb.accesses 33191887 # DTB accesses +system.cpu1.numCycles 2364475282 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 37084001 # Number of instructions committed -system.cpu1.committedOps 46850371 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 42360540 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 5457 # Number of float alu accesses -system.cpu1.num_func_calls 1133542 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 4355119 # number of instructions that are conditional controls -system.cpu1.num_int_insts 42360540 # number of integer instructions -system.cpu1.num_fp_insts 5457 # number of float instructions -system.cpu1.num_int_register_reads 243148462 # number of times the integer registers were read -system.cpu1.num_int_register_writes 45181015 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 3577 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 1884 # number of times the floating registers were written -system.cpu1.num_mem_refs 16764021 # number of memory refs -system.cpu1.num_load_insts 9884261 # Number of load instructions -system.cpu1.num_store_insts 6879760 # Number of store instructions -system.cpu1.num_idle_cycles 1849775265.196436 # Number of idle cycles -system.cpu1.num_busy_cycles 516230962.803564 # Number of busy cycles -system.cpu1.not_idle_fraction 0.218187 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.781813 # Percentage of idle cycles +system.cpu1.committedInsts 32579235 # Number of instructions committed +system.cpu1.committedOps 41086550 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 37310899 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 6793 # Number of float alu accesses +system.cpu1.num_func_calls 962009 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 3732730 # number of instructions that are conditional controls +system.cpu1.num_int_insts 37310899 # number of integer instructions +system.cpu1.num_fp_insts 6793 # number of float instructions +system.cpu1.num_int_register_reads 213650265 # number of times the integer registers were read +system.cpu1.num_int_register_writes 39453467 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 4535 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 2260 # number of times the floating registers were written +system.cpu1.num_mem_refs 14673985 # number of memory refs +system.cpu1.num_load_insts 8631614 # Number of load instructions +system.cpu1.num_store_insts 6042371 # Number of store instructions +system.cpu1.num_idle_cycles 1868339828.826306 # Number of idle cycles +system.cpu1.num_busy_cycles 496135453.173694 # Number of busy cycles +system.cpu1.not_idle_fraction 0.209829 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.790171 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 51687 # number of quiesce instructions executed -system.cpu1.icache.replacements 540342 # number of replacements -system.cpu1.icache.tagsinuse 478.756805 # Cycle average of tags in use -system.cpu1.icache.total_refs 37453609 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 540854 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 69.249019 # Average number of references to valid blocks. +system.cpu1.kern.inst.quiesce 43883 # number of quiesce instructions executed +system.cpu1.icache.replacements 469209 # number of replacements +system.cpu1.icache.tagsinuse 478.755545 # Cycle average of tags in use +system.cpu1.icache.total_refs 32719991 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 469721 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 69.658353 # Average number of references to valid blocks. system.cpu1.icache.warmup_cycle 92137748500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 478.756805 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.935072 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.935072 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 37453609 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 37453609 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 37453609 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 37453609 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 37453609 # number of overall hits -system.cpu1.icache.overall_hits::total 37453609 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 540854 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 540854 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 540854 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 540854 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 540854 # number of overall misses -system.cpu1.icache.overall_misses::total 540854 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7301553500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 7301553500 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 7301553500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 7301553500 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 7301553500 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 7301553500 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 37994463 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 37994463 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 37994463 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 37994463 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 37994463 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 37994463 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.014235 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.014235 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.014235 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.014235 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.014235 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.014235 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13500.045299 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13500.045299 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13500.045299 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13500.045299 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13500.045299 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13500.045299 # average overall miss latency +system.cpu1.icache.occ_blocks::cpu1.inst 478.755545 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.935069 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.935069 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 32719991 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 32719991 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 32719991 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 32719991 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 32719991 # number of overall hits +system.cpu1.icache.overall_hits::total 32719991 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 469721 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 469721 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 469721 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 469721 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 469721 # number of overall misses +system.cpu1.icache.overall_misses::total 469721 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6363755000 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 6363755000 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 6363755000 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 6363755000 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 6363755000 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 6363755000 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 33189712 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 33189712 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 33189712 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 33189712 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 33189712 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 33189712 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.014153 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.014153 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.014153 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.014153 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.014153 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.014153 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13547.946547 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13547.946547 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13547.946547 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13547.946547 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13547.946547 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13547.946547 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1081,120 +1066,120 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # 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number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 6219845500 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 469721 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 469721 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 469721 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 469721 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 469721 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 469721 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5424313000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 5424313000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5424313000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 5424313000 # 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mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.014153 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.014153 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.014153 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.014153 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11547.946547 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11547.946547 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11547.946547 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11547.946547 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11547.946547 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11547.946547 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 343957 # number of replacements -system.cpu1.dcache.tagsinuse 473.088021 # Cycle average of tags in use -system.cpu1.dcache.total_refs 13916365 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 344469 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 40.399470 # Average number of references to valid blocks. +system.cpu1.dcache.replacements 292184 # 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miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.105151 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.105151 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.087766 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.087766 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.026491 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.026491 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.026491 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.026491 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12738.492987 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 12738.492987 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 29258.525014 # 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Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.922136 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.922136 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 6945060 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 6945060 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 4826351 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 4826351 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 81758 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 81758 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 82709 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 82709 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 11771411 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 11771411 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 11771411 # number of overall hits +system.cpu1.dcache.overall_hits::total 11771411 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 170725 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 170725 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 149867 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 149867 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11052 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 11052 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10028 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 10028 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 320592 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 320592 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 320592 # number of overall misses +system.cpu1.dcache.overall_misses::total 320592 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2168241500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 2168241500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 4524943000 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 4524943000 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 92270500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 92270500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 51657000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 51657000 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 6693184500 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 6693184500 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 6693184500 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 6693184500 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 7115785 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 7115785 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 4976218 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 4976218 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 92810 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 92810 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 92737 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 92737 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 12092003 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 12092003 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 12092003 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 12092003 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.023992 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.023992 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.030117 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.030117 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.119082 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.119082 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.108134 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.108134 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.026513 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.026513 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.026513 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.026513 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12700.199151 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 12700.199151 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 30193.057845 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 30193.057845 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 8348.760405 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 8348.760405 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5151.276426 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5151.276426 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20877.578043 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 20877.578043 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20877.578043 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 20877.578043 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1203,66 +1188,66 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 315665 # number of writebacks -system.cpu1.dcache.writebacks::total 315665 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 207178 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 207178 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 165249 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 165249 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11790 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11790 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 9830 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 9830 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 372427 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 372427 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 372427 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 372427 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2224779500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2224779500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 4504444000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 4504444000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 79540000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 79540000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 30847000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 30847000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.writebacks::writebacks 265550 # number of writebacks +system.cpu1.dcache.writebacks::total 265550 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 170725 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 170725 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 149867 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 149867 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11052 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11052 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10024 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 10024 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 320592 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 320592 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 320592 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 320592 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1826791500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1826791500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 4225209000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 4225209000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 70166500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 70166500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 31611000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 31611000 # number of StoreCondReq MSHR miss cycles system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1000 # number of StoreCondFailReq MSHR miss cycles system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 6729223500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 6729223500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 6729223500 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 6729223500 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 169996101000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 169996101000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 17674592500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 17674592500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 187670693500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 187670693500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025015 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.025015 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.028607 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028607 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.105151 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.105151 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.087730 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.087730 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026491 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.026491 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026491 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.026491 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10738.492987 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10738.492987 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 27258.525014 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 27258.525014 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6746.395250 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6746.395250 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3138.046796 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3138.046796 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 6052000500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 6052000500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 6052000500 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 6052000500 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168642802500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168642802500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 17668343500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 17668343500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 186311146000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 186311146000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.023992 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.023992 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.030117 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.030117 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.119082 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.119082 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.108091 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.108091 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026513 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.026513 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026513 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.026513 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10700.199151 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10700.199151 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 28193.057845 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 28193.057845 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6348.760405 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6348.760405 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3153.531524 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3153.531524 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18068.570485 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18068.570485 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18068.570485 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18068.570485 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18877.578043 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18877.578043 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18877.578043 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18877.578043 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1284,10 +1269,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 509652310593 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 509652310593 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 509652310593 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 509652310593 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 509685021664 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 509685021664 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 509685021664 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 509685021664 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt index 73585121b..4975edc6e 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt @@ -1,61 +1,61 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.603665 # Number of seconds simulated -sim_ticks 2603664815000 # Number of ticks simulated -final_tick 2603664815000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.603674 # Number of seconds simulated +sim_ticks 2603674284000 # Number of ticks simulated +final_tick 2603674284000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 536000 # Simulator instruction rate (inst/s) -host_op_rate 682052 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 23183028791 # Simulator tick rate (ticks/s) -host_mem_usage 404656 # Number of bytes of host memory used -host_seconds 112.31 # Real time elapsed on the host -sim_insts 60197643 # Number of instructions simulated -sim_ops 76600583 # Number of ops (including micro ops) simulated +host_inst_rate 271279 # Simulator instruction rate (inst/s) +host_op_rate 345198 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 11733407598 # Simulator tick rate (ticks/s) +host_mem_usage 403640 # Number of bytes of host memory used +host_seconds 221.90 # Real time elapsed on the host +sim_insts 60197457 # Number of instructions simulated +sim_ops 76600355 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 122683392 # Number of bytes read from this memory system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 704800 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9050128 # Number of bytes read from this memory -system.physmem.bytes_read::total 132438832 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 704800 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 704800 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3677504 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.inst 705120 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9050192 # Number of bytes read from this memory +system.physmem.bytes_read::total 132439216 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 705120 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 705120 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3677632 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6693576 # Number of bytes written to this memory +system.physmem.bytes_written::total 6693704 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15335424 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.dtb.walker 5 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 3 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 17215 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 141442 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15494089 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 57461 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.inst 17220 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 141443 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15494095 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 57463 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 811479 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47119503 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 811481 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47119332 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.dtb.walker 123 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 74 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 270695 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3475919 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 50866314 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 270695 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 270695 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1412434 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1158395 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2570829 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1412434 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47119503 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 270817 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3475931 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 50866276 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 270817 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 270817 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1412478 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1158391 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2570868 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1412478 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47119332 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 123 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 74 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 270695 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4634314 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53437143 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15494089 # Total number of read requests seen -system.physmem.writeReqs 811479 # Total number of write requests seen -system.physmem.cpureqs 213984 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 991621696 # Total number of bytes read from memory -system.physmem.bytesWritten 51934656 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 132438832 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 6693576 # bytesWritten derated as per pkt->getSize() +system.physmem.bw_total::cpu.inst 270817 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4634322 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53437145 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15494095 # Total number of read requests seen +system.physmem.writeReqs 811481 # Total number of write requests seen +system.physmem.cpureqs 213992 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 991622080 # Total number of bytes read from memory +system.physmem.bytesWritten 51934784 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 132439216 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 6693704 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 336 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 4510 # Reqs where no action is needed system.physmem.perBankRdReqs::0 974844 # Track reads on a per bank basis @@ -66,13 +66,13 @@ system.physmem.perBankRdReqs::4 968387 # Tr system.physmem.perBankRdReqs::5 967635 # Track reads on a per bank basis system.physmem.perBankRdReqs::6 967737 # Track reads on a per bank basis system.physmem.perBankRdReqs::7 968249 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 968097 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 968100 # Track reads on a per bank basis system.physmem.perBankRdReqs::9 967668 # Track reads on a per bank basis system.physmem.perBankRdReqs::10 967710 # Track reads on a per bank basis system.physmem.perBankRdReqs::11 968007 # Track reads on a per bank basis system.physmem.perBankRdReqs::12 968101 # Track reads on a per bank basis system.physmem.perBankRdReqs::13 967570 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 967431 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 967434 # Track reads on a per bank basis system.physmem.perBankRdReqs::15 968087 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 50753 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 50356 # Track writes on a per bank basis @@ -82,61 +82,48 @@ system.physmem.perBankWrReqs::4 50784 # Tr system.physmem.perBankWrReqs::5 50139 # Track writes on a per bank basis system.physmem.perBankWrReqs::6 50212 # Track writes on a per bank basis system.physmem.perBankWrReqs::7 50710 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 51141 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 51142 # Track writes on a per bank basis system.physmem.perBankWrReqs::9 50687 # Track writes on a per bank basis system.physmem.perBankWrReqs::10 50724 # Track writes on a per bank basis system.physmem.perBankWrReqs::11 51058 # Track writes on a per bank basis system.physmem.perBankWrReqs::12 51155 # Track writes on a per bank basis system.physmem.perBankWrReqs::13 50650 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 50586 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 50587 # Track writes on a per bank basis system.physmem.perBankWrReqs::15 51214 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 2603660455000 # Total gap between requests +system.physmem.totGap 2603669924000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 6652 # Categorize read packet sizes system.physmem.readPktSize::3 15335424 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 152013 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 754018 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 57461 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 4510 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 1115727 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 960917 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 976016 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3645957 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2755251 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2758222 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2725008 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 64130 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 62311 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 112850 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 163186 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 112416 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 10693 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 10526 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 10327 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 10120 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 96 # What read queue length does an incoming req see +system.physmem.readPktSize::6 152019 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 754018 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 57463 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 1115862 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 960938 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 976049 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3645924 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2755202 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2757935 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2724600 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 64133 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 62351 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 112886 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 163253 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 112534 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 10838 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 10625 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 10371 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 10165 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 93 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see @@ -152,15 +139,14 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 35112 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 35261 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 35264 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 35271 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 35275 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 35275 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 35279 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 35281 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 35038 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 35268 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 35271 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 35273 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 35278 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 35278 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 35280 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 35280 # What write queue length does an incoming req see system.physmem.wrQLenPdf::8 35282 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 35282 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 35282 # What write queue length does an incoming req see @@ -169,44 +155,43 @@ system.physmem.wrQLenPdf::12 35282 # Wh system.physmem.wrQLenPdf::13 35282 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 35282 # What write queue length does an incoming req see system.physmem.wrQLenPdf::15 35282 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 35281 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 35281 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 35282 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 35282 # What write queue length does an incoming req see system.physmem.wrQLenPdf::18 35281 # What write queue length does an incoming req see system.physmem.wrQLenPdf::19 35281 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 35281 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 35281 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 35281 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 170 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 21 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 341507754589 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 436421735839 # Sum of mem lat for all requests -system.physmem.totBusLat 77468765000 # Total cycles spent in databus access -system.physmem.totBankLat 17445216250 # Total cycles spent in bank access -system.physmem.avgQLat 22041.64 # Average queueing delay per request -system.physmem.avgBankLat 1125.95 # Average bank access latency per request +system.physmem.totQLat 341488215750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 436408620750 # Sum of mem lat for all requests +system.physmem.totBusLat 77468795000 # Total cycles spent in databus access +system.physmem.totBankLat 17451610000 # Total cycles spent in bank access +system.physmem.avgQLat 22040.37 # Average queueing delay per request +system.physmem.avgBankLat 1126.36 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 28167.59 # Average memory access latency -system.physmem.avgRdBW 380.86 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 28166.74 # Average memory access latency +system.physmem.avgRdBW 380.85 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 19.95 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 50.87 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 2.57 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 3.13 # Data bus utilization in percentage system.physmem.avgRdQLen 0.17 # Average read queue length over time -system.physmem.avgWrQLen 12.39 # Average write queue length over time -system.physmem.readRowHits 15418905 # Number of row buffer hits during reads -system.physmem.writeRowHits 794060 # Number of row buffer hits during writes +system.physmem.avgWrQLen 12.40 # Average write queue length over time +system.physmem.readRowHits 15418728 # Number of row buffer hits during reads +system.physmem.writeRowHits 794030 # Number of row buffer hits during writes system.physmem.readRowHitRate 99.52 # Row buffer hit rate for reads system.physmem.writeRowHitRate 97.85 # Row buffer hit rate for writes -system.physmem.avgGap 159679.22 # Average gap between requests +system.physmem.avgGap 159679.73 # Average gap between requests system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory @@ -227,9 +212,9 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 14995667 # DTB read hits +system.cpu.dtb.read_hits 14995645 # DTB read hits system.cpu.dtb.read_misses 7332 # DTB read misses -system.cpu.dtb.write_hits 11230865 # DTB write hits +system.cpu.dtb.write_hits 11230857 # DTB write hits system.cpu.dtb.write_misses 2203 # DTB write misses system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA @@ -240,13 +225,13 @@ system.cpu.dtb.align_faults 0 # Nu system.cpu.dtb.prefetch_faults 184 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 15002999 # DTB read accesses -system.cpu.dtb.write_accesses 11233068 # DTB write accesses +system.cpu.dtb.read_accesses 15002977 # DTB read accesses +system.cpu.dtb.write_accesses 11233060 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 26226532 # DTB hits +system.cpu.dtb.hits 26226502 # DTB hits system.cpu.dtb.misses 9535 # DTB misses -system.cpu.dtb.accesses 26236067 # DTB accesses -system.cpu.itb.inst_hits 61491584 # ITB inst hits +system.cpu.dtb.accesses 26236037 # DTB accesses +system.cpu.itb.inst_hits 61491397 # ITB inst hits system.cpu.itb.inst_misses 4471 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses @@ -263,79 +248,79 @@ system.cpu.itb.domain_faults 0 # Nu system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 61496055 # ITB inst accesses -system.cpu.itb.hits 61491584 # DTB hits +system.cpu.itb.inst_accesses 61495868 # ITB inst accesses +system.cpu.itb.hits 61491397 # DTB hits system.cpu.itb.misses 4471 # DTB misses -system.cpu.itb.accesses 61496055 # DTB accesses -system.cpu.numCycles 5207329630 # number of cpu cycles simulated +system.cpu.itb.accesses 61495868 # DTB accesses +system.cpu.numCycles 5207348568 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 60197643 # Number of instructions committed -system.cpu.committedOps 76600583 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 68868344 # Number of integer alu accesses +system.cpu.committedInsts 60197457 # Number of instructions committed +system.cpu.committedOps 76600355 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 68868122 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses -system.cpu.num_func_calls 2139730 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 7947806 # number of instructions that are conditional controls -system.cpu.num_int_insts 68868344 # number of integer instructions +system.cpu.num_func_calls 2139722 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 7947784 # number of instructions that are conditional controls +system.cpu.num_int_insts 68868122 # number of integer instructions system.cpu.num_fp_insts 10269 # number of float instructions -system.cpu.num_int_register_reads 394756284 # number of times the integer registers were read -system.cpu.num_int_register_writes 74176271 # number of times the integer registers were written +system.cpu.num_int_register_reads 394755172 # number of times the integer registers were read +system.cpu.num_int_register_writes 74176013 # number of times the integer registers were written system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written -system.cpu.num_mem_refs 27393912 # number of memory refs -system.cpu.num_load_insts 15659685 # Number of load instructions -system.cpu.num_store_insts 11734227 # Number of store instructions -system.cpu.num_idle_cycles 4579092870.576241 # Number of idle cycles -system.cpu.num_busy_cycles 628236759.423759 # Number of busy cycles -system.cpu.not_idle_fraction 0.120645 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.879355 # Percentage of idle cycles +system.cpu.num_mem_refs 27393871 # number of memory refs +system.cpu.num_load_insts 15659652 # Number of load instructions +system.cpu.num_store_insts 11734219 # Number of store instructions +system.cpu.num_idle_cycles 4579092042.576241 # Number of idle cycles +system.cpu.num_busy_cycles 628256525.423759 # Number of busy cycles +system.cpu.not_idle_fraction 0.120648 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.879352 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 83000 # number of quiesce instructions executed -system.cpu.icache.replacements 855486 # number of replacements -system.cpu.icache.tagsinuse 510.979431 # Cycle average of tags in use -system.cpu.icache.total_refs 60635586 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 855998 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 70.836130 # Average number of references to valid blocks. +system.cpu.icache.replacements 855484 # number of replacements +system.cpu.icache.tagsinuse 510.979435 # Cycle average of tags in use +system.cpu.icache.total_refs 60635401 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 855996 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 70.836080 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 18713179000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 510.979431 # Average occupied blocks per requestor +system.cpu.icache.occ_blocks::cpu.inst 510.979435 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.998007 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.998007 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 60635586 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 60635586 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 60635586 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 60635586 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 60635586 # number of overall hits -system.cpu.icache.overall_hits::total 60635586 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 855998 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 855998 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 855998 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 855998 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 855998 # number of overall misses -system.cpu.icache.overall_misses::total 855998 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 11569304000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 11569304000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 11569304000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 11569304000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 11569304000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 11569304000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 61491584 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 61491584 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 61491584 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 61491584 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 61491584 # 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average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 37917.666667 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40563.193512 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 41910.727153 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41214.277319 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10033.851130 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10033.851130 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 33376.060683 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 33376.060683 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 50751 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 37917.666667 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40563.193512 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 33964.302436 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34420.329838 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 50751 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 37917.666667 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40563.193512 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 33964.302436 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34420.329838 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -615,79 +600,79 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 627291 # number of replacements +system.cpu.dcache.replacements 627296 # number of replacements system.cpu.dcache.tagsinuse 511.912639 # Cycle average of tags in use -system.cpu.dcache.total_refs 23655046 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 627803 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 37.679090 # Average number of references to valid blocks. +system.cpu.dcache.total_refs 23655010 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 627808 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 37.678733 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 472186000 # Cycle when the warmup percentage was hit. system.cpu.dcache.occ_blocks::cpu.data 511.912639 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999829 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999829 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 13195134 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13195134 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 9973055 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 9973055 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 236278 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 236278 # number of LoadLockedReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 13195118 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13195118 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 9973036 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 9973036 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 236277 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 236277 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 247678 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 247678 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 23168189 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 23168189 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 23168189 # number of overall hits -system.cpu.dcache.overall_hits::total 23168189 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 368792 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 368792 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 250511 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 250511 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 11401 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 11401 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 619303 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 619303 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 619303 # number of overall misses -system.cpu.dcache.overall_misses::total 619303 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5222508000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5222508000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 8035214500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 8035214500 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 155940000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 155940000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 13257722500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 13257722500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 13257722500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 13257722500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 13563926 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 13563926 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 10223566 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 10223566 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 23168154 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 23168154 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 23168154 # number of overall hits +system.cpu.dcache.overall_hits::total 23168154 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 368785 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 368785 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 250522 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 250522 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 11402 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 11402 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 619307 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 619307 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 619307 # number of overall misses +system.cpu.dcache.overall_misses::total 619307 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5224078000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5224078000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 8042704500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 8042704500 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 155711000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 155711000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 13266782500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 13266782500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 13266782500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 13266782500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 13563903 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 13563903 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 10223558 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 10223558 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247679 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 247679 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 247678 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 247678 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 23787492 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 23787492 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 23787492 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 23787492 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 23787461 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 23787461 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 23787461 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 23787461 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.027189 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.027189 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024503 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.024503 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046031 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046031 # miss rate for LoadLockedReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024504 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.024504 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046035 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046035 # miss rate for LoadLockedReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.026035 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.026035 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.026035 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.026035 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14161.120632 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14161.120632 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 32075.296095 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 32075.296095 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13677.747566 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13677.747566 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 21407.489549 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 21407.489549 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 21407.489549 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 21407.489549 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14165.646650 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14165.646650 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 32103.785296 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 32103.785296 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13656.463778 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13656.463778 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 21421.980536 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 21421.980536 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 21421.980536 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 21421.980536 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -696,54 +681,54 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 596039 # number of writebacks -system.cpu.dcache.writebacks::total 596039 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 368792 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 368792 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250511 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 250511 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11401 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 11401 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 619303 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 619303 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 619303 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 619303 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4484924000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4484924000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7534192500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 7534192500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 133138000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 133138000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12019116500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 12019116500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12019116500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 12019116500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182082004500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182082004500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 18708047000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 18708047000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 200790051500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 200790051500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.writebacks::writebacks 596040 # number of writebacks +system.cpu.dcache.writebacks::total 596040 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 368785 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 368785 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250522 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 250522 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11402 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 11402 # number of LoadLockedReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 619307 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 619307 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 619307 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 619307 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4486508000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4486508000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7541660500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 7541660500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 132907000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 132907000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12028168500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 12028168500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12028168500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12028168500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182082624500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182082624500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 18709226000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 18709226000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 200791850500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 200791850500 # number of overall MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027189 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027189 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024503 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024503 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.046031 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.046031 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024504 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024504 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.046035 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.046035 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026035 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.026035 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026035 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.026035 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12161.120632 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12161.120632 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30075.296095 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30075.296095 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11677.747566 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11677.747566 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19407.489549 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 19407.489549 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19407.489549 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 19407.489549 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12165.646650 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12165.646650 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30103.785296 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30103.785296 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11656.463778 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11656.463778 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19421.980536 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 19421.980536 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19421.980536 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 19421.980536 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -765,10 +750,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1199398748332 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1199398748332 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1199398748332 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1199398748332 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1199377224257 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1199377224257 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1199377224257 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1199377224257 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt index 9d3d17a68..8816091ac 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.332810 # Nu sim_ticks 2332810256000 # Number of ticks simulated final_tick 2332810256000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1011951 # Simulator instruction rate (inst/s) -host_op_rate 1301307 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 39078665084 # Simulator tick rate (ticks/s) -host_mem_usage 435224 # Number of bytes of host memory used -host_seconds 59.70 # Real time elapsed on the host +host_inst_rate 685945 # Simulator instruction rate (inst/s) +host_op_rate 882083 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 26489224850 # Simulator tick rate (ticks/s) +host_mem_usage 391216 # Number of bytes of host memory used +host_seconds 88.07 # Real time elapsed on the host sim_insts 60408639 # Number of instructions simulated sim_ops 77681819 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 111673344 # Number of bytes read from this memory @@ -113,26 +113,13 @@ system.physmem.readPktSize::3 0 # Ca system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes system.physmem.readPktSize::6 0 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 0 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 0 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 0 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 0 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 0 # Categorize write packet sizes system.physmem.rdQLenPdf::0 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 0 # What read queue length does an incoming req see @@ -165,7 +152,6 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see @@ -198,7 +184,6 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see system.physmem.totQLat 0 # Total cycles spent in queuing delays system.physmem.totMemAccLat 0 # Sum of mem lat for all requests system.physmem.totBusLat 0 # Total cycles spent in databus access diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt index 4cde41f9a..fb87772ef 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 5.112041 # Nu sim_ticks 5112040970500 # Number of ticks simulated final_tick 5112040970500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1816388 # Simulator instruction rate (inst/s) -host_op_rate 3719186 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 46471341970 # Simulator tick rate (ticks/s) -host_mem_usage 582576 # Number of bytes of host memory used -host_seconds 110.00 # Real time elapsed on the host +host_inst_rate 1074050 # Simulator instruction rate (inst/s) +host_op_rate 2199194 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 27479001055 # Simulator tick rate (ticks/s) +host_mem_usage 583620 # Number of bytes of host memory used +host_seconds 186.03 # Real time elapsed on the host sim_insts 199810242 # Number of instructions simulated sim_ops 409125913 # Number of ops (including micro ops) simulated system.physmem.bytes_read::pc.south_bridge.ide 2464640 # Number of bytes read from this memory @@ -97,26 +97,13 @@ system.physmem.readPktSize::3 0 # Ca system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes system.physmem.readPktSize::6 0 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 0 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 0 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 0 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 0 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 0 # Categorize write packet sizes system.physmem.rdQLenPdf::0 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 0 # What read queue length does an incoming req see @@ -149,7 +136,6 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see @@ -182,7 +168,6 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see system.physmem.totQLat 0 # Total cycles spent in queuing delays system.physmem.totMemAccLat 0 # Sum of mem lat for all requests system.physmem.totBusLat 0 # Total cycles spent in databus access diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt index da7af1088..38cfd80e2 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt @@ -4,13 +4,13 @@ sim_seconds 5.195162 # Nu sim_ticks 5195162021000 # Number of ticks simulated final_tick 5195162021000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 973985 # Simulator instruction rate (inst/s) -host_op_rate 1877578 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 39447094407 # Simulator tick rate (ticks/s) -host_mem_usage 612564 # Number of bytes of host memory used -host_seconds 131.70 # Real time elapsed on the host -sim_insts 128273348 # Number of instructions simulated -sim_ops 247275973 # Number of ops (including micro ops) simulated +host_inst_rate 926995 # Simulator instruction rate (inst/s) +host_op_rate 1786992 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 37543942770 # Simulator tick rate (ticks/s) +host_mem_usage 611560 # Number of bytes of host memory used +host_seconds 138.38 # Real time elapsed on the host +sim_insts 128273323 # Number of instructions simulated +sim_ops 247275942 # Number of ops (including micro ops) simulated system.physmem.bytes_read::pc.south_bridge.ide 2861312 # Number of bytes read from this memory system.physmem.bytes_read::cpu.dtb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory @@ -48,7 +48,7 @@ system.physmem.bw_total::cpu.data 1734722 # To system.physmem.bw_total::total 4007716 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 198400 # Total number of read requests seen system.physmem.writeReqs 126924 # Total number of write requests seen -system.physmem.cpureqs 331611 # Reqs generatd by CPU via cache - shady +system.physmem.cpureqs 327581 # Reqs generatd by CPU via cache - shady system.physmem.bytesRead 12697600 # Total number of bytes read from memory system.physmem.bytesWritten 8123136 # Total number of bytes written to memory system.physmem.bytesConsumedRd 12697600 # bytesRead derated as per pkt->getSize() @@ -97,44 +97,31 @@ system.physmem.readPktSize::3 0 # Ca system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes system.physmem.readPktSize::6 198400 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 0 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 127557 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 1624 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 155111 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 8768 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 6671 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3417 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3399 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2809 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2248 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2166 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 2070 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 2020 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1315 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1213 # What read queue length does an incoming req see +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 0 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 126924 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 155117 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 8774 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 6658 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3415 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3396 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2811 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2249 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2165 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 2071 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 2021 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1317 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1212 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 1130 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1043 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1042 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 954 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 972 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 1102 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 1082 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 971 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 1103 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 1084 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 505 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 310 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 37 # What read queue length does an incoming req see @@ -149,16 +136,15 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 4190 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4518 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 4189 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 4520 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 5322 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 5432 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 5474 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 5502 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 5509 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 5510 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 5511 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 5434 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 5475 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 5503 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 5510 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 5511 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 5512 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 5519 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 5518 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 5518 # What write queue length does an incoming req see @@ -173,24 +159,23 @@ system.physmem.wrQLenPdf::19 5518 # Wh system.physmem.wrQLenPdf::20 5518 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 5518 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 5518 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 1329 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 1001 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 1330 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 999 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 197 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 87 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 4076582985 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 7872522985 # Sum of mem lat for all requests +system.physmem.wrQLenPdf::26 85 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7 # What write queue length does an incoming req see +system.physmem.totQLat 4073325250 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 7869155250 # Sum of mem lat for all requests system.physmem.totBusLat 991710000 # Total cycles spent in databus access -system.physmem.totBankLat 2804230000 # Total cycles spent in bank access -system.physmem.avgQLat 20553.30 # Average queueing delay per request -system.physmem.avgBankLat 14138.36 # Average bank access latency per request +system.physmem.totBankLat 2804120000 # Total cycles spent in bank access +system.physmem.avgQLat 20536.88 # Average queueing delay per request +system.physmem.avgBankLat 14137.80 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 39691.66 # Average memory access latency +system.physmem.avgMemAccLat 39674.68 # Average memory access latency system.physmem.avgRdBW 2.44 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 1.56 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 2.44 # Average consumed read bandwidth in MB/s @@ -199,10 +184,10 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time system.physmem.avgWrQLen 12.66 # Average write queue length over time -system.physmem.readRowHits 175587 # Number of row buffer hits during reads -system.physmem.writeRowHits 94819 # Number of row buffer hits during writes +system.physmem.readRowHits 175586 # Number of row buffer hits during reads +system.physmem.writeRowHits 94818 # Number of row buffer hits during writes system.physmem.readRowHitRate 88.53 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 74.71 # Row buffer hit rate for writes +system.physmem.writeRowHitRate 74.70 # Row buffer hit rate for writes system.physmem.avgGap 15969193.66 # Average gap between requests system.iocache.replacements 47509 # number of replacements system.iocache.tagsinuse 0.124742 # Cycle average of tags in use @@ -223,12 +208,12 @@ system.iocache.overall_misses::pc.south_bridge.ide 47564 system.iocache.overall_misses::total 47564 # number of overall misses system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 139479932 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 139479932 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 10701739160 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 10701739160 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 10841219092 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 10841219092 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 10841219092 # number of overall miss cycles -system.iocache.overall_miss_latency::total 10841219092 # number of overall miss cycles +system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 10699969160 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 10699969160 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 10839449092 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 10839449092 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 10839449092 # number of overall miss cycles +system.iocache.overall_miss_latency::total 10839449092 # number of overall miss cycles system.iocache.ReadReq_accesses::pc.south_bridge.ide 844 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 844 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) @@ -247,17 +232,17 @@ system.iocache.overall_miss_rate::pc.south_bridge.ide 1 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 165260.582938 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 165260.582938 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 229061.197774 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 229061.197774 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 227929.086957 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 227929.086957 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 227929.086957 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 227929.086957 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 173428 # number of cycles access was blocked +system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 229023.312500 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 229023.312500 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 227891.873938 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 227891.873938 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 227891.873938 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 227891.873938 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 173195 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 16211 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 16181 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 10.698168 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 10.703603 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -271,14 +256,14 @@ system.iocache.demand_mshr_misses::pc.south_bridge.ide 47564 system.iocache.demand_mshr_misses::total 47564 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::pc.south_bridge.ide 47564 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 47564 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 95570991 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 95570991 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 8270938224 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 8270938224 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 8366509215 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 8366509215 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 8366509215 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 8366509215 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 95570962 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 95570962 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 8269165315 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 8269165315 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 8364736277 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 8364736277 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 8364736277 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 8364736277 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses @@ -287,14 +272,14 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 113235.771327 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 113235.771327 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 177032.068151 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 177032.068151 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 175900.033954 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 175900.033954 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 175900.033954 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 175900.033954 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 113235.736967 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 113235.736967 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 176994.120612 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 176994.120612 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 175862.759167 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 175862.759167 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 175862.759167 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 175862.759167 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). @@ -311,72 +296,72 @@ system.pc.south_bridge.ide.disks1.dma_write_txs 1 system.cpu.numCycles 10390324042 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 128273348 # Number of instructions committed -system.cpu.committedOps 247275973 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 232011682 # Number of integer alu accesses +system.cpu.committedInsts 128273323 # Number of instructions committed +system.cpu.committedOps 247275942 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 232011652 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu.num_func_calls 0 # number of times a function call or return occured system.cpu.num_conditional_control_insts 23157367 # number of instructions that are conditional controls -system.cpu.num_int_insts 232011682 # number of integer instructions +system.cpu.num_int_insts 232011652 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 567056120 # number of times the integer registers were read -system.cpu.num_int_register_writes 293242224 # number of times the integer registers were written +system.cpu.num_int_register_reads 567056066 # number of times the integer registers were read +system.cpu.num_int_register_writes 293242220 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 22232138 # number of memory refs -system.cpu.num_load_insts 13871783 # Number of load instructions -system.cpu.num_store_insts 8360355 # Number of store instructions -system.cpu.num_idle_cycles 9789668776.998116 # Number of idle cycles -system.cpu.num_busy_cycles 600655265.001884 # Number of busy cycles +system.cpu.num_mem_refs 22232130 # number of memory refs +system.cpu.num_load_insts 13871776 # Number of load instructions +system.cpu.num_store_insts 8360354 # Number of store instructions +system.cpu.num_idle_cycles 9789674914.998116 # Number of idle cycles +system.cpu.num_busy_cycles 600649127.001884 # Number of busy cycles system.cpu.not_idle_fraction 0.057809 # Percentage of non-idle cycles system.cpu.idle_fraction 0.942191 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu.icache.replacements 791521 # number of replacements +system.cpu.icache.replacements 791510 # number of replacements system.cpu.icache.tagsinuse 510.376104 # Cycle average of tags in use -system.cpu.icache.total_refs 144497694 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 792033 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 182.438982 # Average number of references to valid blocks. +system.cpu.icache.total_refs 144497671 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 792022 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 182.441486 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 159800886000 # Cycle when the warmup percentage was hit. system.cpu.icache.occ_blocks::cpu.inst 510.376104 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.996828 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.996828 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 144497694 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 144497694 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 144497694 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 144497694 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 144497694 # number of overall hits -system.cpu.icache.overall_hits::total 144497694 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 792040 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 792040 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 792040 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 792040 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 792040 # number of overall misses -system.cpu.icache.overall_misses::total 792040 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 10957638500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 10957638500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 10957638500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 10957638500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 10957638500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 10957638500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 145289734 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 145289734 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 145289734 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 145289734 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 145289734 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 145289734 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_hits::cpu.inst 144497671 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 144497671 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 144497671 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 144497671 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 144497671 # number of overall hits +system.cpu.icache.overall_hits::total 144497671 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 792029 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 792029 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 792029 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 792029 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 792029 # number of overall misses +system.cpu.icache.overall_misses::total 792029 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 10955241500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 10955241500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 10955241500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 10955241500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 10955241500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 10955241500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 145289700 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 145289700 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 145289700 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 145289700 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 145289700 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 145289700 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005451 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.005451 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.005451 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.005451 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.005451 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.005451 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13834.703424 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13834.703424 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13834.703424 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13834.703424 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13834.703424 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13834.703424 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13831.869161 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13831.869161 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13831.869161 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13831.869161 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13831.869161 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13831.869161 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -385,30 +370,30 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 792040 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 792040 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 792040 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 792040 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 792040 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 792040 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9373558500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 9373558500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9373558500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 9373558500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9373558500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 9373558500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 792029 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 792029 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 792029 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 792029 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 792029 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 792029 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9371183500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 9371183500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9371183500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 9371183500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9371183500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 9371183500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005451 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005451 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005451 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.005451 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005451 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.005451 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11834.703424 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11834.703424 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11834.703424 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11834.703424 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11834.703424 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11834.703424 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11831.869161 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11831.869161 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11831.869161 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11831.869161 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11831.869161 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11831.869161 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.itb_walker_cache.replacements 3425 # number of replacements system.cpu.itb_walker_cache.tagsinuse 3.077882 # Cycle average of tags in use @@ -494,51 +479,51 @@ system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 7860.975041 system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 7860.975041 # average overall mshr miss latency system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 7860.975041 # average overall mshr miss latency system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.replacements 7538 # number of replacements +system.cpu.dtb_walker_cache.replacements 7540 # number of replacements system.cpu.dtb_walker_cache.tagsinuse 5.062515 # Cycle average of tags in use -system.cpu.dtb_walker_cache.total_refs 13179 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.sampled_refs 7552 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.avg_refs 1.745101 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.total_refs 13178 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.sampled_refs 7554 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.avg_refs 1.744506 # Average number of references to valid blocks. system.cpu.dtb_walker_cache.warmup_cycle 5159123845000 # Cycle when the warmup percentage was hit. system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 5.062515 # Average occupied blocks per requestor system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.316407 # Average percentage of cache occupancy system.cpu.dtb_walker_cache.occ_percent::total 0.316407 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13181 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 13181 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13181 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 13181 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13181 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 13181 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8725 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 8725 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8725 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 8725 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8725 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 8725 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 92081500 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 92081500 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 92081500 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::total 92081500 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 92081500 # number of overall miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::total 92081500 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13180 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 13180 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13180 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 13180 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13180 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 13180 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8726 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 8726 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8726 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 8726 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8726 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 8726 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 92094500 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 92094500 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 92094500 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::total 92094500 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 92094500 # number of overall miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::total 92094500 # number of overall miss cycles system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21906 # number of ReadReq accesses(hits+misses) system.cpu.dtb_walker_cache.ReadReq_accesses::total 21906 # number of ReadReq accesses(hits+misses) system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21906 # number of demand (read+write) accesses system.cpu.dtb_walker_cache.demand_accesses::total 21906 # number of demand (read+write) accesses system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21906 # number of overall (read+write) accesses system.cpu.dtb_walker_cache.overall_accesses::total 21906 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.398293 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.398293 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.398293 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.398293 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.398293 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.398293 # miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10553.753582 # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10553.753582 # average ReadReq miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10553.753582 # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10553.753582 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10553.753582 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10553.753582 # average overall miss latency +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.398338 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.398338 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.398338 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.398338 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.398338 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.398338 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10554.033922 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10554.033922 # average ReadReq miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10554.033922 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10554.033922 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10554.033922 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10554.033922 # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -547,74 +532,74 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 2712 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 2712 # number of writebacks -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 8725 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 8725 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 8725 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::total 8725 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 8725 # number of overall MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::total 8725 # number of overall MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 74631500 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 74631500 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 74631500 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 74631500 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 74631500 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 74631500 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.398293 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.398293 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.398293 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.398293 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.398293 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.398293 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 8553.753582 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8553.753582 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 8553.753582 # average overall mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 8553.753582 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 8553.753582 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 8553.753582 # average overall mshr miss latency +system.cpu.dtb_walker_cache.writebacks::writebacks 2713 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 2713 # number of writebacks +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 8726 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 8726 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 8726 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::total 8726 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 8726 # number of overall MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::total 8726 # number of overall MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 74642500 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 74642500 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 74642500 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 74642500 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 74642500 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 74642500 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.398338 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.398338 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.398338 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.398338 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.398338 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.398338 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 8554.033922 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8554.033922 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 8554.033922 # average overall mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 8554.033922 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 8554.033922 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 8554.033922 # average overall mshr miss latency system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1618787 # number of replacements +system.cpu.dcache.replacements 1618785 # number of replacements system.cpu.dcache.tagsinuse 511.997766 # Cycle average of tags in use -system.cpu.dcache.total_refs 20025899 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1619299 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 12.367017 # Average number of references to valid blocks. +system.cpu.dcache.total_refs 20025893 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1619297 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 12.367029 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 39012000 # Cycle when the warmup percentage was hit. system.cpu.dcache.occ_blocks::cpu.data 511.997766 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999996 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999996 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 11988264 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 11988264 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8035473 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8035473 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 20023737 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 20023737 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 20023737 # number of overall hits -system.cpu.dcache.overall_hits::total 20023737 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1306607 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1306607 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 314888 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 314888 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1621495 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1621495 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1621495 # number of overall misses -system.cpu.dcache.overall_misses::total 1621495 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 18344083000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 18344083000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 8556368000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 8556368000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 26900451000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 26900451000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 26900451000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 26900451000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 13294871 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 13294871 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 8350361 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8350361 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 21645232 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21645232 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 21645232 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21645232 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_hits::cpu.data 11988262 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 11988262 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 8035470 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8035470 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 20023732 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 20023732 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 20023732 # number of overall hits +system.cpu.dcache.overall_hits::total 20023732 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1306602 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1306602 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 314890 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 314890 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1621492 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1621492 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1621492 # number of overall misses +system.cpu.dcache.overall_misses::total 1621492 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 18343104000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 18343104000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 8556691000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 8556691000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 26899795000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 26899795000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 26899795000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 26899795000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 13294864 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 13294864 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 8350360 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 8350360 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 21645224 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 21645224 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 21645224 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 21645224 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098279 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.098279 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037710 # miss rate for WriteReq accesses @@ -623,14 +608,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.074912 system.cpu.dcache.demand_miss_rate::total 0.074912 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.074912 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.074912 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14039.480119 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14039.480119 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27172.734433 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 27172.734433 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 16589.906845 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 16589.906845 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 16589.906845 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 16589.906845 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14038.784573 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14038.784573 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27173.587602 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 27173.587602 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 16589.532973 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 16589.532973 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 16589.532973 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 16589.532973 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -639,24 +624,24 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1536049 # number of writebacks -system.cpu.dcache.writebacks::total 1536049 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1306607 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1306607 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 314888 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 314888 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1621495 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1621495 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1621495 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1621495 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 15730869000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 15730869000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7926592000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 7926592000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23657461000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 23657461000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23657461000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 23657461000 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 1536047 # number of writebacks +system.cpu.dcache.writebacks::total 1536047 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1306602 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1306602 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 314890 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 314890 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1621492 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1621492 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1621492 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1621492 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 15729900000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 15729900000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7926911000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 7926911000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23656811000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 23656811000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23656811000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 23656811000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 94145949000 # number of ReadReq MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 94145949000 # number of ReadReq MSHR uncacheable cycles system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2467832500 # number of WriteReq MSHR uncacheable cycles @@ -671,14 +656,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.074912 system.cpu.dcache.demand_mshr_miss_rate::total 0.074912 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074912 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.074912 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12039.480119 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12039.480119 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25172.734433 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25172.734433 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14589.906845 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 14589.906845 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14589.906845 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 14589.906845 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12038.784573 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12038.784573 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25173.587602 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25173.587602 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14589.532973 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 14589.532973 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14589.532973 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 14589.532973 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -687,43 +672,43 @@ system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 86864 # number of replacements -system.cpu.l2cache.tagsinuse 64770.429000 # Cycle average of tags in use -system.cpu.l2cache.total_refs 3484731 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 64770.428925 # Cycle average of tags in use +system.cpu.l2cache.total_refs 3484716 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 151631 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 22.981653 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 22.981554 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 50336.267441 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::writebacks 50336.266909 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.dtb.walker 0.007172 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.140366 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 3358.135857 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 11075.878163 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 3358.136526 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 11075.877952 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.768070 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.051241 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.169004 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::total 0.988318 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6346 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6347 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2754 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 779155 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1277466 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2065721 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 1539402 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1539402 # number of Writeback hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 779144 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 1277462 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 2065707 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 1539401 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 1539401 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 293 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 293 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 199364 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 199364 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 6346 # number of demand (read+write) hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 199367 # 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number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 779155 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1476830 # number of overall hits -system.cpu.l2cache.overall_hits::total 2265085 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 779144 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1476829 # number of overall hits +system.cpu.l2cache.overall_hits::total 2265074 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 1 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.inst 12872 # number of ReadReq misses @@ -745,44 +730,44 @@ system.cpu.l2cache.overall_misses::cpu.data 141743 # system.cpu.l2cache.overall_misses::total 154621 # number of overall misses system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 68500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 345000 # 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number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1305851 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 2106984 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 1539402 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 1539402 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.inst 792016 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1305847 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 2106970 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 1539401 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 1539401 # number of Writeback accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1657 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 1657 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 312722 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 312722 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6347 # number of demand (read+write) accesses +system.cpu.l2cache.ReadExReq_accesses::cpu.data 312725 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 312725 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6348 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.itb.walker 2759 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 792027 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1618573 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2419706 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6347 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 792016 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1618572 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2419695 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6348 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.itb.walker 2759 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 792027 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1618573 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2419706 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 792016 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1618572 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2419695 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000158 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001812 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016252 # miss rate for ReadReq accesses @@ -790,8 +775,8 @@ system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.021737 system.cpu.l2cache.ReadReq_miss_rate::total 0.019584 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.823174 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 0.823174 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.362488 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.362488 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.362485 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.362485 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000158 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001812 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016252 # miss rate for demand accesses @@ -804,23 +789,23 @@ system.cpu.l2cache.overall_miss_rate::cpu.data 0.087573 system.cpu.l2cache.overall_miss_rate::total 0.063901 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 68500 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 69000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 61370.066812 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 58088.585521 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 59113.818675 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 61194.958048 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 58056.068346 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 59036.824758 # average ReadReq miss latency system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 11858.137830 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 11858.137830 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 49251.706981 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 49251.706981 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 49254.247605 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 49254.247605 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 68500 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 69000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 61370.066812 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 51021.352024 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 51883.563682 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 61194.958048 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 51016.872085 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 51864.879285 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 68500 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 69000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 61370.066812 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 51021.352024 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 51883.563682 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 61194.958048 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 51016.872085 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 51864.879285 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -850,25 +835,25 @@ system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 5 system.cpu.l2cache.overall_mshr_misses::cpu.inst 12872 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 141743 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 154621 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 56252 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 281260 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 630045573 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1296264296 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1926647381 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 56251 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 281255 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 627778857 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1295316957 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1923433320 # number of ReadReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 14542846 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 14542846 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4190240726 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4190240726 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 56252 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 281260 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 630045573 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5486505022 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 6116888107 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 56252 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 281260 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 630045573 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5486505022 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 6116888107 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4190411275 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4190411275 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 56251 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 281255 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 627778857 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5485728232 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 6113844595 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 56251 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 281255 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 627778857 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5485728232 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 6113844595 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 86591175500 # number of ReadReq MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 86591175500 # number of ReadReq MSHR uncacheable cycles system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2305021500 # number of WriteReq MSHR uncacheable cycles @@ -882,8 +867,8 @@ system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.021737 system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.019584 # mshr miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.823174 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.823174 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.362488 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.362488 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.362485 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.362485 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000158 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.001812 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016252 # mshr miss rate for demand accesses @@ -894,25 +879,25 @@ system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.001812 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016252 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.087573 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.063901 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 56252 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 56252 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 48946.983608 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 45667.229029 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 46691.888156 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 56251 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 56251 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 48770.886964 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 45633.854395 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 46613.996074 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10661.910557 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10661.910557 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36964.667037 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36964.667037 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 56252 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 56252 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 48946.983608 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38707.414278 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39560.526106 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 56252 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 56252 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 48946.983608 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38707.414278 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39560.526106 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36966.171554 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36966.171554 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 56251 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 56251 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 48770.886964 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38701.934007 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39540.842415 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 56251 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 56251 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 48770.886964 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38701.934007 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39540.842415 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency diff --git a/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt b/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt index c8eb78d93..ac7e3035a 100644 --- a/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt +++ b/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.200409 # Nu sim_ticks 200409293000 # Number of ticks simulated final_tick 4321201686500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 19440889 # Simulator instruction rate (inst/s) -host_op_rate 19440880 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 7408936081 # Simulator tick rate (ticks/s) -host_mem_usage 472492 # Number of bytes of host memory used -host_seconds 27.05 # Real time elapsed on the host +host_inst_rate 11931696 # Simulator instruction rate (inst/s) +host_op_rate 11931689 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4547176905 # Simulator tick rate (ticks/s) +host_mem_usage 472520 # Number of bytes of host memory used +host_seconds 44.07 # Real time elapsed on the host sim_insts 525869186 # Number of instructions simulated sim_ops 525869186 # Number of ops (including micro ops) simulated testsys.physmem.bytes_read::cpu.inst 81048564 # Number of bytes read from this memory @@ -91,26 +91,13 @@ testsys.physmem.readPktSize::3 0 # Ca testsys.physmem.readPktSize::4 0 # Categorize read packet sizes testsys.physmem.readPktSize::5 0 # Categorize read packet sizes testsys.physmem.readPktSize::6 0 # Categorize read packet sizes -testsys.physmem.readPktSize::7 0 # Categorize read packet sizes -testsys.physmem.readPktSize::8 0 # Categorize read packet sizes -testsys.physmem.writePktSize::0 0 # categorize write packet sizes -testsys.physmem.writePktSize::1 0 # categorize write packet sizes -testsys.physmem.writePktSize::2 0 # categorize write packet sizes -testsys.physmem.writePktSize::3 0 # categorize write packet sizes -testsys.physmem.writePktSize::4 0 # categorize write packet sizes -testsys.physmem.writePktSize::5 0 # categorize write packet sizes -testsys.physmem.writePktSize::6 0 # categorize write packet sizes -testsys.physmem.writePktSize::7 0 # categorize write packet sizes -testsys.physmem.writePktSize::8 0 # categorize write packet sizes -testsys.physmem.neitherpktsize::0 0 # categorize neither packet sizes -testsys.physmem.neitherpktsize::1 0 # categorize neither packet sizes -testsys.physmem.neitherpktsize::2 0 # categorize neither packet sizes -testsys.physmem.neitherpktsize::3 0 # categorize neither packet sizes -testsys.physmem.neitherpktsize::4 0 # categorize neither packet sizes -testsys.physmem.neitherpktsize::5 0 # categorize neither packet sizes -testsys.physmem.neitherpktsize::6 0 # categorize neither packet sizes -testsys.physmem.neitherpktsize::7 0 # categorize neither packet sizes -testsys.physmem.neitherpktsize::8 0 # categorize neither packet sizes +testsys.physmem.writePktSize::0 0 # Categorize write packet sizes +testsys.physmem.writePktSize::1 0 # Categorize write packet sizes +testsys.physmem.writePktSize::2 0 # Categorize write packet sizes +testsys.physmem.writePktSize::3 0 # Categorize write packet sizes +testsys.physmem.writePktSize::4 0 # Categorize write packet sizes +testsys.physmem.writePktSize::5 0 # Categorize write packet sizes +testsys.physmem.writePktSize::6 0 # Categorize write packet sizes testsys.physmem.rdQLenPdf::0 0 # What read queue length does an incoming req see testsys.physmem.rdQLenPdf::1 0 # What read queue length does an incoming req see testsys.physmem.rdQLenPdf::2 0 # What read queue length does an incoming req see @@ -143,7 +130,6 @@ testsys.physmem.rdQLenPdf::28 0 # Wh testsys.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see testsys.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see testsys.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -testsys.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see testsys.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see testsys.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see testsys.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see @@ -176,7 +162,6 @@ testsys.physmem.wrQLenPdf::28 0 # Wh testsys.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see testsys.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see testsys.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -testsys.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see testsys.physmem.totQLat 0 # Total cycles spent in queuing delays testsys.physmem.totMemAccLat 0 # Sum of mem lat for all requests testsys.physmem.totBusLat 0 # Total cycles spent in databus access @@ -462,26 +447,13 @@ drivesys.physmem.readPktSize::3 0 # Ca drivesys.physmem.readPktSize::4 0 # Categorize read packet sizes drivesys.physmem.readPktSize::5 0 # Categorize read packet sizes drivesys.physmem.readPktSize::6 0 # Categorize read packet sizes -drivesys.physmem.readPktSize::7 0 # Categorize read packet sizes -drivesys.physmem.readPktSize::8 0 # Categorize read packet sizes -drivesys.physmem.writePktSize::0 0 # categorize write packet sizes -drivesys.physmem.writePktSize::1 0 # categorize write packet sizes -drivesys.physmem.writePktSize::2 0 # categorize write packet sizes -drivesys.physmem.writePktSize::3 0 # categorize write packet sizes -drivesys.physmem.writePktSize::4 0 # categorize write packet sizes -drivesys.physmem.writePktSize::5 0 # categorize write packet sizes -drivesys.physmem.writePktSize::6 0 # categorize write packet sizes -drivesys.physmem.writePktSize::7 0 # categorize write packet sizes -drivesys.physmem.writePktSize::8 0 # categorize write packet sizes -drivesys.physmem.neitherpktsize::0 0 # categorize neither packet sizes -drivesys.physmem.neitherpktsize::1 0 # categorize neither packet sizes -drivesys.physmem.neitherpktsize::2 0 # categorize neither packet sizes -drivesys.physmem.neitherpktsize::3 0 # categorize neither packet sizes -drivesys.physmem.neitherpktsize::4 0 # categorize neither packet sizes -drivesys.physmem.neitherpktsize::5 0 # categorize neither packet sizes -drivesys.physmem.neitherpktsize::6 0 # categorize neither packet sizes -drivesys.physmem.neitherpktsize::7 0 # categorize neither packet sizes -drivesys.physmem.neitherpktsize::8 0 # categorize neither packet sizes +drivesys.physmem.writePktSize::0 0 # Categorize write packet sizes +drivesys.physmem.writePktSize::1 0 # Categorize write packet sizes +drivesys.physmem.writePktSize::2 0 # Categorize write packet sizes +drivesys.physmem.writePktSize::3 0 # Categorize write packet sizes +drivesys.physmem.writePktSize::4 0 # Categorize write packet sizes +drivesys.physmem.writePktSize::5 0 # Categorize write packet sizes +drivesys.physmem.writePktSize::6 0 # Categorize write packet sizes drivesys.physmem.rdQLenPdf::0 0 # What read queue length does an incoming req see drivesys.physmem.rdQLenPdf::1 0 # What read queue length does an incoming req see drivesys.physmem.rdQLenPdf::2 0 # What read queue length does an incoming req see @@ -514,7 +486,6 @@ drivesys.physmem.rdQLenPdf::28 0 # Wh drivesys.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see drivesys.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see drivesys.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -drivesys.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see drivesys.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see drivesys.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see drivesys.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see @@ -547,7 +518,6 @@ drivesys.physmem.wrQLenPdf::28 0 # Wh drivesys.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see drivesys.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see drivesys.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -drivesys.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see drivesys.physmem.totQLat 0 # Total cycles spent in queuing delays drivesys.physmem.totMemAccLat 0 # Sum of mem lat for all requests drivesys.physmem.totBusLat 0 # Total cycles spent in databus access @@ -751,11 +721,11 @@ sim_seconds 0.000407 # Nu sim_ticks 407365500 # Number of ticks simulated final_tick 4321609052000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 12024534237 # Simulator instruction rate (inst/s) -host_op_rate 12021051237 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 9308365303 # Simulator tick rate (ticks/s) -host_mem_usage 472492 # Number of bytes of host memory used -host_seconds 0.04 # Real time elapsed on the host +host_inst_rate 6212406894 # Simulator instruction rate (inst/s) +host_op_rate 6210790807 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4809282801 # Simulator tick rate (ticks/s) +host_mem_usage 472520 # Number of bytes of host memory used +host_seconds 0.08 # Real time elapsed on the host sim_insts 525940622 # Number of instructions simulated sim_ops 525940622 # Number of ops (including micro ops) simulated testsys.physmem.bytes_read::cpu.inst 141136 # Number of bytes read from this memory @@ -835,26 +805,13 @@ testsys.physmem.readPktSize::3 0 # Ca testsys.physmem.readPktSize::4 0 # Categorize read packet sizes testsys.physmem.readPktSize::5 0 # Categorize read packet sizes testsys.physmem.readPktSize::6 0 # Categorize read packet sizes -testsys.physmem.readPktSize::7 0 # Categorize read packet sizes -testsys.physmem.readPktSize::8 0 # Categorize read packet sizes -testsys.physmem.writePktSize::0 0 # categorize write packet sizes -testsys.physmem.writePktSize::1 0 # categorize write packet sizes -testsys.physmem.writePktSize::2 0 # categorize write packet sizes -testsys.physmem.writePktSize::3 0 # categorize write packet sizes -testsys.physmem.writePktSize::4 0 # categorize write packet sizes -testsys.physmem.writePktSize::5 0 # categorize write packet sizes -testsys.physmem.writePktSize::6 0 # categorize write packet sizes -testsys.physmem.writePktSize::7 0 # categorize write packet sizes -testsys.physmem.writePktSize::8 0 # categorize write packet sizes -testsys.physmem.neitherpktsize::0 0 # categorize neither packet sizes -testsys.physmem.neitherpktsize::1 0 # categorize neither packet sizes -testsys.physmem.neitherpktsize::2 0 # categorize neither packet sizes -testsys.physmem.neitherpktsize::3 0 # categorize neither packet sizes -testsys.physmem.neitherpktsize::4 0 # categorize neither packet sizes -testsys.physmem.neitherpktsize::5 0 # categorize neither packet sizes -testsys.physmem.neitherpktsize::6 0 # categorize neither packet sizes -testsys.physmem.neitherpktsize::7 0 # categorize neither packet sizes -testsys.physmem.neitherpktsize::8 0 # categorize neither packet sizes +testsys.physmem.writePktSize::0 0 # Categorize write packet sizes +testsys.physmem.writePktSize::1 0 # Categorize write packet sizes +testsys.physmem.writePktSize::2 0 # Categorize write packet sizes +testsys.physmem.writePktSize::3 0 # Categorize write packet sizes +testsys.physmem.writePktSize::4 0 # Categorize write packet sizes +testsys.physmem.writePktSize::5 0 # Categorize write packet sizes +testsys.physmem.writePktSize::6 0 # Categorize write packet sizes testsys.physmem.rdQLenPdf::0 0 # What read queue length does an incoming req see testsys.physmem.rdQLenPdf::1 0 # What read queue length does an incoming req see testsys.physmem.rdQLenPdf::2 0 # What read queue length does an incoming req see @@ -887,7 +844,6 @@ testsys.physmem.rdQLenPdf::28 0 # Wh testsys.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see testsys.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see testsys.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -testsys.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see testsys.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see testsys.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see testsys.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see @@ -920,7 +876,6 @@ testsys.physmem.wrQLenPdf::28 0 # Wh testsys.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see testsys.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see testsys.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -testsys.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see testsys.physmem.totQLat 0 # Total cycles spent in queuing delays testsys.physmem.totMemAccLat 0 # Sum of mem lat for all requests testsys.physmem.totBusLat 0 # Total cycles spent in databus access @@ -1157,26 +1112,13 @@ drivesys.physmem.readPktSize::3 0 # Ca drivesys.physmem.readPktSize::4 0 # Categorize read packet sizes drivesys.physmem.readPktSize::5 0 # Categorize read packet sizes drivesys.physmem.readPktSize::6 0 # Categorize read packet sizes -drivesys.physmem.readPktSize::7 0 # Categorize read packet sizes -drivesys.physmem.readPktSize::8 0 # Categorize read packet sizes -drivesys.physmem.writePktSize::0 0 # categorize write packet sizes -drivesys.physmem.writePktSize::1 0 # categorize write packet sizes -drivesys.physmem.writePktSize::2 0 # categorize write packet sizes -drivesys.physmem.writePktSize::3 0 # categorize write packet sizes -drivesys.physmem.writePktSize::4 0 # categorize write packet sizes -drivesys.physmem.writePktSize::5 0 # categorize write packet sizes -drivesys.physmem.writePktSize::6 0 # categorize write packet sizes -drivesys.physmem.writePktSize::7 0 # categorize write packet sizes -drivesys.physmem.writePktSize::8 0 # categorize write packet sizes -drivesys.physmem.neitherpktsize::0 0 # categorize neither packet sizes -drivesys.physmem.neitherpktsize::1 0 # categorize neither packet sizes -drivesys.physmem.neitherpktsize::2 0 # categorize neither packet sizes -drivesys.physmem.neitherpktsize::3 0 # categorize neither packet sizes -drivesys.physmem.neitherpktsize::4 0 # categorize neither packet sizes -drivesys.physmem.neitherpktsize::5 0 # categorize neither packet sizes -drivesys.physmem.neitherpktsize::6 0 # categorize neither packet sizes -drivesys.physmem.neitherpktsize::7 0 # categorize neither packet sizes -drivesys.physmem.neitherpktsize::8 0 # categorize neither packet sizes +drivesys.physmem.writePktSize::0 0 # Categorize write packet sizes +drivesys.physmem.writePktSize::1 0 # Categorize write packet sizes +drivesys.physmem.writePktSize::2 0 # Categorize write packet sizes +drivesys.physmem.writePktSize::3 0 # Categorize write packet sizes +drivesys.physmem.writePktSize::4 0 # Categorize write packet sizes +drivesys.physmem.writePktSize::5 0 # Categorize write packet sizes +drivesys.physmem.writePktSize::6 0 # Categorize write packet sizes drivesys.physmem.rdQLenPdf::0 0 # What read queue length does an incoming req see drivesys.physmem.rdQLenPdf::1 0 # What read queue length does an incoming req see drivesys.physmem.rdQLenPdf::2 0 # What read queue length does an incoming req see @@ -1209,7 +1151,6 @@ drivesys.physmem.rdQLenPdf::28 0 # Wh drivesys.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see drivesys.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see drivesys.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -drivesys.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see drivesys.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see drivesys.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see drivesys.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see @@ -1242,7 +1183,6 @@ drivesys.physmem.wrQLenPdf::28 0 # Wh drivesys.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see drivesys.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see drivesys.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -drivesys.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see drivesys.physmem.totQLat 0 # Total cycles spent in queuing delays drivesys.physmem.totMemAccLat 0 # Sum of mem lat for all requests drivesys.physmem.totBusLat 0 # Total cycles spent in databus access diff --git a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt index 9e62381ba..a38dae954 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000019 # Nu sim_ticks 19476000 # Number of ticks simulated final_tick 19476000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 78389 # Simulator instruction rate (inst/s) -host_op_rate 78368 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 238789679 # Simulator tick rate (ticks/s) -host_mem_usage 223680 # Number of bytes of host memory used -host_seconds 0.08 # Real time elapsed on the host +host_inst_rate 1322 # Simulator instruction rate (inst/s) +host_op_rate 1322 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4028719 # Simulator tick rate (ticks/s) +host_mem_usage 223696 # Number of bytes of host memory used +host_seconds 4.83 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 19200 # Number of bytes read from this memory @@ -78,26 +78,13 @@ system.physmem.readPktSize::3 0 # Ca system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes system.physmem.readPktSize::6 469 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 0 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 0 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 0 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 0 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 0 # Categorize write packet sizes system.physmem.rdQLenPdf::0 301 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 136 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 24 # What read queue length does an incoming req see @@ -130,7 +117,6 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see @@ -163,15 +149,14 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 2628216 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 13374466 # Sum of mem lat for all requests +system.physmem.totQLat 2627750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 13374000 # Sum of mem lat for all requests system.physmem.totBusLat 2345000 # Total cycles spent in databus access system.physmem.totBankLat 8401250 # Total cycles spent in bank access -system.physmem.avgQLat 5603.87 # Average queueing delay per request +system.physmem.avgQLat 5602.88 # Average queueing delay per request system.physmem.avgBankLat 17913.11 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 28516.99 # Average memory access latency +system.physmem.avgMemAccLat 28515.99 # Average memory access latency system.physmem.avgRdBW 1537.89 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 1537.89 # Average consumed read bandwidth in MB/s @@ -372,13 +357,13 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52524.834437 system.cpu.icache.overall_avg_mshr_miss_latency::total 52524.834437 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 199.973805 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 199.973821 # Cycle average of tags in use system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 395 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.002532 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 143.049582 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 56.924223 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 143.049595 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 56.924226 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::cpu.inst 0.004366 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.001737 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::total 0.006103 # Average percentage of cache occupancy @@ -462,17 +447,17 @@ system.cpu.l2cache.demand_mshr_misses::total 469 system.cpu.l2cache.overall_mshr_misses::cpu.inst 301 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 469 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11816499 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4177366 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15993865 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2666348 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2666348 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11816499 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6843714 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 18660213 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11816499 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6843714 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 18660213 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11816250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4177308 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15993558 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2666299 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2666299 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11816250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6843607 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 18659857 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11816250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6843607 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 18659857 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997481 # mshr miss rate for ReadReq accesses @@ -484,17 +469,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.997872 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.997872 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39257.471761 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 43972.273684 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40388.547980 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36525.315068 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36525.315068 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39257.471761 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40736.392857 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39787.234542 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39257.471761 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40736.392857 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39787.234542 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39256.644518 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 43971.663158 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40387.772727 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36524.643836 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36524.643836 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39256.644518 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40735.755952 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39786.475480 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39256.644518 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40735.755952 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39786.475480 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.tagsinuse 104.433203 # Cycle average of tags in use diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt index d7bf6a6b9..8b0cd4f27 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000016 # Number of seconds simulated -sim_ticks 16030500 # Number of ticks simulated -final_tick 16030500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 16039500 # Number of ticks simulated +final_tick 16039500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 76258 # Simulator instruction rate (inst/s) -host_op_rate 76239 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 191753794 # Simulator tick rate (ticks/s) -host_mem_usage 225728 # Number of bytes of host memory used -host_seconds 0.08 # Real time elapsed on the host +host_inst_rate 1336 # Simulator instruction rate (inst/s) +host_op_rate 1336 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3362323 # Simulator tick rate (ticks/s) +host_mem_usage 225744 # Number of bytes of host memory used +host_seconds 4.77 # Real time elapsed on the host sim_insts 6372 # Number of instructions simulated sim_ops 6372 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 19968 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 19968 # Nu system.physmem.num_reads::cpu.inst 312 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 174 # Number of read requests responded to by this memory system.physmem.num_reads::total 486 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1245625526 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 694675774 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1940301301 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1245625526 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1245625526 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1245625526 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 694675774 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1940301301 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1244926587 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 694285981 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1939212569 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1244926587 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1244926587 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1244926587 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 694285981 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1939212569 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 486 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 486 # Reqs generatd by CPU via cache - shady @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 15817000 # Total gap between requests +system.physmem.totGap 15803000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -78,26 +78,13 @@ system.physmem.readPktSize::3 0 # Ca system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes system.physmem.readPktSize::6 486 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 0 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 0 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 0 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 0 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 0 # Categorize write packet sizes system.physmem.rdQLenPdf::0 247 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 152 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 62 # What read queue length does an incoming req see @@ -130,7 +117,6 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see @@ -163,28 +149,27 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 2909986 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 13644986 # Sum of mem lat for all requests +system.physmem.totQLat 2921750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 13656750 # Sum of mem lat for all requests system.physmem.totBusLat 2430000 # Total cycles spent in databus access system.physmem.totBankLat 8305000 # Total cycles spent in bank access -system.physmem.avgQLat 5987.63 # Average queueing delay per request +system.physmem.avgQLat 6011.83 # Average queueing delay per request system.physmem.avgBankLat 17088.48 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 28076.10 # Average memory access latency -system.physmem.avgRdBW 1940.30 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 28100.31 # Average memory access latency +system.physmem.avgRdBW 1939.21 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1940.30 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1939.21 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 15.16 # Data bus utilization in percentage +system.physmem.busUtil 15.15 # Data bus utilization in percentage system.physmem.avgRdQLen 0.85 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time system.physmem.readRowHits 396 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 81.48 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 32545.27 # Average gap between requests +system.physmem.avgGap 32516.46 # Average gap between requests system.cpu.branchPred.lookups 2896 # Number of BP lookups system.cpu.branchPred.condPredicted 1698 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 513 # Number of conditional branches incorrect @@ -227,7 +212,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 32062 # number of cpu cycles simulated +system.cpu.numCycles 32080 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.fetch.icacheStallCycles 8352 # Number of cycles fetch is stalled on an Icache miss @@ -258,8 +243,8 @@ system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Nu system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::total 14509 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.090325 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.515470 # Number of inst fetches per cycle +system.cpu.fetch.branchRate 0.090274 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.515181 # Number of inst fetches per cycle system.cpu.decode.IdleCycles 9308 # Number of cycles decode is idle system.cpu.decode.BlockedCycles 1148 # Number of cycles decode is blocked system.cpu.decode.RunCycles 2753 # Number of cycles decode is running @@ -384,7 +369,7 @@ system.cpu.iq.FU_type_0::MemWrite 1140 10.55% 100.00% # Ty system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::total 10806 # Type of FU issued -system.cpu.iq.rate 0.337034 # Inst issue rate +system.cpu.iq.rate 0.336845 # Inst issue rate system.cpu.iq.fu_busy_cnt 118 # FU busy when requested system.cpu.iq.fu_busy_rate 0.010920 # FU busy rate (busy events/executed inst) system.cpu.iq.int_inst_queue_reads 36268 # Number of integer instruction queue reads @@ -428,13 +413,13 @@ system.cpu.iew.exec_nop 86 # nu system.cpu.iew.exec_refs 3233 # number of memory reference insts executed system.cpu.iew.exec_branches 1613 # Number of branches executed system.cpu.iew.exec_stores 1101 # Number of stores executed -system.cpu.iew.exec_rate 0.316699 # Inst execution rate +system.cpu.iew.exec_rate 0.316521 # Inst execution rate system.cpu.iew.wb_sent 9857 # cumulative count of insts sent to commit system.cpu.iew.wb_count 9710 # cumulative count of insts written-back system.cpu.iew.wb_producers 5134 # num instructions producing a value system.cpu.iew.wb_consumers 6919 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.302851 # insts written-back per cycle +system.cpu.iew.wb_rate 0.302681 # insts written-back per cycle system.cpu.iew.wb_fanout 0.742015 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitSquashedInsts 6741 # The number of squashed insts skipped by commit @@ -472,14 +457,14 @@ system.cpu.commit.bw_limited 0 # nu system.cpu.rob.rob_reads 25928 # The number of ROB reads system.cpu.rob.rob_writes 27481 # The number of ROB writes system.cpu.timesIdled 265 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 17553 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 17571 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 6372 # Number of Instructions Simulated system.cpu.committedOps 6372 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 6372 # Number of Instructions Simulated -system.cpu.cpi 5.031701 # CPI: Cycles Per Instruction -system.cpu.cpi_total 5.031701 # CPI: Total CPI of All Threads -system.cpu.ipc 0.198740 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.198740 # IPC: Total IPC of All Threads +system.cpu.cpi 5.034526 # CPI: Cycles Per Instruction +system.cpu.cpi_total 5.034526 # CPI: Total CPI of All Threads +system.cpu.ipc 0.198628 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.198628 # IPC: Total IPC of All Threads system.cpu.int_regfile_reads 12888 # number of integer regfile reads system.cpu.int_regfile_writes 7343 # number of integer regfile writes system.cpu.fp_regfile_reads 8 # number of floating regfile reads @@ -487,14 +472,14 @@ system.cpu.fp_regfile_writes 2 # nu system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 159.192237 # Cycle average of tags in use +system.cpu.icache.tagsinuse 159.281471 # Cycle average of tags in use system.cpu.icache.total_refs 1869 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 313 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 5.971246 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 159.192237 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.077731 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.077731 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 159.281471 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.077774 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.077774 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 1869 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 1869 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 1869 # number of demand (read+write) hits @@ -507,12 +492,12 @@ system.cpu.icache.demand_misses::cpu.inst 480 # n system.cpu.icache.demand_misses::total 480 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 480 # number of overall misses system.cpu.icache.overall_misses::total 480 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 22202500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 22202500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 22202500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 22202500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 22202500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 22202500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 22197500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 22197500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 22197500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 22197500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 22197500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 22197500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 2349 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 2349 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 2349 # number of demand (read+write) accesses @@ -525,12 +510,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.204342 system.cpu.icache.demand_miss_rate::total 0.204342 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.204342 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.204342 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 46255.208333 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 46255.208333 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 46255.208333 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 46255.208333 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 46255.208333 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 46255.208333 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 46244.791667 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 46244.791667 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 46244.791667 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 46244.791667 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 46244.791667 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 46244.791667 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -551,36 +536,36 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 313 system.cpu.icache.demand_mshr_misses::total 313 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 313 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 313 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16102000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 16102000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16102000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 16102000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16102000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 16102000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16111000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 16111000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16111000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 16111000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16111000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 16111000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.133248 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.133248 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.133248 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.133248 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.133248 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.133248 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51444.089457 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51444.089457 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51444.089457 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 51444.089457 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51444.089457 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 51444.089457 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51472.843450 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51472.843450 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51472.843450 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 51472.843450 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51472.843450 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 51472.843450 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 219.643453 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 219.754912 # Cycle average of tags in use system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 413 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.002421 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 159.327355 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 60.316098 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004862 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 159.415983 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 60.338929 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004865 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.001841 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.006703 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.006706 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits @@ -598,17 +583,17 @@ system.cpu.l2cache.demand_misses::total 486 # nu system.cpu.l2cache.overall_misses::cpu.inst 312 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 174 # number of overall misses system.cpu.l2cache.overall_misses::total 486 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15777000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15786000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6080500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 21857500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 21866500 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3687500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 3687500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 15777000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 15786000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 9768000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 25545000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 15777000 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::total 25554000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 15786000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 9768000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 25545000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 25554000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 313 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 101 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 414 # number of ReadReq accesses(hits+misses) @@ -631,17 +616,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.997947 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996805 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.997947 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50567.307692 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50596.153846 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 60202.970297 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52923.728814 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52945.520581 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50513.698630 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50513.698630 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50567.307692 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50596.153846 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 56137.931034 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52561.728395 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50567.307692 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52580.246914 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50596.153846 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 56137.931034 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52561.728395 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52580.246914 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -661,17 +646,17 @@ system.cpu.l2cache.demand_mshr_misses::total 486 system.cpu.l2cache.overall_mshr_misses::cpu.inst 312 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 174 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 486 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11907990 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4848832 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 16756822 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2795812 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2795812 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11907990 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7644644 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 19552634 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11907990 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7644644 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 19552634 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11916495 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4848791 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 16765286 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2795781 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2795781 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11916495 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7644572 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 19561067 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11916495 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7644572 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 19561067 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997585 # mshr miss rate for ReadReq accesses @@ -683,27 +668,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.997947 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.997947 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38166.634615 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 48008.237624 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40573.418886 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 38298.794521 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 38298.794521 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38166.634615 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43934.735632 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40231.757202 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38166.634615 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43934.735632 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40231.757202 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38193.894231 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 48007.831683 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40593.912833 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 38298.369863 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 38298.369863 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38193.894231 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43934.321839 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40249.109053 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38193.894231 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43934.321839 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40249.109053 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 107.713176 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 107.750370 # Cycle average of tags in use system.cpu.dcache.total_refs 2262 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 174 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 13 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 107.713176 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.026297 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.026297 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 107.750370 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.026306 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.026306 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 1756 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1756 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 506 # number of WriteReq hits diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt index 6b89534e6..c84a7ed5c 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000009 # Nu sim_ticks 9350000 # Number of ticks simulated final_tick 9350000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 146 # Simulator instruction rate (inst/s) -host_op_rate 146 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 570039 # Simulator tick rate (ticks/s) -host_mem_usage 224412 # Number of bytes of host memory used -host_seconds 16.40 # Real time elapsed on the host +host_inst_rate 55287 # Simulator instruction rate (inst/s) +host_op_rate 55271 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 216439769 # Simulator tick rate (ticks/s) +host_mem_usage 224436 # Number of bytes of host memory used +host_seconds 0.04 # Real time elapsed on the host sim_insts 2387 # Number of instructions simulated sim_ops 2387 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 11968 # Number of bytes read from this memory @@ -78,26 +78,13 @@ system.physmem.readPktSize::3 0 # Ca system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes system.physmem.readPktSize::6 272 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 0 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 0 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 0 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 0 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 0 # Categorize write packet sizes system.physmem.rdQLenPdf::0 148 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 87 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 26 # What read queue length does an incoming req see @@ -130,7 +117,6 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see @@ -163,15 +149,14 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 1329022 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 7872772 # Sum of mem lat for all requests +system.physmem.totQLat 1328750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 7872500 # Sum of mem lat for all requests system.physmem.totBusLat 1360000 # Total cycles spent in databus access system.physmem.totBankLat 5183750 # Total cycles spent in bank access -system.physmem.avgQLat 4886.11 # Average queueing delay per request +system.physmem.avgQLat 4885.11 # Average queueing delay per request system.physmem.avgBankLat 19057.90 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 28944.01 # Average memory access latency +system.physmem.avgMemAccLat 28943.01 # Average memory access latency system.physmem.avgRdBW 1861.82 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 1861.82 # Average consumed read bandwidth in MB/s @@ -571,13 +556,13 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51481.278075 system.cpu.icache.overall_avg_mshr_miss_latency::total 51481.278075 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 119.099628 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 119.099647 # Cycle average of tags in use system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 248 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 91.174739 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 27.924890 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 91.174754 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 27.924893 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::cpu.inst 0.002782 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.000852 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::total 0.003635 # Average percentage of cache occupancy @@ -655,17 +640,17 @@ system.cpu.l2cache.demand_mshr_misses::total 272 system.cpu.l2cache.overall_mshr_misses::cpu.inst 187 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 272 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 7118288 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2838816 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 9957104 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1114024 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1114024 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 7118288 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3952840 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 11071128 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 7118288 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3952840 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 11071128 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 7118144 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2838783 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 9956927 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1114012 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1114012 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 7118144 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3952795 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 11070939 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 7118144 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3952795 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 11070939 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -677,17 +662,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 1 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38065.711230 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 46537.967213 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40149.612903 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 46417.666667 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 46417.666667 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38065.711230 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 46504 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40702.676471 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38065.711230 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 46504 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40702.676471 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38064.941176 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 46537.426230 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40148.899194 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 46417.166667 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 46417.166667 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38064.941176 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 46503.470588 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40701.981618 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38064.941176 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 46503.470588 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40701.981618 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.tagsinuse 44.507812 # Cycle average of tags in use diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt index 80cf199ee..ed4523776 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000014 # Nu sim_ticks 13709000 # Number of ticks simulated final_tick 13709000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 51480 # Simulator instruction rate (inst/s) -host_op_rate 64222 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 153638426 # Simulator tick rate (ticks/s) -host_mem_usage 239936 # Number of bytes of host memory used -host_seconds 0.09 # Real time elapsed on the host +host_inst_rate 31817 # Simulator instruction rate (inst/s) +host_op_rate 39697 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 94976589 # Simulator tick rate (ticks/s) +host_mem_usage 239960 # Number of bytes of host memory used +host_seconds 0.14 # Real time elapsed on the host sim_insts 4591 # Number of instructions simulated sim_ops 5729 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 17408 # Number of bytes read from this memory @@ -78,26 +78,13 @@ system.physmem.readPktSize::3 0 # Ca system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes system.physmem.readPktSize::6 394 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 0 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 0 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 0 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 0 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 0 # Categorize write packet sizes system.physmem.rdQLenPdf::0 194 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 127 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 45 # What read queue length does an incoming req see @@ -130,7 +117,6 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see @@ -163,15 +149,14 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 2508144 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 11751894 # Sum of mem lat for all requests +system.physmem.totQLat 2507750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 11751500 # Sum of mem lat for all requests system.physmem.totBusLat 1970000 # Total cycles spent in databus access system.physmem.totBankLat 7273750 # Total cycles spent in bank access -system.physmem.avgQLat 6365.85 # Average queueing delay per request +system.physmem.avgQLat 6364.85 # Average queueing delay per request system.physmem.avgBankLat 18461.29 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 29827.14 # Average memory access latency +system.physmem.avgMemAccLat 29826.14 # Average memory access latency system.physmem.avgRdBW 1839.38 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 1839.38 # Average consumed read bandwidth in MB/s @@ -624,13 +609,13 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50146.048110 system.cpu.icache.overall_avg_mshr_miss_latency::total 50146.048110 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 185.063220 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 185.063238 # Cycle average of tags in use system.cpu.l2cache.total_refs 39 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 353 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.110482 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 138.360527 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 46.702693 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 138.360542 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 46.702695 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::cpu.inst 0.004222 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.001425 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::total 0.005648 # Average percentage of cache occupancy @@ -723,17 +708,17 @@ system.cpu.l2cache.demand_mshr_misses::total 394 system.cpu.l2cache.overall_mshr_misses::cpu.inst 272 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 122 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 394 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10736168 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3756318 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14492486 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1896792 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1896792 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10736168 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5653110 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 16389278 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10736168 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5653110 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 16389278 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10735959 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3756284 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14492243 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1896771 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1896771 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10735959 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5653055 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 16389014 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10735959 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5653055 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 16389014 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.934708 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.764151 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.889169 # mshr miss rate for ReadReq accesses @@ -745,17 +730,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.899543 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.934708 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.899543 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39471.205882 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 46374.296296 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41055.201133 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 46263.219512 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 46263.219512 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39471.205882 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 46336.967213 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 41597.152284 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39471.205882 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 46336.967213 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41597.152284 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39470.437500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 46373.876543 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41054.512748 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 46262.707317 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 46262.707317 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39470.437500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 46336.516393 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 41596.482234 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39470.437500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 46336.516393 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41596.482234 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.tagsinuse 86.502557 # Cycle average of tags in use diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt index 13489057c..ef2f22c88 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000014 # Nu sim_ticks 13709000 # Number of ticks simulated final_tick 13709000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 58002 # Simulator instruction rate (inst/s) -host_op_rate 72354 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 173086159 # Simulator tick rate (ticks/s) -host_mem_usage 238920 # Number of bytes of host memory used -host_seconds 0.08 # Real time elapsed on the host +host_inst_rate 36221 # Simulator instruction rate (inst/s) +host_op_rate 45190 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 108117571 # Simulator tick rate (ticks/s) +host_mem_usage 238932 # Number of bytes of host memory used +host_seconds 0.13 # Real time elapsed on the host sim_insts 4591 # Number of instructions simulated sim_ops 5729 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 17408 # Number of bytes read from this memory @@ -78,26 +78,13 @@ system.physmem.readPktSize::3 0 # Ca system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes system.physmem.readPktSize::6 394 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 0 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 0 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 0 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 0 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 0 # Categorize write packet sizes system.physmem.rdQLenPdf::0 194 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 127 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 45 # What read queue length does an incoming req see @@ -130,7 +117,6 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see @@ -163,15 +149,14 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 2508144 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 11751894 # Sum of mem lat for all requests +system.physmem.totQLat 2507750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 11751500 # Sum of mem lat for all requests system.physmem.totBusLat 1970000 # Total cycles spent in databus access system.physmem.totBankLat 7273750 # Total cycles spent in bank access -system.physmem.avgQLat 6365.85 # Average queueing delay per request +system.physmem.avgQLat 6364.85 # Average queueing delay per request system.physmem.avgBankLat 18461.29 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 29827.14 # Average memory access latency +system.physmem.avgMemAccLat 29826.14 # Average memory access latency system.physmem.avgRdBW 1839.38 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 1839.38 # Average consumed read bandwidth in MB/s @@ -579,13 +564,13 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50146.048110 system.cpu.icache.overall_avg_mshr_miss_latency::total 50146.048110 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 185.063220 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 185.063238 # Cycle average of tags in use system.cpu.l2cache.total_refs 39 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 353 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.110482 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 138.360527 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 46.702693 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 138.360542 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 46.702695 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::cpu.inst 0.004222 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.001425 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::total 0.005648 # Average percentage of cache occupancy @@ -678,17 +663,17 @@ system.cpu.l2cache.demand_mshr_misses::total 394 system.cpu.l2cache.overall_mshr_misses::cpu.inst 272 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 122 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 394 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10736168 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3756318 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14492486 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1896792 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1896792 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10736168 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5653110 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 16389278 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10736168 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5653110 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 16389278 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10735959 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3756284 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14492243 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1896771 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1896771 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10735959 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5653055 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 16389014 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10735959 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5653055 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 16389014 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.934708 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.764151 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.889169 # mshr miss rate for ReadReq accesses @@ -700,17 +685,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.899543 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.934708 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.899543 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39471.205882 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 46374.296296 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41055.201133 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 46263.219512 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 46263.219512 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39471.205882 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 46336.967213 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 41597.152284 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39471.205882 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 46336.967213 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41597.152284 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39470.437500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 46373.876543 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41054.512748 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 46262.707317 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 46262.707317 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39470.437500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 46336.516393 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 41596.482234 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39470.437500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 46336.516393 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41596.482234 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.tagsinuse 86.502557 # Cycle average of tags in use diff --git a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt index 4baa76c40..d65cf38dc 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000019 # Nu sim_ticks 19339000 # Number of ticks simulated final_tick 19339000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 100636 # Simulator instruction rate (inst/s) -host_op_rate 100592 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 334460805 # Simulator tick rate (ticks/s) -host_mem_usage 224316 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host +host_inst_rate 54855 # Simulator instruction rate (inst/s) +host_op_rate 54842 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 182382541 # Simulator tick rate (ticks/s) +host_mem_usage 224336 # Number of bytes of host memory used +host_seconds 0.11 # Real time elapsed on the host sim_insts 5814 # Number of instructions simulated sim_ops 5814 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 20288 # Number of bytes read from this memory @@ -78,26 +78,13 @@ system.physmem.readPktSize::3 0 # Ca system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes system.physmem.readPktSize::6 455 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 0 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 0 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 0 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 0 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 0 # Categorize write packet sizes system.physmem.rdQLenPdf::0 293 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 131 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 23 # What read queue length does an incoming req see @@ -130,7 +117,6 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see @@ -163,15 +149,14 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 2650454 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 13959204 # Sum of mem lat for all requests +system.physmem.totQLat 2650000 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 13958750 # Sum of mem lat for all requests system.physmem.totBusLat 2275000 # Total cycles spent in databus access system.physmem.totBankLat 9033750 # Total cycles spent in bank access -system.physmem.avgQLat 5825.17 # Average queueing delay per request +system.physmem.avgQLat 5824.18 # Average queueing delay per request system.physmem.avgBankLat 19854.40 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 30679.57 # Average memory access latency +system.physmem.avgMemAccLat 30678.57 # Average memory access latency system.physmem.avgRdBW 1505.77 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 1505.77 # Average consumed read bandwidth in MB/s @@ -358,13 +343,13 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54322.884013 system.cpu.icache.overall_avg_mshr_miss_latency::total 54322.884013 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 206.866516 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 206.866533 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 404 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.004950 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 151.045976 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 55.820540 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 151.045990 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 55.820543 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::cpu.inst 0.004610 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.001704 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::total 0.006313 # Average percentage of cache occupancy @@ -448,17 +433,17 @@ system.cpu.l2cache.demand_mshr_misses::total 455 system.cpu.l2cache.overall_mshr_misses::cpu.inst 317 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 455 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 13055529 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4090608 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 17146137 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1925076 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1925076 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 13055529 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6015684 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 19071213 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 13055529 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6015684 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 19071213 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 13055265 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4090554 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 17145819 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1925038 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1925038 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 13055265 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6015592 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 19070857 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 13055265 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6015592 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 19070857 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993730 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.995074 # mshr miss rate for ReadReq accesses @@ -470,17 +455,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.995624 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993730 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.995624 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41184.634069 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 47018.482759 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 42440.933168 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 37746.588235 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 37746.588235 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41184.634069 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43591.913043 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 41914.753846 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41184.634069 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43591.913043 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41914.753846 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41183.801262 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 47017.862069 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 42440.146040 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 37745.843137 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 37745.843137 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41183.801262 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43591.246377 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 41913.971429 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41183.801262 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43591.246377 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41913.971429 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.tagsinuse 89.917113 # Cycle average of tags in use diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt index 7feba62df..13fbe689c 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000017 # Nu sim_ticks 17026500 # Number of ticks simulated final_tick 17026500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 76348 # Simulator instruction rate (inst/s) -host_op_rate 76319 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 251939378 # Simulator tick rate (ticks/s) -host_mem_usage 226380 # Number of bytes of host memory used -host_seconds 0.07 # Real time elapsed on the host +host_inst_rate 44899 # Simulator instruction rate (inst/s) +host_op_rate 44889 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 148205995 # Simulator tick rate (ticks/s) +host_mem_usage 226388 # Number of bytes of host memory used +host_seconds 0.12 # Real time elapsed on the host sim_insts 5156 # Number of instructions simulated sim_ops 5156 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 21504 # Number of bytes read from this memory @@ -78,26 +78,13 @@ system.physmem.readPktSize::3 0 # Ca system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes system.physmem.readPktSize::6 478 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 0 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 0 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 0 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 0 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 0 # Categorize write packet sizes system.physmem.rdQLenPdf::0 253 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 152 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 48 # What read queue length does an incoming req see @@ -130,7 +117,6 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see @@ -163,15 +149,14 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 2863474 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 14617224 # Sum of mem lat for all requests +system.physmem.totQLat 2863000 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 14616750 # Sum of mem lat for all requests system.physmem.totBusLat 2390000 # Total cycles spent in databus access system.physmem.totBankLat 9363750 # Total cycles spent in bank access -system.physmem.avgQLat 5990.53 # Average queueing delay per request +system.physmem.avgQLat 5989.54 # Average queueing delay per request system.physmem.avgBankLat 19589.44 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 30579.97 # Average memory access latency +system.physmem.avgMemAccLat 30578.97 # Average memory access latency system.physmem.avgRdBW 1796.73 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 1796.73 # Average consumed read bandwidth in MB/s @@ -556,13 +541,13 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52572.271386 system.cpu.icache.overall_avg_mshr_miss_latency::total 52572.271386 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 222.426618 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 222.426637 # Cycle average of tags in use system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 427 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.007026 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 164.638321 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 57.788297 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 164.638337 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 57.788300 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::cpu.inst 0.005024 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.001764 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::total 0.006788 # Average percentage of cache occupancy @@ -646,17 +631,17 @@ system.cpu.l2cache.demand_mshr_misses::total 478 system.cpu.l2cache.overall_mshr_misses::cpu.inst 336 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 478 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 13273303 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4804087 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 18077390 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2032056 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2032056 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 13273303 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6836143 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 20109446 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 13273303 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6836143 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 20109446 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 13273027 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4804044 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 18077071 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2032028 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2032028 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 13273027 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6836072 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 20109099 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 13273027 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6836072 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 20109099 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.991150 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.993023 # mshr miss rate for ReadReq accesses @@ -668,17 +653,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.993763 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.991150 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.993763 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39503.877976 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 52792.164835 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 42335.807963 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39844.235294 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39844.235294 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39503.877976 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 48141.852113 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42069.970711 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39503.877976 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 48141.852113 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42069.970711 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39503.056548 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 52791.692308 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 42335.060890 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39843.686275 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39843.686275 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39503.056548 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 48141.352113 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42069.244770 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39503.056548 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 48141.352113 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42069.244770 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.tagsinuse 91.642501 # Cycle average of tags in use diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt index ccc0289be..69396a815 100644 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000015 # Nu sim_ticks 14724500 # Number of ticks simulated final_tick 14724500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 87376 # Simulator instruction rate (inst/s) -host_op_rate 87343 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 221965921 # Simulator tick rate (ticks/s) -host_mem_usage 222644 # Number of bytes of host memory used -host_seconds 0.07 # Real time elapsed on the host +host_inst_rate 62176 # Simulator instruction rate (inst/s) +host_op_rate 62167 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 158021685 # Simulator tick rate (ticks/s) +host_mem_usage 222660 # Number of bytes of host memory used +host_seconds 0.09 # Real time elapsed on the host sim_insts 5792 # Number of instructions simulated sim_ops 5792 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 22080 # Number of bytes read from this memory @@ -78,26 +78,13 @@ system.physmem.readPktSize::3 0 # Ca system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes system.physmem.readPktSize::6 446 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 0 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 0 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 0 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 0 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 0 # Categorize write packet sizes system.physmem.rdQLenPdf::0 232 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 147 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 48 # What read queue length does an incoming req see @@ -130,7 +117,6 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see @@ -163,15 +149,14 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 2286195 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 12779945 # Sum of mem lat for all requests +system.physmem.totQLat 2285750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 12779500 # Sum of mem lat for all requests system.physmem.totBusLat 2230000 # Total cycles spent in databus access system.physmem.totBankLat 8263750 # Total cycles spent in bank access -system.physmem.avgQLat 5126.00 # Average queueing delay per request +system.physmem.avgQLat 5125.00 # Average queueing delay per request system.physmem.avgBankLat 18528.59 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 28654.59 # Average memory access latency +system.physmem.avgMemAccLat 28653.59 # Average memory access latency system.physmem.avgRdBW 1938.54 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 1938.54 # Average consumed read bandwidth in MB/s @@ -553,13 +538,13 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50659.544160 system.cpu.icache.overall_avg_mshr_miss_latency::total 50659.544160 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 198.145802 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 198.145822 # Cycle average of tags in use system.cpu.l2cache.total_refs 7 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 399 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.017544 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 166.786148 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 31.359654 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 166.786167 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 31.359655 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::cpu.inst 0.005090 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.000957 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::total 0.006047 # Average percentage of cache occupancy @@ -646,17 +631,17 @@ system.cpu.l2cache.demand_mshr_misses::total 446 system.cpu.l2cache.overall_mshr_misses::cpu.inst 345 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 101 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 446 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 13081037 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2509304 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15590341 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2332794 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2332794 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 13081037 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4842098 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 17923135 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 13081037 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4842098 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 17923135 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 13080769 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2509277 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15590046 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2332772 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2332772 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 13080769 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4842049 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 17922818 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 13080769 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4842049 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 17922818 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.982906 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.981818 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.982759 # mshr miss rate for ReadReq accesses @@ -668,17 +653,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.984547 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.982906 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.990196 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.984547 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37916.049275 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 46468.592593 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39073.536341 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49633.914894 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49633.914894 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37916.049275 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 47941.564356 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40186.401345 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37916.049275 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 47941.564356 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40186.401345 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37915.272464 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 46468.092593 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39072.796992 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49633.446809 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49633.446809 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37915.272464 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 47941.079208 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40185.690583 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37915.272464 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 47941.079208 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40185.690583 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.tagsinuse 63.324462 # Cycle average of tags in use diff --git a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt index a586f3039..d53327dbb 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000017 # Nu sim_ticks 16783500 # Number of ticks simulated final_tick 16783500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 84096 # Simulator instruction rate (inst/s) -host_op_rate 84062 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 264753473 # Simulator tick rate (ticks/s) -host_mem_usage 230292 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host +host_inst_rate 48421 # Simulator instruction rate (inst/s) +host_op_rate 48416 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 152524495 # Simulator tick rate (ticks/s) +host_mem_usage 230316 # Number of bytes of host memory used +host_seconds 0.11 # Real time elapsed on the host sim_insts 5327 # Number of instructions simulated sim_ops 5327 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 18496 # Number of bytes read from this memory @@ -78,26 +78,13 @@ system.physmem.readPktSize::3 0 # Ca system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes system.physmem.readPktSize::6 423 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 0 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 0 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 0 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 0 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 0 # Categorize write packet sizes system.physmem.rdQLenPdf::0 246 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 124 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 36 # What read queue length does an incoming req see @@ -130,7 +117,6 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see @@ -163,15 +149,14 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 2673172 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 12996922 # Sum of mem lat for all requests +system.physmem.totQLat 2672750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 12996500 # Sum of mem lat for all requests system.physmem.totBusLat 2115000 # Total cycles spent in databus access system.physmem.totBankLat 8208750 # Total cycles spent in bank access -system.physmem.avgQLat 6319.56 # Average queueing delay per request +system.physmem.avgQLat 6318.56 # Average queueing delay per request system.physmem.avgBankLat 19406.03 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 30725.58 # Average memory access latency +system.physmem.avgMemAccLat 30724.59 # Average memory access latency system.physmem.avgRdBW 1613.01 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 1613.01 # Average consumed read bandwidth in MB/s @@ -340,13 +325,13 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53000 system.cpu.icache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 167.397199 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 167.397215 # Cycle average of tags in use system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 342 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.008772 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 140.660988 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 26.736211 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 140.661002 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 26.736213 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::cpu.inst 0.004293 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.000816 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::total 0.005109 # Average percentage of cache occupancy @@ -433,17 +418,17 @@ system.cpu.l2cache.demand_mshr_misses::total 423 system.cpu.l2cache.overall_mshr_misses::cpu.inst 289 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 423 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11527456 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2665331 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14192787 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3719824 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3719824 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11527456 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6385155 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 17912611 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11527456 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6385155 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 17912611 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11527228 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2665291 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14192519 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3719787 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3719787 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11527228 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6385078 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 17912306 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11527228 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6385078 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 17912306 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993127 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.981481 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.991304 # mshr miss rate for ReadReq accesses @@ -455,17 +440,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.992958 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993127 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.992593 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.992958 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39887.391003 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 50289.264151 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41499.377193 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 45923.753086 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 45923.753086 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39887.391003 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 47650.410448 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42346.598109 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39887.391003 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 47650.410448 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42346.598109 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39886.602076 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 50288.509434 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41498.593567 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 45923.296296 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 45923.296296 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39886.602076 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 47649.835821 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42345.877069 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39886.602076 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 47649.835821 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42345.877069 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.tagsinuse 84.137936 # Cycle average of tags in use diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt index b6a3a3279..03f9c34cb 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt @@ -4,10 +4,10 @@ sim_seconds 0.000015 # Nu sim_ticks 15468000 # Number of ticks simulated final_tick 15468000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 31666 # Simulator instruction rate (inst/s) -host_op_rate 57357 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 91020367 # Simulator tick rate (ticks/s) -host_mem_usage 241544 # Number of bytes of host memory used +host_inst_rate 31901 # Simulator instruction rate (inst/s) +host_op_rate 57781 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 91692634 # Simulator tick rate (ticks/s) +host_mem_usage 241568 # Number of bytes of host memory used host_seconds 0.17 # Real time elapsed on the host sim_insts 5380 # Number of instructions simulated sim_ops 9746 # Number of ops (including micro ops) simulated @@ -78,26 +78,13 @@ system.physmem.readPktSize::3 0 # Ca system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes system.physmem.readPktSize::6 451 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 0 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 0 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 0 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 0 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 0 # Categorize write packet sizes system.physmem.rdQLenPdf::0 231 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 151 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 58 # What read queue length does an incoming req see @@ -130,7 +117,6 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see @@ -163,15 +149,14 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 1899951 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 13161201 # Sum of mem lat for all requests +system.physmem.totQLat 1899500 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 13160750 # Sum of mem lat for all requests system.physmem.totBusLat 2255000 # Total cycles spent in databus access system.physmem.totBankLat 9006250 # Total cycles spent in bank access -system.physmem.avgQLat 4212.75 # Average queueing delay per request +system.physmem.avgQLat 4211.75 # Average queueing delay per request system.physmem.avgBankLat 19969.51 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 29182.26 # Average memory access latency +system.physmem.avgMemAccLat 29181.26 # Average memory access latency system.physmem.avgRdBW 1857.77 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 1857.77 # Average consumed read bandwidth in MB/s @@ -536,13 +521,13 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53148.026316 system.cpu.icache.overall_avg_mshr_miss_latency::total 53148.026316 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 177.982441 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 177.982459 # Cycle average of tags in use system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 373 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.002681 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 144.961595 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 33.020847 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 144.961610 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 33.020849 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::cpu.inst 0.004424 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.001008 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::total 0.005432 # Average percentage of cache occupancy @@ -626,17 +611,17 @@ system.cpu.l2cache.demand_mshr_misses::total 451 system.cpu.l2cache.overall_mshr_misses::cpu.inst 303 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 148 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 451 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12092212 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3030082 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15122294 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3058112 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3058112 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12092212 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6088194 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 18180406 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12092212 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6088194 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 18180406 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12091981 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3030041 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15122022 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3058056 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3058056 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12091981 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6088097 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 18180078 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12091981 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6088097 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 18180078 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996711 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997340 # mshr miss rate for ReadReq accesses @@ -648,17 +633,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.997788 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996711 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.997788 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39908.290429 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42084.472222 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40326.117333 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40238.315789 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40238.315789 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39908.290429 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 41136.445946 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40311.321508 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39908.290429 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 41136.445946 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40311.321508 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39907.528053 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42083.902778 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40325.392000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40237.578947 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40237.578947 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39907.528053 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 41135.790541 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40310.594235 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39907.528053 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 41135.790541 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40310.594235 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.tagsinuse 83.496642 # Cycle average of tags in use diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt index 329680740..8505308fc 100644 --- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000024 # Nu sim_ticks 24473000 # Number of ticks simulated final_tick 24473000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 4068 # Simulator instruction rate (inst/s) -host_op_rate 4068 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 7811345 # Simulator tick rate (ticks/s) -host_mem_usage 226312 # Number of bytes of host memory used -host_seconds 3.13 # Real time elapsed on the host +host_inst_rate 87264 # Simulator instruction rate (inst/s) +host_op_rate 87257 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 167537445 # Simulator tick rate (ticks/s) +host_mem_usage 226344 # Number of bytes of host memory used +host_seconds 0.15 # Real time elapsed on the host sim_insts 12745 # Number of instructions simulated sim_ops 12745 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 39808 # Number of bytes read from this memory @@ -78,29 +78,16 @@ system.physmem.readPktSize::3 0 # Ca system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes system.physmem.readPktSize::6 970 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 0 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 0 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 0 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 0 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 0 # Categorize write packet sizes system.physmem.rdQLenPdf::0 166 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 260 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 254 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 261 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 253 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 174 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 86 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 29 # What read queue length does an incoming req see @@ -130,7 +117,6 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see @@ -163,15 +149,14 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 22646466 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 53470216 # Sum of mem lat for all requests +system.physmem.totQLat 22645500 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 53469250 # Sum of mem lat for all requests system.physmem.totBusLat 4850000 # Total cycles spent in databus access system.physmem.totBankLat 25973750 # Total cycles spent in bank access -system.physmem.avgQLat 23346.87 # Average queueing delay per request +system.physmem.avgQLat 23345.88 # Average queueing delay per request system.physmem.avgBankLat 26777.06 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 55123.93 # Average memory access latency +system.physmem.avgMemAccLat 55122.94 # Average memory access latency system.physmem.avgRdBW 2536.67 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 2536.67 # Average consumed read bandwidth in MB/s @@ -717,13 +702,13 @@ system.cpu.icache.no_allocate_misses 0 # Nu system.cpu.l2cache.replacements::0 0 # number of replacements system.cpu.l2cache.replacements::1 0 # number of replacements system.cpu.l2cache.replacements::total 0 # number of replacements -system.cpu.l2cache.tagsinuse 407.828883 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 407.828902 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 824 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.002427 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 293.011617 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 114.817266 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 293.011633 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 114.817269 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::cpu.inst 0.008942 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.003504 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::total 0.012446 # Average percentage of cache occupancy @@ -807,17 +792,17 @@ system.cpu.l2cache.demand_mshr_misses::total 970 system.cpu.l2cache.overall_mshr_misses::cpu.inst 622 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 348 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 970 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 40142034 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 15600631 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 55742665 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10339864 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10339864 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 40142034 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 25940495 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 66082529 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 40142034 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 25940495 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 66082529 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 40141642 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 15600566 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 55742208 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10339807 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10339807 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 40141642 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 25940373 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 66082015 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 40141642 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 25940373 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 66082015 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996795 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997579 # mshr miss rate for ReadReq accesses @@ -829,17 +814,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.997942 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996795 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.997942 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64537.032154 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 77230.846535 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67648.865291 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70820.986301 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70820.986301 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64537.032154 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 74541.652299 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68126.318557 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64537.032154 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 74541.652299 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68126.318557 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64536.401929 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 77230.524752 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67648.310680 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70820.595890 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70820.595890 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64536.401929 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 74541.301724 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68125.788660 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64536.401929 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 74541.301724 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68125.788660 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements::0 0 # number of replacements system.cpu.dcache.replacements::1 0 # number of replacements diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt index 3cd467a4b..7316b9759 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000023 # Nu sim_ticks 23146500 # Number of ticks simulated final_tick 23146500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 62448 # Simulator instruction rate (inst/s) -host_op_rate 62442 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 95315643 # Simulator tick rate (ticks/s) -host_mem_usage 230224 # Number of bytes of host memory used -host_seconds 0.24 # Real time elapsed on the host +host_inst_rate 95077 # Simulator instruction rate (inst/s) +host_op_rate 95070 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 145124480 # Simulator tick rate (ticks/s) +host_mem_usage 230244 # Number of bytes of host memory used +host_seconds 0.16 # Real time elapsed on the host sim_insts 15162 # Number of instructions simulated sim_ops 15162 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 19072 # Number of bytes read from this memory @@ -78,26 +78,13 @@ system.physmem.readPktSize::3 0 # Ca system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes system.physmem.readPktSize::6 436 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 0 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 0 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 0 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 0 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 0 # Categorize write packet sizes system.physmem.rdQLenPdf::0 272 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 118 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 33 # What read queue length does an incoming req see @@ -130,7 +117,6 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see @@ -163,15 +149,14 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 2156686 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 12064186 # Sum of mem lat for all requests +system.physmem.totQLat 2156250 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 12063750 # Sum of mem lat for all requests system.physmem.totBusLat 2180000 # Total cycles spent in databus access system.physmem.totBankLat 7727500 # Total cycles spent in bank access -system.physmem.avgQLat 4946.53 # Average queueing delay per request +system.physmem.avgQLat 4945.53 # Average queueing delay per request system.physmem.avgBankLat 17723.62 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 27670.15 # Average memory access latency +system.physmem.avgMemAccLat 27669.15 # Average memory access latency system.physmem.avgRdBW 1205.54 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 1205.54 # Average consumed read bandwidth in MB/s @@ -340,13 +325,13 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 49700.996678 system.cpu.icache.overall_avg_mshr_miss_latency::total 49700.996678 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 203.582900 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 203.582912 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 351 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.005698 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 171.517590 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 32.065310 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 171.517600 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 32.065312 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::cpu.inst 0.005234 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.000979 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::total 0.006213 # Average percentage of cache occupancy @@ -430,17 +415,17 @@ system.cpu.l2cache.demand_mshr_misses::total 437 system.cpu.l2cache.overall_mshr_misses::cpu.inst 299 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 437 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10987236 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2575826 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13563062 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3583070 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3583070 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10987236 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6158896 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 17146132 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10987236 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6158896 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 17146132 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10986993 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2575788 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13562781 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3583035 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3583035 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10986993 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6158823 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 17145816 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10986993 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6158823 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 17145816 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993355 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.994350 # mshr miss rate for ReadReq accesses @@ -452,17 +437,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.995444 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993355 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.995444 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 36746.608696 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 48600.490566 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 38531.426136 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42153.764706 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42153.764706 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 36746.608696 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 44629.681159 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39236 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 36746.608696 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 44629.681159 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39236 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 36745.795987 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 48599.773585 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 38530.627841 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42153.352941 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42153.352941 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 36745.795987 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 44629.152174 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39235.276888 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 36745.795987 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 44629.152174 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39235.276888 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.tagsinuse 99.212064 # Cycle average of tags in use diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt index cd86d7e47..eaa2ab26e 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt @@ -4,10 +4,10 @@ sim_seconds 0.000024 # Nu sim_ticks 23775500 # Number of ticks simulated final_tick 23775500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 69212 # Simulator instruction rate (inst/s) -host_op_rate 69204 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 113962469 # Simulator tick rate (ticks/s) -host_mem_usage 232268 # Number of bytes of host memory used +host_inst_rate 69027 # Simulator instruction rate (inst/s) +host_op_rate 69023 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 113671122 # Simulator tick rate (ticks/s) +host_mem_usage 232284 # Number of bytes of host memory used host_seconds 0.21 # Real time elapsed on the host sim_insts 14436 # Number of instructions simulated sim_ops 14436 # Number of ops (including micro ops) simulated @@ -78,26 +78,13 @@ system.physmem.readPktSize::3 0 # Ca system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes system.physmem.readPktSize::6 483 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 0 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 0 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 0 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 0 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 0 # Categorize write packet sizes system.physmem.rdQLenPdf::0 273 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 136 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 57 # What read queue length does an incoming req see @@ -130,7 +117,6 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see @@ -163,15 +149,14 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 4632480 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 15613730 # Sum of mem lat for all requests +system.physmem.totQLat 4632000 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 15613250 # Sum of mem lat for all requests system.physmem.totBusLat 2415000 # Total cycles spent in databus access system.physmem.totBankLat 8566250 # Total cycles spent in bank access -system.physmem.avgQLat 9591.06 # Average queueing delay per request +system.physmem.avgQLat 9590.06 # Average queueing delay per request system.physmem.avgBankLat 17735.51 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 32326.56 # Average memory access latency +system.physmem.avgMemAccLat 32325.57 # Average memory access latency system.physmem.avgRdBW 1300.16 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 1300.16 # Average consumed read bandwidth in MB/s @@ -533,13 +518,13 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52118.343195 system.cpu.icache.overall_avg_mshr_miss_latency::total 52118.343195 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 224.642209 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 224.642221 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 400 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.005000 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 189.932225 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 34.709984 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 189.932236 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 34.709985 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::cpu.inst 0.005796 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.001059 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::total 0.006856 # Average percentage of cache occupancy @@ -623,17 +608,17 @@ system.cpu.l2cache.demand_mshr_misses::total 483 system.cpu.l2cache.overall_mshr_misses::cpu.inst 336 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 483 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 13099526 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4042315 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 17141841 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4145826 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4145826 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 13099526 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8188141 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 21287667 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 13099526 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8188141 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 21287667 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 13099263 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4042283 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 17141546 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4145788 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4145788 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 13099263 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8188071 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 21287334 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 13099263 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8188071 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 21287334 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.994083 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.995025 # mshr miss rate for ReadReq accesses @@ -645,17 +630,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.995876 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.994083 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.995876 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38986.684524 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63161.171875 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 42854.602500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49949.710843 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49949.710843 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38986.684524 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 55701.639456 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 44073.844720 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38986.684524 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 55701.639456 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 44073.844720 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38985.901786 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63160.671875 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 42853.865000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49949.253012 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49949.253012 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38985.901786 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 55701.163265 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 44073.155280 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38985.901786 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 55701.163265 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 44073.155280 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.tagsinuse 99.563734 # Cycle average of tags in use diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt index 3dd8cecd5..3eb29c400 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000106 # Nu sim_ticks 105801500 # Number of ticks simulated final_tick 105801500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 99938 # Simulator instruction rate (inst/s) -host_op_rate 99937 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 10207562 # Simulator tick rate (ticks/s) -host_mem_usage 247464 # Number of bytes of host memory used -host_seconds 10.37 # Real time elapsed on the host +host_inst_rate 173787 # Simulator instruction rate (inst/s) +host_op_rate 173787 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 17750545 # Simulator tick rate (ticks/s) +host_mem_usage 247480 # Number of bytes of host memory used +host_seconds 5.96 # Real time elapsed on the host sim_insts 1035849 # Number of instructions simulated sim_ops 1035849 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu0.inst 22848 # Number of bytes read from this memory @@ -59,7 +59,7 @@ system.physmem.bw_total::cpu3.data 7863783 # To system.physmem.bw_total::total 399238196 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 661 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 978 # Reqs generatd by CPU via cache - shady +system.physmem.cpureqs 732 # Reqs generatd by CPU via cache - shady system.physmem.bytesRead 42240 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory system.physmem.bytesConsumedRd 42240 # bytesRead derated as per pkt->getSize() @@ -108,26 +108,13 @@ system.physmem.readPktSize::3 0 # Ca system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes system.physmem.readPktSize::6 661 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 0 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 0 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 71 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 0 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 0 # Categorize write packet sizes system.physmem.rdQLenPdf::0 377 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 205 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 59 # What read queue length does an incoming req see @@ -160,7 +147,6 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see @@ -193,15 +179,14 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 4077160 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 20692160 # Sum of mem lat for all requests +system.physmem.totQLat 4076500 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 20691500 # Sum of mem lat for all requests system.physmem.totBusLat 3305000 # Total cycles spent in databus access system.physmem.totBankLat 13310000 # Total cycles spent in bank access -system.physmem.avgQLat 6168.17 # Average queueing delay per request +system.physmem.avgQLat 6167.17 # Average queueing delay per request system.physmem.avgBankLat 20136.16 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 31304.33 # Average memory access latency +system.physmem.avgMemAccLat 31303.33 # Average memory access latency system.physmem.avgRdBW 399.24 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 399.24 # Average consumed read bandwidth in MB/s @@ -2117,17 +2102,17 @@ system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 9965.116279 system.cpu3.dcache.overall_avg_mshr_miss_latency::total 9965.116279 # average overall mshr miss latency system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.l2c.replacements 0 # number of replacements -system.l2c.tagsinuse 425.230692 # Cycle average of tags in use +system.l2c.tagsinuse 425.230696 # Cycle average of tags in use system.l2c.total_refs 1445 # Total number of references to valid blocks. system.l2c.sampled_refs 527 # Sample count of references to valid blocks. system.l2c.avg_refs 2.741935 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.l2c.occ_blocks::writebacks 0.824596 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 289.832857 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 289.832859 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu0.data 59.073855 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 61.730806 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 61.730807 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu1.data 5.603647 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.inst 4.388881 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2.inst 4.388882 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu2.data 0.760374 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu3.inst 2.293580 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu3.data 0.722095 # Average occupied blocks per requestor @@ -2409,43 +2394,43 @@ system.l2c.overall_mshr_misses::cpu2.data 13 # n system.l2c.overall_mshr_misses::cpu3.inst 3 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu3.data 13 # number of overall MSHR misses system.l2c.overall_mshr_misses::total 661 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 13753074 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 3705088 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 3257128 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 578261 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 230760 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.data 56252 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu3.inst 86256 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu3.data 56252 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 21723071 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 13752787 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 3705044 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 3257064 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 578256 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 230755 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.data 56251 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu3.inst 86253 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu3.data 56251 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 21722661 # number of ReadReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 184010 # number of UpgradeReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 190518 # number of UpgradeReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 161513 # number of UpgradeReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 191511 # number of UpgradeReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_latency::total 727552 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 4247116 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 838760 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 720020 # 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number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 838755 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 720010 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 607510 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 6413333 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 13752787 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 7952102 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 3257064 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 1417011 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.inst 230755 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.data 776261 # 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number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 28135994 # number of overall MSHR miss cycles system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.606780 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.936709 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.188235 # mshr miss rate for ReadReq accesses @@ -2483,43 +2468,43 @@ system.l2c.overall_mshr_miss_rate::cpu2.data 0.541667 system.l2c.overall_mshr_miss_rate::cpu3.inst 0.006993 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::total 0.311792 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 38416.407821 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 50068.756757 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40714.100000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 82608.714286 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 38460 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 56252 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 28752 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 56252 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 40986.926415 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 38415.606145 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 50068.162162 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40713.300000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 82608 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 38459.166667 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 56251 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 28751 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 56251 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40986.152830 # average ReadReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10222.777778 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10027.263158 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10094.562500 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 10639.500000 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10247.211268 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 45182.085106 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 64520 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 60001.666667 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 50626.666667 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 48957.374046 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 38416.407821 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 47334.547619 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40714.100000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 70851.050000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 38460 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 59713.230769 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 28752 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.data 51059.384615 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 42566.546142 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 38416.407821 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 47334.547619 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40714.100000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 70851.050000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 38460 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 59713.230769 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 28752 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.data 51059.384615 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 42566.546142 # average overall mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 45181.468085 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 64519.615385 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 60000.833333 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 50625.833333 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 48956.740458 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 38415.606145 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 47333.940476 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40713.300000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 70850.550000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 38459.166667 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 59712.384615 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 28751 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.data 51058.538462 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 42565.800303 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 38415.606145 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 47333.940476 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40713.300000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 70850.550000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 38459.166667 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 59712.384615 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 28751 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.data 51058.538462 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 42565.800303 # average overall mshr miss latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-dram/stats.txt b/tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-dram/stats.txt index e7866c92f..adb4052b9 100644 --- a/tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-dram/stats.txt +++ b/tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-dram/stats.txt @@ -4,9 +4,9 @@ sim_seconds 0.100000 # Nu sim_ticks 100000000000 # Number of ticks simulated final_tick 100000000000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_tick_rate 29045358432 # Simulator tick rate (ticks/s) -host_mem_usage 222412 # Number of bytes of host memory used -host_seconds 3.44 # Real time elapsed on the host +host_tick_rate 31852968745 # Simulator tick rate (ticks/s) +host_mem_usage 226592 # Number of bytes of host memory used +host_seconds 3.14 # Real time elapsed on the host system.physmem.bytes_read::cpu 213337536 # Number of bytes read from this memory system.physmem.bytes_read::total 213337536 # Number of bytes read from this memory system.physmem.num_reads::cpu 3333399 # Number of read requests responded to by this memory @@ -66,37 +66,24 @@ system.physmem.readPktSize::3 0 # Ca system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes system.physmem.readPktSize::6 3333400 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 0 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 0 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 0 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 0 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 0 # Categorize write packet sizes system.physmem.rdQLenPdf::0 3200711 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 105371 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 4811 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3752 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 4283 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 3751 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 4280 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3757 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 3749 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 3205 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 2146 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 1602 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 2146 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1076 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 2148 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1074 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 546 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see @@ -118,7 +105,6 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see @@ -151,15 +137,14 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 6115686626 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 69505296626 # Sum of mem lat for all requests +system.physmem.totQLat 6112380100 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 69501990100 # Sum of mem lat for all requests system.physmem.totBusLat 16667000000 # Total cycles spent in databus access system.physmem.totBankLat 46722610000 # Total cycles spent in bank access -system.physmem.avgQLat 1834.67 # Average queueing delay per request +system.physmem.avgQLat 1833.68 # Average queueing delay per request system.physmem.avgBankLat 14016.50 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 20851.17 # Average memory access latency +system.physmem.avgMemAccLat 20850.18 # Average memory access latency system.physmem.avgRdBW 2133.38 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 2133.38 # Average consumed read bandwidth in MB/s @@ -278,9 +263,9 @@ system.monitor.writeBandwidthHist::total 100 # Hi system.monitor.averageWriteBandwidth 0 # Average write bandwidth (bytes/s) system.monitor.totalWrittenBytes 0 # Number of bytes written system.monitor.readLatencyHist::samples 3333399 # Read request-response latency -system.monitor.readLatencyHist::mean 20879.051770 # Read request-response latency -system.monitor.readLatencyHist::gmean 19622.150808 # Read request-response latency -system.monitor.readLatencyHist::stdev 15688.008500 # Read request-response latency +system.monitor.readLatencyHist::mean 20878.092191 # Read request-response latency +system.monitor.readLatencyHist::gmean 19621.155070 # Read request-response latency +system.monitor.readLatencyHist::stdev 15688.085413 # Read request-response latency system.monitor.readLatencyHist::0-32767 3201881 96.05% 96.05% # Read request-response latency system.monitor.readLatencyHist::32768-65535 104731 3.14% 99.20% # Read request-response latency system.monitor.readLatencyHist::65536-98303 5355 0.16% 99.36% # Read request-response latency |