diff options
| author | Steve Reinhardt <steve.reinhardt@amd.com> | 2016-03-17 10:32:53 -0700 |
|---|---|---|
| committer | Steve Reinhardt <steve.reinhardt@amd.com> | 2016-03-17 10:32:53 -0700 |
| commit | d7c083864c85c3ab24b40fc85ef3cae8031c5912 (patch) | |
| tree | ae575d831de5d67596ca3aae5e87a71f9c9fd1cd /tests/quick | |
| parent | 9b4249410ec18cac9df2c7e9c0a4a6ce5459233d (diff) | |
| download | gem5-d7c083864c85c3ab24b40fc85ef3cae8031c5912.tar.xz | |
stats: update stats for ld.so support
Additional auxv entries leads to more instructions in start-up
while walking the list, along with different cache conflicts
wrt stack entries.
Diffstat (limited to 'tests/quick')
56 files changed, 5547 insertions, 5519 deletions
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/config.ini index e5dcce47a..a97df4eeb 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/config.ini @@ -135,7 +135,6 @@ clk_domain=system.cpu_clk_domain clusivity=mostly_incl demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=2 is_read_only=false max_miss_count=0 @@ -560,7 +559,6 @@ clk_domain=system.cpu_clk_domain clusivity=mostly_incl demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=2 is_read_only=true max_miss_count=0 @@ -611,7 +609,6 @@ clk_domain=system.cpu_clk_domain clusivity=mostly_incl demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=20 is_read_only=false max_miss_count=0 @@ -646,6 +643,7 @@ clk_domain=system.cpu_clk_domain eventq_index=0 forward_latency=0 frontend_latency=1 +point_of_coherency=false response_latency=1 snoop_filter=system.cpu.toL2Bus.snoop_filter snoop_response_latency=1 @@ -676,7 +674,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello +executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin kvmInSE=false @@ -711,6 +709,7 @@ clk_domain=system.clk_domain eventq_index=0 forward_latency=4 frontend_latency=3 +point_of_coherency=true response_latency=2 snoop_filter=Null snoop_response_latency=4 diff --git a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/simout b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/simout index f7ce5dfcd..7264993fd 100755 --- a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/simout +++ b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/simout @@ -1,13 +1,15 @@ +Redirecting stdout to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/minor-timing/simout +Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/minor-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 21 2016 13:49:21 -gem5 started Jan 21 2016 13:50:03 -gem5 executing on zizzer, pid 34007 -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/minor-timing -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/minor-timing +gem5 compiled Mar 14 2016 21:54:46 +gem5 started Mar 14 2016 21:56:23 +gem5 executing on phenom, pid 28115 +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/minor-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/minor-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 37553000 because target called exit() +Exiting @ tick 37629000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt index 8f96a67ee..60fdb36fc 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000038 # Number of seconds simulated -sim_ticks 37553000 # Number of ticks simulated -final_tick 37553000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 37629000 # Number of ticks simulated +final_tick 37629000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 69445 # Simulator instruction rate (inst/s) -host_op_rate 69425 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 407253641 # Simulator tick rate (ticks/s) -host_mem_usage 231420 # Number of bytes of host memory used -host_seconds 0.09 # Real time elapsed on the host -sim_insts 6400 # Number of instructions simulated -sim_ops 6400 # Number of ops (including micro ops) simulated +host_inst_rate 36642 # Simulator instruction rate (inst/s) +host_op_rate 36638 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 214955628 # Simulator tick rate (ticks/s) +host_mem_usage 227692 # Number of bytes of host memory used +host_seconds 0.18 # Real time elapsed on the host +sim_insts 6413 # Number of instructions simulated +sim_ops 6413 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 23296 # Number of bytes read from this memory @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 23296 # Nu system.physmem.num_reads::cpu.inst 364 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 169 # Number of read requests responded to by this memory system.physmem.num_reads::total 533 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 620349905 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 288019599 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 908369504 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 620349905 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 620349905 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 620349905 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 288019599 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 908369504 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 619096973 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 287437880 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 906534853 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 619096973 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 619096973 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 619096973 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 287437880 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 906534853 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 533 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 533 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 37448500 # Total gap between requests +system.physmem.totGap 37524500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -90,8 +90,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 443 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 85 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 444 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 84 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -186,100 +186,100 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 84 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 384 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 247.290862 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 334.108272 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 20 23.81% 23.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 19 22.62% 46.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 10 11.90% 58.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 11 13.10% 71.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2 2.38% 73.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 5 5.95% 79.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 3 3.57% 83.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 6 7.14% 90.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8 9.52% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 84 # Bytes accessed per row activation -system.physmem.totQLat 3307750 # Total ticks spent queuing -system.physmem.totMemAccLat 13301500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 83 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 388.626506 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 254.752349 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 332.370925 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 18 21.69% 21.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 19 22.89% 44.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 11 13.25% 57.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 11 13.25% 71.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2 2.41% 73.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 5 6.02% 79.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 2 2.41% 81.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 7 8.43% 90.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8 9.64% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 83 # Bytes accessed per row activation +system.physmem.totQLat 3516000 # Total ticks spent queuing +system.physmem.totMemAccLat 13509750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2665000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6205.91 # Average queueing delay per DRAM burst +system.physmem.avgQLat 6596.62 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 24955.91 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 908.37 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 25346.62 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 906.53 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 908.37 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 906.53 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 7.10 # Data bus utilization in percentage -system.physmem.busUtilRead 7.10 # Data bus utilization in percentage for reads +system.physmem.busUtil 7.08 # Data bus utilization in percentage +system.physmem.busUtilRead 7.08 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.19 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 437 # Number of row buffer hits during reads +system.physmem.readRowHits 438 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.99 # Row buffer hit rate for reads +system.physmem.readRowHitRate 82.18 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 70259.85 # Average gap between requests -system.physmem.pageHitRate 81.99 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 226800 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 123750 # Energy for precharge commands per rank (pJ) +system.physmem.avgGap 70402.44 # Average gap between requests +system.physmem.pageHitRate 82.18 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 234360 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 127875 # Energy for precharge commands per rank (pJ) system.physmem_0.readEnergy 2043600 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 2034240 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 21178350 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 265500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 25872240 # Total energy per rank (pJ) -system.physmem_0.averagePower 823.825505 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 346000 # Time in different power states +system.physmem_0.actBackEnergy 21404070 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 67500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 25911645 # Total energy per rank (pJ) +system.physmem_0.averagePower 825.080242 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 105750 # Time in different power states system.physmem_0.memoryStateTime::REF 1040000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 30032750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 30362750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 347760 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 189750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1552200 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 332640 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 181500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1544400 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 2034240 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 20535390 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 831750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 25491090 # Total energy per rank (pJ) -system.physmem_1.averagePower 811.591993 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1333500 # Time in different power states +system.physmem_1.actBackEnergy 20470410 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 886500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 25449690 # Total energy per rank (pJ) +system.physmem_1.averagePower 810.370642 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1337750 # Time in different power states system.physmem_1.memoryStateTime::REF 1040000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 29134000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 29041000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 1929 # Number of BP lookups -system.cpu.branchPred.condPredicted 1187 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 360 # Number of conditional branches incorrect +system.cpu.branchPred.lookups 1942 # Number of BP lookups +system.cpu.branchPred.condPredicted 1197 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 362 # Number of conditional branches incorrect system.cpu.branchPred.BTBLookups 1557 # Number of BTB lookups -system.cpu.branchPred.BTBHits 398 # Number of BTB hits +system.cpu.branchPred.BTBHits 406 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 25.561978 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 224 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 26.075787 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 225 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 14 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 1369 # DTB read hits +system.cpu.dtb.read_hits 1372 # DTB read hits system.cpu.dtb.read_misses 11 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 1380 # DTB read accesses +system.cpu.dtb.read_accesses 1383 # DTB read accesses system.cpu.dtb.write_hits 884 # DTB write hits system.cpu.dtb.write_misses 3 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations system.cpu.dtb.write_accesses 887 # DTB write accesses -system.cpu.dtb.data_hits 2253 # DTB hits +system.cpu.dtb.data_hits 2256 # DTB hits system.cpu.dtb.data_misses 14 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 2267 # DTB accesses -system.cpu.itb.fetch_hits 2651 # ITB hits +system.cpu.dtb.data_accesses 2270 # DTB accesses +system.cpu.itb.fetch_hits 2673 # ITB hits system.cpu.itb.fetch_misses 17 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 2668 # ITB accesses +system.cpu.itb.fetch_accesses 2690 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -293,80 +293,80 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 75106 # number of cpu cycles simulated +system.cpu.numCycles 75258 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 6400 # Number of instructions committed -system.cpu.committedOps 6400 # Number of ops (including micro ops) committed -system.cpu.discardedOps 1085 # Number of ops (including micro ops) which were discarded before commit +system.cpu.committedInsts 6413 # Number of instructions committed +system.cpu.committedOps 6413 # Number of ops (including micro ops) committed +system.cpu.discardedOps 1090 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 11.735312 # CPI: cycles per instruction -system.cpu.ipc 0.085213 # IPC: instructions per cycle -system.cpu.tickCycles 12517 # Number of cycles that the object actually ticked -system.cpu.idleCycles 62589 # Total number of cycles that the object has spent stopped +system.cpu.cpi 11.735225 # CPI: cycles per instruction +system.cpu.ipc 0.085214 # IPC: instructions per cycle +system.cpu.tickCycles 12565 # Number of cycles that the object actually ticked +system.cpu.idleCycles 62693 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 103.920661 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 1972 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 104.289845 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 1974 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 169 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 11.668639 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 11.680473 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 103.920661 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.025371 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.025371 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 104.289845 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.025461 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.025461 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 169 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 147 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.041260 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 4567 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 4567 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 1232 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1232 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 4573 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 4573 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 1234 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1234 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 740 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 740 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 1972 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1972 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1972 # number of overall hits -system.cpu.dcache.overall_hits::total 1972 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 102 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 102 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 1974 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1974 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 1974 # number of overall hits +system.cpu.dcache.overall_hits::total 1974 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 103 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 103 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 125 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 125 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 227 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 227 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 227 # number of overall misses -system.cpu.dcache.overall_misses::total 227 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 8311500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 8311500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 9136500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 9136500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 17448000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 17448000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 17448000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 17448000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1334 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1334 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 228 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 228 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 228 # number of overall misses +system.cpu.dcache.overall_misses::total 228 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 8381500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 8381500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 9164500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 9164500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 17546000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 17546000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 17546000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 17546000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1337 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1337 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2199 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2199 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2199 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2199 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.076462 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.076462 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2202 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2202 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2202 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2202 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.077038 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.077038 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.144509 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.144509 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.103229 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.103229 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.103229 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.103229 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 81485.294118 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 81485.294118 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73092 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 73092 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 76863.436123 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 76863.436123 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 76863.436123 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 76863.436123 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.103542 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.103542 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.103542 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.103542 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 81373.786408 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 81373.786408 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73316 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 73316 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 76956.140351 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 76956.140351 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 76956.140351 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 76956.140351 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -375,14 +375,14 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 6 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 6 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 7 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 7 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 52 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 52 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 58 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 58 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 58 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 58 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 59 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 59 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 59 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 59 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 96 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 96 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses @@ -391,82 +391,82 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 169 system.cpu.dcache.demand_mshr_misses::total 169 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 169 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 169 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7818500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 7818500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5371500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5371500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13190000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 13190000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13190000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 13190000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.071964 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.071964 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7819000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 7819000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5385500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5385500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13204500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 13204500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13204500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 13204500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.071803 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.071803 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.076853 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.076853 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076853 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.076853 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 81442.708333 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 81442.708333 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73582.191781 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73582.191781 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78047.337278 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 78047.337278 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78047.337278 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 78047.337278 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.076748 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.076748 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076748 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.076748 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 81447.916667 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 81447.916667 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73773.972603 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73773.972603 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78133.136095 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 78133.136095 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78133.136095 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 78133.136095 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 175.815240 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 2286 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 175.465909 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 2308 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 365 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 6.263014 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 6.323288 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 175.815240 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.085847 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.085847 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 175.465909 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.085677 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.085677 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 365 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 106 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 259 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.178223 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 5667 # Number of tag accesses -system.cpu.icache.tags.data_accesses 5667 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 2286 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 2286 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 2286 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 2286 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 2286 # number of overall hits -system.cpu.icache.overall_hits::total 2286 # number of overall hits +system.cpu.icache.tags.tag_accesses 5711 # Number of tag accesses +system.cpu.icache.tags.data_accesses 5711 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 2308 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 2308 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 2308 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 2308 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 2308 # number of overall hits +system.cpu.icache.overall_hits::total 2308 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 365 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 365 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 365 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 365 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 365 # number of overall misses system.cpu.icache.overall_misses::total 365 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 27932500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 27932500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 27932500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 27932500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 27932500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 27932500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2651 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2651 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2651 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2651 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2651 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2651 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.137684 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.137684 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.137684 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.137684 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.137684 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.137684 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 76527.397260 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 76527.397260 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 76527.397260 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 76527.397260 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 76527.397260 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 76527.397260 # average overall miss latency +system.cpu.icache.ReadReq_miss_latency::cpu.inst 28127000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 28127000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 28127000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 28127000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 28127000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 28127000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 2673 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 2673 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 2673 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 2673 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 2673 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 2673 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.136551 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.136551 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.136551 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.136551 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.136551 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.136551 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77060.273973 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 77060.273973 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 77060.273973 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 77060.273973 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 77060.273973 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 77060.273973 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -481,36 +481,36 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 365 system.cpu.icache.demand_mshr_misses::total 365 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 365 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 365 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 27567500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 27567500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 27567500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 27567500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 27567500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 27567500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.137684 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.137684 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.137684 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.137684 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.137684 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.137684 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75527.397260 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75527.397260 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75527.397260 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 75527.397260 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75527.397260 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 75527.397260 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 27762000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 27762000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 27762000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 27762000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 27762000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 27762000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.136551 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.136551 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.136551 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.136551 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.136551 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.136551 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 76060.273973 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 76060.273973 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76060.273973 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 76060.273973 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76060.273973 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 76060.273973 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 233.452540 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 233.562418 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 460 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.002174 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 175.828674 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 57.623866 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005366 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.001759 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.007124 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 175.479316 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 58.083102 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005355 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.001773 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.007128 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 460 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 122 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 338 # Occupied blocks per task id @@ -535,18 +535,18 @@ system.cpu.l2cache.demand_misses::total 533 # nu system.cpu.l2cache.overall_misses::cpu.inst 364 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 169 # number of overall misses system.cpu.l2cache.overall_misses::total 533 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5261000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5261000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 27008000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 27008000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 7673000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 7673000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 27008000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 12934000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 39942000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 27008000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 12934000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 39942000 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5275000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5275000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 27202500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 27202500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 7673500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 7673500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 27202500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 12948500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 40151000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 27202500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 12948500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 40151000 # number of overall miss cycles system.cpu.l2cache.ReadExReq_accesses::cpu.data 73 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 365 # number of ReadCleanReq accesses(hits+misses) @@ -571,18 +571,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.998127 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.997260 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.998127 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72068.493151 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72068.493151 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74197.802198 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74197.802198 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 79927.083333 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 79927.083333 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74197.802198 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76532.544379 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 74938.086304 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74197.802198 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76532.544379 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 74938.086304 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72260.273973 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72260.273973 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74732.142857 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74732.142857 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 79932.291667 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 79932.291667 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74732.142857 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76618.343195 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 75330.206379 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74732.142857 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76618.343195 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 75330.206379 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -603,18 +603,18 @@ system.cpu.l2cache.demand_mshr_misses::total 533 system.cpu.l2cache.overall_mshr_misses::cpu.inst 364 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 169 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 533 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4531000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4531000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 23368000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 23368000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6713000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 6713000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 23368000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11244000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 34612000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 23368000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11244000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 34612000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4545000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4545000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 23562500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 23562500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6713500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 6713500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 23562500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11258500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 34821000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 23562500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11258500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 34821000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.997260 # mshr miss rate for ReadCleanReq accesses @@ -627,18 +627,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.998127 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.997260 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.998127 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62068.493151 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62068.493151 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64197.802198 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64197.802198 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 69927.083333 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 69927.083333 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64197.802198 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66532.544379 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64938.086304 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64197.802198 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66532.544379 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64938.086304 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62260.273973 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62260.273973 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64732.142857 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64732.142857 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 69932.291667 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 69932.291667 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64732.142857 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66618.343195 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65330.206379 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64732.142857 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66618.343195 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65330.206379 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.snoop_filter.tot_requests 534 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data. @@ -694,9 +694,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 533 # Request fanout histogram -system.membus.reqLayer0.occupancy 602500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 603000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.6 # Layer utilization (%) -system.membus.respLayer1.occupancy 2833000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2833750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 7.5 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout index bc1887ee5..bd3dd6b17 100755 --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout @@ -1,13 +1,15 @@ +Redirecting stdout to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing/simout +Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 13 2016 22:43:13 -gem5 started Mar 13 2016 22:49:02 -gem5 executing on phenom, pid 19909 +gem5 compiled Mar 14 2016 21:54:46 +gem5 started Mar 14 2016 21:57:45 +gem5 executing on phenom, pid 28188 command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 21900500 because target called exit() +Exiting @ tick 21972500 because target called exit() diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt index f8ab54378..dbdf20650 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt @@ -1,42 +1,42 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000022 # Number of seconds simulated -sim_ticks 21900500 # Number of ticks simulated -final_tick 21900500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 21972500 # Number of ticks simulated +final_tick 21972500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 27169 # Simulator instruction rate (inst/s) -host_op_rate 27167 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 93368241 # Simulator tick rate (ticks/s) -host_mem_usage 228936 # Number of bytes of host memory used -host_seconds 0.23 # Real time elapsed on the host -sim_insts 6372 # Number of instructions simulated -sim_ops 6372 # Number of ops (including micro ops) simulated +host_inst_rate 66596 # Simulator instruction rate (inst/s) +host_op_rate 66584 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 229093695 # Simulator tick rate (ticks/s) +host_mem_usage 228860 # Number of bytes of host memory used +host_seconds 0.10 # Real time elapsed on the host +sim_insts 6385 # Number of instructions simulated +sim_ops 6385 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 19840 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10944 # Number of bytes read from this memory -system.physmem.bytes_read::total 30784 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 11072 # Number of bytes read from this memory +system.physmem.bytes_read::total 30912 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 19840 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 19840 # Number of instructions bytes read from this memory system.physmem.num_reads::cpu.inst 310 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 171 # Number of read requests responded to by this memory -system.physmem.num_reads::total 481 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 905915390 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 499714618 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1405630008 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 905915390 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 905915390 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 905915390 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 499714618 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1405630008 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 481 # Number of read requests accepted +system.physmem.num_reads::cpu.data 173 # Number of read requests responded to by this memory +system.physmem.num_reads::total 483 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 902946865 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 503902606 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1406849471 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 902946865 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 902946865 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 902946865 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 503902606 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1406849471 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 483 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 481 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 483 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 30784 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 30912 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 30784 # Total read bytes from the system interface side +system.physmem.bytesReadSys 30912 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one @@ -45,7 +45,7 @@ system.physmem.perBankRdBursts::0 68 # Pe system.physmem.perBankRdBursts::1 32 # Per bank write bursts system.physmem.perBankRdBursts::2 32 # Per bank write bursts system.physmem.perBankRdBursts::3 47 # Per bank write bursts -system.physmem.perBankRdBursts::4 41 # Per bank write bursts +system.physmem.perBankRdBursts::4 42 # Per bank write bursts system.physmem.perBankRdBursts::5 20 # Per bank write bursts system.physmem.perBankRdBursts::6 1 # Per bank write bursts system.physmem.perBankRdBursts::7 3 # Per bank write bursts @@ -56,7 +56,7 @@ system.physmem.perBankRdBursts::11 25 # Pe system.physmem.perBankRdBursts::12 14 # Per bank write bursts system.physmem.perBankRdBursts::13 118 # Per bank write bursts system.physmem.perBankRdBursts::14 45 # Per bank write bursts -system.physmem.perBankRdBursts::15 12 # Per bank write bursts +system.physmem.perBankRdBursts::15 13 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 21763000 # Total gap between requests +system.physmem.totGap 21835000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 481 # Read request sizes (log2) +system.physmem.readPktSize::6 483 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,10 +90,10 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 270 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 136 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 272 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 135 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 54 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 13 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -186,99 +186,99 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 79 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 337.822785 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 215.071445 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 323.417518 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 21 26.58% 26.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 22 27.85% 54.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 9 11.39% 65.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 9 11.39% 77.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 4 5.06% 82.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1 1.27% 83.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 3 3.80% 87.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 10 12.66% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 79 # Bytes accessed per row activation -system.physmem.totQLat 3965000 # Total ticks spent queuing -system.physmem.totMemAccLat 12983750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2405000 # Total ticks spent in databus transfers -system.physmem.avgQLat 8243.24 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 76 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 352 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 228.419611 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 324.406987 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 18 23.68% 23.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 20 26.32% 50.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 9 11.84% 61.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 11 14.47% 76.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 4 5.26% 81.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1 1.32% 82.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 3 3.95% 86.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 10 13.16% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 76 # Bytes accessed per row activation +system.physmem.totQLat 3936250 # Total ticks spent queuing +system.physmem.totMemAccLat 12992500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2415000 # Total ticks spent in databus transfers +system.physmem.avgQLat 8149.59 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26993.24 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1405.63 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 26899.59 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1406.85 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1405.63 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1406.85 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 10.98 # Data bus utilization in percentage -system.physmem.busUtilRead 10.98 # Data bus utilization in percentage for reads +system.physmem.busUtil 10.99 # Data bus utilization in percentage +system.physmem.busUtilRead 10.99 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.69 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.70 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 387 # Number of row buffer hits during reads +system.physmem.readRowHits 392 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.46 # Row buffer hit rate for reads +system.physmem.readRowHitRate 81.16 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 45245.32 # Average gap between requests -system.physmem.pageHitRate 80.46 # Row buffer hit rate, read and write combined +system.physmem.avgGap 45207.04 # Average gap between requests +system.physmem.pageHitRate 81.16 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 196560 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 107250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1630200 # Energy for read commands per rank (pJ) +system.physmem_0.readEnergy 1638000 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) system.physmem_0.actBackEnergy 10785825 # Energy for active background per rank (pJ) system.physmem_0.preBackEnergy 38250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 13775205 # Total energy per rank (pJ) -system.physmem_0.averagePower 870.058740 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 209750 # Time in different power states +system.physmem_0.totalEnergy 13783005 # Total energy per rank (pJ) +system.physmem_0.averagePower 870.551397 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 281750 # Time in different power states system.physmem_0.memoryStateTime::REF 520000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_0.memoryStateTime::ACT 15303750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 317520 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 173250 # Energy for precharge commands per rank (pJ) +system.physmem_1.actEnergy 294840 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 160875 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 1287000 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 10183905 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 566250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 13545045 # Total energy per rank (pJ) -system.physmem_1.averagePower 855.521554 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 873500 # Time in different power states +system.physmem_1.actBackEnergy 10134315 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 609750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 13503900 # Total energy per rank (pJ) +system.physmem_1.averagePower 852.922785 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 945500 # Time in different power states system.physmem_1.memoryStateTime::REF 520000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 14452750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 14380750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 2551 # Number of BP lookups -system.cpu.branchPred.condPredicted 1518 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 429 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 1991 # Number of BTB lookups -system.cpu.branchPred.BTBHits 726 # Number of BTB hits +system.cpu.branchPred.lookups 2618 # Number of BP lookups +system.cpu.branchPred.condPredicted 1561 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 431 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 2031 # Number of BTB lookups +system.cpu.branchPred.BTBHits 757 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 36.464088 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 383 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 37.272280 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 391 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 29 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 2033 # DTB read hits +system.cpu.dtb.read_hits 2066 # DTB read hits system.cpu.dtb.read_misses 43 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 2076 # DTB read accesses -system.cpu.dtb.write_hits 1052 # DTB write hits +system.cpu.dtb.read_accesses 2109 # DTB read accesses +system.cpu.dtb.write_hits 1060 # DTB write hits system.cpu.dtb.write_misses 28 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 1080 # DTB write accesses -system.cpu.dtb.data_hits 3085 # DTB hits +system.cpu.dtb.write_accesses 1088 # DTB write accesses +system.cpu.dtb.data_hits 3126 # DTB hits system.cpu.dtb.data_misses 71 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 3156 # DTB accesses -system.cpu.itb.fetch_hits 2086 # ITB hits -system.cpu.itb.fetch_misses 32 # ITB misses +system.cpu.dtb.data_accesses 3197 # DTB accesses +system.cpu.itb.fetch_hits 2136 # ITB hits +system.cpu.itb.fetch_misses 29 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 2118 # ITB accesses +system.cpu.itb.fetch_accesses 2165 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -292,460 +292,460 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 43802 # number of cpu cycles simulated +system.cpu.numCycles 43946 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 8360 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 14953 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2551 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 1109 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 4527 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 940 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 24 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 730 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 2086 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 308 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 14111 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.059670 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.447373 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 8425 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 15219 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2618 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 1148 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 4748 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 944 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 23 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 705 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 2136 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 309 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 14373 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.058860 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.441925 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 11381 80.65% 80.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 309 2.19% 82.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 232 1.64% 84.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 210 1.49% 85.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 257 1.82% 87.80% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 204 1.45% 89.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 249 1.76% 91.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 144 1.02% 92.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1125 7.97% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 11578 80.55% 80.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 318 2.21% 82.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 240 1.67% 84.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 228 1.59% 86.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 264 1.84% 87.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 210 1.46% 89.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 253 1.76% 91.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 143 0.99% 92.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1139 7.92% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 14111 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.058239 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.341377 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8350 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 2903 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2283 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 178 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 397 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 199 # Number of times decode resolved a branch +system.cpu.fetch.rateDist::total 14373 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.059573 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.346311 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8351 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 3116 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2327 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 180 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 399 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 208 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 74 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 13658 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 13836 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 213 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 397 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 8499 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 1362 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 551 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2297 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 1005 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 13185 # Number of instructions processed by rename +system.cpu.rename.SquashCycles 399 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 8502 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 1476 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 647 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2338 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 1011 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 13352 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 3 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 29 # Number of times rename has blocked due to IQ full +system.cpu.rename.IQFullEvents 32 # Number of times rename has blocked due to IQ full system.cpu.rename.LQFullEvents 9 # Number of times rename has blocked due to LQ full system.cpu.rename.SQFullEvents 937 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 9916 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 16517 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 16508 # Number of integer rename lookups +system.cpu.rename.RenamedOperands 10012 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 16699 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 16690 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 8 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 4570 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 5346 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 30 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 24 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 571 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2513 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1264 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.CommittedMaps 4577 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 5435 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 32 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 26 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 599 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2560 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1284 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 7 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 12094 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 28 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 10150 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 8 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 5749 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3122 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 11 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 14111 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.719297 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.444291 # Number of insts issued each cycle +system.cpu.iq.iqInstsAdded 12265 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 30 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 10237 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 16 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 5909 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3249 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 13 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 14373 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.712238 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.437631 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 10252 72.65% 72.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1258 8.92% 81.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 873 6.19% 87.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 669 4.74% 92.50% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 489 3.47% 95.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 327 2.32% 98.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 176 1.25% 99.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 10470 72.84% 72.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1281 8.91% 81.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 885 6.16% 87.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 672 4.68% 92.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 490 3.41% 96.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 330 2.30% 98.30% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 178 1.24% 99.53% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 44 0.31% 99.84% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 23 0.16% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 14111 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 14373 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 18 13.64% 13.64% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 13.64% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 13.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 13.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 13.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 13.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 13.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 13.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 13.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 13.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 13.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 13.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 13.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 13.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 13.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 13.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 13.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 13.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 13.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 13.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 13.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 13.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 13.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 13.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 13.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 13.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 13.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 13.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 13.64% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 73 55.30% 68.94% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 41 31.06% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 20 14.93% 14.93% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 14.93% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 14.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 14.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 14.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 14.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 14.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 14.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 14.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 14.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 14.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 14.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 14.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 14.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 14.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 14.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 14.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 14.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 14.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 14.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 14.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 14.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 14.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 14.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 14.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 14.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 14.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 14.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 14.93% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 73 54.48% 69.40% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 41 30.60% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 6822 67.21% 67.23% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.24% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.24% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.26% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.26% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.26% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.26% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.26% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.26% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2214 21.81% 89.07% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1109 10.93% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 6864 67.05% 67.07% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.08% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.08% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2247 21.95% 89.05% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1121 10.95% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 10150 # Type of FU issued -system.cpu.iq.rate 0.231725 # Inst issue rate -system.cpu.iq.fu_busy_cnt 132 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.013005 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 34530 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 17879 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 9316 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 10237 # Type of FU issued +system.cpu.iq.rate 0.232945 # Inst issue rate +system.cpu.iq.fu_busy_cnt 134 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.013090 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 34976 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 18212 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 9377 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 21 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 10 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 10269 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 10358 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 11 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 64 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 65 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1330 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1375 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 20 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 399 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 419 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 71 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 75 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 397 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1267 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 27 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 12206 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 399 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1377 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 29 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 12377 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 103 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2513 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1264 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 28 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 4 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 20 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewDispLoadInsts 2560 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1284 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 30 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 6 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 21 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 20 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 85 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedTakenIncorrect 88 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 341 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 426 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 9752 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2076 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 398 # Number of squashed instructions skipped in execute +system.cpu.iew.branchMispredicts 429 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 9833 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2109 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 404 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 84 # number of nop insts executed -system.cpu.iew.exec_refs 3158 # number of memory reference insts executed -system.cpu.iew.exec_branches 1540 # Number of branches executed -system.cpu.iew.exec_stores 1082 # Number of stores executed -system.cpu.iew.exec_rate 0.222638 # Inst execution rate -system.cpu.iew.wb_sent 9474 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 9326 # cumulative count of insts written-back -system.cpu.iew.wb_producers 4992 # num instructions producing a value -system.cpu.iew.wb_consumers 6833 # num instructions consuming a value -system.cpu.iew.wb_rate 0.212913 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.730572 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 5821 # The number of squashed insts skipped by commit +system.cpu.iew.exec_nop 82 # number of nop insts executed +system.cpu.iew.exec_refs 3199 # number of memory reference insts executed +system.cpu.iew.exec_branches 1559 # Number of branches executed +system.cpu.iew.exec_stores 1090 # Number of stores executed +system.cpu.iew.exec_rate 0.223752 # Inst execution rate +system.cpu.iew.wb_sent 9541 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 9387 # cumulative count of insts written-back +system.cpu.iew.wb_producers 5006 # num instructions producing a value +system.cpu.iew.wb_consumers 6861 # num instructions consuming a value +system.cpu.iew.wb_rate 0.213603 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.729631 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 5982 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 356 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 13063 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.489091 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.409393 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 358 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 13303 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.481245 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.398957 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 10626 81.34% 81.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1163 8.90% 90.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 487 3.73% 93.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 202 1.55% 95.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 127 0.97% 96.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 82 0.63% 97.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 98 0.75% 97.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 84 0.64% 98.51% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 194 1.49% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 10861 81.64% 81.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1165 8.76% 90.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 487 3.66% 94.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 203 1.53% 95.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 129 0.97% 96.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 82 0.62% 97.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 98 0.74% 97.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 84 0.63% 98.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 194 1.46% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 13063 # Number of insts commited each cycle -system.cpu.commit.committedInsts 6389 # Number of instructions committed -system.cpu.commit.committedOps 6389 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 13303 # Number of insts commited each cycle +system.cpu.commit.committedInsts 6402 # Number of instructions committed +system.cpu.commit.committedOps 6402 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 2048 # Number of memory references committed -system.cpu.commit.loads 1183 # Number of loads committed +system.cpu.commit.refs 2050 # Number of memory references committed +system.cpu.commit.loads 1185 # Number of loads committed system.cpu.commit.membars 0 # Number of memory barriers committed -system.cpu.commit.branches 1050 # Number of branches committed +system.cpu.commit.branches 1056 # Number of branches committed system.cpu.commit.fp_insts 10 # Number of committed floating point instructions. -system.cpu.commit.int_insts 6307 # Number of committed integer instructions. +system.cpu.commit.int_insts 6319 # Number of committed integer instructions. system.cpu.commit.function_calls 127 # Number of function calls committed. system.cpu.commit.op_class_0::No_OpClass 19 0.30% 0.30% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 4319 67.60% 67.90% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 1 0.02% 67.91% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 0 0.00% 67.91% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 2 0.03% 67.94% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCmp 0 0.00% 67.94% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCvt 0 0.00% 67.94% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMult 0 0.00% 67.94% # Class of committed instruction -system.cpu.commit.op_class_0::FloatDiv 0 0.00% 67.94% # Class of committed instruction -system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 67.94% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAdd 0 0.00% 67.94% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 67.94% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAlu 0 0.00% 67.94% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCmp 0 0.00% 67.94% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCvt 0 0.00% 67.94% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMisc 0 0.00% 67.94% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMult 0 0.00% 67.94% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 67.94% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShift 0 0.00% 67.94% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 67.94% # Class of committed instruction -system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 67.94% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 67.94% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 67.94% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 67.94% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 67.94% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 67.94% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 67.94% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 67.94% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.94% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.94% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 1183 18.52% 86.46% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 865 13.54% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 4330 67.64% 67.93% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 1 0.02% 67.95% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 0 0.00% 67.95% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 2 0.03% 67.98% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 67.98% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 67.98% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 67.98% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 67.98% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 67.98% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 67.98% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 67.98% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 67.98% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 67.98% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 67.98% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 67.98% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 67.98% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 67.98% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 67.98% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 67.98% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 67.98% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 67.98% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 67.98% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 67.98% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 67.98% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 67.98% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 67.98% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 67.98% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.98% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.98% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 1185 18.51% 86.49% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 865 13.51% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 6389 # Class of committed instruction +system.cpu.commit.op_class_0::total 6402 # Class of committed instruction system.cpu.commit.bw_lim_events 194 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 24728 # The number of ROB reads -system.cpu.rob.rob_writes 25475 # The number of ROB writes -system.cpu.timesIdled 260 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 29691 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 6372 # Number of Instructions Simulated -system.cpu.committedOps 6372 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 6.874137 # CPI: Cycles Per Instruction -system.cpu.cpi_total 6.874137 # CPI: Total CPI of All Threads -system.cpu.ipc 0.145473 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.145473 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 12363 # number of integer regfile reads -system.cpu.int_regfile_writes 7056 # number of integer regfile writes +system.cpu.rob.rob_reads 25142 # The number of ROB reads +system.cpu.rob.rob_writes 25845 # The number of ROB writes +system.cpu.timesIdled 258 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 29573 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 6385 # Number of Instructions Simulated +system.cpu.committedOps 6385 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 6.882694 # CPI: Cycles Per Instruction +system.cpu.cpi_total 6.882694 # CPI: Total CPI of All Threads +system.cpu.ipc 0.145292 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.145292 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 12434 # number of integer regfile reads +system.cpu.int_regfile_writes 7099 # number of integer regfile writes system.cpu.fp_regfile_reads 8 # number of floating regfile reads system.cpu.fp_regfile_writes 2 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 107.516544 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2276 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 171 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 13.309942 # Average number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 109.593222 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2292 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 173 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 13.248555 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 107.516544 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.026249 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.026249 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 171 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 126 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.041748 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 5747 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 5747 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 1770 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1770 # number of ReadReq hits +system.cpu.dcache.tags.occ_blocks::cpu.data 109.593222 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.026756 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.026756 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 173 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 129 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.042236 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 5805 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 5805 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 1786 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1786 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 506 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 506 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2276 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2276 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2276 # number of overall hits -system.cpu.dcache.overall_hits::total 2276 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 153 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 153 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 2292 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2292 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2292 # number of overall hits +system.cpu.dcache.overall_hits::total 2292 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 165 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 165 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 359 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 359 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 512 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 512 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 512 # number of overall misses -system.cpu.dcache.overall_misses::total 512 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11315000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11315000 # number of ReadReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 524 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 524 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 524 # number of overall misses +system.cpu.dcache.overall_misses::total 524 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 12170500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 12170500 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 23651475 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 23651475 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 34966475 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 34966475 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 34966475 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 34966475 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1923 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1923 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 35821975 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 35821975 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 35821975 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 35821975 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1951 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1951 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2788 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2788 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2788 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2788 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.079563 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.079563 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2816 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2816 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2816 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2816 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.084572 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.084572 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.415029 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.415029 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.183644 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.183644 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.183644 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.183644 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 73954.248366 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 73954.248366 # average ReadReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.186080 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.186080 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.186080 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.186080 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 73760.606061 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 73760.606061 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65881.545961 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 65881.545961 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 68293.896484 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 68293.896484 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 68293.896484 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 68293.896484 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 2328 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 68362.547710 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 68362.547710 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 68362.547710 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 68362.547710 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 2432 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 42 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 43 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 55.428571 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 56.558140 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 54 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 54 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 64 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 64 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 287 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 287 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 341 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 341 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 341 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 341 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 99 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 99 # number of ReadReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 351 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 351 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 351 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 351 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 101 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 101 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 72 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 72 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 171 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 171 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 171 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 171 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8341000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 8341000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 173 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 173 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 173 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8462500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 8462500 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5669500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 5669500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14010500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 14010500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14010500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 14010500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.051482 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.051482 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14132000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 14132000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14132000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 14132000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.051768 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.051768 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083237 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.083237 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.061334 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.061334 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.061334 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.061334 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 84252.525253 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 84252.525253 # average ReadReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.061435 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.061435 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.061435 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.061435 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 83787.128713 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 83787.128713 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78743.055556 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78743.055556 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 81932.748538 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 81932.748538 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 81932.748538 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 81932.748538 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 81687.861272 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 81687.861272 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 81687.861272 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 81687.861272 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 157.774008 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1627 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 157.288732 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1677 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 311 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 5.231511 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 5.392283 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 157.774008 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.077038 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.077038 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 157.288732 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.076801 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.076801 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 311 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 138 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 173 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.151855 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 4483 # Number of tag accesses -system.cpu.icache.tags.data_accesses 4483 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 1627 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1627 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1627 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1627 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1627 # number of overall hits -system.cpu.icache.overall_hits::total 1627 # number of overall hits +system.cpu.icache.tags.tag_accesses 4583 # Number of tag accesses +system.cpu.icache.tags.data_accesses 4583 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 1677 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1677 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1677 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1677 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1677 # number of overall hits +system.cpu.icache.overall_hits::total 1677 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 459 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 459 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 459 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 459 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 459 # number of overall misses system.cpu.icache.overall_misses::total 459 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 32353500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 32353500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 32353500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 32353500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 32353500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 32353500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2086 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2086 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2086 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2086 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2086 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2086 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.220038 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.220038 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.220038 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.220038 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.220038 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.220038 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70486.928105 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 70486.928105 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 70486.928105 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 70486.928105 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 70486.928105 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 70486.928105 # average overall miss latency +system.cpu.icache.ReadReq_miss_latency::cpu.inst 32358000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 32358000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 32358000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 32358000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 32358000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 32358000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 2136 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 2136 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 2136 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 2136 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 2136 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 2136 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.214888 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.214888 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.214888 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.214888 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.214888 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.214888 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70496.732026 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 70496.732026 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 70496.732026 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 70496.732026 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 70496.732026 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 70496.732026 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -766,42 +766,42 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 311 system.cpu.icache.demand_mshr_misses::total 311 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 311 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 311 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23860500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 23860500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23860500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 23860500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23860500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 23860500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.149089 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.149089 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.149089 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.149089 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.149089 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.149089 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 76721.864952 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 76721.864952 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76721.864952 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 76721.864952 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76721.864952 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 76721.864952 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23850000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 23850000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23850000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 23850000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23850000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 23850000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.145599 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.145599 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.145599 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.145599 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.145599 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.145599 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 76688.102894 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 76688.102894 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76688.102894 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 76688.102894 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76688.102894 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 76688.102894 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 218.211579 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 219.942323 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 409 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.002445 # Average number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 411 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.002433 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 157.816586 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 60.394993 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004816 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.001843 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.006659 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 409 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 172 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 237 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012482 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 4337 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 4337 # Number of data accesses +system.cpu.l2cache.tags.occ_blocks::cpu.inst 157.331171 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 62.611152 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004801 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.001911 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.006712 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 411 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 171 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 240 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012543 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 4355 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 4355 # Number of data accesses system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1 # number of ReadCleanReq hits system.cpu.l2cache.ReadCleanReq_hits::total 1 # number of ReadCleanReq hits system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits @@ -812,38 +812,38 @@ system.cpu.l2cache.ReadExReq_misses::cpu.data 72 system.cpu.l2cache.ReadExReq_misses::total 72 # number of ReadExReq misses system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 310 # number of ReadCleanReq misses system.cpu.l2cache.ReadCleanReq_misses::total 310 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 99 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 99 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 101 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 101 # number of ReadSharedReq misses system.cpu.l2cache.demand_misses::cpu.inst 310 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 171 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 481 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 173 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 483 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 310 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 171 # number of overall misses -system.cpu.l2cache.overall_misses::total 481 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 173 # number of overall misses +system.cpu.l2cache.overall_misses::total 483 # number of overall misses system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5558500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 5558500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 23380000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 23380000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 8185000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 8185000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 23380000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 13743500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 37123500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 23380000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 13743500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 37123500 # number of overall miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 23369500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 23369500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 8303500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 8303500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 23369500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 13862000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 37231500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 23369500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 13862000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 37231500 # number of overall miss cycles system.cpu.l2cache.ReadExReq_accesses::cpu.data 72 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 72 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 311 # number of ReadCleanReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::total 311 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 99 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 99 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 101 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 101 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 311 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 171 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 482 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 173 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 484 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 311 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 171 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 482 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 173 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 484 # number of overall (read+write) accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.996785 # miss rate for ReadCleanReq accesses @@ -852,22 +852,22 @@ system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996785 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.997925 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.997934 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996785 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.997925 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.997934 # miss rate for overall accesses system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77201.388889 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77201.388889 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75419.354839 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75419.354839 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 82676.767677 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 82676.767677 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75419.354839 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80371.345029 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 77179.833680 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75419.354839 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80371.345029 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 77179.833680 # average overall miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75385.483871 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75385.483871 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 82212.871287 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 82212.871287 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75385.483871 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80127.167630 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 77083.850932 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75385.483871 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80127.167630 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 77083.850932 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -880,26 +880,26 @@ system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 72 system.cpu.l2cache.ReadExReq_mshr_misses::total 72 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 310 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::total 310 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 99 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 99 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 101 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 101 # number of ReadSharedReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 310 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 171 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 481 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 173 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 483 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 310 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 171 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 481 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 173 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 483 # number of overall MSHR misses system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4838500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4838500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 20280000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 20280000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7195000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7195000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 20280000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 12033500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 32313500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 20280000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12033500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 32313500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 20269500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 20269500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7293500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7293500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 20269500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 12132000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 32401500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 20269500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12132000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 32401500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.996785 # mshr miss rate for ReadCleanReq accesses @@ -908,80 +908,80 @@ system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996785 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.997925 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.997934 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996785 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.997925 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.997934 # mshr miss rate for overall accesses system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67201.388889 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67201.388889 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65419.354839 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65419.354839 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72676.767677 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72676.767677 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65419.354839 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70371.345029 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67179.833680 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65419.354839 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70371.345029 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67179.833680 # average overall mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65385.483871 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65385.483871 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72212.871287 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72212.871287 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65385.483871 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70127.167630 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67083.850932 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65385.483871 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70127.167630 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67083.850932 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 482 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.tot_requests 484 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 410 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 412 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 72 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 72 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 311 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 99 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 101 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 622 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 342 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 964 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 346 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 968 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19904 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10944 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 30848 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 11072 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 30976 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 482 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.002075 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.045549 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 484 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.002066 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.045455 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 481 99.79% 99.79% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 483 99.79% 99.79% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 1 0.21% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 482 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 241000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 484 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 242000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 466500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 2.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 256500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 259500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) -system.membus.trans_dist::ReadResp 409 # Transaction distribution +system.membus.trans_dist::ReadResp 411 # Transaction distribution system.membus.trans_dist::ReadExReq 72 # Transaction distribution system.membus.trans_dist::ReadExResp 72 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 409 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 962 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 962 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30784 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 30784 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 411 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 966 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 966 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30912 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 30912 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 481 # Request fanout histogram +system.membus.snoop_fanout::samples 483 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 481 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 483 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 481 # Request fanout histogram -system.membus.reqLayer0.occupancy 586000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 483 # Request fanout histogram +system.membus.reqLayer0.occupancy 588000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 2558250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2567750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 11.7 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/config.ini index ab97850f7..1e89f2405 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/config.ini @@ -116,7 +116,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello +executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin kvmInSE=false @@ -151,6 +151,7 @@ clk_domain=system.clk_domain eventq_index=0 forward_latency=4 frontend_latency=3 +point_of_coherency=true response_latency=2 snoop_filter=Null snoop_response_latency=4 diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/simout b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/simout index 7d01b9cb4..e982daec6 100755 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/simout +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/simout @@ -1,13 +1,15 @@ +Redirecting stdout to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-atomic/simout +Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-atomic/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 21 2016 13:49:21 -gem5 started Jan 21 2016 13:50:02 -gem5 executing on zizzer, pid 34000 -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-atomic -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-atomic +gem5 compiled Mar 14 2016 21:54:46 +gem5 started Mar 14 2016 21:56:00 +gem5 executing on phenom, pid 28087 +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-atomic -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 3208000 because target called exit() +Exiting @ tick 3214500 because target called exit() diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt index ec5525b66..a9b70663c 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt @@ -1,61 +1,61 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000003 # Number of seconds simulated -sim_ticks 3208000 # Number of ticks simulated -final_tick 3208000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 3214500 # Number of ticks simulated +final_tick 3214500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 146057 # Simulator instruction rate (inst/s) -host_op_rate 145971 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 73240755 # Simulator tick rate (ticks/s) -host_mem_usage 220608 # Number of bytes of host memory used -host_seconds 0.04 # Real time elapsed on the host -sim_insts 6390 # Number of instructions simulated -sim_ops 6390 # Number of ops (including micro ops) simulated +host_inst_rate 21023 # Simulator instruction rate (inst/s) +host_op_rate 21020 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 10551583 # Simulator tick rate (ticks/s) +host_mem_usage 216888 # Number of bytes of host memory used +host_seconds 0.30 # Real time elapsed on the host +sim_insts 6403 # Number of instructions simulated +sim_ops 6403 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 25600 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 8788 # Number of bytes read from this memory -system.physmem.bytes_read::total 34388 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 25600 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 25600 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 25652 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 8804 # Number of bytes read from this memory +system.physmem.bytes_read::total 34456 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 25652 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 25652 # Number of instructions bytes read from this memory system.physmem.bytes_written::cpu.data 6696 # Number of bytes written to this memory system.physmem.bytes_written::total 6696 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 6400 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1183 # Number of read requests responded to by this memory -system.physmem.num_reads::total 7583 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 6413 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1185 # Number of read requests responded to by this memory +system.physmem.num_reads::total 7598 # Number of read requests responded to by this memory system.physmem.num_writes::cpu.data 865 # Number of write requests responded to by this memory system.physmem.num_writes::total 865 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 7980049875 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2739401496 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 10719451372 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 7980049875 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 7980049875 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 2087281796 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2087281796 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 7980049875 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4826683292 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 12806733167 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 7980090216 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2738839633 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 10718929849 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 7980090216 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 7980090216 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 2083061129 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2083061129 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 7980090216 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4821900762 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 12801990978 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 1183 # DTB read hits +system.cpu.dtb.read_hits 1185 # DTB read hits system.cpu.dtb.read_misses 7 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 1190 # DTB read accesses +system.cpu.dtb.read_accesses 1192 # DTB read accesses system.cpu.dtb.write_hits 865 # DTB write hits system.cpu.dtb.write_misses 3 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations system.cpu.dtb.write_accesses 868 # DTB write accesses -system.cpu.dtb.data_hits 2048 # DTB hits +system.cpu.dtb.data_hits 2050 # DTB hits system.cpu.dtb.data_misses 10 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 2058 # DTB accesses -system.cpu.itb.fetch_hits 6400 # ITB hits +system.cpu.dtb.data_accesses 2060 # DTB accesses +system.cpu.itb.fetch_hits 6413 # ITB hits system.cpu.itb.fetch_misses 17 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 6417 # ITB accesses +system.cpu.itb.fetch_accesses 6430 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -69,84 +69,84 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 6417 # number of cpu cycles simulated +system.cpu.numCycles 6430 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 6390 # Number of instructions committed -system.cpu.committedOps 6390 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 6317 # Number of integer alu accesses +system.cpu.committedInsts 6403 # Number of instructions committed +system.cpu.committedOps 6403 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 6329 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses system.cpu.num_func_calls 251 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 749 # number of instructions that are conditional controls -system.cpu.num_int_insts 6317 # number of integer instructions +system.cpu.num_conditional_control_insts 754 # number of instructions that are conditional controls +system.cpu.num_int_insts 6329 # number of integer instructions system.cpu.num_fp_insts 10 # number of float instructions -system.cpu.num_int_register_reads 8285 # number of times the integer registers were read -system.cpu.num_int_register_writes 4568 # number of times the integer registers were written +system.cpu.num_int_register_reads 8297 # number of times the integer registers were read +system.cpu.num_int_register_writes 4575 # number of times the integer registers were written system.cpu.num_fp_register_reads 8 # number of times the floating registers were read system.cpu.num_fp_register_writes 2 # number of times the floating registers were written -system.cpu.num_mem_refs 2058 # number of memory refs -system.cpu.num_load_insts 1190 # Number of load instructions +system.cpu.num_mem_refs 2060 # number of memory refs +system.cpu.num_load_insts 1192 # Number of load instructions system.cpu.num_store_insts 868 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 6417 # Number of busy cycles +system.cpu.num_busy_cycles 6430 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 1050 # Number of branches fetched +system.cpu.Branches 1056 # Number of branches fetched system.cpu.op_class::No_OpClass 19 0.30% 0.30% # Class of executed instruction -system.cpu.op_class::IntAlu 4320 67.50% 67.80% # Class of executed instruction -system.cpu.op_class::IntMult 1 0.02% 67.81% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 67.81% # Class of executed instruction -system.cpu.op_class::FloatAdd 2 0.03% 67.84% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::MemRead 1190 18.59% 86.44% # Class of executed instruction -system.cpu.op_class::MemWrite 868 13.56% 100.00% # Class of executed instruction +system.cpu.op_class::IntAlu 4331 67.53% 67.83% # Class of executed instruction +system.cpu.op_class::IntMult 1 0.02% 67.85% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 67.85% # Class of executed instruction +system.cpu.op_class::FloatAdd 2 0.03% 67.88% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::MemRead 1192 18.59% 86.46% # Class of executed instruction +system.cpu.op_class::MemWrite 868 13.54% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 6400 # Class of executed instruction -system.membus.trans_dist::ReadReq 7583 # Transaction distribution -system.membus.trans_dist::ReadResp 7583 # Transaction distribution +system.cpu.op_class::total 6413 # Class of executed instruction +system.membus.trans_dist::ReadReq 7598 # Transaction distribution +system.membus.trans_dist::ReadResp 7598 # Transaction distribution system.membus.trans_dist::WriteReq 865 # Transaction distribution system.membus.trans_dist::WriteResp 865 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 12800 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 4096 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 16896 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 25600 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 15484 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 41084 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 12826 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 4100 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 16926 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 25652 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 15500 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 41152 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 8448 # Request fanout histogram -system.membus.snoop_fanout::mean 0.757576 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.428575 # Request fanout histogram +system.membus.snoop_fanout::samples 8463 # Request fanout histogram +system.membus.snoop_fanout::mean 0.757769 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.428459 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 2048 24.24% 24.24% # Request fanout histogram -system.membus.snoop_fanout::1 6400 75.76% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 2050 24.22% 24.22% # Request fanout histogram +system.membus.snoop_fanout::1 6413 75.78% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 8448 # Request fanout histogram +system.membus.snoop_fanout::total 8463 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/config.ini index 7e399d299..c48b9e2ab 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/config.ini @@ -120,7 +120,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello +executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin kvmInSE=false diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/simout b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/simout index f1833345c..838211534 100755 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/simout +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/simout @@ -1,13 +1,15 @@ +Redirecting stdout to build/ALPHA_MESI_Two_Level/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MESI_Two_Level/simout +Redirecting stderr to build/ALPHA_MESI_Two_Level/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MESI_Two_Level/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 21 2016 14:01:33 -gem5 started Jan 21 2016 14:02:10 -gem5 executing on zizzer, pid 44721 -command line: build/ALPHA_MESI_Two_Level/gem5.opt -d build/ALPHA_MESI_Two_Level/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MESI_Two_Level -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ALPHA_MESI_Two_Level/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MESI_Two_Level +gem5 compiled Mar 14 2016 22:00:08 +gem5 started Mar 14 2016 22:01:20 +gem5 executing on phenom, pid 28860 +command line: build/ALPHA_MESI_Two_Level/gem5.opt -d build/ALPHA_MESI_Two_Level/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MESI_Two_Level -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA_MESI_Two_Level/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MESI_Two_Level Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 121460 because target called exit() +Exiting @ tick 121535 because target called exit() diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/stats.txt index dc74457ff..7c6c13cf7 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/stats.txt @@ -1,40 +1,40 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000121 # Number of seconds simulated -sim_ticks 121460 # Number of ticks simulated -final_tick 121460 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000122 # Number of seconds simulated +sim_ticks 121535 # Number of ticks simulated +final_tick 121535 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 58804 # Simulator instruction rate (inst/s) -host_op_rate 58798 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1117518 # Simulator tick rate (ticks/s) -host_mem_usage 412400 # Number of bytes of host memory used -host_seconds 0.11 # Real time elapsed on the host -sim_insts 6390 # Number of instructions simulated -sim_ops 6390 # Number of ops (including micro ops) simulated +host_inst_rate 23854 # Simulator instruction rate (inst/s) +host_op_rate 23852 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 452710 # Simulator tick rate (ticks/s) +host_mem_usage 387364 # Number of bytes of host memory used +host_seconds 0.27 # Real time elapsed on the host +sim_insts 6403 # Number of instructions simulated +sim_ops 6403 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks -system.mem_ctrls.bytes_read::ruby.dir_cntrl0 93440 # Number of bytes read from this memory -system.mem_ctrls.bytes_read::total 93440 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::ruby.dir_cntrl0 93504 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 93504 # Number of bytes read from this memory system.mem_ctrls.bytes_written::ruby.dir_cntrl0 17728 # Number of bytes written to this memory system.mem_ctrls.bytes_written::total 17728 # Number of bytes written to this memory -system.mem_ctrls.num_reads::ruby.dir_cntrl0 1460 # Number of read requests responded to by this memory -system.mem_ctrls.num_reads::total 1460 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::ruby.dir_cntrl0 1461 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 1461 # Number of read requests responded to by this memory system.mem_ctrls.num_writes::ruby.dir_cntrl0 277 # Number of write requests responded to by this memory system.mem_ctrls.num_writes::total 277 # Number of write requests responded to by this memory -system.mem_ctrls.bw_read::ruby.dir_cntrl0 769306768 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_read::total 769306768 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::ruby.dir_cntrl0 145957517 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::total 145957517 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_total::ruby.dir_cntrl0 915264285 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.bw_total::total 915264285 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.readReqs 1460 # Number of read requests accepted +system.mem_ctrls.bw_read::ruby.dir_cntrl0 769358621 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 769358621 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::ruby.dir_cntrl0 145867446 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::total 145867446 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::ruby.dir_cntrl0 915226067 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 915226067 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.readReqs 1461 # Number of read requests accepted system.mem_ctrls.writeReqs 277 # Number of write requests accepted -system.mem_ctrls.readBursts 1460 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.readBursts 1461 # Number of DRAM read bursts, including those serviced by the write queue system.mem_ctrls.writeBursts 277 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrls.bytesReadDRAM 74176 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadDRAM 74240 # Total number of bytes read from DRAM system.mem_ctrls.bytesReadWrQ 19264 # Total number of bytes read from write queue system.mem_ctrls.bytesWritten 5376 # Total number of bytes written to DRAM -system.mem_ctrls.bytesReadSys 93440 # Total read bytes from the system interface side +system.mem_ctrls.bytesReadSys 93504 # Total read bytes from the system interface side system.mem_ctrls.bytesWrittenSys 17728 # Total written bytes from the system interface side system.mem_ctrls.servicedByWrQ 301 # Number of DRAM read bursts serviced by the write queue system.mem_ctrls.mergedWrBursts 163 # Number of DRAM write bursts merged with an existing one @@ -54,7 +54,7 @@ system.mem_ctrls.perBankRdBursts::11 75 # Pe system.mem_ctrls.perBankRdBursts::12 26 # Per bank write bursts system.mem_ctrls.perBankRdBursts::13 395 # Per bank write bursts system.mem_ctrls.perBankRdBursts::14 67 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::15 48 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::15 49 # Per bank write bursts system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts @@ -73,14 +73,14 @@ system.mem_ctrls.perBankWrBursts::14 41 # Pe system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrls.totGap 121373 # Total gap between requests +system.mem_ctrls.totGap 121448 # Total gap between requests system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::6 1460 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 1461 # Read request sizes (log2) system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) @@ -88,7 +88,7 @@ system.mem_ctrls.writePktSize::3 0 # Wr system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::6 277 # Write request sizes (log2) -system.mem_ctrls.rdQLenPdf::0 1159 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::0 1160 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see @@ -184,24 +184,24 @@ system.mem_ctrls.wrQLenPdf::60 0 # Wh system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrls.bytesPerActivate::samples 215 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::mean 361.079070 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::gmean 218.518186 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::stdev 343.911785 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::0-127 62 28.84% 28.84% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::128-255 53 24.65% 53.49% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::256-383 19 8.84% 62.33% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::384-511 18 8.37% 70.70% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::512-639 12 5.58% 76.28% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::640-767 6 2.79% 79.07% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::768-895 11 5.12% 84.19% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::896-1023 8 3.72% 87.91% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::1024-1151 26 12.09% 100.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::total 215 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::samples 217 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 357.751152 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 214.775071 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 343.064988 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 66 30.41% 30.41% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 51 23.50% 53.92% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 17 7.83% 61.75% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 18 8.29% 70.05% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 15 6.91% 76.96% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 6 2.76% 79.72% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 12 5.53% 85.25% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 4 1.84% 87.10% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 28 12.90% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 217 # Bytes accessed per row activation system.mem_ctrls.rdPerTurnAround::samples 5 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::mean 150.200000 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::gmean 107.544474 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::stdev 96.970098 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::mean 150.400000 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::gmean 107.633945 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::stdev 97.202366 # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::16-23 1 20.00% 20.00% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::72-79 1 20.00% 40.00% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::200-207 1 20.00% 60.00% # Reads before turning the bus around for writes @@ -215,77 +215,77 @@ system.mem_ctrls.wrPerTurnAround::stdev 1.095445 # Wr system.mem_ctrls.wrPerTurnAround::16 3 60.00% 60.00% # Writes before turning the bus around for reads system.mem_ctrls.wrPerTurnAround::18 2 40.00% 100.00% # Writes before turning the bus around for reads system.mem_ctrls.wrPerTurnAround::total 5 # Writes before turning the bus around for reads -system.mem_ctrls.totQLat 8037 # Total ticks spent queuing -system.mem_ctrls.totMemAccLat 30058 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrls.totBusLat 5795 # Total ticks spent in databus transfers -system.mem_ctrls.avgQLat 6.93 # Average queueing delay per DRAM burst +system.mem_ctrls.totQLat 8011 # Total ticks spent queuing +system.mem_ctrls.totMemAccLat 30051 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.totBusLat 5800 # Total ticks spent in databus transfers +system.mem_ctrls.avgQLat 6.91 # Average queueing delay per DRAM burst system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst -system.mem_ctrls.avgMemAccLat 25.93 # Average memory access latency per DRAM burst -system.mem_ctrls.avgRdBW 610.70 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrls.avgWrBW 44.26 # Average achieved write bandwidth in MiByte/s -system.mem_ctrls.avgRdBWSys 769.31 # Average system read bandwidth in MiByte/s -system.mem_ctrls.avgWrBWSys 145.96 # Average system write bandwidth in MiByte/s +system.mem_ctrls.avgMemAccLat 25.91 # Average memory access latency per DRAM burst +system.mem_ctrls.avgRdBW 610.85 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 44.23 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 769.36 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 145.87 # Average system write bandwidth in MiByte/s system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.mem_ctrls.busUtil 5.12 # Data bus utilization in percentage system.mem_ctrls.busUtilRead 4.77 # Data bus utilization in percentage for reads system.mem_ctrls.busUtilWrite 0.35 # Data bus utilization in percentage for writes system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing -system.mem_ctrls.avgWrQLen 22.44 # Average write queue length when enqueuing -system.mem_ctrls.readRowHits 944 # Number of row buffer hits during reads +system.mem_ctrls.avgWrQLen 22.41 # Average write queue length when enqueuing +system.mem_ctrls.readRowHits 943 # Number of row buffer hits during reads system.mem_ctrls.writeRowHits 78 # Number of row buffer hits during writes -system.mem_ctrls.readRowHitRate 81.45 # Row buffer hit rate for reads +system.mem_ctrls.readRowHitRate 81.29 # Row buffer hit rate for reads system.mem_ctrls.writeRowHitRate 68.42 # Row buffer hit rate for writes system.mem_ctrls.avgGap 69.88 # Average gap between requests -system.mem_ctrls.pageHitRate 80.28 # Row buffer hit rate, read and write combined +system.mem_ctrls.pageHitRate 80.14 # Row buffer hit rate, read and write combined system.mem_ctrls_0.actEnergy 506520 # Energy for activate commands per rank (pJ) system.mem_ctrls_0.preEnergy 281400 # Energy for precharge commands per rank (pJ) system.mem_ctrls_0.readEnergy 5703360 # Energy for read commands per rank (pJ) system.mem_ctrls_0.writeEnergy 248832 # Energy for write commands per rank (pJ) system.mem_ctrls_0.refreshEnergy 7628400 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_0.actBackEnergy 66392460 # Energy for active background per rank (pJ) -system.mem_ctrls_0.preBackEnergy 11991000 # Energy for precharge background per rank (pJ) -system.mem_ctrls_0.totalEnergy 92751972 # Total energy per rank (pJ) -system.mem_ctrls_0.averagePower 792.413259 # Core power per rank (mW) -system.mem_ctrls_0.memoryStateTime::IDLE 22133 # Time in different power states +system.mem_ctrls_0.actBackEnergy 65986164 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 12347400 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.totalEnergy 92702076 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 791.986980 # Core power per rank (mW) +system.mem_ctrls_0.memoryStateTime::IDLE 22788 # Time in different power states system.mem_ctrls_0.memoryStateTime::REF 3900 # Time in different power states system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT 93571 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 92991 # Time in different power states system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrls_1.actEnergy 1088640 # Energy for activate commands per rank (pJ) -system.mem_ctrls_1.preEnergy 604800 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.actEnergy 1103760 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 613200 # Energy for precharge commands per rank (pJ) system.mem_ctrls_1.readEnergy 8236800 # Energy for read commands per rank (pJ) system.mem_ctrls_1.writeEnergy 622080 # Energy for write commands per rank (pJ) system.mem_ctrls_1.refreshEnergy 7628400 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_1.actBackEnergy 78596388 # Energy for active background per rank (pJ) -system.mem_ctrls_1.preBackEnergy 1285800 # Energy for precharge background per rank (pJ) -system.mem_ctrls_1.totalEnergy 98062908 # Total energy per rank (pJ) -system.mem_ctrls_1.averagePower 837.786484 # Core power per rank (mW) -system.mem_ctrls_1.memoryStateTime::IDLE 1555 # Time in different power states +system.mem_ctrls_1.actBackEnergy 78402132 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 1456200 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.totalEnergy 98062572 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 837.783614 # Core power per rank (mW) +system.mem_ctrls_1.memoryStateTime::IDLE 1811 # Time in different power states system.mem_ctrls_1.memoryStateTime::REF 3900 # Time in different power states system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT 111609 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 111353 # Time in different power states system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.clk_domain.clock 1 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 1183 # DTB read hits +system.cpu.dtb.read_hits 1185 # DTB read hits system.cpu.dtb.read_misses 7 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 1190 # DTB read accesses +system.cpu.dtb.read_accesses 1192 # DTB read accesses system.cpu.dtb.write_hits 865 # DTB write hits system.cpu.dtb.write_misses 3 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations system.cpu.dtb.write_accesses 868 # DTB write accesses -system.cpu.dtb.data_hits 2048 # DTB hits +system.cpu.dtb.data_hits 2050 # DTB hits system.cpu.dtb.data_misses 10 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 2058 # DTB accesses -system.cpu.itb.fetch_hits 6401 # ITB hits +system.cpu.dtb.data_accesses 2060 # DTB accesses +system.cpu.itb.fetch_hits 6414 # ITB hits system.cpu.itb.fetch_misses 17 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 6418 # ITB accesses +system.cpu.itb.fetch_accesses 6431 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -299,108 +299,108 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 121460 # number of cpu cycles simulated +system.cpu.numCycles 121535 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 6390 # Number of instructions committed -system.cpu.committedOps 6390 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 6317 # Number of integer alu accesses +system.cpu.committedInsts 6403 # Number of instructions committed +system.cpu.committedOps 6403 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 6329 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses system.cpu.num_func_calls 251 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 749 # number of instructions that are conditional controls -system.cpu.num_int_insts 6317 # number of integer instructions +system.cpu.num_conditional_control_insts 754 # number of instructions that are conditional controls +system.cpu.num_int_insts 6329 # number of integer instructions system.cpu.num_fp_insts 10 # number of float instructions -system.cpu.num_int_register_reads 8285 # number of times the integer registers were read -system.cpu.num_int_register_writes 4568 # number of times the integer registers were written +system.cpu.num_int_register_reads 8297 # number of times the integer registers were read +system.cpu.num_int_register_writes 4575 # number of times the integer registers were written system.cpu.num_fp_register_reads 8 # number of times the floating registers were read system.cpu.num_fp_register_writes 2 # number of times the floating registers were written -system.cpu.num_mem_refs 2058 # number of memory refs -system.cpu.num_load_insts 1190 # Number of load instructions +system.cpu.num_mem_refs 2060 # number of memory refs +system.cpu.num_load_insts 1192 # Number of load instructions system.cpu.num_store_insts 868 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 121460 # Number of busy cycles +system.cpu.num_busy_cycles 121535 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 1050 # Number of branches fetched +system.cpu.Branches 1056 # Number of branches fetched system.cpu.op_class::No_OpClass 19 0.30% 0.30% # Class of executed instruction -system.cpu.op_class::IntAlu 4320 67.50% 67.80% # Class of executed instruction -system.cpu.op_class::IntMult 1 0.02% 67.81% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 67.81% # Class of executed instruction -system.cpu.op_class::FloatAdd 2 0.03% 67.84% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::MemRead 1190 18.59% 86.44% # Class of executed instruction -system.cpu.op_class::MemWrite 868 13.56% 100.00% # Class of executed instruction +system.cpu.op_class::IntAlu 4331 67.53% 67.83% # Class of executed instruction +system.cpu.op_class::IntMult 1 0.02% 67.85% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 67.85% # Class of executed instruction +system.cpu.op_class::FloatAdd 2 0.03% 67.88% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::MemRead 1192 18.59% 86.46% # Class of executed instruction +system.cpu.op_class::MemWrite 868 13.54% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 6400 # Class of executed instruction +system.cpu.op_class::total 6413 # Class of executed instruction system.ruby.clk_domain.clock 1 # Clock period in ticks system.ruby.delayHist::bucket_size 1 # delay histogram for all message system.ruby.delayHist::max_bucket 9 # delay histogram for all message -system.ruby.delayHist::samples 9645 # delay histogram for all message -system.ruby.delayHist::mean 0.164852 # delay histogram for all message -system.ruby.delayHist::stdev 1.012053 # delay histogram for all message -system.ruby.delayHist | 9285 96.27% 96.27% | 0 0.00% 96.27% | 215 2.23% 98.50% | 0 0.00% 98.50% | 0 0.00% 98.50% | 0 0.00% 98.50% | 0 0.00% 98.50% | 0 0.00% 98.50% | 145 1.50% 100.00% | 0 0.00% 100.00% # delay histogram for all message -system.ruby.delayHist::total 9645 # delay histogram for all message +system.ruby.delayHist::samples 9652 # delay histogram for all message +system.ruby.delayHist::mean 0.164525 # delay histogram for all message +system.ruby.delayHist::stdev 1.011525 # delay histogram for all message +system.ruby.delayHist | 9293 96.28% 96.28% | 0 0.00% 96.28% | 214 2.22% 98.50% | 0 0.00% 98.50% | 0 0.00% 98.50% | 0 0.00% 98.50% | 0 0.00% 98.50% | 0 0.00% 98.50% | 145 1.50% 100.00% | 0 0.00% 100.00% # delay histogram for all message +system.ruby.delayHist::total 9652 # delay histogram for all message system.ruby.outstanding_req_hist_seqr::bucket_size 1 system.ruby.outstanding_req_hist_seqr::max_bucket 9 -system.ruby.outstanding_req_hist_seqr::samples 8449 +system.ruby.outstanding_req_hist_seqr::samples 8464 system.ruby.outstanding_req_hist_seqr::mean 1 system.ruby.outstanding_req_hist_seqr::gmean 1 -system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 8449 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.outstanding_req_hist_seqr::total 8449 +system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 8464 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist_seqr::total 8464 system.ruby.latency_hist_seqr::bucket_size 64 system.ruby.latency_hist_seqr::max_bucket 639 -system.ruby.latency_hist_seqr::samples 8448 -system.ruby.latency_hist_seqr::mean 13.377367 -system.ruby.latency_hist_seqr::gmean 2.098947 -system.ruby.latency_hist_seqr::stdev 29.666839 -system.ruby.latency_hist_seqr | 7289 86.28% 86.28% | 1140 13.49% 99.78% | 4 0.05% 99.82% | 1 0.01% 99.83% | 5 0.06% 99.89% | 9 0.11% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.latency_hist_seqr::total 8448 +system.ruby.latency_hist_seqr::samples 8463 +system.ruby.latency_hist_seqr::mean 13.360747 +system.ruby.latency_hist_seqr::gmean 2.097350 +system.ruby.latency_hist_seqr::stdev 29.565169 +system.ruby.latency_hist_seqr | 7303 86.29% 86.29% | 1141 13.48% 99.78% | 4 0.05% 99.82% | 1 0.01% 99.83% | 8 0.09% 99.93% | 6 0.07% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.latency_hist_seqr::total 8463 system.ruby.hit_latency_hist_seqr::bucket_size 1 system.ruby.hit_latency_hist_seqr::max_bucket 9 -system.ruby.hit_latency_hist_seqr::samples 6958 +system.ruby.hit_latency_hist_seqr::samples 6972 system.ruby.hit_latency_hist_seqr::mean 1 system.ruby.hit_latency_hist_seqr::gmean 1 -system.ruby.hit_latency_hist_seqr | 0 0.00% 0.00% | 6958 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.hit_latency_hist_seqr::total 6958 +system.ruby.hit_latency_hist_seqr | 0 0.00% 0.00% | 6972 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.hit_latency_hist_seqr::total 6972 system.ruby.miss_latency_hist_seqr::bucket_size 64 system.ruby.miss_latency_hist_seqr::max_bucket 639 -system.ruby.miss_latency_hist_seqr::samples 1490 -system.ruby.miss_latency_hist_seqr::mean 71.177181 -system.ruby.miss_latency_hist_seqr::gmean 66.939744 -system.ruby.miss_latency_hist_seqr::stdev 30.560087 -system.ruby.miss_latency_hist_seqr | 331 22.21% 22.21% | 1140 76.51% 98.72% | 4 0.27% 98.99% | 1 0.07% 99.06% | 5 0.34% 99.40% | 9 0.60% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.miss_latency_hist_seqr::total 1490 -system.ruby.l1_cntrl0.L1Dcache.demand_hits 1249 # Number of cache demand hits -system.ruby.l1_cntrl0.L1Dcache.demand_misses 799 # Number of cache demand misses -system.ruby.l1_cntrl0.L1Dcache.demand_accesses 2048 # Number of cache demand accesses -system.ruby.l1_cntrl0.L1Icache.demand_hits 5709 # Number of cache demand hits +system.ruby.miss_latency_hist_seqr::samples 1491 +system.ruby.miss_latency_hist_seqr::mean 71.160295 +system.ruby.miss_latency_hist_seqr::gmean 66.961050 +system.ruby.miss_latency_hist_seqr::stdev 30.103565 +system.ruby.miss_latency_hist_seqr | 331 22.20% 22.20% | 1141 76.53% 98.73% | 4 0.27% 98.99% | 1 0.07% 99.06% | 8 0.54% 99.60% | 6 0.40% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.miss_latency_hist_seqr::total 1491 +system.ruby.l1_cntrl0.L1Dcache.demand_hits 1250 # Number of cache demand hits +system.ruby.l1_cntrl0.L1Dcache.demand_misses 800 # Number of cache demand misses +system.ruby.l1_cntrl0.L1Dcache.demand_accesses 2050 # Number of cache demand accesses +system.ruby.l1_cntrl0.L1Icache.demand_hits 5722 # Number of cache demand hits system.ruby.l1_cntrl0.L1Icache.demand_misses 691 # Number of cache demand misses -system.ruby.l1_cntrl0.L1Icache.demand_accesses 6400 # Number of cache demand accesses +system.ruby.l1_cntrl0.L1Icache.demand_accesses 6413 # Number of cache demand accesses system.ruby.l1_cntrl0.prefetcher.miss_observed 0 # number of misses observed system.ruby.l1_cntrl0.prefetcher.allocated_streams 0 # number of streams allocated for prefetching system.ruby.l1_cntrl0.prefetcher.prefetches_requested 0 # number of prefetch requests made @@ -411,178 +411,178 @@ system.ruby.l1_cntrl0.prefetcher.partial_hits 0 system.ruby.l1_cntrl0.prefetcher.pages_crossed 0 # number of prefetches across pages system.ruby.l1_cntrl0.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed system.ruby.l2_cntrl0.L2cache.demand_hits 30 # Number of cache demand hits -system.ruby.l2_cntrl0.L2cache.demand_misses 1460 # Number of cache demand misses -system.ruby.l2_cntrl0.L2cache.demand_accesses 1490 # Number of cache demand accesses +system.ruby.l2_cntrl0.L2cache.demand_misses 1461 # Number of cache demand misses +system.ruby.l2_cntrl0.L2cache.demand_accesses 1491 # Number of cache demand accesses system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.ruby.network.routers0.percent_links_utilized 4.310267 -system.ruby.network.routers0.msg_count.Control::0 1490 +system.ruby.network.routers0.percent_links_utilized 4.310281 +system.ruby.network.routers0.msg_count.Control::0 1491 system.ruby.network.routers0.msg_count.Request_Control::2 1041 -system.ruby.network.routers0.msg_count.Response_Data::1 1490 -system.ruby.network.routers0.msg_count.Response_Control::1 1336 -system.ruby.network.routers0.msg_count.Response_Control::2 799 +system.ruby.network.routers0.msg_count.Response_Data::1 1491 +system.ruby.network.routers0.msg_count.Response_Control::1 1337 +system.ruby.network.routers0.msg_count.Response_Control::2 800 system.ruby.network.routers0.msg_count.Writeback_Data::0 145 system.ruby.network.routers0.msg_count.Writeback_Data::1 141 -system.ruby.network.routers0.msg_count.Writeback_Control::0 291 -system.ruby.network.routers0.msg_bytes.Control::0 11920 +system.ruby.network.routers0.msg_count.Writeback_Control::0 292 +system.ruby.network.routers0.msg_bytes.Control::0 11928 system.ruby.network.routers0.msg_bytes.Request_Control::2 8328 -system.ruby.network.routers0.msg_bytes.Response_Data::1 107280 -system.ruby.network.routers0.msg_bytes.Response_Control::1 10688 -system.ruby.network.routers0.msg_bytes.Response_Control::2 6392 +system.ruby.network.routers0.msg_bytes.Response_Data::1 107352 +system.ruby.network.routers0.msg_bytes.Response_Control::1 10696 +system.ruby.network.routers0.msg_bytes.Response_Control::2 6400 system.ruby.network.routers0.msg_bytes.Writeback_Data::0 10440 system.ruby.network.routers0.msg_bytes.Writeback_Data::1 10152 -system.ruby.network.routers0.msg_bytes.Writeback_Control::0 2328 -system.ruby.network.routers1.percent_links_utilized 8.369216 -system.ruby.network.routers1.msg_count.Control::0 2950 +system.ruby.network.routers0.msg_bytes.Writeback_Control::0 2336 +system.ruby.network.routers1.percent_links_utilized 8.369194 +system.ruby.network.routers1.msg_count.Control::0 2952 system.ruby.network.routers1.msg_count.Request_Control::2 1041 -system.ruby.network.routers1.msg_count.Response_Data::1 3227 -system.ruby.network.routers1.msg_count.Response_Control::1 3963 -system.ruby.network.routers1.msg_count.Response_Control::2 799 +system.ruby.network.routers1.msg_count.Response_Data::1 3229 +system.ruby.network.routers1.msg_count.Response_Control::1 3966 +system.ruby.network.routers1.msg_count.Response_Control::2 800 system.ruby.network.routers1.msg_count.Writeback_Data::0 145 system.ruby.network.routers1.msg_count.Writeback_Data::1 141 -system.ruby.network.routers1.msg_count.Writeback_Control::0 291 -system.ruby.network.routers1.msg_bytes.Control::0 23600 +system.ruby.network.routers1.msg_count.Writeback_Control::0 292 +system.ruby.network.routers1.msg_bytes.Control::0 23616 system.ruby.network.routers1.msg_bytes.Request_Control::2 8328 -system.ruby.network.routers1.msg_bytes.Response_Data::1 232344 -system.ruby.network.routers1.msg_bytes.Response_Control::1 31704 -system.ruby.network.routers1.msg_bytes.Response_Control::2 6392 +system.ruby.network.routers1.msg_bytes.Response_Data::1 232488 +system.ruby.network.routers1.msg_bytes.Response_Control::1 31728 +system.ruby.network.routers1.msg_bytes.Response_Control::2 6400 system.ruby.network.routers1.msg_bytes.Writeback_Data::0 10440 system.ruby.network.routers1.msg_bytes.Writeback_Data::1 10152 -system.ruby.network.routers1.msg_bytes.Writeback_Control::0 2328 -system.ruby.network.routers2.percent_links_utilized 4.058949 -system.ruby.network.routers2.msg_count.Control::0 1460 -system.ruby.network.routers2.msg_count.Response_Data::1 1737 -system.ruby.network.routers2.msg_count.Response_Control::1 2627 -system.ruby.network.routers2.msg_bytes.Control::0 11680 -system.ruby.network.routers2.msg_bytes.Response_Data::1 125064 -system.ruby.network.routers2.msg_bytes.Response_Control::1 21016 -system.ruby.network.routers3.percent_links_utilized 5.579477 -system.ruby.network.routers3.msg_count.Control::0 2950 +system.ruby.network.routers1.msg_bytes.Writeback_Control::0 2336 +system.ruby.network.routers2.percent_links_utilized 4.058913 +system.ruby.network.routers2.msg_count.Control::0 1461 +system.ruby.network.routers2.msg_count.Response_Data::1 1738 +system.ruby.network.routers2.msg_count.Response_Control::1 2629 +system.ruby.network.routers2.msg_bytes.Control::0 11688 +system.ruby.network.routers2.msg_bytes.Response_Data::1 125136 +system.ruby.network.routers2.msg_bytes.Response_Control::1 21032 +system.ruby.network.routers3.percent_links_utilized 5.579463 +system.ruby.network.routers3.msg_count.Control::0 2952 system.ruby.network.routers3.msg_count.Request_Control::2 1041 -system.ruby.network.routers3.msg_count.Response_Data::1 3227 -system.ruby.network.routers3.msg_count.Response_Control::1 3963 -system.ruby.network.routers3.msg_count.Response_Control::2 799 +system.ruby.network.routers3.msg_count.Response_Data::1 3229 +system.ruby.network.routers3.msg_count.Response_Control::1 3966 +system.ruby.network.routers3.msg_count.Response_Control::2 800 system.ruby.network.routers3.msg_count.Writeback_Data::0 145 system.ruby.network.routers3.msg_count.Writeback_Data::1 141 -system.ruby.network.routers3.msg_count.Writeback_Control::0 291 -system.ruby.network.routers3.msg_bytes.Control::0 23600 +system.ruby.network.routers3.msg_count.Writeback_Control::0 292 +system.ruby.network.routers3.msg_bytes.Control::0 23616 system.ruby.network.routers3.msg_bytes.Request_Control::2 8328 -system.ruby.network.routers3.msg_bytes.Response_Data::1 232344 -system.ruby.network.routers3.msg_bytes.Response_Control::1 31704 -system.ruby.network.routers3.msg_bytes.Response_Control::2 6392 +system.ruby.network.routers3.msg_bytes.Response_Data::1 232488 +system.ruby.network.routers3.msg_bytes.Response_Control::1 31728 +system.ruby.network.routers3.msg_bytes.Response_Control::2 6400 system.ruby.network.routers3.msg_bytes.Writeback_Data::0 10440 system.ruby.network.routers3.msg_bytes.Writeback_Data::1 10152 -system.ruby.network.routers3.msg_bytes.Writeback_Control::0 2328 -system.ruby.network.msg_count.Control 8850 +system.ruby.network.routers3.msg_bytes.Writeback_Control::0 2336 +system.ruby.network.msg_count.Control 8856 system.ruby.network.msg_count.Request_Control 3123 -system.ruby.network.msg_count.Response_Data 9681 -system.ruby.network.msg_count.Response_Control 14286 +system.ruby.network.msg_count.Response_Data 9687 +system.ruby.network.msg_count.Response_Control 14298 system.ruby.network.msg_count.Writeback_Data 858 -system.ruby.network.msg_count.Writeback_Control 873 -system.ruby.network.msg_byte.Control 70800 +system.ruby.network.msg_count.Writeback_Control 876 +system.ruby.network.msg_byte.Control 70848 system.ruby.network.msg_byte.Request_Control 24984 -system.ruby.network.msg_byte.Response_Data 697032 -system.ruby.network.msg_byte.Response_Control 114288 +system.ruby.network.msg_byte.Response_Data 697464 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-system.ruby.network.routers0.throttle1.msg_count.Control::0 1490 +system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::1 107352 +system.ruby.network.routers0.throttle0.msg_bytes.Response_Control::1 3496 +system.ruby.network.routers0.throttle1.link_utilization 2.491875 +system.ruby.network.routers0.throttle1.msg_count.Control::0 1491 system.ruby.network.routers0.throttle1.msg_count.Response_Control::1 900 -system.ruby.network.routers0.throttle1.msg_count.Response_Control::2 799 +system.ruby.network.routers0.throttle1.msg_count.Response_Control::2 800 system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::0 145 system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::1 141 -system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::0 291 -system.ruby.network.routers0.throttle1.msg_bytes.Control::0 11920 +system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::0 292 +system.ruby.network.routers0.throttle1.msg_bytes.Control::0 11928 system.ruby.network.routers0.throttle1.msg_bytes.Response_Control::1 7200 -system.ruby.network.routers0.throttle1.msg_bytes.Response_Control::2 6392 +system.ruby.network.routers0.throttle1.msg_bytes.Response_Control::2 6400 system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::0 10440 system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::1 10152 -system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::0 2328 -system.ruby.network.routers1.throttle0.link_utilization 8.499094 -system.ruby.network.routers1.throttle0.msg_count.Control::0 1490 -system.ruby.network.routers1.throttle0.msg_count.Response_Data::1 1460 -system.ruby.network.routers1.throttle0.msg_count.Response_Control::1 2352 -system.ruby.network.routers1.throttle0.msg_count.Response_Control::2 799 +system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::0 2336 +system.ruby.network.routers1.throttle0.link_utilization 8.499198 +system.ruby.network.routers1.throttle0.msg_count.Control::0 1491 +system.ruby.network.routers1.throttle0.msg_count.Response_Data::1 1461 +system.ruby.network.routers1.throttle0.msg_count.Response_Control::1 2353 +system.ruby.network.routers1.throttle0.msg_count.Response_Control::2 800 system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::0 145 system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::1 141 -system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::0 291 -system.ruby.network.routers1.throttle0.msg_bytes.Control::0 11920 -system.ruby.network.routers1.throttle0.msg_bytes.Response_Data::1 105120 -system.ruby.network.routers1.throttle0.msg_bytes.Response_Control::1 18816 -system.ruby.network.routers1.throttle0.msg_bytes.Response_Control::2 6392 +system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::0 292 +system.ruby.network.routers1.throttle0.msg_bytes.Control::0 11928 +system.ruby.network.routers1.throttle0.msg_bytes.Response_Data::1 105192 +system.ruby.network.routers1.throttle0.msg_bytes.Response_Control::1 18824 +system.ruby.network.routers1.throttle0.msg_bytes.Response_Control::2 6400 system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::0 10440 system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::1 10152 -system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::0 2328 -system.ruby.network.routers1.throttle1.link_utilization 8.239338 -system.ruby.network.routers1.throttle1.msg_count.Control::0 1460 +system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::0 2336 +system.ruby.network.routers1.throttle1.link_utilization 8.239190 +system.ruby.network.routers1.throttle1.msg_count.Control::0 1461 system.ruby.network.routers1.throttle1.msg_count.Request_Control::2 1041 -system.ruby.network.routers1.throttle1.msg_count.Response_Data::1 1767 -system.ruby.network.routers1.throttle1.msg_count.Response_Control::1 1611 -system.ruby.network.routers1.throttle1.msg_bytes.Control::0 11680 +system.ruby.network.routers1.throttle1.msg_count.Response_Data::1 1768 +system.ruby.network.routers1.throttle1.msg_count.Response_Control::1 1613 +system.ruby.network.routers1.throttle1.msg_bytes.Control::0 11688 system.ruby.network.routers1.throttle1.msg_bytes.Request_Control::2 8328 -system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::1 127224 -system.ruby.network.routers1.throttle1.msg_bytes.Response_Control::1 12888 -system.ruby.network.routers2.throttle0.link_utilization 2.110983 -system.ruby.network.routers2.throttle0.msg_count.Control::0 1460 +system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::1 127296 +system.ruby.network.routers1.throttle1.msg_bytes.Response_Control::1 12904 +system.ruby.network.routers2.throttle0.link_utilization 2.110503 +system.ruby.network.routers2.throttle0.msg_count.Control::0 1461 system.ruby.network.routers2.throttle0.msg_count.Response_Data::1 277 -system.ruby.network.routers2.throttle0.msg_count.Response_Control::1 1175 -system.ruby.network.routers2.throttle0.msg_bytes.Control::0 11680 +system.ruby.network.routers2.throttle0.msg_count.Response_Control::1 1176 +system.ruby.network.routers2.throttle0.msg_bytes.Control::0 11688 system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::1 19944 -system.ruby.network.routers2.throttle0.msg_bytes.Response_Control::1 9400 -system.ruby.network.routers2.throttle1.link_utilization 6.006916 -system.ruby.network.routers2.throttle1.msg_count.Response_Data::1 1460 -system.ruby.network.routers2.throttle1.msg_count.Response_Control::1 1452 -system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::1 105120 -system.ruby.network.routers2.throttle1.msg_bytes.Response_Control::1 11616 -system.ruby.network.routers3.throttle0.link_utilization 6.128355 +system.ruby.network.routers2.throttle0.msg_bytes.Response_Control::1 9408 +system.ruby.network.routers2.throttle1.link_utilization 6.007323 +system.ruby.network.routers2.throttle1.msg_count.Response_Data::1 1461 +system.ruby.network.routers2.throttle1.msg_count.Response_Control::1 1453 +system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::1 105192 +system.ruby.network.routers2.throttle1.msg_bytes.Response_Control::1 11624 +system.ruby.network.routers3.throttle0.link_utilization 6.128687 system.ruby.network.routers3.throttle0.msg_count.Request_Control::2 1041 -system.ruby.network.routers3.throttle0.msg_count.Response_Data::1 1490 -system.ruby.network.routers3.throttle0.msg_count.Response_Control::1 436 +system.ruby.network.routers3.throttle0.msg_count.Response_Data::1 1491 +system.ruby.network.routers3.throttle0.msg_count.Response_Control::1 437 system.ruby.network.routers3.throttle0.msg_bytes.Request_Control::2 8328 -system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::1 107280 -system.ruby.network.routers3.throttle0.msg_bytes.Response_Control::1 3488 -system.ruby.network.routers3.throttle1.link_utilization 8.499094 -system.ruby.network.routers3.throttle1.msg_count.Control::0 1490 -system.ruby.network.routers3.throttle1.msg_count.Response_Data::1 1460 -system.ruby.network.routers3.throttle1.msg_count.Response_Control::1 2352 -system.ruby.network.routers3.throttle1.msg_count.Response_Control::2 799 +system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::1 107352 +system.ruby.network.routers3.throttle0.msg_bytes.Response_Control::1 3496 +system.ruby.network.routers3.throttle1.link_utilization 8.499198 +system.ruby.network.routers3.throttle1.msg_count.Control::0 1491 +system.ruby.network.routers3.throttle1.msg_count.Response_Data::1 1461 +system.ruby.network.routers3.throttle1.msg_count.Response_Control::1 2353 +system.ruby.network.routers3.throttle1.msg_count.Response_Control::2 800 system.ruby.network.routers3.throttle1.msg_count.Writeback_Data::0 145 system.ruby.network.routers3.throttle1.msg_count.Writeback_Data::1 141 -system.ruby.network.routers3.throttle1.msg_count.Writeback_Control::0 291 -system.ruby.network.routers3.throttle1.msg_bytes.Control::0 11920 -system.ruby.network.routers3.throttle1.msg_bytes.Response_Data::1 105120 -system.ruby.network.routers3.throttle1.msg_bytes.Response_Control::1 18816 -system.ruby.network.routers3.throttle1.msg_bytes.Response_Control::2 6392 +system.ruby.network.routers3.throttle1.msg_count.Writeback_Control::0 292 +system.ruby.network.routers3.throttle1.msg_bytes.Control::0 11928 +system.ruby.network.routers3.throttle1.msg_bytes.Response_Data::1 105192 +system.ruby.network.routers3.throttle1.msg_bytes.Response_Control::1 18824 +system.ruby.network.routers3.throttle1.msg_bytes.Response_Control::2 6400 system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::0 10440 system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::1 10152 -system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::0 2328 -system.ruby.network.routers3.throttle2.link_utilization 2.110983 -system.ruby.network.routers3.throttle2.msg_count.Control::0 1460 +system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::0 2336 +system.ruby.network.routers3.throttle2.link_utilization 2.110503 +system.ruby.network.routers3.throttle2.msg_count.Control::0 1461 system.ruby.network.routers3.throttle2.msg_count.Response_Data::1 277 -system.ruby.network.routers3.throttle2.msg_count.Response_Control::1 1175 -system.ruby.network.routers3.throttle2.msg_bytes.Control::0 11680 +system.ruby.network.routers3.throttle2.msg_count.Response_Control::1 1176 +system.ruby.network.routers3.throttle2.msg_bytes.Control::0 11688 system.ruby.network.routers3.throttle2.msg_bytes.Response_Data::1 19944 -system.ruby.network.routers3.throttle2.msg_bytes.Response_Control::1 9400 +system.ruby.network.routers3.throttle2.msg_bytes.Response_Control::1 9408 system.ruby.delayVCHist.vnet_0::bucket_size 1 # delay histogram for vnet_0 system.ruby.delayVCHist.vnet_0::max_bucket 9 # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0::samples 2725 # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0::mean 0.425688 # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0::stdev 1.795962 # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0 | 2580 94.68% 94.68% | 0 0.00% 94.68% | 0 0.00% 94.68% | 0 0.00% 94.68% | 0 0.00% 94.68% | 0 0.00% 94.68% | 0 0.00% 94.68% | 0 0.00% 94.68% | 145 5.32% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0::total 2725 # delay histogram for vnet_0 +system.ruby.delayVCHist.vnet_0::samples 2728 # delay histogram for vnet_0 +system.ruby.delayVCHist.vnet_0::mean 0.425220 # delay histogram for vnet_0 +system.ruby.delayVCHist.vnet_0::stdev 1.795029 # delay histogram for vnet_0 +system.ruby.delayVCHist.vnet_0 | 2583 94.68% 94.68% | 0 0.00% 94.68% | 0 0.00% 94.68% | 0 0.00% 94.68% | 0 0.00% 94.68% | 0 0.00% 94.68% | 0 0.00% 94.68% | 0 0.00% 94.68% | 145 5.32% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_0 +system.ruby.delayVCHist.vnet_0::total 2728 # delay histogram for vnet_0 system.ruby.delayVCHist.vnet_1::bucket_size 1 # delay histogram for vnet_1 system.ruby.delayVCHist.vnet_1::max_bucket 9 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::samples 5879 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::mean 0.073142 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::stdev 0.375443 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1 | 5664 96.34% 96.34% | 0 0.00% 96.34% | 215 3.66% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::total 5879 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::samples 5883 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::mean 0.072752 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::stdev 0.374480 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1 | 5669 96.36% 96.36% | 0 0.00% 96.36% | 214 3.64% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::total 5883 # delay histogram for vnet_1 system.ruby.delayVCHist.vnet_2::bucket_size 1 # delay histogram for vnet_2 system.ruby.delayVCHist.vnet_2::max_bucket 9 # delay histogram for vnet_2 system.ruby.delayVCHist.vnet_2::samples 1041 # delay histogram for vnet_2 @@ -590,34 +590,34 @@ system.ruby.delayVCHist.vnet_2 | 1041 100.00% 100.00% | system.ruby.delayVCHist.vnet_2::total 1041 # delay histogram for vnet_2 system.ruby.LD.latency_hist_seqr::bucket_size 64 system.ruby.LD.latency_hist_seqr::max_bucket 639 -system.ruby.LD.latency_hist_seqr::samples 1183 -system.ruby.LD.latency_hist_seqr::mean 33.972105 -system.ruby.LD.latency_hist_seqr::gmean 7.701642 -system.ruby.LD.latency_hist_seqr::stdev 40.478944 -system.ruby.LD.latency_hist_seqr | 802 67.79% 67.79% | 375 31.70% 99.49% | 0 0.00% 99.49% | 0 0.00% 99.49% | 2 0.17% 99.66% | 4 0.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.latency_hist_seqr::total 1183 +system.ruby.LD.latency_hist_seqr::samples 1185 +system.ruby.LD.latency_hist_seqr::mean 33.565401 +system.ruby.LD.latency_hist_seqr::gmean 7.686795 +system.ruby.LD.latency_hist_seqr::stdev 38.515936 +system.ruby.LD.latency_hist_seqr | 803 67.76% 67.76% | 378 31.90% 99.66% | 0 0.00% 99.66% | 0 0.00% 99.66% | 3 0.25% 99.92% | 1 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.latency_hist_seqr::total 1185 system.ruby.LD.hit_latency_hist_seqr::bucket_size 1 system.ruby.LD.hit_latency_hist_seqr::max_bucket 9 -system.ruby.LD.hit_latency_hist_seqr::samples 600 +system.ruby.LD.hit_latency_hist_seqr::samples 601 system.ruby.LD.hit_latency_hist_seqr::mean 1 system.ruby.LD.hit_latency_hist_seqr::gmean 1 -system.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 600 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.hit_latency_hist_seqr::total 600 +system.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 601 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.hit_latency_hist_seqr::total 601 system.ruby.LD.miss_latency_hist_seqr::bucket_size 64 system.ruby.LD.miss_latency_hist_seqr::max_bucket 639 -system.ruby.LD.miss_latency_hist_seqr::samples 583 -system.ruby.LD.miss_latency_hist_seqr::mean 67.905660 -system.ruby.LD.miss_latency_hist_seqr::gmean 62.953372 -system.ruby.LD.miss_latency_hist_seqr::stdev 32.457951 -system.ruby.LD.miss_latency_hist_seqr | 202 34.65% 34.65% | 375 64.32% 98.97% | 0 0.00% 98.97% | 0 0.00% 98.97% | 2 0.34% 99.31% | 4 0.69% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.miss_latency_hist_seqr::total 583 +system.ruby.LD.miss_latency_hist_seqr::samples 584 +system.ruby.LD.miss_latency_hist_seqr::mean 67.078767 +system.ruby.LD.miss_latency_hist_seqr::gmean 62.700967 +system.ruby.LD.miss_latency_hist_seqr::stdev 28.185747 +system.ruby.LD.miss_latency_hist_seqr | 202 34.59% 34.59% | 378 64.73% 99.32% | 0 0.00% 99.32% | 0 0.00% 99.32% | 3 0.51% 99.83% | 1 0.17% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.miss_latency_hist_seqr::total 584 system.ruby.ST.latency_hist_seqr::bucket_size 64 system.ruby.ST.latency_hist_seqr::max_bucket 639 system.ruby.ST.latency_hist_seqr::samples 865 -system.ruby.ST.latency_hist_seqr::mean 15.273988 -system.ruby.ST.latency_hist_seqr::gmean 2.701326 -system.ruby.ST.latency_hist_seqr::stdev 28.276128 -system.ruby.ST.latency_hist_seqr | 773 89.36% 89.36% | 91 10.52% 99.88% | 0 0.00% 99.88% | 0 0.00% 99.88% | 0 0.00% 99.88% | 1 0.12% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.latency_hist_seqr::mean 15.551445 +system.ruby.ST.latency_hist_seqr::gmean 2.706248 +system.ruby.ST.latency_hist_seqr::stdev 29.831548 +system.ruby.ST.latency_hist_seqr | 773 89.36% 89.36% | 90 10.40% 99.77% | 0 0.00% 99.77% | 0 0.00% 99.77% | 1 0.12% 99.88% | 1 0.12% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ST.latency_hist_seqr::total 865 system.ruby.ST.hit_latency_hist_seqr::bucket_size 1 system.ruby.ST.hit_latency_hist_seqr::max_bucket 9 @@ -629,53 +629,53 @@ system.ruby.ST.hit_latency_hist_seqr::total 649 system.ruby.ST.miss_latency_hist_seqr::bucket_size 64 system.ruby.ST.miss_latency_hist_seqr::max_bucket 639 system.ruby.ST.miss_latency_hist_seqr::samples 216 -system.ruby.ST.miss_latency_hist_seqr::mean 58.162037 -system.ruby.ST.miss_latency_hist_seqr::gmean 53.494090 -system.ruby.ST.miss_latency_hist_seqr::stdev 27.387260 -system.ruby.ST.miss_latency_hist_seqr | 124 57.41% 57.41% | 91 42.13% 99.54% | 0 0.00% 99.54% | 0 0.00% 99.54% | 0 0.00% 99.54% | 1 0.46% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.miss_latency_hist_seqr::mean 59.273148 +system.ruby.ST.miss_latency_hist_seqr::gmean 53.885554 +system.ruby.ST.miss_latency_hist_seqr::stdev 31.884011 +system.ruby.ST.miss_latency_hist_seqr | 124 57.41% 57.41% | 90 41.67% 99.07% | 0 0.00% 99.07% | 0 0.00% 99.07% | 1 0.46% 99.54% | 1 0.46% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ST.miss_latency_hist_seqr::total 216 system.ruby.IFETCH.latency_hist_seqr::bucket_size 64 system.ruby.IFETCH.latency_hist_seqr::max_bucket 639 -system.ruby.IFETCH.latency_hist_seqr::samples 6400 -system.ruby.IFETCH.latency_hist_seqr::mean 9.314219 -system.ruby.IFETCH.latency_hist_seqr::gmean 1.595263 -system.ruby.IFETCH.latency_hist_seqr::stdev 25.608064 -system.ruby.IFETCH.latency_hist_seqr | 5714 89.28% 89.28% | 674 10.53% 99.81% | 4 0.06% 99.88% | 1 0.02% 99.89% | 3 0.05% 99.94% | 4 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.latency_hist_seqr::total 6400 +system.ruby.IFETCH.latency_hist_seqr::samples 6413 +system.ruby.IFETCH.latency_hist_seqr::mean 9.331826 +system.ruby.IFETCH.latency_hist_seqr::gmean 1.594079 +system.ruby.IFETCH.latency_hist_seqr::stdev 25.833878 +system.ruby.IFETCH.latency_hist_seqr | 5727 89.30% 89.30% | 673 10.49% 99.80% | 4 0.06% 99.86% | 1 0.02% 99.88% | 4 0.06% 99.94% | 4 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.latency_hist_seqr::total 6413 system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 1 system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 9 -system.ruby.IFETCH.hit_latency_hist_seqr::samples 5709 +system.ruby.IFETCH.hit_latency_hist_seqr::samples 5722 system.ruby.IFETCH.hit_latency_hist_seqr::mean 1 system.ruby.IFETCH.hit_latency_hist_seqr::gmean 1 -system.ruby.IFETCH.hit_latency_hist_seqr | 0 0.00% 0.00% | 5709 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.hit_latency_hist_seqr::total 5709 +system.ruby.IFETCH.hit_latency_hist_seqr | 0 0.00% 0.00% | 5722 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.hit_latency_hist_seqr::total 5722 system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 64 system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 639 system.ruby.IFETCH.miss_latency_hist_seqr::samples 691 -system.ruby.IFETCH.miss_latency_hist_seqr::mean 78.005789 -system.ruby.IFETCH.miss_latency_hist_seqr::gmean 75.617268 -system.ruby.IFETCH.miss_latency_hist_seqr::stdev 28.004761 -system.ruby.IFETCH.miss_latency_hist_seqr | 5 0.72% 0.72% | 674 97.54% 98.26% | 4 0.58% 98.84% | 1 0.14% 98.99% | 3 0.43% 99.42% | 4 0.58% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.miss_latency_hist_seqr::mean 78.325615 +system.ruby.IFETCH.miss_latency_hist_seqr::gmean 75.760449 +system.ruby.IFETCH.miss_latency_hist_seqr::stdev 29.311514 +system.ruby.IFETCH.miss_latency_hist_seqr | 5 0.72% 0.72% | 673 97.40% 98.12% | 4 0.58% 98.70% | 1 0.14% 98.84% | 4 0.58% 99.42% | 4 0.58% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.miss_latency_hist_seqr::total 691 -system.ruby.Directory_Controller.Fetch 1460 0.00% 0.00% +system.ruby.Directory_Controller.Fetch 1461 0.00% 0.00% system.ruby.Directory_Controller.Data 277 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 1460 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 1461 0.00% 0.00% system.ruby.Directory_Controller.Memory_Ack 277 0.00% 0.00% -system.ruby.Directory_Controller.CleanReplacement 1175 0.00% 0.00% -system.ruby.Directory_Controller.I.Fetch 1460 0.00% 0.00% +system.ruby.Directory_Controller.CleanReplacement 1176 0.00% 0.00% +system.ruby.Directory_Controller.I.Fetch 1461 0.00% 0.00% system.ruby.Directory_Controller.M.Data 277 0.00% 0.00% -system.ruby.Directory_Controller.M.CleanReplacement 1175 0.00% 0.00% -system.ruby.Directory_Controller.IM.Memory_Data 1460 0.00% 0.00% +system.ruby.Directory_Controller.M.CleanReplacement 1176 0.00% 0.00% +system.ruby.Directory_Controller.IM.Memory_Data 1461 0.00% 0.00% system.ruby.Directory_Controller.MI.Memory_Ack 277 0.00% 0.00% -system.ruby.L1Cache_Controller.Load 1183 0.00% 0.00% -system.ruby.L1Cache_Controller.Ifetch 6400 0.00% 0.00% +system.ruby.L1Cache_Controller.Load 1185 0.00% 0.00% +system.ruby.L1Cache_Controller.Ifetch 6413 0.00% 0.00% system.ruby.L1Cache_Controller.Store 865 0.00% 0.00% system.ruby.L1Cache_Controller.Inv 1041 0.00% 0.00% -system.ruby.L1Cache_Controller.L1_Replacement 1354 0.00% 0.00% -system.ruby.L1Cache_Controller.Data_Exclusive 583 0.00% 0.00% +system.ruby.L1Cache_Controller.L1_Replacement 1355 0.00% 0.00% +system.ruby.L1Cache_Controller.Data_Exclusive 584 0.00% 0.00% system.ruby.L1Cache_Controller.Data_all_Acks 907 0.00% 0.00% -system.ruby.L1Cache_Controller.WB_Ack 436 0.00% 0.00% -system.ruby.L1Cache_Controller.NP.Load 525 0.00% 0.00% +system.ruby.L1Cache_Controller.WB_Ack 437 0.00% 0.00% +system.ruby.L1Cache_Controller.NP.Load 526 0.00% 0.00% system.ruby.L1Cache_Controller.NP.Ifetch 646 0.00% 0.00% system.ruby.L1Cache_Controller.NP.Store 191 0.00% 0.00% system.ruby.L1Cache_Controller.NP.Inv 356 0.00% 0.00% @@ -683,53 +683,53 @@ system.ruby.L1Cache_Controller.I.Load 58 0.00% 0.00% system.ruby.L1Cache_Controller.I.Ifetch 45 0.00% 0.00% system.ruby.L1Cache_Controller.I.Store 25 0.00% 0.00% system.ruby.L1Cache_Controller.I.L1_Replacement 556 0.00% 0.00% -system.ruby.L1Cache_Controller.S.Ifetch 5709 0.00% 0.00% +system.ruby.L1Cache_Controller.S.Ifetch 5722 0.00% 0.00% system.ruby.L1Cache_Controller.S.Inv 325 0.00% 0.00% system.ruby.L1Cache_Controller.S.L1_Replacement 362 0.00% 0.00% -system.ruby.L1Cache_Controller.E.Load 452 0.00% 0.00% +system.ruby.L1Cache_Controller.E.Load 453 0.00% 0.00% system.ruby.L1Cache_Controller.E.Store 71 0.00% 0.00% system.ruby.L1Cache_Controller.E.Inv 219 0.00% 0.00% -system.ruby.L1Cache_Controller.E.L1_Replacement 291 0.00% 0.00% +system.ruby.L1Cache_Controller.E.L1_Replacement 292 0.00% 0.00% system.ruby.L1Cache_Controller.M.Load 148 0.00% 0.00% system.ruby.L1Cache_Controller.M.Store 578 0.00% 0.00% system.ruby.L1Cache_Controller.M.Inv 141 0.00% 0.00% system.ruby.L1Cache_Controller.M.L1_Replacement 145 0.00% 0.00% -system.ruby.L1Cache_Controller.IS.Data_Exclusive 583 0.00% 0.00% +system.ruby.L1Cache_Controller.IS.Data_Exclusive 584 0.00% 0.00% system.ruby.L1Cache_Controller.IS.Data_all_Acks 691 0.00% 0.00% system.ruby.L1Cache_Controller.IM.Data_all_Acks 216 0.00% 0.00% -system.ruby.L1Cache_Controller.M_I.WB_Ack 436 0.00% 0.00% +system.ruby.L1Cache_Controller.M_I.WB_Ack 437 0.00% 0.00% system.ruby.L2Cache_Controller.L1_GET_INSTR 691 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_GETS 583 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_GETS 584 0.00% 0.00% system.ruby.L2Cache_Controller.L1_GETX 216 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_PUTX 436 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_PUTX 437 0.00% 0.00% system.ruby.L2Cache_Controller.L2_Replacement 142 0.00% 0.00% -system.ruby.L2Cache_Controller.L2_Replacement_clean 1310 0.00% 0.00% -system.ruby.L2Cache_Controller.Mem_Data 1460 0.00% 0.00% -system.ruby.L2Cache_Controller.Mem_Ack 1452 0.00% 0.00% +system.ruby.L2Cache_Controller.L2_Replacement_clean 1311 0.00% 0.00% +system.ruby.L2Cache_Controller.Mem_Data 1461 0.00% 0.00% +system.ruby.L2Cache_Controller.Mem_Ack 1453 0.00% 0.00% system.ruby.L2Cache_Controller.WB_Data 141 0.00% 0.00% system.ruby.L2Cache_Controller.Ack_all 900 0.00% 0.00% -system.ruby.L2Cache_Controller.Exclusive_Unblock 799 0.00% 0.00% +system.ruby.L2Cache_Controller.Exclusive_Unblock 800 0.00% 0.00% system.ruby.L2Cache_Controller.NP.L1_GET_INSTR 686 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.L1_GETS 570 0.00% 0.00% +system.ruby.L2Cache_Controller.NP.L1_GETS 571 0.00% 0.00% system.ruby.L2Cache_Controller.NP.L1_GETX 204 0.00% 0.00% system.ruby.L2Cache_Controller.SS.L1_GET_INSTR 5 0.00% 0.00% system.ruby.L2Cache_Controller.SS.L2_Replacement_clean 681 0.00% 0.00% system.ruby.L2Cache_Controller.M.L1_GETS 13 0.00% 0.00% system.ruby.L2Cache_Controller.M.L1_GETX 12 0.00% 0.00% system.ruby.L2Cache_Controller.M.L2_Replacement 134 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L2_Replacement_clean 277 0.00% 0.00% -system.ruby.L2Cache_Controller.MT.L1_PUTX 436 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L2_Replacement_clean 278 0.00% 0.00% +system.ruby.L2Cache_Controller.MT.L1_PUTX 437 0.00% 0.00% system.ruby.L2Cache_Controller.MT.L2_Replacement 8 0.00% 0.00% system.ruby.L2Cache_Controller.MT.L2_Replacement_clean 352 0.00% 0.00% -system.ruby.L2Cache_Controller.M_I.Mem_Ack 1452 0.00% 0.00% +system.ruby.L2Cache_Controller.M_I.Mem_Ack 1453 0.00% 0.00% system.ruby.L2Cache_Controller.MT_I.WB_Data 6 0.00% 0.00% system.ruby.L2Cache_Controller.MT_I.Ack_all 2 0.00% 0.00% system.ruby.L2Cache_Controller.MCT_I.WB_Data 135 0.00% 0.00% system.ruby.L2Cache_Controller.MCT_I.Ack_all 217 0.00% 0.00% system.ruby.L2Cache_Controller.I_I.Ack_all 681 0.00% 0.00% -system.ruby.L2Cache_Controller.ISS.Mem_Data 570 0.00% 0.00% +system.ruby.L2Cache_Controller.ISS.Mem_Data 571 0.00% 0.00% system.ruby.L2Cache_Controller.IS.Mem_Data 686 0.00% 0.00% system.ruby.L2Cache_Controller.IM.Mem_Data 204 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_MB.Exclusive_Unblock 799 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_MB.Exclusive_Unblock 800 0.00% 0.00% ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini index 87378aae3..72c6ff442 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini @@ -120,7 +120,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello +executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin kvmInSE=false diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout index ce03b27b1..c750cc80b 100755 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout @@ -1,13 +1,15 @@ +Redirecting stdout to build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout +Redirecting stderr to build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 21 2016 14:06:59 -gem5 started Jan 21 2016 14:07:35 -gem5 executing on zizzer, pid 50076 -command line: build/ALPHA_MOESI_CMP_directory/gem5.opt -d build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory +gem5 compiled Mar 14 2016 22:01:23 +gem5 started Mar 14 2016 22:02:29 +gem5 executing on phenom, pid 29128 +command line: build/ALPHA_MOESI_CMP_directory/gem5.opt -d build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 108694 because target called exit() +Exiting @ tick 108878 because target called exit() diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt index adb01be8a..58f4afdee 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt @@ -1,43 +1,43 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000109 # Number of seconds simulated -sim_ticks 108694 # Number of ticks simulated -final_tick 108694 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 108878 # Number of ticks simulated +final_tick 108878 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 71872 # Simulator instruction rate (inst/s) -host_op_rate 71865 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1222276 # Simulator tick rate (ticks/s) -host_mem_usage 417856 # Number of bytes of host memory used -host_seconds 0.09 # Real time elapsed on the host -sim_insts 6390 # Number of instructions simulated -sim_ops 6390 # Number of ops (including micro ops) simulated +host_inst_rate 17471 # Simulator instruction rate (inst/s) +host_op_rate 17470 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 297052 # Simulator tick rate (ticks/s) +host_mem_usage 393472 # Number of bytes of host memory used +host_seconds 0.37 # Real time elapsed on the host +sim_insts 6403 # Number of instructions simulated +sim_ops 6403 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks -system.mem_ctrls.bytes_read::ruby.dir_cntrl0 75648 # Number of bytes read from this memory -system.mem_ctrls.bytes_read::total 75648 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::ruby.dir_cntrl0 75712 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 75712 # Number of bytes read from this memory system.mem_ctrls.bytes_written::ruby.dir_cntrl0 12416 # Number of bytes written to this memory system.mem_ctrls.bytes_written::total 12416 # Number of bytes written to this memory -system.mem_ctrls.num_reads::ruby.dir_cntrl0 1182 # Number of read requests responded to by this memory -system.mem_ctrls.num_reads::total 1182 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::ruby.dir_cntrl0 1183 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 1183 # Number of read requests responded to by this memory system.mem_ctrls.num_writes::ruby.dir_cntrl0 194 # Number of write requests responded to by this memory system.mem_ctrls.num_writes::total 194 # Number of write requests responded to by this memory -system.mem_ctrls.bw_read::ruby.dir_cntrl0 695972179 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_read::total 695972179 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::ruby.dir_cntrl0 114228936 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::total 114228936 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_total::ruby.dir_cntrl0 810201115 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.bw_total::total 810201115 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.readReqs 1182 # Number of read requests accepted +system.mem_ctrls.bw_read::ruby.dir_cntrl0 695383824 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 695383824 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::ruby.dir_cntrl0 114035893 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::total 114035893 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::ruby.dir_cntrl0 809419717 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 809419717 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.readReqs 1183 # Number of read requests accepted system.mem_ctrls.writeReqs 194 # Number of write requests accepted -system.mem_ctrls.readBursts 1182 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.readBursts 1183 # Number of DRAM read bursts, including those serviced by the write queue system.mem_ctrls.writeBursts 194 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrls.bytesReadDRAM 64448 # Total number of bytes read from DRAM -system.mem_ctrls.bytesReadWrQ 11200 # Total number of bytes read from write queue -system.mem_ctrls.bytesWritten 5440 # Total number of bytes written to DRAM -system.mem_ctrls.bytesReadSys 75648 # Total read bytes from the system interface side +system.mem_ctrls.bytesReadDRAM 64576 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 11136 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 5504 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 75712 # Total read bytes from the system interface side system.mem_ctrls.bytesWrittenSys 12416 # Total written bytes from the system interface side -system.mem_ctrls.servicedByWrQ 175 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrls.mergedWrBursts 82 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.servicedByWrQ 174 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 81 # Number of DRAM write bursts merged with an existing one system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.mem_ctrls.perBankRdBursts::0 83 # Per bank write bursts system.mem_ctrls.perBankRdBursts::1 51 # Per bank write bursts @@ -53,13 +53,13 @@ system.mem_ctrls.perBankRdBursts::10 56 # Pe system.mem_ctrls.perBankRdBursts::11 51 # Per bank write bursts system.mem_ctrls.perBankRdBursts::12 21 # Per bank write bursts system.mem_ctrls.perBankRdBursts::13 365 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::14 66 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::15 40 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 67 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::15 41 # Per bank write bursts system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::4 17 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 18 # Per bank write bursts system.mem_ctrls.perBankWrBursts::5 6 # Per bank write bursts system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts @@ -73,14 +73,14 @@ system.mem_ctrls.perBankWrBursts::14 41 # Pe system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrls.totGap 108642 # Total gap between requests +system.mem_ctrls.totGap 108826 # Total gap between requests system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::6 1182 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 1183 # Read request sizes (log2) system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) @@ -88,7 +88,7 @@ system.mem_ctrls.writePktSize::3 0 # Wr system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::6 194 # Write request sizes (log2) -system.mem_ctrls.rdQLenPdf::0 1007 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::0 1009 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see @@ -135,18 +135,18 @@ system.mem_ctrls.wrQLenPdf::11 1 # Wh system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::15 3 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 4 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::16 4 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::17 5 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 4 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::18 6 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::19 6 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::20 7 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 6 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::21 6 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::22 6 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::23 6 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 7 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::24 6 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::25 6 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::26 6 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 7 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::27 5 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::28 5 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::29 5 # What write queue length does an incoming req see @@ -184,109 +184,108 @@ system.mem_ctrls.wrQLenPdf::60 0 # Wh system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrls.bytesPerActivate::samples 202 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::mean 335.524752 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::gmean 204.886741 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::stdev 324.305016 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::0-127 65 32.18% 32.18% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::128-255 47 23.27% 55.45% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::256-383 21 10.40% 65.84% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::384-511 14 6.93% 72.77% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::512-639 12 5.94% 78.71% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::640-767 11 5.45% 84.16% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::768-895 6 2.97% 87.13% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::896-1023 5 2.48% 89.60% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::1024-1151 21 10.40% 100.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::total 202 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::samples 203 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 334.817734 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 202.715946 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 328.878595 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 65 32.02% 32.02% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 47 23.15% 55.17% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 25 12.32% 67.49% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 11 5.42% 72.91% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 11 5.42% 78.33% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 10 4.93% 83.25% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 5 2.46% 85.71% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 8 3.94% 89.66% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 21 10.34% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 203 # Bytes accessed per row activation system.mem_ctrls.rdPerTurnAround::samples 5 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::mean 141.200000 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::gmean 107.481731 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::stdev 78.180560 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::mean 138.600000 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::gmean 101.703151 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::stdev 85.219129 # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::16-23 1 20.00% 20.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::128-135 1 20.00% 40.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::136-143 1 20.00% 60.00% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::80-87 1 20.00% 40.00% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::168-175 1 20.00% 60.00% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::192-199 1 20.00% 80.00% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::216-223 1 20.00% 100.00% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::total 5 # Reads before turning the bus around for writes system.mem_ctrls.wrPerTurnAround::samples 5 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::mean 17 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::gmean 16.976446 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::stdev 1 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::mean 17.200000 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::gmean 17.171629 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::stdev 1.095445 # Writes before turning the bus around for reads system.mem_ctrls.wrPerTurnAround::16 2 40.00% 40.00% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::17 1 20.00% 60.00% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::18 2 40.00% 100.00% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::18 3 60.00% 100.00% # Writes before turning the bus around for reads system.mem_ctrls.wrPerTurnAround::total 5 # Writes before turning the bus around for reads -system.mem_ctrls.totQLat 6988 # Total ticks spent queuing -system.mem_ctrls.totMemAccLat 26121 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrls.totBusLat 5035 # Total ticks spent in databus transfers -system.mem_ctrls.avgQLat 6.94 # Average queueing delay per DRAM burst +system.mem_ctrls.totQLat 7036 # Total ticks spent queuing +system.mem_ctrls.totMemAccLat 26207 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.totBusLat 5045 # Total ticks spent in databus transfers +system.mem_ctrls.avgQLat 6.97 # Average queueing delay per DRAM burst system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst -system.mem_ctrls.avgMemAccLat 25.94 # Average memory access latency per DRAM burst -system.mem_ctrls.avgRdBW 592.93 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrls.avgWrBW 50.05 # Average achieved write bandwidth in MiByte/s -system.mem_ctrls.avgRdBWSys 695.97 # Average system read bandwidth in MiByte/s -system.mem_ctrls.avgWrBWSys 114.23 # Average system write bandwidth in MiByte/s +system.mem_ctrls.avgMemAccLat 25.97 # Average memory access latency per DRAM burst +system.mem_ctrls.avgRdBW 593.10 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 50.55 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 695.38 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 114.04 # Average system write bandwidth in MiByte/s system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrls.busUtil 5.02 # Data bus utilization in percentage +system.mem_ctrls.busUtil 5.03 # Data bus utilization in percentage system.mem_ctrls.busUtilRead 4.63 # Data bus utilization in percentage for reads system.mem_ctrls.busUtilWrite 0.39 # Data bus utilization in percentage for writes system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing -system.mem_ctrls.avgWrQLen 21.56 # Average write queue length when enqueuing -system.mem_ctrls.readRowHits 807 # Number of row buffer hits during reads -system.mem_ctrls.writeRowHits 77 # Number of row buffer hits during writes -system.mem_ctrls.readRowHitRate 80.14 # Row buffer hit rate for reads -system.mem_ctrls.writeRowHitRate 68.75 # Row buffer hit rate for writes -system.mem_ctrls.avgGap 78.95 # Average gap between requests -system.mem_ctrls.pageHitRate 79.00 # Row buffer hit rate, read and write combined +system.mem_ctrls.avgWrQLen 21.05 # Average write queue length when enqueuing +system.mem_ctrls.readRowHits 806 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 80 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 79.88 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate 70.80 # Row buffer hit rate for writes +system.mem_ctrls.avgGap 79.03 # Average gap between requests +system.mem_ctrls.pageHitRate 78.97 # Row buffer hit rate, read and write combined system.mem_ctrls_0.actEnergy 529200 # Energy for activate commands per rank (pJ) system.mem_ctrls_0.preEnergy 294000 # Energy for precharge commands per rank (pJ) system.mem_ctrls_0.readEnergy 5004480 # Energy for read commands per rank (pJ) -system.mem_ctrls_0.writeEnergy 238464 # Energy for write commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 248832 # Energy for write commands per rank (pJ) system.mem_ctrls_0.refreshEnergy 6611280 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_0.actBackEnergy 62170812 # Energy for active background per rank (pJ) -system.mem_ctrls_0.preBackEnergy 6351000 # Energy for precharge background per rank (pJ) -system.mem_ctrls_0.totalEnergy 81199236 # Total energy per rank (pJ) -system.mem_ctrls_0.averagePower 800.165908 # Core power per rank (mW) -system.mem_ctrls_0.memoryStateTime::IDLE 15769 # Time in different power states +system.mem_ctrls_0.actBackEnergy 61961508 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 6534600 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.totalEnergy 81183900 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 800.014782 # Core power per rank (mW) +system.mem_ctrls_0.memoryStateTime::IDLE 16245 # Time in different power states system.mem_ctrls_0.memoryStateTime::REF 3380 # Time in different power states system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT 87863 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 87571 # Time in different power states system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.mem_ctrls_1.actEnergy 907200 # Energy for activate commands per rank (pJ) system.mem_ctrls_1.preEnergy 504000 # Energy for precharge commands per rank (pJ) system.mem_ctrls_1.readEnergy 6764160 # Energy for read commands per rank (pJ) system.mem_ctrls_1.writeEnergy 642816 # Energy for write commands per rank (pJ) system.mem_ctrls_1.refreshEnergy 6611280 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_1.actBackEnergy 67286448 # Energy for active background per rank (pJ) -system.mem_ctrls_1.preBackEnergy 1863600 # Energy for precharge background per rank (pJ) -system.mem_ctrls_1.totalEnergy 84579504 # Total energy per rank (pJ) -system.mem_ctrls_1.averagePower 833.476261 # Core power per rank (mW) -system.mem_ctrls_1.memoryStateTime::IDLE 2630 # Time in different power states +system.mem_ctrls_1.actBackEnergy 67902048 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 1323600 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.totalEnergy 84655104 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 834.221250 # Core power per rank (mW) +system.mem_ctrls_1.memoryStateTime::IDLE 1730 # Time in different power states system.mem_ctrls_1.memoryStateTime::REF 3380 # Time in different power states system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT 95482 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 96382 # Time in different power states system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.clk_domain.clock 1 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 1183 # DTB read hits +system.cpu.dtb.read_hits 1185 # DTB read hits system.cpu.dtb.read_misses 7 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 1190 # DTB read accesses +system.cpu.dtb.read_accesses 1192 # DTB read accesses system.cpu.dtb.write_hits 865 # DTB write hits system.cpu.dtb.write_misses 3 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations system.cpu.dtb.write_accesses 868 # DTB write accesses -system.cpu.dtb.data_hits 2048 # DTB hits +system.cpu.dtb.data_hits 2050 # DTB hits system.cpu.dtb.data_misses 10 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 2058 # DTB accesses -system.cpu.itb.fetch_hits 6401 # ITB hits +system.cpu.dtb.data_accesses 2060 # DTB accesses +system.cpu.itb.fetch_hits 6414 # ITB hits system.cpu.itb.fetch_misses 17 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 6418 # ITB accesses +system.cpu.itb.fetch_accesses 6431 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -300,292 +299,292 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 108694 # number of cpu cycles simulated +system.cpu.numCycles 108878 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 6390 # Number of instructions committed -system.cpu.committedOps 6390 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 6317 # Number of integer alu accesses +system.cpu.committedInsts 6403 # Number of instructions committed +system.cpu.committedOps 6403 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 6329 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses system.cpu.num_func_calls 251 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 749 # number of instructions that are conditional controls -system.cpu.num_int_insts 6317 # number of integer instructions +system.cpu.num_conditional_control_insts 754 # number of instructions that are conditional controls +system.cpu.num_int_insts 6329 # number of integer instructions system.cpu.num_fp_insts 10 # number of float instructions -system.cpu.num_int_register_reads 8285 # number of times the integer registers were read -system.cpu.num_int_register_writes 4568 # number of times the integer registers were written +system.cpu.num_int_register_reads 8297 # number of times the integer registers were read +system.cpu.num_int_register_writes 4575 # number of times the integer registers were written system.cpu.num_fp_register_reads 8 # number of times the floating registers were read system.cpu.num_fp_register_writes 2 # number of times the floating registers were written -system.cpu.num_mem_refs 2058 # number of memory refs -system.cpu.num_load_insts 1190 # Number of load instructions +system.cpu.num_mem_refs 2060 # number of memory refs +system.cpu.num_load_insts 1192 # Number of load instructions system.cpu.num_store_insts 868 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 108694 # Number of busy cycles +system.cpu.num_busy_cycles 108878 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 1050 # Number of branches fetched +system.cpu.Branches 1056 # Number of branches fetched system.cpu.op_class::No_OpClass 19 0.30% 0.30% # Class of executed instruction -system.cpu.op_class::IntAlu 4320 67.50% 67.80% # Class of executed instruction -system.cpu.op_class::IntMult 1 0.02% 67.81% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 67.81% # Class of executed instruction -system.cpu.op_class::FloatAdd 2 0.03% 67.84% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::MemRead 1190 18.59% 86.44% # Class of executed instruction -system.cpu.op_class::MemWrite 868 13.56% 100.00% # Class of executed instruction +system.cpu.op_class::IntAlu 4331 67.53% 67.83% # Class of executed instruction +system.cpu.op_class::IntMult 1 0.02% 67.85% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 67.85% # Class of executed instruction +system.cpu.op_class::FloatAdd 2 0.03% 67.88% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::MemRead 1192 18.59% 86.46% # Class of executed instruction +system.cpu.op_class::MemWrite 868 13.54% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 6400 # Class of executed instruction +system.cpu.op_class::total 6413 # Class of executed instruction system.ruby.clk_domain.clock 1 # Clock period in ticks system.ruby.outstanding_req_hist_seqr::bucket_size 1 system.ruby.outstanding_req_hist_seqr::max_bucket 9 -system.ruby.outstanding_req_hist_seqr::samples 8449 +system.ruby.outstanding_req_hist_seqr::samples 8464 system.ruby.outstanding_req_hist_seqr::mean 1 system.ruby.outstanding_req_hist_seqr::gmean 1 -system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 8449 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.outstanding_req_hist_seqr::total 8449 +system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 8464 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist_seqr::total 8464 system.ruby.latency_hist_seqr::bucket_size 64 system.ruby.latency_hist_seqr::max_bucket 639 -system.ruby.latency_hist_seqr::samples 8448 -system.ruby.latency_hist_seqr::mean 11.866241 -system.ruby.latency_hist_seqr::gmean 1.974485 -system.ruby.latency_hist_seqr::stdev 27.814086 -system.ruby.latency_hist_seqr | 7440 88.07% 88.07% | 991 11.73% 99.80% | 4 0.05% 99.85% | 1 0.01% 99.86% | 9 0.11% 99.96% | 3 0.04% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.latency_hist_seqr::total 8448 +system.ruby.latency_hist_seqr::samples 8463 +system.ruby.latency_hist_seqr::mean 11.865178 +system.ruby.latency_hist_seqr::gmean 1.973283 +system.ruby.latency_hist_seqr::stdev 27.863065 +system.ruby.latency_hist_seqr | 7453 88.07% 88.07% | 995 11.76% 99.82% | 2 0.02% 99.85% | 0 0.00% 99.85% | 9 0.11% 99.95% | 4 0.05% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.latency_hist_seqr::total 8463 system.ruby.hit_latency_hist_seqr::bucket_size 1 system.ruby.hit_latency_hist_seqr::max_bucket 9 -system.ruby.hit_latency_hist_seqr::samples 7027 +system.ruby.hit_latency_hist_seqr::samples 7041 system.ruby.hit_latency_hist_seqr::mean 1 system.ruby.hit_latency_hist_seqr::gmean 1 -system.ruby.hit_latency_hist_seqr | 0 0.00% 0.00% | 7027 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.hit_latency_hist_seqr::total 7027 +system.ruby.hit_latency_hist_seqr | 0 0.00% 0.00% | 7041 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.hit_latency_hist_seqr::total 7041 system.ruby.miss_latency_hist_seqr::bucket_size 64 system.ruby.miss_latency_hist_seqr::max_bucket 639 -system.ruby.miss_latency_hist_seqr::samples 1421 -system.ruby.miss_latency_hist_seqr::mean 65.600985 -system.ruby.miss_latency_hist_seqr::gmean 57.082853 -system.ruby.miss_latency_hist_seqr::stdev 33.588801 -system.ruby.miss_latency_hist_seqr | 413 29.06% 29.06% | 991 69.74% 98.80% | 4 0.28% 99.09% | 1 0.07% 99.16% | 9 0.63% 99.79% | 3 0.21% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.miss_latency_hist_seqr::total 1421 -system.ruby.l1_cntrl0.L1Dcache.demand_hits 1273 # Number of cache demand hits -system.ruby.l1_cntrl0.L1Dcache.demand_misses 775 # Number of cache demand misses -system.ruby.l1_cntrl0.L1Dcache.demand_accesses 2048 # Number of cache demand accesses -system.ruby.l1_cntrl0.L1Icache.demand_hits 5754 # Number of cache demand hits +system.ruby.miss_latency_hist_seqr::samples 1422 +system.ruby.miss_latency_hist_seqr::mean 65.663854 +system.ruby.miss_latency_hist_seqr::gmean 57.123275 +system.ruby.miss_latency_hist_seqr::stdev 33.791401 +system.ruby.miss_latency_hist_seqr | 412 28.97% 28.97% | 995 69.97% 98.95% | 2 0.14% 99.09% | 0 0.00% 99.09% | 9 0.63% 99.72% | 4 0.28% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.miss_latency_hist_seqr::total 1422 +system.ruby.l1_cntrl0.L1Dcache.demand_hits 1274 # Number of cache demand hits +system.ruby.l1_cntrl0.L1Dcache.demand_misses 776 # Number of cache demand misses +system.ruby.l1_cntrl0.L1Dcache.demand_accesses 2050 # Number of cache demand accesses +system.ruby.l1_cntrl0.L1Icache.demand_hits 5767 # Number of cache demand hits system.ruby.l1_cntrl0.L1Icache.demand_misses 646 # Number of cache demand misses -system.ruby.l1_cntrl0.L1Icache.demand_accesses 6400 # Number of cache demand accesses +system.ruby.l1_cntrl0.L1Icache.demand_accesses 6413 # Number of cache demand accesses system.ruby.l2_cntrl0.L2cache.demand_hits 239 # Number of cache demand hits -system.ruby.l2_cntrl0.L2cache.demand_misses 1182 # Number of cache demand misses -system.ruby.l2_cntrl0.L2cache.demand_accesses 1421 # Number of cache demand accesses +system.ruby.l2_cntrl0.L2cache.demand_misses 1183 # Number of cache demand misses +system.ruby.l2_cntrl0.L2cache.demand_accesses 1422 # Number of cache demand accesses system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.ruby.network.routers0.percent_links_utilized 6.936215 -system.ruby.network.routers0.msg_count.Request_Control::0 1421 -system.ruby.network.routers0.msg_count.Response_Data::2 1182 +system.ruby.network.routers0.percent_links_utilized 6.929545 +system.ruby.network.routers0.msg_count.Request_Control::0 1422 +system.ruby.network.routers0.msg_count.Response_Data::2 1183 system.ruby.network.routers0.msg_count.ResponseL2hit_Data::2 239 -system.ruby.network.routers0.msg_count.Writeback_Data::2 1308 -system.ruby.network.routers0.msg_count.Writeback_Control::0 2708 -system.ruby.network.routers0.msg_count.Unblock_Control::2 1467 -system.ruby.network.routers0.msg_bytes.Request_Control::0 11368 -system.ruby.network.routers0.msg_bytes.Response_Data::2 85104 +system.ruby.network.routers0.msg_count.Writeback_Data::2 1309 +system.ruby.network.routers0.msg_count.Writeback_Control::0 2710 +system.ruby.network.routers0.msg_count.Unblock_Control::2 1468 +system.ruby.network.routers0.msg_bytes.Request_Control::0 11376 +system.ruby.network.routers0.msg_bytes.Response_Data::2 85176 system.ruby.network.routers0.msg_bytes.ResponseL2hit_Data::2 17208 -system.ruby.network.routers0.msg_bytes.Writeback_Data::2 94176 -system.ruby.network.routers0.msg_bytes.Writeback_Control::0 21664 -system.ruby.network.routers0.msg_bytes.Unblock_Control::2 11736 -system.ruby.network.routers1.percent_links_utilized 10.417548 -system.ruby.network.routers1.msg_count.Request_Control::0 1421 -system.ruby.network.routers1.msg_count.Request_Control::1 1182 -system.ruby.network.routers1.msg_count.Response_Data::2 2364 +system.ruby.network.routers0.msg_bytes.Writeback_Data::2 94248 +system.ruby.network.routers0.msg_bytes.Writeback_Control::0 21680 +system.ruby.network.routers0.msg_bytes.Unblock_Control::2 11744 +system.ruby.network.routers1.percent_links_utilized 10.407520 +system.ruby.network.routers1.msg_count.Request_Control::0 1422 +system.ruby.network.routers1.msg_count.Request_Control::1 1183 +system.ruby.network.routers1.msg_count.Response_Data::2 2366 system.ruby.network.routers1.msg_count.ResponseL2hit_Data::2 239 -system.ruby.network.routers1.msg_count.Writeback_Data::2 1502 -system.ruby.network.routers1.msg_count.Writeback_Control::0 2708 +system.ruby.network.routers1.msg_count.Writeback_Data::2 1503 +system.ruby.network.routers1.msg_count.Writeback_Control::0 2710 system.ruby.network.routers1.msg_count.Writeback_Control::1 388 -system.ruby.network.routers1.msg_count.Unblock_Control::2 2649 -system.ruby.network.routers1.msg_bytes.Request_Control::0 11368 -system.ruby.network.routers1.msg_bytes.Request_Control::1 9456 -system.ruby.network.routers1.msg_bytes.Response_Data::2 170208 +system.ruby.network.routers1.msg_count.Unblock_Control::2 2651 +system.ruby.network.routers1.msg_bytes.Request_Control::0 11376 +system.ruby.network.routers1.msg_bytes.Request_Control::1 9464 +system.ruby.network.routers1.msg_bytes.Response_Data::2 170352 system.ruby.network.routers1.msg_bytes.ResponseL2hit_Data::2 17208 -system.ruby.network.routers1.msg_bytes.Writeback_Data::2 108144 -system.ruby.network.routers1.msg_bytes.Writeback_Control::0 21664 +system.ruby.network.routers1.msg_bytes.Writeback_Data::2 108216 +system.ruby.network.routers1.msg_bytes.Writeback_Control::0 21680 system.ruby.network.routers1.msg_bytes.Writeback_Control::1 3104 -system.ruby.network.routers1.msg_bytes.Unblock_Control::2 21192 -system.ruby.network.routers2.percent_links_utilized 3.481333 -system.ruby.network.routers2.msg_count.Request_Control::1 1182 -system.ruby.network.routers2.msg_count.Response_Data::2 1182 +system.ruby.network.routers1.msg_bytes.Unblock_Control::2 21208 +system.ruby.network.routers2.percent_links_utilized 3.477975 +system.ruby.network.routers2.msg_count.Request_Control::1 1183 +system.ruby.network.routers2.msg_count.Response_Data::2 1183 system.ruby.network.routers2.msg_count.Writeback_Data::2 194 system.ruby.network.routers2.msg_count.Writeback_Control::1 388 -system.ruby.network.routers2.msg_count.Unblock_Control::2 1182 -system.ruby.network.routers2.msg_bytes.Request_Control::1 9456 -system.ruby.network.routers2.msg_bytes.Response_Data::2 85104 +system.ruby.network.routers2.msg_count.Unblock_Control::2 1183 +system.ruby.network.routers2.msg_bytes.Request_Control::1 9464 +system.ruby.network.routers2.msg_bytes.Response_Data::2 85176 system.ruby.network.routers2.msg_bytes.Writeback_Data::2 13968 system.ruby.network.routers2.msg_bytes.Writeback_Control::1 3104 -system.ruby.network.routers2.msg_bytes.Unblock_Control::2 9456 -system.ruby.network.routers3.percent_links_utilized 6.945032 -system.ruby.network.routers3.msg_count.Request_Control::0 1421 -system.ruby.network.routers3.msg_count.Request_Control::1 1182 -system.ruby.network.routers3.msg_count.Response_Data::2 2364 +system.ruby.network.routers2.msg_bytes.Unblock_Control::2 9464 +system.ruby.network.routers3.percent_links_utilized 6.938347 +system.ruby.network.routers3.msg_count.Request_Control::0 1422 +system.ruby.network.routers3.msg_count.Request_Control::1 1183 +system.ruby.network.routers3.msg_count.Response_Data::2 2366 system.ruby.network.routers3.msg_count.ResponseL2hit_Data::2 239 -system.ruby.network.routers3.msg_count.Writeback_Data::2 1502 -system.ruby.network.routers3.msg_count.Writeback_Control::0 2708 +system.ruby.network.routers3.msg_count.Writeback_Data::2 1503 +system.ruby.network.routers3.msg_count.Writeback_Control::0 2710 system.ruby.network.routers3.msg_count.Writeback_Control::1 388 -system.ruby.network.routers3.msg_count.Unblock_Control::2 2649 -system.ruby.network.routers3.msg_bytes.Request_Control::0 11368 -system.ruby.network.routers3.msg_bytes.Request_Control::1 9456 -system.ruby.network.routers3.msg_bytes.Response_Data::2 170208 +system.ruby.network.routers3.msg_count.Unblock_Control::2 2651 +system.ruby.network.routers3.msg_bytes.Request_Control::0 11376 +system.ruby.network.routers3.msg_bytes.Request_Control::1 9464 +system.ruby.network.routers3.msg_bytes.Response_Data::2 170352 system.ruby.network.routers3.msg_bytes.ResponseL2hit_Data::2 17208 -system.ruby.network.routers3.msg_bytes.Writeback_Data::2 108144 -system.ruby.network.routers3.msg_bytes.Writeback_Control::0 21664 +system.ruby.network.routers3.msg_bytes.Writeback_Data::2 108216 +system.ruby.network.routers3.msg_bytes.Writeback_Control::0 21680 system.ruby.network.routers3.msg_bytes.Writeback_Control::1 3104 -system.ruby.network.routers3.msg_bytes.Unblock_Control::2 21192 -system.ruby.network.msg_count.Request_Control 7809 -system.ruby.network.msg_count.Response_Data 7092 +system.ruby.network.routers3.msg_bytes.Unblock_Control::2 21208 +system.ruby.network.msg_count.Request_Control 7815 +system.ruby.network.msg_count.Response_Data 7098 system.ruby.network.msg_count.ResponseL2hit_Data 717 -system.ruby.network.msg_count.Writeback_Data 4506 -system.ruby.network.msg_count.Writeback_Control 9288 -system.ruby.network.msg_count.Unblock_Control 7947 -system.ruby.network.msg_byte.Request_Control 62472 -system.ruby.network.msg_byte.Response_Data 510624 +system.ruby.network.msg_count.Writeback_Data 4509 +system.ruby.network.msg_count.Writeback_Control 9294 +system.ruby.network.msg_count.Unblock_Control 7953 +system.ruby.network.msg_byte.Request_Control 62520 +system.ruby.network.msg_byte.Response_Data 511056 system.ruby.network.msg_byte.ResponseL2hit_Data 51624 -system.ruby.network.msg_byte.Writeback_Data 324432 -system.ruby.network.msg_byte.Writeback_Control 74304 -system.ruby.network.msg_byte.Unblock_Control 63576 -system.ruby.network.routers0.throttle0.link_utilization 6.505879 -system.ruby.network.routers0.throttle0.msg_count.Response_Data::2 1182 +system.ruby.network.msg_byte.Writeback_Data 324648 +system.ruby.network.msg_byte.Writeback_Control 74352 +system.ruby.network.msg_byte.Unblock_Control 63624 +system.ruby.network.routers0.throttle0.link_utilization 6.499476 +system.ruby.network.routers0.throttle0.msg_count.Response_Data::2 1183 system.ruby.network.routers0.throttle0.msg_count.ResponseL2hit_Data::2 239 -system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::0 1354 -system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::2 85104 +system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::0 1355 +system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::2 85176 system.ruby.network.routers0.throttle0.msg_bytes.ResponseL2hit_Data::2 17208 -system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::0 10832 -system.ruby.network.routers0.throttle1.link_utilization 7.366552 -system.ruby.network.routers0.throttle1.msg_count.Request_Control::0 1421 -system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::2 1308 -system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::0 1354 -system.ruby.network.routers0.throttle1.msg_count.Unblock_Control::2 1467 -system.ruby.network.routers0.throttle1.msg_bytes.Request_Control::0 11368 -system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::2 94176 -system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::0 10832 -system.ruby.network.routers0.throttle1.msg_bytes.Unblock_Control::2 11736 -system.ruby.network.routers1.throttle0.link_utilization 12.349348 -system.ruby.network.routers1.throttle0.msg_count.Request_Control::0 1421 -system.ruby.network.routers1.throttle0.msg_count.Response_Data::2 1182 -system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::2 1308 -system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::0 1354 +system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::0 10840 +system.ruby.network.routers0.throttle1.link_utilization 7.359614 +system.ruby.network.routers0.throttle1.msg_count.Request_Control::0 1422 +system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::2 1309 +system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::0 1355 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-system.ruby.network.routers3.throttle1.msg_bytes.Unblock_Control::2 11736 -system.ruby.network.routers3.throttle2.link_utilization 1.979870 -system.ruby.network.routers3.throttle2.msg_count.Request_Control::1 1182 +system.ruby.network.routers3.throttle1.msg_bytes.Unblock_Control::2 11744 +system.ruby.network.routers3.throttle2.link_utilization 1.977443 +system.ruby.network.routers3.throttle2.msg_count.Request_Control::1 1183 system.ruby.network.routers3.throttle2.msg_count.Writeback_Data::2 194 system.ruby.network.routers3.throttle2.msg_count.Writeback_Control::1 194 -system.ruby.network.routers3.throttle2.msg_count.Unblock_Control::2 1182 -system.ruby.network.routers3.throttle2.msg_bytes.Request_Control::1 9456 +system.ruby.network.routers3.throttle2.msg_count.Unblock_Control::2 1183 +system.ruby.network.routers3.throttle2.msg_bytes.Request_Control::1 9464 system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Data::2 13968 system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Control::1 1552 -system.ruby.network.routers3.throttle2.msg_bytes.Unblock_Control::2 9456 -system.ruby.LD.latency_hist_seqr::bucket_size 64 -system.ruby.LD.latency_hist_seqr::max_bucket 639 -system.ruby.LD.latency_hist_seqr::samples 1183 -system.ruby.LD.latency_hist_seqr::mean 27.265427 -system.ruby.LD.latency_hist_seqr::gmean 5.733715 -system.ruby.LD.latency_hist_seqr::stdev 35.817674 -system.ruby.LD.latency_hist_seqr | 862 72.87% 72.87% | 317 26.80% 99.66% | 2 0.17% 99.83% | 1 0.08% 99.92% | 0 0.00% 99.92% | 1 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.latency_hist_seqr::total 1183 +system.ruby.network.routers3.throttle2.msg_bytes.Unblock_Control::2 9464 +system.ruby.LD.latency_hist_seqr::bucket_size 32 +system.ruby.LD.latency_hist_seqr::max_bucket 319 +system.ruby.LD.latency_hist_seqr::samples 1185 +system.ruby.LD.latency_hist_seqr::mean 27.428692 +system.ruby.LD.latency_hist_seqr::gmean 5.747000 +system.ruby.LD.latency_hist_seqr::stdev 36.091782 +system.ruby.LD.latency_hist_seqr | 775 65.40% 65.40% | 87 7.34% 72.74% | 279 23.54% 96.29% | 40 3.38% 99.66% | 1 0.08% 99.75% | 1 0.08% 99.83% | 0 0.00% 99.83% | 0 0.00% 99.83% | 1 0.08% 99.92% | 1 0.08% 100.00% +system.ruby.LD.latency_hist_seqr::total 1185 system.ruby.LD.hit_latency_hist_seqr::bucket_size 1 system.ruby.LD.hit_latency_hist_seqr::max_bucket 9 -system.ruby.LD.hit_latency_hist_seqr::samples 658 +system.ruby.LD.hit_latency_hist_seqr::samples 659 system.ruby.LD.hit_latency_hist_seqr::mean 1 system.ruby.LD.hit_latency_hist_seqr::gmean 1 -system.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 658 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.hit_latency_hist_seqr::total 658 -system.ruby.LD.miss_latency_hist_seqr::bucket_size 64 -system.ruby.LD.miss_latency_hist_seqr::max_bucket 639 -system.ruby.LD.miss_latency_hist_seqr::samples 525 -system.ruby.LD.miss_latency_hist_seqr::mean 60.184762 -system.ruby.LD.miss_latency_hist_seqr::gmean 51.169278 -system.ruby.LD.miss_latency_hist_seqr::stdev 30.689440 -system.ruby.LD.miss_latency_hist_seqr | 204 38.86% 38.86% | 317 60.38% 99.24% | 2 0.38% 99.62% | 1 0.19% 99.81% | 0 0.00% 99.81% | 1 0.19% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.miss_latency_hist_seqr::total 525 +system.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 659 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.hit_latency_hist_seqr::total 659 +system.ruby.LD.miss_latency_hist_seqr::bucket_size 32 +system.ruby.LD.miss_latency_hist_seqr::max_bucket 319 +system.ruby.LD.miss_latency_hist_seqr::samples 526 +system.ruby.LD.miss_latency_hist_seqr::mean 60.539924 +system.ruby.LD.miss_latency_hist_seqr::gmean 51.393520 +system.ruby.LD.miss_latency_hist_seqr::stdev 31.024435 +system.ruby.LD.miss_latency_hist_seqr | 116 22.05% 22.05% | 87 16.54% 38.59% | 279 53.04% 91.63% | 40 7.60% 99.24% | 1 0.19% 99.43% | 1 0.19% 99.62% | 0 0.00% 99.62% | 0 0.00% 99.62% | 1 0.19% 99.81% | 1 0.19% 100.00% +system.ruby.LD.miss_latency_hist_seqr::total 526 system.ruby.ST.latency_hist_seqr::bucket_size 64 system.ruby.ST.latency_hist_seqr::max_bucket 639 system.ruby.ST.latency_hist_seqr::samples 865 -system.ruby.ST.latency_hist_seqr::mean 17.593064 -system.ruby.ST.latency_hist_seqr::gmean 3.080574 -system.ruby.ST.latency_hist_seqr::stdev 34.156278 -system.ruby.ST.latency_hist_seqr | 753 87.05% 87.05% | 108 12.49% 99.54% | 0 0.00% 99.54% | 0 0.00% 99.54% | 2 0.23% 99.77% | 2 0.23% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.latency_hist_seqr::mean 17.057803 +system.ruby.ST.latency_hist_seqr::gmean 3.071194 +system.ruby.ST.latency_hist_seqr::stdev 31.094076 +system.ruby.ST.latency_hist_seqr | 753 87.05% 87.05% | 110 12.72% 99.77% | 0 0.00% 99.77% | 0 0.00% 99.77% | 1 0.12% 99.88% | 1 0.12% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ST.latency_hist_seqr::total 865 system.ruby.ST.hit_latency_hist_seqr::bucket_size 1 system.ruby.ST.hit_latency_hist_seqr::max_bucket 9 @@ -597,73 +596,73 @@ system.ruby.ST.hit_latency_hist_seqr::total 615 system.ruby.ST.miss_latency_hist_seqr::bucket_size 64 system.ruby.ST.miss_latency_hist_seqr::max_bucket 639 system.ruby.ST.miss_latency_hist_seqr::samples 250 -system.ruby.ST.miss_latency_hist_seqr::mean 58.412000 -system.ruby.ST.miss_latency_hist_seqr::gmean 49.053018 -system.ruby.ST.miss_latency_hist_seqr::stdev 41.173185 -system.ruby.ST.miss_latency_hist_seqr | 138 55.20% 55.20% | 108 43.20% 98.40% | 0 0.00% 98.40% | 0 0.00% 98.40% | 2 0.80% 99.20% | 2 0.80% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.miss_latency_hist_seqr::mean 56.560000 +system.ruby.ST.miss_latency_hist_seqr::gmean 48.538116 +system.ruby.ST.miss_latency_hist_seqr::stdev 33.930333 +system.ruby.ST.miss_latency_hist_seqr | 138 55.20% 55.20% | 110 44.00% 99.20% | 0 0.00% 99.20% | 0 0.00% 99.20% | 1 0.40% 99.60% | 1 0.40% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ST.miss_latency_hist_seqr::total 250 -system.ruby.IFETCH.latency_hist_seqr::bucket_size 32 -system.ruby.IFETCH.latency_hist_seqr::max_bucket 319 -system.ruby.IFETCH.latency_hist_seqr::samples 6400 -system.ruby.IFETCH.latency_hist_seqr::mean 8.245781 -system.ruby.IFETCH.latency_hist_seqr::gmean 1.526741 -system.ruby.IFETCH.latency_hist_seqr::stdev 23.776931 -system.ruby.IFETCH.latency_hist_seqr | 5825 91.02% 91.02% | 0 0.00% 91.02% | 525 8.20% 99.22% | 41 0.64% 99.86% | 2 0.03% 99.89% | 0 0.00% 99.89% | 0 0.00% 99.89% | 0 0.00% 99.89% | 2 0.03% 99.92% | 5 0.08% 100.00% -system.ruby.IFETCH.latency_hist_seqr::total 6400 +system.ruby.IFETCH.latency_hist_seqr::bucket_size 64 +system.ruby.IFETCH.latency_hist_seqr::max_bucket 639 +system.ruby.IFETCH.latency_hist_seqr::samples 6413 +system.ruby.IFETCH.latency_hist_seqr::mean 8.288944 +system.ruby.IFETCH.latency_hist_seqr::gmean 1.525778 +system.ruby.IFETCH.latency_hist_seqr::stdev 24.342417 +system.ruby.IFETCH.latency_hist_seqr | 5838 91.03% 91.03% | 566 8.83% 99.86% | 0 0.00% 99.86% | 0 0.00% 99.86% | 6 0.09% 99.95% | 3 0.05% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.latency_hist_seqr::total 6413 system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 1 system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 9 -system.ruby.IFETCH.hit_latency_hist_seqr::samples 5754 +system.ruby.IFETCH.hit_latency_hist_seqr::samples 5767 system.ruby.IFETCH.hit_latency_hist_seqr::mean 1 system.ruby.IFETCH.hit_latency_hist_seqr::gmean 1 -system.ruby.IFETCH.hit_latency_hist_seqr | 0 0.00% 0.00% | 5754 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.hit_latency_hist_seqr::total 5754 -system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 32 -system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 319 +system.ruby.IFETCH.hit_latency_hist_seqr | 0 0.00% 0.00% | 5767 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.hit_latency_hist_seqr::total 5767 +system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 64 +system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 639 system.ruby.IFETCH.miss_latency_hist_seqr::samples 646 -system.ruby.IFETCH.miss_latency_hist_seqr::mean 72.784830 -system.ruby.IFETCH.miss_latency_hist_seqr::gmean 66.158480 -system.ruby.IFETCH.miss_latency_hist_seqr::stdev 31.122591 -system.ruby.IFETCH.miss_latency_hist_seqr | 71 10.99% 10.99% | 0 0.00% 10.99% | 525 81.27% 92.26% | 41 6.35% 98.61% | 2 0.31% 98.92% | 0 0.00% 98.92% | 0 0.00% 98.92% | 0 0.00% 98.92% | 2 0.31% 99.23% | 5 0.77% 100.00% +system.ruby.IFETCH.miss_latency_hist_seqr::mean 73.359133 +system.ruby.IFETCH.miss_latency_hist_seqr::gmean 66.307554 +system.ruby.IFETCH.miss_latency_hist_seqr::stdev 34.276818 +system.ruby.IFETCH.miss_latency_hist_seqr | 71 10.99% 10.99% | 566 87.62% 98.61% | 0 0.00% 98.61% | 0 0.00% 98.61% | 6 0.93% 99.54% | 3 0.46% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.miss_latency_hist_seqr::total 646 system.ruby.Directory_Controller.GETX 198 0.00% 0.00% -system.ruby.Directory_Controller.GETS 984 0.00% 0.00% +system.ruby.Directory_Controller.GETS 985 0.00% 0.00% system.ruby.Directory_Controller.PUTX 194 0.00% 0.00% system.ruby.Directory_Controller.Unblock 466 0.00% 0.00% -system.ruby.Directory_Controller.Last_Unblock 517 0.00% 0.00% +system.ruby.Directory_Controller.Last_Unblock 518 0.00% 0.00% system.ruby.Directory_Controller.Exclusive_Unblock 198 0.00% 0.00% system.ruby.Directory_Controller.Dirty_Writeback 194 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 1182 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 1183 0.00% 0.00% system.ruby.Directory_Controller.Memory_Ack 194 0.00% 0.00% system.ruby.Directory_Controller.I.GETX 111 0.00% 0.00% system.ruby.Directory_Controller.I.GETS 466 0.00% 0.00% system.ruby.Directory_Controller.I.Memory_Ack 194 0.00% 0.00% system.ruby.Directory_Controller.S.GETX 87 0.00% 0.00% -system.ruby.Directory_Controller.S.GETS 518 0.00% 0.00% +system.ruby.Directory_Controller.S.GETS 519 0.00% 0.00% system.ruby.Directory_Controller.M.PUTX 194 0.00% 0.00% system.ruby.Directory_Controller.IS.Unblock 466 0.00% 0.00% system.ruby.Directory_Controller.IS.Memory_Data 466 0.00% 0.00% -system.ruby.Directory_Controller.SS.Last_Unblock 517 0.00% 0.00% -system.ruby.Directory_Controller.SS.Memory_Data 518 0.00% 0.00% +system.ruby.Directory_Controller.SS.Last_Unblock 518 0.00% 0.00% +system.ruby.Directory_Controller.SS.Memory_Data 519 0.00% 0.00% system.ruby.Directory_Controller.MM.Exclusive_Unblock 198 0.00% 0.00% system.ruby.Directory_Controller.MM.Memory_Data 198 0.00% 0.00% system.ruby.Directory_Controller.MI.Dirty_Writeback 194 0.00% 0.00% -system.ruby.L1Cache_Controller.Load 1183 0.00% 0.00% -system.ruby.L1Cache_Controller.Ifetch 6400 0.00% 0.00% +system.ruby.L1Cache_Controller.Load 1185 0.00% 0.00% +system.ruby.L1Cache_Controller.Ifetch 6413 0.00% 0.00% system.ruby.L1Cache_Controller.Store 865 0.00% 0.00% -system.ruby.L1Cache_Controller.L1_Replacement 1368 0.00% 0.00% -system.ruby.L1Cache_Controller.Data 1125 0.00% 0.00% +system.ruby.L1Cache_Controller.L1_Replacement 1369 0.00% 0.00% +system.ruby.L1Cache_Controller.Data 1126 0.00% 0.00% system.ruby.L1Cache_Controller.Exclusive_Data 296 0.00% 0.00% system.ruby.L1Cache_Controller.Writeback_Ack 46 0.00% 0.00% -system.ruby.L1Cache_Controller.Writeback_Ack_Data 1308 0.00% 0.00% +system.ruby.L1Cache_Controller.Writeback_Ack_Data 1309 0.00% 0.00% system.ruby.L1Cache_Controller.All_acks 250 0.00% 0.00% system.ruby.L1Cache_Controller.Use_Timeout 296 0.00% 0.00% -system.ruby.L1Cache_Controller.I.Load 525 0.00% 0.00% +system.ruby.L1Cache_Controller.I.Load 526 0.00% 0.00% system.ruby.L1Cache_Controller.I.Ifetch 646 0.00% 0.00% system.ruby.L1Cache_Controller.I.Store 191 0.00% 0.00% -system.ruby.L1Cache_Controller.S.Load 299 0.00% 0.00% -system.ruby.L1Cache_Controller.S.Ifetch 5754 0.00% 0.00% +system.ruby.L1Cache_Controller.S.Load 300 0.00% 0.00% +system.ruby.L1Cache_Controller.S.Ifetch 5767 0.00% 0.00% system.ruby.L1Cache_Controller.S.Store 59 0.00% 0.00% -system.ruby.L1Cache_Controller.S.L1_Replacement 1059 0.00% 0.00% +system.ruby.L1Cache_Controller.S.L1_Replacement 1060 0.00% 0.00% system.ruby.L1Cache_Controller.M.Load 79 0.00% 0.00% system.ruby.L1Cache_Controller.M.Store 18 0.00% 0.00% system.ruby.L1Cache_Controller.M.L1_Replacement 27 0.00% 0.00% @@ -680,42 +679,42 @@ system.ruby.L1Cache_Controller.MM_W.Use_Timeout 251 0.00% 0.0 system.ruby.L1Cache_Controller.IM.Exclusive_Data 191 0.00% 0.00% system.ruby.L1Cache_Controller.SM.Exclusive_Data 59 0.00% 0.00% system.ruby.L1Cache_Controller.OM.All_acks 250 0.00% 0.00% -system.ruby.L1Cache_Controller.IS.Data 1125 0.00% 0.00% +system.ruby.L1Cache_Controller.IS.Data 1126 0.00% 0.00% system.ruby.L1Cache_Controller.IS.Exclusive_Data 46 0.00% 0.00% system.ruby.L1Cache_Controller.SI.Writeback_Ack 46 0.00% 0.00% -system.ruby.L1Cache_Controller.SI.Writeback_Ack_Data 1013 0.00% 0.00% +system.ruby.L1Cache_Controller.SI.Writeback_Ack_Data 1014 0.00% 0.00% system.ruby.L1Cache_Controller.MI.Writeback_Ack_Data 295 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_GETS 1171 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_GETS 1172 0.00% 0.00% system.ruby.L2Cache_Controller.L1_GETX 250 0.00% 0.00% system.ruby.L2Cache_Controller.L1_PUTX 295 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_PUTS_only 1059 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_PUTS_only 1060 0.00% 0.00% system.ruby.L2Cache_Controller.All_Acks 198 0.00% 0.00% -system.ruby.L2Cache_Controller.Data 1182 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_WBCLEANDATA 1013 0.00% 0.00% +system.ruby.L2Cache_Controller.Data 1183 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_WBCLEANDATA 1014 0.00% 0.00% system.ruby.L2Cache_Controller.L1_WBDIRTYDATA 295 0.00% 0.00% system.ruby.L2Cache_Controller.Writeback_Ack 194 0.00% 0.00% -system.ruby.L2Cache_Controller.Unblock 1171 0.00% 0.00% +system.ruby.L2Cache_Controller.Unblock 1172 0.00% 0.00% system.ruby.L2Cache_Controller.Exclusive_Unblock 296 0.00% 0.00% -system.ruby.L2Cache_Controller.L2_Replacement 1193 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.L1_GETS 984 0.00% 0.00% +system.ruby.L2Cache_Controller.L2_Replacement 1194 0.00% 0.00% +system.ruby.L2Cache_Controller.NP.L1_GETS 985 0.00% 0.00% system.ruby.L2Cache_Controller.NP.L1_GETX 132 0.00% 0.00% system.ruby.L2Cache_Controller.ILS.L1_GETX 57 0.00% 0.00% -system.ruby.L2Cache_Controller.ILS.L1_PUTS_only 1013 0.00% 0.00% +system.ruby.L2Cache_Controller.ILS.L1_PUTS_only 1014 0.00% 0.00% system.ruby.L2Cache_Controller.ILX.L1_PUTX 295 0.00% 0.00% system.ruby.L2Cache_Controller.S.L1_GETS 141 0.00% 0.00% system.ruby.L2Cache_Controller.S.L1_GETX 7 0.00% 0.00% -system.ruby.L2Cache_Controller.S.L2_Replacement 906 0.00% 0.00% +system.ruby.L2Cache_Controller.S.L2_Replacement 907 0.00% 0.00% system.ruby.L2Cache_Controller.SLS.L1_GETX 2 0.00% 0.00% system.ruby.L2Cache_Controller.SLS.L1_PUTS_only 46 0.00% 0.00% system.ruby.L2Cache_Controller.SLS.L2_Replacement 93 0.00% 0.00% system.ruby.L2Cache_Controller.M.L1_GETS 46 0.00% 0.00% system.ruby.L2Cache_Controller.M.L1_GETX 52 0.00% 0.00% system.ruby.L2Cache_Controller.M.L2_Replacement 194 0.00% 0.00% -system.ruby.L2Cache_Controller.IW.L1_WBCLEANDATA 1013 0.00% 0.00% +system.ruby.L2Cache_Controller.IW.L1_WBCLEANDATA 1014 0.00% 0.00% system.ruby.L2Cache_Controller.SW.Unblock 46 0.00% 0.00% system.ruby.L2Cache_Controller.ILXW.L1_WBDIRTYDATA 295 0.00% 0.00% -system.ruby.L2Cache_Controller.IGS.Data 984 0.00% 0.00% -system.ruby.L2Cache_Controller.IGS.Unblock 984 0.00% 0.00% +system.ruby.L2Cache_Controller.IGS.Data 985 0.00% 0.00% +system.ruby.L2Cache_Controller.IGS.Unblock 985 0.00% 0.00% system.ruby.L2Cache_Controller.IGM.Data 139 0.00% 0.00% system.ruby.L2Cache_Controller.IGMLS.Data 59 0.00% 0.00% system.ruby.L2Cache_Controller.IGMO.All_Acks 198 0.00% 0.00% diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini index 6857839bd..f83b6e49b 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini @@ -120,7 +120,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello +executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin kvmInSE=false diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout index a72f8ac98..f535b9682 100755 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout @@ -1,10 +1,12 @@ +Redirecting stdout to build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout +Redirecting stderr to build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 21 2016 14:12:23 -gem5 started Jan 21 2016 14:12:59 -gem5 executing on zizzer, pid 55399 -command line: build/ALPHA_MOESI_CMP_token/gem5.opt -d build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token +gem5 compiled Mar 14 2016 22:02:54 +gem5 started Mar 14 2016 22:04:07 +gem5 executing on phenom, pid 29513 +command line: build/ALPHA_MOESI_CMP_token/gem5.opt -d build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt index d6192ccc7..5e0571904 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt @@ -4,37 +4,37 @@ sim_seconds 0.000108 # Nu sim_ticks 108253 # Number of ticks simulated final_tick 108253 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 33873 # Simulator instruction rate (inst/s) -host_op_rate 33870 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 573730 # Simulator tick rate (ticks/s) -host_mem_usage 391892 # Number of bytes of host memory used -host_seconds 0.19 # Real time elapsed on the host -sim_insts 6390 # Number of instructions simulated -sim_ops 6390 # Number of ops (including micro ops) simulated +host_inst_rate 39556 # Simulator instruction rate (inst/s) +host_op_rate 39552 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 668635 # Simulator tick rate (ticks/s) +host_mem_usage 388512 # Number of bytes of host memory used +host_seconds 0.16 # Real time elapsed on the host +sim_insts 6403 # Number of instructions simulated +sim_ops 6403 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks -system.mem_ctrls.bytes_read::ruby.dir_cntrl0 75392 # Number of bytes read from this memory -system.mem_ctrls.bytes_read::total 75392 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::ruby.dir_cntrl0 75456 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 75456 # Number of bytes read from this memory system.mem_ctrls.bytes_written::ruby.dir_cntrl0 14656 # Number of bytes written to this memory system.mem_ctrls.bytes_written::total 14656 # Number of bytes written to this memory -system.mem_ctrls.num_reads::ruby.dir_cntrl0 1178 # Number of read requests responded to by this memory -system.mem_ctrls.num_reads::total 1178 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::ruby.dir_cntrl0 1179 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 1179 # Number of read requests responded to by this memory system.mem_ctrls.num_writes::ruby.dir_cntrl0 229 # Number of write requests responded to by this memory system.mem_ctrls.num_writes::total 229 # Number of write requests responded to by this memory -system.mem_ctrls.bw_read::ruby.dir_cntrl0 696442593 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_read::total 696442593 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::ruby.dir_cntrl0 697033800 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 697033800 # Total read bandwidth from this memory (bytes/s) system.mem_ctrls.bw_write::ruby.dir_cntrl0 135386548 # Write bandwidth from this memory (bytes/s) system.mem_ctrls.bw_write::total 135386548 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_total::ruby.dir_cntrl0 831829141 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.bw_total::total 831829141 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.readReqs 1178 # Number of read requests accepted +system.mem_ctrls.bw_total::ruby.dir_cntrl0 832420349 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 832420349 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.readReqs 1179 # Number of read requests accepted system.mem_ctrls.writeReqs 229 # Number of write requests accepted -system.mem_ctrls.readBursts 1178 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.readBursts 1179 # Number of DRAM read bursts, including those serviced by the write queue system.mem_ctrls.writeBursts 229 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrls.bytesReadDRAM 65024 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadDRAM 65088 # Total number of bytes read from DRAM system.mem_ctrls.bytesReadWrQ 10368 # Total number of bytes read from write queue system.mem_ctrls.bytesWritten 6144 # Total number of bytes written to DRAM -system.mem_ctrls.bytesReadSys 75392 # Total read bytes from the system interface side +system.mem_ctrls.bytesReadSys 75456 # Total read bytes from the system interface side system.mem_ctrls.bytesWrittenSys 14656 # Total written bytes from the system interface side system.mem_ctrls.servicedByWrQ 162 # Number of DRAM read bursts serviced by the write queue system.mem_ctrls.mergedWrBursts 112 # Number of DRAM write bursts merged with an existing one @@ -54,7 +54,7 @@ system.mem_ctrls.perBankRdBursts::11 53 # Pe system.mem_ctrls.perBankRdBursts::12 22 # Per bank write bursts system.mem_ctrls.perBankRdBursts::13 361 # Per bank write bursts system.mem_ctrls.perBankRdBursts::14 61 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::15 44 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::15 45 # Per bank write bursts system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts @@ -80,7 +80,7 @@ system.mem_ctrls.readPktSize::2 0 # Re system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::6 1178 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 1179 # Read request sizes (log2) system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) @@ -88,7 +88,7 @@ system.mem_ctrls.writePktSize::3 0 # Wr system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::6 229 # Write request sizes (log2) -system.mem_ctrls.rdQLenPdf::0 1016 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::0 1017 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see @@ -185,9 +185,9 @@ system.mem_ctrls.wrQLenPdf::61 0 # Wh system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see system.mem_ctrls.bytesPerActivate::samples 203 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::mean 338.600985 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::gmean 206.377683 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::stdev 325.274619 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 338.916256 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 206.604664 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 325.225174 # Bytes accessed per row activation system.mem_ctrls.bytesPerActivate::0-127 65 32.02% 32.02% # Bytes accessed per row activation system.mem_ctrls.bytesPerActivate::128-255 46 22.66% 54.68% # Bytes accessed per row activation system.mem_ctrls.bytesPerActivate::256-383 21 10.34% 65.02% # Bytes accessed per row activation @@ -199,9 +199,9 @@ system.mem_ctrls.bytesPerActivate::896-1023 4 1.97% 89.66% # system.mem_ctrls.bytesPerActivate::1024-1151 21 10.34% 100.00% # Bytes accessed per row activation system.mem_ctrls.bytesPerActivate::total 203 # Bytes accessed per row activation system.mem_ctrls.rdPerTurnAround::samples 6 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::mean 156.333333 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::gmean 116.994790 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::stdev 90.254455 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::mean 156.500000 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::gmean 117.084065 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::stdev 90.391924 # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::16-31 1 16.67% 16.67% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::80-95 1 16.67% 33.33% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::160-175 1 16.67% 50.00% # Reads before turning the bus around for writes @@ -214,77 +214,77 @@ system.mem_ctrls.wrPerTurnAround::mean 16 # Wr system.mem_ctrls.wrPerTurnAround::gmean 16.000000 # Writes before turning the bus around for reads system.mem_ctrls.wrPerTurnAround::16 6 100.00% 100.00% # Writes before turning the bus around for reads system.mem_ctrls.wrPerTurnAround::total 6 # Writes before turning the bus around for reads -system.mem_ctrls.totQLat 7316 # Total ticks spent queuing -system.mem_ctrls.totMemAccLat 26620 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrls.totBusLat 5080 # Total ticks spent in databus transfers -system.mem_ctrls.avgQLat 7.20 # Average queueing delay per DRAM burst +system.mem_ctrls.totQLat 7213 # Total ticks spent queuing +system.mem_ctrls.totMemAccLat 26536 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.totBusLat 5085 # Total ticks spent in databus transfers +system.mem_ctrls.avgQLat 7.09 # Average queueing delay per DRAM burst system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst -system.mem_ctrls.avgMemAccLat 26.20 # Average memory access latency per DRAM burst -system.mem_ctrls.avgRdBW 600.67 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgMemAccLat 26.09 # Average memory access latency per DRAM burst +system.mem_ctrls.avgRdBW 601.26 # Average DRAM read bandwidth in MiByte/s system.mem_ctrls.avgWrBW 56.76 # Average achieved write bandwidth in MiByte/s -system.mem_ctrls.avgRdBWSys 696.44 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 697.03 # Average system read bandwidth in MiByte/s system.mem_ctrls.avgWrBWSys 135.39 # Average system write bandwidth in MiByte/s system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.mem_ctrls.busUtil 5.14 # Data bus utilization in percentage -system.mem_ctrls.busUtilRead 4.69 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilRead 4.70 # Data bus utilization in percentage for reads system.mem_ctrls.busUtilWrite 0.44 # Data bus utilization in percentage for writes system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing system.mem_ctrls.avgWrQLen 23.01 # Average write queue length when enqueuing -system.mem_ctrls.readRowHits 815 # Number of row buffer hits during reads +system.mem_ctrls.readRowHits 816 # Number of row buffer hits during reads system.mem_ctrls.writeRowHits 88 # Number of row buffer hits during writes -system.mem_ctrls.readRowHitRate 80.22 # Row buffer hit rate for reads +system.mem_ctrls.readRowHitRate 80.24 # Row buffer hit rate for reads system.mem_ctrls.writeRowHitRate 75.21 # Row buffer hit rate for writes -system.mem_ctrls.avgGap 76.88 # Average gap between requests -system.mem_ctrls.pageHitRate 79.70 # Row buffer hit rate, read and write combined +system.mem_ctrls.avgGap 76.83 # Average gap between requests +system.mem_ctrls.pageHitRate 79.72 # Row buffer hit rate, read and write combined system.mem_ctrls_0.actEnergy 521640 # Energy for activate commands per rank (pJ) system.mem_ctrls_0.preEnergy 289800 # Energy for precharge commands per rank (pJ) system.mem_ctrls_0.readEnergy 5104320 # Energy for read commands per rank (pJ) system.mem_ctrls_0.writeEnergy 311040 # Energy for write commands per rank (pJ) system.mem_ctrls_0.refreshEnergy 6611280 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_0.actBackEnergy 57834936 # Energy for active background per rank (pJ) -system.mem_ctrls_0.preBackEnergy 10154400 # Energy for precharge background per rank (pJ) -system.mem_ctrls_0.totalEnergy 80827416 # Total energy per rank (pJ) -system.mem_ctrls_0.averagePower 796.501862 # Core power per rank (mW) -system.mem_ctrls_0.memoryStateTime::IDLE 21697 # Time in different power states +system.mem_ctrls_0.actBackEnergy 57840408 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 10149600 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.totalEnergy 80828088 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 796.508485 # Core power per rank (mW) +system.mem_ctrls_0.memoryStateTime::IDLE 21689 # Time in different power states system.mem_ctrls_0.memoryStateTime::REF 3380 # Time in different power states system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT 81524 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 81532 # Time in different power states system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.mem_ctrls_1.actEnergy 945000 # Energy for activate commands per rank (pJ) system.mem_ctrls_1.preEnergy 525000 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_1.readEnergy 6751680 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.readEnergy 6764160 # Energy for read commands per rank (pJ) system.mem_ctrls_1.writeEnergy 684288 # Energy for write commands per rank (pJ) system.mem_ctrls_1.refreshEnergy 6611280 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_1.actBackEnergy 67458132 # Energy for active background per rank (pJ) -system.mem_ctrls_1.preBackEnergy 1721400 # Energy for precharge background per rank (pJ) -system.mem_ctrls_1.totalEnergy 84696780 # Total energy per rank (pJ) -system.mem_ctrls_1.averagePower 834.516809 # Core power per rank (mW) -system.mem_ctrls_1.memoryStateTime::IDLE 2421 # Time in different power states +system.mem_ctrls_1.actBackEnergy 67474548 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 1707000 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.totalEnergy 84711276 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 834.659638 # Core power per rank (mW) +system.mem_ctrls_1.memoryStateTime::IDLE 2397 # Time in different power states system.mem_ctrls_1.memoryStateTime::REF 3380 # Time in different power states system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT 95705 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 95729 # Time in different power states system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.clk_domain.clock 1 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 1183 # DTB read hits +system.cpu.dtb.read_hits 1185 # DTB read hits system.cpu.dtb.read_misses 7 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 1190 # DTB read accesses +system.cpu.dtb.read_accesses 1192 # DTB read accesses system.cpu.dtb.write_hits 865 # DTB write hits system.cpu.dtb.write_misses 3 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations system.cpu.dtb.write_accesses 868 # DTB write accesses -system.cpu.dtb.data_hits 2048 # DTB hits +system.cpu.dtb.data_hits 2050 # DTB hits system.cpu.dtb.data_misses 10 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 2058 # DTB accesses -system.cpu.itb.fetch_hits 6401 # ITB hits +system.cpu.dtb.data_accesses 2060 # DTB accesses +system.cpu.itb.fetch_hits 6414 # ITB hits system.cpu.itb.fetch_misses 17 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 6418 # ITB accesses +system.cpu.itb.fetch_accesses 6431 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -301,338 +301,338 @@ system.cpu.workload.num_syscalls 17 # Nu system.cpu.numCycles 108253 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 6390 # Number of instructions committed -system.cpu.committedOps 6390 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 6317 # Number of integer alu accesses +system.cpu.committedInsts 6403 # Number of instructions committed +system.cpu.committedOps 6403 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 6329 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses system.cpu.num_func_calls 251 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 749 # number of instructions that are conditional controls -system.cpu.num_int_insts 6317 # number of integer instructions +system.cpu.num_conditional_control_insts 754 # number of instructions that are conditional controls +system.cpu.num_int_insts 6329 # number of integer instructions system.cpu.num_fp_insts 10 # number of float instructions -system.cpu.num_int_register_reads 8285 # number of times the integer registers were read -system.cpu.num_int_register_writes 4568 # number of times the integer registers were written +system.cpu.num_int_register_reads 8297 # number of times the integer registers were read +system.cpu.num_int_register_writes 4575 # number of times the integer registers were written system.cpu.num_fp_register_reads 8 # number of times the floating registers were read system.cpu.num_fp_register_writes 2 # number of times the floating registers were written -system.cpu.num_mem_refs 2058 # number of memory refs -system.cpu.num_load_insts 1190 # Number of load instructions +system.cpu.num_mem_refs 2060 # number of memory refs +system.cpu.num_load_insts 1192 # Number of load instructions system.cpu.num_store_insts 868 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_busy_cycles 108253 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 1050 # Number of branches fetched +system.cpu.Branches 1056 # Number of branches fetched system.cpu.op_class::No_OpClass 19 0.30% 0.30% # Class of executed instruction -system.cpu.op_class::IntAlu 4320 67.50% 67.80% # Class of executed instruction -system.cpu.op_class::IntMult 1 0.02% 67.81% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 67.81% # Class of executed instruction -system.cpu.op_class::FloatAdd 2 0.03% 67.84% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::MemRead 1190 18.59% 86.44% # Class of executed instruction -system.cpu.op_class::MemWrite 868 13.56% 100.00% # Class of executed instruction +system.cpu.op_class::IntAlu 4331 67.53% 67.83% # Class of executed instruction +system.cpu.op_class::IntMult 1 0.02% 67.85% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 67.85% # Class of executed instruction +system.cpu.op_class::FloatAdd 2 0.03% 67.88% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::MemRead 1192 18.59% 86.46% # Class of executed instruction +system.cpu.op_class::MemWrite 868 13.54% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 6400 # Class of executed instruction +system.cpu.op_class::total 6413 # Class of executed instruction system.ruby.clk_domain.clock 1 # Clock period in ticks system.ruby.outstanding_req_hist_seqr::bucket_size 1 system.ruby.outstanding_req_hist_seqr::max_bucket 9 -system.ruby.outstanding_req_hist_seqr::samples 8449 +system.ruby.outstanding_req_hist_seqr::samples 8464 system.ruby.outstanding_req_hist_seqr::mean 1 system.ruby.outstanding_req_hist_seqr::gmean 1 -system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 8449 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.outstanding_req_hist_seqr::total 8449 +system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 8464 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist_seqr::total 8464 system.ruby.latency_hist_seqr::bucket_size 64 system.ruby.latency_hist_seqr::max_bucket 639 -system.ruby.latency_hist_seqr::samples 8448 -system.ruby.latency_hist_seqr::mean 11.814039 -system.ruby.latency_hist_seqr::gmean 1.958059 -system.ruby.latency_hist_seqr::stdev 27.675120 -system.ruby.latency_hist_seqr | 7432 87.97% 87.97% | 995 11.78% 99.75% | 8 0.09% 99.85% | 3 0.04% 99.88% | 6 0.07% 99.95% | 4 0.05% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.latency_hist_seqr::total 8448 +system.ruby.latency_hist_seqr::samples 8463 +system.ruby.latency_hist_seqr::mean 11.791327 +system.ruby.latency_hist_seqr::gmean 1.956562 +system.ruby.latency_hist_seqr::stdev 27.556143 +system.ruby.latency_hist_seqr | 7446 87.98% 87.98% | 996 11.77% 99.75% | 8 0.09% 99.85% | 4 0.05% 99.89% | 5 0.06% 99.95% | 4 0.05% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.latency_hist_seqr::total 8463 system.ruby.hit_latency_hist_seqr::bucket_size 8 system.ruby.hit_latency_hist_seqr::max_bucket 79 -system.ruby.hit_latency_hist_seqr::samples 7270 -system.ruby.hit_latency_hist_seqr::mean 1.637552 -system.ruby.hit_latency_hist_seqr::gmean 1.092853 -system.ruby.hit_latency_hist_seqr::stdev 3.762080 -system.ruby.hit_latency_hist_seqr | 7066 97.19% 97.19% | 0 0.00% 97.19% | 19 0.26% 97.46% | 184 2.53% 99.99% | 0 0.00% 99.99% | 1 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.hit_latency_hist_seqr::total 7270 +system.ruby.hit_latency_hist_seqr::samples 7284 +system.ruby.hit_latency_hist_seqr::mean 1.635502 +system.ruby.hit_latency_hist_seqr::gmean 1.092626 +system.ruby.hit_latency_hist_seqr::stdev 3.754063 +system.ruby.hit_latency_hist_seqr | 7080 97.20% 97.20% | 0 0.00% 97.20% | 21 0.29% 97.49% | 182 2.50% 99.99% | 0 0.00% 99.99% | 1 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.hit_latency_hist_seqr::total 7284 system.ruby.miss_latency_hist_seqr::bucket_size 64 system.ruby.miss_latency_hist_seqr::max_bucket 639 -system.ruby.miss_latency_hist_seqr::samples 1178 -system.ruby.miss_latency_hist_seqr::mean 74.617997 -system.ruby.miss_latency_hist_seqr::gmean 71.587772 -system.ruby.miss_latency_hist_seqr::stdev 28.670099 -system.ruby.miss_latency_hist_seqr | 162 13.75% 13.75% | 995 84.47% 98.22% | 8 0.68% 98.90% | 3 0.25% 99.15% | 6 0.51% 99.66% | 4 0.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.miss_latency_hist_seqr::total 1178 -system.ruby.Directory.incomplete_times_seqr 1177 -system.ruby.l1_cntrl0.L1Dcache.demand_hits 1312 # Number of cache demand hits -system.ruby.l1_cntrl0.L1Dcache.demand_misses 736 # Number of cache demand misses -system.ruby.l1_cntrl0.L1Dcache.demand_accesses 2048 # Number of cache demand accesses -system.ruby.l1_cntrl0.L1Icache.demand_hits 5754 # Number of cache demand hits +system.ruby.miss_latency_hist_seqr::samples 1179 +system.ruby.miss_latency_hist_seqr::mean 74.535199 +system.ruby.miss_latency_hist_seqr::gmean 71.564149 +system.ruby.miss_latency_hist_seqr::stdev 28.099799 +system.ruby.miss_latency_hist_seqr | 162 13.74% 13.74% | 996 84.48% 98.22% | 8 0.68% 98.90% | 4 0.34% 99.24% | 5 0.42% 99.66% | 4 0.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.miss_latency_hist_seqr::total 1179 +system.ruby.Directory.incomplete_times_seqr 1178 +system.ruby.l1_cntrl0.L1Dcache.demand_hits 1313 # Number of cache demand hits +system.ruby.l1_cntrl0.L1Dcache.demand_misses 737 # Number of cache demand misses +system.ruby.l1_cntrl0.L1Dcache.demand_accesses 2050 # Number of cache demand accesses +system.ruby.l1_cntrl0.L1Icache.demand_hits 5767 # Number of cache demand hits system.ruby.l1_cntrl0.L1Icache.demand_misses 646 # Number of cache demand misses -system.ruby.l1_cntrl0.L1Icache.demand_accesses 6400 # Number of cache demand accesses +system.ruby.l1_cntrl0.L1Icache.demand_accesses 6413 # Number of cache demand accesses system.ruby.l2_cntrl0.L2cache.demand_hits 187 # Number of cache demand hits -system.ruby.l2_cntrl0.L2cache.demand_misses 1195 # Number of cache demand misses -system.ruby.l2_cntrl0.L2cache.demand_accesses 1382 # Number of cache demand accesses +system.ruby.l2_cntrl0.L2cache.demand_misses 1196 # Number of cache demand misses +system.ruby.l2_cntrl0.L2cache.demand_accesses 1383 # Number of cache demand accesses system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.ruby.network.routers0.percent_links_utilized 6.018078 -system.ruby.network.routers0.msg_count.Request_Control::1 1382 -system.ruby.network.routers0.msg_count.Response_Data::4 1178 +system.ruby.network.routers0.percent_links_utilized 6.022466 +system.ruby.network.routers0.msg_count.Request_Control::1 1383 +system.ruby.network.routers0.msg_count.Response_Data::4 1179 system.ruby.network.routers0.msg_count.ResponseL2hit_Data::4 204 system.ruby.network.routers0.msg_count.Response_Control::4 1 -system.ruby.network.routers0.msg_count.Writeback_Data::4 1354 +system.ruby.network.routers0.msg_count.Writeback_Data::4 1355 system.ruby.network.routers0.msg_count.Persistent_Control::3 52 -system.ruby.network.routers0.msg_bytes.Request_Control::1 11056 -system.ruby.network.routers0.msg_bytes.Response_Data::4 84816 +system.ruby.network.routers0.msg_bytes.Request_Control::1 11064 +system.ruby.network.routers0.msg_bytes.Response_Data::4 84888 system.ruby.network.routers0.msg_bytes.ResponseL2hit_Data::4 14688 system.ruby.network.routers0.msg_bytes.Response_Control::4 8 -system.ruby.network.routers0.msg_bytes.Writeback_Data::4 97488 +system.ruby.network.routers0.msg_bytes.Writeback_Data::4 97560 system.ruby.network.routers0.msg_bytes.Persistent_Control::3 416 -system.ruby.network.routers1.percent_links_utilized 4.538904 -system.ruby.network.routers1.msg_count.Request_Control::1 1382 -system.ruby.network.routers1.msg_count.Request_Control::2 1195 +system.ruby.network.routers1.percent_links_utilized 4.541676 +system.ruby.network.routers1.msg_count.Request_Control::1 1383 +system.ruby.network.routers1.msg_count.Request_Control::2 1196 system.ruby.network.routers1.msg_count.ResponseL2hit_Data::4 204 system.ruby.network.routers1.msg_count.Response_Control::4 1 -system.ruby.network.routers1.msg_count.Writeback_Data::4 1583 -system.ruby.network.routers1.msg_count.Writeback_Control::4 967 +system.ruby.network.routers1.msg_count.Writeback_Data::4 1584 +system.ruby.network.routers1.msg_count.Writeback_Control::4 968 system.ruby.network.routers1.msg_count.Persistent_Control::3 26 -system.ruby.network.routers1.msg_bytes.Request_Control::1 11056 -system.ruby.network.routers1.msg_bytes.Request_Control::2 9560 +system.ruby.network.routers1.msg_bytes.Request_Control::1 11064 +system.ruby.network.routers1.msg_bytes.Request_Control::2 9568 system.ruby.network.routers1.msg_bytes.ResponseL2hit_Data::4 14688 system.ruby.network.routers1.msg_bytes.Response_Control::4 8 -system.ruby.network.routers1.msg_bytes.Writeback_Data::4 113976 -system.ruby.network.routers1.msg_bytes.Writeback_Control::4 7736 +system.ruby.network.routers1.msg_bytes.Writeback_Data::4 114048 +system.ruby.network.routers1.msg_bytes.Writeback_Control::4 7744 system.ruby.network.routers1.msg_bytes.Persistent_Control::3 208 -system.ruby.network.routers2.percent_links_utilized 3.429697 -system.ruby.network.routers2.msg_count.Request_Control::2 1195 -system.ruby.network.routers2.msg_count.Response_Data::4 1178 +system.ruby.network.routers2.percent_links_utilized 3.432237 +system.ruby.network.routers2.msg_count.Request_Control::2 1196 +system.ruby.network.routers2.msg_count.Response_Data::4 1179 system.ruby.network.routers2.msg_count.Writeback_Data::4 229 -system.ruby.network.routers2.msg_count.Writeback_Control::4 967 +system.ruby.network.routers2.msg_count.Writeback_Control::4 968 system.ruby.network.routers2.msg_count.Persistent_Control::3 26 -system.ruby.network.routers2.msg_bytes.Request_Control::2 9560 -system.ruby.network.routers2.msg_bytes.Response_Data::4 84816 +system.ruby.network.routers2.msg_bytes.Request_Control::2 9568 +system.ruby.network.routers2.msg_bytes.Response_Data::4 84888 system.ruby.network.routers2.msg_bytes.Writeback_Data::4 16488 -system.ruby.network.routers2.msg_bytes.Writeback_Control::4 7736 +system.ruby.network.routers2.msg_bytes.Writeback_Control::4 7744 system.ruby.network.routers2.msg_bytes.Persistent_Control::3 208 -system.ruby.network.routers3.percent_links_utilized 4.662226 -system.ruby.network.routers3.msg_count.Request_Control::1 1382 -system.ruby.network.routers3.msg_count.Request_Control::2 1195 -system.ruby.network.routers3.msg_count.Response_Data::4 1178 +system.ruby.network.routers3.percent_links_utilized 4.665460 +system.ruby.network.routers3.msg_count.Request_Control::1 1383 +system.ruby.network.routers3.msg_count.Request_Control::2 1196 +system.ruby.network.routers3.msg_count.Response_Data::4 1179 system.ruby.network.routers3.msg_count.ResponseL2hit_Data::4 204 system.ruby.network.routers3.msg_count.Response_Control::4 1 -system.ruby.network.routers3.msg_count.Writeback_Data::4 1583 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0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.latency_hist_seqr::total 1183 +system.ruby.LD.latency_hist_seqr::samples 1185 +system.ruby.LD.latency_hist_seqr::mean 28.779747 +system.ruby.LD.latency_hist_seqr::gmean 6.012520 +system.ruby.LD.latency_hist_seqr::stdev 37.360727 +system.ruby.LD.latency_hist_seqr | 843 71.14% 71.14% | 337 28.44% 99.58% | 2 0.17% 99.75% | 0 0.00% 99.75% | 2 0.17% 99.92% | 1 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.latency_hist_seqr::total 1185 system.ruby.LD.hit_latency_hist_seqr::bucket_size 4 system.ruby.LD.hit_latency_hist_seqr::max_bucket 39 -system.ruby.LD.hit_latency_hist_seqr::samples 758 -system.ruby.LD.hit_latency_hist_seqr::mean 4.034301 -system.ruby.LD.hit_latency_hist_seqr::gmean 1.520848 -system.ruby.LD.hit_latency_hist_seqr::stdev 7.788579 -system.ruby.LD.hit_latency_hist_seqr | 658 86.81% 86.81% | 0 0.00% 86.81% | 0 0.00% 86.81% | 0 0.00% 86.81% | 0 0.00% 86.81% | 0 0.00% 86.81% | 100 13.19% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.hit_latency_hist_seqr::total 758 +system.ruby.LD.hit_latency_hist_seqr::samples 759 +system.ruby.LD.hit_latency_hist_seqr::mean 4.030303 +system.ruby.LD.hit_latency_hist_seqr::gmean 1.520008 +system.ruby.LD.hit_latency_hist_seqr::stdev 7.784219 +system.ruby.LD.hit_latency_hist_seqr | 659 86.82% 86.82% | 0 0.00% 86.82% | 0 0.00% 86.82% | 0 0.00% 86.82% | 0 0.00% 86.82% | 0 0.00% 86.82% | 100 13.18% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.hit_latency_hist_seqr::total 759 system.ruby.LD.miss_latency_hist_seqr::bucket_size 64 system.ruby.LD.miss_latency_hist_seqr::max_bucket 639 -system.ruby.LD.miss_latency_hist_seqr::samples 425 -system.ruby.LD.miss_latency_hist_seqr::mean 72.901176 -system.ruby.LD.miss_latency_hist_seqr::gmean 69.708423 -system.ruby.LD.miss_latency_hist_seqr::stdev 27.218709 -system.ruby.LD.miss_latency_hist_seqr | 84 19.76% 19.76% | 336 79.06% 98.82% | 2 0.47% 99.29% | 0 0.00% 99.29% | 2 0.47% 99.76% | 1 0.24% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.miss_latency_hist_seqr::total 425 +system.ruby.LD.miss_latency_hist_seqr::samples 426 +system.ruby.LD.miss_latency_hist_seqr::mean 72.875587 +system.ruby.LD.miss_latency_hist_seqr::gmean 69.678801 +system.ruby.LD.miss_latency_hist_seqr::stdev 27.158723 +system.ruby.LD.miss_latency_hist_seqr | 84 19.72% 19.72% | 337 79.11% 98.83% | 2 0.47% 99.30% | 0 0.00% 99.30% | 2 0.47% 99.77% | 1 0.23% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.miss_latency_hist_seqr::total 426 system.ruby.ST.latency_hist_seqr::bucket_size 32 system.ruby.ST.latency_hist_seqr::max_bucket 319 system.ruby.ST.latency_hist_seqr::samples 865 -system.ruby.ST.latency_hist_seqr::mean 14.011561 -system.ruby.ST.latency_hist_seqr::gmean 2.583043 -system.ruby.ST.latency_hist_seqr::stdev 26.009033 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+system.ruby.ST.hit_latency_hist_seqr::gmean 1.210352 +system.ruby.ST.hit_latency_hist_seqr::stdev 5.118132 +system.ruby.ST.hit_latency_hist_seqr | 654 93.83% 93.83% | 0 0.00% 93.83% | 0 0.00% 93.83% | 0 0.00% 93.83% | 0 0.00% 93.83% | 21 3.01% 96.84% | 22 3.16% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ST.hit_latency_hist_seqr::total 697 system.ruby.ST.miss_latency_hist_seqr::bucket_size 32 system.ruby.ST.miss_latency_hist_seqr::max_bucket 319 system.ruby.ST.miss_latency_hist_seqr::samples 168 -system.ruby.ST.miss_latency_hist_seqr::mean 62.511905 -system.ruby.ST.miss_latency_hist_seqr::gmean 59.804102 -system.ruby.ST.miss_latency_hist_seqr::stdev 21.242819 +system.ruby.ST.miss_latency_hist_seqr::mean 62.500000 +system.ruby.ST.miss_latency_hist_seqr::gmean 59.782556 +system.ruby.ST.miss_latency_hist_seqr::stdev 21.264516 system.ruby.ST.miss_latency_hist_seqr | 0 0.00% 0.00% | 78 46.43% 46.43% | 85 50.60% 97.02% | 3 1.79% 98.81% | 0 0.00% 98.81% | 1 0.60% 99.40% | 1 0.60% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ST.miss_latency_hist_seqr::total 168 system.ruby.IFETCH.latency_hist_seqr::bucket_size 64 system.ruby.IFETCH.latency_hist_seqr::max_bucket 639 -system.ruby.IFETCH.latency_hist_seqr::samples 6400 -system.ruby.IFETCH.latency_hist_seqr::mean 8.381875 -system.ruby.IFETCH.latency_hist_seqr::gmean 1.532979 -system.ruby.IFETCH.latency_hist_seqr::stdev 24.412953 -system.ruby.IFETCH.latency_hist_seqr | 5815 90.86% 90.86% | 571 8.92% 99.78% | 5 0.08% 99.86% | 2 0.03% 99.89% | 4 0.06% 99.95% | 3 0.05% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.latency_hist_seqr::total 6400 +system.ruby.IFETCH.latency_hist_seqr::samples 6413 +system.ruby.IFETCH.latency_hist_seqr::mean 8.354748 +system.ruby.IFETCH.latency_hist_seqr::gmean 1.531676 +system.ruby.IFETCH.latency_hist_seqr::stdev 24.237273 +system.ruby.IFETCH.latency_hist_seqr | 5828 90.88% 90.88% | 571 8.90% 99.78% | 5 0.08% 99.86% | 3 0.05% 99.91% | 3 0.05% 99.95% | 3 0.05% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.latency_hist_seqr::total 6413 system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 8 system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 79 -system.ruby.IFETCH.hit_latency_hist_seqr::samples 5815 -system.ruby.IFETCH.hit_latency_hist_seqr::mean 1.243164 -system.ruby.IFETCH.hit_latency_hist_seqr::gmean 1.033952 -system.ruby.IFETCH.hit_latency_hist_seqr::stdev 2.371578 -system.ruby.IFETCH.hit_latency_hist_seqr | 5754 98.95% 98.95% | 0 0.00% 98.95% | 2 0.03% 98.99% | 58 1.00% 99.98% | 0 0.00% 99.98% | 1 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.hit_latency_hist_seqr::total 5815 +system.ruby.IFETCH.hit_latency_hist_seqr::samples 5828 +system.ruby.IFETCH.hit_latency_hist_seqr::mean 1.243480 +system.ruby.IFETCH.hit_latency_hist_seqr::gmean 1.033914 +system.ruby.IFETCH.hit_latency_hist_seqr::stdev 2.376718 +system.ruby.IFETCH.hit_latency_hist_seqr | 5767 98.95% 98.95% | 0 0.00% 98.95% | 0 0.00% 98.95% | 60 1.03% 99.98% | 0 0.00% 99.98% | 1 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.hit_latency_hist_seqr::total 5828 system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 64 system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 639 system.ruby.IFETCH.miss_latency_hist_seqr::samples 585 -system.ruby.IFETCH.miss_latency_hist_seqr::mean 79.341880 -system.ruby.IFETCH.miss_latency_hist_seqr::gmean 76.853466 -system.ruby.IFETCH.miss_latency_hist_seqr::stdev 30.381468 -system.ruby.IFETCH.miss_latency_hist_seqr | 0 0.00% 0.00% | 571 97.61% 97.61% | 5 0.85% 98.46% | 2 0.34% 98.80% | 4 0.68% 99.49% | 3 0.51% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.miss_latency_hist_seqr::mean 79.200000 +system.ruby.IFETCH.miss_latency_hist_seqr::gmean 76.837583 +system.ruby.IFETCH.miss_latency_hist_seqr::stdev 29.345532 +system.ruby.IFETCH.miss_latency_hist_seqr | 0 0.00% 0.00% | 571 97.61% 97.61% | 5 0.85% 98.46% | 3 0.51% 98.97% | 3 0.51% 99.49% | 3 0.51% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.miss_latency_hist_seqr::total 585 system.ruby.L1Cache.hit_mach_latency_hist_seqr::bucket_size 1 system.ruby.L1Cache.hit_mach_latency_hist_seqr::max_bucket 9 -system.ruby.L1Cache.hit_mach_latency_hist_seqr::samples 7066 +system.ruby.L1Cache.hit_mach_latency_hist_seqr::samples 7080 system.ruby.L1Cache.hit_mach_latency_hist_seqr::mean 1 system.ruby.L1Cache.hit_mach_latency_hist_seqr::gmean 1 -system.ruby.L1Cache.hit_mach_latency_hist_seqr | 0 0.00% 0.00% | 7066 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache.hit_mach_latency_hist_seqr::total 7066 +system.ruby.L1Cache.hit_mach_latency_hist_seqr | 0 0.00% 0.00% | 7080 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache.hit_mach_latency_hist_seqr::total 7080 system.ruby.L2Cache.hit_mach_latency_hist_seqr::bucket_size 8 system.ruby.L2Cache.hit_mach_latency_hist_seqr::max_bucket 79 system.ruby.L2Cache.hit_mach_latency_hist_seqr::samples 204 -system.ruby.L2Cache.hit_mach_latency_hist_seqr::mean 23.720588 -system.ruby.L2Cache.hit_mach_latency_hist_seqr::gmean 23.671773 -system.ruby.L2Cache.hit_mach_latency_hist_seqr::stdev 1.608281 -system.ruby.L2Cache.hit_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 19 9.31% 9.31% | 184 90.20% 99.51% | 0 0.00% 99.51% | 1 0.49% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L2Cache.hit_mach_latency_hist_seqr::mean 23.691176 +system.ruby.L2Cache.hit_mach_latency_hist_seqr::gmean 23.640301 +system.ruby.L2Cache.hit_mach_latency_hist_seqr::stdev 1.636324 +system.ruby.L2Cache.hit_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 21 10.29% 10.29% | 182 89.22% 99.51% | 0 0.00% 99.51% | 1 0.49% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.L2Cache.hit_mach_latency_hist_seqr::total 204 system.ruby.Directory.miss_mach_latency_hist_seqr::bucket_size 64 system.ruby.Directory.miss_mach_latency_hist_seqr::max_bucket 639 -system.ruby.Directory.miss_mach_latency_hist_seqr::samples 1178 -system.ruby.Directory.miss_mach_latency_hist_seqr::mean 74.617997 -system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 71.587772 -system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 28.670099 -system.ruby.Directory.miss_mach_latency_hist_seqr | 162 13.75% 13.75% | 995 84.47% 98.22% | 8 0.68% 98.90% | 3 0.25% 99.15% | 6 0.51% 99.66% | 4 0.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_mach_latency_hist_seqr::total 1178 +system.ruby.Directory.miss_mach_latency_hist_seqr::samples 1179 +system.ruby.Directory.miss_mach_latency_hist_seqr::mean 74.535199 +system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 71.564149 +system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 28.099799 +system.ruby.Directory.miss_mach_latency_hist_seqr | 162 13.74% 13.74% | 996 84.48% 98.22% | 8 0.68% 98.90% | 4 0.34% 99.24% | 5 0.42% 99.66% | 4 0.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_mach_latency_hist_seqr::total 1179 system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::bucket_size 1 system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::max_bucket 9 system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::samples 1 @@ -661,11 +661,11 @@ system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion | system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::total 1 system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::bucket_size 1 system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::max_bucket 9 -system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::samples 658 +system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::samples 659 system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::mean 1 system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::gmean 1 -system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 658 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::total 658 +system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 659 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::total 659 system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::bucket_size 4 system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::max_bucket 39 system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::samples 100 @@ -675,12 +675,12 @@ system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr | 0 0.00% system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::total 100 system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples 425 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 72.901176 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 69.708423 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 27.218709 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 84 19.76% 19.76% | 336 79.06% 98.82% | 2 0.47% 99.29% | 0 0.00% 99.29% | 2 0.47% 99.76% | 1 0.24% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total 425 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples 426 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 72.875587 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 69.678801 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 27.158723 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 84 19.72% 19.72% | 337 79.11% 98.83% | 2 0.47% 99.30% | 0 0.00% 99.30% | 2 0.47% 99.77% | 1 0.23% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total 426 system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::bucket_size 1 system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::max_bucket 9 system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::samples 654 @@ -691,99 +691,99 @@ system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::total 654 system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::bucket_size 4 system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::max_bucket 39 system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::samples 43 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::mean 22.418605 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::gmean 22.330941 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::stdev 1.978847 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 17 39.53% 39.53% | 26 60.47% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::mean 22.162791 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::gmean 22.076919 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::stdev 1.963115 +system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 21 48.84% 48.84% | 22 51.16% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::total 43 system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size 32 system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket 319 system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::samples 168 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 62.511905 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 59.804102 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 21.242819 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 62.500000 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 59.782556 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 21.264516 system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 78 46.43% 46.43% | 85 50.60% 97.02% | 3 1.79% 98.81% | 0 0.00% 98.81% | 1 0.60% 99.40% | 1 0.60% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total 168 system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::bucket_size 1 system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::max_bucket 9 -system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::samples 5754 +system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::samples 5767 system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::mean 1 system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::gmean 1 -system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 5754 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::total 5754 +system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 5767 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::total 5767 system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::bucket_size 8 system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::max_bucket 79 system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::samples 61 -system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::mean 24.180328 -system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::gmean 24.114482 -system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::stdev 2.109567 -system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 2 3.28% 3.28% | 58 95.08% 98.36% | 0 0.00% 98.36% | 1 1.64% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::mean 24.262295 +system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::gmean 24.201824 +system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::stdev 2.048590 +system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 60 98.36% 98.36% | 0 0.00% 98.36% | 1 1.64% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::total 61 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::samples 585 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 79.341880 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 76.853466 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 30.381468 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 571 97.61% 97.61% | 5 0.85% 98.46% | 2 0.34% 98.80% | 4 0.68% 99.49% | 3 0.51% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 79.200000 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 76.837583 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 29.345532 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 571 97.61% 97.61% | 5 0.85% 98.46% | 3 0.51% 98.97% | 3 0.51% 99.49% | 3 0.51% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::total 585 system.ruby.Directory_Controller.GETX 208 0.00% 0.00% -system.ruby.Directory_Controller.GETS 1016 0.00% 0.00% +system.ruby.Directory_Controller.GETS 1017 0.00% 0.00% system.ruby.Directory_Controller.Lockdown 13 0.00% 0.00% system.ruby.Directory_Controller.Unlockdown 13 0.00% 0.00% system.ruby.Directory_Controller.Data_Owner 9 0.00% 0.00% system.ruby.Directory_Controller.Data_All_Tokens 220 0.00% 0.00% system.ruby.Directory_Controller.Ack_Owner 29 0.00% 0.00% -system.ruby.Directory_Controller.Ack_Owner_All_Tokens 904 0.00% 0.00% +system.ruby.Directory_Controller.Ack_Owner_All_Tokens 905 0.00% 0.00% system.ruby.Directory_Controller.Ack_All_Tokens 34 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 1178 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 1179 0.00% 0.00% system.ruby.Directory_Controller.Memory_Ack 229 0.00% 0.00% system.ruby.Directory_Controller.O.GETX 168 0.00% 0.00% -system.ruby.Directory_Controller.O.GETS 1010 0.00% 0.00% +system.ruby.Directory_Controller.O.GETS 1011 0.00% 0.00% system.ruby.Directory_Controller.O.Ack_All_Tokens 34 0.00% 0.00% system.ruby.Directory_Controller.NO.GETX 17 0.00% 0.00% system.ruby.Directory_Controller.NO.Lockdown 2 0.00% 0.00% system.ruby.Directory_Controller.NO.Data_Owner 9 0.00% 0.00% system.ruby.Directory_Controller.NO.Data_All_Tokens 220 0.00% 0.00% system.ruby.Directory_Controller.NO.Ack_Owner 29 0.00% 0.00% -system.ruby.Directory_Controller.NO.Ack_Owner_All_Tokens 904 0.00% 0.00% +system.ruby.Directory_Controller.NO.Ack_Owner_All_Tokens 905 0.00% 0.00% system.ruby.Directory_Controller.L.Unlockdown 13 0.00% 0.00% system.ruby.Directory_Controller.O_W.GETX 23 0.00% 0.00% system.ruby.Directory_Controller.O_W.GETS 6 0.00% 0.00% system.ruby.Directory_Controller.O_W.Memory_Ack 229 0.00% 0.00% system.ruby.Directory_Controller.L_NO_W.Memory_Data 11 0.00% 0.00% system.ruby.Directory_Controller.NO_W.Lockdown 11 0.00% 0.00% -system.ruby.Directory_Controller.NO_W.Memory_Data 1167 0.00% 0.00% -system.ruby.L1Cache_Controller.Load 1183 0.00% 0.00% -system.ruby.L1Cache_Controller.Ifetch 6400 0.00% 0.00% +system.ruby.Directory_Controller.NO_W.Memory_Data 1168 0.00% 0.00% +system.ruby.L1Cache_Controller.Load 1185 0.00% 0.00% +system.ruby.L1Cache_Controller.Ifetch 6413 0.00% 0.00% system.ruby.L1Cache_Controller.Store 865 0.00% 0.00% -system.ruby.L1Cache_Controller.L1_Replacement 1367 0.00% 0.00% +system.ruby.L1Cache_Controller.L1_Replacement 1368 0.00% 0.00% system.ruby.L1Cache_Controller.Data_Shared 161 0.00% 0.00% -system.ruby.L1Cache_Controller.Data_All_Tokens 1221 0.00% 0.00% +system.ruby.L1Cache_Controller.Data_All_Tokens 1222 0.00% 0.00% system.ruby.L1Cache_Controller.Ack 1 0.00% 0.00% system.ruby.L1Cache_Controller.Own_Lock_or_Unlock 26 0.00% 0.00% system.ruby.L1Cache_Controller.Request_Timeout 13 0.00% 0.00% -system.ruby.L1Cache_Controller.Use_TimeoutNoStarvers 1220 0.00% 0.00% -system.ruby.L1Cache_Controller.NP.Load 525 0.00% 0.00% +system.ruby.L1Cache_Controller.Use_TimeoutNoStarvers 1221 0.00% 0.00% +system.ruby.L1Cache_Controller.NP.Load 526 0.00% 0.00% system.ruby.L1Cache_Controller.NP.Ifetch 646 0.00% 0.00% system.ruby.L1Cache_Controller.NP.Store 191 0.00% 0.00% system.ruby.L1Cache_Controller.S.Load 153 0.00% 0.00% system.ruby.L1Cache_Controller.S.Ifetch 331 0.00% 0.00% system.ruby.L1Cache_Controller.S.Store 20 0.00% 0.00% system.ruby.L1Cache_Controller.S.L1_Replacement 141 0.00% 0.00% -system.ruby.L1Cache_Controller.M.Load 180 0.00% 0.00% -system.ruby.L1Cache_Controller.M.Ifetch 3187 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Load 181 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Ifetch 3194 0.00% 0.00% system.ruby.L1Cache_Controller.M.Store 33 0.00% 0.00% -system.ruby.L1Cache_Controller.M.L1_Replacement 945 0.00% 0.00% +system.ruby.L1Cache_Controller.M.L1_Replacement 946 0.00% 0.00% system.ruby.L1Cache_Controller.M.Own_Lock_or_Unlock 13 0.00% 0.00% system.ruby.L1Cache_Controller.MM.Load 218 0.00% 0.00% system.ruby.L1Cache_Controller.MM.Store 265 0.00% 0.00% system.ruby.L1Cache_Controller.MM.L1_Replacement 268 0.00% 0.00% system.ruby.L1Cache_Controller.M_W.Load 84 0.00% 0.00% -system.ruby.L1Cache_Controller.M_W.Ifetch 2236 0.00% 0.00% +system.ruby.L1Cache_Controller.M_W.Ifetch 2242 0.00% 0.00% system.ruby.L1Cache_Controller.M_W.Store 25 0.00% 0.00% system.ruby.L1Cache_Controller.M_W.L1_Replacement 9 0.00% 0.00% -system.ruby.L1Cache_Controller.M_W.Use_TimeoutNoStarvers 984 0.00% 0.00% +system.ruby.L1Cache_Controller.M_W.Use_TimeoutNoStarvers 985 0.00% 0.00% system.ruby.L1Cache_Controller.MM_W.Load 23 0.00% 0.00% system.ruby.L1Cache_Controller.MM_W.Store 331 0.00% 0.00% system.ruby.L1Cache_Controller.MM_W.L1_Replacement 4 0.00% 0.00% @@ -792,21 +792,21 @@ system.ruby.L1Cache_Controller.IM.Data_All_Tokens 191 0.00% 0 system.ruby.L1Cache_Controller.IM.Ack 1 0.00% 0.00% system.ruby.L1Cache_Controller.SM.Data_All_Tokens 20 0.00% 0.00% system.ruby.L1Cache_Controller.IS.Data_Shared 161 0.00% 0.00% -system.ruby.L1Cache_Controller.IS.Data_All_Tokens 1010 0.00% 0.00% +system.ruby.L1Cache_Controller.IS.Data_All_Tokens 1011 0.00% 0.00% system.ruby.L1Cache_Controller.IS.Own_Lock_or_Unlock 13 0.00% 0.00% system.ruby.L1Cache_Controller.IS.Request_Timeout 13 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_GETS 1122 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_GETS 1123 0.00% 0.00% system.ruby.L2Cache_Controller.L1_GETS_Last_Token 49 0.00% 0.00% system.ruby.L2Cache_Controller.L1_GETX 211 0.00% 0.00% -system.ruby.L2Cache_Controller.L2_Replacement 1265 0.00% 0.00% +system.ruby.L2Cache_Controller.L2_Replacement 1266 0.00% 0.00% system.ruby.L2Cache_Controller.Writeback_Shared_Data 84 0.00% 0.00% -system.ruby.L2Cache_Controller.Writeback_All_Tokens 1270 0.00% 0.00% +system.ruby.L2Cache_Controller.Writeback_All_Tokens 1271 0.00% 0.00% system.ruby.L2Cache_Controller.Persistent_GETS 13 0.00% 0.00% system.ruby.L2Cache_Controller.Own_Lock_or_Unlock 13 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.L1_GETS 1010 0.00% 0.00% +system.ruby.L2Cache_Controller.NP.L1_GETS 1011 0.00% 0.00% system.ruby.L2Cache_Controller.NP.L1_GETX 166 0.00% 0.00% system.ruby.L2Cache_Controller.NP.Writeback_Shared_Data 81 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.Writeback_All_Tokens 1192 0.00% 0.00% +system.ruby.L2Cache_Controller.NP.Writeback_All_Tokens 1193 0.00% 0.00% system.ruby.L2Cache_Controller.NP.Own_Lock_or_Unlock 13 0.00% 0.00% system.ruby.L2Cache_Controller.I.L1_GETX 1 0.00% 0.00% system.ruby.L2Cache_Controller.I.L2_Replacement 69 0.00% 0.00% @@ -820,7 +820,7 @@ system.ruby.L2Cache_Controller.O.L2_Replacement 38 0.00% 0.0 system.ruby.L2Cache_Controller.O.Writeback_All_Tokens 57 0.00% 0.00% system.ruby.L2Cache_Controller.M.L1_GETS 112 0.00% 0.00% system.ruby.L2Cache_Controller.M.L1_GETX 26 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L2_Replacement 1124 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L2_Replacement 1125 0.00% 0.00% system.ruby.L2Cache_Controller.I_L.Persistent_GETS 13 0.00% 0.00% ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini index b9a8c8074..7e20448ad 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini @@ -120,7 +120,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello +executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin kvmInSE=false diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout index 2e0d7516c..2d739759e 100755 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout @@ -1,13 +1,15 @@ +Redirecting stdout to build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer/simout +Redirecting stderr to build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 21 2016 13:56:08 -gem5 started Jan 21 2016 13:56:42 -gem5 executing on zizzer, pid 39359 -command line: build/ALPHA_MOESI_hammer/gem5.opt -d build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer +gem5 compiled Mar 14 2016 21:55:52 +gem5 started Mar 14 2016 21:57:33 +gem5 executing on phenom, pid 28167 +command line: build/ALPHA_MOESI_hammer/gem5.opt -d build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 86673 because target called exit() +Exiting @ tick 86770 because target called exit() diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt index fc2b85717..7e8297657 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt @@ -1,40 +1,40 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000087 # Number of seconds simulated -sim_ticks 86673 # Number of ticks simulated -final_tick 86673 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 86770 # Number of ticks simulated +final_tick 86770 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 58973 # Simulator instruction rate (inst/s) -host_op_rate 58962 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 799609 # Simulator tick rate (ticks/s) -host_mem_usage 411856 # Number of bytes of host memory used -host_seconds 0.11 # Real time elapsed on the host -sim_insts 6390 # Number of instructions simulated -sim_ops 6390 # Number of ops (including micro ops) simulated +host_inst_rate 43915 # Simulator instruction rate (inst/s) +host_op_rate 43910 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 594975 # Simulator tick rate (ticks/s) +host_mem_usage 388108 # Number of bytes of host memory used +host_seconds 0.15 # Real time elapsed on the host +sim_insts 6403 # Number of instructions simulated +sim_ops 6403 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks -system.mem_ctrls.bytes_read::ruby.dir_cntrl0 74176 # Number of bytes read from this memory -system.mem_ctrls.bytes_read::total 74176 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::ruby.dir_cntrl0 74240 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 74240 # Number of bytes read from this memory system.mem_ctrls.bytes_written::ruby.dir_cntrl0 14080 # Number of bytes written to this memory system.mem_ctrls.bytes_written::total 14080 # Number of bytes written to this memory -system.mem_ctrls.num_reads::ruby.dir_cntrl0 1159 # Number of read requests responded to by this memory -system.mem_ctrls.num_reads::total 1159 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::ruby.dir_cntrl0 1160 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 1160 # Number of read requests responded to by this memory system.mem_ctrls.num_writes::ruby.dir_cntrl0 220 # Number of write requests responded to by this memory system.mem_ctrls.num_writes::total 220 # Number of write requests responded to by this memory -system.mem_ctrls.bw_read::ruby.dir_cntrl0 855814383 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_read::total 855814383 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::ruby.dir_cntrl0 162449667 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::total 162449667 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_total::ruby.dir_cntrl0 1018264050 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.bw_total::total 1018264050 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.readReqs 1159 # Number of read requests accepted +system.mem_ctrls.bw_read::ruby.dir_cntrl0 855595252 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 855595252 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::ruby.dir_cntrl0 162268065 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::total 162268065 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::ruby.dir_cntrl0 1017863317 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 1017863317 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.readReqs 1160 # Number of read requests accepted system.mem_ctrls.writeReqs 220 # Number of write requests accepted -system.mem_ctrls.readBursts 1159 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.readBursts 1160 # Number of DRAM read bursts, including those serviced by the write queue system.mem_ctrls.writeBursts 220 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrls.bytesReadDRAM 63680 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadDRAM 63744 # Total number of bytes read from DRAM system.mem_ctrls.bytesReadWrQ 10496 # Total number of bytes read from write queue system.mem_ctrls.bytesWritten 5504 # Total number of bytes written to DRAM -system.mem_ctrls.bytesReadSys 74176 # Total read bytes from the system interface side +system.mem_ctrls.bytesReadSys 74240 # Total read bytes from the system interface side system.mem_ctrls.bytesWrittenSys 14080 # Total written bytes from the system interface side system.mem_ctrls.servicedByWrQ 164 # Number of DRAM read bursts serviced by the write queue system.mem_ctrls.mergedWrBursts 109 # Number of DRAM write bursts merged with an existing one @@ -54,7 +54,7 @@ system.mem_ctrls.perBankRdBursts::11 47 # Pe system.mem_ctrls.perBankRdBursts::12 22 # Per bank write bursts system.mem_ctrls.perBankRdBursts::13 358 # Per bank write bursts system.mem_ctrls.perBankRdBursts::14 61 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::15 40 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::15 41 # Per bank write bursts system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts @@ -73,14 +73,14 @@ system.mem_ctrls.perBankWrBursts::14 42 # Pe system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrls.totGap 86601 # Total gap between requests +system.mem_ctrls.totGap 86698 # Total gap between requests system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::6 1159 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 1160 # Read request sizes (log2) system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) @@ -88,7 +88,7 @@ system.mem_ctrls.writePktSize::3 0 # Wr system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::6 220 # Write request sizes (log2) -system.mem_ctrls.rdQLenPdf::0 995 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::0 996 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see @@ -184,24 +184,24 @@ system.mem_ctrls.wrQLenPdf::60 0 # Wh system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrls.bytesPerActivate::samples 190 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::mean 360.757895 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::gmean 214.175980 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::stdev 351.466789 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::0-127 60 31.58% 31.58% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::128-255 43 22.63% 54.21% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::256-383 19 10.00% 64.21% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::384-511 13 6.84% 71.05% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::512-639 11 5.79% 76.84% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::640-767 4 2.11% 78.95% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::768-895 8 4.21% 83.16% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::896-1023 5 2.63% 85.79% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::1024-1151 27 14.21% 100.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::total 190 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::samples 191 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 358.869110 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 215.937059 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 347.377875 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 57 29.84% 29.84% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 46 24.08% 53.93% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 20 10.47% 64.40% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 14 7.33% 71.73% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 10 5.24% 76.96% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 4 2.09% 79.06% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 7 3.66% 82.72% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 8 4.19% 86.91% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 25 13.09% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 191 # Bytes accessed per row activation system.mem_ctrls.rdPerTurnAround::samples 5 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::mean 143.200000 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::gmean 107.762756 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::stdev 83.250826 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::mean 143.400000 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::gmean 107.861440 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::stdev 83.476344 # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::16-23 1 20.00% 20.00% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::120-127 1 20.00% 40.00% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::128-135 1 20.00% 60.00% # Reads before turning the bus around for writes @@ -214,77 +214,77 @@ system.mem_ctrls.wrPerTurnAround::stdev 1.095445 # Wr system.mem_ctrls.wrPerTurnAround::16 2 40.00% 40.00% # Writes before turning the bus around for reads system.mem_ctrls.wrPerTurnAround::18 3 60.00% 100.00% # Writes before turning the bus around for reads system.mem_ctrls.wrPerTurnAround::total 5 # Writes before turning the bus around for reads -system.mem_ctrls.totQLat 6132 # Total ticks spent queuing -system.mem_ctrls.totMemAccLat 25037 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrls.totBusLat 4975 # Total ticks spent in databus transfers -system.mem_ctrls.avgQLat 6.16 # Average queueing delay per DRAM burst +system.mem_ctrls.totQLat 6142 # Total ticks spent queuing +system.mem_ctrls.totMemAccLat 25066 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.totBusLat 4980 # Total ticks spent in databus transfers +system.mem_ctrls.avgQLat 6.17 # Average queueing delay per DRAM burst system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst -system.mem_ctrls.avgMemAccLat 25.16 # Average memory access latency per DRAM burst -system.mem_ctrls.avgRdBW 734.72 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrls.avgWrBW 63.50 # Average achieved write bandwidth in MiByte/s -system.mem_ctrls.avgRdBWSys 855.81 # Average system read bandwidth in MiByte/s -system.mem_ctrls.avgWrBWSys 162.45 # Average system write bandwidth in MiByte/s +system.mem_ctrls.avgMemAccLat 25.17 # Average memory access latency per DRAM burst +system.mem_ctrls.avgRdBW 734.63 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 63.43 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 855.60 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 162.27 # Average system write bandwidth in MiByte/s system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrls.busUtil 6.24 # Data bus utilization in percentage +system.mem_ctrls.busUtil 6.23 # Data bus utilization in percentage system.mem_ctrls.busUtilRead 5.74 # Data bus utilization in percentage for reads system.mem_ctrls.busUtilWrite 0.50 # Data bus utilization in percentage for writes system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing -system.mem_ctrls.avgWrQLen 20.56 # Average write queue length when enqueuing +system.mem_ctrls.avgWrQLen 20.55 # Average write queue length when enqueuing system.mem_ctrls.readRowHits 808 # Number of row buffer hits during reads system.mem_ctrls.writeRowHits 78 # Number of row buffer hits during writes -system.mem_ctrls.readRowHitRate 81.21 # Row buffer hit rate for reads +system.mem_ctrls.readRowHitRate 81.12 # Row buffer hit rate for reads system.mem_ctrls.writeRowHitRate 70.27 # Row buffer hit rate for writes -system.mem_ctrls.avgGap 62.80 # Average gap between requests -system.mem_ctrls.pageHitRate 80.11 # Row buffer hit rate, read and write combined -system.mem_ctrls_0.actEnergy 461160 # Energy for activate commands per rank (pJ) -system.mem_ctrls_0.preEnergy 256200 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.avgGap 62.82 # Average gap between requests +system.mem_ctrls.pageHitRate 80.04 # Row buffer hit rate, read and write combined +system.mem_ctrls_0.actEnergy 476280 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 264600 # Energy for precharge commands per rank (pJ) system.mem_ctrls_0.readEnergy 5091840 # Energy for read commands per rank (pJ) system.mem_ctrls_0.writeEnergy 259200 # Energy for write commands per rank (pJ) system.mem_ctrls_0.refreshEnergy 5594160 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_0.actBackEnergy 49992876 # Energy for active background per rank (pJ) -system.mem_ctrls_0.preBackEnergy 7690200 # Energy for precharge background per rank (pJ) -system.mem_ctrls_0.totalEnergy 69345636 # Total energy per rank (pJ) -system.mem_ctrls_0.averagePower 807.226922 # Core power per rank (mW) -system.mem_ctrls_0.memoryStateTime::IDLE 12934 # Time in different power states +system.mem_ctrls_0.actBackEnergy 50178924 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 7527000 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.totalEnergy 69392004 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 807.766675 # Core power per rank (mW) +system.mem_ctrls_0.memoryStateTime::IDLE 12759 # Time in different power states system.mem_ctrls_0.memoryStateTime::REF 2860 # Time in different power states system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT 70523 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 70795 # Time in different power states system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrls_1.actEnergy 975240 # Energy for activate commands per rank (pJ) -system.mem_ctrls_1.preEnergy 541800 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.actEnergy 967680 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 537600 # Energy for precharge commands per rank (pJ) system.mem_ctrls_1.readEnergy 7200960 # Energy for read commands per rank (pJ) system.mem_ctrls_1.writeEnergy 632448 # Energy for write commands per rank (pJ) system.mem_ctrls_1.refreshEnergy 5594160 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_1.actBackEnergy 57826728 # Energy for active background per rank (pJ) -system.mem_ctrls_1.preBackEnergy 818400 # Energy for precharge background per rank (pJ) -system.mem_ctrls_1.totalEnergy 73589736 # Total energy per rank (pJ) -system.mem_ctrls_1.averagePower 856.630922 # Core power per rank (mW) -system.mem_ctrls_1.memoryStateTime::IDLE 958 # Time in different power states +system.mem_ctrls_1.actBackEnergy 57849984 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 798000 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.totalEnergy 73580832 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 856.527274 # Core power per rank (mW) +system.mem_ctrls_1.memoryStateTime::IDLE 910 # Time in different power states system.mem_ctrls_1.memoryStateTime::REF 2860 # Time in different power states system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT 82102 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 82150 # Time in different power states system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.clk_domain.clock 1 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 1183 # DTB read hits +system.cpu.dtb.read_hits 1185 # DTB read hits system.cpu.dtb.read_misses 7 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 1190 # DTB read accesses +system.cpu.dtb.read_accesses 1192 # DTB read accesses system.cpu.dtb.write_hits 865 # DTB write hits system.cpu.dtb.write_misses 3 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations system.cpu.dtb.write_accesses 868 # DTB write accesses -system.cpu.dtb.data_hits 2048 # DTB hits +system.cpu.dtb.data_hits 2050 # DTB hits system.cpu.dtb.data_misses 10 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 2058 # DTB accesses -system.cpu.itb.fetch_hits 6401 # ITB hits +system.cpu.dtb.data_accesses 2060 # DTB accesses +system.cpu.itb.fetch_hits 6414 # ITB hits system.cpu.itb.fetch_misses 17 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 6418 # ITB accesses +system.cpu.itb.fetch_accesses 6431 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -298,238 +298,238 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 86673 # number of cpu cycles simulated +system.cpu.numCycles 86770 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 6390 # Number of instructions committed -system.cpu.committedOps 6390 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 6317 # Number of integer alu accesses +system.cpu.committedInsts 6403 # Number of instructions committed +system.cpu.committedOps 6403 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 6329 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses system.cpu.num_func_calls 251 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 749 # number of instructions that are conditional controls -system.cpu.num_int_insts 6317 # number of integer instructions +system.cpu.num_conditional_control_insts 754 # number of instructions that are conditional controls +system.cpu.num_int_insts 6329 # number of integer instructions system.cpu.num_fp_insts 10 # number of float instructions -system.cpu.num_int_register_reads 8285 # number of times the integer registers were read -system.cpu.num_int_register_writes 4568 # number of times the integer registers were written +system.cpu.num_int_register_reads 8297 # number of times the integer registers were read +system.cpu.num_int_register_writes 4575 # number of times the integer registers were written system.cpu.num_fp_register_reads 8 # number of times the floating registers were read system.cpu.num_fp_register_writes 2 # number of times the floating registers were written -system.cpu.num_mem_refs 2058 # number of memory refs -system.cpu.num_load_insts 1190 # Number of load instructions +system.cpu.num_mem_refs 2060 # number of memory refs +system.cpu.num_load_insts 1192 # Number of load instructions system.cpu.num_store_insts 868 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 86673 # Number of busy cycles +system.cpu.num_busy_cycles 86770 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 1050 # Number of branches fetched +system.cpu.Branches 1056 # Number of branches fetched system.cpu.op_class::No_OpClass 19 0.30% 0.30% # Class of executed instruction -system.cpu.op_class::IntAlu 4320 67.50% 67.80% # Class of executed instruction -system.cpu.op_class::IntMult 1 0.02% 67.81% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 67.81% # Class of executed instruction -system.cpu.op_class::FloatAdd 2 0.03% 67.84% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::MemRead 1190 18.59% 86.44% # Class of executed instruction -system.cpu.op_class::MemWrite 868 13.56% 100.00% # Class of executed instruction +system.cpu.op_class::IntAlu 4331 67.53% 67.83% # Class of executed instruction +system.cpu.op_class::IntMult 1 0.02% 67.85% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 67.85% # Class of executed instruction +system.cpu.op_class::FloatAdd 2 0.03% 67.88% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::MemRead 1192 18.59% 86.46% # Class of executed instruction +system.cpu.op_class::MemWrite 868 13.54% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 6400 # Class of executed instruction +system.cpu.op_class::total 6413 # Class of executed instruction system.ruby.clk_domain.clock 1 # Clock period in ticks system.ruby.outstanding_req_hist_seqr::bucket_size 1 system.ruby.outstanding_req_hist_seqr::max_bucket 9 -system.ruby.outstanding_req_hist_seqr::samples 8449 +system.ruby.outstanding_req_hist_seqr::samples 8464 system.ruby.outstanding_req_hist_seqr::mean 1 system.ruby.outstanding_req_hist_seqr::gmean 1 -system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 8449 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.outstanding_req_hist_seqr::total 8449 +system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 8464 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist_seqr::total 8464 system.ruby.latency_hist_seqr::bucket_size 64 system.ruby.latency_hist_seqr::max_bucket 639 -system.ruby.latency_hist_seqr::samples 8448 -system.ruby.latency_hist_seqr::mean 9.259588 -system.ruby.latency_hist_seqr::gmean 1.841457 -system.ruby.latency_hist_seqr::stdev 22.233278 -system.ruby.latency_hist_seqr | 8216 97.25% 97.25% | 221 2.62% 99.87% | 0 0.00% 99.87% | 3 0.04% 99.91% | 6 0.07% 99.98% | 2 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.latency_hist_seqr::total 8448 +system.ruby.latency_hist_seqr::samples 8463 +system.ruby.latency_hist_seqr::mean 9.252865 +system.ruby.latency_hist_seqr::gmean 1.840314 +system.ruby.latency_hist_seqr::stdev 22.282539 +system.ruby.latency_hist_seqr | 8231 97.26% 97.26% | 222 2.62% 99.88% | 0 0.00% 99.88% | 1 0.01% 99.89% | 7 0.08% 99.98% | 2 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.latency_hist_seqr::total 8463 system.ruby.hit_latency_hist_seqr::bucket_size 2 system.ruby.hit_latency_hist_seqr::max_bucket 19 -system.ruby.hit_latency_hist_seqr::samples 7289 -system.ruby.hit_latency_hist_seqr::mean 1.278502 -system.ruby.hit_latency_hist_seqr::gmean 1.069062 -system.ruby.hit_latency_hist_seqr::stdev 1.645548 -system.ruby.hit_latency_hist_seqr | 7086 97.21% 97.21% | 0 0.00% 97.21% | 0 0.00% 97.21% | 0 0.00% 97.21% | 0 0.00% 97.21% | 203 2.79% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.hit_latency_hist_seqr::total 7289 +system.ruby.hit_latency_hist_seqr::samples 7303 +system.ruby.hit_latency_hist_seqr::mean 1.277968 +system.ruby.hit_latency_hist_seqr::gmean 1.068925 +system.ruby.hit_latency_hist_seqr::stdev 1.644014 +system.ruby.hit_latency_hist_seqr | 7100 97.22% 97.22% | 0 0.00% 97.22% | 0 0.00% 97.22% | 0 0.00% 97.22% | 0 0.00% 97.22% | 203 2.78% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.hit_latency_hist_seqr::total 7303 system.ruby.miss_latency_hist_seqr::bucket_size 64 system.ruby.miss_latency_hist_seqr::max_bucket 639 -system.ruby.miss_latency_hist_seqr::samples 1159 -system.ruby.miss_latency_hist_seqr::mean 59.452977 -system.ruby.miss_latency_hist_seqr::gmean 56.282360 -system.ruby.miss_latency_hist_seqr::stdev 25.811948 -system.ruby.miss_latency_hist_seqr | 927 79.98% 79.98% | 221 19.07% 99.05% | 0 0.00% 99.05% | 3 0.26% 99.31% | 6 0.52% 99.83% | 2 0.17% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.miss_latency_hist_seqr::total 1159 -system.ruby.Directory.incomplete_times_seqr 1158 +system.ruby.miss_latency_hist_seqr::samples 1160 +system.ruby.miss_latency_hist_seqr::mean 59.460345 +system.ruby.miss_latency_hist_seqr::gmean 56.276317 +system.ruby.miss_latency_hist_seqr::stdev 26.160126 +system.ruby.miss_latency_hist_seqr | 928 80.00% 80.00% | 222 19.14% 99.14% | 0 0.00% 99.14% | 1 0.09% 99.22% | 7 0.60% 99.83% | 2 0.17% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.miss_latency_hist_seqr::total 1160 +system.ruby.Directory.incomplete_times_seqr 1159 system.ruby.dir_cntrl0.probeFilter.demand_hits 0 # Number of cache demand hits system.ruby.dir_cntrl0.probeFilter.demand_misses 0 # Number of cache demand misses system.ruby.dir_cntrl0.probeFilter.demand_accesses 0 # Number of cache demand accesses -system.ruby.l1_cntrl0.L1Dcache.demand_hits 1332 # Number of cache demand hits -system.ruby.l1_cntrl0.L1Dcache.demand_misses 716 # Number of cache demand misses -system.ruby.l1_cntrl0.L1Dcache.demand_accesses 2048 # Number of cache demand accesses -system.ruby.l1_cntrl0.L1Icache.demand_hits 5754 # Number of cache demand hits +system.ruby.l1_cntrl0.L1Dcache.demand_hits 1333 # Number of cache demand hits +system.ruby.l1_cntrl0.L1Dcache.demand_misses 717 # Number of cache demand misses +system.ruby.l1_cntrl0.L1Dcache.demand_accesses 2050 # Number of cache demand accesses +system.ruby.l1_cntrl0.L1Icache.demand_hits 5767 # Number of cache demand hits system.ruby.l1_cntrl0.L1Icache.demand_misses 646 # Number of cache demand misses -system.ruby.l1_cntrl0.L1Icache.demand_accesses 6400 # Number of cache demand accesses +system.ruby.l1_cntrl0.L1Icache.demand_accesses 6413 # Number of cache demand accesses system.ruby.l1_cntrl0.L2cache.demand_hits 203 # Number of cache demand hits -system.ruby.l1_cntrl0.L2cache.demand_misses 1159 # Number of cache demand misses -system.ruby.l1_cntrl0.L2cache.demand_accesses 1362 # Number of cache demand accesses +system.ruby.l1_cntrl0.L2cache.demand_misses 1160 # Number of cache demand misses +system.ruby.l1_cntrl0.L2cache.demand_accesses 1363 # Number of cache demand accesses system.ruby.l1_cntrl0.fully_busy_cycles 7 # cycles for which number of transistions == max transitions system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.ruby.network.routers0.percent_links_utilized 5.174045 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100.00% | 0 0.00% 100.00% -system.ruby.LD.miss_latency_hist_seqr::total 420 +system.ruby.LD.miss_latency_hist_seqr::samples 421 +system.ruby.LD.miss_latency_hist_seqr::mean 56.707838 +system.ruby.LD.miss_latency_hist_seqr::gmean 52.779793 +system.ruby.LD.miss_latency_hist_seqr::stdev 25.484779 +system.ruby.LD.miss_latency_hist_seqr | 89 21.14% 21.14% | 244 57.96% 79.10% | 84 19.95% 99.05% | 1 0.24% 99.29% | 0 0.00% 99.29% | 0 0.00% 99.29% | 0 0.00% 99.29% | 0 0.00% 99.29% | 1 0.24% 99.52% | 2 0.48% 100.00% +system.ruby.LD.miss_latency_hist_seqr::total 421 system.ruby.ST.latency_hist_seqr::bucket_size 16 system.ruby.ST.latency_hist_seqr::max_bucket 159 system.ruby.ST.latency_hist_seqr::samples 865 @@ -556,35 +556,35 @@ system.ruby.ST.miss_latency_hist_seqr | 0 0.00% 0.00% | system.ruby.ST.miss_latency_hist_seqr::total 158 system.ruby.IFETCH.latency_hist_seqr::bucket_size 64 system.ruby.IFETCH.latency_hist_seqr::max_bucket 639 -system.ruby.IFETCH.latency_hist_seqr::samples 6400 -system.ruby.IFETCH.latency_hist_seqr::mean 6.828750 -system.ruby.IFETCH.latency_hist_seqr::gmean 1.489407 -system.ruby.IFETCH.latency_hist_seqr::stdev 20.190166 -system.ruby.IFETCH.latency_hist_seqr | 6294 98.34% 98.34% | 97 1.52% 99.86% | 0 0.00% 99.86% | 2 0.03% 99.89% | 5 0.08% 99.97% | 2 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.latency_hist_seqr::total 6400 +system.ruby.IFETCH.latency_hist_seqr::samples 6413 +system.ruby.IFETCH.latency_hist_seqr::mean 6.780914 +system.ruby.IFETCH.latency_hist_seqr::gmean 1.487888 +system.ruby.IFETCH.latency_hist_seqr::stdev 19.876102 +system.ruby.IFETCH.latency_hist_seqr | 6306 98.33% 98.33% | 100 1.56% 99.89% | 0 0.00% 99.89% | 1 0.02% 99.91% | 4 0.06% 99.97% | 2 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.latency_hist_seqr::total 6413 system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 2 system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 19 -system.ruby.IFETCH.hit_latency_hist_seqr::samples 5819 -system.ruby.IFETCH.hit_latency_hist_seqr::mean 1.111703 -system.ruby.IFETCH.hit_latency_hist_seqr::gmean 1.027147 -system.ruby.IFETCH.hit_latency_hist_seqr::stdev 1.051067 -system.ruby.IFETCH.hit_latency_hist_seqr | 5754 98.88% 98.88% | 0 0.00% 98.88% | 0 0.00% 98.88% | 0 0.00% 98.88% | 0 0.00% 98.88% | 65 1.12% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.hit_latency_hist_seqr::total 5819 +system.ruby.IFETCH.hit_latency_hist_seqr::samples 5832 +system.ruby.IFETCH.hit_latency_hist_seqr::mean 1.111454 +system.ruby.IFETCH.hit_latency_hist_seqr::gmean 1.027086 +system.ruby.IFETCH.hit_latency_hist_seqr::stdev 1.049908 +system.ruby.IFETCH.hit_latency_hist_seqr | 5767 98.89% 98.89% | 0 0.00% 98.89% | 0 0.00% 98.89% | 0 0.00% 98.89% | 0 0.00% 98.89% | 65 1.11% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.hit_latency_hist_seqr::total 5832 system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 64 system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 639 system.ruby.IFETCH.miss_latency_hist_seqr::samples 581 -system.ruby.IFETCH.miss_latency_hist_seqr::mean 64.087780 -system.ruby.IFETCH.miss_latency_hist_seqr::gmean 61.562973 -system.ruby.IFETCH.miss_latency_hist_seqr::stdev 29.566480 -system.ruby.IFETCH.miss_latency_hist_seqr | 475 81.76% 81.76% | 97 16.70% 98.45% | 0 0.00% 98.45% | 2 0.34% 98.80% | 5 0.86% 99.66% | 2 0.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.miss_latency_hist_seqr::mean 63.690189 +system.ruby.IFETCH.miss_latency_hist_seqr::gmean 61.418649 +system.ruby.IFETCH.miss_latency_hist_seqr::stdev 28.087678 +system.ruby.IFETCH.miss_latency_hist_seqr | 474 81.58% 81.58% | 100 17.21% 98.80% | 0 0.00% 98.80% | 1 0.17% 98.97% | 4 0.69% 99.66% | 2 0.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.miss_latency_hist_seqr::total 581 system.ruby.L1Cache.hit_mach_latency_hist_seqr::bucket_size 1 system.ruby.L1Cache.hit_mach_latency_hist_seqr::max_bucket 9 -system.ruby.L1Cache.hit_mach_latency_hist_seqr::samples 7086 +system.ruby.L1Cache.hit_mach_latency_hist_seqr::samples 7100 system.ruby.L1Cache.hit_mach_latency_hist_seqr::mean 1 system.ruby.L1Cache.hit_mach_latency_hist_seqr::gmean 1 -system.ruby.L1Cache.hit_mach_latency_hist_seqr | 0 0.00% 0.00% | 7086 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache.hit_mach_latency_hist_seqr::total 7086 +system.ruby.L1Cache.hit_mach_latency_hist_seqr | 0 0.00% 0.00% | 7100 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache.hit_mach_latency_hist_seqr::total 7100 system.ruby.L2Cache.hit_mach_latency_hist_seqr::bucket_size 2 system.ruby.L2Cache.hit_mach_latency_hist_seqr::max_bucket 19 system.ruby.L2Cache.hit_mach_latency_hist_seqr::samples 203 @@ -594,12 +594,12 @@ system.ruby.L2Cache.hit_mach_latency_hist_seqr | 0 0.00% 0.0 system.ruby.L2Cache.hit_mach_latency_hist_seqr::total 203 system.ruby.Directory.miss_mach_latency_hist_seqr::bucket_size 64 system.ruby.Directory.miss_mach_latency_hist_seqr::max_bucket 639 -system.ruby.Directory.miss_mach_latency_hist_seqr::samples 1159 -system.ruby.Directory.miss_mach_latency_hist_seqr::mean 59.452977 -system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 56.282360 -system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 25.811948 -system.ruby.Directory.miss_mach_latency_hist_seqr | 927 79.98% 79.98% | 221 19.07% 99.05% | 0 0.00% 99.05% | 3 0.26% 99.31% | 6 0.52% 99.83% | 2 0.17% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_mach_latency_hist_seqr::total 1159 +system.ruby.Directory.miss_mach_latency_hist_seqr::samples 1160 +system.ruby.Directory.miss_mach_latency_hist_seqr::mean 59.460345 +system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 56.276317 +system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 26.160126 +system.ruby.Directory.miss_mach_latency_hist_seqr | 928 80.00% 80.00% | 222 19.14% 99.14% | 0 0.00% 99.14% | 1 0.09% 99.22% | 7 0.60% 99.83% | 2 0.17% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_mach_latency_hist_seqr::total 1160 system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::bucket_size 1 system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::max_bucket 9 system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::samples 1 @@ -628,11 +628,11 @@ system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion | system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::total 1 system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::bucket_size 1 system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::max_bucket 9 -system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::samples 658 +system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::samples 659 system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::mean 1 system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::gmean 1 -system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 658 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::total 658 +system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 659 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::total 659 system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::bucket_size 2 system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::max_bucket 19 system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::samples 105 @@ -642,12 +642,12 @@ system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr | 0 0.00% system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::total 105 system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size 32 system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket 319 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples 420 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 56.130952 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 52.616261 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 21.748058 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 89 21.19% 21.19% | 242 57.62% 78.81% | 85 20.24% 99.05% | 2 0.48% 99.52% | 0 0.00% 99.52% | 0 0.00% 99.52% | 0 0.00% 99.52% | 1 0.24% 99.76% | 1 0.24% 100.00% | 0 0.00% 100.00% -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total 420 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples 421 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 56.707838 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 52.779793 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 25.484779 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 89 21.14% 21.14% | 244 57.96% 79.10% | 84 19.95% 99.05% | 1 0.24% 99.29% | 0 0.00% 99.29% | 0 0.00% 99.29% | 0 0.00% 99.29% | 0 0.00% 99.29% | 1 0.24% 99.52% | 2 0.48% 100.00% +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total 421 system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::bucket_size 1 system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::max_bucket 9 system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::samples 674 @@ -672,11 +672,11 @@ system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 0 0.0 system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total 158 system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::bucket_size 1 system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::max_bucket 9 -system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::samples 5754 +system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::samples 5767 system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::mean 1 system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::gmean 1 -system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 5754 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::total 5754 +system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 5767 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::total 5767 system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::bucket_size 2 system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::max_bucket 19 system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::samples 65 @@ -687,48 +687,48 @@ system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::total 65 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::samples 581 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 64.087780 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 61.562973 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 29.566480 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 475 81.76% 81.76% | 97 16.70% 98.45% | 0 0.00% 98.45% | 2 0.34% 98.80% | 5 0.86% 99.66% | 2 0.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 63.690189 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 61.418649 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 28.087678 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 474 81.58% 81.58% | 100 17.21% 98.80% | 0 0.00% 98.80% | 1 0.17% 98.97% | 4 0.69% 99.66% | 2 0.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::total 581 system.ruby.Directory_Controller.GETX 185 0.00% 0.00% -system.ruby.Directory_Controller.GETS 1020 0.00% 0.00% -system.ruby.Directory_Controller.PUT 1143 0.00% 0.00% -system.ruby.Directory_Controller.UnblockM 1158 0.00% 0.00% -system.ruby.Directory_Controller.Writeback_Exclusive_Clean 923 0.00% 0.00% +system.ruby.Directory_Controller.GETS 1021 0.00% 0.00% +system.ruby.Directory_Controller.PUT 1144 0.00% 0.00% +system.ruby.Directory_Controller.UnblockM 1159 0.00% 0.00% +system.ruby.Directory_Controller.Writeback_Exclusive_Clean 924 0.00% 0.00% system.ruby.Directory_Controller.Writeback_Exclusive_Dirty 220 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 1159 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 1160 0.00% 0.00% system.ruby.Directory_Controller.Memory_Ack 220 0.00% 0.00% -system.ruby.Directory_Controller.NO.PUT 1143 0.00% 0.00% +system.ruby.Directory_Controller.NO.PUT 1144 0.00% 0.00% system.ruby.Directory_Controller.E.GETX 158 0.00% 0.00% -system.ruby.Directory_Controller.E.GETS 1001 0.00% 0.00% -system.ruby.Directory_Controller.NO_B.UnblockM 1158 0.00% 0.00% -system.ruby.Directory_Controller.NO_B_W.Memory_Data 1159 0.00% 0.00% +system.ruby.Directory_Controller.E.GETS 1002 0.00% 0.00% +system.ruby.Directory_Controller.NO_B.UnblockM 1159 0.00% 0.00% +system.ruby.Directory_Controller.NO_B_W.Memory_Data 1160 0.00% 0.00% system.ruby.Directory_Controller.WB.GETX 27 0.00% 0.00% system.ruby.Directory_Controller.WB.GETS 19 0.00% 0.00% -system.ruby.Directory_Controller.WB.Writeback_Exclusive_Clean 923 0.00% 0.00% +system.ruby.Directory_Controller.WB.Writeback_Exclusive_Clean 924 0.00% 0.00% system.ruby.Directory_Controller.WB.Writeback_Exclusive_Dirty 220 0.00% 0.00% system.ruby.Directory_Controller.WB_E_W.Memory_Ack 220 0.00% 0.00% -system.ruby.L1Cache_Controller.Load 1191 0.00% 0.00% -system.ruby.L1Cache_Controller.Ifetch 6411 0.00% 0.00% +system.ruby.L1Cache_Controller.Load 1193 0.00% 0.00% +system.ruby.L1Cache_Controller.Ifetch 6424 0.00% 0.00% system.ruby.L1Cache_Controller.Store 892 0.00% 0.00% -system.ruby.L1Cache_Controller.L2_Replacement 1143 0.00% 0.00% -system.ruby.L1Cache_Controller.L1_to_L2 1354 0.00% 0.00% +system.ruby.L1Cache_Controller.L2_Replacement 1144 0.00% 0.00% +system.ruby.L1Cache_Controller.L1_to_L2 1355 0.00% 0.00% system.ruby.L1Cache_Controller.Trigger_L2_to_L1D 138 0.00% 0.00% system.ruby.L1Cache_Controller.Trigger_L2_to_L1I 65 0.00% 0.00% system.ruby.L1Cache_Controller.Complete_L2_to_L1 203 0.00% 0.00% -system.ruby.L1Cache_Controller.Exclusive_Data 1159 0.00% 0.00% -system.ruby.L1Cache_Controller.Writeback_Ack 1143 0.00% 0.00% -system.ruby.L1Cache_Controller.All_acks_no_sharers 1159 0.00% 0.00% -system.ruby.L1Cache_Controller.I.Load 420 0.00% 0.00% +system.ruby.L1Cache_Controller.Exclusive_Data 1160 0.00% 0.00% +system.ruby.L1Cache_Controller.Writeback_Ack 1144 0.00% 0.00% +system.ruby.L1Cache_Controller.All_acks_no_sharers 1160 0.00% 0.00% +system.ruby.L1Cache_Controller.I.Load 421 0.00% 0.00% system.ruby.L1Cache_Controller.I.Ifetch 581 0.00% 0.00% system.ruby.L1Cache_Controller.I.Store 158 0.00% 0.00% -system.ruby.L1Cache_Controller.M.Load 304 0.00% 0.00% -system.ruby.L1Cache_Controller.M.Ifetch 5754 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Load 305 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Ifetch 5767 0.00% 0.00% system.ruby.L1Cache_Controller.M.Store 60 0.00% 0.00% -system.ruby.L1Cache_Controller.M.L2_Replacement 923 0.00% 0.00% -system.ruby.L1Cache_Controller.M.L1_to_L2 1061 0.00% 0.00% +system.ruby.L1Cache_Controller.M.L2_Replacement 924 0.00% 0.00% +system.ruby.L1Cache_Controller.M.L1_to_L2 1062 0.00% 0.00% system.ruby.L1Cache_Controller.M.Trigger_L2_to_L1D 68 0.00% 0.00% system.ruby.L1Cache_Controller.M.Trigger_L2_to_L1I 65 0.00% 0.00% system.ruby.L1Cache_Controller.MM.Load 354 0.00% 0.00% @@ -742,13 +742,13 @@ system.ruby.L1Cache_Controller.MR.Store 6 0.00% 0.00% system.ruby.L1Cache_Controller.MMR.Load 43 0.00% 0.00% system.ruby.L1Cache_Controller.MMR.Store 27 0.00% 0.00% system.ruby.L1Cache_Controller.IM.Exclusive_Data 158 0.00% 0.00% -system.ruby.L1Cache_Controller.M_W.All_acks_no_sharers 1001 0.00% 0.00% +system.ruby.L1Cache_Controller.M_W.All_acks_no_sharers 1002 0.00% 0.00% system.ruby.L1Cache_Controller.MM_W.All_acks_no_sharers 158 0.00% 0.00% -system.ruby.L1Cache_Controller.IS.Exclusive_Data 1001 0.00% 0.00% +system.ruby.L1Cache_Controller.IS.Exclusive_Data 1002 0.00% 0.00% system.ruby.L1Cache_Controller.MI.Load 8 0.00% 0.00% system.ruby.L1Cache_Controller.MI.Ifetch 11 0.00% 0.00% system.ruby.L1Cache_Controller.MI.Store 27 0.00% 0.00% -system.ruby.L1Cache_Controller.MI.Writeback_Ack 1143 0.00% 0.00% +system.ruby.L1Cache_Controller.MI.Writeback_Ack 1144 0.00% 0.00% system.ruby.L1Cache_Controller.MT.Complete_L2_to_L1 133 0.00% 0.00% system.ruby.L1Cache_Controller.MMT.Complete_L2_to_L1 70 0.00% 0.00% diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini index 7cbd97c4b..b3071363a 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini @@ -120,7 +120,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello +executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin kvmInSE=false diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simout b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simout index 925eb0bfe..9c35f4885 100755 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simout +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simout @@ -1,13 +1,15 @@ +Redirecting stdout to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby/simout +Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 21 2016 13:49:21 -gem5 started Jan 21 2016 13:50:00 -gem5 executing on zizzer, pid 33967 -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby +gem5 compiled Mar 14 2016 21:54:46 +gem5 started Mar 14 2016 21:55:58 +gem5 executing on phenom, pid 28070 +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 107210 because target called exit() +Exiting @ tick 107065 because target called exit() diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt index cf623ae19..0d68fa8cb 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt @@ -1,94 +1,94 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000107 # Number of seconds simulated -sim_ticks 107210 # Number of ticks simulated -final_tick 107210 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 107065 # Number of ticks simulated +final_tick 107065 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 108799 # Simulator instruction rate (inst/s) -host_op_rate 108769 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1824399 # Simulator tick rate (ticks/s) -host_mem_usage 416280 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host -sim_insts 6390 # Number of instructions simulated -sim_ops 6390 # Number of ops (including micro ops) simulated +host_inst_rate 18652 # Simulator instruction rate (inst/s) +host_op_rate 18652 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 311861 # Simulator tick rate (ticks/s) +host_mem_usage 390536 # Number of bytes of host memory used +host_seconds 0.34 # Real time elapsed on the host +sim_insts 6403 # Number of instructions simulated +sim_ops 6403 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks -system.mem_ctrls.bytes_read::ruby.dir_cntrl0 110720 # Number of bytes read from this memory -system.mem_ctrls.bytes_read::total 110720 # Number of bytes read from this memory -system.mem_ctrls.bytes_written::ruby.dir_cntrl0 110464 # Number of bytes written to this memory -system.mem_ctrls.bytes_written::total 110464 # Number of bytes written to this memory -system.mem_ctrls.num_reads::ruby.dir_cntrl0 1730 # Number of read requests responded to by this memory -system.mem_ctrls.num_reads::total 1730 # Number of read requests responded to by this memory -system.mem_ctrls.num_writes::ruby.dir_cntrl0 1726 # Number of write requests responded to by this memory -system.mem_ctrls.num_writes::total 1726 # Number of write requests responded to by this memory -system.mem_ctrls.bw_read::ruby.dir_cntrl0 1032739483 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_read::total 1032739483 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::ruby.dir_cntrl0 1030351646 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::total 1030351646 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_total::ruby.dir_cntrl0 2063091130 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.bw_total::total 2063091130 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.readReqs 1730 # Number of read requests accepted -system.mem_ctrls.writeReqs 1726 # Number of write requests accepted -system.mem_ctrls.readBursts 1730 # Number of DRAM read bursts, including those serviced by the write queue -system.mem_ctrls.writeBursts 1726 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrls.bytesReadDRAM 56896 # Total number of bytes read from DRAM -system.mem_ctrls.bytesReadWrQ 53824 # Total number of bytes read from write queue -system.mem_ctrls.bytesWritten 56448 # Total number of bytes written to DRAM -system.mem_ctrls.bytesReadSys 110720 # Total read bytes from the system interface side -system.mem_ctrls.bytesWrittenSys 110464 # Total written bytes from the system interface side -system.mem_ctrls.servicedByWrQ 841 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrls.mergedWrBursts 814 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.bytes_read::ruby.dir_cntrl0 110784 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 110784 # Number of bytes read from this memory +system.mem_ctrls.bytes_written::ruby.dir_cntrl0 110528 # Number of bytes written to this memory +system.mem_ctrls.bytes_written::total 110528 # Number of bytes written to this memory +system.mem_ctrls.num_reads::ruby.dir_cntrl0 1731 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 1731 # Number of read requests responded to by this memory +system.mem_ctrls.num_writes::ruby.dir_cntrl0 1727 # Number of write requests responded to by this memory +system.mem_ctrls.num_writes::total 1727 # Number of write requests responded to by this memory +system.mem_ctrls.bw_read::ruby.dir_cntrl0 1034735908 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 1034735908 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::ruby.dir_cntrl0 1032344837 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::total 1032344837 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::ruby.dir_cntrl0 2067080745 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 2067080745 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.readReqs 1731 # Number of read requests accepted +system.mem_ctrls.writeReqs 1727 # Number of write requests accepted +system.mem_ctrls.readBursts 1731 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 1727 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.bytesReadDRAM 56512 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 54272 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 57856 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 110784 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 110528 # Total written bytes from the system interface side +system.mem_ctrls.servicedByWrQ 848 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 792 # Number of DRAM write bursts merged with an existing one system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.mem_ctrls.perBankRdBursts::0 82 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::1 48 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::2 85 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::3 66 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::4 116 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::5 24 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::0 85 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 47 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 74 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 68 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 112 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 23 # Per bank write bursts system.mem_ctrls.perBankRdBursts::6 1 # Per bank write bursts system.mem_ctrls.perBankRdBursts::7 3 # Per bank write bursts system.mem_ctrls.perBankRdBursts::8 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::9 1 # Per bank write bursts system.mem_ctrls.perBankRdBursts::10 49 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::11 31 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::12 19 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::13 266 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 33 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::12 17 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 263 # Per bank write bursts system.mem_ctrls.perBankRdBursts::14 79 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::15 19 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::0 81 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::1 49 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::2 85 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::3 62 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::4 126 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::5 27 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::15 28 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 83 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 47 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 80 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 68 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 133 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 25 # Per bank write bursts system.mem_ctrls.perBankWrBursts::6 1 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::7 3 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 4 # Per bank write bursts system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::9 1 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::10 44 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::11 29 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::12 13 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::13 262 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::14 79 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::15 20 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 46 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::11 28 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::12 11 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 268 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 81 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::15 28 # Per bank write bursts system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrls.totGap 107138 # Total gap between requests +system.mem_ctrls.totGap 106993 # Total gap between requests system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::6 1730 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 1731 # Read request sizes (log2) system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::6 1726 # Write request sizes (log2) -system.mem_ctrls.rdQLenPdf::0 889 # What read queue length does an incoming req see +system.mem_ctrls.writePktSize::6 1727 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 883 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see @@ -135,25 +135,25 @@ system.mem_ctrls.wrQLenPdf::11 1 # Wh system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::15 8 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::16 8 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::17 52 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::18 56 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::19 57 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::20 57 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 9 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 10 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 50 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 57 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 60 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 61 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::21 57 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::22 55 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::23 55 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::24 55 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::25 55 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::26 55 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::27 55 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::28 55 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::29 55 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::30 54 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::31 54 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::32 54 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 56 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 57 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::24 56 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 56 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 56 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 56 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::28 56 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 56 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 56 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 55 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::32 55 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::33 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see @@ -184,110 +184,110 @@ system.mem_ctrls.wrQLenPdf::60 0 # Wh system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrls.bytesPerActivate::samples 253 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::mean 437.122530 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::gmean 269.105572 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::stdev 371.515393 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::0-127 63 24.90% 24.90% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::128-255 51 20.16% 45.06% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::256-383 24 9.49% 54.55% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::384-511 18 7.11% 61.66% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::512-639 14 5.53% 67.19% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::640-767 10 3.95% 71.15% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::768-895 18 7.11% 78.26% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::896-1023 10 3.95% 82.21% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::1024-1151 45 17.79% 100.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::total 253 # Bytes accessed per row activation -system.mem_ctrls.rdPerTurnAround::samples 54 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::mean 16.203704 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::gmean 16.028046 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::stdev 2.999243 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::12-13 1 1.85% 1.85% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::14-15 20 37.04% 38.89% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::16-17 27 50.00% 88.89% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::18-19 4 7.41% 96.30% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::20-21 1 1.85% 98.15% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::36-37 1 1.85% 100.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::total 54 # Reads before turning the bus around for writes -system.mem_ctrls.wrPerTurnAround::samples 54 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::mean 16.333333 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::gmean 16.311361 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::stdev 0.890198 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::16 47 87.04% 87.04% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::18 3 5.56% 92.59% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::19 4 7.41% 100.00% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::total 54 # Writes before turning the bus around for reads -system.mem_ctrls.totQLat 10919 # Total ticks spent queuing -system.mem_ctrls.totMemAccLat 27810 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrls.totBusLat 4445 # Total ticks spent in databus transfers -system.mem_ctrls.avgQLat 12.28 # Average queueing delay per DRAM burst +system.mem_ctrls.bytesPerActivate::samples 275 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 406.341818 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 258.682678 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 357.059585 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 55 20.00% 20.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 74 26.91% 46.91% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 37 13.45% 60.36% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 16 5.82% 66.18% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 18 6.55% 72.73% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 12 4.36% 77.09% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 8 2.91% 80.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 6 2.18% 82.18% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 49 17.82% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 275 # Bytes accessed per row activation +system.mem_ctrls.rdPerTurnAround::samples 55 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::mean 15.781818 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::gmean 15.596648 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::stdev 2.973282 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::12-13 4 7.27% 7.27% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::14-15 25 45.45% 52.73% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::16-17 21 38.18% 90.91% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::18-19 4 7.27% 98.18% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::34-35 1 1.82% 100.00% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::total 55 # Reads before turning the bus around for writes +system.mem_ctrls.wrPerTurnAround::samples 55 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::mean 16.436364 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::gmean 16.408895 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::stdev 0.995613 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::16 45 81.82% 81.82% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::17 2 3.64% 85.45% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::18 2 3.64% 89.09% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::19 6 10.91% 100.00% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::total 55 # Writes before turning the bus around for reads +system.mem_ctrls.totQLat 10887 # Total ticks spent queuing +system.mem_ctrls.totMemAccLat 27664 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.totBusLat 4415 # Total ticks spent in databus transfers +system.mem_ctrls.avgQLat 12.33 # Average queueing delay per DRAM burst system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst -system.mem_ctrls.avgMemAccLat 31.28 # Average memory access latency per DRAM burst -system.mem_ctrls.avgRdBW 530.70 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrls.avgWrBW 526.52 # Average achieved write bandwidth in MiByte/s -system.mem_ctrls.avgRdBWSys 1032.74 # Average system read bandwidth in MiByte/s -system.mem_ctrls.avgWrBWSys 1030.35 # Average system write bandwidth in MiByte/s +system.mem_ctrls.avgMemAccLat 31.33 # Average memory access latency per DRAM burst +system.mem_ctrls.avgRdBW 527.83 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 540.38 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 1034.74 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 1032.34 # Average system write bandwidth in MiByte/s system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrls.busUtil 8.26 # Data bus utilization in percentage -system.mem_ctrls.busUtilRead 4.15 # Data bus utilization in percentage for reads -system.mem_ctrls.busUtilWrite 4.11 # Data bus utilization in percentage for writes +system.mem_ctrls.busUtil 8.35 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 4.12 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 4.22 # Data bus utilization in percentage for writes system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing -system.mem_ctrls.avgWrQLen 25.52 # Average write queue length when enqueuing -system.mem_ctrls.readRowHits 682 # Number of row buffer hits during reads -system.mem_ctrls.writeRowHits 829 # Number of row buffer hits during writes -system.mem_ctrls.readRowHitRate 76.72 # Row buffer hit rate for reads -system.mem_ctrls.writeRowHitRate 90.90 # Row buffer hit rate for writes -system.mem_ctrls.avgGap 31.00 # Average gap between requests -system.mem_ctrls.pageHitRate 83.90 # Row buffer hit rate, read and write combined -system.mem_ctrls_0.actEnergy 748440 # Energy for activate commands per rank (pJ) -system.mem_ctrls_0.preEnergy 415800 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_0.readEnergy 5166720 # Energy for read commands per rank (pJ) -system.mem_ctrls_0.writeEnergy 4447872 # Energy for write commands per rank (pJ) +system.mem_ctrls.avgWrQLen 26.13 # Average write queue length when enqueuing +system.mem_ctrls.readRowHits 670 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 835 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 75.88 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate 89.30 # Row buffer hit rate for writes +system.mem_ctrls.avgGap 30.94 # Average gap between requests +system.mem_ctrls.pageHitRate 82.78 # Row buffer hit rate, read and write combined +system.mem_ctrls_0.actEnergy 876960 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 487200 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 4992000 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 4489344 # Energy for write commands per rank (pJ) system.mem_ctrls_0.refreshEnergy 6611280 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_0.actBackEnergy 64735128 # Energy for active background per rank (pJ) -system.mem_ctrls_0.preBackEnergy 4101600 # Energy for precharge background per rank (pJ) -system.mem_ctrls_0.totalEnergy 86226840 # Total energy per rank (pJ) -system.mem_ctrls_0.averagePower 849.709691 # Core power per rank (mW) -system.mem_ctrls_0.memoryStateTime::IDLE 7218 # Time in different power states +system.mem_ctrls_0.actBackEnergy 63943740 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 4795800 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.totalEnergy 86196324 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 849.408975 # Core power per rank (mW) +system.mem_ctrls_0.memoryStateTime::IDLE 8418 # Time in different power states system.mem_ctrls_0.memoryStateTime::REF 3380 # Time in different power states system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT 91640 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 90483 # Time in different power states system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrls_1.actEnergy 1088640 # Energy for activate commands per rank (pJ) -system.mem_ctrls_1.preEnergy 604800 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_1.readEnergy 5241600 # Energy for read commands per rank (pJ) -system.mem_ctrls_1.writeEnergy 4167936 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.actEnergy 1156680 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 642600 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 5366400 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 4385664 # Energy for write commands per rank (pJ) system.mem_ctrls_1.refreshEnergy 6611280 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_1.actBackEnergy 64577808 # Energy for active background per rank (pJ) -system.mem_ctrls_1.preBackEnergy 4239600 # Energy for precharge background per rank (pJ) -system.mem_ctrls_1.totalEnergy 86531664 # Total energy per rank (pJ) -system.mem_ctrls_1.averagePower 852.713534 # Core power per rank (mW) -system.mem_ctrls_1.memoryStateTime::IDLE 6460 # Time in different power states +system.mem_ctrls_1.actBackEnergy 65375352 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 3540000 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.totalEnergy 87077976 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 858.097085 # Core power per rank (mW) +system.mem_ctrls_1.memoryStateTime::IDLE 5471 # Time in different power states system.mem_ctrls_1.memoryStateTime::REF 3380 # Time in different power states system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT 91652 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 92641 # Time in different power states system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.clk_domain.clock 1 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 1183 # DTB read hits +system.cpu.dtb.read_hits 1185 # DTB read hits system.cpu.dtb.read_misses 7 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 1190 # DTB read accesses +system.cpu.dtb.read_accesses 1192 # DTB read accesses system.cpu.dtb.write_hits 865 # DTB write hits system.cpu.dtb.write_misses 3 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations system.cpu.dtb.write_accesses 868 # DTB write accesses -system.cpu.dtb.data_hits 2048 # DTB hits +system.cpu.dtb.data_hits 2050 # DTB hits system.cpu.dtb.data_misses 10 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 2058 # DTB accesses -system.cpu.itb.fetch_hits 6401 # ITB hits +system.cpu.dtb.data_accesses 2060 # DTB accesses +system.cpu.itb.fetch_hits 6414 # ITB hits system.cpu.itb.fetch_misses 17 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 6418 # ITB accesses +system.cpu.itb.fetch_accesses 6431 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -301,210 +301,210 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 107210 # number of cpu cycles simulated +system.cpu.numCycles 107065 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 6390 # Number of instructions committed -system.cpu.committedOps 6390 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 6317 # Number of integer alu accesses +system.cpu.committedInsts 6403 # Number of instructions committed +system.cpu.committedOps 6403 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 6329 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses system.cpu.num_func_calls 251 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 749 # number of instructions that are conditional controls -system.cpu.num_int_insts 6317 # number of integer instructions +system.cpu.num_conditional_control_insts 754 # number of instructions that are conditional controls +system.cpu.num_int_insts 6329 # number of integer instructions system.cpu.num_fp_insts 10 # number of float instructions -system.cpu.num_int_register_reads 8285 # number of times the integer registers were read -system.cpu.num_int_register_writes 4568 # number of times the integer registers were written +system.cpu.num_int_register_reads 8297 # number of times the integer registers were read +system.cpu.num_int_register_writes 4575 # number of times the integer registers were written system.cpu.num_fp_register_reads 8 # number of times the floating registers were read system.cpu.num_fp_register_writes 2 # number of times the floating registers were written -system.cpu.num_mem_refs 2058 # number of memory refs -system.cpu.num_load_insts 1190 # Number of load instructions +system.cpu.num_mem_refs 2060 # number of memory refs +system.cpu.num_load_insts 1192 # Number of load instructions system.cpu.num_store_insts 868 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 107210 # Number of busy cycles +system.cpu.num_busy_cycles 107065 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 1050 # Number of branches fetched +system.cpu.Branches 1056 # Number of branches fetched system.cpu.op_class::No_OpClass 19 0.30% 0.30% # Class of executed instruction -system.cpu.op_class::IntAlu 4320 67.50% 67.80% # Class of executed instruction -system.cpu.op_class::IntMult 1 0.02% 67.81% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 67.81% # Class of executed instruction -system.cpu.op_class::FloatAdd 2 0.03% 67.84% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::MemRead 1190 18.59% 86.44% # Class of executed instruction -system.cpu.op_class::MemWrite 868 13.56% 100.00% # Class of executed instruction +system.cpu.op_class::IntAlu 4331 67.53% 67.83% # Class of executed instruction +system.cpu.op_class::IntMult 1 0.02% 67.85% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 67.85% # Class of executed instruction +system.cpu.op_class::FloatAdd 2 0.03% 67.88% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::MemRead 1192 18.59% 86.46% # Class of executed instruction +system.cpu.op_class::MemWrite 868 13.54% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 6400 # Class of executed instruction +system.cpu.op_class::total 6413 # Class of executed instruction system.ruby.clk_domain.clock 1 # Clock period in ticks system.ruby.delayHist::bucket_size 1 # delay histogram for all message system.ruby.delayHist::max_bucket 9 # delay histogram for all message -system.ruby.delayHist::samples 3456 # delay histogram for all message -system.ruby.delayHist | 3456 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message -system.ruby.delayHist::total 3456 # delay histogram for all message +system.ruby.delayHist::samples 3458 # delay histogram for all message +system.ruby.delayHist | 3458 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message +system.ruby.delayHist::total 3458 # delay histogram for all message system.ruby.outstanding_req_hist_seqr::bucket_size 1 system.ruby.outstanding_req_hist_seqr::max_bucket 9 -system.ruby.outstanding_req_hist_seqr::samples 8449 +system.ruby.outstanding_req_hist_seqr::samples 8464 system.ruby.outstanding_req_hist_seqr::mean 1 system.ruby.outstanding_req_hist_seqr::gmean 1 -system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 8449 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.outstanding_req_hist_seqr::total 8449 +system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 8464 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist_seqr::total 8464 system.ruby.latency_hist_seqr::bucket_size 64 system.ruby.latency_hist_seqr::max_bucket 639 -system.ruby.latency_hist_seqr::samples 8448 -system.ruby.latency_hist_seqr::mean 11.690578 -system.ruby.latency_hist_seqr::gmean 2.205273 -system.ruby.latency_hist_seqr::stdev 25.830363 -system.ruby.latency_hist_seqr | 8209 97.17% 97.17% | 184 2.18% 99.35% | 38 0.45% 99.80% | 7 0.08% 99.88% | 6 0.07% 99.95% | 3 0.04% 99.99% | 0 0.00% 99.99% | 1 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.latency_hist_seqr::total 8448 +system.ruby.latency_hist_seqr::samples 8463 +system.ruby.latency_hist_seqr::mean 11.650951 +system.ruby.latency_hist_seqr::gmean 2.202191 +system.ruby.latency_hist_seqr::stdev 25.742711 +system.ruby.latency_hist_seqr | 8220 97.13% 97.13% | 190 2.25% 99.37% | 41 0.48% 99.86% | 1 0.01% 99.87% | 6 0.07% 99.94% | 4 0.05% 99.99% | 1 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.latency_hist_seqr::total 8463 system.ruby.hit_latency_hist_seqr::bucket_size 1 system.ruby.hit_latency_hist_seqr::max_bucket 9 -system.ruby.hit_latency_hist_seqr::samples 6718 +system.ruby.hit_latency_hist_seqr::samples 6732 system.ruby.hit_latency_hist_seqr::mean 1 system.ruby.hit_latency_hist_seqr::gmean 1 -system.ruby.hit_latency_hist_seqr | 0 0.00% 0.00% | 6718 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.hit_latency_hist_seqr::total 6718 +system.ruby.hit_latency_hist_seqr | 0 0.00% 0.00% | 6732 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.hit_latency_hist_seqr::total 6732 system.ruby.miss_latency_hist_seqr::bucket_size 64 system.ruby.miss_latency_hist_seqr::max_bucket 639 -system.ruby.miss_latency_hist_seqr::samples 1730 -system.ruby.miss_latency_hist_seqr::mean 53.204624 -system.ruby.miss_latency_hist_seqr::gmean 47.556283 -system.ruby.miss_latency_hist_seqr::stdev 33.032605 -system.ruby.miss_latency_hist_seqr | 1491 86.18% 86.18% | 184 10.64% 96.82% | 38 2.20% 99.02% | 7 0.40% 99.42% | 6 0.35% 99.77% | 3 0.17% 99.94% | 0 0.00% 99.94% | 1 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.miss_latency_hist_seqr::total 1730 -system.ruby.Directory.incomplete_times_seqr 1729 -system.ruby.l1_cntrl0.cacheMemory.demand_hits 6718 # Number of cache demand hits -system.ruby.l1_cntrl0.cacheMemory.demand_misses 1730 # Number of cache demand misses -system.ruby.l1_cntrl0.cacheMemory.demand_accesses 8448 # Number of cache demand accesses +system.ruby.miss_latency_hist_seqr::samples 1731 +system.ruby.miss_latency_hist_seqr::mean 53.073368 +system.ruby.miss_latency_hist_seqr::gmean 47.451096 +system.ruby.miss_latency_hist_seqr::stdev 32.911544 +system.ruby.miss_latency_hist_seqr | 1488 85.96% 85.96% | 190 10.98% 96.94% | 41 2.37% 99.31% | 1 0.06% 99.36% | 6 0.35% 99.71% | 4 0.23% 99.94% | 1 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.miss_latency_hist_seqr::total 1731 +system.ruby.Directory.incomplete_times_seqr 1730 +system.ruby.l1_cntrl0.cacheMemory.demand_hits 6732 # Number of cache demand hits +system.ruby.l1_cntrl0.cacheMemory.demand_misses 1731 # Number of cache demand misses +system.ruby.l1_cntrl0.cacheMemory.demand_accesses 8463 # Number of cache demand accesses system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.ruby.network.routers0.percent_links_utilized 8.058950 -system.ruby.network.routers0.msg_count.Control::2 1730 -system.ruby.network.routers0.msg_count.Data::2 1726 -system.ruby.network.routers0.msg_count.Response_Data::4 1730 -system.ruby.network.routers0.msg_count.Writeback_Control::3 1726 -system.ruby.network.routers0.msg_bytes.Control::2 13840 -system.ruby.network.routers0.msg_bytes.Data::2 124272 -system.ruby.network.routers0.msg_bytes.Response_Data::4 124560 -system.ruby.network.routers0.msg_bytes.Writeback_Control::3 13808 -system.ruby.network.routers1.percent_links_utilized 8.058950 -system.ruby.network.routers1.msg_count.Control::2 1730 -system.ruby.network.routers1.msg_count.Data::2 1726 -system.ruby.network.routers1.msg_count.Response_Data::4 1730 -system.ruby.network.routers1.msg_count.Writeback_Control::3 1726 -system.ruby.network.routers1.msg_bytes.Control::2 13840 -system.ruby.network.routers1.msg_bytes.Data::2 124272 -system.ruby.network.routers1.msg_bytes.Response_Data::4 124560 -system.ruby.network.routers1.msg_bytes.Writeback_Control::3 13808 -system.ruby.network.routers2.percent_links_utilized 8.058950 -system.ruby.network.routers2.msg_count.Control::2 1730 -system.ruby.network.routers2.msg_count.Data::2 1726 -system.ruby.network.routers2.msg_count.Response_Data::4 1730 -system.ruby.network.routers2.msg_count.Writeback_Control::3 1726 -system.ruby.network.routers2.msg_bytes.Control::2 13840 -system.ruby.network.routers2.msg_bytes.Data::2 124272 -system.ruby.network.routers2.msg_bytes.Response_Data::4 124560 -system.ruby.network.routers2.msg_bytes.Writeback_Control::3 13808 -system.ruby.network.msg_count.Control 5190 -system.ruby.network.msg_count.Data 5178 -system.ruby.network.msg_count.Response_Data 5190 -system.ruby.network.msg_count.Writeback_Control 5178 -system.ruby.network.msg_byte.Control 41520 -system.ruby.network.msg_byte.Data 372816 -system.ruby.network.msg_byte.Response_Data 373680 -system.ruby.network.msg_byte.Writeback_Control 41424 -system.ruby.network.routers0.throttle0.link_utilization 8.066412 -system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1730 -system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 1726 -system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 124560 -system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 13808 -system.ruby.network.routers0.throttle1.link_utilization 8.051488 -system.ruby.network.routers0.throttle1.msg_count.Control::2 1730 -system.ruby.network.routers0.throttle1.msg_count.Data::2 1726 -system.ruby.network.routers0.throttle1.msg_bytes.Control::2 13840 -system.ruby.network.routers0.throttle1.msg_bytes.Data::2 124272 -system.ruby.network.routers1.throttle0.link_utilization 8.051488 -system.ruby.network.routers1.throttle0.msg_count.Control::2 1730 -system.ruby.network.routers1.throttle0.msg_count.Data::2 1726 -system.ruby.network.routers1.throttle0.msg_bytes.Control::2 13840 -system.ruby.network.routers1.throttle0.msg_bytes.Data::2 124272 -system.ruby.network.routers1.throttle1.link_utilization 8.066412 -system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 1730 -system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 1726 -system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 124560 -system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 13808 -system.ruby.network.routers2.throttle0.link_utilization 8.066412 -system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 1730 -system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 1726 -system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 124560 -system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 13808 -system.ruby.network.routers2.throttle1.link_utilization 8.051488 -system.ruby.network.routers2.throttle1.msg_count.Control::2 1730 -system.ruby.network.routers2.throttle1.msg_count.Data::2 1726 -system.ruby.network.routers2.throttle1.msg_bytes.Control::2 13840 -system.ruby.network.routers2.throttle1.msg_bytes.Data::2 124272 +system.ruby.network.routers0.percent_links_utilized 8.074534 +system.ruby.network.routers0.msg_count.Control::2 1731 +system.ruby.network.routers0.msg_count.Data::2 1727 +system.ruby.network.routers0.msg_count.Response_Data::4 1731 +system.ruby.network.routers0.msg_count.Writeback_Control::3 1727 +system.ruby.network.routers0.msg_bytes.Control::2 13848 +system.ruby.network.routers0.msg_bytes.Data::2 124344 +system.ruby.network.routers0.msg_bytes.Response_Data::4 124632 +system.ruby.network.routers0.msg_bytes.Writeback_Control::3 13816 +system.ruby.network.routers1.percent_links_utilized 8.074534 +system.ruby.network.routers1.msg_count.Control::2 1731 +system.ruby.network.routers1.msg_count.Data::2 1727 +system.ruby.network.routers1.msg_count.Response_Data::4 1731 +system.ruby.network.routers1.msg_count.Writeback_Control::3 1727 +system.ruby.network.routers1.msg_bytes.Control::2 13848 +system.ruby.network.routers1.msg_bytes.Data::2 124344 +system.ruby.network.routers1.msg_bytes.Response_Data::4 124632 +system.ruby.network.routers1.msg_bytes.Writeback_Control::3 13816 +system.ruby.network.routers2.percent_links_utilized 8.074534 +system.ruby.network.routers2.msg_count.Control::2 1731 +system.ruby.network.routers2.msg_count.Data::2 1727 +system.ruby.network.routers2.msg_count.Response_Data::4 1731 +system.ruby.network.routers2.msg_count.Writeback_Control::3 1727 +system.ruby.network.routers2.msg_bytes.Control::2 13848 +system.ruby.network.routers2.msg_bytes.Data::2 124344 +system.ruby.network.routers2.msg_bytes.Response_Data::4 124632 +system.ruby.network.routers2.msg_bytes.Writeback_Control::3 13816 +system.ruby.network.msg_count.Control 5193 +system.ruby.network.msg_count.Data 5181 +system.ruby.network.msg_count.Response_Data 5193 +system.ruby.network.msg_count.Writeback_Control 5181 +system.ruby.network.msg_byte.Control 41544 +system.ruby.network.msg_byte.Data 373032 +system.ruby.network.msg_byte.Response_Data 373896 +system.ruby.network.msg_byte.Writeback_Control 41448 +system.ruby.network.routers0.throttle0.link_utilization 8.082006 +system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1731 +system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 1727 +system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 124632 +system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 13816 +system.ruby.network.routers0.throttle1.link_utilization 8.067062 +system.ruby.network.routers0.throttle1.msg_count.Control::2 1731 +system.ruby.network.routers0.throttle1.msg_count.Data::2 1727 +system.ruby.network.routers0.throttle1.msg_bytes.Control::2 13848 +system.ruby.network.routers0.throttle1.msg_bytes.Data::2 124344 +system.ruby.network.routers1.throttle0.link_utilization 8.067062 +system.ruby.network.routers1.throttle0.msg_count.Control::2 1731 +system.ruby.network.routers1.throttle0.msg_count.Data::2 1727 +system.ruby.network.routers1.throttle0.msg_bytes.Control::2 13848 +system.ruby.network.routers1.throttle0.msg_bytes.Data::2 124344 +system.ruby.network.routers1.throttle1.link_utilization 8.082006 +system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 1731 +system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 1727 +system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 124632 +system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 13816 +system.ruby.network.routers2.throttle0.link_utilization 8.082006 +system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 1731 +system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 1727 +system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 124632 +system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 13816 +system.ruby.network.routers2.throttle1.link_utilization 8.067062 +system.ruby.network.routers2.throttle1.msg_count.Control::2 1731 +system.ruby.network.routers2.throttle1.msg_count.Data::2 1727 +system.ruby.network.routers2.throttle1.msg_bytes.Control::2 13848 +system.ruby.network.routers2.throttle1.msg_bytes.Data::2 124344 system.ruby.delayVCHist.vnet_1::bucket_size 1 # delay histogram for vnet_1 system.ruby.delayVCHist.vnet_1::max_bucket 9 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::samples 1730 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1 | 1730 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::total 1730 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::samples 1731 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1 | 1731 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::total 1731 # delay histogram for vnet_1 system.ruby.delayVCHist.vnet_2::bucket_size 1 # delay histogram for vnet_2 system.ruby.delayVCHist.vnet_2::max_bucket 9 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::samples 1726 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2 | 1726 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::total 1726 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::samples 1727 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2 | 1727 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::total 1727 # delay histogram for vnet_2 system.ruby.LD.latency_hist_seqr::bucket_size 64 system.ruby.LD.latency_hist_seqr::max_bucket 639 -system.ruby.LD.latency_hist_seqr::samples 1183 -system.ruby.LD.latency_hist_seqr::mean 31.638208 -system.ruby.LD.latency_hist_seqr::gmean 10.419015 -system.ruby.LD.latency_hist_seqr::stdev 35.065266 -system.ruby.LD.latency_hist_seqr | 1085 91.72% 91.72% | 74 6.26% 97.97% | 18 1.52% 99.49% | 2 0.17% 99.66% | 3 0.25% 99.92% | 1 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.latency_hist_seqr::total 1183 +system.ruby.LD.latency_hist_seqr::samples 1185 +system.ruby.LD.latency_hist_seqr::mean 31.532489 +system.ruby.LD.latency_hist_seqr::gmean 10.421226 +system.ruby.LD.latency_hist_seqr::stdev 34.906160 +system.ruby.LD.latency_hist_seqr | 1091 92.07% 92.07% | 75 6.33% 98.40% | 15 1.27% 99.66% | 0 0.00% 99.66% | 2 0.17% 99.83% | 1 0.08% 99.92% | 1 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.latency_hist_seqr::total 1185 system.ruby.LD.hit_latency_hist_seqr::bucket_size 1 system.ruby.LD.hit_latency_hist_seqr::max_bucket 9 -system.ruby.LD.hit_latency_hist_seqr::samples 456 +system.ruby.LD.hit_latency_hist_seqr::samples 457 system.ruby.LD.hit_latency_hist_seqr::mean 1 system.ruby.LD.hit_latency_hist_seqr::gmean 1 -system.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 456 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.hit_latency_hist_seqr::total 456 +system.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 457 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.hit_latency_hist_seqr::total 457 system.ruby.LD.miss_latency_hist_seqr::bucket_size 64 system.ruby.LD.miss_latency_hist_seqr::max_bucket 639 -system.ruby.LD.miss_latency_hist_seqr::samples 727 -system.ruby.LD.miss_latency_hist_seqr::mean 50.855571 -system.ruby.LD.miss_latency_hist_seqr::gmean 45.315147 -system.ruby.LD.miss_latency_hist_seqr::stdev 32.287061 -system.ruby.LD.miss_latency_hist_seqr | 629 86.52% 86.52% | 74 10.18% 96.70% | 18 2.48% 99.17% | 2 0.28% 99.45% | 3 0.41% 99.86% | 1 0.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.miss_latency_hist_seqr::total 727 +system.ruby.LD.miss_latency_hist_seqr::samples 728 +system.ruby.LD.miss_latency_hist_seqr::mean 50.699176 +system.ruby.LD.miss_latency_hist_seqr::gmean 45.385232 +system.ruby.LD.miss_latency_hist_seqr::stdev 32.101179 +system.ruby.LD.miss_latency_hist_seqr | 634 87.09% 87.09% | 75 10.30% 97.39% | 15 2.06% 99.45% | 0 0.00% 99.45% | 2 0.27% 99.73% | 1 0.14% 99.86% | 1 0.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.miss_latency_hist_seqr::total 728 system.ruby.ST.latency_hist_seqr::bucket_size 32 system.ruby.ST.latency_hist_seqr::max_bucket 319 system.ruby.ST.latency_hist_seqr::samples 865 -system.ruby.ST.latency_hist_seqr::mean 16.483237 -system.ruby.ST.latency_hist_seqr::gmean 3.324735 -system.ruby.ST.latency_hist_seqr::stdev 28.016571 -system.ruby.ST.latency_hist_seqr | 592 68.44% 68.44% | 244 28.21% 96.65% | 18 2.08% 98.73% | 2 0.23% 98.96% | 5 0.58% 99.54% | 2 0.23% 99.77% | 1 0.12% 99.88% | 0 0.00% 99.88% | 1 0.12% 100.00% | 0 0.00% 100.00% +system.ruby.ST.latency_hist_seqr::mean 16.426590 +system.ruby.ST.latency_hist_seqr::gmean 3.318487 +system.ruby.ST.latency_hist_seqr::stdev 28.264983 +system.ruby.ST.latency_hist_seqr | 592 68.44% 68.44% | 242 27.98% 96.42% | 21 2.43% 98.84% | 1 0.12% 98.96% | 4 0.46% 99.42% | 4 0.46% 99.88% | 0 0.00% 99.88% | 0 0.00% 99.88% | 0 0.00% 99.88% | 1 0.12% 100.00% system.ruby.ST.latency_hist_seqr::total 865 system.ruby.ST.hit_latency_hist_seqr::bucket_size 1 system.ruby.ST.hit_latency_hist_seqr::max_bucket 9 @@ -516,42 +516,42 @@ system.ruby.ST.hit_latency_hist_seqr::total 592 system.ruby.ST.miss_latency_hist_seqr::bucket_size 32 system.ruby.ST.miss_latency_hist_seqr::max_bucket 319 system.ruby.ST.miss_latency_hist_seqr::samples 273 -system.ruby.ST.miss_latency_hist_seqr::mean 50.058608 -system.ruby.ST.miss_latency_hist_seqr::gmean 44.997273 -system.ruby.ST.miss_latency_hist_seqr::stdev 28.984216 -system.ruby.ST.miss_latency_hist_seqr | 0 0.00% 0.00% | 244 89.38% 89.38% | 18 6.59% 95.97% | 2 0.73% 96.70% | 5 1.83% 98.53% | 2 0.73% 99.27% | 1 0.37% 99.63% | 0 0.00% 99.63% | 1 0.37% 100.00% | 0 0.00% 100.00% +system.ruby.ST.miss_latency_hist_seqr::mean 49.879121 +system.ruby.ST.miss_latency_hist_seqr::gmean 44.729882 +system.ruby.ST.miss_latency_hist_seqr::stdev 29.942777 +system.ruby.ST.miss_latency_hist_seqr | 0 0.00% 0.00% | 242 88.64% 88.64% | 21 7.69% 96.34% | 1 0.37% 96.70% | 4 1.47% 98.17% | 4 1.47% 99.63% | 0 0.00% 99.63% | 0 0.00% 99.63% | 0 0.00% 99.63% | 1 0.37% 100.00% system.ruby.ST.miss_latency_hist_seqr::total 273 system.ruby.IFETCH.latency_hist_seqr::bucket_size 64 system.ruby.IFETCH.latency_hist_seqr::max_bucket 639 -system.ruby.IFETCH.latency_hist_seqr::samples 6400 -system.ruby.IFETCH.latency_hist_seqr::mean 7.355625 -system.ruby.IFETCH.latency_hist_seqr::gmean 1.565715 -system.ruby.IFETCH.latency_hist_seqr::stdev 21.264557 -system.ruby.IFETCH.latency_hist_seqr | 6288 98.25% 98.25% | 90 1.41% 99.66% | 13 0.20% 99.86% | 4 0.06% 99.92% | 2 0.03% 99.95% | 2 0.03% 99.98% | 0 0.00% 99.98% | 1 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.latency_hist_seqr::total 6400 +system.ruby.IFETCH.latency_hist_seqr::samples 6413 +system.ruby.IFETCH.latency_hist_seqr::mean 7.333073 +system.ruby.IFETCH.latency_hist_seqr::gmean 1.563492 +system.ruby.IFETCH.latency_hist_seqr::stdev 21.145733 +system.ruby.IFETCH.latency_hist_seqr | 6295 98.16% 98.16% | 93 1.45% 99.61% | 18 0.28% 99.89% | 1 0.02% 99.91% | 3 0.05% 99.95% | 3 0.05% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.latency_hist_seqr::total 6413 system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 1 system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 9 -system.ruby.IFETCH.hit_latency_hist_seqr::samples 5670 +system.ruby.IFETCH.hit_latency_hist_seqr::samples 5683 system.ruby.IFETCH.hit_latency_hist_seqr::mean 1 system.ruby.IFETCH.hit_latency_hist_seqr::gmean 1 -system.ruby.IFETCH.hit_latency_hist_seqr | 0 0.00% 0.00% | 5670 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.hit_latency_hist_seqr::total 5670 +system.ruby.IFETCH.hit_latency_hist_seqr | 0 0.00% 0.00% | 5683 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.hit_latency_hist_seqr::total 5683 system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 64 system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 639 system.ruby.IFETCH.miss_latency_hist_seqr::samples 730 -system.ruby.IFETCH.miss_latency_hist_seqr::mean 56.720548 -system.ruby.IFETCH.miss_latency_hist_seqr::gmean 50.941265 -system.ruby.IFETCH.miss_latency_hist_seqr::stdev 34.853032 -system.ruby.IFETCH.miss_latency_hist_seqr | 618 84.66% 84.66% | 90 12.33% 96.99% | 13 1.78% 98.77% | 4 0.55% 99.32% | 2 0.27% 99.59% | 2 0.27% 99.86% | 0 0.00% 99.86% | 1 0.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.miss_latency_hist_seqr::mean 56.635616 +system.ruby.IFETCH.miss_latency_hist_seqr::gmean 50.712708 +system.ruby.IFETCH.miss_latency_hist_seqr::stdev 34.440483 +system.ruby.IFETCH.miss_latency_hist_seqr | 612 83.84% 83.84% | 93 12.74% 96.58% | 18 2.47% 99.04% | 1 0.14% 99.18% | 3 0.41% 99.59% | 3 0.41% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.miss_latency_hist_seqr::total 730 system.ruby.Directory.miss_mach_latency_hist_seqr::bucket_size 64 system.ruby.Directory.miss_mach_latency_hist_seqr::max_bucket 639 -system.ruby.Directory.miss_mach_latency_hist_seqr::samples 1730 -system.ruby.Directory.miss_mach_latency_hist_seqr::mean 53.204624 -system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 47.556283 -system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 33.032605 -system.ruby.Directory.miss_mach_latency_hist_seqr | 1491 86.18% 86.18% | 184 10.64% 96.82% | 38 2.20% 99.02% | 7 0.40% 99.42% | 6 0.35% 99.77% | 3 0.17% 99.94% | 0 0.00% 99.94% | 1 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_mach_latency_hist_seqr::total 1730 +system.ruby.Directory.miss_mach_latency_hist_seqr::samples 1731 +system.ruby.Directory.miss_mach_latency_hist_seqr::mean 53.073368 +system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 47.451096 +system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 32.911544 +system.ruby.Directory.miss_mach_latency_hist_seqr | 1488 85.96% 85.96% | 190 10.98% 96.94% | 41 2.37% 99.31% | 1 0.06% 99.36% | 6 0.35% 99.71% | 4 0.23% 99.94% | 1 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_mach_latency_hist_seqr::total 1731 system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::bucket_size 1 system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::max_bucket 9 system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::samples 1 @@ -580,51 +580,51 @@ system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion | system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::total 1 system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples 727 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 50.855571 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 45.315147 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 32.287061 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 629 86.52% 86.52% | 74 10.18% 96.70% | 18 2.48% 99.17% | 2 0.28% 99.45% | 3 0.41% 99.86% | 1 0.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total 727 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples 728 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 50.699176 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 45.385232 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 32.101179 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 634 87.09% 87.09% | 75 10.30% 97.39% | 15 2.06% 99.45% | 0 0.00% 99.45% | 2 0.27% 99.73% | 1 0.14% 99.86% | 1 0.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total 728 system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size 32 system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket 319 system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::samples 273 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 50.058608 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 44.997273 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 28.984216 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 244 89.38% 89.38% | 18 6.59% 95.97% | 2 0.73% 96.70% | 5 1.83% 98.53% | 2 0.73% 99.27% | 1 0.37% 99.63% | 0 0.00% 99.63% | 1 0.37% 100.00% | 0 0.00% 100.00% +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 49.879121 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 44.729882 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 29.942777 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 242 88.64% 88.64% | 21 7.69% 96.34% | 1 0.37% 96.70% | 4 1.47% 98.17% | 4 1.47% 99.63% | 0 0.00% 99.63% | 0 0.00% 99.63% | 0 0.00% 99.63% | 1 0.37% 100.00% system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total 273 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::samples 730 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 56.720548 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 50.941265 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 34.853032 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 618 84.66% 84.66% | 90 12.33% 96.99% | 13 1.78% 98.77% | 4 0.55% 99.32% | 2 0.27% 99.59% | 2 0.27% 99.86% | 0 0.00% 99.86% | 1 0.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 56.635616 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 50.712708 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 34.440483 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 612 83.84% 83.84% | 93 12.74% 96.58% | 18 2.47% 99.04% | 1 0.14% 99.18% | 3 0.41% 99.59% | 3 0.41% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::total 730 -system.ruby.Directory_Controller.GETX 1730 0.00% 0.00% -system.ruby.Directory_Controller.PUTX 1726 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 1730 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 1726 0.00% 0.00% -system.ruby.Directory_Controller.I.GETX 1730 0.00% 0.00% -system.ruby.Directory_Controller.M.PUTX 1726 0.00% 0.00% -system.ruby.Directory_Controller.IM.Memory_Data 1730 0.00% 0.00% -system.ruby.Directory_Controller.MI.Memory_Ack 1726 0.00% 0.00% -system.ruby.L1Cache_Controller.Load 1183 0.00% 0.00% -system.ruby.L1Cache_Controller.Ifetch 6400 0.00% 0.00% +system.ruby.Directory_Controller.GETX 1731 0.00% 0.00% +system.ruby.Directory_Controller.PUTX 1727 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 1731 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 1727 0.00% 0.00% +system.ruby.Directory_Controller.I.GETX 1731 0.00% 0.00% +system.ruby.Directory_Controller.M.PUTX 1727 0.00% 0.00% +system.ruby.Directory_Controller.IM.Memory_Data 1731 0.00% 0.00% +system.ruby.Directory_Controller.MI.Memory_Ack 1727 0.00% 0.00% +system.ruby.L1Cache_Controller.Load 1185 0.00% 0.00% +system.ruby.L1Cache_Controller.Ifetch 6413 0.00% 0.00% system.ruby.L1Cache_Controller.Store 865 0.00% 0.00% -system.ruby.L1Cache_Controller.Data 1730 0.00% 0.00% -system.ruby.L1Cache_Controller.Replacement 1726 0.00% 0.00% -system.ruby.L1Cache_Controller.Writeback_Ack 1726 0.00% 0.00% -system.ruby.L1Cache_Controller.I.Load 727 0.00% 0.00% +system.ruby.L1Cache_Controller.Data 1731 0.00% 0.00% +system.ruby.L1Cache_Controller.Replacement 1727 0.00% 0.00% +system.ruby.L1Cache_Controller.Writeback_Ack 1727 0.00% 0.00% +system.ruby.L1Cache_Controller.I.Load 728 0.00% 0.00% system.ruby.L1Cache_Controller.I.Ifetch 730 0.00% 0.00% system.ruby.L1Cache_Controller.I.Store 273 0.00% 0.00% -system.ruby.L1Cache_Controller.M.Load 456 0.00% 0.00% -system.ruby.L1Cache_Controller.M.Ifetch 5670 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Load 457 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Ifetch 5683 0.00% 0.00% system.ruby.L1Cache_Controller.M.Store 592 0.00% 0.00% -system.ruby.L1Cache_Controller.M.Replacement 1726 0.00% 0.00% -system.ruby.L1Cache_Controller.MI.Writeback_Ack 1726 0.00% 0.00% -system.ruby.L1Cache_Controller.IS.Data 1457 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Replacement 1727 0.00% 0.00% +system.ruby.L1Cache_Controller.MI.Writeback_Ack 1727 0.00% 0.00% +system.ruby.L1Cache_Controller.IS.Data 1458 0.00% 0.00% system.ruby.L1Cache_Controller.IM.Data 273 0.00% 0.00% ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini index 1342c10c6..11ab1d0ac 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini @@ -88,7 +88,6 @@ clk_domain=system.cpu_clk_domain clusivity=mostly_incl demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=2 is_read_only=false max_miss_count=0 @@ -130,7 +129,6 @@ clk_domain=system.cpu_clk_domain clusivity=mostly_incl demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=2 is_read_only=true max_miss_count=0 @@ -181,7 +179,6 @@ clk_domain=system.cpu_clk_domain clusivity=mostly_incl demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=20 is_read_only=false max_miss_count=0 @@ -216,6 +213,7 @@ clk_domain=system.cpu_clk_domain eventq_index=0 forward_latency=0 frontend_latency=1 +point_of_coherency=false response_latency=1 snoop_filter=system.cpu.toL2Bus.snoop_filter snoop_response_latency=1 @@ -246,7 +244,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello +executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin kvmInSE=false @@ -281,6 +279,7 @@ clk_domain=system.clk_domain eventq_index=0 forward_latency=4 frontend_latency=3 +point_of_coherency=true response_latency=2 snoop_filter=Null snoop_response_latency=4 diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/simout b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/simout index 006646a27..9c12b76cc 100755 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/simout +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/simout @@ -1,13 +1,15 @@ +Redirecting stdout to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing/simout +Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 21 2016 13:49:21 -gem5 started Jan 21 2016 13:50:02 -gem5 executing on zizzer, pid 34003 -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing +gem5 compiled Mar 14 2016 21:54:46 +gem5 started Mar 14 2016 21:56:12 +gem5 executing on phenom, pid 28101 +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 35667500 because target called exit() +Exiting @ tick 35682500 because target called exit() diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt index f47665bf0..9846d6881 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000036 # Number of seconds simulated -sim_ticks 35667500 # Number of ticks simulated -final_tick 35667500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 35682500 # Number of ticks simulated +final_tick 35682500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 102057 # Simulator instruction rate (inst/s) -host_op_rate 102013 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 569174066 # Simulator tick rate (ticks/s) -host_mem_usage 230332 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host -sim_insts 6390 # Number of instructions simulated -sim_ops 6390 # Number of ops (including micro ops) simulated +host_inst_rate 44587 # Simulator instruction rate (inst/s) +host_op_rate 44581 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 248411942 # Simulator tick rate (ticks/s) +host_mem_usage 226904 # Number of bytes of host memory used +host_seconds 0.14 # Real time elapsed on the host +sim_insts 6403 # Number of instructions simulated +sim_ops 6403 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 17792 # Number of bytes read from this memory @@ -21,35 +21,35 @@ system.physmem.bytes_inst_read::total 17792 # Nu system.physmem.num_reads::cpu.inst 278 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 168 # Number of read requests responded to by this memory system.physmem.num_reads::total 446 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 498829467 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 301450901 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 800280367 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 498829467 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 498829467 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 498829467 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 301450901 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 800280367 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 498619772 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 301324179 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 799943950 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 498619772 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 498619772 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 498619772 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 301324179 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 799943950 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 1183 # DTB read hits +system.cpu.dtb.read_hits 1185 # DTB read hits system.cpu.dtb.read_misses 7 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 1190 # DTB read accesses +system.cpu.dtb.read_accesses 1192 # DTB read accesses system.cpu.dtb.write_hits 865 # DTB write hits system.cpu.dtb.write_misses 3 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations system.cpu.dtb.write_accesses 868 # DTB write accesses -system.cpu.dtb.data_hits 2048 # DTB hits +system.cpu.dtb.data_hits 2050 # DTB hits system.cpu.dtb.data_misses 10 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 2058 # DTB accesses -system.cpu.itb.fetch_hits 6401 # ITB hits +system.cpu.dtb.data_accesses 2060 # DTB accesses +system.cpu.itb.fetch_hits 6414 # ITB hits system.cpu.itb.fetch_misses 17 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 6418 # ITB accesses +system.cpu.itb.fetch_accesses 6431 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -63,87 +63,87 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 71335 # number of cpu cycles simulated +system.cpu.numCycles 71365 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 6390 # Number of instructions committed -system.cpu.committedOps 6390 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 6317 # Number of integer alu accesses +system.cpu.committedInsts 6403 # Number of instructions committed +system.cpu.committedOps 6403 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 6329 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses system.cpu.num_func_calls 251 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 749 # number of instructions that are conditional controls -system.cpu.num_int_insts 6317 # number of integer instructions +system.cpu.num_conditional_control_insts 754 # number of instructions that are conditional controls +system.cpu.num_int_insts 6329 # number of integer instructions system.cpu.num_fp_insts 10 # number of float instructions -system.cpu.num_int_register_reads 8285 # number of times the integer registers were read -system.cpu.num_int_register_writes 4568 # number of times the integer registers were written +system.cpu.num_int_register_reads 8297 # number of times the integer registers were read +system.cpu.num_int_register_writes 4575 # number of times the integer registers were written system.cpu.num_fp_register_reads 8 # number of times the floating registers were read system.cpu.num_fp_register_writes 2 # number of times the floating registers were written -system.cpu.num_mem_refs 2058 # number of memory refs -system.cpu.num_load_insts 1190 # Number of load instructions +system.cpu.num_mem_refs 2060 # number of memory refs +system.cpu.num_load_insts 1192 # Number of load instructions system.cpu.num_store_insts 868 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 71335 # Number of busy cycles +system.cpu.num_busy_cycles 71365 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 1050 # Number of branches fetched +system.cpu.Branches 1056 # Number of branches fetched system.cpu.op_class::No_OpClass 19 0.30% 0.30% # Class of executed instruction -system.cpu.op_class::IntAlu 4320 67.50% 67.80% # Class of executed instruction -system.cpu.op_class::IntMult 1 0.02% 67.81% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 67.81% # Class of executed instruction -system.cpu.op_class::FloatAdd 2 0.03% 67.84% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.84% # Class of executed instruction -system.cpu.op_class::MemRead 1190 18.59% 86.44% # Class of executed instruction -system.cpu.op_class::MemWrite 868 13.56% 100.00% # Class of executed instruction +system.cpu.op_class::IntAlu 4331 67.53% 67.83% # Class of executed instruction +system.cpu.op_class::IntMult 1 0.02% 67.85% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 67.85% # Class of executed instruction +system.cpu.op_class::FloatAdd 2 0.03% 67.88% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.88% # Class of executed instruction +system.cpu.op_class::MemRead 1192 18.59% 86.46% # Class of executed instruction +system.cpu.op_class::MemWrite 868 13.54% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 6400 # Class of executed instruction +system.cpu.op_class::total 6413 # Class of executed instruction system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 103.427155 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 1880 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 103.763836 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 1882 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 168 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 11.190476 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 11.202381 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 103.427155 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.025251 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.025251 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 103.763836 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.025333 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.025333 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 168 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 143 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.041016 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 4264 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 4264 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 1088 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1088 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 4268 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 4268 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 1090 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1090 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 792 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 792 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 1880 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1880 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1880 # number of overall hits -system.cpu.dcache.overall_hits::total 1880 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 1882 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1882 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 1882 # number of overall hits +system.cpu.dcache.overall_hits::total 1882 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 95 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 95 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 73 # number of WriteReq misses @@ -160,22 +160,22 @@ system.cpu.dcache.demand_miss_latency::cpu.data 10416000 system.cpu.dcache.demand_miss_latency::total 10416000 # number of demand (read+write) miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 10416000 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 10416000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1183 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1183 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::cpu.data 1185 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1185 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2048 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2048 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2048 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2048 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.080304 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.080304 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2050 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2050 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2050 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2050 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.080169 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.080169 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.084393 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.084393 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.082031 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.082031 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.082031 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.082031 # miss rate for overall accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.081951 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.081951 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.081951 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.081951 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62000 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 62000 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62000 # average WriteReq miss latency @@ -208,14 +208,14 @@ system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10248000 system.cpu.dcache.demand_mshr_miss_latency::total 10248000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10248000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 10248000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.080304 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.080304 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.080169 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.080169 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.082031 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.082031 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.082031 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.082031 # mshr miss rate for overall accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.081951 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.081951 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.081951 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.081951 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61000 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61000 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61000 # average WriteReq mshr miss latency @@ -226,26 +226,26 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61000 system.cpu.dcache.overall_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 127.519931 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 6122 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 127.232065 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 6135 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 279 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 21.942652 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 21.989247 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 127.519931 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.062266 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.062266 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 127.232065 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.062125 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.062125 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 279 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 95 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 184 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.136230 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 13081 # Number of tag accesses -system.cpu.icache.tags.data_accesses 13081 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 6122 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 6122 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 6122 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 6122 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 6122 # number of overall hits -system.cpu.icache.overall_hits::total 6122 # number of overall hits +system.cpu.icache.tags.tag_accesses 13107 # Number of tag accesses +system.cpu.icache.tags.data_accesses 13107 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 6135 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 6135 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 6135 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 6135 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 6135 # number of overall hits +system.cpu.icache.overall_hits::total 6135 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 279 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 279 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 279 # number of demand (read+write) misses @@ -258,18 +258,18 @@ system.cpu.icache.demand_miss_latency::cpu.inst 17250500 system.cpu.icache.demand_miss_latency::total 17250500 # number of demand (read+write) miss cycles system.cpu.icache.overall_miss_latency::cpu.inst 17250500 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 17250500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 6401 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 6401 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 6401 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 6401 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 6401 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 6401 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.043587 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.043587 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.043587 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.043587 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.043587 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.043587 # miss rate for overall accesses +system.cpu.icache.ReadReq_accesses::cpu.inst 6414 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 6414 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 6414 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 6414 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 6414 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 6414 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.043499 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.043499 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.043499 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.043499 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.043499 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.043499 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61829.749104 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total 61829.749104 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 61829.749104 # average overall miss latency @@ -296,12 +296,12 @@ system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16971500 system.cpu.icache.demand_mshr_miss_latency::total 16971500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16971500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 16971500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.043587 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.043587 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.043587 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.043587 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.043587 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.043587 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.043499 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.043499 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.043499 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.043499 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.043499 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.043499 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60829.749104 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60829.749104 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60829.749104 # average overall mshr miss latency @@ -310,16 +310,16 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60829.749104 system.cpu.icache.overall_avg_mshr_miss_latency::total 60829.749104 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 183.843350 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 184.000496 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 373 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.002681 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 127.517941 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 56.325409 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003892 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.001719 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.005610 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 127.230075 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 56.770421 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003883 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.001732 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.005615 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 373 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 112 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 261 # Occupied blocks per task id @@ -506,6 +506,6 @@ system.membus.snoop_fanout::total 446 # Re system.membus.reqLayer0.occupancy 446500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.3 # Layer utilization (%) system.membus.respLayer1.occupancy 2230000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 6.3 # Layer utilization (%) +system.membus.respLayer1.utilization 6.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout index 811ca2575..fea443199 100755 --- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout @@ -1,9 +1,11 @@ +Redirecting stdout to build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing/simout +Redirecting stderr to build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 13 2016 22:42:39 -gem5 started Mar 13 2016 22:47:14 -gem5 executing on phenom, pid 19880 +gem5 compiled Mar 14 2016 22:04:10 +gem5 started Mar 14 2016 22:06:34 +gem5 executing on phenom, pid 29859 command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt index 7fc5ea5ec..27cfa20b6 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt @@ -4,39 +4,39 @@ sim_seconds 0.000022 # Nu sim_ticks 22454000 # Number of ticks simulated final_tick 22454000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 18374 # Simulator instruction rate (inst/s) -host_op_rate 18373 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 82737910 # Simulator tick rate (ticks/s) -host_mem_usage 226740 # Number of bytes of host memory used -host_seconds 0.27 # Real time elapsed on the host -sim_insts 4986 # Number of instructions simulated -sim_ops 4986 # Number of ops (including micro ops) simulated +host_inst_rate 22135 # Simulator instruction rate (inst/s) +host_op_rate 22134 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 99411388 # Simulator tick rate (ticks/s) +host_mem_usage 226732 # Number of bytes of host memory used +host_seconds 0.23 # Real time elapsed on the host +sim_insts 4999 # Number of instructions simulated +sim_ops 4999 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 20992 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9024 # Number of bytes read from this memory -system.physmem.bytes_read::total 30016 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 8960 # Number of bytes read from this memory +system.physmem.bytes_read::total 29952 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 20992 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 20992 # Number of instructions bytes read from this memory system.physmem.num_reads::cpu.inst 328 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 141 # Number of read requests responded to by this memory -system.physmem.num_reads::total 469 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 140 # Number of read requests responded to by this memory +system.physmem.num_reads::total 468 # Number of read requests responded to by this memory system.physmem.bw_read::cpu.inst 934889107 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 401888305 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1336777412 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 399038033 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1333927140 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 934889107 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 934889107 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_total::cpu.inst 934889107 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 401888305 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1336777412 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 469 # Number of read requests accepted +system.physmem.bw_total::cpu.data 399038033 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1333927140 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 468 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 469 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 468 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 30016 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 29952 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 30016 # Total read bytes from the system interface side +system.physmem.bytesReadSys 29952 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one @@ -55,7 +55,7 @@ system.physmem.perBankRdBursts::10 43 # Pe system.physmem.perBankRdBursts::11 20 # Per bank write bursts system.physmem.perBankRdBursts::12 51 # Per bank write bursts system.physmem.perBankRdBursts::13 29 # Per bank write bursts -system.physmem.perBankRdBursts::14 78 # Per bank write bursts +system.physmem.perBankRdBursts::14 77 # Per bank write bursts system.physmem.perBankRdBursts::15 7 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts @@ -82,7 +82,7 @@ system.physmem.readPktSize::2 0 # Re system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 469 # Read request sizes (log2) +system.physmem.readPktSize::6 468 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,10 +90,10 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 273 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 274 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 135 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 41 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 16 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 40 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 15 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -186,79 +186,79 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 104 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 262.153846 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 180.926322 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 251.694944 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 29 27.88% 27.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 32 30.77% 58.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 20 19.23% 77.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 9 8.65% 86.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 4 3.85% 90.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2 1.92% 92.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1 0.96% 93.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1 0.96% 94.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 6 5.77% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 104 # Bytes accessed per row activation -system.physmem.totQLat 4505500 # Total ticks spent queuing -system.physmem.totMemAccLat 13299250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2345000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9606.61 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 103 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 264.077670 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 182.760997 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 252.156180 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 28 27.18% 27.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 32 31.07% 58.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 20 19.42% 77.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 9 8.74% 86.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 4 3.88% 90.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2 1.94% 92.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1 0.97% 93.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1 0.97% 94.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 6 5.83% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 103 # Bytes accessed per row activation +system.physmem.totQLat 4465750 # Total ticks spent queuing +system.physmem.totMemAccLat 13240750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2340000 # Total ticks spent in databus transfers +system.physmem.avgQLat 9542.20 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28356.61 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1336.78 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 28292.20 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1333.93 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1336.78 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1333.93 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 10.44 # Data bus utilization in percentage -system.physmem.busUtilRead 10.44 # Data bus utilization in percentage for reads +system.physmem.busUtil 10.42 # Data bus utilization in percentage +system.physmem.busUtilRead 10.42 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.73 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.72 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing system.physmem.readRowHits 355 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 75.69 # Row buffer hit rate for reads +system.physmem.readRowHitRate 75.85 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 47690.83 # Average gap between requests -system.physmem.pageHitRate 75.69 # Row buffer hit rate, read and write combined +system.physmem.avgGap 47792.74 # Average gap between requests +system.physmem.pageHitRate 75.85 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 128520 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 70125 # Energy for precharge commands per rank (pJ) system.physmem_0.readEnergy 530400 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 9542655 # Energy for active background per rank (pJ) +system.physmem_0.actBackEnergy 9540945 # Energy for active background per rank (pJ) system.physmem_0.preBackEnergy 1130250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 12419070 # Total energy per rank (pJ) -system.physmem_0.averagePower 784.279760 # Core power per rank (mW) +system.physmem_0.totalEnergy 12417360 # Total energy per rank (pJ) +system.physmem_0.averagePower 784.295595 # Core power per rank (mW) system.physmem_0.memoryStateTime::IDLE 1840500 # Time in different power states system.physmem_0.memoryStateTime::REF 520000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 13487750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 13485750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 514080 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 280500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 2168400 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 506520 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 276375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 2160600 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) system.physmem_1.actBackEnergy 10730250 # Energy for active background per rank (pJ) system.physmem_1.preBackEnergy 87000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 14797350 # Total energy per rank (pJ) -system.physmem_1.averagePower 934.618664 # Core power per rank (mW) +system.physmem_1.totalEnergy 14777865 # Total energy per rank (pJ) +system.physmem_1.averagePower 933.387968 # Core power per rank (mW) system.physmem_1.memoryStateTime::IDLE 103500 # Time in different power states system.physmem_1.memoryStateTime::REF 520000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 15222750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 2031 # Number of BP lookups -system.cpu.branchPred.condPredicted 1362 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 402 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 1641 # Number of BTB lookups -system.cpu.branchPred.BTBHits 605 # Number of BTB hits +system.cpu.branchPred.lookups 2026 # Number of BP lookups +system.cpu.branchPred.condPredicted 1358 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 403 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 1632 # Number of BTB lookups +system.cpu.branchPred.BTBHits 603 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 36.867764 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 242 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 66 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 36.948529 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 244 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 68 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses @@ -282,83 +282,83 @@ system.cpu.workload.num_syscalls 7 # Nu system.cpu.numCycles 44909 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 8843 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 12328 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2031 # Number of branches that fetch encountered +system.cpu.fetch.icacheStallCycles 8846 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 12312 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2026 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 847 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 4817 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 822 # Number of cycles fetch has spent squashing -system.cpu.fetch.PendingTrapStallCycles 190 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 1979 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 255 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 14261 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.864456 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.133927 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.Cycles 4822 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 824 # Number of cycles fetch has spent squashing +system.cpu.fetch.PendingTrapStallCycles 205 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 1982 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 254 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 14285 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.861883 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.130483 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 10999 77.13% 77.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1480 10.38% 87.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 118 0.83% 88.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 169 1.19% 89.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 282 1.98% 91.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 102 0.72% 92.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 134 0.94% 93.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 153 1.07% 94.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 824 5.78% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 11018 77.13% 77.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1489 10.42% 87.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 118 0.83% 88.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 170 1.19% 89.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 281 1.97% 91.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 100 0.70% 92.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 134 0.94% 93.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 151 1.06% 94.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 824 5.77% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 14261 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.045225 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.274511 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8380 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 2677 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2707 # Number of cycles decode is running +system.cpu.fetch.rateDist::total 14285 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.045113 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.274154 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8398 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 2675 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2714 # Number of cycles decode is running system.cpu.decode.UnblockCycles 126 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 371 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 167 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 41 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 11351 # Number of instructions handled by decode +system.cpu.decode.SquashCycles 372 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 164 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 40 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 11356 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 162 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 371 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 8518 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 542 # Number of cycles rename is blocking +system.cpu.rename.SquashCycles 372 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 8537 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 540 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 996 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2675 # Number of cycles rename is running +system.cpu.rename.RunCycles 2681 # Number of cycles rename is running system.cpu.rename.UnblockCycles 1159 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 10918 # Number of instructions processed by rename +system.cpu.rename.RenamedInsts 10925 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 4 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 4 # Number of times rename has blocked due to IQ full system.cpu.rename.LQFullEvents 179 # Number of times rename has blocked due to LQ full system.cpu.rename.SQFullEvents 954 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 6512 # Number of destination operands rename has renamed +system.cpu.rename.RenamedOperands 6515 # Number of destination operands rename has renamed system.cpu.rename.RenameLookups 12905 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 12683 # Number of integer rename lookups +system.cpu.rename.int_rename_lookups 12681 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 3 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 3282 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 3230 # Number of HB maps that are undone due to squashing +system.cpu.rename.CommittedMaps 3292 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 3223 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 14 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 10 # count of temporary serializing insts renamed system.cpu.rename.skidInsts 314 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2295 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedLoads 2297 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 1159 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 2 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 8632 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 8637 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 11 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 7937 # Number of instructions issued +system.cpu.iq.iqInstsIssued 7943 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 20 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 3656 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1608 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedInstsExamined 3648 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1606 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 14261 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.556553 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.276985 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 14285 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.556038 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.275658 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 10981 77.00% 77.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1321 9.26% 86.26% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 733 5.14% 91.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 439 3.08% 94.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 350 2.45% 96.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 10995 76.97% 76.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1332 9.32% 86.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 734 5.14% 91.43% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 438 3.07% 94.50% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 349 2.44% 96.94% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 277 1.94% 98.88% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 91 0.64% 99.52% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 50 0.35% 99.87% # Number of insts issued each cycle @@ -366,7 +366,7 @@ system.cpu.iq.issued_per_cycle::8 19 0.13% 100.00% # Nu system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 14261 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 14285 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 6 3.41% 3.41% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 3.41% # attempts to use FU when none available @@ -402,54 +402,54 @@ system.cpu.iq.fu_full::MemWrite 58 32.95% 100.00% # at system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 4719 59.46% 59.46% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 4723 59.46% 59.46% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 4 0.05% 59.51% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 1 0.01% 59.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.03% 59.54% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.54% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.54% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.54% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.54% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.54% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2143 27.00% 86.54% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1068 13.46% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.03% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2145 27.00% 86.55% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1068 13.45% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 7937 # Type of FU issued -system.cpu.iq.rate 0.176735 # Inst issue rate +system.cpu.iq.FU_type_0::total 7943 # Type of FU issued +system.cpu.iq.rate 0.176869 # Inst issue rate system.cpu.iq.fu_busy_cnt 176 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.022175 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 30327 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 12306 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 7277 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fu_busy_rate 0.022158 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 30363 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 12303 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 7281 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 4 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 2 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 8111 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 8117 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 2 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 89 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1163 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1162 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 8 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 10 # Number of memory ordering violations system.cpu.iew.lsq.thread0.squashedStores 258 # Number of stores squashed @@ -458,179 +458,179 @@ system.cpu.iew.lsq.thread0.blockedLoads 0 # Nu system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 22 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 371 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 425 # Number of cycles IEW is blocking +system.cpu.iew.iewSquashCycles 372 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 422 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 88 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 10126 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 130 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2295 # Number of dispatched load instructions +system.cpu.iew.iewDispatchedInsts 10138 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 138 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2297 # Number of dispatched load instructions system.cpu.iew.iewDispStoreInsts 1159 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 11 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 89 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 10 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 98 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 321 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 100 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 319 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 419 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 7671 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2045 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 266 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 7674 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2046 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 269 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1483 # number of nop insts executed -system.cpu.iew.exec_refs 3098 # number of memory reference insts executed -system.cpu.iew.exec_branches 1353 # Number of branches executed +system.cpu.iew.exec_nop 1490 # number of nop insts executed +system.cpu.iew.exec_refs 3099 # number of memory reference insts executed +system.cpu.iew.exec_branches 1356 # Number of branches executed system.cpu.iew.exec_stores 1053 # Number of stores executed -system.cpu.iew.exec_rate 0.170812 # Inst execution rate -system.cpu.iew.wb_sent 7354 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 7279 # cumulative count of insts written-back -system.cpu.iew.wb_producers 2832 # num instructions producing a value -system.cpu.iew.wb_consumers 4198 # num instructions consuming a value -system.cpu.iew.wb_rate 0.162083 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.674607 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 4505 # The number of squashed insts skipped by commit +system.cpu.iew.exec_rate 0.170879 # Inst execution rate +system.cpu.iew.wb_sent 7358 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 7283 # cumulative count of insts written-back +system.cpu.iew.wb_producers 2837 # num instructions producing a value +system.cpu.iew.wb_consumers 4202 # num instructions consuming a value +system.cpu.iew.wb_rate 0.162172 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.675155 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 4500 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 9 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 362 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 13468 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.417508 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.246465 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 363 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 13494 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.417964 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.246672 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 11324 84.08% 84.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 857 6.36% 90.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 503 3.73% 94.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 247 1.83% 96.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 153 1.14% 97.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 168 1.25% 98.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 61 0.45% 98.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 39 0.29% 99.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 116 0.86% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 11340 84.04% 84.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 862 6.39% 90.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 508 3.76% 94.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 248 1.84% 96.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 152 1.13% 97.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 167 1.24% 98.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 61 0.45% 98.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 39 0.29% 99.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 117 0.87% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 13468 # Number of insts commited each cycle -system.cpu.commit.committedInsts 5623 # Number of instructions committed -system.cpu.commit.committedOps 5623 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 13494 # Number of insts commited each cycle +system.cpu.commit.committedInsts 5640 # Number of instructions committed +system.cpu.commit.committedOps 5640 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 2033 # Number of memory references committed -system.cpu.commit.loads 1132 # Number of loads committed +system.cpu.commit.refs 2036 # Number of memory references committed +system.cpu.commit.loads 1135 # Number of loads committed system.cpu.commit.membars 0 # Number of memory barriers committed -system.cpu.commit.branches 883 # Number of branches committed +system.cpu.commit.branches 886 # Number of branches committed system.cpu.commit.fp_insts 2 # Number of committed floating point instructions. -system.cpu.commit.int_insts 4942 # Number of committed integer instructions. +system.cpu.commit.int_insts 4955 # Number of committed integer instructions. system.cpu.commit.function_calls 85 # Number of function calls committed. -system.cpu.commit.op_class_0::No_OpClass 637 11.33% 11.33% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 2949 52.45% 63.77% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 2 0.04% 63.81% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 0 0.00% 63.81% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 2 0.04% 63.84% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCmp 0 0.00% 63.84% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCvt 0 0.00% 63.84% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMult 0 0.00% 63.84% # Class of committed instruction -system.cpu.commit.op_class_0::FloatDiv 0 0.00% 63.84% # Class of committed instruction -system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 63.84% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAdd 0 0.00% 63.84% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 63.84% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAlu 0 0.00% 63.84% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCmp 0 0.00% 63.84% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCvt 0 0.00% 63.84% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMisc 0 0.00% 63.84% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMult 0 0.00% 63.84% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 63.84% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShift 0 0.00% 63.84% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 63.84% # Class of committed instruction -system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 63.84% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 63.84% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 63.84% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 63.84% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 63.84% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 63.84% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 63.84% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 63.84% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 63.84% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 63.84% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 1132 20.13% 83.98% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 901 16.02% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::No_OpClass 641 11.37% 11.37% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 2959 52.46% 63.83% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 2 0.04% 63.87% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 0 0.00% 63.87% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 2 0.04% 63.90% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 63.90% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 63.90% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 63.90% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 63.90% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 63.90% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 63.90% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 63.90% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 63.90% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 63.90% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 63.90% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 63.90% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 63.90% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 63.90% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 63.90% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 63.90% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 63.90% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 63.90% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 63.90% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 63.90% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 63.90% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 63.90% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 63.90% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 63.90% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 63.90% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 63.90% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 1135 20.12% 84.02% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 901 15.98% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 5623 # Class of committed instruction -system.cpu.commit.bw_lim_events 116 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 23467 # The number of ROB reads -system.cpu.rob.rob_writes 21056 # The number of ROB writes +system.cpu.commit.op_class_0::total 5640 # Class of committed instruction +system.cpu.commit.bw_lim_events 117 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 23504 # The number of ROB reads +system.cpu.rob.rob_writes 21078 # The number of ROB writes system.cpu.timesIdled 265 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 30648 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 4986 # Number of Instructions Simulated -system.cpu.committedOps 4986 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 9.007020 # CPI: Cycles Per Instruction -system.cpu.cpi_total 9.007020 # CPI: Total CPI of All Threads -system.cpu.ipc 0.111025 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.111025 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 10419 # number of integer regfile reads -system.cpu.int_regfile_writes 5064 # number of integer regfile writes +system.cpu.idleCycles 30624 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 4999 # Number of Instructions Simulated +system.cpu.committedOps 4999 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 8.983597 # CPI: Cycles Per Instruction +system.cpu.cpi_total 8.983597 # CPI: Total CPI of All Threads +system.cpu.ipc 0.111314 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.111314 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 10422 # number of integer regfile reads +system.cpu.int_regfile_writes 5065 # number of integer regfile writes system.cpu.fp_regfile_reads 3 # number of floating regfile reads system.cpu.fp_regfile_writes 1 # number of floating regfile writes -system.cpu.misc_regfile_reads 158 # number of misc regfile reads +system.cpu.misc_regfile_reads 160 # number of misc regfile reads system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 90.676519 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2302 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 141 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 16.326241 # Average number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 90.103369 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2304 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 140 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 16.457143 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 90.676519 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.022138 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.022138 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id +system.cpu.dcache.tags.occ_blocks::cpu.data 90.103369 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.021998 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.021998 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 140 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 36 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 105 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.034424 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 5765 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 5765 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 1746 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1746 # number of ReadReq hits +system.cpu.dcache.tags.age_task_id_blocks_1024::1 104 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.034180 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 5766 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 5766 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 1748 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1748 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 556 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 556 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2302 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2302 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2302 # number of overall hits -system.cpu.dcache.overall_hits::total 2302 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 165 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 165 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 2304 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2304 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2304 # number of overall hits +system.cpu.dcache.overall_hits::total 2304 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 164 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 164 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 345 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 345 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 510 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 510 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 510 # number of overall misses -system.cpu.dcache.overall_misses::total 510 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11734000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11734000 # number of ReadReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 509 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 509 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 509 # number of overall misses +system.cpu.dcache.overall_misses::total 509 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11628500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11628500 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 24014999 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 24014999 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 35748999 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 35748999 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 35748999 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 35748999 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1911 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1911 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 35643499 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 35643499 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 35643499 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 35643499 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1912 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1912 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2812 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2812 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2812 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2812 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.086342 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.086342 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2813 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2813 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2813 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2813 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.085774 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.085774 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.382908 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.382908 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.181366 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.181366 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.181366 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.181366 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 71115.151515 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 71115.151515 # average ReadReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.180946 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.180946 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.180946 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.180946 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 70905.487805 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 70905.487805 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69608.692754 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 69608.692754 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 70096.076471 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 70096.076471 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 70096.076471 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 70096.076471 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 70026.520629 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 70026.520629 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 70026.520629 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 70026.520629 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 587 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 10 # number of cycles access was blocked @@ -647,90 +647,90 @@ system.cpu.dcache.demand_mshr_hits::cpu.data 369 system.cpu.dcache.demand_mshr_hits::total 369 # number of demand (read+write) MSHR hits system.cpu.dcache.overall_mshr_hits::cpu.data 369 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::total 369 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 91 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 91 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 90 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 90 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 50 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 50 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 141 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 141 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 141 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7594500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 7594500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 140 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 140 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 140 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 140 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7490000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 7490000 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4083499 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 4083499 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11677999 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 11677999 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11677999 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 11677999 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.047619 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.047619 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11573499 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 11573499 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11573499 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 11573499 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.047071 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.047071 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055494 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055494 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.050142 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.050142 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.050142 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.050142 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 83456.043956 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 83456.043956 # average ReadReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.049769 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.049769 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.049769 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.049769 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 83222.222222 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 83222.222222 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 81669.980000 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 81669.980000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 82822.687943 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 82822.687943 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 82822.687943 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 82822.687943 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 82667.850000 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 82667.850000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 82667.850000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 82667.850000 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 17 # number of replacements -system.cpu.icache.tags.tagsinuse 156.413207 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1547 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 156.353975 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1550 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 331 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 4.673716 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 4.682779 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 156.413207 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.076374 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.076374 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 156.353975 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.076345 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.076345 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 314 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 146 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 168 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.153320 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 4289 # Number of tag accesses -system.cpu.icache.tags.data_accesses 4289 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 1547 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1547 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1547 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1547 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1547 # number of overall hits -system.cpu.icache.overall_hits::total 1547 # number of overall hits +system.cpu.icache.tags.tag_accesses 4295 # Number of tag accesses +system.cpu.icache.tags.data_accesses 4295 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 1550 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1550 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1550 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1550 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1550 # number of overall hits +system.cpu.icache.overall_hits::total 1550 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 432 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 432 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 432 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 432 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 432 # number of overall misses system.cpu.icache.overall_misses::total 432 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 32422500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 32422500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 32422500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 32422500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 32422500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 32422500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1979 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1979 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1979 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1979 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1979 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1979 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.218292 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.218292 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.218292 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.218292 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.218292 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.218292 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75052.083333 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 75052.083333 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 75052.083333 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 75052.083333 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 75052.083333 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 75052.083333 # average overall miss latency +system.cpu.icache.ReadReq_miss_latency::cpu.inst 32414500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 32414500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 32414500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 32414500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 32414500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 32414500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1982 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1982 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1982 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1982 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1982 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1982 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.217962 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.217962 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.217962 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.217962 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.217962 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.217962 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75033.564815 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 75033.564815 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 75033.564815 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 75033.564815 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 75033.564815 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 75033.564815 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -753,42 +753,42 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 331 system.cpu.icache.demand_mshr_misses::total 331 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 331 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 331 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25904500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 25904500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25904500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 25904500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25904500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 25904500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.167256 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.167256 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.167256 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.167256 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.167256 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.167256 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 78261.329305 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 78261.329305 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 78261.329305 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 78261.329305 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 78261.329305 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 78261.329305 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25897500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 25897500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25897500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 25897500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25897500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 25897500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.167003 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.167003 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.167003 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.167003 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.167003 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.167003 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 78240.181269 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 78240.181269 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 78240.181269 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 78240.181269 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 78240.181269 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 78240.181269 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 215.857139 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 215.242460 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 20 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 419 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.047733 # Average number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 418 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.047847 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 158.337319 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 57.519820 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004832 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.001755 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.006587 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 419 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_blocks::cpu.inst 158.278087 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 56.964373 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004830 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.001738 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.006569 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 418 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 184 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 235 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012787 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 4381 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 4381 # Number of data accesses +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 234 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012756 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 4372 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 4372 # Number of data accesses system.cpu.l2cache.WritebackClean_hits::writebacks 17 # number of WritebackClean hits system.cpu.l2cache.WritebackClean_hits::total 17 # number of WritebackClean hits system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 3 # number of ReadCleanReq hits @@ -801,40 +801,40 @@ system.cpu.l2cache.ReadExReq_misses::cpu.data 50 system.cpu.l2cache.ReadExReq_misses::total 50 # number of ReadExReq misses system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 328 # number of ReadCleanReq misses system.cpu.l2cache.ReadCleanReq_misses::total 328 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 91 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 91 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 90 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 90 # number of ReadSharedReq misses system.cpu.l2cache.demand_misses::cpu.inst 328 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 141 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 469 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 140 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 468 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 328 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 141 # number of overall misses -system.cpu.l2cache.overall_misses::total 469 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 140 # number of overall misses +system.cpu.l2cache.overall_misses::total 468 # number of overall misses system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4007500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 4007500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 25375000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 25375000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 7455000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 7455000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 25375000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 11462500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 36837500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 25375000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 11462500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 36837500 # number of overall miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 25368000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 25368000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 7352000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 7352000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 25368000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 11359500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 36727500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 25368000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 11359500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 36727500 # number of overall miss cycles system.cpu.l2cache.WritebackClean_accesses::writebacks 17 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::total 17 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 50 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 50 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 331 # number of ReadCleanReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::total 331 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 91 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 91 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 90 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 90 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 331 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 141 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 472 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 140 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 471 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 331 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 141 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 472 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 140 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 471 # number of overall (read+write) accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.990937 # miss rate for ReadCleanReq accesses @@ -843,22 +843,22 @@ system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.990937 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.993644 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.993631 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.990937 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.993644 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.993631 # miss rate for overall accesses system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80150 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80150 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 77362.804878 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 77362.804878 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 81923.076923 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 81923.076923 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77362.804878 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81294.326241 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 78544.776119 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77362.804878 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81294.326241 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 78544.776119 # average overall miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 77341.463415 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 77341.463415 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 81688.888889 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 81688.888889 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77341.463415 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81139.285714 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 78477.564103 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77341.463415 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81139.285714 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 78477.564103 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -871,26 +871,26 @@ system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 50 system.cpu.l2cache.ReadExReq_mshr_misses::total 50 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 328 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::total 328 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 91 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 91 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 90 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 90 # number of ReadSharedReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 328 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 141 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 469 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 140 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 468 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 328 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 469 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 140 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 468 # number of overall MSHR misses system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3507500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3507500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 22095000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 22095000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6545000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 6545000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22095000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10052500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 32147500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22095000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10052500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 32147500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 22088000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 22088000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6452000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 6452000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22088000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9959500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 32047500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22088000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9959500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 32047500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.990937 # mshr miss rate for ReadCleanReq accesses @@ -899,81 +899,81 @@ system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.990937 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.993644 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.993631 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.990937 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.993644 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.993631 # mshr miss rate for overall accesses system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70150 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70150 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67362.804878 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67362.804878 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71923.076923 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71923.076923 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67362.804878 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71294.326241 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68544.776119 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67362.804878 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71294.326241 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68544.776119 # average overall mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67341.463415 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67341.463415 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71688.888889 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71688.888889 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67341.463415 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71139.285714 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68477.564103 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67341.463415 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71139.285714 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68477.564103 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 489 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.tot_requests 488 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 17 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 422 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 421 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 17 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 50 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 50 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 331 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 91 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 90 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 679 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 282 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 961 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 280 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 959 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 22272 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9024 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 31296 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8960 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 31232 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 472 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 471 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 472 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 471 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 472 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 261500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 471 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 261000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 496500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 2.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 211500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 210000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) -system.membus.trans_dist::ReadResp 419 # Transaction distribution +system.membus.trans_dist::ReadResp 418 # Transaction distribution system.membus.trans_dist::ReadExReq 50 # Transaction distribution system.membus.trans_dist::ReadExResp 50 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 419 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 938 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 938 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30016 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 30016 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 418 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 936 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 936 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 29952 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 29952 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 469 # Request fanout histogram +system.membus.snoop_fanout::samples 468 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 469 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 468 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 469 # Request fanout histogram -system.membus.reqLayer0.occupancy 581500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 468 # Request fanout histogram +system.membus.reqLayer0.occupancy 580000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.6 # Layer utilization (%) -system.membus.respLayer1.occupancy 2493500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2487500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 11.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/config.ini index c14cdc26c..d92d6b0d8 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/config.ini +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/config.ini @@ -118,7 +118,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/dist/m5/regression/test-progs/hello/bin/mips/linux/hello +executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/hello/bin/mips/linux/hello gid=100 input=cin kvmInSE=false @@ -153,6 +153,7 @@ clk_domain=system.clk_domain eventq_index=0 forward_latency=4 frontend_latency=3 +point_of_coherency=true response_latency=2 snoop_filter=Null snoop_response_latency=4 diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/simerr b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/simerr index 0f553ea6b..1a4f96712 100755 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/simerr +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/simerr @@ -1,2 +1 @@ warn: Sockets disabled, not accepting gdb connections -warn: mmap failing: arguments not page-aligned: start 0x0 offset 0x7efefeff diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/simout b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/simout index b150c3b1d..3810aff86 100755 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/simout +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/simout @@ -1,13 +1,15 @@ +Redirecting stdout to build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-atomic/simout +Redirecting stderr to build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-atomic/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 21 2016 14:17:41 -gem5 started Jan 21 2016 14:18:13 -gem5 executing on zizzer, pid 60571 -command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-atomic -re /z/atgutier/gem5/gem5-commit/tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-atomic +gem5 compiled Mar 14 2016 22:04:10 +gem5 started Mar 14 2016 22:06:34 +gem5 executing on phenom, pid 29858 +command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-atomic -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello World! -Exiting @ tick 2812000 because target called exit() +Exiting @ tick 2820500 because target called exit() diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt index cd97b68c3..9b5c0be15 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt @@ -1,40 +1,40 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000003 # Number of seconds simulated -sim_ticks 2812000 # Number of ticks simulated -final_tick 2812000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 2820500 # Number of ticks simulated +final_tick 2820500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 70039 # Simulator instruction rate (inst/s) -host_op_rate 70020 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 35000361 # Simulator tick rate (ticks/s) -host_mem_usage 218484 # Number of bytes of host memory used -host_seconds 0.08 # Real time elapsed on the host -sim_insts 5624 # Number of instructions simulated -sim_ops 5624 # Number of ops (including micro ops) simulated +host_inst_rate 42403 # Simulator instruction rate (inst/s) +host_op_rate 42398 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 21196256 # Simulator tick rate (ticks/s) +host_mem_usage 214708 # Number of bytes of host memory used +host_seconds 0.13 # Real time elapsed on the host +sim_insts 5641 # Number of instructions simulated +sim_ops 5641 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 22500 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 4289 # Number of bytes read from this memory -system.physmem.bytes_read::total 26789 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 22500 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 22500 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 22568 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 4301 # Number of bytes read from this memory +system.physmem.bytes_read::total 26869 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 22568 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 22568 # Number of instructions bytes read from this memory system.physmem.bytes_written::cpu.data 3601 # Number of bytes written to this memory system.physmem.bytes_written::total 3601 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 5625 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1132 # Number of read requests responded to by this memory -system.physmem.num_reads::total 6757 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 5642 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1135 # Number of read requests responded to by this memory +system.physmem.num_reads::total 6777 # Number of read requests responded to by this memory system.physmem.num_writes::cpu.data 901 # Number of write requests responded to by this memory system.physmem.num_writes::total 901 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 8001422475 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1525248933 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 9526671408 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 8001422475 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 8001422475 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1280583215 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1280583215 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 8001422475 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2805832148 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 10807254623 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 8001418188 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1524906931 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 9526325120 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 8001418188 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 8001418188 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1276723985 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1276723985 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 8001418188 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2801630917 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 10803049105 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses @@ -55,84 +55,84 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 7 # Number of system calls -system.cpu.numCycles 5625 # number of cpu cycles simulated +system.cpu.numCycles 5642 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 5624 # Number of instructions committed -system.cpu.committedOps 5624 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 4944 # Number of integer alu accesses +system.cpu.committedInsts 5641 # Number of instructions committed +system.cpu.committedOps 5641 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 4957 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 2 # Number of float alu accesses -system.cpu.num_func_calls 190 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 649 # number of instructions that are conditional controls -system.cpu.num_int_insts 4944 # number of integer instructions +system.cpu.num_func_calls 191 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 651 # number of instructions that are conditional controls +system.cpu.num_int_insts 4957 # number of integer instructions system.cpu.num_fp_insts 2 # number of float instructions -system.cpu.num_int_register_reads 7054 # number of times the integer registers were read -system.cpu.num_int_register_writes 3281 # number of times the integer registers were written +system.cpu.num_int_register_reads 7072 # number of times the integer registers were read +system.cpu.num_int_register_writes 3291 # number of times the integer registers were written system.cpu.num_fp_register_reads 3 # number of times the floating registers were read system.cpu.num_fp_register_writes 1 # number of times the floating registers were written -system.cpu.num_mem_refs 2034 # number of memory refs -system.cpu.num_load_insts 1132 # Number of load instructions +system.cpu.num_mem_refs 2037 # number of memory refs +system.cpu.num_load_insts 1135 # Number of load instructions system.cpu.num_store_insts 902 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 5625 # Number of busy cycles +system.cpu.num_busy_cycles 5642 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 883 # Number of branches fetched -system.cpu.op_class::No_OpClass 637 11.32% 11.32% # Class of executed instruction -system.cpu.op_class::IntAlu 2950 52.44% 63.77% # Class of executed instruction -system.cpu.op_class::IntMult 2 0.04% 63.80% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 63.80% # Class of executed instruction -system.cpu.op_class::FloatAdd 2 0.04% 63.84% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::MemRead 1132 20.12% 83.96% # Class of executed instruction -system.cpu.op_class::MemWrite 902 16.04% 100.00% # Class of executed instruction +system.cpu.Branches 886 # Number of branches fetched +system.cpu.op_class::No_OpClass 641 11.36% 11.36% # Class of executed instruction +system.cpu.op_class::IntAlu 2960 52.46% 63.82% # Class of executed instruction +system.cpu.op_class::IntMult 2 0.04% 63.86% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 63.86% # Class of executed instruction +system.cpu.op_class::FloatAdd 2 0.04% 63.90% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::MemRead 1135 20.12% 84.01% # Class of executed instruction +system.cpu.op_class::MemWrite 902 15.99% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 5625 # Class of executed instruction -system.membus.trans_dist::ReadReq 6757 # Transaction distribution -system.membus.trans_dist::ReadResp 6757 # Transaction distribution +system.cpu.op_class::total 5642 # Class of executed instruction +system.membus.trans_dist::ReadReq 6777 # Transaction distribution +system.membus.trans_dist::ReadResp 6777 # Transaction distribution system.membus.trans_dist::WriteReq 901 # Transaction distribution system.membus.trans_dist::WriteResp 901 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 11250 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 4066 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 15316 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 22500 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 7890 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 30390 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 11284 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 4072 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 15356 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 22568 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 7902 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 30470 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 7658 # Request fanout histogram -system.membus.snoop_fanout::mean 0.734526 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.441614 # Request fanout histogram +system.membus.snoop_fanout::samples 7678 # Request fanout histogram +system.membus.snoop_fanout::mean 0.734827 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.441454 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 2033 26.55% 26.55% # Request fanout histogram -system.membus.snoop_fanout::1 5625 73.45% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 2036 26.52% 26.52% # Request fanout histogram +system.membus.snoop_fanout::1 5642 73.48% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 7658 # Request fanout histogram +system.membus.snoop_fanout::total 7678 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/config.ini index 66492880c..5053dfd9a 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/config.ini +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/config.ini @@ -122,7 +122,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/dist/m5/regression/test-progs/hello/bin/mips/linux/hello +executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/hello/bin/mips/linux/hello gid=100 input=cin kvmInSE=false diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/simerr b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/simerr index f56064f64..22fffb44f 100755 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/simerr +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/simerr @@ -7,4 +7,3 @@ warn: rounding error > tolerance warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes) warn: Sockets disabled, not accepting gdb connections warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files! -warn: mmap failing: arguments not page-aligned: start 0x0 offset 0x7efefeff diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/simout b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/simout index 64fadbc16..735671e5f 100755 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/simout +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/simout @@ -1,13 +1,15 @@ +Redirecting stdout to build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing-ruby/simout +Redirecting stderr to build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing-ruby/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 21 2016 14:17:41 -gem5 started Jan 21 2016 14:18:13 -gem5 executing on zizzer, pid 60577 -command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing-ruby -re /z/atgutier/gem5/gem5-commit/tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing-ruby +gem5 compiled Mar 14 2016 22:04:10 +gem5 started Mar 14 2016 22:06:34 +gem5 executing on phenom, pid 29860 +command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing-ruby -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing-ruby Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello World! -Exiting @ tick 100307 because target called exit() +Exiting @ tick 100232 because target called exit() diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt index 3ed561887..4c477fff4 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt @@ -1,94 +1,94 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000100 # Number of seconds simulated -sim_ticks 100307 # Number of ticks simulated -final_tick 100307 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 100232 # Number of ticks simulated +final_tick 100232 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 28982 # Simulator instruction rate (inst/s) -host_op_rate 28978 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 516775 # Simulator tick rate (ticks/s) -host_mem_usage 393304 # Number of bytes of host memory used -host_seconds 0.19 # Real time elapsed on the host -sim_insts 5624 # Number of instructions simulated -sim_ops 5624 # Number of ops (including micro ops) simulated +host_inst_rate 20831 # Simulator instruction rate (inst/s) +host_op_rate 20830 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 370097 # Simulator tick rate (ticks/s) +host_mem_usage 389556 # Number of bytes of host memory used +host_seconds 0.27 # Real time elapsed on the host +sim_insts 5641 # Number of instructions simulated +sim_ops 5641 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks -system.mem_ctrls.bytes_read::ruby.dir_cntrl0 94080 # Number of bytes read from this memory -system.mem_ctrls.bytes_read::total 94080 # Number of bytes read from this memory -system.mem_ctrls.bytes_written::ruby.dir_cntrl0 93824 # Number of bytes written to this memory -system.mem_ctrls.bytes_written::total 93824 # Number of bytes written to this memory -system.mem_ctrls.num_reads::ruby.dir_cntrl0 1470 # Number of read requests responded to by this memory -system.mem_ctrls.num_reads::total 1470 # Number of read requests responded to by this memory -system.mem_ctrls.num_writes::ruby.dir_cntrl0 1466 # Number of write requests responded to by this memory -system.mem_ctrls.num_writes::total 1466 # Number of write requests responded to by this memory -system.mem_ctrls.bw_read::ruby.dir_cntrl0 937920584 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_read::total 937920584 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::ruby.dir_cntrl0 935368419 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::total 935368419 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_total::ruby.dir_cntrl0 1873289003 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.bw_total::total 1873289003 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.readReqs 1470 # Number of read requests accepted -system.mem_ctrls.writeReqs 1466 # Number of write requests accepted -system.mem_ctrls.readBursts 1470 # Number of DRAM read bursts, including those serviced by the write queue -system.mem_ctrls.writeBursts 1466 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrls.bytesReadDRAM 58560 # Total number of bytes read from DRAM -system.mem_ctrls.bytesReadWrQ 35520 # Total number of bytes read from write queue -system.mem_ctrls.bytesWritten 59456 # Total number of bytes written to DRAM -system.mem_ctrls.bytesReadSys 94080 # Total read bytes from the system interface side -system.mem_ctrls.bytesWrittenSys 93824 # Total written bytes from the system interface side -system.mem_ctrls.servicedByWrQ 555 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrls.mergedWrBursts 516 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.bytes_read::ruby.dir_cntrl0 94208 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 94208 # Number of bytes read from this memory +system.mem_ctrls.bytes_written::ruby.dir_cntrl0 93952 # Number of bytes written to this memory +system.mem_ctrls.bytes_written::total 93952 # Number of bytes written to this memory +system.mem_ctrls.num_reads::ruby.dir_cntrl0 1472 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 1472 # Number of read requests responded to by this memory +system.mem_ctrls.num_writes::ruby.dir_cntrl0 1468 # Number of write requests responded to by this memory +system.mem_ctrls.num_writes::total 1468 # Number of write requests responded to by this memory +system.mem_ctrls.bw_read::ruby.dir_cntrl0 939899433 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 939899433 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::ruby.dir_cntrl0 937345359 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::total 937345359 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::ruby.dir_cntrl0 1877244792 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 1877244792 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.readReqs 1472 # Number of read requests accepted +system.mem_ctrls.writeReqs 1468 # Number of write requests accepted +system.mem_ctrls.readBursts 1472 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 1468 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.bytesReadDRAM 58752 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 35456 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 60352 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 94208 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 93952 # Total written bytes from the system interface side +system.mem_ctrls.servicedByWrQ 554 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 502 # Number of DRAM write bursts merged with an existing one system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.mem_ctrls.perBankRdBursts::0 31 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::0 33 # Per bank write bursts system.mem_ctrls.perBankRdBursts::1 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::2 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::3 0 # Per bank write bursts system.mem_ctrls.perBankRdBursts::4 7 # Per bank write bursts system.mem_ctrls.perBankRdBursts::5 3 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::6 12 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::7 84 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 13 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 81 # Per bank write bursts system.mem_ctrls.perBankRdBursts::8 66 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::9 243 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::10 97 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::11 46 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::12 113 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::13 44 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::14 160 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::15 9 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::0 32 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::9 245 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 98 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 45 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::12 114 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 45 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 154 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::15 14 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 34 # Per bank write bursts system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::4 7 # Per bank write bursts system.mem_ctrls.perBankWrBursts::5 3 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::6 12 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::7 83 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::8 61 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::9 239 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::10 97 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::11 47 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::12 117 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::13 44 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::14 176 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::15 11 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 13 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 74 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::8 60 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::9 247 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 100 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::11 46 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::12 118 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 49 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 178 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::15 14 # Per bank write bursts system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrls.totGap 100258 # Total gap between requests +system.mem_ctrls.totGap 100183 # Total gap between requests system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::6 1470 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 1472 # Read request sizes (log2) system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::6 1466 # Write request sizes (log2) -system.mem_ctrls.rdQLenPdf::0 915 # What read queue length does an incoming req see +system.mem_ctrls.writePktSize::6 1468 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 918 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see @@ -135,25 +135,25 @@ system.mem_ctrls.wrQLenPdf::11 1 # Wh system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::15 6 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::16 7 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::17 54 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::18 59 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::19 61 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::20 62 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::21 59 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::22 57 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::23 57 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::24 57 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::25 57 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::26 57 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::27 57 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::28 57 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::29 57 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::30 57 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::31 57 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::32 57 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 5 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 8 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 50 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 60 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 60 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 67 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 61 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 59 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 58 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::24 58 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 58 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 58 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 58 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::28 58 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 58 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 58 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 58 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::32 58 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::33 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see @@ -184,88 +184,88 @@ system.mem_ctrls.wrQLenPdf::60 0 # Wh system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrls.bytesPerActivate::samples 346 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::mean 337.017341 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::gmean 221.831279 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::stdev 312.425842 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::0-127 75 21.68% 21.68% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::128-255 111 32.08% 53.76% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::256-383 54 15.61% 69.36% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::384-511 22 6.36% 75.72% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::512-639 14 4.05% 79.77% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::640-767 16 4.62% 84.39% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::768-895 11 3.18% 87.57% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::896-1023 8 2.31% 89.88% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::1024-1151 35 10.12% 100.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::total 346 # Bytes accessed per row activation -system.mem_ctrls.rdPerTurnAround::samples 57 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::mean 15.982456 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::gmean 15.826931 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::stdev 2.722205 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::12-13 2 3.51% 3.51% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::14-15 25 43.86% 47.37% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::16-17 25 43.86% 91.23% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::18-19 4 7.02% 98.25% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::34-35 1 1.75% 100.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::total 57 # Reads before turning the bus around for writes -system.mem_ctrls.wrPerTurnAround::samples 57 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::mean 16.298246 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::gmean 16.275827 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::stdev 0.905635 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::16 51 89.47% 89.47% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::18 2 3.51% 92.98% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::19 3 5.26% 98.25% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::20 1 1.75% 100.00% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::total 57 # Writes before turning the bus around for reads -system.mem_ctrls.totQLat 12902 # Total ticks spent queuing -system.mem_ctrls.totMemAccLat 30287 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrls.totBusLat 4575 # Total ticks spent in databus transfers -system.mem_ctrls.avgQLat 14.10 # Average queueing delay per DRAM burst +system.mem_ctrls.bytesPerActivate::samples 336 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 348.571429 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 224.382213 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 328.447975 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 77 22.92% 22.92% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 103 30.65% 53.57% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 48 14.29% 67.86% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 26 7.74% 75.60% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 11 3.27% 78.87% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 8 2.38% 81.25% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 13 3.87% 85.12% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 7 2.08% 87.20% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 43 12.80% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 336 # Bytes accessed per row activation +system.mem_ctrls.rdPerTurnAround::samples 58 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::mean 15.706897 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::gmean 15.549891 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::stdev 2.720995 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::12-13 5 8.62% 8.62% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::14-15 26 44.83% 53.45% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::16-17 25 43.10% 96.55% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::18-19 1 1.72% 98.28% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::34-35 1 1.72% 100.00% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::total 58 # Reads before turning the bus around for writes +system.mem_ctrls.wrPerTurnAround::samples 58 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::mean 16.258621 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::gmean 16.240724 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::stdev 0.806995 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::16 52 89.66% 89.66% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::18 4 6.90% 96.55% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::19 1 1.72% 98.28% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::20 1 1.72% 100.00% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::total 58 # Writes before turning the bus around for reads +system.mem_ctrls.totQLat 12638 # Total ticks spent queuing +system.mem_ctrls.totMemAccLat 30080 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.totBusLat 4590 # Total ticks spent in databus transfers +system.mem_ctrls.avgQLat 13.77 # Average queueing delay per DRAM burst system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst -system.mem_ctrls.avgMemAccLat 33.10 # Average memory access latency per DRAM burst -system.mem_ctrls.avgRdBW 583.81 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrls.avgWrBW 592.74 # Average achieved write bandwidth in MiByte/s -system.mem_ctrls.avgRdBWSys 937.92 # Average system read bandwidth in MiByte/s -system.mem_ctrls.avgWrBWSys 935.37 # Average system write bandwidth in MiByte/s +system.mem_ctrls.avgMemAccLat 32.77 # Average memory access latency per DRAM burst +system.mem_ctrls.avgRdBW 586.16 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 602.12 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 939.90 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 937.35 # Average system write bandwidth in MiByte/s system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrls.busUtil 9.19 # Data bus utilization in percentage -system.mem_ctrls.busUtilRead 4.56 # Data bus utilization in percentage for reads -system.mem_ctrls.busUtilWrite 4.63 # Data bus utilization in percentage for writes +system.mem_ctrls.busUtil 9.28 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 4.58 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 4.70 # Data bus utilization in percentage for writes system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing -system.mem_ctrls.avgWrQLen 25.61 # Average write queue length when enqueuing -system.mem_ctrls.readRowHits 627 # Number of row buffer hits during reads -system.mem_ctrls.writeRowHits 865 # Number of row buffer hits during writes -system.mem_ctrls.readRowHitRate 68.52 # Row buffer hit rate for reads -system.mem_ctrls.writeRowHitRate 91.05 # Row buffer hit rate for writes -system.mem_ctrls.avgGap 34.15 # Average gap between requests -system.mem_ctrls.pageHitRate 80.00 # Row buffer hit rate, read and write combined -system.mem_ctrls_0.actEnergy 506520 # Energy for activate commands per rank (pJ) -system.mem_ctrls_0.preEnergy 281400 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_0.readEnergy 1497600 # Energy for read commands per rank (pJ) -system.mem_ctrls_0.writeEnergy 1254528 # Energy for write commands per rank (pJ) +system.mem_ctrls.avgWrQLen 25.54 # Average write queue length when enqueuing +system.mem_ctrls.readRowHits 642 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 873 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 69.93 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate 90.37 # Row buffer hit rate for writes +system.mem_ctrls.avgGap 34.08 # Average gap between requests +system.mem_ctrls.pageHitRate 80.41 # Row buffer hit rate, read and write combined +system.mem_ctrls_0.actEnergy 491400 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 273000 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 1547520 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 1099008 # Energy for write commands per rank (pJ) system.mem_ctrls_0.refreshEnergy 6102720 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_0.actBackEnergy 47014056 # Energy for active background per rank (pJ) -system.mem_ctrls_0.preBackEnergy 14974800 # Energy for precharge background per rank (pJ) -system.mem_ctrls_0.totalEnergy 71631624 # Total energy per rank (pJ) -system.mem_ctrls_0.averagePower 764.543654 # Core power per rank (mW) -system.mem_ctrls_0.memoryStateTime::IDLE 25717 # Time in different power states +system.mem_ctrls_0.actBackEnergy 55680336 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 7372800 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.totalEnergy 72566784 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 774.524869 # Core power per rank (mW) +system.mem_ctrls_0.memoryStateTime::IDLE 11950 # Time in different power states system.mem_ctrls_0.memoryStateTime::REF 3120 # Time in different power states system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT 71078 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 78690 # Time in different power states system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrls_1.actEnergy 1950480 # Energy for activate commands per rank (pJ) -system.mem_ctrls_1.preEnergy 1083600 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_1.readEnergy 9197760 # Energy for read commands per rank (pJ) -system.mem_ctrls_1.writeEnergy 7713792 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.actEnergy 1882440 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 1045800 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 9247680 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 7993728 # Energy for write commands per rank (pJ) system.mem_ctrls_1.refreshEnergy 6102720 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_1.actBackEnergy 63796680 # Energy for active background per rank (pJ) -system.mem_ctrls_1.preBackEnergy 253200 # Energy for precharge background per rank (pJ) -system.mem_ctrls_1.totalEnergy 90098232 # Total energy per rank (pJ) -system.mem_ctrls_1.averagePower 961.642744 # Core power per rank (mW) -system.mem_ctrls_1.memoryStateTime::IDLE 100 # Time in different power states +system.mem_ctrls_1.actBackEnergy 63740592 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 302400 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.totalEnergy 90315360 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 963.960210 # Core power per rank (mW) +system.mem_ctrls_1.memoryStateTime::IDLE 182 # Time in different power states system.mem_ctrls_1.memoryStateTime::REF 3120 # Time in different power states system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT 90486 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 90404 # Time in different power states system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.clk_domain.clock 1 # Clock period in ticks system.cpu.dtb.read_hits 0 # DTB read hits @@ -287,210 +287,210 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 7 # Number of system calls -system.cpu.numCycles 100307 # number of cpu cycles simulated +system.cpu.numCycles 100232 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 5624 # Number of instructions committed -system.cpu.committedOps 5624 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 4944 # Number of integer alu accesses +system.cpu.committedInsts 5641 # Number of instructions committed +system.cpu.committedOps 5641 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 4957 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 2 # Number of float alu accesses -system.cpu.num_func_calls 190 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 649 # number of instructions that are conditional controls -system.cpu.num_int_insts 4944 # number of integer instructions +system.cpu.num_func_calls 191 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 651 # number of instructions that are conditional controls +system.cpu.num_int_insts 4957 # number of integer instructions system.cpu.num_fp_insts 2 # number of float instructions -system.cpu.num_int_register_reads 7054 # number of times the integer registers were read -system.cpu.num_int_register_writes 3281 # number of times the integer registers were written +system.cpu.num_int_register_reads 7072 # number of times the integer registers were read +system.cpu.num_int_register_writes 3291 # number of times the integer registers were written system.cpu.num_fp_register_reads 3 # number of times the floating registers were read system.cpu.num_fp_register_writes 1 # number of times the floating registers were written -system.cpu.num_mem_refs 2034 # number of memory refs -system.cpu.num_load_insts 1132 # Number of load instructions +system.cpu.num_mem_refs 2037 # number of memory refs +system.cpu.num_load_insts 1135 # Number of load instructions system.cpu.num_store_insts 902 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 100307 # Number of busy cycles +system.cpu.num_busy_cycles 100232 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 883 # Number of branches fetched -system.cpu.op_class::No_OpClass 637 11.32% 11.32% # Class of executed instruction -system.cpu.op_class::IntAlu 2950 52.44% 63.77% # Class of executed instruction -system.cpu.op_class::IntMult 2 0.04% 63.80% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 63.80% # Class of executed instruction -system.cpu.op_class::FloatAdd 2 0.04% 63.84% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::MemRead 1132 20.12% 83.96% # Class of executed instruction -system.cpu.op_class::MemWrite 902 16.04% 100.00% # Class of executed instruction +system.cpu.Branches 886 # Number of branches fetched +system.cpu.op_class::No_OpClass 641 11.36% 11.36% # Class of executed instruction +system.cpu.op_class::IntAlu 2960 52.46% 63.82% # Class of executed instruction +system.cpu.op_class::IntMult 2 0.04% 63.86% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 63.86% # Class of executed instruction +system.cpu.op_class::FloatAdd 2 0.04% 63.90% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::MemRead 1135 20.12% 84.01% # Class of executed instruction +system.cpu.op_class::MemWrite 902 15.99% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 5625 # Class of executed instruction +system.cpu.op_class::total 5642 # Class of executed instruction system.ruby.clk_domain.clock 1 # Clock period in ticks system.ruby.delayHist::bucket_size 1 # delay histogram for all message system.ruby.delayHist::max_bucket 9 # delay histogram for all message -system.ruby.delayHist::samples 2936 # delay histogram for all message -system.ruby.delayHist | 2936 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message -system.ruby.delayHist::total 2936 # delay histogram for all message +system.ruby.delayHist::samples 2940 # delay histogram for all message +system.ruby.delayHist | 2940 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message +system.ruby.delayHist::total 2940 # delay histogram for all message system.ruby.outstanding_req_hist_seqr::bucket_size 1 system.ruby.outstanding_req_hist_seqr::max_bucket 9 -system.ruby.outstanding_req_hist_seqr::samples 7659 +system.ruby.outstanding_req_hist_seqr::samples 7679 system.ruby.outstanding_req_hist_seqr::mean 1 system.ruby.outstanding_req_hist_seqr::gmean 1 -system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 7659 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.outstanding_req_hist_seqr::total 7659 +system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 7679 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist_seqr::total 7679 system.ruby.latency_hist_seqr::bucket_size 64 system.ruby.latency_hist_seqr::max_bucket 639 -system.ruby.latency_hist_seqr::samples 7658 -system.ruby.latency_hist_seqr::mean 12.098329 -system.ruby.latency_hist_seqr::gmean 2.138684 -system.ruby.latency_hist_seqr::stdev 27.490264 -system.ruby.latency_hist_seqr | 7348 95.95% 95.95% | 251 3.28% 99.23% | 42 0.55% 99.78% | 5 0.07% 99.84% | 10 0.13% 99.97% | 2 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.latency_hist_seqr::total 7658 +system.ruby.latency_hist_seqr::samples 7678 +system.ruby.latency_hist_seqr::mean 12.054441 +system.ruby.latency_hist_seqr::gmean 2.136034 +system.ruby.latency_hist_seqr::stdev 27.599754 +system.ruby.latency_hist_seqr | 7372 96.01% 96.01% | 253 3.30% 99.31% | 37 0.48% 99.79% | 4 0.05% 99.84% | 6 0.08% 99.92% | 5 0.07% 99.99% | 0 0.00% 99.99% | 1 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.latency_hist_seqr::total 7678 system.ruby.hit_latency_hist_seqr::bucket_size 1 system.ruby.hit_latency_hist_seqr::max_bucket 9 -system.ruby.hit_latency_hist_seqr::samples 6188 +system.ruby.hit_latency_hist_seqr::samples 6206 system.ruby.hit_latency_hist_seqr::mean 1 system.ruby.hit_latency_hist_seqr::gmean 1 -system.ruby.hit_latency_hist_seqr | 0 0.00% 0.00% | 6188 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.hit_latency_hist_seqr::total 6188 +system.ruby.hit_latency_hist_seqr | 0 0.00% 0.00% | 6206 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.hit_latency_hist_seqr::total 6206 system.ruby.miss_latency_hist_seqr::bucket_size 64 system.ruby.miss_latency_hist_seqr::max_bucket 639 -system.ruby.miss_latency_hist_seqr::samples 1470 -system.ruby.miss_latency_hist_seqr::mean 58.817007 -system.ruby.miss_latency_hist_seqr::gmean 52.469450 -system.ruby.miss_latency_hist_seqr::stdev 35.158300 -system.ruby.miss_latency_hist_seqr | 1160 78.91% 78.91% | 251 17.07% 95.99% | 42 2.86% 98.84% | 5 0.34% 99.18% | 10 0.68% 99.86% | 2 0.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.miss_latency_hist_seqr::total 1470 -system.ruby.Directory.incomplete_times_seqr 1469 -system.ruby.l1_cntrl0.cacheMemory.demand_hits 6188 # Number of cache demand hits -system.ruby.l1_cntrl0.cacheMemory.demand_misses 1470 # Number of cache demand misses -system.ruby.l1_cntrl0.cacheMemory.demand_accesses 7658 # Number of cache demand accesses +system.ruby.miss_latency_hist_seqr::samples 1472 +system.ruby.miss_latency_hist_seqr::mean 58.660326 +system.ruby.miss_latency_hist_seqr::gmean 52.389786 +system.ruby.miss_latency_hist_seqr::stdev 35.865583 +system.ruby.miss_latency_hist_seqr | 1166 79.21% 79.21% | 253 17.19% 96.40% | 37 2.51% 98.91% | 4 0.27% 99.18% | 6 0.41% 99.59% | 5 0.34% 99.93% | 0 0.00% 99.93% | 1 0.07% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.miss_latency_hist_seqr::total 1472 +system.ruby.Directory.incomplete_times_seqr 1471 +system.ruby.l1_cntrl0.cacheMemory.demand_hits 6206 # Number of cache demand hits +system.ruby.l1_cntrl0.cacheMemory.demand_misses 1472 # Number of cache demand misses +system.ruby.l1_cntrl0.cacheMemory.demand_accesses 7678 # Number of cache demand accesses system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.ruby.network.routers0.percent_links_utilized 7.317535 -system.ruby.network.routers0.msg_count.Control::2 1470 -system.ruby.network.routers0.msg_count.Data::2 1466 -system.ruby.network.routers0.msg_count.Response_Data::4 1470 -system.ruby.network.routers0.msg_count.Writeback_Control::3 1466 -system.ruby.network.routers0.msg_bytes.Control::2 11760 -system.ruby.network.routers0.msg_bytes.Data::2 105552 -system.ruby.network.routers0.msg_bytes.Response_Data::4 105840 -system.ruby.network.routers0.msg_bytes.Writeback_Control::3 11728 -system.ruby.network.routers1.percent_links_utilized 7.317535 -system.ruby.network.routers1.msg_count.Control::2 1470 -system.ruby.network.routers1.msg_count.Data::2 1466 -system.ruby.network.routers1.msg_count.Response_Data::4 1470 -system.ruby.network.routers1.msg_count.Writeback_Control::3 1466 -system.ruby.network.routers1.msg_bytes.Control::2 11760 -system.ruby.network.routers1.msg_bytes.Data::2 105552 -system.ruby.network.routers1.msg_bytes.Response_Data::4 105840 -system.ruby.network.routers1.msg_bytes.Writeback_Control::3 11728 -system.ruby.network.routers2.percent_links_utilized 7.317535 -system.ruby.network.routers2.msg_count.Control::2 1470 -system.ruby.network.routers2.msg_count.Data::2 1466 -system.ruby.network.routers2.msg_count.Response_Data::4 1470 -system.ruby.network.routers2.msg_count.Writeback_Control::3 1466 -system.ruby.network.routers2.msg_bytes.Control::2 11760 -system.ruby.network.routers2.msg_bytes.Data::2 105552 -system.ruby.network.routers2.msg_bytes.Response_Data::4 105840 -system.ruby.network.routers2.msg_bytes.Writeback_Control::3 11728 -system.ruby.network.msg_count.Control 4410 -system.ruby.network.msg_count.Data 4398 -system.ruby.network.msg_count.Response_Data 4410 -system.ruby.network.msg_count.Writeback_Control 4398 -system.ruby.network.msg_byte.Control 35280 -system.ruby.network.msg_byte.Data 316656 -system.ruby.network.msg_byte.Response_Data 317520 -system.ruby.network.msg_byte.Writeback_Control 35184 -system.ruby.network.routers0.throttle0.link_utilization 7.325511 -system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1470 -system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 1466 -system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 105840 -system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 11728 -system.ruby.network.routers0.throttle1.link_utilization 7.309560 -system.ruby.network.routers0.throttle1.msg_count.Control::2 1470 -system.ruby.network.routers0.throttle1.msg_count.Data::2 1466 -system.ruby.network.routers0.throttle1.msg_bytes.Control::2 11760 -system.ruby.network.routers0.throttle1.msg_bytes.Data::2 105552 -system.ruby.network.routers1.throttle0.link_utilization 7.309560 -system.ruby.network.routers1.throttle0.msg_count.Control::2 1470 -system.ruby.network.routers1.throttle0.msg_count.Data::2 1466 -system.ruby.network.routers1.throttle0.msg_bytes.Control::2 11760 -system.ruby.network.routers1.throttle0.msg_bytes.Data::2 105552 -system.ruby.network.routers1.throttle1.link_utilization 7.325511 -system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 1470 -system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 1466 -system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 105840 -system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 11728 -system.ruby.network.routers2.throttle0.link_utilization 7.325511 -system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 1470 -system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 1466 -system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 105840 -system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 11728 -system.ruby.network.routers2.throttle1.link_utilization 7.309560 -system.ruby.network.routers2.throttle1.msg_count.Control::2 1470 -system.ruby.network.routers2.throttle1.msg_count.Data::2 1466 -system.ruby.network.routers2.throttle1.msg_bytes.Control::2 11760 -system.ruby.network.routers2.throttle1.msg_bytes.Data::2 105552 +system.ruby.network.routers0.percent_links_utilized 7.332987 +system.ruby.network.routers0.msg_count.Control::2 1472 +system.ruby.network.routers0.msg_count.Data::2 1468 +system.ruby.network.routers0.msg_count.Response_Data::4 1472 +system.ruby.network.routers0.msg_count.Writeback_Control::3 1468 +system.ruby.network.routers0.msg_bytes.Control::2 11776 +system.ruby.network.routers0.msg_bytes.Data::2 105696 +system.ruby.network.routers0.msg_bytes.Response_Data::4 105984 +system.ruby.network.routers0.msg_bytes.Writeback_Control::3 11744 +system.ruby.network.routers1.percent_links_utilized 7.332987 +system.ruby.network.routers1.msg_count.Control::2 1472 +system.ruby.network.routers1.msg_count.Data::2 1468 +system.ruby.network.routers1.msg_count.Response_Data::4 1472 +system.ruby.network.routers1.msg_count.Writeback_Control::3 1468 +system.ruby.network.routers1.msg_bytes.Control::2 11776 +system.ruby.network.routers1.msg_bytes.Data::2 105696 +system.ruby.network.routers1.msg_bytes.Response_Data::4 105984 +system.ruby.network.routers1.msg_bytes.Writeback_Control::3 11744 +system.ruby.network.routers2.percent_links_utilized 7.332987 +system.ruby.network.routers2.msg_count.Control::2 1472 +system.ruby.network.routers2.msg_count.Data::2 1468 +system.ruby.network.routers2.msg_count.Response_Data::4 1472 +system.ruby.network.routers2.msg_count.Writeback_Control::3 1468 +system.ruby.network.routers2.msg_bytes.Control::2 11776 +system.ruby.network.routers2.msg_bytes.Data::2 105696 +system.ruby.network.routers2.msg_bytes.Response_Data::4 105984 +system.ruby.network.routers2.msg_bytes.Writeback_Control::3 11744 +system.ruby.network.msg_count.Control 4416 +system.ruby.network.msg_count.Data 4404 +system.ruby.network.msg_count.Response_Data 4416 +system.ruby.network.msg_count.Writeback_Control 4404 +system.ruby.network.msg_byte.Control 35328 +system.ruby.network.msg_byte.Data 317088 +system.ruby.network.msg_byte.Response_Data 317952 +system.ruby.network.msg_byte.Writeback_Control 35232 +system.ruby.network.routers0.throttle0.link_utilization 7.340969 +system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1472 +system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 1468 +system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 105984 +system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 11744 +system.ruby.network.routers0.throttle1.link_utilization 7.325006 +system.ruby.network.routers0.throttle1.msg_count.Control::2 1472 +system.ruby.network.routers0.throttle1.msg_count.Data::2 1468 +system.ruby.network.routers0.throttle1.msg_bytes.Control::2 11776 +system.ruby.network.routers0.throttle1.msg_bytes.Data::2 105696 +system.ruby.network.routers1.throttle0.link_utilization 7.325006 +system.ruby.network.routers1.throttle0.msg_count.Control::2 1472 +system.ruby.network.routers1.throttle0.msg_count.Data::2 1468 +system.ruby.network.routers1.throttle0.msg_bytes.Control::2 11776 +system.ruby.network.routers1.throttle0.msg_bytes.Data::2 105696 +system.ruby.network.routers1.throttle1.link_utilization 7.340969 +system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 1472 +system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 1468 +system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 105984 +system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 11744 +system.ruby.network.routers2.throttle0.link_utilization 7.340969 +system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 1472 +system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 1468 +system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 105984 +system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 11744 +system.ruby.network.routers2.throttle1.link_utilization 7.325006 +system.ruby.network.routers2.throttle1.msg_count.Control::2 1472 +system.ruby.network.routers2.throttle1.msg_count.Data::2 1468 +system.ruby.network.routers2.throttle1.msg_bytes.Control::2 11776 +system.ruby.network.routers2.throttle1.msg_bytes.Data::2 105696 system.ruby.delayVCHist.vnet_1::bucket_size 1 # delay histogram for vnet_1 system.ruby.delayVCHist.vnet_1::max_bucket 9 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::samples 1470 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1 | 1470 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::total 1470 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::samples 1472 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1 | 1472 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::total 1472 # delay histogram for vnet_1 system.ruby.delayVCHist.vnet_2::bucket_size 1 # delay histogram for vnet_2 system.ruby.delayVCHist.vnet_2::max_bucket 9 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::samples 1466 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2 | 1466 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::total 1466 # delay histogram for vnet_2 -system.ruby.LD.latency_hist_seqr::bucket_size 32 -system.ruby.LD.latency_hist_seqr::max_bucket 319 -system.ruby.LD.latency_hist_seqr::samples 1132 -system.ruby.LD.latency_hist_seqr::mean 33.356007 -system.ruby.LD.latency_hist_seqr::gmean 9.984943 -system.ruby.LD.latency_hist_seqr::stdev 37.413851 -system.ruby.LD.latency_hist_seqr | 465 41.08% 41.08% | 534 47.17% 88.25% | 104 9.19% 97.44% | 3 0.27% 97.70% | 10 0.88% 98.59% | 8 0.71% 99.29% | 4 0.35% 99.65% | 0 0.00% 99.65% | 0 0.00% 99.65% | 4 0.35% 100.00% -system.ruby.LD.latency_hist_seqr::total 1132 +system.ruby.delayVCHist.vnet_2::samples 1468 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2 | 1468 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::total 1468 # delay histogram for vnet_2 +system.ruby.LD.latency_hist_seqr::bucket_size 64 +system.ruby.LD.latency_hist_seqr::max_bucket 639 +system.ruby.LD.latency_hist_seqr::samples 1135 +system.ruby.LD.latency_hist_seqr::mean 33.525991 +system.ruby.LD.latency_hist_seqr::gmean 10.018050 +system.ruby.LD.latency_hist_seqr::stdev 38.312060 +system.ruby.LD.latency_hist_seqr | 999 88.02% 88.02% | 116 10.22% 98.24% | 13 1.15% 99.38% | 0 0.00% 99.38% | 6 0.53% 99.91% | 1 0.09% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.latency_hist_seqr::total 1135 system.ruby.LD.hit_latency_hist_seqr::bucket_size 1 system.ruby.LD.hit_latency_hist_seqr::max_bucket 9 -system.ruby.LD.hit_latency_hist_seqr::samples 465 +system.ruby.LD.hit_latency_hist_seqr::samples 466 system.ruby.LD.hit_latency_hist_seqr::mean 1 system.ruby.LD.hit_latency_hist_seqr::gmean 1 -system.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 465 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.hit_latency_hist_seqr::total 465 -system.ruby.LD.miss_latency_hist_seqr::bucket_size 32 -system.ruby.LD.miss_latency_hist_seqr::max_bucket 319 -system.ruby.LD.miss_latency_hist_seqr::samples 667 -system.ruby.LD.miss_latency_hist_seqr::mean 55.913043 -system.ruby.LD.miss_latency_hist_seqr::gmean 49.663893 -system.ruby.LD.miss_latency_hist_seqr::stdev 33.713440 -system.ruby.LD.miss_latency_hist_seqr | 0 0.00% 0.00% | 534 80.06% 80.06% | 104 15.59% 95.65% | 3 0.45% 96.10% | 10 1.50% 97.60% | 8 1.20% 98.80% | 4 0.60% 99.40% | 0 0.00% 99.40% | 0 0.00% 99.40% | 4 0.60% 100.00% -system.ruby.LD.miss_latency_hist_seqr::total 667 -system.ruby.ST.latency_hist_seqr::bucket_size 32 -system.ruby.ST.latency_hist_seqr::max_bucket 319 +system.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 466 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.hit_latency_hist_seqr::total 466 +system.ruby.LD.miss_latency_hist_seqr::bucket_size 64 +system.ruby.LD.miss_latency_hist_seqr::max_bucket 639 +system.ruby.LD.miss_latency_hist_seqr::samples 669 +system.ruby.LD.miss_latency_hist_seqr::mean 56.182362 +system.ruby.LD.miss_latency_hist_seqr::gmean 49.875907 +system.ruby.LD.miss_latency_hist_seqr::stdev 35.208867 +system.ruby.LD.miss_latency_hist_seqr | 533 79.67% 79.67% | 116 17.34% 97.01% | 13 1.94% 98.95% | 0 0.00% 98.95% | 6 0.90% 99.85% | 1 0.15% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.miss_latency_hist_seqr::total 669 +system.ruby.ST.latency_hist_seqr::bucket_size 64 +system.ruby.ST.latency_hist_seqr::max_bucket 639 system.ruby.ST.latency_hist_seqr::samples 901 -system.ruby.ST.latency_hist_seqr::mean 12.753607 -system.ruby.ST.latency_hist_seqr::gmean 2.500911 -system.ruby.ST.latency_hist_seqr::stdev 24.939066 -system.ruby.ST.latency_hist_seqr | 684 75.92% 75.92% | 184 20.42% 96.34% | 28 3.11% 99.45% | 1 0.11% 99.56% | 1 0.11% 99.67% | 2 0.22% 99.89% | 0 0.00% 99.89% | 0 0.00% 99.89% | 1 0.11% 100.00% | 0 0.00% 100.00% +system.ruby.ST.latency_hist_seqr::mean 13.069922 +system.ruby.ST.latency_hist_seqr::gmean 2.509564 +system.ruby.ST.latency_hist_seqr::stdev 28.093942 +system.ruby.ST.latency_hist_seqr | 870 96.56% 96.56% | 27 3.00% 99.56% | 3 0.33% 99.89% | 0 0.00% 99.89% | 0 0.00% 99.89% | 0 0.00% 99.89% | 0 0.00% 99.89% | 1 0.11% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ST.latency_hist_seqr::total 901 system.ruby.ST.hit_latency_hist_seqr::bucket_size 1 system.ruby.ST.hit_latency_hist_seqr::max_bucket 9 @@ -499,45 +499,45 @@ system.ruby.ST.hit_latency_hist_seqr::mean 1 system.ruby.ST.hit_latency_hist_seqr::gmean 1 system.ruby.ST.hit_latency_hist_seqr | 0 0.00% 0.00% | 684 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ST.hit_latency_hist_seqr::total 684 -system.ruby.ST.miss_latency_hist_seqr::bucket_size 32 -system.ruby.ST.miss_latency_hist_seqr::max_bucket 319 +system.ruby.ST.miss_latency_hist_seqr::bucket_size 64 +system.ruby.ST.miss_latency_hist_seqr::max_bucket 639 system.ruby.ST.miss_latency_hist_seqr::samples 217 -system.ruby.ST.miss_latency_hist_seqr::mean 49.801843 -system.ruby.ST.miss_latency_hist_seqr::gmean 44.971096 -system.ruby.ST.miss_latency_hist_seqr::stdev 27.840525 -system.ruby.ST.miss_latency_hist_seqr | 0 0.00% 0.00% | 184 84.79% 84.79% | 28 12.90% 97.70% | 1 0.46% 98.16% | 1 0.46% 98.62% | 2 0.92% 99.54% | 0 0.00% 99.54% | 0 0.00% 99.54% | 1 0.46% 100.00% | 0 0.00% 100.00% +system.ruby.ST.miss_latency_hist_seqr::mean 51.115207 +system.ruby.ST.miss_latency_hist_seqr::gmean 45.620625 +system.ruby.ST.miss_latency_hist_seqr::stdev 37.056021 +system.ruby.ST.miss_latency_hist_seqr | 186 85.71% 85.71% | 27 12.44% 98.16% | 3 1.38% 99.54% | 0 0.00% 99.54% | 0 0.00% 99.54% | 0 0.00% 99.54% | 0 0.00% 99.54% | 1 0.46% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ST.miss_latency_hist_seqr::total 217 system.ruby.IFETCH.latency_hist_seqr::bucket_size 64 system.ruby.IFETCH.latency_hist_seqr::max_bucket 639 -system.ruby.IFETCH.latency_hist_seqr::samples 5625 -system.ruby.IFETCH.latency_hist_seqr::mean 7.715378 -system.ruby.IFETCH.latency_hist_seqr::gmean 1.529642 -system.ruby.IFETCH.latency_hist_seqr::stdev 23.186705 -system.ruby.IFETCH.latency_hist_seqr | 5481 97.44% 97.44% | 115 2.04% 99.48% | 21 0.37% 99.86% | 1 0.02% 99.88% | 5 0.09% 99.96% | 2 0.04% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.latency_hist_seqr::total 5625 +system.ruby.IFETCH.latency_hist_seqr::samples 5642 +system.ruby.IFETCH.latency_hist_seqr::mean 7.572847 +system.ruby.IFETCH.latency_hist_seqr::gmean 1.525495 +system.ruby.IFETCH.latency_hist_seqr::stdev 22.420339 +system.ruby.IFETCH.latency_hist_seqr | 5503 97.54% 97.54% | 110 1.95% 99.49% | 21 0.37% 99.86% | 4 0.07% 99.93% | 0 0.00% 99.93% | 4 0.07% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.latency_hist_seqr::total 5642 system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 1 system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 9 -system.ruby.IFETCH.hit_latency_hist_seqr::samples 5039 +system.ruby.IFETCH.hit_latency_hist_seqr::samples 5056 system.ruby.IFETCH.hit_latency_hist_seqr::mean 1 system.ruby.IFETCH.hit_latency_hist_seqr::gmean 1 -system.ruby.IFETCH.hit_latency_hist_seqr | 0 0.00% 0.00% | 5039 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.hit_latency_hist_seqr::total 5039 +system.ruby.IFETCH.hit_latency_hist_seqr | 0 0.00% 0.00% | 5056 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.hit_latency_hist_seqr::total 5056 system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 64 system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 639 system.ruby.IFETCH.miss_latency_hist_seqr::samples 586 -system.ruby.IFETCH.miss_latency_hist_seqr::mean 65.460751 -system.ruby.IFETCH.miss_latency_hist_seqr::gmean 59.138692 -system.ruby.IFETCH.miss_latency_hist_seqr::stdev 37.945521 -system.ruby.IFETCH.miss_latency_hist_seqr | 442 75.43% 75.43% | 115 19.62% 95.05% | 21 3.58% 98.63% | 1 0.17% 98.81% | 5 0.85% 99.66% | 2 0.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.miss_latency_hist_seqr::mean 64.283276 +system.ruby.IFETCH.miss_latency_hist_seqr::gmean 58.328027 +system.ruby.IFETCH.miss_latency_hist_seqr::stdev 35.386051 +system.ruby.IFETCH.miss_latency_hist_seqr | 447 76.28% 76.28% | 110 18.77% 95.05% | 21 3.58% 98.63% | 4 0.68% 99.32% | 0 0.00% 99.32% | 4 0.68% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.miss_latency_hist_seqr::total 586 system.ruby.Directory.miss_mach_latency_hist_seqr::bucket_size 64 system.ruby.Directory.miss_mach_latency_hist_seqr::max_bucket 639 -system.ruby.Directory.miss_mach_latency_hist_seqr::samples 1470 -system.ruby.Directory.miss_mach_latency_hist_seqr::mean 58.817007 -system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 52.469450 -system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 35.158300 -system.ruby.Directory.miss_mach_latency_hist_seqr | 1160 78.91% 78.91% | 251 17.07% 95.99% | 42 2.86% 98.84% | 5 0.34% 99.18% | 10 0.68% 99.86% | 2 0.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_mach_latency_hist_seqr::total 1470 +system.ruby.Directory.miss_mach_latency_hist_seqr::samples 1472 +system.ruby.Directory.miss_mach_latency_hist_seqr::mean 58.660326 +system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 52.389786 +system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 35.865583 +system.ruby.Directory.miss_mach_latency_hist_seqr | 1166 79.21% 79.21% | 253 17.19% 96.40% | 37 2.51% 98.91% | 4 0.27% 99.18% | 6 0.41% 99.59% | 5 0.34% 99.93% | 0 0.00% 99.93% | 1 0.07% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_mach_latency_hist_seqr::total 1472 system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::bucket_size 1 system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::max_bucket 9 system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::samples 1 @@ -564,53 +564,53 @@ system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::gmean system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::stdev nan system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::total 1 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size 32 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket 319 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples 667 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 55.913043 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 49.663893 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 33.713440 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 534 80.06% 80.06% | 104 15.59% 95.65% | 3 0.45% 96.10% | 10 1.50% 97.60% | 8 1.20% 98.80% | 4 0.60% 99.40% | 0 0.00% 99.40% | 0 0.00% 99.40% | 4 0.60% 100.00% -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total 667 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size 32 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket 319 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples 669 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 56.182362 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 49.875907 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 35.208867 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 533 79.67% 79.67% | 116 17.34% 97.01% | 13 1.94% 98.95% | 0 0.00% 98.95% | 6 0.90% 99.85% | 1 0.15% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total 669 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::samples 217 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 49.801843 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 44.971096 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 27.840525 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 184 84.79% 84.79% | 28 12.90% 97.70% | 1 0.46% 98.16% | 1 0.46% 98.62% | 2 0.92% 99.54% | 0 0.00% 99.54% | 0 0.00% 99.54% | 1 0.46% 100.00% | 0 0.00% 100.00% +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 51.115207 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 45.620625 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 37.056021 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 186 85.71% 85.71% | 27 12.44% 98.16% | 3 1.38% 99.54% | 0 0.00% 99.54% | 0 0.00% 99.54% | 0 0.00% 99.54% | 0 0.00% 99.54% | 1 0.46% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total 217 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::samples 586 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 65.460751 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 59.138692 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 37.945521 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 442 75.43% 75.43% | 115 19.62% 95.05% | 21 3.58% 98.63% | 1 0.17% 98.81% | 5 0.85% 99.66% | 2 0.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 64.283276 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 58.328027 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 35.386051 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 447 76.28% 76.28% | 110 18.77% 95.05% | 21 3.58% 98.63% | 4 0.68% 99.32% | 0 0.00% 99.32% | 4 0.68% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::total 586 -system.ruby.Directory_Controller.GETX 1470 0.00% 0.00% -system.ruby.Directory_Controller.PUTX 1466 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 1470 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 1466 0.00% 0.00% -system.ruby.Directory_Controller.I.GETX 1470 0.00% 0.00% -system.ruby.Directory_Controller.M.PUTX 1466 0.00% 0.00% -system.ruby.Directory_Controller.IM.Memory_Data 1470 0.00% 0.00% -system.ruby.Directory_Controller.MI.Memory_Ack 1466 0.00% 0.00% -system.ruby.L1Cache_Controller.Load 1132 0.00% 0.00% -system.ruby.L1Cache_Controller.Ifetch 5625 0.00% 0.00% +system.ruby.Directory_Controller.GETX 1472 0.00% 0.00% +system.ruby.Directory_Controller.PUTX 1468 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 1472 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 1468 0.00% 0.00% +system.ruby.Directory_Controller.I.GETX 1472 0.00% 0.00% +system.ruby.Directory_Controller.M.PUTX 1468 0.00% 0.00% +system.ruby.Directory_Controller.IM.Memory_Data 1472 0.00% 0.00% +system.ruby.Directory_Controller.MI.Memory_Ack 1468 0.00% 0.00% +system.ruby.L1Cache_Controller.Load 1135 0.00% 0.00% +system.ruby.L1Cache_Controller.Ifetch 5642 0.00% 0.00% system.ruby.L1Cache_Controller.Store 901 0.00% 0.00% -system.ruby.L1Cache_Controller.Data 1470 0.00% 0.00% -system.ruby.L1Cache_Controller.Replacement 1466 0.00% 0.00% -system.ruby.L1Cache_Controller.Writeback_Ack 1466 0.00% 0.00% -system.ruby.L1Cache_Controller.I.Load 667 0.00% 0.00% +system.ruby.L1Cache_Controller.Data 1472 0.00% 0.00% +system.ruby.L1Cache_Controller.Replacement 1468 0.00% 0.00% +system.ruby.L1Cache_Controller.Writeback_Ack 1468 0.00% 0.00% +system.ruby.L1Cache_Controller.I.Load 669 0.00% 0.00% system.ruby.L1Cache_Controller.I.Ifetch 586 0.00% 0.00% system.ruby.L1Cache_Controller.I.Store 217 0.00% 0.00% -system.ruby.L1Cache_Controller.M.Load 465 0.00% 0.00% -system.ruby.L1Cache_Controller.M.Ifetch 5039 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Load 466 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Ifetch 5056 0.00% 0.00% system.ruby.L1Cache_Controller.M.Store 684 0.00% 0.00% -system.ruby.L1Cache_Controller.M.Replacement 1466 0.00% 0.00% -system.ruby.L1Cache_Controller.MI.Writeback_Ack 1466 0.00% 0.00% -system.ruby.L1Cache_Controller.IS.Data 1253 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Replacement 1468 0.00% 0.00% +system.ruby.L1Cache_Controller.MI.Writeback_Ack 1468 0.00% 0.00% +system.ruby.L1Cache_Controller.IS.Data 1255 0.00% 0.00% system.ruby.L1Cache_Controller.IM.Data 217 0.00% 0.00% ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/config.ini index af5da1786..d2fab27ec 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/config.ini +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/config.ini @@ -88,7 +88,6 @@ clk_domain=system.cpu_clk_domain clusivity=mostly_incl demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=2 is_read_only=false max_miss_count=0 @@ -130,7 +129,6 @@ clk_domain=system.cpu_clk_domain clusivity=mostly_incl demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=2 is_read_only=true max_miss_count=0 @@ -183,7 +181,6 @@ clk_domain=system.cpu_clk_domain clusivity=mostly_incl demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=20 is_read_only=false max_miss_count=0 @@ -218,6 +215,7 @@ clk_domain=system.cpu_clk_domain eventq_index=0 forward_latency=0 frontend_latency=1 +point_of_coherency=false response_latency=1 snoop_filter=system.cpu.toL2Bus.snoop_filter snoop_response_latency=1 @@ -248,7 +246,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/dist/m5/regression/test-progs/hello/bin/mips/linux/hello +executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/hello/bin/mips/linux/hello gid=100 input=cin kvmInSE=false @@ -283,6 +281,7 @@ clk_domain=system.clk_domain eventq_index=0 forward_latency=4 frontend_latency=3 +point_of_coherency=true response_latency=2 snoop_filter=Null snoop_response_latency=4 diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/simerr b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/simerr index 0f553ea6b..1a4f96712 100755 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/simerr +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/simerr @@ -1,2 +1 @@ warn: Sockets disabled, not accepting gdb connections -warn: mmap failing: arguments not page-aligned: start 0x0 offset 0x7efefeff diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/simout b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/simout index 349ff71a4..c38df8b63 100755 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/simout +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/simout @@ -1,13 +1,15 @@ +Redirecting stdout to build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing/simout +Redirecting stderr to build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 21 2016 14:17:41 -gem5 started Jan 21 2016 14:18:13 -gem5 executing on zizzer, pid 60580 -command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing -re /z/atgutier/gem5/gem5-commit/tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing +gem5 compiled Mar 14 2016 22:04:10 +gem5 started Mar 14 2016 22:06:34 +gem5 executing on phenom, pid 29861 +command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello World! -Exiting @ tick 33912500 because target called exit() +Exiting @ tick 33932500 because target called exit() diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt index be6c762f8..dc14a2b12 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000034 # Number of seconds simulated -sim_ticks 33912500 # Number of ticks simulated -final_tick 33912500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 33932500 # Number of ticks simulated +final_tick 33932500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 109628 # Simulator instruction rate (inst/s) -host_op_rate 109584 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 660533411 # Simulator tick rate (ticks/s) -host_mem_usage 228304 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host -sim_insts 5624 # Number of instructions simulated -sim_ops 5624 # Number of ops (including micro ops) simulated +host_inst_rate 42153 # Simulator instruction rate (inst/s) +host_op_rate 42149 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 253513577 # Simulator tick rate (ticks/s) +host_mem_usage 224784 # Number of bytes of host memory used +host_seconds 0.13 # Real time elapsed on the host +sim_insts 5641 # Number of instructions simulated +sim_ops 5641 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 18752 # Number of bytes read from this memory @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 18752 # Nu system.physmem.num_reads::cpu.inst 293 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 137 # Number of read requests responded to by this memory system.physmem.num_reads::total 430 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 552952451 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 258547733 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 811500184 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 552952451 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 552952451 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 552952451 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 258547733 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 811500184 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 552626538 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 258395344 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 811021882 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 552626538 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 552626538 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 552626538 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 258395344 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 811021882 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses @@ -49,87 +49,87 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 7 # Number of system calls -system.cpu.numCycles 67825 # number of cpu cycles simulated +system.cpu.numCycles 67865 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 5624 # Number of instructions committed -system.cpu.committedOps 5624 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 4944 # Number of integer alu accesses +system.cpu.committedInsts 5641 # Number of instructions committed +system.cpu.committedOps 5641 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 4957 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 2 # Number of float alu accesses -system.cpu.num_func_calls 190 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 649 # number of instructions that are conditional controls -system.cpu.num_int_insts 4944 # number of integer instructions +system.cpu.num_func_calls 191 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 651 # number of instructions that are conditional controls +system.cpu.num_int_insts 4957 # number of integer instructions system.cpu.num_fp_insts 2 # number of float instructions -system.cpu.num_int_register_reads 7054 # number of times the integer registers were read -system.cpu.num_int_register_writes 3281 # number of times the integer registers were written +system.cpu.num_int_register_reads 7072 # number of times the integer registers were read +system.cpu.num_int_register_writes 3291 # number of times the integer registers were written system.cpu.num_fp_register_reads 3 # number of times the floating registers were read system.cpu.num_fp_register_writes 1 # number of times the floating registers were written -system.cpu.num_mem_refs 2034 # number of memory refs -system.cpu.num_load_insts 1132 # Number of load instructions +system.cpu.num_mem_refs 2037 # number of memory refs +system.cpu.num_load_insts 1135 # Number of load instructions system.cpu.num_store_insts 902 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 67825 # Number of busy cycles +system.cpu.num_busy_cycles 67865 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 883 # Number of branches fetched -system.cpu.op_class::No_OpClass 637 11.32% 11.32% # Class of executed instruction -system.cpu.op_class::IntAlu 2950 52.44% 63.77% # Class of executed instruction -system.cpu.op_class::IntMult 2 0.04% 63.80% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 63.80% # Class of executed instruction -system.cpu.op_class::FloatAdd 2 0.04% 63.84% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::MemRead 1132 20.12% 83.96% # Class of executed instruction -system.cpu.op_class::MemWrite 902 16.04% 100.00% # Class of executed instruction +system.cpu.Branches 886 # Number of branches fetched +system.cpu.op_class::No_OpClass 641 11.36% 11.36% # Class of executed instruction +system.cpu.op_class::IntAlu 2960 52.46% 63.82% # Class of executed instruction +system.cpu.op_class::IntMult 2 0.04% 63.86% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 63.86% # Class of executed instruction +system.cpu.op_class::FloatAdd 2 0.04% 63.90% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::MemRead 1135 20.12% 84.01% # Class of executed instruction +system.cpu.op_class::MemWrite 902 15.99% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 5625 # Class of executed instruction +system.cpu.op_class::total 5642 # Class of executed instruction system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 86.067027 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 1896 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 86.030444 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 1899 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 137 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 13.839416 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 13.861314 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 86.067027 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.021012 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.021012 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 86.030444 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.021004 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.021004 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 137 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 115 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.033447 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 4203 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 4203 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 1045 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1045 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 4209 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 4209 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 1048 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1048 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 851 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 851 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 1896 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1896 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1896 # number of overall hits -system.cpu.dcache.overall_hits::total 1896 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 1899 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1899 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 1899 # number of overall hits +system.cpu.dcache.overall_hits::total 1899 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 87 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 87 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 50 # number of WriteReq misses @@ -146,22 +146,22 @@ system.cpu.dcache.demand_miss_latency::cpu.data 8494000 system.cpu.dcache.demand_miss_latency::total 8494000 # number of demand (read+write) miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 8494000 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 8494000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1132 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1132 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::cpu.data 1135 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1135 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2033 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2033 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2033 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2033 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.076855 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.076855 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2036 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2036 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2036 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2036 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.076652 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.076652 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.055494 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.055494 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.067388 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.067388 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.067388 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.067388 # miss rate for overall accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.067289 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.067289 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.067289 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.067289 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62000 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 62000 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62000 # average WriteReq miss latency @@ -194,14 +194,14 @@ system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8357000 system.cpu.dcache.demand_mshr_miss_latency::total 8357000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8357000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 8357000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076855 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076855 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076652 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076652 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055494 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055494 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.067388 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.067388 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.067388 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.067388 # mshr miss rate for overall accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.067289 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.067289 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.067289 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.067289 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61000 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61000 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61000 # average WriteReq mshr miss latency @@ -212,26 +212,26 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61000 system.cpu.dcache.overall_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 13 # number of replacements -system.cpu.icache.tags.tagsinuse 129.022312 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 5331 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 128.953338 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 5348 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 295 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 18.071186 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 18.128814 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 129.022312 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.062999 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.062999 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 128.953338 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.062965 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.062965 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 282 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 105 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 177 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.137695 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 11547 # Number of tag accesses -system.cpu.icache.tags.data_accesses 11547 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 5331 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 5331 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 5331 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 5331 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 5331 # number of overall hits -system.cpu.icache.overall_hits::total 5331 # number of overall hits +system.cpu.icache.tags.tag_accesses 11581 # Number of tag accesses +system.cpu.icache.tags.data_accesses 11581 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 5348 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 5348 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 5348 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 5348 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 5348 # number of overall hits +system.cpu.icache.overall_hits::total 5348 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 295 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 295 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 295 # number of demand (read+write) misses @@ -244,18 +244,18 @@ system.cpu.icache.demand_miss_latency::cpu.inst 18192500 system.cpu.icache.demand_miss_latency::total 18192500 # number of demand (read+write) miss cycles system.cpu.icache.overall_miss_latency::cpu.inst 18192500 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 18192500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 5626 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 5626 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 5626 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 5626 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 5626 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 5626 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.052435 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.052435 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.052435 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.052435 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.052435 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.052435 # miss rate for overall accesses +system.cpu.icache.ReadReq_accesses::cpu.inst 5643 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 5643 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 5643 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 5643 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 5643 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 5643 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.052277 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.052277 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.052277 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.052277 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.052277 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.052277 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61669.491525 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total 61669.491525 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 61669.491525 # average overall miss latency @@ -284,12 +284,12 @@ system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17897500 system.cpu.icache.demand_mshr_miss_latency::total 17897500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17897500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 17897500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.052435 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.052435 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.052435 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.052435 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.052435 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.052435 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.052277 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.052277 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.052277 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.052277 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.052277 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.052277 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60669.491525 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60669.491525 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60669.491525 # average overall mshr miss latency @@ -298,16 +298,16 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60669.491525 system.cpu.icache.overall_avg_mshr_miss_latency::total 60669.491525 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 183.581605 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 183.490494 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 15 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 380 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.039474 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 130.156658 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 53.424948 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003972 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 130.087016 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 53.403478 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003970 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.001630 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.005602 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.005600 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 380 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 255 # Occupied blocks per task id diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/simout b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/simout index 39d3a0691..a1fd37503 100755 --- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/simout +++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/simout @@ -1,9 +1,11 @@ +Redirecting stdout to build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing-mt/simout +Redirecting stderr to build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing-mt/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 13 2016 22:43:13 -gem5 started Mar 13 2016 22:49:02 -gem5 executing on phenom, pid 19910 +gem5 compiled Mar 14 2016 21:54:46 +gem5 started Mar 14 2016 21:58:29 +gem5 executing on phenom, pid 28223 command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing-mt -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing-mt Global frequency set at 1000000000000 ticks per second @@ -12,4 +14,4 @@ info: Increasing stack size by one page. info: Increasing stack size by one page. Hello world! Hello world! -Exiting @ tick 24832500 because target called exit() +Exiting @ tick 24794500 because target called exit() diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/stats.txt b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/stats.txt index 82bc89dfe..7854782f4 100644 --- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/stats.txt +++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/stats.txt @@ -1,55 +1,55 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000025 # Number of seconds simulated -sim_ticks 24832500 # Number of ticks simulated -final_tick 24832500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 24794500 # Number of ticks simulated +final_tick 24794500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 23208 # Simulator instruction rate (inst/s) -host_op_rate 23207 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 45219113 # Simulator tick rate (ticks/s) -host_mem_usage 229684 # Number of bytes of host memory used -host_seconds 0.55 # Real time elapsed on the host -sim_insts 12744 # Number of instructions simulated -sim_ops 12744 # Number of ops (including micro ops) simulated +host_inst_rate 50796 # Simulator instruction rate (inst/s) +host_op_rate 50792 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 98611945 # Simulator tick rate (ticks/s) +host_mem_usage 229596 # Number of bytes of host memory used +host_seconds 0.25 # Real time elapsed on the host +sim_insts 12770 # Number of instructions simulated +sim_ops 12770 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 40448 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 22016 # Number of bytes read from this memory -system.physmem.bytes_read::total 62464 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 40448 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 40448 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 632 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 344 # Number of read requests responded to by this memory -system.physmem.num_reads::total 976 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1628833182 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 886580087 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2515413269 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1628833182 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1628833182 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1628833182 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 886580087 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2515413269 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 976 # Number of read requests accepted +system.physmem.bytes_read::cpu.inst 40320 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 22080 # Number of bytes read from this memory +system.physmem.bytes_read::total 62400 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 40320 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 40320 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 630 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 345 # Number of read requests responded to by this memory +system.physmem.num_reads::total 975 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1626167094 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 890520075 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2516687169 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1626167094 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1626167094 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1626167094 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 890520075 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2516687169 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 975 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 976 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 975 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 62464 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 62400 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 62464 # Total read bytes from the system interface side +system.physmem.bytesReadSys 62400 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 84 # Per bank write bursts -system.physmem.perBankRdBursts::1 152 # Per bank write bursts +system.physmem.perBankRdBursts::0 85 # Per bank write bursts +system.physmem.perBankRdBursts::1 151 # Per bank write bursts system.physmem.perBankRdBursts::2 78 # Per bank write bursts system.physmem.perBankRdBursts::3 59 # Per bank write bursts -system.physmem.perBankRdBursts::4 88 # Per bank write bursts -system.physmem.perBankRdBursts::5 48 # Per bank write bursts -system.physmem.perBankRdBursts::6 33 # Per bank write bursts +system.physmem.perBankRdBursts::4 86 # Per bank write bursts +system.physmem.perBankRdBursts::5 49 # Per bank write bursts +system.physmem.perBankRdBursts::6 32 # Per bank write bursts system.physmem.perBankRdBursts::7 50 # Per bank write bursts -system.physmem.perBankRdBursts::8 42 # Per bank write bursts +system.physmem.perBankRdBursts::8 43 # Per bank write bursts system.physmem.perBankRdBursts::9 39 # Per bank write bursts system.physmem.perBankRdBursts::10 29 # Per bank write bursts system.physmem.perBankRdBursts::11 34 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 24688000 # Total gap between requests +system.physmem.totGap 24650000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 976 # Read request sizes (log2) +system.physmem.readPktSize::6 975 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,14 +90,14 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 340 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 321 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 209 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 78 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 21 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 7 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 354 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 330 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 188 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 71 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 20 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 8 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see @@ -186,100 +186,100 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 217 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 280.184332 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 175.894103 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 284.655938 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 78 35.94% 35.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 61 28.11% 64.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 19 8.76% 72.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 11 5.07% 77.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 14 6.45% 84.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 13 5.99% 90.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 4 1.84% 92.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 6 2.76% 94.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 11 5.07% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 217 # Bytes accessed per row activation -system.physmem.totQLat 12728500 # Total ticks spent queuing -system.physmem.totMemAccLat 31028500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 4880000 # Total ticks spent in databus transfers -system.physmem.avgQLat 13041.50 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 215 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 283.088372 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 180.093050 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 284.959526 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 71 33.02% 33.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 62 28.84% 61.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 23 10.70% 72.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 14 6.51% 79.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 10 4.65% 83.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 14 6.51% 90.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 5 2.33% 92.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 3 1.40% 93.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 13 6.05% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 215 # Bytes accessed per row activation +system.physmem.totQLat 13049000 # Total ticks spent queuing +system.physmem.totMemAccLat 31330250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 4875000 # Total ticks spent in databus transfers +system.physmem.avgQLat 13383.59 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31791.50 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2515.41 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 32133.59 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2516.69 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2515.41 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 2516.69 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 19.65 # Data bus utilization in percentage -system.physmem.busUtilRead 19.65 # Data bus utilization in percentage for reads +system.physmem.busUtil 19.66 # Data bus utilization in percentage +system.physmem.busUtilRead 19.66 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 2.42 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 749 # Number of row buffer hits during reads +system.physmem.readRowHits 751 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 76.74 # Row buffer hit rate for reads +system.physmem.readRowHitRate 77.03 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 25295.08 # Average gap between requests -system.physmem.pageHitRate 76.74 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 892080 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 486750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 4516200 # Energy for read commands per rank (pJ) +system.physmem.avgGap 25282.05 # Average gap between requests +system.physmem.pageHitRate 77.03 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 899640 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 490875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 4531800 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 16092810 # Energy for active background per rank (pJ) +system.physmem_0.actBackEnergy 16120170 # Energy for active background per rank (pJ) system.physmem_0.preBackEnergy 54750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 23568270 # Total energy per rank (pJ) -system.physmem_0.averagePower 997.862715 # Core power per rank (mW) +system.physmem_0.totalEnergy 23622915 # Total energy per rank (pJ) +system.physmem_0.averagePower 998.485338 # Core power per rank (mW) system.physmem_0.memoryStateTime::IDLE 22500 # Time in different power states system.physmem_0.memoryStateTime::REF 780000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 22830000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 22869500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 718200 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 391875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 2847000 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 703080 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 383625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 2854800 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 15524235 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 557250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 21564240 # Total energy per rank (pJ) -system.physmem_1.averagePower 912.772063 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 830500 # Time in different power states +system.physmem_1.actBackEnergy 15614010 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 495000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 21576195 # Total energy per rank (pJ) +system.physmem_1.averagePower 912.216256 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 727500 # Time in different power states system.physmem_1.memoryStateTime::REF 780000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 22027750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 22158250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 6978 # Number of BP lookups -system.cpu.branchPred.condPredicted 3979 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1366 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 5343 # Number of BTB lookups -system.cpu.branchPred.BTBHits 988 # Number of BTB hits +system.cpu.branchPred.lookups 6577 # Number of BP lookups +system.cpu.branchPred.condPredicted 3752 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1243 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 4859 # Number of BTB lookups +system.cpu.branchPred.BTBHits 1038 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 18.491484 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1115 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 79 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 21.362420 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1078 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 78 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 4756 # DTB read hits -system.cpu.dtb.read_misses 94 # DTB read misses +system.cpu.dtb.read_hits 4547 # DTB read hits +system.cpu.dtb.read_misses 85 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 4850 # DTB read accesses -system.cpu.dtb.write_hits 2093 # DTB write hits +system.cpu.dtb.read_accesses 4632 # DTB read accesses +system.cpu.dtb.write_hits 2078 # DTB write hits system.cpu.dtb.write_misses 69 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 2162 # DTB write accesses -system.cpu.dtb.data_hits 6849 # DTB hits -system.cpu.dtb.data_misses 163 # DTB misses +system.cpu.dtb.write_accesses 2147 # DTB write accesses +system.cpu.dtb.data_hits 6625 # DTB hits +system.cpu.dtb.data_misses 154 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 7012 # DTB accesses -system.cpu.itb.fetch_hits 5404 # ITB hits -system.cpu.itb.fetch_misses 57 # ITB misses +system.cpu.dtb.data_accesses 6779 # DTB accesses +system.cpu.itb.fetch_hits 5175 # ITB hits +system.cpu.itb.fetch_misses 51 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 5461 # ITB accesses +system.cpu.itb.fetch_accesses 5226 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -294,432 +294,432 @@ system.cpu.itb.data_acv 0 # DT system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload0.num_syscalls 17 # Number of system calls system.cpu.workload1.num_syscalls 17 # Number of system calls -system.cpu.numCycles 49666 # number of cpu cycles simulated +system.cpu.numCycles 49590 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 1235 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 39551 # Number of instructions fetch has processed -system.cpu.fetch.Branches 6978 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 2103 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 10833 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1446 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 389 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.CacheLines 5404 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 838 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 27534 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.436442 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.801385 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 1137 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 37512 # Number of instructions fetch has processed +system.cpu.fetch.Branches 6577 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 2116 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 11769 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1328 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 489 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.CacheLines 5175 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 779 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 28288 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.326075 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.708941 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 20751 75.37% 75.37% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 584 2.12% 77.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 426 1.55% 79.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 584 2.12% 81.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 571 2.07% 83.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 441 1.60% 84.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 491 1.78% 86.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 560 2.03% 88.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 3126 11.35% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 21788 77.02% 77.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 562 1.99% 79.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 445 1.57% 80.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 567 2.00% 82.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 586 2.07% 84.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 389 1.38% 86.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 492 1.74% 87.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 554 1.96% 89.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 2905 10.27% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 27534 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.140499 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.796340 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 37297 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 10659 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 5112 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 614 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1127 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 528 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 328 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 32206 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 725 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1127 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 37872 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 4968 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 1226 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 5150 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 4466 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 30281 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 78 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 324 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 847 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 3132 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 22821 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 37713 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 37695 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 28288 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.132628 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.756443 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 38487 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 11291 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 4912 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 546 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1060 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 470 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 278 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 30785 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 643 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1060 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 39027 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 4538 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 1512 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 4932 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 5227 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 29058 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 36 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 481 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 927 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 3808 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 21804 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 36221 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 36203 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 16 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 9140 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 13681 # Number of HB maps that are undone due to squashing +system.cpu.rename.CommittedMaps 9154 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 12650 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 60 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 48 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 2263 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2834 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1407 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 13 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 7 # Number of conflicting stores. -system.cpu.memDep1.insertedLoads 2862 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep1.insertedStores 1462 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep1.conflictingLoads 2 # Number of conflicting loads. -system.cpu.memDep1.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 27015 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 50 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 22338 # Number of instructions issued +system.cpu.rename.skidInsts 2095 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2679 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1390 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 4 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. +system.cpu.memDep1.insertedLoads 2734 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep1.insertedStores 1411 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep1.conflictingLoads 10 # Number of conflicting loads. +system.cpu.memDep1.conflictingStores 4 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 25901 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 52 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 21580 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 130 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 14320 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 8141 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 16 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 27534 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.811288 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.520707 # Number of insts issued each cycle +system.cpu.iq.iqSquashedInstsExamined 13182 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 7478 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 18 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 28288 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.762868 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.484406 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 19179 69.66% 69.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 2638 9.58% 79.24% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 1919 6.97% 86.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 1327 4.82% 91.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 1227 4.46% 95.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 711 2.58% 98.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 354 1.29% 99.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 138 0.50% 99.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 41 0.15% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 20144 71.21% 71.21% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 2630 9.30% 80.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 1862 6.58% 87.09% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 1311 4.63% 91.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 1169 4.13% 95.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 655 2.32% 98.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 329 1.16% 99.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 136 0.48% 99.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 52 0.18% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 27534 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 28288 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 32 9.64% 9.64% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 9.64% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 9.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 9.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 9.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 9.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 9.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 9.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 9.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 9.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 9.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 9.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 9.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 9.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 9.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 9.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 9.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 9.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 9.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 9.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.64% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 217 65.36% 75.00% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 83 25.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 37 11.97% 11.97% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 11.97% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 11.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 11.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 11.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 11.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.97% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 189 61.17% 73.14% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 83 26.86% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 7321 66.01% 66.03% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.01% 66.04% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.04% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 66.06% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.06% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.06% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.06% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.06% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.06% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2641 23.81% 89.87% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1123 10.13% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 7104 66.24% 66.26% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.01% 66.27% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 66.29% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.29% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.29% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.29% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.29% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.29% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2483 23.15% 89.44% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1132 10.56% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 11090 # Type of FU issued +system.cpu.iq.FU_type_0::total 10724 # Type of FU issued system.cpu.iq.FU_type_1::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_1::IntAlu 7446 66.20% 66.22% # Type of FU issued -system.cpu.iq.FU_type_1::IntMult 1 0.01% 66.23% # Type of FU issued -system.cpu.iq.FU_type_1::IntDiv 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_1::FloatAdd 2 0.02% 66.24% # Type of FU issued -system.cpu.iq.FU_type_1::FloatCmp 0 0.00% 66.24% # Type of FU issued -system.cpu.iq.FU_type_1::FloatCvt 0 0.00% 66.24% # Type of FU issued -system.cpu.iq.FU_type_1::FloatMult 0 0.00% 66.24% # Type of FU issued -system.cpu.iq.FU_type_1::FloatDiv 0 0.00% 66.24% # Type of FU issued -system.cpu.iq.FU_type_1::FloatSqrt 0 0.00% 66.24% # Type of FU issued -system.cpu.iq.FU_type_1::SimdAdd 0 0.00% 66.24% # Type of FU issued -system.cpu.iq.FU_type_1::SimdAddAcc 0 0.00% 66.24% # Type of FU issued -system.cpu.iq.FU_type_1::SimdAlu 0 0.00% 66.24% # Type of FU issued -system.cpu.iq.FU_type_1::SimdCmp 0 0.00% 66.24% # Type of FU issued -system.cpu.iq.FU_type_1::SimdCvt 0 0.00% 66.24% # Type of FU issued -system.cpu.iq.FU_type_1::SimdMisc 0 0.00% 66.24% # Type of FU issued -system.cpu.iq.FU_type_1::SimdMult 0 0.00% 66.24% # Type of FU issued -system.cpu.iq.FU_type_1::SimdMultAcc 0 0.00% 66.24% # Type of FU issued -system.cpu.iq.FU_type_1::SimdShift 0 0.00% 66.24% # Type of FU issued -system.cpu.iq.FU_type_1::SimdShiftAcc 0 0.00% 66.24% # Type of FU issued -system.cpu.iq.FU_type_1::SimdSqrt 0 0.00% 66.24% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatAdd 0 0.00% 66.24% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatAlu 0 0.00% 66.24% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatCmp 0 0.00% 66.24% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatCvt 0 0.00% 66.24% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatDiv 0 0.00% 66.24% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatMisc 0 0.00% 66.24% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatMult 0 0.00% 66.24% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatMultAcc 0 0.00% 66.24% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatSqrt 0 0.00% 66.24% # Type of FU issued -system.cpu.iq.FU_type_1::MemRead 2645 23.52% 89.76% # Type of FU issued -system.cpu.iq.FU_type_1::MemWrite 1152 10.24% 100.00% # Type of FU issued +system.cpu.iq.FU_type_1::IntAlu 7199 66.31% 66.33% # Type of FU issued +system.cpu.iq.FU_type_1::IntMult 1 0.01% 66.34% # Type of FU issued +system.cpu.iq.FU_type_1::IntDiv 0 0.00% 66.34% # Type of FU issued +system.cpu.iq.FU_type_1::FloatAdd 2 0.02% 66.36% # Type of FU issued +system.cpu.iq.FU_type_1::FloatCmp 0 0.00% 66.36% # Type of FU issued +system.cpu.iq.FU_type_1::FloatCvt 0 0.00% 66.36% # Type of FU issued +system.cpu.iq.FU_type_1::FloatMult 0 0.00% 66.36% # Type of FU issued +system.cpu.iq.FU_type_1::FloatDiv 0 0.00% 66.36% # Type of FU issued +system.cpu.iq.FU_type_1::FloatSqrt 0 0.00% 66.36% # Type of FU issued +system.cpu.iq.FU_type_1::SimdAdd 0 0.00% 66.36% # Type of FU issued +system.cpu.iq.FU_type_1::SimdAddAcc 0 0.00% 66.36% # Type of FU issued +system.cpu.iq.FU_type_1::SimdAlu 0 0.00% 66.36% # Type of FU issued +system.cpu.iq.FU_type_1::SimdCmp 0 0.00% 66.36% # Type of FU issued +system.cpu.iq.FU_type_1::SimdCvt 0 0.00% 66.36% # Type of FU issued +system.cpu.iq.FU_type_1::SimdMisc 0 0.00% 66.36% # Type of FU issued +system.cpu.iq.FU_type_1::SimdMult 0 0.00% 66.36% # Type of FU issued +system.cpu.iq.FU_type_1::SimdMultAcc 0 0.00% 66.36% # Type of FU issued +system.cpu.iq.FU_type_1::SimdShift 0 0.00% 66.36% # Type of FU issued +system.cpu.iq.FU_type_1::SimdShiftAcc 0 0.00% 66.36% # Type of FU issued +system.cpu.iq.FU_type_1::SimdSqrt 0 0.00% 66.36% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatAdd 0 0.00% 66.36% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatAlu 0 0.00% 66.36% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatCmp 0 0.00% 66.36% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatCvt 0 0.00% 66.36% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatDiv 0 0.00% 66.36% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatMisc 0 0.00% 66.36% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatMult 0 0.00% 66.36% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatMultAcc 0 0.00% 66.36% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatSqrt 0 0.00% 66.36% # Type of FU issued +system.cpu.iq.FU_type_1::MemRead 2532 23.32% 89.68% # Type of FU issued +system.cpu.iq.FU_type_1::MemWrite 1120 10.32% 100.00% # Type of FU issued system.cpu.iq.FU_type_1::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_1::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_1::total 11248 # Type of FU issued -system.cpu.iq.FU_type::total 22338 0.00% 0.00% # Type of FU issued -system.cpu.iq.rate 0.449764 # Inst issue rate -system.cpu.iq.fu_busy_cnt::0 166 # FU busy when requested -system.cpu.iq.fu_busy_cnt::1 166 # FU busy when requested -system.cpu.iq.fu_busy_cnt::total 332 # FU busy when requested -system.cpu.iq.fu_busy_rate::0 0.007431 # FU busy rate (busy events/executed inst) -system.cpu.iq.fu_busy_rate::1 0.007431 # FU busy rate (busy events/executed inst) -system.cpu.iq.fu_busy_rate::total 0.014863 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 72630 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 41400 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 19613 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_1::total 10856 # Type of FU issued +system.cpu.iq.FU_type::total 21580 0.00% 0.00% # Type of FU issued +system.cpu.iq.rate 0.435168 # Inst issue rate +system.cpu.iq.fu_busy_cnt::0 153 # FU busy when requested +system.cpu.iq.fu_busy_cnt::1 156 # FU busy when requested +system.cpu.iq.fu_busy_cnt::total 309 # FU busy when requested +system.cpu.iq.fu_busy_rate::0 0.007090 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_busy_rate::1 0.007229 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_busy_rate::total 0.014319 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 71845 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 39156 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 19068 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 42 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 20 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 20 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 22644 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 21863 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 22 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 80 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 63 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1651 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 20 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 542 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1494 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 18 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 525 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 309 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread1.forwLoads 73 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.cacheBlocked 275 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread1.forwLoads 81 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread1.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread1.squashedLoads 1679 # Number of loads squashed -system.cpu.iew.lsq.thread1.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread1.memOrderViolation 17 # Number of memory ordering violations -system.cpu.iew.lsq.thread1.squashedStores 597 # Number of stores squashed +system.cpu.iew.lsq.thread1.squashedLoads 1549 # Number of loads squashed +system.cpu.iew.lsq.thread1.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread1.memOrderViolation 25 # Number of memory ordering violations +system.cpu.iew.lsq.thread1.squashedStores 546 # Number of stores squashed system.cpu.iew.lsq.thread1.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread1.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread1.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread1.cacheBlocked 327 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread1.cacheBlocked 273 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1127 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 2708 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 614 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 27211 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 237 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 5696 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 2869 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 50 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 33 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 589 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 37 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 160 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1089 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1249 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 21052 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts::0 2447 # Number of load instructions executed -system.cpu.iew.iewExecLoadInsts::1 2411 # Number of load instructions executed -system.cpu.iew.iewExecLoadInsts::total 4858 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1286 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1060 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 2492 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 405 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 26102 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 214 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 5413 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 2801 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 52 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 25 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 387 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 43 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 158 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1006 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1164 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 20390 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts::0 2303 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts::1 2335 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts::total 4638 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1190 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp::0 0 # number of swp insts executed system.cpu.iew.exec_swp::1 0 # number of swp insts executed system.cpu.iew.exec_swp::total 0 # number of swp insts executed -system.cpu.iew.exec_nop::0 74 # number of nop insts executed -system.cpu.iew.exec_nop::1 72 # number of nop insts executed -system.cpu.iew.exec_nop::total 146 # number of nop insts executed -system.cpu.iew.exec_refs::0 3514 # number of memory reference insts executed -system.cpu.iew.exec_refs::1 3522 # number of memory reference insts executed -system.cpu.iew.exec_refs::total 7036 # number of memory reference insts executed -system.cpu.iew.exec_branches::0 1644 # Number of branches executed -system.cpu.iew.exec_branches::1 1639 # Number of branches executed -system.cpu.iew.exec_branches::total 3283 # Number of branches executed -system.cpu.iew.exec_stores::0 1067 # Number of stores executed -system.cpu.iew.exec_stores::1 1111 # Number of stores executed -system.cpu.iew.exec_stores::total 2178 # Number of stores executed -system.cpu.iew.exec_rate 0.423871 # Inst execution rate -system.cpu.iew.wb_sent::0 9939 # cumulative count of insts sent to commit -system.cpu.iew.wb_sent::1 10068 # cumulative count of insts sent to commit -system.cpu.iew.wb_sent::total 20007 # cumulative count of insts sent to commit -system.cpu.iew.wb_count::0 9740 # cumulative count of insts written-back -system.cpu.iew.wb_count::1 9893 # cumulative count of insts written-back -system.cpu.iew.wb_count::total 19633 # cumulative count of insts written-back -system.cpu.iew.wb_producers::0 5189 # num instructions producing a value -system.cpu.iew.wb_producers::1 5256 # num instructions producing a value -system.cpu.iew.wb_producers::total 10445 # num instructions producing a value -system.cpu.iew.wb_consumers::0 6868 # num instructions consuming a value -system.cpu.iew.wb_consumers::1 6926 # num instructions consuming a value -system.cpu.iew.wb_consumers::total 13794 # num instructions consuming a value -system.cpu.iew.wb_rate::0 0.196110 # insts written-back per cycle -system.cpu.iew.wb_rate::1 0.199191 # insts written-back per cycle -system.cpu.iew.wb_rate::total 0.395301 # insts written-back per cycle -system.cpu.iew.wb_fanout::0 0.755533 # average fanout of values written-back -system.cpu.iew.wb_fanout::1 0.758880 # average fanout of values written-back -system.cpu.iew.wb_fanout::total 0.757213 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 14447 # The number of squashed insts skipped by commit +system.cpu.iew.exec_nop::0 75 # number of nop insts executed +system.cpu.iew.exec_nop::1 74 # number of nop insts executed +system.cpu.iew.exec_nop::total 149 # number of nop insts executed +system.cpu.iew.exec_refs::0 3395 # number of memory reference insts executed +system.cpu.iew.exec_refs::1 3403 # number of memory reference insts executed +system.cpu.iew.exec_refs::total 6798 # number of memory reference insts executed +system.cpu.iew.exec_branches::0 1585 # Number of branches executed +system.cpu.iew.exec_branches::1 1614 # Number of branches executed +system.cpu.iew.exec_branches::total 3199 # Number of branches executed +system.cpu.iew.exec_stores::0 1092 # Number of stores executed +system.cpu.iew.exec_stores::1 1068 # Number of stores executed +system.cpu.iew.exec_stores::total 2160 # Number of stores executed +system.cpu.iew.exec_rate 0.411172 # Inst execution rate +system.cpu.iew.wb_sent::0 9687 # cumulative count of insts sent to commit +system.cpu.iew.wb_sent::1 9764 # cumulative count of insts sent to commit +system.cpu.iew.wb_sent::total 19451 # cumulative count of insts sent to commit +system.cpu.iew.wb_count::0 9532 # cumulative count of insts written-back +system.cpu.iew.wb_count::1 9556 # cumulative count of insts written-back +system.cpu.iew.wb_count::total 19088 # cumulative count of insts written-back +system.cpu.iew.wb_producers::0 5025 # num instructions producing a value +system.cpu.iew.wb_producers::1 5077 # num instructions producing a value +system.cpu.iew.wb_producers::total 10102 # num instructions producing a value +system.cpu.iew.wb_consumers::0 6671 # num instructions consuming a value +system.cpu.iew.wb_consumers::1 6701 # num instructions consuming a value +system.cpu.iew.wb_consumers::total 13372 # num instructions consuming a value +system.cpu.iew.wb_rate::0 0.192216 # insts written-back per cycle +system.cpu.iew.wb_rate::1 0.192700 # insts written-back per cycle +system.cpu.iew.wb_rate::total 0.384916 # insts written-back per cycle +system.cpu.iew.wb_fanout::0 0.753260 # average fanout of values written-back +system.cpu.iew.wb_fanout::1 0.757648 # average fanout of values written-back +system.cpu.iew.wb_fanout::total 0.755459 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 13275 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 34 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1048 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 27467 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.465213 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.343088 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 976 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 28256 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.453143 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.335890 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 22438 81.69% 81.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 2371 8.63% 90.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 1089 3.96% 94.29% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 414 1.51% 95.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 277 1.01% 96.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 199 0.72% 97.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 197 0.72% 98.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 154 0.56% 98.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 328 1.19% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 23155 81.95% 81.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 2552 9.03% 90.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 1012 3.58% 94.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 380 1.34% 95.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 269 0.95% 96.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 177 0.63% 97.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 194 0.69% 98.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 173 0.61% 98.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 344 1.22% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 27467 # Number of insts commited each cycle -system.cpu.commit.committedInsts::0 6389 # Number of instructions committed -system.cpu.commit.committedInsts::1 6389 # Number of instructions committed -system.cpu.commit.committedInsts::total 12778 # Number of instructions committed -system.cpu.commit.committedOps::0 6389 # Number of ops (including micro ops) committed -system.cpu.commit.committedOps::1 6389 # Number of ops (including micro ops) committed -system.cpu.commit.committedOps::total 12778 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 28256 # Number of insts commited each cycle +system.cpu.commit.committedInsts::0 6402 # Number of instructions committed +system.cpu.commit.committedInsts::1 6402 # Number of instructions committed +system.cpu.commit.committedInsts::total 12804 # Number of instructions committed +system.cpu.commit.committedOps::0 6402 # Number of ops (including micro ops) committed +system.cpu.commit.committedOps::1 6402 # Number of ops (including micro ops) committed +system.cpu.commit.committedOps::total 12804 # Number of ops (including micro ops) committed system.cpu.commit.swp_count::0 0 # Number of s/w prefetches committed system.cpu.commit.swp_count::1 0 # Number of s/w prefetches committed system.cpu.commit.swp_count::total 0 # Number of s/w prefetches committed -system.cpu.commit.refs::0 2048 # Number of memory references committed -system.cpu.commit.refs::1 2048 # Number of memory references committed -system.cpu.commit.refs::total 4096 # Number of memory references committed -system.cpu.commit.loads::0 1183 # Number of loads committed -system.cpu.commit.loads::1 1183 # Number of loads committed -system.cpu.commit.loads::total 2366 # Number of loads committed +system.cpu.commit.refs::0 2050 # Number of memory references committed +system.cpu.commit.refs::1 2050 # Number of memory references committed +system.cpu.commit.refs::total 4100 # Number of memory references committed +system.cpu.commit.loads::0 1185 # Number of loads committed +system.cpu.commit.loads::1 1185 # Number of loads committed +system.cpu.commit.loads::total 2370 # Number of loads committed system.cpu.commit.membars::0 0 # Number of memory barriers committed system.cpu.commit.membars::1 0 # Number of memory barriers committed system.cpu.commit.membars::total 0 # Number of memory barriers committed -system.cpu.commit.branches::0 1050 # Number of branches committed -system.cpu.commit.branches::1 1050 # Number of branches committed -system.cpu.commit.branches::total 2100 # Number of branches committed +system.cpu.commit.branches::0 1056 # Number of branches committed +system.cpu.commit.branches::1 1056 # Number of branches committed +system.cpu.commit.branches::total 2112 # Number of branches committed system.cpu.commit.fp_insts::0 10 # Number of committed floating point instructions. system.cpu.commit.fp_insts::1 10 # Number of committed floating point instructions. system.cpu.commit.fp_insts::total 20 # Number of committed floating point instructions. -system.cpu.commit.int_insts::0 6307 # Number of committed integer instructions. -system.cpu.commit.int_insts::1 6307 # Number of committed integer instructions. -system.cpu.commit.int_insts::total 12614 # Number of committed integer instructions. +system.cpu.commit.int_insts::0 6319 # Number of committed integer instructions. +system.cpu.commit.int_insts::1 6319 # Number of committed integer instructions. +system.cpu.commit.int_insts::total 12638 # Number of committed integer instructions. system.cpu.commit.function_calls::0 127 # Number of function calls committed. system.cpu.commit.function_calls::1 127 # Number of function calls committed. system.cpu.commit.function_calls::total 254 # Number of function calls committed. system.cpu.commit.op_class_0::No_OpClass 19 0.30% 0.30% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 4319 67.60% 67.90% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 1 0.02% 67.91% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 0 0.00% 67.91% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 2 0.03% 67.94% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCmp 0 0.00% 67.94% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCvt 0 0.00% 67.94% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMult 0 0.00% 67.94% # Class of committed instruction -system.cpu.commit.op_class_0::FloatDiv 0 0.00% 67.94% # Class of committed instruction -system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 67.94% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAdd 0 0.00% 67.94% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 67.94% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAlu 0 0.00% 67.94% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCmp 0 0.00% 67.94% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCvt 0 0.00% 67.94% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMisc 0 0.00% 67.94% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMult 0 0.00% 67.94% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 67.94% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShift 0 0.00% 67.94% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 67.94% # Class of committed instruction -system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 67.94% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 67.94% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 67.94% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 67.94% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 67.94% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 67.94% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 67.94% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 67.94% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.94% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.94% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 1183 18.52% 86.46% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 865 13.54% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 4330 67.64% 67.93% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 1 0.02% 67.95% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 0 0.00% 67.95% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 2 0.03% 67.98% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 67.98% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 67.98% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 67.98% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 67.98% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 67.98% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 67.98% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 67.98% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 67.98% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 67.98% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 67.98% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 67.98% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 67.98% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 67.98% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 67.98% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 67.98% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 67.98% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 67.98% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 67.98% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 67.98% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 67.98% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 67.98% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 67.98% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 67.98% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.98% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.98% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 1185 18.51% 86.49% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 865 13.51% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 6389 # Class of committed instruction +system.cpu.commit.op_class_0::total 6402 # Class of committed instruction system.cpu.commit.op_class_1::No_OpClass 19 0.30% 0.30% # Class of committed instruction -system.cpu.commit.op_class_1::IntAlu 4319 67.60% 67.90% # Class of committed instruction -system.cpu.commit.op_class_1::IntMult 1 0.02% 67.91% # Class of committed instruction -system.cpu.commit.op_class_1::IntDiv 0 0.00% 67.91% # Class of committed instruction -system.cpu.commit.op_class_1::FloatAdd 2 0.03% 67.94% # Class of committed instruction -system.cpu.commit.op_class_1::FloatCmp 0 0.00% 67.94% # Class of committed instruction -system.cpu.commit.op_class_1::FloatCvt 0 0.00% 67.94% # Class of committed instruction -system.cpu.commit.op_class_1::FloatMult 0 0.00% 67.94% # Class of committed instruction -system.cpu.commit.op_class_1::FloatDiv 0 0.00% 67.94% # Class of committed instruction -system.cpu.commit.op_class_1::FloatSqrt 0 0.00% 67.94% # Class of committed instruction -system.cpu.commit.op_class_1::SimdAdd 0 0.00% 67.94% # Class of committed instruction -system.cpu.commit.op_class_1::SimdAddAcc 0 0.00% 67.94% # Class of committed instruction -system.cpu.commit.op_class_1::SimdAlu 0 0.00% 67.94% # Class of committed instruction -system.cpu.commit.op_class_1::SimdCmp 0 0.00% 67.94% # Class of committed instruction -system.cpu.commit.op_class_1::SimdCvt 0 0.00% 67.94% # Class of committed instruction -system.cpu.commit.op_class_1::SimdMisc 0 0.00% 67.94% # Class of committed instruction -system.cpu.commit.op_class_1::SimdMult 0 0.00% 67.94% # Class of committed instruction -system.cpu.commit.op_class_1::SimdMultAcc 0 0.00% 67.94% # Class of committed instruction -system.cpu.commit.op_class_1::SimdShift 0 0.00% 67.94% # Class of committed instruction -system.cpu.commit.op_class_1::SimdShiftAcc 0 0.00% 67.94% # Class of committed instruction -system.cpu.commit.op_class_1::SimdSqrt 0 0.00% 67.94% # Class of committed instruction -system.cpu.commit.op_class_1::SimdFloatAdd 0 0.00% 67.94% # Class of committed instruction -system.cpu.commit.op_class_1::SimdFloatAlu 0 0.00% 67.94% # Class of committed instruction -system.cpu.commit.op_class_1::SimdFloatCmp 0 0.00% 67.94% # Class of committed instruction -system.cpu.commit.op_class_1::SimdFloatCvt 0 0.00% 67.94% # Class of committed instruction -system.cpu.commit.op_class_1::SimdFloatDiv 0 0.00% 67.94% # Class of committed instruction -system.cpu.commit.op_class_1::SimdFloatMisc 0 0.00% 67.94% # Class of committed instruction -system.cpu.commit.op_class_1::SimdFloatMult 0 0.00% 67.94% # Class of committed instruction -system.cpu.commit.op_class_1::SimdFloatMultAcc 0 0.00% 67.94% # Class of committed instruction -system.cpu.commit.op_class_1::SimdFloatSqrt 0 0.00% 67.94% # Class of committed instruction -system.cpu.commit.op_class_1::MemRead 1183 18.52% 86.46% # Class of committed instruction -system.cpu.commit.op_class_1::MemWrite 865 13.54% 100.00% # Class of committed instruction +system.cpu.commit.op_class_1::IntAlu 4330 67.64% 67.93% # Class of committed instruction +system.cpu.commit.op_class_1::IntMult 1 0.02% 67.95% # Class of committed instruction +system.cpu.commit.op_class_1::IntDiv 0 0.00% 67.95% # Class of committed instruction +system.cpu.commit.op_class_1::FloatAdd 2 0.03% 67.98% # Class of committed instruction +system.cpu.commit.op_class_1::FloatCmp 0 0.00% 67.98% # Class of committed instruction +system.cpu.commit.op_class_1::FloatCvt 0 0.00% 67.98% # Class of committed instruction +system.cpu.commit.op_class_1::FloatMult 0 0.00% 67.98% # Class of committed instruction +system.cpu.commit.op_class_1::FloatDiv 0 0.00% 67.98% # Class of committed instruction +system.cpu.commit.op_class_1::FloatSqrt 0 0.00% 67.98% # Class of committed instruction +system.cpu.commit.op_class_1::SimdAdd 0 0.00% 67.98% # Class of committed instruction +system.cpu.commit.op_class_1::SimdAddAcc 0 0.00% 67.98% # Class of committed instruction +system.cpu.commit.op_class_1::SimdAlu 0 0.00% 67.98% # Class of committed instruction +system.cpu.commit.op_class_1::SimdCmp 0 0.00% 67.98% # Class of committed instruction +system.cpu.commit.op_class_1::SimdCvt 0 0.00% 67.98% # Class of committed instruction +system.cpu.commit.op_class_1::SimdMisc 0 0.00% 67.98% # Class of committed instruction +system.cpu.commit.op_class_1::SimdMult 0 0.00% 67.98% # Class of committed instruction +system.cpu.commit.op_class_1::SimdMultAcc 0 0.00% 67.98% # Class of committed instruction +system.cpu.commit.op_class_1::SimdShift 0 0.00% 67.98% # Class of committed instruction +system.cpu.commit.op_class_1::SimdShiftAcc 0 0.00% 67.98% # Class of committed instruction +system.cpu.commit.op_class_1::SimdSqrt 0 0.00% 67.98% # Class of committed instruction +system.cpu.commit.op_class_1::SimdFloatAdd 0 0.00% 67.98% # Class of committed instruction +system.cpu.commit.op_class_1::SimdFloatAlu 0 0.00% 67.98% # Class of committed instruction +system.cpu.commit.op_class_1::SimdFloatCmp 0 0.00% 67.98% # Class of committed instruction +system.cpu.commit.op_class_1::SimdFloatCvt 0 0.00% 67.98% # Class of committed instruction +system.cpu.commit.op_class_1::SimdFloatDiv 0 0.00% 67.98% # Class of committed instruction +system.cpu.commit.op_class_1::SimdFloatMisc 0 0.00% 67.98% # Class of committed instruction +system.cpu.commit.op_class_1::SimdFloatMult 0 0.00% 67.98% # Class of committed instruction +system.cpu.commit.op_class_1::SimdFloatMultAcc 0 0.00% 67.98% # Class of committed instruction +system.cpu.commit.op_class_1::SimdFloatSqrt 0 0.00% 67.98% # Class of committed instruction +system.cpu.commit.op_class_1::MemRead 1185 18.51% 86.49% # Class of committed instruction +system.cpu.commit.op_class_1::MemWrite 865 13.51% 100.00% # Class of committed instruction system.cpu.commit.op_class_1::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_1::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_1::total 6389 # Class of committed instruction -system.cpu.commit.op_class::total 12778 0.00% 0.00% # Class of committed instruction -system.cpu.commit.bw_lim_events 328 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 129836 # The number of ROB reads -system.cpu.rob.rob_writes 57114 # The number of ROB writes -system.cpu.timesIdled 383 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 22132 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts::0 6372 # Number of Instructions Simulated -system.cpu.committedInsts::1 6372 # Number of Instructions Simulated -system.cpu.committedInsts::total 12744 # Number of Instructions Simulated -system.cpu.committedOps::0 6372 # Number of Ops (including micro ops) Simulated -system.cpu.committedOps::1 6372 # Number of Ops (including micro ops) Simulated -system.cpu.committedOps::total 12744 # Number of Ops (including micro ops) Simulated -system.cpu.cpi::0 7.794413 # CPI: Cycles Per Instruction -system.cpu.cpi::1 7.794413 # CPI: Cycles Per Instruction -system.cpu.cpi_total 3.897207 # CPI: Total CPI of All Threads -system.cpu.ipc::0 0.128297 # IPC: Instructions Per Cycle -system.cpu.ipc::1 0.128297 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.256594 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 26493 # number of integer regfile reads -system.cpu.int_regfile_writes 14992 # number of integer regfile writes +system.cpu.commit.op_class_1::total 6402 # Class of committed instruction +system.cpu.commit.op_class::total 12804 0.00% 0.00% # Class of committed instruction +system.cpu.commit.bw_lim_events 344 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 128366 # The number of ROB reads +system.cpu.rob.rob_writes 54620 # The number of ROB writes +system.cpu.timesIdled 375 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 21302 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts::0 6385 # Number of Instructions Simulated +system.cpu.committedInsts::1 6385 # Number of Instructions Simulated +system.cpu.committedInsts::total 12770 # Number of Instructions Simulated +system.cpu.committedOps::0 6385 # Number of Ops (including micro ops) Simulated +system.cpu.committedOps::1 6385 # Number of Ops (including micro ops) Simulated +system.cpu.committedOps::total 12770 # Number of Ops (including micro ops) Simulated +system.cpu.cpi::0 7.766641 # CPI: Cycles Per Instruction +system.cpu.cpi::1 7.766641 # CPI: Cycles Per Instruction +system.cpu.cpi_total 3.883320 # CPI: Total CPI of All Threads +system.cpu.ipc::0 0.128756 # IPC: Instructions Per Cycle +system.cpu.ipc::1 0.128756 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.257512 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 25695 # number of integer regfile reads +system.cpu.int_regfile_writes 14528 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads system.cpu.fp_regfile_writes 4 # number of floating regfile writes system.cpu.misc_regfile_reads 2 # number of misc regfile reads @@ -727,230 +727,230 @@ system.cpu.misc_regfile_writes 2 # nu system.cpu.dcache.tags.replacements::0 0 # number of replacements system.cpu.dcache.tags.replacements::1 0 # number of replacements system.cpu.dcache.tags.replacements::total 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 212.222617 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 4769 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 344 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 13.863372 # Average number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 213.419877 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 4643 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 345 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 13.457971 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 212.222617 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.051812 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.051812 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 344 # Occupied blocks per task id +system.cpu.dcache.tags.occ_blocks::cpu.data 213.419877 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.052104 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.052104 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 345 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 88 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 256 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.083984 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 11936 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 11936 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 3748 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 3748 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 1021 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 1021 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 4769 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 4769 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 4769 # number of overall hits -system.cpu.dcache.overall_hits::total 4769 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 318 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 318 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 709 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 709 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1027 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1027 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1027 # number of overall misses -system.cpu.dcache.overall_misses::total 1027 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 24395500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 24395500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 50809414 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 50809414 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 75204914 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 75204914 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 75204914 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 75204914 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 4066 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 4066 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.age_task_id_blocks_1024::1 257 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.084229 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 11689 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 11689 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 3618 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 3618 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 1025 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 1025 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 4643 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 4643 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 4643 # number of overall hits +system.cpu.dcache.overall_hits::total 4643 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 324 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 324 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 705 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 705 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1029 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1029 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1029 # number of overall misses +system.cpu.dcache.overall_misses::total 1029 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 25567500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 25567500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 52147927 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 52147927 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 77715427 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 77715427 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 77715427 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 77715427 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 3942 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 3942 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1730 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 1730 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 5796 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 5796 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 5796 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 5796 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.078210 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.078210 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.409827 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.409827 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.177191 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.177191 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.177191 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.177191 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 76715.408805 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 76715.408805 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 71663.489422 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 71663.489422 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 73227.764362 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 73227.764362 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 73227.764362 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 73227.764362 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 5829 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 5672 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 5672 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 5672 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 5672 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.082192 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.082192 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.407514 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.407514 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.181417 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.181417 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.181417 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.181417 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 78912.037037 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 78912.037037 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73968.690780 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 73968.690780 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 75525.196307 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 75525.196307 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 75525.196307 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 75525.196307 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 5306 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 135 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 120 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 43.177778 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 44.216667 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 120 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 120 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 563 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 563 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 683 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 683 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 683 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 683 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 198 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 198 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 146 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 146 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 344 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 344 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 344 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 344 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17299000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 17299000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12670989 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 12670989 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29969989 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 29969989 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29969989 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 29969989 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.048697 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.048697 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.059351 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.059351 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.059351 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.059351 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 87368.686869 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 87368.686869 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 86787.595890 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 86787.595890 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 87122.061047 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 87122.061047 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 87122.061047 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 87122.061047 # average overall mshr miss latency +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 123 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 123 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 561 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 561 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 684 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 684 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 684 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 684 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 201 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 201 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 144 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 144 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 345 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 345 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 345 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 345 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17683500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 17683500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12260990 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 12260990 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29944490 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 29944490 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29944490 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 29944490 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.050989 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.050989 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083237 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.083237 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.060825 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.060825 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.060825 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.060825 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 87977.611940 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 87977.611940 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 85145.763889 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 85145.763889 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 86795.623188 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 86795.623188 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 86795.623188 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 86795.623188 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements::0 8 # number of replacements system.cpu.icache.tags.replacements::1 0 # number of replacements system.cpu.icache.tags.replacements::total 8 # number of replacements -system.cpu.icache.tags.tagsinuse 317.014953 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 4463 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 634 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 7.039432 # Average number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 317.233633 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 4245 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 632 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 6.716772 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 317.014953 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.154792 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.154792 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 626 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 260 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 366 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.305664 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 11430 # Number of tag accesses -system.cpu.icache.tags.data_accesses 11430 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 4463 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 4463 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 4463 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 4463 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 4463 # number of overall hits -system.cpu.icache.overall_hits::total 4463 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 935 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 935 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 935 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 935 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 935 # number of overall misses -system.cpu.icache.overall_misses::total 935 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 70147997 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 70147997 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 70147997 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 70147997 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 70147997 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 70147997 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 5398 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 5398 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 5398 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 5398 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 5398 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 5398 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.173212 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.173212 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.173212 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.173212 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.173212 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.173212 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75024.595722 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 75024.595722 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 75024.595722 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 75024.595722 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 75024.595722 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 75024.595722 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 3484 # number of cycles access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 317.233633 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.154899 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.154899 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 624 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 257 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 367 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.304688 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 10968 # Number of tag accesses +system.cpu.icache.tags.data_accesses 10968 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 4245 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 4245 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 4245 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 4245 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 4245 # number of overall hits +system.cpu.icache.overall_hits::total 4245 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 923 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 923 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 923 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 923 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 923 # number of overall misses +system.cpu.icache.overall_misses::total 923 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 69430495 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 69430495 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 69430495 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 69430495 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 69430495 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 69430495 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 5168 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 5168 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 5168 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 5168 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 5168 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 5168 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.178599 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.178599 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.178599 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.178599 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.178599 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.178599 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75222.638137 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 75222.638137 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 75222.638137 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 75222.638137 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 75222.638137 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 75222.638137 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 3541 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 77 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 68 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 45.246753 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 52.073529 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # 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number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 44263000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 44263000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 15014000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 15014000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 44263000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 25998500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 70261500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 44263000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 25998500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 70261500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 144 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 144 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 630 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 630 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 201 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 201 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 630 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 345 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 975 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 630 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 345 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 975 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10598000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10598000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 44562500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 44562500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 15364000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 15364000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 44562500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 25962000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 70524500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 44562500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 25962000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 70524500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.996845 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.996845 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.996835 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.996835 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996845 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996835 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.997955 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996845 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.997953 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996835 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.997955 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 75236.301370 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 75236.301370 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70036.392405 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70036.392405 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 75828.282828 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 75828.282828 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70036.392405 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 75577.034884 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71989.241803 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70036.392405 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 75577.034884 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71989.241803 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.997953 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 73597.222222 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 73597.222222 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70734.126984 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70734.126984 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76437.810945 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76437.810945 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70734.126984 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 75252.173913 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72332.820513 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70734.126984 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 75252.173913 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72332.820513 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 986 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.tot_requests 985 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 10 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 832 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 833 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 8 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 146 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 146 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 634 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 198 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1276 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 688 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 1964 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 41088 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22016 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 63104 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadExReq 144 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 144 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 632 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 201 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1272 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 690 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 1962 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 40960 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22080 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 63040 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 978 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.002045 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.045198 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 977 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.002047 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.045222 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 976 99.80% 99.80% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 975 99.80% 99.80% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 2 0.20% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 978 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 501000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 977 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 500500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 2.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 951000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 948000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 3.8 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 516000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 517500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 2.1 # Layer utilization (%) -system.membus.trans_dist::ReadResp 830 # Transaction distribution -system.membus.trans_dist::ReadExReq 146 # Transaction distribution -system.membus.trans_dist::ReadExResp 146 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 830 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1952 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1952 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 62464 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 62464 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadResp 831 # Transaction distribution +system.membus.trans_dist::ReadExReq 144 # Transaction distribution +system.membus.trans_dist::ReadExResp 144 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 831 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1950 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1950 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 62400 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 62400 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 976 # Request fanout histogram +system.membus.snoop_fanout::samples 975 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 976 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 975 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 976 # Request fanout histogram -system.membus.reqLayer0.occupancy 1189000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 975 # Request fanout histogram +system.membus.reqLayer0.occupancy 1186000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 4.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 5195000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 20.9 # Layer utilization (%) +system.membus.respLayer1.occupancy 5196500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 21.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/config.ini b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/config.ini index 3db01e542..7b696dc10 100644 --- a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/config.ini +++ b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/config.ini @@ -222,6 +222,7 @@ clk_domain=system.clk_domain eventq_index=0 forward_latency=4 frontend_latency=3 +point_of_coherency=true response_latency=2 snoop_filter=Null snoop_response_latency=4 diff --git a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/simout b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/simout index e1906cb05..fa59b7ebb 100755 --- a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/simout +++ b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/simout @@ -1,14 +1,16 @@ +Redirecting stdout to build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-simple/simout +Redirecting stderr to build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-simple/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 21 2016 13:49:21 -gem5 started Jan 21 2016 13:50:15 -gem5 executing on zizzer, pid 34054 -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-simple -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-simple +gem5 compiled Mar 14 2016 21:54:46 +gem5 started Mar 14 2016 21:58:08 +gem5 executing on phenom, pid 28209 +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-simple -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-simple Global frequency set at 1000000000000 ticks per second Beginning simulation! info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 405501000 because target called exit() +Exiting @ tick 405365000 because target called exit() diff --git a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/stats.txt b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/stats.txt index dee41c633..1b652ed70 100644 --- a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/stats.txt @@ -1,91 +1,91 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000406 # Number of seconds simulated -sim_ticks 405501000 # Number of ticks simulated -final_tick 405501000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000405 # Number of seconds simulated +sim_ticks 405365000 # Number of ticks simulated +final_tick 405365000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 86197 # Simulator instruction rate (inst/s) -host_op_rate 86167 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5423806428 # Simulator tick rate (ticks/s) -host_mem_usage 613516 # Number of bytes of host memory used -host_seconds 0.07 # Real time elapsed on the host -sim_insts 6440 # Number of instructions simulated -sim_ops 6440 # Number of ops (including micro ops) simulated +host_inst_rate 83628 # Simulator instruction rate (inst/s) +host_op_rate 83610 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5251060650 # Simulator tick rate (ticks/s) +host_mem_usage 610048 # Number of bytes of host memory used +host_seconds 0.08 # Real time elapsed on the host +sim_insts 6453 # Number of instructions simulated +sim_ops 6453 # Number of ops (including micro ops) simulated system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.mem_ctrl.bytes_read::cpu.inst 25800 # Number of bytes read from this memory -system.mem_ctrl.bytes_read::cpu.data 8828 # Number of bytes read from this memory -system.mem_ctrl.bytes_read::total 34628 # Number of bytes read from this memory -system.mem_ctrl.bytes_inst_read::cpu.inst 25800 # Number of instructions bytes read from this memory -system.mem_ctrl.bytes_inst_read::total 25800 # Number of instructions bytes read from this memory +system.mem_ctrl.bytes_read::cpu.inst 25852 # Number of bytes read from this memory +system.mem_ctrl.bytes_read::cpu.data 8844 # Number of bytes read from this memory +system.mem_ctrl.bytes_read::total 34696 # Number of bytes read from this memory +system.mem_ctrl.bytes_inst_read::cpu.inst 25852 # Number of instructions bytes read from this memory +system.mem_ctrl.bytes_inst_read::total 25852 # Number of instructions bytes read from this memory system.mem_ctrl.bytes_written::cpu.data 6696 # Number of bytes written to this memory system.mem_ctrl.bytes_written::total 6696 # Number of bytes written to this memory -system.mem_ctrl.num_reads::cpu.inst 6450 # Number of read requests responded to by this memory -system.mem_ctrl.num_reads::cpu.data 1188 # Number of read requests responded to by this memory -system.mem_ctrl.num_reads::total 7638 # Number of read requests responded to by this memory +system.mem_ctrl.num_reads::cpu.inst 6463 # Number of read requests responded to by this memory +system.mem_ctrl.num_reads::cpu.data 1190 # Number of read requests responded to by this memory +system.mem_ctrl.num_reads::total 7653 # Number of read requests responded to by this memory system.mem_ctrl.num_writes::cpu.data 865 # Number of write requests responded to by this memory system.mem_ctrl.num_writes::total 865 # Number of write requests responded to by this memory -system.mem_ctrl.bw_read::cpu.inst 63624997 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::cpu.data 21770600 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::total 85395597 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::cpu.inst 63624997 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::total 63624997 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_write::cpu.data 16512906 # Write bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_write::total 16512906 # Write bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.inst 63624997 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.data 38283506 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::total 101908503 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.readReqs 7639 # Number of read requests accepted +system.mem_ctrl.bw_read::cpu.inst 63774623 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::cpu.data 21817374 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::total 85591997 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::cpu.inst 63774623 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::total 63774623 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_write::cpu.data 16518446 # Write bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_write::total 16518446 # Write bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.inst 63774623 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.data 38335821 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::total 102110444 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.readReqs 7654 # Number of read requests accepted system.mem_ctrl.writeReqs 865 # Number of write requests accepted -system.mem_ctrl.readBursts 7639 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrl.readBursts 7654 # Number of DRAM read bursts, including those serviced by the write queue system.mem_ctrl.writeBursts 865 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrl.bytesReadDRAM 477632 # Total number of bytes read from DRAM -system.mem_ctrl.bytesReadWrQ 11264 # Total number of bytes read from write queue +system.mem_ctrl.bytesReadDRAM 477504 # Total number of bytes read from DRAM +system.mem_ctrl.bytesReadWrQ 12352 # Total number of bytes read from write queue system.mem_ctrl.bytesWritten 6144 # Total number of bytes written to DRAM -system.mem_ctrl.bytesReadSys 34632 # Total read bytes from the system interface side +system.mem_ctrl.bytesReadSys 34700 # Total read bytes from the system interface side system.mem_ctrl.bytesWrittenSys 6696 # Total written bytes from the system interface side -system.mem_ctrl.servicedByWrQ 176 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrl.servicedByWrQ 193 # Number of DRAM read bursts serviced by the write queue system.mem_ctrl.mergedWrBursts 747 # Number of DRAM write bursts merged with an existing one system.mem_ctrl.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.mem_ctrl.perBankRdBursts::0 1736 # Per bank write bursts system.mem_ctrl.perBankRdBursts::1 393 # Per bank write bursts system.mem_ctrl.perBankRdBursts::2 768 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::3 787 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::4 776 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::3 800 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::4 763 # Per bank write bursts system.mem_ctrl.perBankRdBursts::5 293 # Per bank write bursts system.mem_ctrl.perBankRdBursts::6 6 # Per bank write bursts system.mem_ctrl.perBankRdBursts::7 26 # Per bank write bursts system.mem_ctrl.perBankRdBursts::8 0 # Per bank write bursts system.mem_ctrl.perBankRdBursts::9 1 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::10 257 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::10 253 # Per bank write bursts system.mem_ctrl.perBankRdBursts::11 578 # Per bank write bursts system.mem_ctrl.perBankRdBursts::12 167 # Per bank write bursts system.mem_ctrl.perBankRdBursts::13 1430 # Per bank write bursts system.mem_ctrl.perBankRdBursts::14 89 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::15 156 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::15 158 # Per bank write bursts system.mem_ctrl.perBankWrBursts::0 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::1 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::2 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::3 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::4 27 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::5 6 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::4 18 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::5 8 # Per bank write bursts system.mem_ctrl.perBankWrBursts::6 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::7 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::8 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::9 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::10 5 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::10 6 # Per bank write bursts system.mem_ctrl.perBankWrBursts::11 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::12 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::13 14 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::14 44 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::13 21 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::14 43 # Per bank write bursts system.mem_ctrl.perBankWrBursts::15 0 # Per bank write bursts system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrl.totGap 405425000 # Total gap between requests +system.mem_ctrl.totGap 405289000 # Total gap between requests system.mem_ctrl.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrl.readPktSize::1 0 # Read request sizes (log2) -system.mem_ctrl.readPktSize::2 6620 # Read request sizes (log2) -system.mem_ctrl.readPktSize::3 1019 # Read request sizes (log2) +system.mem_ctrl.readPktSize::2 6633 # Read request sizes (log2) +system.mem_ctrl.readPktSize::3 1021 # Read request sizes (log2) system.mem_ctrl.readPktSize::4 0 # Read request sizes (log2) system.mem_ctrl.readPktSize::5 0 # Read request sizes (log2) system.mem_ctrl.readPktSize::6 0 # Read request sizes (log2) @@ -96,7 +96,7 @@ system.mem_ctrl.writePktSize::3 809 # Wr system.mem_ctrl.writePktSize::4 0 # Write request sizes (log2) system.mem_ctrl.writePktSize::5 0 # Write request sizes (log2) system.mem_ctrl.writePktSize::6 0 # Write request sizes (log2) -system.mem_ctrl.rdQLenPdf::0 7463 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::0 7461 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::1 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::2 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::3 0 # What read queue length does an incoming req see @@ -192,106 +192,105 @@ system.mem_ctrl.wrQLenPdf::60 0 # Wh system.mem_ctrl.wrQLenPdf::61 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrl.bytesPerActivate::samples 775 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::mean 623.649032 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::gmean 407.696259 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::stdev 407.140251 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::0-127 158 20.39% 20.39% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::128-255 63 8.13% 28.52% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::256-383 48 6.19% 34.71% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::384-511 41 5.29% 40.00% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::512-639 47 6.06% 46.06% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::640-767 28 3.61% 49.68% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::768-895 28 3.61% 53.29% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::896-1023 33 4.26% 57.55% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::1024-1151 329 42.45% 100.00% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::total 775 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::samples 762 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::mean 634.288714 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::gmean 419.900652 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::stdev 405.302633 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::0-127 146 19.16% 19.16% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::128-255 69 9.06% 28.22% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::256-383 39 5.12% 33.33% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::384-511 43 5.64% 38.98% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::512-639 44 5.77% 44.75% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::640-767 27 3.54% 48.29% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::768-895 31 4.07% 52.36% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::896-1023 30 3.94% 56.30% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::1024-1151 333 43.70% 100.00% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::total 762 # Bytes accessed per row activation system.mem_ctrl.rdPerTurnAround::samples 6 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::mean 1159.333333 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::gmean 1053.861325 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::stdev 505.634519 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::512-575 1 16.67% 16.67% # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::576-639 1 16.67% 33.33% # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::1152-1215 1 16.67% 50.00% # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::1344-1407 1 16.67% 66.67% # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::1408-1471 1 16.67% 83.33% # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::1792-1855 1 16.67% 100.00% # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::mean 1203.833333 # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::gmean 1052.985580 # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::stdev 699.444184 # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::512-639 2 33.33% 33.33% # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::896-1023 1 16.67% 50.00% # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::1152-1279 1 16.67% 66.67% # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::1408-1535 1 16.67% 83.33% # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::2432-2559 1 16.67% 100.00% # Reads before turning the bus around for writes system.mem_ctrl.rdPerTurnAround::total 6 # Reads before turning the bus around for writes system.mem_ctrl.wrPerTurnAround::samples 6 # Writes before turning the bus around for reads system.mem_ctrl.wrPerTurnAround::mean 16 # Writes before turning the bus around for reads system.mem_ctrl.wrPerTurnAround::gmean 16.000000 # Writes before turning the bus around for reads system.mem_ctrl.wrPerTurnAround::16 6 100.00% 100.00% # Writes before turning the bus around for reads system.mem_ctrl.wrPerTurnAround::total 6 # Writes before turning the bus around for reads -system.mem_ctrl.totQLat 26448250 # Total ticks spent queuing -system.mem_ctrl.totMemAccLat 166379500 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrl.totBusLat 37315000 # Total ticks spent in databus transfers -system.mem_ctrl.avgQLat 3543.92 # Average queueing delay per DRAM burst +system.mem_ctrl.totQLat 26088750 # Total ticks spent queuing +system.mem_ctrl.totMemAccLat 165982500 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrl.totBusLat 37305000 # Total ticks spent in databus transfers +system.mem_ctrl.avgQLat 3496.68 # Average queueing delay per DRAM burst system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.mem_ctrl.avgMemAccLat 22293.92 # Average memory access latency per DRAM burst -system.mem_ctrl.avgRdBW 1177.88 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrl.avgWrBW 15.15 # Average achieved write bandwidth in MiByte/s -system.mem_ctrl.avgRdBWSys 85.41 # Average system read bandwidth in MiByte/s -system.mem_ctrl.avgWrBWSys 16.51 # Average system write bandwidth in MiByte/s +system.mem_ctrl.avgMemAccLat 22246.68 # Average memory access latency per DRAM burst +system.mem_ctrl.avgRdBW 1177.96 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrl.avgWrBW 15.16 # Average achieved write bandwidth in MiByte/s +system.mem_ctrl.avgRdBWSys 85.60 # Average system read bandwidth in MiByte/s +system.mem_ctrl.avgWrBWSys 16.52 # Average system write bandwidth in MiByte/s system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.mem_ctrl.busUtil 9.32 # Data bus utilization in percentage system.mem_ctrl.busUtilRead 9.20 # Data bus utilization in percentage for reads system.mem_ctrl.busUtilWrite 0.12 # Data bus utilization in percentage for writes system.mem_ctrl.avgRdQLen 1.00 # Average read queue length when enqueuing -system.mem_ctrl.avgWrQLen 23.37 # Average write queue length when enqueuing -system.mem_ctrl.readRowHits 6696 # Number of row buffer hits during reads -system.mem_ctrl.writeRowHits 87 # Number of row buffer hits during writes -system.mem_ctrl.readRowHitRate 89.72 # Row buffer hit rate for reads -system.mem_ctrl.writeRowHitRate 73.73 # Row buffer hit rate for writes -system.mem_ctrl.avgGap 47674.62 # Average gap between requests -system.mem_ctrl.pageHitRate 89.47 # Row buffer hit rate, read and write combined -system.mem_ctrl_0.actEnergy 3439800 # Energy for activate commands per rank (pJ) -system.mem_ctrl_0.preEnergy 1876875 # Energy for precharge commands per rank (pJ) -system.mem_ctrl_0.readEnergy 37268400 # Energy for read commands per rank (pJ) -system.mem_ctrl_0.writeEnergy 213840 # Energy for write commands per rank (pJ) +system.mem_ctrl.avgWrQLen 24.34 # Average write queue length when enqueuing +system.mem_ctrl.readRowHits 6706 # Number of row buffer hits during reads +system.mem_ctrl.writeRowHits 88 # Number of row buffer hits during writes +system.mem_ctrl.readRowHitRate 89.88 # Row buffer hit rate for reads +system.mem_ctrl.writeRowHitRate 74.58 # Row buffer hit rate for writes +system.mem_ctrl.avgGap 47574.72 # Average gap between requests +system.mem_ctrl.pageHitRate 89.64 # Row buffer hit rate, read and write combined +system.mem_ctrl_0.actEnergy 3333960 # Energy for activate commands per rank (pJ) +system.mem_ctrl_0.preEnergy 1819125 # Energy for precharge commands per rank (pJ) +system.mem_ctrl_0.readEnergy 37284000 # Energy for read commands per rank (pJ) +system.mem_ctrl_0.writeEnergy 168480 # Energy for write commands per rank (pJ) system.mem_ctrl_0.refreshEnergy 26445120 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_0.actBackEnergy 264293325 # Energy for active background per rank (pJ) -system.mem_ctrl_0.preBackEnergy 11250750 # Energy for precharge background per rank (pJ) -system.mem_ctrl_0.totalEnergy 344788110 # Total energy per rank (pJ) -system.mem_ctrl_0.averagePower 851.023979 # Core power per rank (mW) -system.mem_ctrl_0.memoryStateTime::IDLE 15542500 # Time in different power states +system.mem_ctrl_0.actBackEnergy 262765440 # Energy for active background per rank (pJ) +system.mem_ctrl_0.preBackEnergy 12591750 # Energy for precharge background per rank (pJ) +system.mem_ctrl_0.totalEnergy 344407875 # Total energy per rank (pJ) +system.mem_ctrl_0.averagePower 850.082840 # Core power per rank (mW) +system.mem_ctrl_0.memoryStateTime::IDLE 17896000 # Time in different power states system.mem_ctrl_0.memoryStateTime::REF 13520000 # Time in different power states system.mem_ctrl_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrl_0.memoryStateTime::ACT 376096250 # Time in different power states +system.mem_ctrl_0.memoryStateTime::ACT 373743250 # Time in different power states system.mem_ctrl_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrl_1.actEnergy 2419200 # Energy for activate commands per rank (pJ) -system.mem_ctrl_1.preEnergy 1320000 # Energy for precharge commands per rank (pJ) -system.mem_ctrl_1.readEnergy 20888400 # Energy for read commands per rank (pJ) -system.mem_ctrl_1.writeEnergy 408240 # Energy for write commands per rank (pJ) +system.mem_ctrl_1.actEnergy 2426760 # Energy for activate commands per rank (pJ) +system.mem_ctrl_1.preEnergy 1324125 # Energy for precharge commands per rank (pJ) +system.mem_ctrl_1.readEnergy 20872800 # Energy for read commands per rank (pJ) +system.mem_ctrl_1.writeEnergy 453600 # Energy for write commands per rank (pJ) system.mem_ctrl_1.refreshEnergy 26445120 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_1.actBackEnergy 228585105 # Energy for active background per rank (pJ) -system.mem_ctrl_1.preBackEnergy 42573750 # Energy for precharge background per rank (pJ) -system.mem_ctrl_1.totalEnergy 322639815 # Total energy per rank (pJ) -system.mem_ctrl_1.averagePower 796.356403 # Core power per rank (mW) -system.mem_ctrl_1.memoryStateTime::IDLE 69100250 # Time in different power states +system.mem_ctrl_1.actBackEnergy 229562370 # Energy for active background per rank (pJ) +system.mem_ctrl_1.preBackEnergy 41716500 # Energy for precharge background per rank (pJ) +system.mem_ctrl_1.totalEnergy 322801275 # Total energy per rank (pJ) +system.mem_ctrl_1.averagePower 796.754927 # Core power per rank (mW) +system.mem_ctrl_1.memoryStateTime::IDLE 67586500 # Time in different power states system.mem_ctrl_1.memoryStateTime::REF 13520000 # Time in different power states system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrl_1.memoryStateTime::ACT 322538500 # Time in different power states +system.mem_ctrl_1.memoryStateTime::ACT 324052250 # Time in different power states system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 1188 # DTB read hits +system.cpu.dtb.read_hits 1190 # DTB read hits system.cpu.dtb.read_misses 7 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 1195 # DTB read accesses +system.cpu.dtb.read_accesses 1197 # DTB read accesses system.cpu.dtb.write_hits 865 # DTB write hits system.cpu.dtb.write_misses 3 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations system.cpu.dtb.write_accesses 868 # DTB write accesses -system.cpu.dtb.data_hits 2053 # DTB hits +system.cpu.dtb.data_hits 2055 # DTB hits system.cpu.dtb.data_misses 10 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 2063 # DTB accesses -system.cpu.itb.fetch_hits 6451 # ITB hits +system.cpu.dtb.data_accesses 2065 # DTB accesses +system.cpu.itb.fetch_hits 6464 # ITB hits system.cpu.itb.fetch_misses 17 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 6468 # ITB accesses +system.cpu.itb.fetch_accesses 6481 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -305,90 +304,90 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 405501 # number of cpu cycles simulated +system.cpu.numCycles 405365 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 6440 # Number of instructions committed -system.cpu.committedOps 6440 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 6368 # Number of integer alu accesses +system.cpu.committedInsts 6453 # Number of instructions committed +system.cpu.committedOps 6453 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 6380 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses system.cpu.num_func_calls 251 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 754 # number of instructions that are conditional controls -system.cpu.num_int_insts 6368 # number of integer instructions +system.cpu.num_conditional_control_insts 759 # number of instructions that are conditional controls +system.cpu.num_int_insts 6380 # number of integer instructions system.cpu.num_fp_insts 10 # number of float instructions -system.cpu.num_int_register_reads 8380 # number of times the integer registers were read -system.cpu.num_int_register_writes 4614 # number of times the integer registers were written +system.cpu.num_int_register_reads 8392 # number of times the integer registers were read +system.cpu.num_int_register_writes 4621 # number of times the integer registers were written system.cpu.num_fp_register_reads 8 # number of times the floating registers were read system.cpu.num_fp_register_writes 2 # number of times the floating registers were written -system.cpu.num_mem_refs 2063 # number of memory refs -system.cpu.num_load_insts 1195 # Number of load instructions +system.cpu.num_mem_refs 2065 # number of memory refs +system.cpu.num_load_insts 1197 # Number of load instructions system.cpu.num_store_insts 868 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 405501 # Number of busy cycles +system.cpu.num_busy_cycles 405365 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 1054 # Number of branches fetched +system.cpu.Branches 1060 # Number of branches fetched system.cpu.op_class::No_OpClass 19 0.29% 0.29% # Class of executed instruction -system.cpu.op_class::IntAlu 4365 67.67% 67.97% # Class of executed instruction -system.cpu.op_class::IntMult 1 0.02% 67.98% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 67.98% # Class of executed instruction -system.cpu.op_class::FloatAdd 2 0.03% 68.02% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 68.02% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 68.02% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 68.02% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 68.02% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 68.02% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 68.02% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 68.02% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 68.02% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 68.02% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 68.02% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 68.02% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 68.02% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 68.02% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 68.02% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 68.02% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 68.02% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 68.02% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 68.02% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 68.02% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 68.02% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 68.02% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 68.02% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 68.02% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.02% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 68.02% # Class of executed instruction -system.cpu.op_class::MemRead 1195 18.53% 86.54% # Class of executed instruction -system.cpu.op_class::MemWrite 868 13.46% 100.00% # Class of executed instruction +system.cpu.op_class::IntAlu 4376 67.71% 68.00% # Class of executed instruction +system.cpu.op_class::IntMult 1 0.02% 68.02% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 68.02% # Class of executed instruction +system.cpu.op_class::FloatAdd 2 0.03% 68.05% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 68.05% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 68.05% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 68.05% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 68.05% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 68.05% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 68.05% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 68.05% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 68.05% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 68.05% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 68.05% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 68.05% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 68.05% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 68.05% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 68.05% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 68.05% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 68.05% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 68.05% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 68.05% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 68.05% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 68.05% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 68.05% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 68.05% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 68.05% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.05% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 68.05% # Class of executed instruction +system.cpu.op_class::MemRead 1197 18.52% 86.57% # Class of executed instruction +system.cpu.op_class::MemWrite 868 13.43% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 6450 # Class of executed instruction -system.membus.trans_dist::ReadReq 7639 # Transaction distribution -system.membus.trans_dist::ReadResp 7638 # Transaction distribution +system.cpu.op_class::total 6463 # Class of executed instruction +system.membus.trans_dist::ReadReq 7654 # Transaction distribution +system.membus.trans_dist::ReadResp 7653 # Transaction distribution system.membus.trans_dist::WriteReq 865 # Transaction distribution system.membus.trans_dist::WriteResp 865 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.mem_ctrl.port 12901 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.mem_ctrl.port 4106 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 17007 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.mem_ctrl.port 25800 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.mem_ctrl.port 15524 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 41324 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.icache_port::system.mem_ctrl.port 12927 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.mem_ctrl.port 4110 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 17037 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.mem_ctrl.port 25852 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.mem_ctrl.port 15540 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 41392 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 8504 # Request fanout histogram -system.membus.snoop_fanout::mean 0.758584 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.427967 # Request fanout histogram +system.membus.snoop_fanout::samples 8519 # Request fanout histogram +system.membus.snoop_fanout::mean 0.758775 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.427852 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 2053 24.14% 24.14% # Request fanout histogram -system.membus.snoop_fanout::1 6451 75.86% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 2055 24.12% 24.12% # Request fanout histogram +system.membus.snoop_fanout::1 6464 75.88% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 8504 # Request fanout histogram -system.membus.reqLayer0.occupancy 9369000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 8519 # Request fanout histogram +system.membus.reqLayer0.occupancy 9384000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.3 # Layer utilization (%) -system.membus.respLayer0.occupancy 14662500 # Layer occupancy (ticks) +system.membus.respLayer0.occupancy 14690750 # Layer occupancy (ticks) system.membus.respLayer0.utilization 3.6 # Layer utilization (%) -system.membus.respLayer1.occupancy 3576750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 3574500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.9 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/config.ini b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/config.ini index 66f02e253..2d8c24695 100644 --- a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/config.ini +++ b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/config.ini @@ -94,7 +94,6 @@ clk_domain=system.clk_domain clusivity=mostly_incl demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=2 is_read_only=false max_miss_count=0 @@ -136,7 +135,6 @@ clk_domain=system.clk_domain clusivity=mostly_incl demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=2 is_read_only=false max_miss_count=0 @@ -220,6 +218,7 @@ clk_domain=system.clk_domain eventq_index=0 forward_latency=0 frontend_latency=1 +point_of_coherency=false response_latency=1 snoop_filter=system.l2bus.snoop_filter snoop_response_latency=1 @@ -245,7 +244,6 @@ clk_domain=system.clk_domain clusivity=mostly_incl demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=20 is_read_only=false max_miss_count=0 @@ -356,6 +354,7 @@ clk_domain=system.clk_domain eventq_index=0 forward_latency=4 frontend_latency=3 +point_of_coherency=true response_latency=2 snoop_filter=Null snoop_response_latency=4 diff --git a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/simout b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/simout index e33184bae..33f584256 100755 --- a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/simout +++ b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/simout @@ -1,14 +1,16 @@ +Redirecting stdout to build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-two-level/simout +Redirecting stderr to build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-two-level/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 21 2016 13:49:21 -gem5 started Jan 21 2016 13:50:14 -gem5 executing on zizzer, pid 34037 -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-two-level -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-two-level +gem5 compiled Mar 14 2016 21:54:46 +gem5 started Mar 14 2016 21:56:34 +gem5 executing on phenom, pid 28126 +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-two-level -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-two-level Global frequency set at 1000000000000 ticks per second Beginning simulation! info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 61610000 because target called exit() +Exiting @ tick 61470000 because target called exit() diff --git a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/stats.txt b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/stats.txt index f030be200..b37d8b5b7 100644 --- a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000062 # Number of seconds simulated -sim_ticks 61610000 # Number of ticks simulated -final_tick 61610000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000061 # Number of seconds simulated +sim_ticks 61470000 # Number of ticks simulated +final_tick 61470000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 98323 # Simulator instruction rate (inst/s) -host_op_rate 98283 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 939896452 # Simulator tick rate (ticks/s) -host_mem_usage 618136 # Number of bytes of host memory used -host_seconds 0.07 # Real time elapsed on the host -sim_insts 6440 # Number of instructions simulated -sim_ops 6440 # Number of ops (including micro ops) simulated +host_inst_rate 62593 # Simulator instruction rate (inst/s) +host_op_rate 62569 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 595804848 # Simulator tick rate (ticks/s) +host_mem_usage 614668 # Number of bytes of host memory used +host_seconds 0.10 # Real time elapsed on the host +sim_insts 6453 # Number of instructions simulated +sim_ops 6453 # Number of ops (including micro ops) simulated system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.mem_ctrl.bytes_read::cpu.inst 17792 # Number of bytes read from this memory @@ -21,14 +21,14 @@ system.mem_ctrl.bytes_inst_read::total 17792 # Nu system.mem_ctrl.num_reads::cpu.inst 278 # Number of read requests responded to by this memory system.mem_ctrl.num_reads::cpu.data 168 # Number of read requests responded to by this memory system.mem_ctrl.num_reads::total 446 # Number of read requests responded to by this memory -system.mem_ctrl.bw_read::cpu.inst 288784288 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::cpu.data 174517124 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::total 463301412 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::cpu.inst 288784288 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::total 288784288 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.inst 288784288 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.data 174517124 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::total 463301412 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_read::cpu.inst 289442004 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::cpu.data 174914592 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::total 464356597 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::cpu.inst 289442004 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::total 289442004 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.inst 289442004 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.data 174914592 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::total 464356597 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrl.readReqs 446 # Number of read requests accepted system.mem_ctrl.writeReqs 0 # Number of write requests accepted system.mem_ctrl.readBursts 446 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.mem_ctrl.perBankWrBursts::14 0 # Pe system.mem_ctrl.perBankWrBursts::15 0 # Per bank write bursts system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrl.totGap 61360000 # Total gap between requests +system.mem_ctrl.totGap 61220000 # Total gap between requests system.mem_ctrl.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrl.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrl.readPktSize::2 0 # Read request sizes (log2) @@ -187,88 +187,88 @@ system.mem_ctrl.wrQLenPdf::61 0 # Wh system.mem_ctrl.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::63 0 # What write queue length does an incoming req see system.mem_ctrl.bytesPerActivate::samples 95 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::mean 270.147368 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::gmean 180.864884 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::stdev 259.243949 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::0-127 27 28.42% 28.42% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::128-255 31 32.63% 61.05% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::256-383 11 11.58% 72.63% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::384-511 8 8.42% 81.05% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::512-639 6 6.32% 87.37% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::mean 270.821053 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::gmean 180.792132 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::stdev 259.793616 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::0-127 28 29.47% 29.47% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::128-255 29 30.53% 60.00% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::256-383 12 12.63% 72.63% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::384-511 9 9.47% 82.11% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::512-639 5 5.26% 87.37% # Bytes accessed per row activation system.mem_ctrl.bytesPerActivate::640-767 6 6.32% 93.68% # Bytes accessed per row activation system.mem_ctrl.bytesPerActivate::768-895 1 1.05% 94.74% # Bytes accessed per row activation system.mem_ctrl.bytesPerActivate::1024-1151 5 5.26% 100.00% # Bytes accessed per row activation system.mem_ctrl.bytesPerActivate::total 95 # Bytes accessed per row activation -system.mem_ctrl.totQLat 3464500 # Total ticks spent queuing -system.mem_ctrl.totMemAccLat 11827000 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrl.totQLat 3294500 # Total ticks spent queuing +system.mem_ctrl.totMemAccLat 11657000 # Total ticks spent from burst creation until serviced by the DRAM system.mem_ctrl.totBusLat 2230000 # Total ticks spent in databus transfers -system.mem_ctrl.avgQLat 7767.94 # Average queueing delay per DRAM burst +system.mem_ctrl.avgQLat 7386.77 # Average queueing delay per DRAM burst system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.mem_ctrl.avgMemAccLat 26517.94 # Average memory access latency per DRAM burst -system.mem_ctrl.avgRdBW 463.30 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrl.avgMemAccLat 26136.77 # Average memory access latency per DRAM burst +system.mem_ctrl.avgRdBW 464.36 # Average DRAM read bandwidth in MiByte/s system.mem_ctrl.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.mem_ctrl.avgRdBWSys 463.30 # Average system read bandwidth in MiByte/s +system.mem_ctrl.avgRdBWSys 464.36 # Average system read bandwidth in MiByte/s system.mem_ctrl.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrl.busUtil 3.62 # Data bus utilization in percentage -system.mem_ctrl.busUtilRead 3.62 # Data bus utilization in percentage for reads +system.mem_ctrl.busUtil 3.63 # Data bus utilization in percentage +system.mem_ctrl.busUtilRead 3.63 # Data bus utilization in percentage for reads system.mem_ctrl.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.mem_ctrl.avgRdQLen 1.00 # Average read queue length when enqueuing system.mem_ctrl.avgWrQLen 0.00 # Average write queue length when enqueuing -system.mem_ctrl.readRowHits 340 # Number of row buffer hits during reads +system.mem_ctrl.readRowHits 341 # Number of row buffer hits during reads system.mem_ctrl.writeRowHits 0 # Number of row buffer hits during writes -system.mem_ctrl.readRowHitRate 76.23 # Row buffer hit rate for reads +system.mem_ctrl.readRowHitRate 76.46 # Row buffer hit rate for reads system.mem_ctrl.writeRowHitRate nan # Row buffer hit rate for writes -system.mem_ctrl.avgGap 137578.48 # Average gap between requests -system.mem_ctrl.pageHitRate 76.23 # Row buffer hit rate, read and write combined -system.mem_ctrl_0.actEnergy 302400 # Energy for activate commands per rank (pJ) -system.mem_ctrl_0.preEnergy 165000 # Energy for precharge commands per rank (pJ) -system.mem_ctrl_0.readEnergy 1583400 # Energy for read commands per rank (pJ) +system.mem_ctrl.avgGap 137264.57 # Average gap between requests +system.mem_ctrl.pageHitRate 76.46 # Row buffer hit rate, read and write combined +system.mem_ctrl_0.actEnergy 309960 # Energy for activate commands per rank (pJ) +system.mem_ctrl_0.preEnergy 169125 # Energy for precharge commands per rank (pJ) +system.mem_ctrl_0.readEnergy 1591200 # Energy for read commands per rank (pJ) system.mem_ctrl_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.mem_ctrl_0.refreshEnergy 3559920 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_0.actBackEnergy 37159155 # Energy for active background per rank (pJ) -system.mem_ctrl_0.preBackEnergy 262500 # Energy for precharge background per rank (pJ) -system.mem_ctrl_0.totalEnergy 43032375 # Total energy per rank (pJ) -system.mem_ctrl_0.averagePower 785.782110 # Core power per rank (mW) -system.mem_ctrl_0.memoryStateTime::IDLE 256750 # Time in different power states +system.mem_ctrl_0.actBackEnergy 37059120 # Energy for active background per rank (pJ) +system.mem_ctrl_0.preBackEnergy 350250 # Energy for precharge background per rank (pJ) +system.mem_ctrl_0.totalEnergy 43039575 # Total energy per rank (pJ) +system.mem_ctrl_0.averagePower 785.913583 # Core power per rank (mW) +system.mem_ctrl_0.memoryStateTime::IDLE 388750 # Time in different power states system.mem_ctrl_0.memoryStateTime::REF 1820000 # Time in different power states system.mem_ctrl_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrl_0.memoryStateTime::ACT 52700750 # Time in different power states +system.mem_ctrl_0.memoryStateTime::ACT 52568750 # Time in different power states system.mem_ctrl_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrl_1.actEnergy 393120 # Energy for activate commands per rank (pJ) -system.mem_ctrl_1.preEnergy 214500 # Energy for precharge commands per rank (pJ) +system.mem_ctrl_1.actEnergy 385560 # Energy for activate commands per rank (pJ) +system.mem_ctrl_1.preEnergy 210375 # Energy for precharge commands per rank (pJ) system.mem_ctrl_1.readEnergy 1489800 # Energy for read commands per rank (pJ) system.mem_ctrl_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.mem_ctrl_1.refreshEnergy 3559920 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_1.actBackEnergy 35929665 # Energy for active background per rank (pJ) -system.mem_ctrl_1.preBackEnergy 1341000 # Energy for precharge background per rank (pJ) -system.mem_ctrl_1.totalEnergy 42928005 # Total energy per rank (pJ) -system.mem_ctrl_1.averagePower 783.876287 # Core power per rank (mW) -system.mem_ctrl_1.memoryStateTime::IDLE 2295000 # Time in different power states +system.mem_ctrl_1.actBackEnergy 35948475 # Energy for active background per rank (pJ) +system.mem_ctrl_1.preBackEnergy 1324500 # Energy for precharge background per rank (pJ) +system.mem_ctrl_1.totalEnergy 42918630 # Total energy per rank (pJ) +system.mem_ctrl_1.averagePower 783.705097 # Core power per rank (mW) +system.mem_ctrl_1.memoryStateTime::IDLE 2128500 # Time in different power states system.mem_ctrl_1.memoryStateTime::REF 1820000 # Time in different power states system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrl_1.memoryStateTime::ACT 51042000 # Time in different power states +system.mem_ctrl_1.memoryStateTime::ACT 51068500 # Time in different power states system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 1188 # DTB read hits +system.cpu.dtb.read_hits 1190 # DTB read hits system.cpu.dtb.read_misses 7 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 1195 # DTB read accesses +system.cpu.dtb.read_accesses 1197 # DTB read accesses system.cpu.dtb.write_hits 865 # DTB write hits system.cpu.dtb.write_misses 3 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations system.cpu.dtb.write_accesses 868 # DTB write accesses -system.cpu.dtb.data_hits 2053 # DTB hits +system.cpu.dtb.data_hits 2055 # DTB hits system.cpu.dtb.data_misses 10 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 2063 # DTB accesses -system.cpu.itb.fetch_hits 6451 # ITB hits +system.cpu.dtb.data_accesses 2065 # DTB accesses +system.cpu.itb.fetch_hits 6464 # ITB hits system.cpu.itb.fetch_misses 17 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 6468 # ITB accesses +system.cpu.itb.fetch_accesses 6481 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -282,87 +282,87 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 61610 # number of cpu cycles simulated +system.cpu.numCycles 61470 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 6440 # Number of instructions committed -system.cpu.committedOps 6440 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 6368 # Number of integer alu accesses +system.cpu.committedInsts 6453 # Number of instructions committed +system.cpu.committedOps 6453 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 6380 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses system.cpu.num_func_calls 251 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 754 # number of instructions that are conditional controls -system.cpu.num_int_insts 6368 # number of integer instructions +system.cpu.num_conditional_control_insts 759 # number of instructions that are conditional controls +system.cpu.num_int_insts 6380 # number of integer instructions system.cpu.num_fp_insts 10 # number of float instructions -system.cpu.num_int_register_reads 8380 # number of times the integer registers were read -system.cpu.num_int_register_writes 4614 # number of times the integer registers were written +system.cpu.num_int_register_reads 8392 # number of times the integer registers were read +system.cpu.num_int_register_writes 4621 # number of times the integer registers were written system.cpu.num_fp_register_reads 8 # number of times the floating registers were read system.cpu.num_fp_register_writes 2 # number of times the floating registers were written -system.cpu.num_mem_refs 2063 # number of memory refs -system.cpu.num_load_insts 1195 # Number of load instructions +system.cpu.num_mem_refs 2065 # number of memory refs +system.cpu.num_load_insts 1197 # Number of load instructions system.cpu.num_store_insts 868 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 61610 # Number of busy cycles +system.cpu.num_busy_cycles 61470 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 1054 # Number of branches fetched +system.cpu.Branches 1060 # Number of branches fetched system.cpu.op_class::No_OpClass 19 0.29% 0.29% # Class of executed instruction -system.cpu.op_class::IntAlu 4365 67.67% 67.97% # Class of executed instruction -system.cpu.op_class::IntMult 1 0.02% 67.98% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 67.98% # Class of executed instruction -system.cpu.op_class::FloatAdd 2 0.03% 68.02% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 68.02% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 68.02% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 68.02% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 68.02% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 68.02% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 68.02% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 68.02% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 68.02% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 68.02% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 68.02% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 68.02% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 68.02% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 68.02% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 68.02% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 68.02% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 68.02% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 68.02% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 68.02% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 68.02% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 68.02% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 68.02% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 68.02% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 68.02% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.02% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 68.02% # Class of executed instruction -system.cpu.op_class::MemRead 1195 18.53% 86.54% # Class of executed instruction -system.cpu.op_class::MemWrite 868 13.46% 100.00% # Class of executed instruction +system.cpu.op_class::IntAlu 4376 67.71% 68.00% # Class of executed instruction +system.cpu.op_class::IntMult 1 0.02% 68.02% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 68.02% # Class of executed instruction +system.cpu.op_class::FloatAdd 2 0.03% 68.05% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 68.05% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 68.05% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 68.05% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 68.05% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 68.05% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 68.05% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 68.05% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 68.05% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 68.05% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 68.05% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 68.05% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 68.05% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 68.05% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 68.05% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 68.05% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 68.05% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 68.05% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 68.05% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 68.05% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 68.05% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 68.05% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 68.05% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 68.05% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.05% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 68.05% # Class of executed instruction +system.cpu.op_class::MemRead 1197 18.52% 86.57% # Class of executed instruction +system.cpu.op_class::MemWrite 868 13.43% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 6450 # Class of executed instruction +system.cpu.op_class::total 6463 # Class of executed instruction system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 104.302306 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 1885 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 104.645861 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 1887 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 168 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 11.220238 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 11.232143 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 104.302306 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.101858 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.101858 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 104.645861 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.102193 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.102193 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 168 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 12 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 156 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.164062 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 4274 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 4274 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 1093 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1093 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 4278 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 4278 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 1095 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1095 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 792 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 792 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 1885 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1885 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1885 # number of overall hits -system.cpu.dcache.overall_hits::total 1885 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 1887 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1887 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 1887 # number of overall hits +system.cpu.dcache.overall_hits::total 1887 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 95 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 95 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 73 # number of WriteReq misses @@ -371,38 +371,38 @@ system.cpu.dcache.demand_misses::cpu.data 168 # n system.cpu.dcache.demand_misses::total 168 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 168 # number of overall misses system.cpu.dcache.overall_misses::total 168 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 9733000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 9733000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 7588000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 7588000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 17321000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 17321000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 17321000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 17321000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1188 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1188 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_latency::cpu.data 10102000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 10102000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 7278000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 7278000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 17380000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 17380000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 17380000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 17380000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1190 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1190 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2053 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2053 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2053 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2053 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.079966 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.079966 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2055 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2055 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2055 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2055 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.079832 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.079832 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.084393 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.084393 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.081831 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.081831 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.081831 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.081831 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 102452.631579 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 102452.631579 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 103945.205479 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 103945.205479 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 103101.190476 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 103101.190476 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 103101.190476 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 103101.190476 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.081752 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.081752 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.081752 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.081752 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 106336.842105 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 106336.842105 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 99698.630137 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 99698.630137 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 103452.380952 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 103452.380952 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 103452.380952 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 103452.380952 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -419,82 +419,82 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 168 system.cpu.dcache.demand_mshr_misses::total 168 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 168 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9543000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 9543000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7442000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 7442000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16985000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 16985000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16985000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 16985000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.079966 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.079966 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9912000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 9912000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7132000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 7132000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 17044000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 17044000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 17044000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 17044000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.079832 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.079832 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.081831 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.081831 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.081831 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.081831 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 100452.631579 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 100452.631579 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 101945.205479 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 101945.205479 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 101101.190476 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 101101.190476 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 101101.190476 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 101101.190476 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.081752 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.081752 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.081752 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.081752 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 104336.842105 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 104336.842105 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 97698.630137 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 97698.630137 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 101452.380952 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 101452.380952 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 101452.380952 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 101452.380952 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 62 # number of replacements -system.cpu.icache.tags.tagsinuse 113.926978 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 6170 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 113.715440 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 6183 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 281 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 21.957295 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 22.003559 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 113.926978 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.445027 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.445027 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 113.715440 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.444201 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.444201 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 219 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 167 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.855469 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 13183 # Number of tag accesses -system.cpu.icache.tags.data_accesses 13183 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 6170 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 6170 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 6170 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 6170 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 6170 # number of overall hits -system.cpu.icache.overall_hits::total 6170 # number of overall hits +system.cpu.icache.tags.tag_accesses 13209 # Number of tag accesses +system.cpu.icache.tags.data_accesses 13209 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 6183 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 6183 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 6183 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 6183 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 6183 # number of overall hits +system.cpu.icache.overall_hits::total 6183 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 281 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 281 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 281 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 281 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 281 # number of overall misses system.cpu.icache.overall_misses::total 281 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 28181000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 28181000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 28181000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 28181000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 28181000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 28181000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 6451 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 6451 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 6451 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 6451 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 6451 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 6451 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.043559 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.043559 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.043559 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.043559 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.043559 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.043559 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 100288.256228 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 100288.256228 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 100288.256228 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 100288.256228 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 100288.256228 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 100288.256228 # average overall miss latency +system.cpu.icache.ReadReq_miss_latency::cpu.inst 27952000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 27952000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 27952000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 27952000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 27952000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 27952000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 6464 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 6464 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 6464 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 6464 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 6464 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 6464 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.043472 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.043472 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.043472 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.043472 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.043472 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.043472 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 99473.309609 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 99473.309609 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 99473.309609 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 99473.309609 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 99473.309609 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 99473.309609 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -509,24 +509,24 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 281 system.cpu.icache.demand_mshr_misses::total 281 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 281 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 281 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 27619000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 27619000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 27619000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 27619000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 27619000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 27619000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.043559 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.043559 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.043559 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.043559 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.043559 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.043559 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 98288.256228 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 98288.256228 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 98288.256228 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 98288.256228 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 98288.256228 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 98288.256228 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 27390000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 27390000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 27390000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 27390000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 27390000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 27390000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.043472 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.043472 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.043472 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.043472 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.043472 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.043472 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 97473.309609 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 97473.309609 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 97473.309609 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 97473.309609 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 97473.309609 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 97473.309609 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.l2bus.snoop_filter.tot_requests 511 # Total number of requests made to the snoop filter. system.l2bus.snoop_filter.hit_single_requests 63 # Number of requests hitting in the snoop filter with a single holder of the requested data. @@ -564,16 +564,16 @@ system.l2bus.respLayer0.utilization 1.4 # La system.l2bus.respLayer1.occupancy 504000 # Layer occupancy (ticks) system.l2bus.respLayer1.utilization 0.8 # Layer utilization (%) system.l2cache.tags.replacements 0 # number of replacements -system.l2cache.tags.tagsinuse 185.392407 # Cycle average of tags in use +system.l2cache.tags.tagsinuse 185.619069 # Cycle average of tags in use system.l2cache.tags.total_refs 65 # Total number of references to valid blocks. system.l2cache.tags.sampled_refs 373 # Sample count of references to valid blocks. system.l2cache.tags.avg_refs 0.174263 # Average number of references to valid blocks. system.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2cache.tags.occ_blocks::cpu.inst 128.681337 # Average occupied blocks per requestor -system.l2cache.tags.occ_blocks::cpu.data 56.711070 # Average occupied blocks per requestor -system.l2cache.tags.occ_percent::cpu.inst 0.031416 # Average percentage of cache occupancy -system.l2cache.tags.occ_percent::cpu.data 0.013845 # Average percentage of cache occupancy -system.l2cache.tags.occ_percent::total 0.045262 # Average percentage of cache occupancy +system.l2cache.tags.occ_blocks::cpu.inst 128.455542 # Average occupied blocks per requestor +system.l2cache.tags.occ_blocks::cpu.data 57.163528 # Average occupied blocks per requestor +system.l2cache.tags.occ_percent::cpu.inst 0.031361 # Average percentage of cache occupancy +system.l2cache.tags.occ_percent::cpu.data 0.013956 # Average percentage of cache occupancy +system.l2cache.tags.occ_percent::total 0.045317 # Average percentage of cache occupancy system.l2cache.tags.occ_task_id_blocks::1024 373 # Occupied blocks per task id system.l2cache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id system.l2cache.tags.age_task_id_blocks_1024::1 311 # Occupied blocks per task id @@ -597,17 +597,17 @@ system.l2cache.demand_misses::total 446 # nu system.l2cache.overall_misses::cpu.inst 278 # number of overall misses system.l2cache.overall_misses::cpu.data 168 # number of overall misses system.l2cache.overall_misses::total 446 # number of overall misses -system.l2cache.ReadExReq_miss_latency::cpu.data 7223000 # number of ReadExReq miss cycles -system.l2cache.ReadExReq_miss_latency::total 7223000 # number of ReadExReq miss cycles -system.l2cache.ReadSharedReq_miss_latency::cpu.inst 26711000 # number of ReadSharedReq miss cycles -system.l2cache.ReadSharedReq_miss_latency::cpu.data 9258000 # number of ReadSharedReq miss cycles -system.l2cache.ReadSharedReq_miss_latency::total 35969000 # number of ReadSharedReq miss cycles -system.l2cache.demand_miss_latency::cpu.inst 26711000 # number of demand (read+write) miss cycles -system.l2cache.demand_miss_latency::cpu.data 16481000 # number of demand (read+write) miss cycles -system.l2cache.demand_miss_latency::total 43192000 # number of demand (read+write) miss cycles -system.l2cache.overall_miss_latency::cpu.inst 26711000 # number of overall miss cycles -system.l2cache.overall_miss_latency::cpu.data 16481000 # number of overall miss cycles -system.l2cache.overall_miss_latency::total 43192000 # number of overall miss cycles +system.l2cache.ReadExReq_miss_latency::cpu.data 6913000 # number of ReadExReq miss cycles +system.l2cache.ReadExReq_miss_latency::total 6913000 # number of ReadExReq miss cycles +system.l2cache.ReadSharedReq_miss_latency::cpu.inst 26482000 # number of ReadSharedReq miss cycles +system.l2cache.ReadSharedReq_miss_latency::cpu.data 9627000 # number of ReadSharedReq miss cycles +system.l2cache.ReadSharedReq_miss_latency::total 36109000 # number of ReadSharedReq miss cycles +system.l2cache.demand_miss_latency::cpu.inst 26482000 # number of demand (read+write) miss cycles +system.l2cache.demand_miss_latency::cpu.data 16540000 # number of demand (read+write) miss cycles +system.l2cache.demand_miss_latency::total 43022000 # number of demand (read+write) miss cycles +system.l2cache.overall_miss_latency::cpu.inst 26482000 # number of overall miss cycles +system.l2cache.overall_miss_latency::cpu.data 16540000 # number of overall miss cycles +system.l2cache.overall_miss_latency::total 43022000 # number of overall miss cycles system.l2cache.ReadExReq_accesses::cpu.data 73 # number of ReadExReq accesses(hits+misses) system.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses) system.l2cache.ReadSharedReq_accesses::cpu.inst 281 # number of ReadSharedReq accesses(hits+misses) @@ -630,17 +630,17 @@ system.l2cache.demand_miss_rate::total 0.993318 # mi system.l2cache.overall_miss_rate::cpu.inst 0.989324 # miss rate for overall accesses system.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.l2cache.overall_miss_rate::total 0.993318 # miss rate for overall accesses -system.l2cache.ReadExReq_avg_miss_latency::cpu.data 98945.205479 # average ReadExReq miss latency -system.l2cache.ReadExReq_avg_miss_latency::total 98945.205479 # average ReadExReq miss latency -system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 96082.733813 # average ReadSharedReq miss latency -system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 97452.631579 # average ReadSharedReq miss latency -system.l2cache.ReadSharedReq_avg_miss_latency::total 96431.635389 # average ReadSharedReq miss latency -system.l2cache.demand_avg_miss_latency::cpu.inst 96082.733813 # average overall miss latency -system.l2cache.demand_avg_miss_latency::cpu.data 98101.190476 # average overall miss latency -system.l2cache.demand_avg_miss_latency::total 96843.049327 # average overall miss latency -system.l2cache.overall_avg_miss_latency::cpu.inst 96082.733813 # average overall miss latency -system.l2cache.overall_avg_miss_latency::cpu.data 98101.190476 # average overall miss latency -system.l2cache.overall_avg_miss_latency::total 96843.049327 # average overall miss latency +system.l2cache.ReadExReq_avg_miss_latency::cpu.data 94698.630137 # average ReadExReq miss latency +system.l2cache.ReadExReq_avg_miss_latency::total 94698.630137 # average ReadExReq miss latency +system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 95258.992806 # average ReadSharedReq miss latency +system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 101336.842105 # average ReadSharedReq miss latency +system.l2cache.ReadSharedReq_avg_miss_latency::total 96806.970509 # average ReadSharedReq miss latency +system.l2cache.demand_avg_miss_latency::cpu.inst 95258.992806 # average overall miss latency +system.l2cache.demand_avg_miss_latency::cpu.data 98452.380952 # average overall miss latency +system.l2cache.demand_avg_miss_latency::total 96461.883408 # average overall miss latency +system.l2cache.overall_avg_miss_latency::cpu.inst 95258.992806 # average overall miss latency +system.l2cache.overall_avg_miss_latency::cpu.data 98452.380952 # average overall miss latency +system.l2cache.overall_avg_miss_latency::total 96461.883408 # average overall miss latency system.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -660,17 +660,17 @@ system.l2cache.demand_mshr_misses::total 446 # nu system.l2cache.overall_mshr_misses::cpu.inst 278 # number of overall MSHR misses system.l2cache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses system.l2cache.overall_mshr_misses::total 446 # number of overall MSHR misses -system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5763000 # number of ReadExReq MSHR miss cycles -system.l2cache.ReadExReq_mshr_miss_latency::total 5763000 # number of ReadExReq MSHR miss cycles -system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 21151000 # number of ReadSharedReq MSHR miss cycles -system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7358000 # number of ReadSharedReq MSHR miss cycles -system.l2cache.ReadSharedReq_mshr_miss_latency::total 28509000 # number of ReadSharedReq MSHR miss cycles -system.l2cache.demand_mshr_miss_latency::cpu.inst 21151000 # number of demand (read+write) MSHR miss cycles -system.l2cache.demand_mshr_miss_latency::cpu.data 13121000 # number of demand (read+write) MSHR miss cycles -system.l2cache.demand_mshr_miss_latency::total 34272000 # number of demand (read+write) MSHR miss cycles -system.l2cache.overall_mshr_miss_latency::cpu.inst 21151000 # number of overall MSHR miss cycles -system.l2cache.overall_mshr_miss_latency::cpu.data 13121000 # number of overall MSHR miss cycles -system.l2cache.overall_mshr_miss_latency::total 34272000 # number of overall MSHR miss cycles +system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5453000 # number of ReadExReq MSHR miss cycles +system.l2cache.ReadExReq_mshr_miss_latency::total 5453000 # number of ReadExReq MSHR miss cycles +system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 20922000 # number of ReadSharedReq MSHR miss cycles +system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7727000 # number of ReadSharedReq MSHR miss cycles +system.l2cache.ReadSharedReq_mshr_miss_latency::total 28649000 # number of ReadSharedReq MSHR miss cycles +system.l2cache.demand_mshr_miss_latency::cpu.inst 20922000 # number of demand (read+write) MSHR miss cycles +system.l2cache.demand_mshr_miss_latency::cpu.data 13180000 # number of demand (read+write) MSHR miss cycles +system.l2cache.demand_mshr_miss_latency::total 34102000 # number of demand (read+write) MSHR miss cycles +system.l2cache.overall_mshr_miss_latency::cpu.inst 20922000 # number of overall MSHR miss cycles +system.l2cache.overall_mshr_miss_latency::cpu.data 13180000 # number of overall MSHR miss cycles +system.l2cache.overall_mshr_miss_latency::total 34102000 # number of overall MSHR miss cycles system.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.inst 0.989324 # mshr miss rate for ReadSharedReq accesses @@ -682,17 +682,17 @@ system.l2cache.demand_mshr_miss_rate::total 0.993318 # system.l2cache.overall_mshr_miss_rate::cpu.inst 0.989324 # mshr miss rate for overall accesses system.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.l2cache.overall_mshr_miss_rate::total 0.993318 # mshr miss rate for overall accesses -system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78945.205479 # average ReadExReq mshr miss latency -system.l2cache.ReadExReq_avg_mshr_miss_latency::total 78945.205479 # average ReadExReq mshr miss latency -system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 76082.733813 # average ReadSharedReq mshr miss latency -system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 77452.631579 # average ReadSharedReq mshr miss latency -system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76431.635389 # average ReadSharedReq mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 76082.733813 # average overall mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::cpu.data 78101.190476 # average overall mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::total 76843.049327 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 76082.733813 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::cpu.data 78101.190476 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::total 76843.049327 # average overall mshr miss latency +system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 74698.630137 # average ReadExReq mshr miss latency +system.l2cache.ReadExReq_avg_mshr_miss_latency::total 74698.630137 # average ReadExReq mshr miss latency +system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 75258.992806 # average ReadSharedReq mshr miss latency +system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 81336.842105 # average ReadSharedReq mshr miss latency +system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76806.970509 # average ReadSharedReq mshr miss latency +system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 75258.992806 # average overall mshr miss latency +system.l2cache.demand_avg_mshr_miss_latency::cpu.data 78452.380952 # average overall mshr miss latency +system.l2cache.demand_avg_mshr_miss_latency::total 76461.883408 # average overall mshr miss latency +system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 75258.992806 # average overall mshr miss latency +system.l2cache.overall_avg_mshr_miss_latency::cpu.data 78452.380952 # average overall mshr miss latency +system.l2cache.overall_avg_mshr_miss_latency::total 76461.883408 # average overall mshr miss latency system.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadResp 373 # Transaction distribution system.membus.trans_dist::ReadExReq 73 # Transaction distribution diff --git a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/config.ini b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/config.ini index 7660b2f8f..59bad1d00 100644 --- a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/config.ini +++ b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/config.ini @@ -224,6 +224,7 @@ clk_domain=system.clk_domain eventq_index=0 forward_latency=4 frontend_latency=3 +point_of_coherency=true response_latency=2 snoop_filter=Null snoop_response_latency=4 diff --git a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/simerr b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/simerr index b3b7d2ff9..8e03cc523 100755 --- a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/simerr +++ b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/simerr @@ -1,3 +1,2 @@ warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (512 Mbytes) warn: Sockets disabled, not accepting gdb connections -warn: mmap failing: arguments not page-aligned: start 0x0 offset 0x7efefeff diff --git a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/simout b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/simout index 0bd088620..f1e009cf1 100755 --- a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/simout +++ b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/simout @@ -1,14 +1,16 @@ +Redirecting stdout to build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-simple/simout +Redirecting stderr to build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-simple/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 21 2016 14:17:41 -gem5 started Jan 21 2016 14:18:13 -gem5 executing on zizzer, pid 60583 -command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-simple -re /z/atgutier/gem5/gem5-commit/tests/run.py build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-simple +gem5 compiled Mar 14 2016 22:04:10 +gem5 started Mar 14 2016 22:06:34 +gem5 executing on phenom, pid 29862 +command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-simple -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-simple Global frequency set at 1000000000000 ticks per second Beginning simulation! info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello World! -Exiting @ tick 367783000 because target called exit() +Exiting @ tick 368887000 because target called exit() diff --git a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/stats.txt b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/stats.txt index e03fcae5a..4088c6bf9 100644 --- a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/stats.txt @@ -1,48 +1,48 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000368 # Number of seconds simulated -sim_ticks 367783000 # Number of ticks simulated -final_tick 367783000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000369 # Number of seconds simulated +sim_ticks 368887000 # Number of ticks simulated +final_tick 368887000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 91194 # Simulator instruction rate (inst/s) -host_op_rate 91153 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5958550453 # Simulator tick rate (ticks/s) -host_mem_usage 611392 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host -sim_insts 5624 # Number of instructions simulated -sim_ops 5624 # Number of ops (including micro ops) simulated +host_inst_rate 25687 # Simulator instruction rate (inst/s) +host_op_rate 25686 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1679592961 # Simulator tick rate (ticks/s) +host_mem_usage 607900 # Number of bytes of host memory used +host_seconds 0.22 # Real time elapsed on the host +sim_insts 5641 # Number of instructions simulated +sim_ops 5641 # Number of ops (including micro ops) simulated system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.mem_ctrl.bytes_read::cpu.inst 22500 # Number of bytes read from this memory -system.mem_ctrl.bytes_read::cpu.data 4289 # Number of bytes read from this memory -system.mem_ctrl.bytes_read::total 26789 # Number of bytes read from this memory -system.mem_ctrl.bytes_inst_read::cpu.inst 22500 # Number of instructions bytes read from this memory -system.mem_ctrl.bytes_inst_read::total 22500 # Number of instructions bytes read from this memory +system.mem_ctrl.bytes_read::cpu.inst 22568 # Number of bytes read from this memory +system.mem_ctrl.bytes_read::cpu.data 4301 # Number of bytes read from this memory +system.mem_ctrl.bytes_read::total 26869 # Number of bytes read from this memory +system.mem_ctrl.bytes_inst_read::cpu.inst 22568 # Number of instructions bytes read from this memory +system.mem_ctrl.bytes_inst_read::total 22568 # Number of instructions bytes read from this memory system.mem_ctrl.bytes_written::cpu.data 3601 # Number of bytes written to this memory system.mem_ctrl.bytes_written::total 3601 # Number of bytes written to this memory -system.mem_ctrl.num_reads::cpu.inst 5625 # Number of read requests responded to by this memory -system.mem_ctrl.num_reads::cpu.data 1132 # Number of read requests responded to by this memory -system.mem_ctrl.num_reads::total 6757 # Number of read requests responded to by this memory +system.mem_ctrl.num_reads::cpu.inst 5642 # Number of read requests responded to by this memory +system.mem_ctrl.num_reads::cpu.data 1135 # Number of read requests responded to by this memory +system.mem_ctrl.num_reads::total 6777 # Number of read requests responded to by this memory system.mem_ctrl.num_writes::cpu.data 901 # Number of write requests responded to by this memory system.mem_ctrl.num_writes::total 901 # Number of write requests responded to by this memory -system.mem_ctrl.bw_read::cpu.inst 61177379 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::cpu.data 11661768 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::total 72839147 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::cpu.inst 61177379 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::total 61177379 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_write::cpu.data 9791100 # Write bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_write::total 9791100 # Write bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.inst 61177379 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.data 21452868 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::total 82630247 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.readReqs 6758 # Number of read requests accepted +system.mem_ctrl.bw_read::cpu.inst 61178627 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::cpu.data 11659397 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::total 72838024 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::cpu.inst 61178627 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::total 61178627 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_write::cpu.data 9761797 # Write bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_write::total 9761797 # Write bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.inst 61178627 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.data 21421194 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::total 82599821 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.readReqs 6778 # Number of read requests accepted system.mem_ctrl.writeReqs 901 # Number of write requests accepted -system.mem_ctrl.readBursts 6758 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrl.readBursts 6778 # Number of DRAM read bursts, including those serviced by the write queue system.mem_ctrl.writeBursts 901 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrl.bytesReadDRAM 426368 # Total number of bytes read from DRAM +system.mem_ctrl.bytesReadDRAM 427648 # Total number of bytes read from DRAM system.mem_ctrl.bytesReadWrQ 6144 # Total number of bytes read from write queue system.mem_ctrl.bytesWritten 4096 # Total number of bytes written to DRAM -system.mem_ctrl.bytesReadSys 26793 # Total read bytes from the system interface side +system.mem_ctrl.bytesReadSys 26873 # Total read bytes from the system interface side system.mem_ctrl.bytesWrittenSys 3601 # Total written bytes from the system interface side system.mem_ctrl.servicedByWrQ 96 # Number of DRAM read bursts serviced by the write queue system.mem_ctrl.mergedWrBursts 807 # Number of DRAM write bursts merged with an existing one @@ -56,12 +56,12 @@ system.mem_ctrl.perBankRdBursts::5 18 # Pe system.mem_ctrl.perBankRdBursts::6 105 # Per bank write bursts system.mem_ctrl.perBankRdBursts::7 518 # Per bank write bursts system.mem_ctrl.perBankRdBursts::8 543 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::9 1211 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::9 1212 # Per bank write bursts system.mem_ctrl.perBankRdBursts::10 899 # Per bank write bursts system.mem_ctrl.perBankRdBursts::11 346 # Per bank write bursts system.mem_ctrl.perBankRdBursts::12 677 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::13 396 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::14 1409 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::13 398 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::14 1426 # Per bank write bursts system.mem_ctrl.perBankRdBursts::15 50 # Per bank write bursts system.mem_ctrl.perBankWrBursts::0 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::1 0 # Per bank write bursts @@ -81,10 +81,10 @@ system.mem_ctrl.perBankWrBursts::14 19 # Pe system.mem_ctrl.perBankWrBursts::15 2 # Per bank write bursts system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrl.totGap 367707000 # Total gap between requests +system.mem_ctrl.totGap 368811000 # Total gap between requests system.mem_ctrl.readPktSize::0 79 # Read request sizes (log2) system.mem_ctrl.readPktSize::1 1 # Read request sizes (log2) -system.mem_ctrl.readPktSize::2 6678 # Read request sizes (log2) +system.mem_ctrl.readPktSize::2 6698 # Read request sizes (log2) system.mem_ctrl.readPktSize::3 0 # Read request sizes (log2) system.mem_ctrl.readPktSize::4 0 # Read request sizes (log2) system.mem_ctrl.readPktSize::5 0 # Read request sizes (log2) @@ -96,7 +96,7 @@ system.mem_ctrl.writePktSize::3 0 # Wr system.mem_ctrl.writePktSize::4 0 # Write request sizes (log2) system.mem_ctrl.writePktSize::5 0 # Write request sizes (log2) system.mem_ctrl.writePktSize::6 0 # Write request sizes (log2) -system.mem_ctrl.rdQLenPdf::0 6662 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::0 6682 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::1 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::2 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::3 0 # What read queue length does an incoming req see @@ -192,27 +192,27 @@ system.mem_ctrl.wrQLenPdf::60 0 # Wh system.mem_ctrl.wrQLenPdf::61 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrl.bytesPerActivate::samples 842 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::mean 509.263658 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::gmean 293.556275 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::stdev 414.582189 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::0-127 268 31.83% 31.83% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::128-255 81 9.62% 41.45% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::256-383 48 5.70% 47.15% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::384-511 49 5.82% 52.97% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::512-639 36 4.28% 57.24% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::640-767 49 5.82% 63.06% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::768-895 19 2.26% 65.32% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::896-1023 21 2.49% 67.81% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::1024-1151 271 32.19% 100.00% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::total 842 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::samples 849 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::mean 506.270907 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::gmean 291.216794 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::stdev 415.367861 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::0-127 272 32.04% 32.04% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::128-255 76 8.95% 40.99% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::256-383 61 7.18% 48.17% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::384-511 46 5.42% 53.59% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::512-639 36 4.24% 57.83% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::640-767 42 4.95% 62.78% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::768-895 24 2.83% 65.61% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::896-1023 15 1.77% 67.37% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::1024-1151 277 32.63% 100.00% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::total 849 # Bytes accessed per row activation system.mem_ctrl.rdPerTurnAround::samples 4 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::mean 1344.750000 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::gmean 1258.849963 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::stdev 502.036104 # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::mean 1349.750000 # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::gmean 1262.645152 # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::stdev 506.185325 # Reads before turning the bus around for writes system.mem_ctrl.rdPerTurnAround::640-703 1 25.00% 25.00% # Reads before turning the bus around for writes system.mem_ctrl.rdPerTurnAround::1216-1279 1 25.00% 50.00% # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::1600-1663 1 25.00% 75.00% # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::1664-1727 1 25.00% 75.00% # Reads before turning the bus around for writes system.mem_ctrl.rdPerTurnAround::1792-1855 1 25.00% 100.00% # Reads before turning the bus around for writes system.mem_ctrl.rdPerTurnAround::total 4 # Reads before turning the bus around for writes system.mem_ctrl.wrPerTurnAround::samples 4 # Writes before turning the bus around for reads @@ -220,55 +220,55 @@ system.mem_ctrl.wrPerTurnAround::mean 16 # Wr system.mem_ctrl.wrPerTurnAround::gmean 16.000000 # Writes before turning the bus around for reads system.mem_ctrl.wrPerTurnAround::16 4 100.00% 100.00% # Writes before turning the bus around for reads system.mem_ctrl.wrPerTurnAround::total 4 # Writes before turning the bus around for reads -system.mem_ctrl.totQLat 27926000 # Total ticks spent queuing -system.mem_ctrl.totMemAccLat 152838500 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrl.totBusLat 33310000 # Total ticks spent in databus transfers -system.mem_ctrl.avgQLat 4191.83 # Average queueing delay per DRAM burst +system.mem_ctrl.totQLat 28067250 # Total ticks spent queuing +system.mem_ctrl.totMemAccLat 153354750 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrl.totBusLat 33410000 # Total ticks spent in databus transfers +system.mem_ctrl.avgQLat 4200.43 # Average queueing delay per DRAM burst system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.mem_ctrl.avgMemAccLat 22941.83 # Average memory access latency per DRAM burst +system.mem_ctrl.avgMemAccLat 22950.43 # Average memory access latency per DRAM burst system.mem_ctrl.avgRdBW 1159.29 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrl.avgWrBW 11.14 # Average achieved write bandwidth in MiByte/s +system.mem_ctrl.avgWrBW 11.10 # Average achieved write bandwidth in MiByte/s system.mem_ctrl.avgRdBWSys 72.85 # Average system read bandwidth in MiByte/s -system.mem_ctrl.avgWrBWSys 9.79 # Average system write bandwidth in MiByte/s +system.mem_ctrl.avgWrBWSys 9.76 # Average system write bandwidth in MiByte/s system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.mem_ctrl.busUtil 9.14 # Data bus utilization in percentage system.mem_ctrl.busUtilRead 9.06 # Data bus utilization in percentage for reads system.mem_ctrl.busUtilWrite 0.09 # Data bus utilization in percentage for writes system.mem_ctrl.avgRdQLen 1.00 # Average read queue length when enqueuing -system.mem_ctrl.avgWrQLen 23.24 # Average write queue length when enqueuing -system.mem_ctrl.readRowHits 5822 # Number of row buffer hits during reads +system.mem_ctrl.avgWrQLen 23.19 # Average write queue length when enqueuing +system.mem_ctrl.readRowHits 5834 # Number of row buffer hits during reads system.mem_ctrl.writeRowHits 58 # Number of row buffer hits during writes -system.mem_ctrl.readRowHitRate 87.39 # Row buffer hit rate for reads +system.mem_ctrl.readRowHitRate 87.31 # Row buffer hit rate for reads system.mem_ctrl.writeRowHitRate 61.70 # Row buffer hit rate for writes -system.mem_ctrl.avgGap 48009.79 # Average gap between requests -system.mem_ctrl.pageHitRate 87.03 # Row buffer hit rate, read and write combined +system.mem_ctrl.avgGap 48028.52 # Average gap between requests +system.mem_ctrl.pageHitRate 86.95 # Row buffer hit rate, read and write combined system.mem_ctrl_0.actEnergy 1058400 # Energy for activate commands per rank (pJ) system.mem_ctrl_0.preEnergy 577500 # Energy for precharge commands per rank (pJ) -system.mem_ctrl_0.readEnergy 8821800 # Energy for read commands per rank (pJ) +system.mem_ctrl_0.readEnergy 8806200 # Energy for read commands per rank (pJ) system.mem_ctrl_0.writeEnergy 38880 # Energy for write commands per rank (pJ) system.mem_ctrl_0.refreshEnergy 23902320 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_0.actBackEnergy 136778625 # Energy for active background per rank (pJ) -system.mem_ctrl_0.preBackEnergy 99747000 # Energy for precharge background per rank (pJ) -system.mem_ctrl_0.totalEnergy 270924525 # Total energy per rank (pJ) -system.mem_ctrl_0.averagePower 739.798888 # Core power per rank (mW) -system.mem_ctrl_0.memoryStateTime::IDLE 164402500 # Time in different power states +system.mem_ctrl_0.actBackEnergy 143993115 # Energy for active background per rank (pJ) +system.mem_ctrl_0.preBackEnergy 93418500 # Energy for precharge background per rank (pJ) +system.mem_ctrl_0.totalEnergy 271794915 # Total energy per rank (pJ) +system.mem_ctrl_0.averagePower 742.175615 # Core power per rank (mW) +system.mem_ctrl_0.memoryStateTime::IDLE 153996500 # Time in different power states system.mem_ctrl_0.memoryStateTime::REF 12220000 # Time in different power states system.mem_ctrl_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrl_0.memoryStateTime::ACT 189605000 # Time in different power states +system.mem_ctrl_0.memoryStateTime::ACT 200230500 # Time in different power states system.mem_ctrl_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrl_1.actEnergy 5299560 # Energy for activate commands per rank (pJ) -system.mem_ctrl_1.preEnergy 2891625 # Energy for precharge commands per rank (pJ) +system.mem_ctrl_1.actEnergy 5344920 # Energy for activate commands per rank (pJ) +system.mem_ctrl_1.preEnergy 2916375 # Energy for precharge commands per rank (pJ) system.mem_ctrl_1.readEnergy 42907800 # Energy for read commands per rank (pJ) system.mem_ctrl_1.writeEnergy 375840 # Energy for write commands per rank (pJ) system.mem_ctrl_1.refreshEnergy 23902320 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_1.actBackEnergy 246879540 # Energy for active background per rank (pJ) -system.mem_ctrl_1.preBackEnergy 3167250 # Energy for precharge background per rank (pJ) -system.mem_ctrl_1.totalEnergy 325423935 # Total energy per rank (pJ) -system.mem_ctrl_1.averagePower 888.617467 # Core power per rank (mW) -system.mem_ctrl_1.memoryStateTime::IDLE 3404750 # Time in different power states +system.mem_ctrl_1.actBackEnergy 246623040 # Energy for active background per rank (pJ) +system.mem_ctrl_1.preBackEnergy 3392250 # Energy for precharge background per rank (pJ) +system.mem_ctrl_1.totalEnergy 325462545 # Total energy per rank (pJ) +system.mem_ctrl_1.averagePower 888.722897 # Core power per rank (mW) +system.mem_ctrl_1.memoryStateTime::IDLE 3452250 # Time in different power states system.mem_ctrl_1.memoryStateTime::REF 12220000 # Time in different power states system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrl_1.memoryStateTime::ACT 350602750 # Time in different power states +system.mem_ctrl_1.memoryStateTime::ACT 350555250 # Time in different power states system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses @@ -289,90 +289,90 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 7 # Number of system calls -system.cpu.numCycles 367783 # number of cpu cycles simulated +system.cpu.numCycles 368887 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 5624 # Number of instructions committed -system.cpu.committedOps 5624 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 4944 # Number of integer alu accesses +system.cpu.committedInsts 5641 # Number of instructions committed +system.cpu.committedOps 5641 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 4957 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 2 # Number of float alu accesses -system.cpu.num_func_calls 190 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 649 # number of instructions that are conditional controls -system.cpu.num_int_insts 4944 # number of integer instructions +system.cpu.num_func_calls 191 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 651 # number of instructions that are conditional controls +system.cpu.num_int_insts 4957 # number of integer instructions system.cpu.num_fp_insts 2 # number of float instructions -system.cpu.num_int_register_reads 7054 # number of times the integer registers were read -system.cpu.num_int_register_writes 3281 # number of times the integer registers were written +system.cpu.num_int_register_reads 7072 # number of times the integer registers were read +system.cpu.num_int_register_writes 3291 # number of times the integer registers were written system.cpu.num_fp_register_reads 3 # number of times the floating registers were read system.cpu.num_fp_register_writes 1 # number of times the floating registers were written -system.cpu.num_mem_refs 2034 # number of memory refs -system.cpu.num_load_insts 1132 # Number of load instructions +system.cpu.num_mem_refs 2037 # number of memory refs +system.cpu.num_load_insts 1135 # Number of load instructions system.cpu.num_store_insts 902 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 367783 # Number of busy cycles +system.cpu.num_busy_cycles 368887 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 883 # Number of branches fetched -system.cpu.op_class::No_OpClass 637 11.32% 11.32% # Class of executed instruction -system.cpu.op_class::IntAlu 2950 52.44% 63.77% # Class of executed instruction -system.cpu.op_class::IntMult 2 0.04% 63.80% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 63.80% # Class of executed instruction -system.cpu.op_class::FloatAdd 2 0.04% 63.84% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::MemRead 1132 20.12% 83.96% # Class of executed instruction -system.cpu.op_class::MemWrite 902 16.04% 100.00% # Class of executed instruction +system.cpu.Branches 886 # Number of branches fetched +system.cpu.op_class::No_OpClass 641 11.36% 11.36% # Class of executed instruction +system.cpu.op_class::IntAlu 2960 52.46% 63.82% # Class of executed instruction +system.cpu.op_class::IntMult 2 0.04% 63.86% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 63.86% # Class of executed instruction +system.cpu.op_class::FloatAdd 2 0.04% 63.90% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::MemRead 1135 20.12% 84.01% # Class of executed instruction +system.cpu.op_class::MemWrite 902 15.99% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 5625 # Class of executed instruction -system.membus.trans_dist::ReadReq 6758 # Transaction distribution -system.membus.trans_dist::ReadResp 6757 # Transaction distribution +system.cpu.op_class::total 5642 # Class of executed instruction +system.membus.trans_dist::ReadReq 6778 # Transaction distribution +system.membus.trans_dist::ReadResp 6777 # Transaction distribution system.membus.trans_dist::WriteReq 901 # Transaction distribution system.membus.trans_dist::WriteResp 901 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.mem_ctrl.port 11251 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.mem_ctrl.port 4066 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 15317 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.mem_ctrl.port 22500 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.mem_ctrl.port 7890 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 30390 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.icache_port::system.mem_ctrl.port 11285 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.mem_ctrl.port 4072 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 15357 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.mem_ctrl.port 22568 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.mem_ctrl.port 7902 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 30470 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 7659 # Request fanout histogram -system.membus.snoop_fanout::mean 0.734561 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.441596 # Request fanout histogram +system.membus.snoop_fanout::samples 7679 # Request fanout histogram +system.membus.snoop_fanout::mean 0.734861 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.441436 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 2033 26.54% 26.54% # Request fanout histogram -system.membus.snoop_fanout::1 5626 73.46% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 2036 26.51% 26.51% # Request fanout histogram +system.membus.snoop_fanout::1 5643 73.49% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 7659 # Request fanout histogram -system.membus.reqLayer0.occupancy 8560000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 7679 # Request fanout histogram +system.membus.reqLayer0.occupancy 8580000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.3 # Layer utilization (%) -system.membus.respLayer0.occupancy 12820000 # Layer occupancy (ticks) +system.membus.respLayer0.occupancy 12857500 # Layer occupancy (ticks) system.membus.respLayer0.utilization 3.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 3545250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 3555500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/config.ini b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/config.ini index 1fc2588a9..9caeea038 100644 --- a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/config.ini +++ b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/config.ini @@ -94,7 +94,6 @@ clk_domain=system.clk_domain clusivity=mostly_incl demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=2 is_read_only=false max_miss_count=0 @@ -136,7 +135,6 @@ clk_domain=system.clk_domain clusivity=mostly_incl demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=2 is_read_only=false max_miss_count=0 @@ -222,6 +220,7 @@ clk_domain=system.clk_domain eventq_index=0 forward_latency=0 frontend_latency=1 +point_of_coherency=false response_latency=1 snoop_filter=system.l2bus.snoop_filter snoop_response_latency=1 @@ -247,7 +246,6 @@ clk_domain=system.clk_domain clusivity=mostly_incl demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=20 is_read_only=false max_miss_count=0 @@ -358,6 +356,7 @@ clk_domain=system.clk_domain eventq_index=0 forward_latency=4 frontend_latency=3 +point_of_coherency=true response_latency=2 snoop_filter=Null snoop_response_latency=4 diff --git a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/simerr b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/simerr index b3b7d2ff9..8e03cc523 100755 --- a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/simerr +++ b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/simerr @@ -1,3 +1,2 @@ warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (512 Mbytes) warn: Sockets disabled, not accepting gdb connections -warn: mmap failing: arguments not page-aligned: start 0x0 offset 0x7efefeff diff --git a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/simout b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/simout index 3d3991862..cda55876d 100755 --- a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/simout +++ b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/simout @@ -1,10 +1,12 @@ +Redirecting stdout to build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-two-level/simout +Redirecting stderr to build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-two-level/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 21 2016 14:17:41 -gem5 started Jan 21 2016 14:18:14 -gem5 executing on zizzer, pid 60586 -command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-two-level -re /z/atgutier/gem5/gem5-commit/tests/run.py build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-two-level +gem5 compiled Mar 14 2016 22:04:10 +gem5 started Mar 14 2016 22:06:34 +gem5 executing on phenom, pid 29863 +command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-two-level -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-two-level Global frequency set at 1000000000000 ticks per second Beginning simulation! diff --git a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/stats.txt b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/stats.txt index 8a196fe6c..c1870ce65 100644 --- a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/stats.txt @@ -4,13 +4,13 @@ sim_seconds 0.000059 # Nu sim_ticks 58892000 # Number of ticks simulated final_tick 58892000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 88343 # Simulator instruction rate (inst/s) -host_op_rate 88311 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 924415589 # Simulator tick rate (ticks/s) -host_mem_usage 616028 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host -sim_insts 5624 # Number of instructions simulated -sim_ops 5624 # Number of ops (including micro ops) simulated +host_inst_rate 44023 # Simulator instruction rate (inst/s) +host_op_rate 44007 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 459268108 # Simulator tick rate (ticks/s) +host_mem_usage 612532 # Number of bytes of host memory used +host_seconds 0.13 # Real time elapsed on the host +sim_insts 5641 # Number of instructions simulated +sim_ops 5641 # Number of ops (including micro ops) simulated system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.mem_ctrl.bytes_read::cpu.inst 18752 # Number of bytes read from this memory @@ -199,12 +199,12 @@ system.mem_ctrl.bytesPerActivate::640-767 4 3.54% 96.46% # B system.mem_ctrl.bytesPerActivate::768-895 1 0.88% 97.35% # Bytes accessed per row activation system.mem_ctrl.bytesPerActivate::1024-1151 3 2.65% 100.00% # Bytes accessed per row activation system.mem_ctrl.bytesPerActivate::total 113 # Bytes accessed per row activation -system.mem_ctrl.totQLat 3878500 # Total ticks spent queuing -system.mem_ctrl.totMemAccLat 11941000 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrl.totQLat 3838500 # Total ticks spent queuing +system.mem_ctrl.totMemAccLat 11901000 # Total ticks spent from burst creation until serviced by the DRAM system.mem_ctrl.totBusLat 2150000 # Total ticks spent in databus transfers -system.mem_ctrl.avgQLat 9019.77 # Average queueing delay per DRAM burst +system.mem_ctrl.avgQLat 8926.74 # Average queueing delay per DRAM burst system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.mem_ctrl.avgMemAccLat 27769.77 # Average memory access latency per DRAM burst +system.mem_ctrl.avgMemAccLat 27676.74 # Average memory access latency per DRAM burst system.mem_ctrl.avgRdBW 467.30 # Average DRAM read bandwidth in MiByte/s system.mem_ctrl.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.mem_ctrl.avgRdBWSys 467.30 # Average system read bandwidth in MiByte/s @@ -271,84 +271,84 @@ system.cpu.workload.num_syscalls 7 # Nu system.cpu.numCycles 58892 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 5624 # Number of instructions committed -system.cpu.committedOps 5624 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 4944 # Number of integer alu accesses +system.cpu.committedInsts 5641 # Number of instructions committed +system.cpu.committedOps 5641 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 4957 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 2 # Number of float alu accesses -system.cpu.num_func_calls 190 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 649 # number of instructions that are conditional controls -system.cpu.num_int_insts 4944 # number of integer instructions +system.cpu.num_func_calls 191 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 651 # number of instructions that are conditional controls +system.cpu.num_int_insts 4957 # number of integer instructions system.cpu.num_fp_insts 2 # number of float instructions -system.cpu.num_int_register_reads 7054 # number of times the integer registers were read -system.cpu.num_int_register_writes 3281 # number of times the integer registers were written +system.cpu.num_int_register_reads 7072 # number of times the integer registers were read +system.cpu.num_int_register_writes 3291 # number of times the integer registers were written system.cpu.num_fp_register_reads 3 # number of times the floating registers were read system.cpu.num_fp_register_writes 1 # number of times the floating registers were written -system.cpu.num_mem_refs 2034 # number of memory refs -system.cpu.num_load_insts 1132 # Number of load instructions +system.cpu.num_mem_refs 2037 # number of memory refs +system.cpu.num_load_insts 1135 # Number of load instructions system.cpu.num_store_insts 902 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_busy_cycles 58892 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 883 # Number of branches fetched -system.cpu.op_class::No_OpClass 637 11.32% 11.32% # Class of executed instruction -system.cpu.op_class::IntAlu 2950 52.44% 63.77% # Class of executed instruction -system.cpu.op_class::IntMult 2 0.04% 63.80% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 63.80% # Class of executed instruction -system.cpu.op_class::FloatAdd 2 0.04% 63.84% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::MemRead 1132 20.12% 83.96% # Class of executed instruction -system.cpu.op_class::MemWrite 902 16.04% 100.00% # Class of executed instruction +system.cpu.Branches 886 # Number of branches fetched +system.cpu.op_class::No_OpClass 641 11.36% 11.36% # Class of executed instruction +system.cpu.op_class::IntAlu 2960 52.46% 63.82% # Class of executed instruction +system.cpu.op_class::IntMult 2 0.04% 63.86% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 63.86% # Class of executed instruction +system.cpu.op_class::FloatAdd 2 0.04% 63.90% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.90% # Class of executed instruction +system.cpu.op_class::MemRead 1135 20.12% 84.01% # Class of executed instruction +system.cpu.op_class::MemWrite 902 15.99% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 5625 # Class of executed instruction +system.cpu.op_class::total 5642 # Class of executed instruction system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 86.277492 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 1896 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 86.268662 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 1899 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 137 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 13.839416 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 13.861314 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 86.277492 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.084255 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.084255 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 86.268662 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.084247 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.084247 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 137 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.133789 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 4203 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 4203 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 1045 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1045 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 4209 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 4209 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 1048 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1048 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 851 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 851 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 1896 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1896 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1896 # number of overall hits -system.cpu.dcache.overall_hits::total 1896 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 1899 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1899 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 1899 # number of overall hits +system.cpu.dcache.overall_hits::total 1899 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 87 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 87 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 50 # number of WriteReq misses @@ -365,22 +365,22 @@ system.cpu.dcache.demand_miss_latency::cpu.data 14174000 system.cpu.dcache.demand_miss_latency::total 14174000 # number of demand (read+write) miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 14174000 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 14174000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1132 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1132 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::cpu.data 1135 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1135 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2033 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2033 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2033 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2033 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.076855 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.076855 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2036 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2036 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2036 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2036 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.076652 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.076652 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.055494 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.055494 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.067388 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.067388 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.067388 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.067388 # miss rate for overall accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.067289 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.067289 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.067289 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.067289 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 102413.793103 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 102413.793103 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 105280 # average WriteReq miss latency @@ -413,14 +413,14 @@ system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13900000 system.cpu.dcache.demand_mshr_miss_latency::total 13900000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13900000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 13900000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076855 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076855 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076652 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076652 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055494 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055494 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.067388 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.067388 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.067388 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.067388 # mshr miss rate for overall accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.067289 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.067289 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.067289 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.067289 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 100413.793103 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 100413.793103 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 103280 # average WriteReq mshr miss latency @@ -431,56 +431,56 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 101459.854015 system.cpu.dcache.overall_avg_mshr_miss_latency::total 101459.854015 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 94 # number of replacements -system.cpu.icache.tags.tagsinuse 110.157629 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 5329 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 110.145403 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 5346 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 297 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 17.942761 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 18 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 110.157629 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.430303 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.430303 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 110.145403 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.430255 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.430255 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 203 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 139 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.792969 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 11549 # Number of tag accesses -system.cpu.icache.tags.data_accesses 11549 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 5329 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 5329 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 5329 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 5329 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 5329 # number of overall hits -system.cpu.icache.overall_hits::total 5329 # number of overall hits +system.cpu.icache.tags.tag_accesses 11583 # Number of tag accesses +system.cpu.icache.tags.data_accesses 11583 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 5346 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 5346 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 5346 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 5346 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 5346 # number of overall hits +system.cpu.icache.overall_hits::total 5346 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 297 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 297 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 297 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 297 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 297 # number of overall misses system.cpu.icache.overall_misses::total 297 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 30270000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 30270000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 30270000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 30270000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 30270000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 30270000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 5626 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 5626 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 5626 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 5626 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 5626 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 5626 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.052791 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.052791 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.052791 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.052791 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.052791 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.052791 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 101919.191919 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 101919.191919 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 101919.191919 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 101919.191919 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 101919.191919 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 101919.191919 # average overall miss latency +system.cpu.icache.ReadReq_miss_latency::cpu.inst 30230000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 30230000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 30230000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 30230000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 30230000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 30230000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 5643 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 5643 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 5643 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 5643 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 5643 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 5643 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.052632 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.052632 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.052632 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.052632 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.052632 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.052632 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 101784.511785 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 101784.511785 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 101784.511785 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 101784.511785 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 101784.511785 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 101784.511785 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -495,24 +495,24 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 297 system.cpu.icache.demand_mshr_misses::total 297 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 297 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 297 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 29676000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 29676000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 29676000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 29676000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 29676000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 29676000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.052791 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.052791 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.052791 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.052791 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.052791 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.052791 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 99919.191919 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 99919.191919 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 99919.191919 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 99919.191919 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 99919.191919 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 99919.191919 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 29636000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 29636000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 29636000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 29636000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 29636000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 29636000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.052632 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.052632 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.052632 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.052632 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.052632 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.052632 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 99784.511785 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 99784.511785 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 99784.511785 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 99784.511785 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 99784.511785 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 99784.511785 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.l2bus.snoop_filter.tot_requests 528 # Total number of requests made to the snoop filter. system.l2bus.snoop_filter.hit_single_requests 94 # Number of requests hitting in the snoop filter with a single holder of the requested data. @@ -550,16 +550,16 @@ system.l2bus.respLayer0.utilization 1.5 # La system.l2bus.respLayer1.occupancy 411000 # Layer occupancy (ticks) system.l2bus.respLayer1.utilization 0.7 # Layer utilization (%) system.l2cache.tags.replacements 0 # number of replacements -system.l2cache.tags.tagsinuse 183.881600 # Cycle average of tags in use +system.l2cache.tags.tagsinuse 183.861903 # Cycle average of tags in use system.l2cache.tags.total_refs 98 # Total number of references to valid blocks. system.l2cache.tags.sampled_refs 380 # Sample count of references to valid blocks. system.l2cache.tags.avg_refs 0.257895 # Average number of references to valid blocks. system.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2cache.tags.occ_blocks::cpu.inst 130.357827 # Average occupied blocks per requestor -system.l2cache.tags.occ_blocks::cpu.data 53.523773 # Average occupied blocks per requestor -system.l2cache.tags.occ_percent::cpu.inst 0.031826 # Average percentage of cache occupancy -system.l2cache.tags.occ_percent::cpu.data 0.013067 # Average percentage of cache occupancy -system.l2cache.tags.occ_percent::total 0.044893 # Average percentage of cache occupancy +system.l2cache.tags.occ_blocks::cpu.inst 130.345601 # Average occupied blocks per requestor +system.l2cache.tags.occ_blocks::cpu.data 53.516302 # Average occupied blocks per requestor +system.l2cache.tags.occ_percent::cpu.inst 0.031823 # Average percentage of cache occupancy +system.l2cache.tags.occ_percent::cpu.data 0.013066 # Average percentage of cache occupancy +system.l2cache.tags.occ_percent::total 0.044888 # Average percentage of cache occupancy system.l2cache.tags.occ_task_id_blocks::1024 380 # Occupied blocks per task id system.l2cache.tags.age_task_id_blocks_1024::0 77 # Occupied blocks per task id system.l2cache.tags.age_task_id_blocks_1024::1 303 # Occupied blocks per task id @@ -585,15 +585,15 @@ system.l2cache.overall_misses::cpu.data 137 # nu system.l2cache.overall_misses::total 430 # number of overall misses system.l2cache.ReadExReq_miss_latency::cpu.data 5014000 # number of ReadExReq miss cycles system.l2cache.ReadExReq_miss_latency::total 5014000 # number of ReadExReq miss cycles -system.l2cache.ReadSharedReq_miss_latency::cpu.inst 28701000 # number of ReadSharedReq miss cycles +system.l2cache.ReadSharedReq_miss_latency::cpu.inst 28661000 # number of ReadSharedReq miss cycles system.l2cache.ReadSharedReq_miss_latency::cpu.data 8475000 # number of ReadSharedReq miss cycles -system.l2cache.ReadSharedReq_miss_latency::total 37176000 # number of ReadSharedReq miss cycles -system.l2cache.demand_miss_latency::cpu.inst 28701000 # number of demand (read+write) miss cycles +system.l2cache.ReadSharedReq_miss_latency::total 37136000 # number of ReadSharedReq miss cycles +system.l2cache.demand_miss_latency::cpu.inst 28661000 # number of demand (read+write) miss cycles system.l2cache.demand_miss_latency::cpu.data 13489000 # number of demand (read+write) miss cycles -system.l2cache.demand_miss_latency::total 42190000 # number of demand (read+write) miss cycles -system.l2cache.overall_miss_latency::cpu.inst 28701000 # number of overall miss cycles +system.l2cache.demand_miss_latency::total 42150000 # number of demand (read+write) miss cycles +system.l2cache.overall_miss_latency::cpu.inst 28661000 # number of overall miss cycles system.l2cache.overall_miss_latency::cpu.data 13489000 # number of overall miss cycles -system.l2cache.overall_miss_latency::total 42190000 # number of overall miss cycles +system.l2cache.overall_miss_latency::total 42150000 # number of overall miss cycles system.l2cache.ReadExReq_accesses::cpu.data 50 # number of ReadExReq accesses(hits+misses) system.l2cache.ReadExReq_accesses::total 50 # number of ReadExReq accesses(hits+misses) system.l2cache.ReadSharedReq_accesses::cpu.inst 297 # number of ReadSharedReq accesses(hits+misses) @@ -618,15 +618,15 @@ system.l2cache.overall_miss_rate::cpu.data 1 # system.l2cache.overall_miss_rate::total 0.990783 # miss rate for overall accesses system.l2cache.ReadExReq_avg_miss_latency::cpu.data 100280 # average ReadExReq miss latency system.l2cache.ReadExReq_avg_miss_latency::total 100280 # average ReadExReq miss latency -system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 97955.631399 # average ReadSharedReq miss latency +system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 97819.112628 # average ReadSharedReq miss latency system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 97413.793103 # average ReadSharedReq miss latency -system.l2cache.ReadSharedReq_avg_miss_latency::total 97831.578947 # average ReadSharedReq miss latency -system.l2cache.demand_avg_miss_latency::cpu.inst 97955.631399 # average overall miss latency +system.l2cache.ReadSharedReq_avg_miss_latency::total 97726.315789 # average ReadSharedReq miss latency +system.l2cache.demand_avg_miss_latency::cpu.inst 97819.112628 # average overall miss latency system.l2cache.demand_avg_miss_latency::cpu.data 98459.854015 # average overall miss latency -system.l2cache.demand_avg_miss_latency::total 98116.279070 # average overall miss latency -system.l2cache.overall_avg_miss_latency::cpu.inst 97955.631399 # average overall miss latency +system.l2cache.demand_avg_miss_latency::total 98023.255814 # average overall miss latency +system.l2cache.overall_avg_miss_latency::cpu.inst 97819.112628 # average overall miss latency system.l2cache.overall_avg_miss_latency::cpu.data 98459.854015 # average overall miss latency -system.l2cache.overall_avg_miss_latency::total 98116.279070 # average overall miss latency +system.l2cache.overall_avg_miss_latency::total 98023.255814 # average overall miss latency system.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -648,15 +648,15 @@ system.l2cache.overall_mshr_misses::cpu.data 137 system.l2cache.overall_mshr_misses::total 430 # number of overall MSHR misses system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4014000 # number of ReadExReq MSHR miss cycles system.l2cache.ReadExReq_mshr_miss_latency::total 4014000 # number of ReadExReq MSHR miss cycles -system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 22841000 # number of ReadSharedReq MSHR miss cycles +system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 22801000 # number of ReadSharedReq MSHR miss cycles system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6735000 # number of ReadSharedReq MSHR miss cycles -system.l2cache.ReadSharedReq_mshr_miss_latency::total 29576000 # number of ReadSharedReq MSHR miss cycles -system.l2cache.demand_mshr_miss_latency::cpu.inst 22841000 # number of demand (read+write) MSHR miss cycles +system.l2cache.ReadSharedReq_mshr_miss_latency::total 29536000 # number of ReadSharedReq MSHR miss cycles +system.l2cache.demand_mshr_miss_latency::cpu.inst 22801000 # number of demand (read+write) MSHR miss cycles system.l2cache.demand_mshr_miss_latency::cpu.data 10749000 # number of demand (read+write) MSHR miss cycles -system.l2cache.demand_mshr_miss_latency::total 33590000 # number of demand (read+write) MSHR miss cycles -system.l2cache.overall_mshr_miss_latency::cpu.inst 22841000 # number of overall MSHR miss cycles +system.l2cache.demand_mshr_miss_latency::total 33550000 # number of demand (read+write) MSHR miss cycles +system.l2cache.overall_mshr_miss_latency::cpu.inst 22801000 # number of overall MSHR miss cycles system.l2cache.overall_mshr_miss_latency::cpu.data 10749000 # number of overall MSHR miss cycles -system.l2cache.overall_mshr_miss_latency::total 33590000 # number of overall MSHR miss cycles +system.l2cache.overall_mshr_miss_latency::total 33550000 # number of overall MSHR miss cycles system.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.inst 0.986532 # mshr miss rate for ReadSharedReq accesses @@ -670,15 +670,15 @@ system.l2cache.overall_mshr_miss_rate::cpu.data 1 system.l2cache.overall_mshr_miss_rate::total 0.990783 # mshr miss rate for overall accesses system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80280 # average ReadExReq mshr miss latency system.l2cache.ReadExReq_avg_mshr_miss_latency::total 80280 # average ReadExReq mshr miss latency -system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 77955.631399 # average ReadSharedReq mshr miss latency +system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 77819.112628 # average ReadSharedReq mshr miss latency system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 77413.793103 # average ReadSharedReq mshr miss latency -system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 77831.578947 # average ReadSharedReq mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 77955.631399 # average overall mshr miss latency +system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 77726.315789 # average ReadSharedReq mshr miss latency +system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 77819.112628 # average overall mshr miss latency system.l2cache.demand_avg_mshr_miss_latency::cpu.data 78459.854015 # average overall mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::total 78116.279070 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 77955.631399 # average overall mshr miss latency +system.l2cache.demand_avg_mshr_miss_latency::total 78023.255814 # average overall mshr miss latency +system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 77819.112628 # average overall mshr miss latency system.l2cache.overall_avg_mshr_miss_latency::cpu.data 78459.854015 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::total 78116.279070 # average overall mshr miss latency +system.l2cache.overall_avg_mshr_miss_latency::total 78023.255814 # average overall mshr miss latency system.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadResp 380 # Transaction distribution system.membus.trans_dist::ReadExReq 50 # Transaction distribution |