stats: changes due to recent changesets.

27 files changed, 724 insertions, 421 deletions

diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini
index ee9b56ccf..2a2f37965 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini
@@ -102,6 +102,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
@@ -142,6 +143,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=1
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
@@ -232,6 +234,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
@@ -272,6 +275,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=1
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
@@ -403,6 +407,7 @@ children=tags
 addr_ranges=0:134217727
 assoc=8
 clk_domain=system.clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=false
 hit_latency=50
@@ -438,6 +443,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=20
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini
index 3f9a7bd5f..22813f4db 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini
@@ -102,6 +102,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
@@ -142,6 +143,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=1
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
@@ -191,6 +193,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=20
@@ -320,6 +323,7 @@ children=tags
 addr_ranges=0:134217727
 assoc=8
 clk_domain=system.clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=false
 hit_latency=50
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini
index 8f2902a1b..9e0ef63d1 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini
@@ -15,10 +15,10 @@ boot_cpu_frequency=500
 boot_osflags=root=/dev/hda1 console=ttyS0
 cache_line_size=64
 clk_domain=system.clk_domain
-console=/dist/binaries/console
+console=/scratch/nilay/GEM5/system/binaries/console
 eventq_index=0
 init_param=0
-kernel=/dist/binaries/vmlinux
+kernel=/scratch/nilay/GEM5/system/binaries/vmlinux
 kernel_addr_check=true
 load_addr_mask=1099511627775
 load_offset=0
@@ -26,8 +26,8 @@ mem_mode=timing
 mem_ranges=0:134217727
 memories=system.physmem
 num_work_ids=16
-pal=/dist/binaries/ts_osfpal
-readfile=/work/gem5.latest/tests/halt.sh
+pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal
+readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
 symbolfile=
 system_rev=1024
 system_type=34
@@ -98,6 +98,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
@@ -138,6 +139,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=1
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
@@ -224,6 +226,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
@@ -264,6 +267,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=1
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
@@ -339,7 +343,7 @@ table_size=65536
 [system.disk0.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/dist/disks/linux-latest.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
 read_only=true
 
 [system.disk2]
@@ -362,7 +366,7 @@ table_size=65536
 [system.disk2.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/dist/disks/linux-bigswap2.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
 read_only=true
 
 [system.dvfs_handler]
@@ -395,6 +399,7 @@ children=tags
 addr_ranges=0:134217727
 assoc=8
 clk_domain=system.clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=false
 hit_latency=50
@@ -430,6 +435,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=20
@@ -578,7 +584,7 @@ system=system
 [system.simple_disk.disk]
 type=RawDiskImage
 eventq_index=0
-image_file=/dist/disks/linux-latest.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
 read_only=true
 
 [system.terminal]
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini
index 39571b45c..3be47cc9f 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini
@@ -15,10 +15,10 @@ boot_cpu_frequency=500
 boot_osflags=root=/dev/hda1 console=ttyS0
 cache_line_size=64
 clk_domain=system.clk_domain
-console=/dist/binaries/console
+console=/scratch/nilay/GEM5/system/binaries/console
 eventq_index=0
 init_param=0
-kernel=/dist/binaries/vmlinux
+kernel=/scratch/nilay/GEM5/system/binaries/vmlinux
 kernel_addr_check=true
 load_addr_mask=1099511627775
 load_offset=0
@@ -26,8 +26,8 @@ mem_mode=timing
 mem_ranges=0:134217727
 memories=system.physmem
 num_work_ids=16
-pal=/dist/binaries/ts_osfpal
-readfile=/work/gem5.latest/tests/halt.sh
+pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal
+readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
 symbolfile=
 system_rev=1024
 system_type=34
@@ -98,6 +98,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
@@ -138,6 +139,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=1
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
@@ -187,6 +189,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=20
@@ -260,7 +263,7 @@ table_size=65536
 [system.disk0.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/dist/disks/linux-latest.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
 read_only=true
 
 [system.disk2]
@@ -283,7 +286,7 @@ table_size=65536
 [system.disk2.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/dist/disks/linux-bigswap2.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
 read_only=true
 
 [system.dvfs_handler]
@@ -316,6 +319,7 @@ children=tags
 addr_ranges=0:134217727
 assoc=8
 clk_domain=system.clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=false
 hit_latency=50
@@ -464,7 +468,7 @@ system=system
 [system.simple_disk.disk]
 type=RawDiskImage
 eventq_index=0
-image_file=/dist/disks/linux-latest.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
 read_only=true
 
 [system.terminal]
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini
index aaf42338c..dfefc0ae8 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini
@@ -12,12 +12,12 @@ time_sync_spin_threshold=100000000
 type=LinuxArmSystem
 children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
 atags_addr=134217728
-boot_loader=/dist/binaries/boot_emm.arm
+boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm
 boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
 boot_release_addr=65528
 cache_line_size=64
 clk_domain=system.clk_domain
-dtb_filename=/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb
+dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb
 early_kernel_symbols=false
 enable_context_switch_stats_dump=false
 eventq_index=0
@@ -30,20 +30,20 @@ have_security=false
 have_virtualization=false
 highest_el_is_64=false
 init_param=0
-kernel=/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
+kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
 kernel_addr_check=true
 load_addr_mask=268435455
 load_offset=2147483648
 machine_type=VExpress_EMM
 mem_mode=atomic
 mem_ranges=2147483648:2415919103
-memories=system.physmem system.realview.vram system.realview.nvmem
+memories=system.physmem system.realview.nvmem system.realview.vram
 multi_proc=true
 num_work_ids=16
 panic_on_oops=true
 panic_on_panic=true
 phys_addr_range_64=40
-readfile=/work/gem5.ext/tests/halt.sh
+readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
 reset_addr_64=0
 symbolfile=
 work_begin_ckpt_count=0
@@ -86,7 +86,7 @@ table_size=65536
 [system.cf0.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/dist/disks/linux-aarch32-ael.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-aarch32-ael.img
 read_only=true
 
 [system.clk_domain]
@@ -142,6 +142,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
@@ -218,6 +219,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=1
@@ -328,6 +330,7 @@ children=prefetcher tags
 addr_ranges=0:18446744073709551615
 assoc=16
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=12
@@ -349,19 +352,27 @@ mem_side=system.toL2Bus.slave[0]
 
 [system.cpu0.l2cache.prefetcher]
 type=StridePrefetcher
+cache_snoop=false
 clk_domain=system.cpu_clk_domain
-cross_pages=false
-data_accesses_only=false
 degree=8
 eventq_index=0
-inst_tagged=true
 latency=1
-on_miss_only=false
-on_prefetch=true
-on_read_only=false
-serial_squash=false
-size=100
+max_conf=7
+min_conf=0
+on_data=true
+on_inst=true
+on_miss=false
+on_read=true
+on_write=true
+queue_filter=true
+queue_size=32
+queue_squash=true
+start_conf=4
 sys=system
+table_assoc=4
+table_sets=16
+tag_prefetch=true
+thresh_conf=4
 use_master_id=true
 
 [system.cpu0.l2cache.tags]
@@ -435,6 +446,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
@@ -511,6 +523,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=1
@@ -621,6 +634,7 @@ children=prefetcher tags
 addr_ranges=0:18446744073709551615
 assoc=16
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=12
@@ -642,19 +656,27 @@ mem_side=system.toL2Bus.slave[1]
 
 [system.cpu1.l2cache.prefetcher]
 type=StridePrefetcher
+cache_snoop=false
 clk_domain=system.cpu_clk_domain
-cross_pages=false
-data_accesses_only=false
 degree=8
 eventq_index=0
-inst_tagged=true
 latency=1
-on_miss_only=false
-on_prefetch=true
-on_read_only=false
-serial_squash=false
-size=100
+max_conf=7
+min_conf=0
+on_data=true
+on_inst=true
+on_miss=false
+on_read=true
+on_write=true
+queue_filter=true
+queue_size=32
+queue_squash=true
+start_conf=4
 sys=system
+table_assoc=4
+table_sets=16
+tag_prefetch=true
+thresh_conf=4
 use_master_id=true
 
 [system.cpu1.l2cache.tags]
@@ -721,6 +743,7 @@ children=tags
 addr_ranges=2147483648:2415919103
 assoc=8
 clk_domain=system.clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=false
 hit_latency=50
@@ -756,6 +779,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=20
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini
index ce59aa175..214674a58 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini
@@ -12,12 +12,12 @@ time_sync_spin_threshold=100000000
 type=LinuxArmSystem
 children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain
 atags_addr=134217728
-boot_loader=/dist/binaries/boot_emm.arm
+boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm
 boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
 boot_release_addr=65528
 cache_line_size=64
 clk_domain=system.clk_domain
-dtb_filename=/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb
+dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb
 early_kernel_symbols=false
 enable_context_switch_stats_dump=false
 eventq_index=0
@@ -30,20 +30,20 @@ have_security=false
 have_virtualization=false
 highest_el_is_64=false
 init_param=0
-kernel=/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
+kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
 kernel_addr_check=true
 load_addr_mask=268435455
 load_offset=2147483648
 machine_type=VExpress_EMM
 mem_mode=atomic
 mem_ranges=2147483648:2415919103
-memories=system.physmem system.realview.vram system.realview.nvmem
+memories=system.physmem system.realview.nvmem system.realview.vram
 multi_proc=true
 num_work_ids=16
 panic_on_oops=true
 panic_on_panic=true
 phys_addr_range_64=40
-readfile=/work/gem5.ext/tests/halt.sh
+readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
 reset_addr_64=0
 symbolfile=
 work_begin_ckpt_count=0
@@ -86,7 +86,7 @@ table_size=65536
 [system.cf0.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/dist/disks/linux-aarch32-ael.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-aarch32-ael.img
 read_only=true
 
 [system.clk_domain]
@@ -142,6 +142,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
@@ -218,6 +219,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=1
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
@@ -328,6 +330,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=20
@@ -411,6 +414,7 @@ children=tags
 addr_ranges=2147483648:2415919103
 assoc=8
 clk_domain=system.clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=false
 hit_latency=50
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini
index a40d111c2..ab3d1e239 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini
@@ -12,12 +12,12 @@ time_sync_spin_threshold=100000000
 type=LinuxArmSystem
 children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
 atags_addr=134217728
-boot_loader=/dist/binaries/boot_emm.arm
+boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm
 boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
 boot_release_addr=65528
 cache_line_size=64
 clk_domain=system.clk_domain
-dtb_filename=/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb
+dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb
 early_kernel_symbols=false
 enable_context_switch_stats_dump=false
 eventq_index=0
@@ -30,20 +30,20 @@ have_security=false
 have_virtualization=false
 highest_el_is_64=false
 init_param=0
-kernel=/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
+kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
 kernel_addr_check=true
 load_addr_mask=268435455
 load_offset=2147483648
 machine_type=VExpress_EMM
 mem_mode=timing
 mem_ranges=2147483648:2415919103
-memories=system.physmem system.realview.vram system.realview.nvmem
+memories=system.physmem system.realview.nvmem system.realview.vram
 multi_proc=true
 num_work_ids=16
 panic_on_oops=true
 panic_on_panic=true
 phys_addr_range_64=40
-readfile=/work/gem5.ext/tests/halt.sh
+readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
 reset_addr_64=0
 symbolfile=
 work_begin_ckpt_count=0
@@ -86,7 +86,7 @@ table_size=65536
 [system.cf0.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/dist/disks/linux-aarch32-ael.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-aarch32-ael.img
 read_only=true
 
 [system.clk_domain]
@@ -138,6 +138,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
@@ -214,6 +215,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=1
@@ -324,6 +326,7 @@ children=prefetcher tags
 addr_ranges=0:18446744073709551615
 assoc=16
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=12
@@ -345,19 +348,27 @@ mem_side=system.toL2Bus.slave[0]
 
 [system.cpu0.l2cache.prefetcher]
 type=StridePrefetcher
+cache_snoop=false
 clk_domain=system.cpu_clk_domain
-cross_pages=false
-data_accesses_only=false
 degree=8
 eventq_index=0
-inst_tagged=true
 latency=1
-on_miss_only=false
-on_prefetch=true
-on_read_only=false
-serial_squash=false
-size=100
+max_conf=7
+min_conf=0
+on_data=true
+on_inst=true
+on_miss=false
+on_read=true
+on_write=true
+queue_filter=true
+queue_size=32
+queue_squash=true
+start_conf=4
 sys=system
+table_assoc=4
+table_sets=16
+tag_prefetch=true
+thresh_conf=4
 use_master_id=true
 
 [system.cpu0.l2cache.tags]
@@ -427,6 +438,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
@@ -503,6 +515,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=1
@@ -613,6 +626,7 @@ children=prefetcher tags
 addr_ranges=0:18446744073709551615
 assoc=16
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=12
@@ -634,19 +648,27 @@ mem_side=system.toL2Bus.slave[1]
 
 [system.cpu1.l2cache.prefetcher]
 type=StridePrefetcher
+cache_snoop=false
 clk_domain=system.cpu_clk_domain
-cross_pages=false
-data_accesses_only=false
 degree=8
 eventq_index=0
-inst_tagged=true
 latency=1
-on_miss_only=false
-on_prefetch=true
-on_read_only=false
-serial_squash=false
-size=100
+max_conf=7
+min_conf=0
+on_data=true
+on_inst=true
+on_miss=false
+on_read=true
+on_write=true
+queue_filter=true
+queue_size=32
+queue_squash=true
+start_conf=4
 sys=system
+table_assoc=4
+table_sets=16
+tag_prefetch=true
+thresh_conf=4
 use_master_id=true
 
 [system.cpu1.l2cache.tags]
@@ -713,6 +735,7 @@ children=tags
 addr_ranges=2147483648:2415919103
 assoc=8
 clk_domain=system.clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=false
 hit_latency=50
@@ -748,6 +771,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=20
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini
index 0ae66cc7f..8649cd2a1 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini
@@ -12,12 +12,12 @@ time_sync_spin_threshold=100000000
 type=LinuxArmSystem
 children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain
 atags_addr=134217728
-boot_loader=/dist/binaries/boot_emm.arm
+boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm
 boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
 boot_release_addr=65528
 cache_line_size=64
 clk_domain=system.clk_domain
-dtb_filename=/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb
+dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb
 early_kernel_symbols=false
 enable_context_switch_stats_dump=false
 eventq_index=0
@@ -30,20 +30,20 @@ have_security=false
 have_virtualization=false
 highest_el_is_64=false
 init_param=0
-kernel=/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
+kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
 kernel_addr_check=true
 load_addr_mask=268435455
 load_offset=2147483648
 machine_type=VExpress_EMM
 mem_mode=timing
 mem_ranges=2147483648:2415919103
-memories=system.physmem system.realview.vram system.realview.nvmem
+memories=system.physmem system.realview.nvmem system.realview.vram
 multi_proc=true
 num_work_ids=16
 panic_on_oops=true
 panic_on_panic=true
 phys_addr_range_64=40
-readfile=/work/gem5.ext/tests/halt.sh
+readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
 reset_addr_64=0
 symbolfile=
 work_begin_ckpt_count=0
@@ -86,7 +86,7 @@ table_size=65536
 [system.cf0.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/dist/disks/linux-aarch32-ael.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-aarch32-ael.img
 read_only=true
 
 [system.clk_domain]
@@ -138,6 +138,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
@@ -214,6 +215,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=1
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
@@ -324,6 +326,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=20
@@ -407,6 +410,7 @@ children=tags
 addr_ranges=2147483648:2415919103
 assoc=8
 clk_domain=system.clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=false
 hit_latency=50
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/config.ini
index 72e487329..f413c6048 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/config.ini
@@ -12,12 +12,12 @@ time_sync_spin_threshold=100000000
 type=LinuxArmSystem
 children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
 atags_addr=134217728
-boot_loader=/dist/binaries/boot_emm.arm
+boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm
 boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
 boot_release_addr=65528
 cache_line_size=64
 clk_domain=system.clk_domain
-dtb_filename=/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb
+dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb
 early_kernel_symbols=false
 enable_context_switch_stats_dump=false
 eventq_index=0
@@ -30,20 +30,20 @@ have_security=false
 have_virtualization=false
 highest_el_is_64=false
 init_param=0
-kernel=/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
+kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
 kernel_addr_check=true
 load_addr_mask=268435455
 load_offset=2147483648
 machine_type=VExpress_EMM
 mem_mode=atomic
 mem_ranges=2147483648:2415919103
-memories=system.realview.nvmem system.physmem system.realview.vram
+memories=system.physmem system.realview.nvmem system.realview.vram
 multi_proc=true
 num_work_ids=16
 panic_on_oops=true
 panic_on_panic=true
 phys_addr_range_64=40
-readfile=/work/gem5.ext/tests/halt.sh
+readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
 reset_addr_64=0
 symbolfile=
 work_begin_ckpt_count=0
@@ -86,7 +86,7 @@ table_size=65536
 [system.cf0.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/dist/disks/linux-aarch32-ael.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-aarch32-ael.img
 read_only=true
 
 [system.clk_domain]
@@ -142,6 +142,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
@@ -218,6 +219,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=1
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
@@ -513,6 +515,7 @@ children=tags
 addr_ranges=2147483648:2415919103
 assoc=8
 clk_domain=system.clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=false
 hit_latency=50
@@ -548,6 +551,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=20
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/config.ini
index 14e332c86..76a216752 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/config.ini
@@ -12,12 +12,12 @@ time_sync_spin_threshold=100000000
 type=LinuxArmSystem
 children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
 atags_addr=134217728
-boot_loader=/projects/pd/randd/dist/binaries/boot_emm.arm64
+boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm64
 boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
 boot_release_addr=65528
 cache_line_size=64
 clk_domain=system.clk_domain
-dtb_filename=/projects/pd/randd/dist/binaries/vexpress.aarch64.20140821.dtb
+dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch64.20140821.dtb
 early_kernel_symbols=false
 enable_context_switch_stats_dump=false
 eventq_index=0
@@ -30,7 +30,7 @@ have_security=false
 have_virtualization=false
 highest_el_is_64=false
 init_param=0
-kernel=/projects/pd/randd/dist/binaries/vmlinux.aarch64.20140821
+kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch64.20140821
 kernel_addr_check=true
 load_addr_mask=268435455
 load_offset=2147483648
@@ -43,7 +43,7 @@ num_work_ids=16
 panic_on_oops=true
 panic_on_panic=true
 phys_addr_range_64=40
-readfile=/work/gem5.latest/tests/halt.sh
+readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
 reset_addr_64=0
 symbolfile=
 work_begin_ckpt_count=0
@@ -86,7 +86,7 @@ table_size=65536
 [system.cf0.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/projects/pd/randd/dist/disks/linaro-minimal-aarch64.img
+image_file=/scratch/nilay/GEM5/system/disks/linaro-minimal-aarch64.img
 read_only=true
 
 [system.clk_domain]
@@ -142,6 +142,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
@@ -218,6 +219,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=1
@@ -328,6 +330,7 @@ children=prefetcher tags
 addr_ranges=0:18446744073709551615
 assoc=16
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=12
@@ -349,19 +352,27 @@ mem_side=system.toL2Bus.slave[0]
 
 [system.cpu0.l2cache.prefetcher]
 type=StridePrefetcher
+cache_snoop=false
 clk_domain=system.cpu_clk_domain
-cross_pages=false
-data_accesses_only=false
 degree=8
 eventq_index=0
-inst_tagged=true
 latency=1
-on_miss_only=false
-on_prefetch=true
-on_read_only=false
-serial_squash=false
-size=100
+max_conf=7
+min_conf=0
+on_data=true
+on_inst=true
+on_miss=false
+on_read=true
+on_write=true
+queue_filter=true
+queue_size=32
+queue_squash=true
+start_conf=4
 sys=system
+table_assoc=4
+table_sets=16
+tag_prefetch=true
+thresh_conf=4
 use_master_id=true
 
 [system.cpu0.l2cache.tags]
@@ -435,6 +446,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
@@ -511,6 +523,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=1
@@ -621,6 +634,7 @@ children=prefetcher tags
 addr_ranges=0:18446744073709551615
 assoc=16
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=12
@@ -642,19 +656,27 @@ mem_side=system.toL2Bus.slave[1]
 
 [system.cpu1.l2cache.prefetcher]
 type=StridePrefetcher
+cache_snoop=false
 clk_domain=system.cpu_clk_domain
-cross_pages=false
-data_accesses_only=false
 degree=8
 eventq_index=0
-inst_tagged=true
 latency=1
-on_miss_only=false
-on_prefetch=true
-on_read_only=false
-serial_squash=false
-size=100
+max_conf=7
+min_conf=0
+on_data=true
+on_inst=true
+on_miss=false
+on_read=true
+on_write=true
+queue_filter=true
+queue_size=32
+queue_squash=true
+start_conf=4
 sys=system
+table_assoc=4
+table_sets=16
+tag_prefetch=true
+thresh_conf=4
 use_master_id=true
 
 [system.cpu1.l2cache.tags]
@@ -721,6 +743,7 @@ children=tags
 addr_ranges=2147483648:2415919103
 assoc=8
 clk_domain=system.clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=false
 hit_latency=50
@@ -756,6 +779,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=20
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/config.ini
index f85d9f074..eb15ee6f5 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/config.ini
@@ -12,12 +12,12 @@ time_sync_spin_threshold=100000000
 type=LinuxArmSystem
 children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain
 atags_addr=134217728
-boot_loader=/projects/pd/randd/dist/binaries/boot_emm.arm64
+boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm64
 boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
 boot_release_addr=65528
 cache_line_size=64
 clk_domain=system.clk_domain
-dtb_filename=/projects/pd/randd/dist/binaries/vexpress.aarch64.20140821.dtb
+dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch64.20140821.dtb
 early_kernel_symbols=false
 enable_context_switch_stats_dump=false
 eventq_index=0
@@ -30,20 +30,20 @@ have_security=false
 have_virtualization=false
 highest_el_is_64=false
 init_param=0
-kernel=/projects/pd/randd/dist/binaries/vmlinux.aarch64.20140821
+kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch64.20140821
 kernel_addr_check=true
 load_addr_mask=268435455
 load_offset=2147483648
 machine_type=VExpress_EMM64
 mem_mode=atomic
 mem_ranges=2147483648:2415919103
-memories=system.physmem system.realview.vram system.realview.nvmem
+memories=system.physmem system.realview.nvmem system.realview.vram
 multi_proc=true
 num_work_ids=16
 panic_on_oops=true
 panic_on_panic=true
 phys_addr_range_64=40
-readfile=/work/gem5.latest/tests/halt.sh
+readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
 reset_addr_64=0
 symbolfile=
 work_begin_ckpt_count=0
@@ -86,7 +86,7 @@ table_size=65536
 [system.cf0.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/projects/pd/randd/dist/disks/linaro-minimal-aarch64.img
+image_file=/scratch/nilay/GEM5/system/disks/linaro-minimal-aarch64.img
 read_only=true
 
 [system.clk_domain]
@@ -142,6 +142,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
@@ -218,6 +219,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=1
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
@@ -328,6 +330,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=20
@@ -411,6 +414,7 @@ children=tags
 addr_ranges=2147483648:2415919103
 assoc=8
 clk_domain=system.clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=false
 hit_latency=50
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/config.ini
index bc3129ffa..95d0c343b 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/config.ini
@@ -12,12 +12,12 @@ time_sync_spin_threshold=100000000
 type=LinuxArmSystem
 children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
 atags_addr=134217728
-boot_loader=/projects/pd/randd/dist/binaries/boot_emm.arm64
+boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm64
 boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
 boot_release_addr=65528
 cache_line_size=64
 clk_domain=system.clk_domain
-dtb_filename=/projects/pd/randd/dist/binaries/vexpress.aarch64.20140821.dtb
+dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch64.20140821.dtb
 early_kernel_symbols=false
 enable_context_switch_stats_dump=false
 eventq_index=0
@@ -30,7 +30,7 @@ have_security=false
 have_virtualization=false
 highest_el_is_64=false
 init_param=0
-kernel=/projects/pd/randd/dist/binaries/vmlinux.aarch64.20140821
+kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch64.20140821
 kernel_addr_check=true
 load_addr_mask=268435455
 load_offset=2147483648
@@ -43,7 +43,7 @@ num_work_ids=16
 panic_on_oops=true
 panic_on_panic=true
 phys_addr_range_64=40
-readfile=/work/gem5.latest/tests/halt.sh
+readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
 reset_addr_64=0
 symbolfile=
 work_begin_ckpt_count=0
@@ -86,7 +86,7 @@ table_size=65536
 [system.cf0.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/projects/pd/randd/dist/disks/linaro-minimal-aarch64.img
+image_file=/scratch/nilay/GEM5/system/disks/linaro-minimal-aarch64.img
 read_only=true
 
 [system.clk_domain]
@@ -138,6 +138,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
@@ -214,6 +215,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=1
@@ -324,6 +326,7 @@ children=prefetcher tags
 addr_ranges=0:18446744073709551615
 assoc=16
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=12
@@ -345,19 +348,27 @@ mem_side=system.toL2Bus.slave[0]
 
 [system.cpu0.l2cache.prefetcher]
 type=StridePrefetcher
+cache_snoop=false
 clk_domain=system.cpu_clk_domain
-cross_pages=false
-data_accesses_only=false
 degree=8
 eventq_index=0
-inst_tagged=true
 latency=1
-on_miss_only=false
-on_prefetch=true
-on_read_only=false
-serial_squash=false
-size=100
+max_conf=7
+min_conf=0
+on_data=true
+on_inst=true
+on_miss=false
+on_read=true
+on_write=true
+queue_filter=true
+queue_size=32
+queue_squash=true
+start_conf=4
 sys=system
+table_assoc=4
+table_sets=16
+tag_prefetch=true
+thresh_conf=4
 use_master_id=true
 
 [system.cpu0.l2cache.tags]
@@ -427,6 +438,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
@@ -503,6 +515,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=1
@@ -613,6 +626,7 @@ children=prefetcher tags
 addr_ranges=0:18446744073709551615
 assoc=16
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=12
@@ -634,19 +648,27 @@ mem_side=system.toL2Bus.slave[1]
 
 [system.cpu1.l2cache.prefetcher]
 type=StridePrefetcher
+cache_snoop=false
 clk_domain=system.cpu_clk_domain
-cross_pages=false
-data_accesses_only=false
 degree=8
 eventq_index=0
-inst_tagged=true
 latency=1
-on_miss_only=false
-on_prefetch=true
-on_read_only=false
-serial_squash=false
-size=100
+max_conf=7
+min_conf=0
+on_data=true
+on_inst=true
+on_miss=false
+on_read=true
+on_write=true
+queue_filter=true
+queue_size=32
+queue_squash=true
+start_conf=4
 sys=system
+table_assoc=4
+table_sets=16
+tag_prefetch=true
+thresh_conf=4
 use_master_id=true
 
 [system.cpu1.l2cache.tags]
@@ -713,6 +735,7 @@ children=tags
 addr_ranges=2147483648:2415919103
 assoc=8
 clk_domain=system.clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=false
 hit_latency=50
@@ -748,6 +771,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=20
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/config.ini
index 0f90b5153..a676cb380 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/config.ini
@@ -12,12 +12,12 @@ time_sync_spin_threshold=100000000
 type=LinuxArmSystem
 children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain
 atags_addr=134217728
-boot_loader=/projects/pd/randd/dist/binaries/boot_emm.arm64
+boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm64
 boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
 boot_release_addr=65528
 cache_line_size=64
 clk_domain=system.clk_domain
-dtb_filename=/projects/pd/randd/dist/binaries/vexpress.aarch64.20140821.dtb
+dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch64.20140821.dtb
 early_kernel_symbols=false
 enable_context_switch_stats_dump=false
 eventq_index=0
@@ -30,20 +30,20 @@ have_security=false
 have_virtualization=false
 highest_el_is_64=false
 init_param=0
-kernel=/projects/pd/randd/dist/binaries/vmlinux.aarch64.20140821
+kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch64.20140821
 kernel_addr_check=true
 load_addr_mask=268435455
 load_offset=2147483648
 machine_type=VExpress_EMM64
 mem_mode=timing
 mem_ranges=2147483648:2415919103
-memories=system.physmem system.realview.vram system.realview.nvmem
+memories=system.physmem system.realview.nvmem system.realview.vram
 multi_proc=true
 num_work_ids=16
 panic_on_oops=true
 panic_on_panic=true
 phys_addr_range_64=40
-readfile=/work/gem5.latest/tests/halt.sh
+readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
 reset_addr_64=0
 symbolfile=
 work_begin_ckpt_count=0
@@ -86,7 +86,7 @@ table_size=65536
 [system.cf0.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/projects/pd/randd/dist/disks/linaro-minimal-aarch64.img
+image_file=/scratch/nilay/GEM5/system/disks/linaro-minimal-aarch64.img
 read_only=true
 
 [system.clk_domain]
@@ -138,6 +138,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
@@ -214,6 +215,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=1
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
@@ -324,6 +326,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=20
@@ -407,6 +410,7 @@ children=tags
 addr_ranges=2147483648:2415919103
 assoc=8
 clk_domain=system.clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=false
 hit_latency=50
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/simerr b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/simerr
index 744db2c76..744db2c76 100644..100755
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/simerr
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/simerr
diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini
index 80ccc521c..180ce1eb4 100644
--- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini
@@ -20,7 +20,7 @@ eventq_index=0
 init_param=0
 intel_mp_pointer=system.intel_mp_pointer
 intel_mp_table=system.intel_mp_table
-kernel=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
+kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9
 kernel_addr_check=true
 load_addr_mask=18446744073709551615
 load_offset=0
@@ -28,7 +28,7 @@ mem_mode=atomic
 mem_ranges=0:134217727
 memories=system.physmem
 num_work_ids=16
-readfile=/usr/local/google/home/gabeblack/gem5/hg/gem5/tests/halt.sh
+readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
 smbios_table=system.smbios_table
 symbolfile=
 work_begin_ckpt_count=0
@@ -138,6 +138,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
@@ -188,6 +189,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
@@ -223,6 +225,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=1
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
@@ -289,6 +292,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
@@ -324,6 +328,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=20
@@ -826,6 +831,7 @@ children=tags
 addr_ranges=0:134217727
 assoc=8
 clk_domain=system.clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=false
 hit_latency=50
@@ -1202,7 +1208,7 @@ table_size=65536
 [system.pc.south_bridge.ide.disks0.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/usr/local/google/home/gabeblack/gem5/dist/m5/system/disks/linux-x86.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img
 read_only=true
 
 [system.pc.south_bridge.ide.disks1]
@@ -1225,7 +1231,7 @@ table_size=65536
 [system.pc.south_bridge.ide.disks1.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/usr/local/google/home/gabeblack/gem5/dist/m5/system/disks/linux-bigswap2.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
 read_only=true
 
 [system.pc.south_bridge.int_lines0]
diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini
index 014efe16e..4721e8a2a 100644
--- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini
@@ -20,7 +20,7 @@ eventq_index=0
 init_param=0
 intel_mp_pointer=system.intel_mp_pointer
 intel_mp_table=system.intel_mp_table
-kernel=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
+kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9
 kernel_addr_check=true
 load_addr_mask=18446744073709551615
 load_offset=0
@@ -28,7 +28,7 @@ mem_mode=timing
 mem_ranges=0:134217727
 memories=system.physmem
 num_work_ids=16
-readfile=/usr/local/google/home/gabeblack/gem5/hg/gem5/tests/halt.sh
+readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
 smbios_table=system.smbios_table
 symbolfile=
 work_begin_ckpt_count=0
@@ -134,6 +134,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
@@ -184,6 +185,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
@@ -219,6 +221,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=1
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
@@ -285,6 +288,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
@@ -320,6 +324,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=20
@@ -822,6 +827,7 @@ children=tags
 addr_ranges=0:134217727
 assoc=8
 clk_domain=system.clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=false
 hit_latency=50
@@ -1198,7 +1204,7 @@ table_size=65536
 [system.pc.south_bridge.ide.disks0.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/usr/local/google/home/gabeblack/gem5/dist/m5/system/disks/linux-x86.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img
 read_only=true
 
 [system.pc.south_bridge.ide.disks1]
@@ -1221,7 +1227,7 @@ table_size=65536
 [system.pc.south_bridge.ide.disks1.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/usr/local/google/home/gabeblack/gem5/dist/m5/system/disks/linux-bigswap2.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
 read_only=true
 
 [system.pc.south_bridge.int_lines0]
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/config.ini
index bbd960583..0f651c9f7 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/config.ini
@@ -130,6 +130,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
@@ -553,6 +554,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
@@ -602,6 +604,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=20
@@ -651,6 +654,7 @@ eventq_index=0
 type=LiveProcess
 cmd=hello
 cwd=
+drivers=
 egid=100
 env=
 errout=cerr
@@ -659,6 +663,7 @@ eventq_index=0
 executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/alpha/linux/hello
 gid=100
 input=cin
+kvmInSE=false
 max_stack_size=67108864
 output=cout
 pid=100
@@ -732,6 +737,7 @@ clk_domain=system.clk_domain
 conf_table_reported=true
 device_bus_width=8
 device_rowbuffer_size=1024
+device_size=536870912
 devices_per_rank=8
 dll=true
 eventq_index=0
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt
index 954061e30..eedb7e6a0 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt
@@ -4,26 +4,30 @@ sim_seconds                                  0.000035                       # Nu
 sim_ticks                                    34993500                       # Number of ticks simulated
 final_tick                                   34993500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 162128                       # Simulator instruction rate (inst/s)
-host_op_rate                                   162075                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              885888965                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 292456                       # Number of bytes of host memory used
-host_seconds                                     0.04                       # Real time elapsed on the host
+host_inst_rate                                  25302                       # Simulator instruction rate (inst/s)
+host_op_rate                                    25300                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              138325772                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 279800                       # Number of bytes of host memory used
+host_seconds                                     0.25                       # Real time elapsed on the host
 sim_insts                                        6400                       # Number of instructions simulated
 sim_ops                                          6400                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst             34112                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst             23296                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data             10816                       # Number of bytes read from this memory
 system.physmem.bytes_read::total                34112                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read::cpu.inst        23296                       # Number of instructions bytes read from this memory
 system.physmem.bytes_inst_read::total           23296                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst                533                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst                364                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data                169                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                   533                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst            974809607                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst            665723634                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            309085973                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::total               974809607                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_inst_read::cpu.inst       665723634                       # Instruction read bandwidth from this memory (bytes/s)
 system.physmem.bw_inst_read::total          665723634                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst           974809607                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst           665723634                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           309085973                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::total              974809607                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.readReqs                           533                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
@@ -306,8 +310,8 @@ system.cpu.dcache.tags.total_refs                1973                       # To
 system.cpu.dcache.tags.sampled_refs               169                       # Sample count of references to valid blocks.
 system.cpu.dcache.tags.avg_refs             11.674556                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.inst   104.036694                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.inst     0.025400                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data   104.036694                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.025400                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.025400                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          169                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           25                       # Occupied blocks per task id
@@ -315,53 +319,53 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::1          144
 system.cpu.dcache.tags.occ_task_id_percent::1024     0.041260                       # Percentage of cache occupancy per task id
 system.cpu.dcache.tags.tag_accesses              4569                       # Number of tag accesses
 system.cpu.dcache.tags.data_accesses             4569                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.inst         1233                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::cpu.data         1233                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total            1233                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.inst          740                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data          740                       # number of WriteReq hits
 system.cpu.dcache.WriteReq_hits::total            740                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.inst          1973                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::cpu.data          1973                       # number of demand (read+write) hits
 system.cpu.dcache.demand_hits::total             1973                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.inst         1973                       # number of overall hits
+system.cpu.dcache.overall_hits::cpu.data         1973                       # number of overall hits
 system.cpu.dcache.overall_hits::total            1973                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.inst          102                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::cpu.data          102                       # number of ReadReq misses
 system.cpu.dcache.ReadReq_misses::total           102                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.inst          125                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data          125                       # number of WriteReq misses
 system.cpu.dcache.WriteReq_misses::total          125                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.inst          227                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::cpu.data          227                       # number of demand (read+write) misses
 system.cpu.dcache.demand_misses::total            227                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.inst          227                       # number of overall misses
+system.cpu.dcache.overall_misses::cpu.data          227                       # number of overall misses
 system.cpu.dcache.overall_misses::total           227                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.inst      7703250                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data      7703250                       # number of ReadReq miss cycles
 system.cpu.dcache.ReadReq_miss_latency::total      7703250                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.inst      8670250                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data      8670250                       # number of WriteReq miss cycles
 system.cpu.dcache.WriteReq_miss_latency::total      8670250                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.inst     16373500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data     16373500                       # number of demand (read+write) miss cycles
 system.cpu.dcache.demand_miss_latency::total     16373500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.inst     16373500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data     16373500                       # number of overall miss cycles
 system.cpu.dcache.overall_miss_latency::total     16373500                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.inst         1335                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::cpu.data         1335                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total         1335                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.inst          865                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data          865                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total          865                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.inst         2200                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.data         2200                       # number of demand (read+write) accesses
 system.cpu.dcache.demand_accesses::total         2200                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.inst         2200                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data         2200                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_accesses::total         2200                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.inst     0.076404                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.076404                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_miss_rate::total     0.076404                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.inst     0.144509                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.144509                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_miss_rate::total     0.144509                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.inst     0.103182                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.103182                       # miss rate for demand accesses
 system.cpu.dcache.demand_miss_rate::total     0.103182                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.inst     0.103182                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.103182                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.103182                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 75522.058824                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 75522.058824                       # average ReadReq miss latency
 system.cpu.dcache.ReadReq_avg_miss_latency::total 75522.058824                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst        69362                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data        69362                       # average WriteReq miss latency
 system.cpu.dcache.WriteReq_avg_miss_latency::total        69362                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.inst 72129.955947                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 72129.955947                       # average overall miss latency
 system.cpu.dcache.demand_avg_miss_latency::total 72129.955947                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.inst 72129.955947                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 72129.955947                       # average overall miss latency
 system.cpu.dcache.overall_avg_miss_latency::total 72129.955947                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
@@ -371,45 +375,45 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.ReadReq_mshr_hits::cpu.inst            6                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data            6                       # number of ReadReq MSHR hits
 system.cpu.dcache.ReadReq_mshr_hits::total            6                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.inst           52                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data           52                       # number of WriteReq MSHR hits
 system.cpu.dcache.WriteReq_mshr_hits::total           52                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.inst           58                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data           58                       # number of demand (read+write) MSHR hits
 system.cpu.dcache.demand_mshr_hits::total           58                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.inst           58                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data           58                       # number of overall MSHR hits
 system.cpu.dcache.overall_mshr_hits::total           58                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.inst           96                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data           96                       # number of ReadReq MSHR misses
 system.cpu.dcache.ReadReq_mshr_misses::total           96                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.inst           73                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data           73                       # number of WriteReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::total           73                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.inst          169                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data          169                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.demand_mshr_misses::total          169                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.inst          169                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data          169                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total          169                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst      7131000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      7131000                       # number of ReadReq MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_latency::total      7131000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst      5119000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      5119000                       # number of WriteReq MSHR miss cycles
 system.cpu.dcache.WriteReq_mshr_miss_latency::total      5119000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.inst     12250000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data     12250000                       # number of demand (read+write) MSHR miss cycles
 system.cpu.dcache.demand_mshr_miss_latency::total     12250000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.inst     12250000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data     12250000                       # number of overall MSHR miss cycles
 system.cpu.dcache.overall_mshr_miss_latency::total     12250000                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst     0.071910                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.071910                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.071910                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst     0.084393                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.084393                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.084393                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.inst     0.076818                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.076818                       # mshr miss rate for demand accesses
 system.cpu.dcache.demand_mshr_miss_rate::total     0.076818                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.inst     0.076818                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.076818                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.076818                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 74281.250000                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 74281.250000                       # average ReadReq mshr miss latency
 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 74281.250000                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 70123.287671                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 70123.287671                       # average WriteReq mshr miss latency
 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70123.287671                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 72485.207101                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 72485.207101                       # average overall mshr miss latency
 system.cpu.dcache.demand_avg_mshr_miss_latency::total 72485.207101                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 72485.207101                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 72485.207101                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 72485.207101                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements                 0                       # number of replacements
@@ -502,8 +506,10 @@ system.cpu.l2cache.tags.total_refs                  1                       # To
 system.cpu.l2cache.tags.sampled_refs              460                       # Sample count of references to valid blocks.
 system.cpu.l2cache.tags.avg_refs             0.002174                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   233.762820                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.007134                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   176.091079                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data    57.671740                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.005374                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.001760                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::total     0.007134                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024          460                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::0          135                       # Occupied blocks per task id
@@ -517,45 +523,60 @@ system.cpu.l2cache.demand_hits::cpu.inst            1                       # nu
 system.cpu.l2cache.demand_hits::total               1                       # number of demand (read+write) hits
 system.cpu.l2cache.overall_hits::cpu.inst            1                       # number of overall hits
 system.cpu.l2cache.overall_hits::total              1                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst          460                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.inst          364                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data           96                       # number of ReadReq misses
 system.cpu.l2cache.ReadReq_misses::total          460                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.inst           73                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data           73                       # number of ReadExReq misses
 system.cpu.l2cache.ReadExReq_misses::total           73                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst          533                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.inst          364                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data          169                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_misses::total           533                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst          533                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.inst          364                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data          169                       # number of overall misses
 system.cpu.l2cache.overall_misses::total          533                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     31657000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     24623500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data      7033500                       # number of ReadReq miss cycles
 system.cpu.l2cache.ReadReq_miss_latency::total     31657000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst      5044000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      5044000                       # number of ReadExReq miss cycles
 system.cpu.l2cache.ReadExReq_miss_latency::total      5044000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     36701000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     24623500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data     12077500                       # number of demand (read+write) miss cycles
 system.cpu.l2cache.demand_miss_latency::total     36701000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     36701000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     24623500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data     12077500                       # number of overall miss cycles
 system.cpu.l2cache.overall_miss_latency::total     36701000                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst          461                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.inst          365                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data           96                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::total          461                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.inst           73                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data           73                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total           73                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst          534                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.inst          365                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data          169                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_accesses::total          534                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst          534                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst          365                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data          169                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::total          534                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.997831                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.997260                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data            1                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_miss_rate::total     0.997831                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst            1                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::total            1                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.998127                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.997260                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data            1                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::total     0.998127                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.998127                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.997260                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.998127                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68819.565217                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67646.978022                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 73265.625000                       # average ReadReq miss latency
 system.cpu.l2cache.ReadReq_avg_miss_latency::total 68819.565217                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 69095.890411                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69095.890411                       # average ReadExReq miss latency
 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69095.890411                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68857.410882                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67646.978022                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71464.497041                       # average overall miss latency
 system.cpu.l2cache.demand_avg_miss_latency::total 68857.410882                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68857.410882                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67646.978022                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71464.497041                       # average overall miss latency
 system.cpu.l2cache.overall_avg_miss_latency::total 68857.410882                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
@@ -565,37 +586,49 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          460                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          364                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data           96                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadReq_mshr_misses::total          460                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst           73                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data           73                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total           73                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst          533                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst          364                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data          169                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::total          533                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst          533                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst          364                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data          169                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total          533                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     25891500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     20056500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      5835000                       # number of ReadReq MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_latency::total     25891500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst      4138000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      4138000                       # number of ReadExReq MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      4138000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     30029500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     20056500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      9973000                       # number of demand (read+write) MSHR miss cycles
 system.cpu.l2cache.demand_mshr_miss_latency::total     30029500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     30029500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     20056500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      9973000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.overall_mshr_miss_latency::total     30029500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.997831                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.997260                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.997831                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.998127                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.997260                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data            1                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::total     0.998127                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.998127                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.997260                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.998127                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56285.869565                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55100.274725                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60781.250000                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56285.869565                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 56684.931507                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56684.931507                       # average ReadExReq mshr miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56684.931507                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56340.525328                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55100.274725                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59011.834320                       # average overall mshr miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56340.525328                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56340.525328                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55100.274725                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59011.834320                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56340.525328                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.trans_dist::ReadReq            461                       # Transaction distribution
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini
index 67de80452..9165579c2 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini
@@ -155,6 +155,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
@@ -502,6 +503,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
@@ -551,6 +553,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=20
@@ -600,6 +603,7 @@ eventq_index=0
 type=LiveProcess
 cmd=hello
 cwd=
+drivers=
 egid=100
 env=
 errout=cerr
@@ -608,6 +612,7 @@ eventq_index=0
 executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/alpha/linux/hello
 gid=100
 input=cin
+kvmInSE=false
 max_stack_size=67108864
 output=cout
 pid=100
@@ -681,6 +686,7 @@ clk_domain=system.clk_domain
 conf_table_reported=true
 device_bus_width=8
 device_rowbuffer_size=1024
+device_size=536870912
 devices_per_rank=8
 dll=true
 eventq_index=0
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini
index 091cdad96..8332a7a3a 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini
@@ -82,6 +82,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
@@ -122,6 +123,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
@@ -171,6 +173,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=20
@@ -220,6 +223,7 @@ eventq_index=0
 type=LiveProcess
 cmd=hello
 cwd=
+drivers=
 egid=100
 env=
 errout=cerr
@@ -228,6 +232,7 @@ eventq_index=0
 executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/alpha/linux/hello
 gid=100
 input=cin
+kvmInSE=false
 max_stack_size=67108864
 output=cout
 pid=100
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/config.ini
index c9efff137..66098146a 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/config.ini
@@ -130,6 +130,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
@@ -553,6 +554,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
@@ -602,6 +604,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=20
@@ -651,6 +654,7 @@ eventq_index=0
 type=LiveProcess
 cmd=hello
 cwd=
+drivers=
 egid=100
 env=
 errout=cerr
@@ -659,6 +663,7 @@ eventq_index=0
 executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/alpha/tru64/hello
 gid=100
 input=cin
+kvmInSE=false
 max_stack_size=67108864
 output=cout
 pid=100
@@ -732,6 +737,7 @@ clk_domain=system.clk_domain
 conf_table_reported=true
 device_bus_width=8
 device_rowbuffer_size=1024
+device_size=536870912
 devices_per_rank=8
 dll=true
 eventq_index=0
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt
index 8eeabeb60..6a0f7583b 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt
@@ -4,26 +4,30 @@ sim_seconds                                  0.000019                       # Nu
 sim_ticks                                    18733500                       # Number of ticks simulated
 final_tick                                   18733500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  81438                       # Simulator instruction rate (inst/s)
-host_op_rate                                    81405                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              589715743                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 292180                       # Number of bytes of host memory used
-host_seconds                                     0.03                       # Real time elapsed on the host
+host_inst_rate                                  33056                       # Simulator instruction rate (inst/s)
+host_op_rate                                    33048                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              239448729                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 278492                       # Number of bytes of host memory used
+host_seconds                                     0.08                       # Real time elapsed on the host
 sim_insts                                        2585                       # Number of instructions simulated
 sim_ops                                          2585                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst             19712                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst             14272                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data              5440                       # Number of bytes read from this memory
 system.physmem.bytes_read::total                19712                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read::cpu.inst        14272                       # Number of instructions bytes read from this memory
 system.physmem.bytes_inst_read::total           14272                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst                308                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst                223                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data                 85                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                   308                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst           1052232631                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst            761843756                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            290388876                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::total              1052232631                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_inst_read::cpu.inst       761843756                       # Instruction read bandwidth from this memory (bytes/s)
 system.physmem.bw_inst_read::total          761843756                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst          1052232631                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst           761843756                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           290388876                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::total             1052232631                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.readReqs                           308                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
@@ -306,8 +310,8 @@ system.cpu.dcache.tags.total_refs                 692                       # To
 system.cpu.dcache.tags.sampled_refs                85                       # Sample count of references to valid blocks.
 system.cpu.dcache.tags.avg_refs              8.141176                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.inst    48.478730                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.inst     0.011836                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data    48.478730                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.011836                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.011836                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024           85                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           35                       # Occupied blocks per task id
@@ -315,53 +319,53 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::1           50
 system.cpu.dcache.tags.occ_task_id_percent::1024     0.020752                       # Percentage of cache occupancy per task id
 system.cpu.dcache.tags.tag_accesses              1677                       # Number of tag accesses
 system.cpu.dcache.tags.data_accesses             1677                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.inst          441                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::cpu.data          441                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total             441                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.inst          251                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data          251                       # number of WriteReq hits
 system.cpu.dcache.WriteReq_hits::total            251                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.inst           692                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::cpu.data           692                       # number of demand (read+write) hits
 system.cpu.dcache.demand_hits::total              692                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.inst          692                       # number of overall hits
+system.cpu.dcache.overall_hits::cpu.data          692                       # number of overall hits
 system.cpu.dcache.overall_hits::total             692                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.inst           61                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::cpu.data           61                       # number of ReadReq misses
 system.cpu.dcache.ReadReq_misses::total            61                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.inst           43                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data           43                       # number of WriteReq misses
 system.cpu.dcache.WriteReq_misses::total           43                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.inst          104                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::cpu.data          104                       # number of demand (read+write) misses
 system.cpu.dcache.demand_misses::total            104                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.inst          104                       # number of overall misses
+system.cpu.dcache.overall_misses::cpu.data          104                       # number of overall misses
 system.cpu.dcache.overall_misses::total           104                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.inst      4644500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data      4644500                       # number of ReadReq miss cycles
 system.cpu.dcache.ReadReq_miss_latency::total      4644500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.inst      3502000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data      3502000                       # number of WriteReq miss cycles
 system.cpu.dcache.WriteReq_miss_latency::total      3502000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.inst      8146500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data      8146500                       # number of demand (read+write) miss cycles
 system.cpu.dcache.demand_miss_latency::total      8146500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.inst      8146500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data      8146500                       # number of overall miss cycles
 system.cpu.dcache.overall_miss_latency::total      8146500                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.inst          502                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::cpu.data          502                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total          502                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.inst          294                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data          294                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total          294                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.inst          796                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.data          796                       # number of demand (read+write) accesses
 system.cpu.dcache.demand_accesses::total          796                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.inst          796                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data          796                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_accesses::total          796                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.inst     0.121514                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.121514                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_miss_rate::total     0.121514                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.inst     0.146259                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.146259                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_miss_rate::total     0.146259                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.inst     0.130653                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.130653                       # miss rate for demand accesses
 system.cpu.dcache.demand_miss_rate::total     0.130653                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.inst     0.130653                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.130653                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.130653                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 76139.344262                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 76139.344262                       # average ReadReq miss latency
 system.cpu.dcache.ReadReq_avg_miss_latency::total 76139.344262                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 81441.860465                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 81441.860465                       # average WriteReq miss latency
 system.cpu.dcache.WriteReq_avg_miss_latency::total 81441.860465                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.inst 78331.730769                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 78331.730769                       # average overall miss latency
 system.cpu.dcache.demand_avg_miss_latency::total 78331.730769                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.inst 78331.730769                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 78331.730769                       # average overall miss latency
 system.cpu.dcache.overall_avg_miss_latency::total 78331.730769                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
@@ -371,45 +375,45 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.ReadReq_mshr_hits::cpu.inst            3                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data            3                       # number of ReadReq MSHR hits
 system.cpu.dcache.ReadReq_mshr_hits::total            3                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.inst           16                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data           16                       # number of WriteReq MSHR hits
 system.cpu.dcache.WriteReq_mshr_hits::total           16                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.inst           19                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data           19                       # number of demand (read+write) MSHR hits
 system.cpu.dcache.demand_mshr_hits::total           19                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.inst           19                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data           19                       # number of overall MSHR hits
 system.cpu.dcache.overall_mshr_hits::total           19                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.inst           58                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data           58                       # number of ReadReq MSHR misses
 system.cpu.dcache.ReadReq_mshr_misses::total           58                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.inst           27                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data           27                       # number of WriteReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::total           27                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.inst           85                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data           85                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.demand_mshr_misses::total           85                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.inst           85                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data           85                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total           85                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst      4310500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      4310500                       # number of ReadReq MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_latency::total      4310500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst      2079250                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      2079250                       # number of WriteReq MSHR miss cycles
 system.cpu.dcache.WriteReq_mshr_miss_latency::total      2079250                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.inst      6389750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data      6389750                       # number of demand (read+write) MSHR miss cycles
 system.cpu.dcache.demand_mshr_miss_latency::total      6389750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.inst      6389750                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data      6389750                       # number of overall MSHR miss cycles
 system.cpu.dcache.overall_mshr_miss_latency::total      6389750                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst     0.115538                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.115538                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.115538                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst     0.091837                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.091837                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.091837                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.inst     0.106784                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.106784                       # mshr miss rate for demand accesses
 system.cpu.dcache.demand_mshr_miss_rate::total     0.106784                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.inst     0.106784                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.106784                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.106784                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 74318.965517                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 74318.965517                       # average ReadReq mshr miss latency
 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 74318.965517                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 77009.259259                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77009.259259                       # average WriteReq mshr miss latency
 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77009.259259                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 75173.529412                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75173.529412                       # average overall mshr miss latency
 system.cpu.dcache.demand_avg_mshr_miss_latency::total 75173.529412                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 75173.529412                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75173.529412                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 75173.529412                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements                 0                       # number of replacements
@@ -502,8 +506,10 @@ system.cpu.l2cache.tags.total_refs                  0                       # To
 system.cpu.l2cache.tags.sampled_refs              281                       # Sample count of references to valid blocks.
 system.cpu.l2cache.tags.avg_refs                    0                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   146.534478                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.004472                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   118.615214                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data    27.919264                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.003620                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.000852                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::total     0.004472                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024          281                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::0          142                       # Occupied blocks per task id
@@ -511,45 +517,60 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::1          139
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.008575                       # Percentage of cache occupancy per task id
 system.cpu.l2cache.tags.tag_accesses             2772                       # Number of tag accesses
 system.cpu.l2cache.tags.data_accesses            2772                       # Number of data accesses
-system.cpu.l2cache.ReadReq_misses::cpu.inst          281                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.inst          223                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data           58                       # number of ReadReq misses
 system.cpu.l2cache.ReadReq_misses::total          281                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.inst           27                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data           27                       # number of ReadExReq misses
 system.cpu.l2cache.ReadExReq_misses::total           27                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst          308                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.inst          223                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data           85                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_misses::total           308                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst          308                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.inst          223                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data           85                       # number of overall misses
 system.cpu.l2cache.overall_misses::total          308                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     18913000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     14661500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data      4251500                       # number of ReadReq miss cycles
 system.cpu.l2cache.ReadReq_miss_latency::total     18913000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst      2052250                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      2052250                       # number of ReadExReq miss cycles
 system.cpu.l2cache.ReadExReq_miss_latency::total      2052250                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     20965250                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     14661500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data      6303750                       # number of demand (read+write) miss cycles
 system.cpu.l2cache.demand_miss_latency::total     20965250                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     20965250                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     14661500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data      6303750                       # number of overall miss cycles
 system.cpu.l2cache.overall_miss_latency::total     20965250                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst          281                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.inst          223                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data           58                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::total          281                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.inst           27                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data           27                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total           27                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst          308                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.inst          223                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data           85                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_accesses::total          308                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst          308                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst          223                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data           85                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::total          308                       # number of overall (read+write) accesses
 system.cpu.l2cache.ReadReq_miss_rate::cpu.inst            1                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data            1                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_miss_rate::total            1                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst            1                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::total            1                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.demand_miss_rate::cpu.inst            1                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data            1                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::total            1                       # miss rate for demand accesses
 system.cpu.l2cache.overall_miss_rate::cpu.inst            1                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total            1                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67306.049822                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 65746.636771                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 73301.724138                       # average ReadReq miss latency
 system.cpu.l2cache.ReadReq_avg_miss_latency::total 67306.049822                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 76009.259259                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76009.259259                       # average ReadExReq miss latency
 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76009.259259                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68068.993506                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 65746.636771                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74161.764706                       # average overall miss latency
 system.cpu.l2cache.demand_avg_miss_latency::total 68068.993506                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68068.993506                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 65746.636771                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74161.764706                       # average overall miss latency
 system.cpu.l2cache.overall_avg_miss_latency::total 68068.993506                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
@@ -559,37 +580,49 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          281                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          223                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data           58                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadReq_mshr_misses::total          281                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst           27                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data           27                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total           27                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst          308                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst          223                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data           85                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::total          308                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst          308                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst          223                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data           85                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total          308                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     15398500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     11864500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      3534000                       # number of ReadReq MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_latency::total     15398500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst      1718250                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      1718250                       # number of ReadExReq MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      1718250                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     17116750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     11864500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      5252250                       # number of demand (read+write) MSHR miss cycles
 system.cpu.l2cache.demand_mshr_miss_latency::total     17116750                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     17116750                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     11864500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      5252250                       # number of overall MSHR miss cycles
 system.cpu.l2cache.overall_mshr_miss_latency::total     17116750                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data            1                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54798.932384                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53204.035874                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60931.034483                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 54798.932384                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 63638.888889                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63638.888889                       # average ReadExReq mshr miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63638.888889                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55573.863636                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53204.035874                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61791.176471                       # average overall mshr miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55573.863636                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55573.863636                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53204.035874                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61791.176471                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55573.863636                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.trans_dist::ReadReq            281                       # Transaction distribution
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini
index 5f42de628..19ac3530d 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini
@@ -155,6 +155,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
@@ -502,6 +503,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
@@ -551,6 +553,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=20
@@ -600,6 +603,7 @@ eventq_index=0
 type=LiveProcess
 cmd=hello
 cwd=
+drivers=
 egid=100
 env=
 errout=cerr
@@ -608,6 +612,7 @@ eventq_index=0
 executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/alpha/tru64/hello
 gid=100
 input=cin
+kvmInSE=false
 max_stack_size=67108864
 output=cout
 pid=100
@@ -681,6 +686,7 @@ clk_domain=system.clk_domain
 conf_table_reported=true
 device_bus_width=8
 device_rowbuffer_size=1024
+device_size=536870912
 devices_per_rank=8
 dll=true
 eventq_index=0
diff --git a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/config.ini b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/config.ini
index 300b9d035..c7a245793 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/config.ini
@@ -132,6 +132,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
@@ -591,6 +592,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
@@ -651,6 +653,7 @@ id_mmfr3=34611729
 id_pfr0=49
 id_pfr1=4113
 midr=1091551472
+pmu=Null
 system=system
 
 [system.cpu.istage2_mmu]
@@ -700,6 +703,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=20
@@ -749,6 +753,7 @@ eventq_index=0
 type=LiveProcess
 cmd=hello
 cwd=
+drivers=
 egid=100
 env=
 errout=cerr
@@ -757,6 +762,7 @@ eventq_index=0
 executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/arm/linux/hello
 gid=100
 input=cin
+kvmInSE=false
 max_stack_size=67108864
 output=cout
 pid=100
@@ -830,6 +836,7 @@ clk_domain=system.clk_domain
 conf_table_reported=true
 device_bus_width=8
 device_rowbuffer_size=1024
+device_size=536870912
 devices_per_rank=8
 dll=true
 eventq_index=0
diff --git a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt
index 58622e09f..452f74fef 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt
@@ -4,26 +4,30 @@ sim_seconds                                  0.000028                       # Nu
 sim_ticks                                    27981000                       # Number of ticks simulated
 final_tick                                   27981000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  95550                       # Simulator instruction rate (inst/s)
-host_op_rate                                   111835                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              580422337                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 309164                       # Number of bytes of host memory used
-host_seconds                                     0.05                       # Real time elapsed on the host
+host_inst_rate                                  40383                       # Simulator instruction rate (inst/s)
+host_op_rate                                    47269                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              245344554                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 297404                       # Number of bytes of host memory used
+host_seconds                                     0.11                       # Real time elapsed on the host
 sim_insts                                        4604                       # Number of instructions simulated
 sim_ops                                          5390                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst             26944                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst             19520                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data              7424                       # Number of bytes read from this memory
 system.physmem.bytes_read::total                26944                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read::cpu.inst        19520                       # Number of instructions bytes read from this memory
 system.physmem.bytes_inst_read::total           19520                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst                421                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst                305                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data                116                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                   421                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst            962939137                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst            697616240                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            265322898                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::total               962939137                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_inst_read::cpu.inst       697616240                       # Instruction read bandwidth from this memory (bytes/s)
 system.physmem.bw_inst_read::total          697616240                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst           962939137                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst           697616240                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           265322898                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::total              962939137                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.readReqs                           421                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
@@ -389,8 +393,8 @@ system.cpu.dcache.tags.total_refs                1922                       # To
 system.cpu.dcache.tags.sampled_refs               146                       # Sample count of references to valid blocks.
 system.cpu.dcache.tags.avg_refs             13.164384                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.inst    86.669090                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.inst     0.021159                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data    86.669090                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.021159                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.021159                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          146                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           39                       # Occupied blocks per task id
@@ -398,61 +402,61 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::1          107
 system.cpu.dcache.tags.occ_task_id_percent::1024     0.035645                       # Percentage of cache occupancy per task id
 system.cpu.dcache.tags.tag_accesses              4354                       # Number of tag accesses
 system.cpu.dcache.tags.data_accesses             4354                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.inst         1054                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::cpu.data         1054                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total            1054                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.inst          846                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data          846                       # number of WriteReq hits
 system.cpu.dcache.WriteReq_hits::total            846                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.inst           11                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data           11                       # number of LoadLockedReq hits
 system.cpu.dcache.LoadLockedReq_hits::total           11                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.inst           11                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data           11                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total           11                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.inst          1900                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::cpu.data          1900                       # number of demand (read+write) hits
 system.cpu.dcache.demand_hits::total             1900                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.inst         1900                       # number of overall hits
+system.cpu.dcache.overall_hits::cpu.data         1900                       # number of overall hits
 system.cpu.dcache.overall_hits::total            1900                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.inst          115                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::cpu.data          115                       # number of ReadReq misses
 system.cpu.dcache.ReadReq_misses::total           115                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.inst           67                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data           67                       # number of WriteReq misses
 system.cpu.dcache.WriteReq_misses::total           67                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.inst          182                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::cpu.data          182                       # number of demand (read+write) misses
 system.cpu.dcache.demand_misses::total            182                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.inst          182                       # number of overall misses
+system.cpu.dcache.overall_misses::cpu.data          182                       # number of overall misses
 system.cpu.dcache.overall_misses::total           182                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.inst      6708741                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data      6708741                       # number of ReadReq miss cycles
 system.cpu.dcache.ReadReq_miss_latency::total      6708741                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.inst      4576500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data      4576500                       # number of WriteReq miss cycles
 system.cpu.dcache.WriteReq_miss_latency::total      4576500                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.inst     11285241                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data     11285241                       # number of demand (read+write) miss cycles
 system.cpu.dcache.demand_miss_latency::total     11285241                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.inst     11285241                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data     11285241                       # number of overall miss cycles
 system.cpu.dcache.overall_miss_latency::total     11285241                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.inst         1169                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::cpu.data         1169                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total         1169                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.inst          913                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data          913                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total          913                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.inst           11                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data           11                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::total           11                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.inst           11                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data           11                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total           11                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.inst         2082                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.data         2082                       # number of demand (read+write) accesses
 system.cpu.dcache.demand_accesses::total         2082                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.inst         2082                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data         2082                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_accesses::total         2082                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.inst     0.098375                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.098375                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_miss_rate::total     0.098375                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.inst     0.073384                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.073384                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_miss_rate::total     0.073384                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.inst     0.087416                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.087416                       # miss rate for demand accesses
 system.cpu.dcache.demand_miss_rate::total     0.087416                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.inst     0.087416                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.087416                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.087416                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 58336.878261                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 58336.878261                       # average ReadReq miss latency
 system.cpu.dcache.ReadReq_avg_miss_latency::total 58336.878261                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 68305.970149                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 68305.970149                       # average WriteReq miss latency
 system.cpu.dcache.WriteReq_avg_miss_latency::total 68305.970149                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.inst 62006.818681                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 62006.818681                       # average overall miss latency
 system.cpu.dcache.demand_avg_miss_latency::total 62006.818681                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.inst 62006.818681                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 62006.818681                       # average overall miss latency
 system.cpu.dcache.overall_avg_miss_latency::total 62006.818681                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
@@ -462,45 +466,45 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.ReadReq_mshr_hits::cpu.inst           12                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data           12                       # number of ReadReq MSHR hits
 system.cpu.dcache.ReadReq_mshr_hits::total           12                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.inst           24                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data           24                       # number of WriteReq MSHR hits
 system.cpu.dcache.WriteReq_mshr_hits::total           24                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.inst           36                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data           36                       # number of demand (read+write) MSHR hits
 system.cpu.dcache.demand_mshr_hits::total           36                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.inst           36                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data           36                       # number of overall MSHR hits
 system.cpu.dcache.overall_mshr_hits::total           36                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.inst          103                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data          103                       # number of ReadReq MSHR misses
 system.cpu.dcache.ReadReq_mshr_misses::total          103                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.inst           43                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data           43                       # number of WriteReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::total           43                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.inst          146                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data          146                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.demand_mshr_misses::total          146                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.inst          146                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data          146                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total          146                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst      6015258                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      6015258                       # number of ReadReq MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_latency::total      6015258                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst      2857500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      2857500                       # number of WriteReq MSHR miss cycles
 system.cpu.dcache.WriteReq_mshr_miss_latency::total      2857500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.inst      8872758                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data      8872758                       # number of demand (read+write) MSHR miss cycles
 system.cpu.dcache.demand_mshr_miss_latency::total      8872758                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.inst      8872758                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data      8872758                       # number of overall MSHR miss cycles
 system.cpu.dcache.overall_mshr_miss_latency::total      8872758                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst     0.088109                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.088109                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.088109                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst     0.047097                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.047097                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.047097                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.inst     0.070125                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.070125                       # mshr miss rate for demand accesses
 system.cpu.dcache.demand_mshr_miss_rate::total     0.070125                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.inst     0.070125                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.070125                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.070125                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 58400.563107                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 58400.563107                       # average ReadReq mshr miss latency
 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 58400.563107                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 66453.488372                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 66453.488372                       # average WriteReq mshr miss latency
 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 66453.488372                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 60772.315068                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 60772.315068                       # average overall mshr miss latency
 system.cpu.dcache.demand_avg_mshr_miss_latency::total 60772.315068                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 60772.315068                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 60772.315068                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 60772.315068                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements                 3                       # number of replacements
@@ -593,8 +597,10 @@ system.cpu.l2cache.tags.total_refs                 39                       # To
 system.cpu.l2cache.tags.sampled_refs              378                       # Sample count of references to valid blocks.
 system.cpu.l2cache.tags.avg_refs             0.103175                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   195.981905                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.005981                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   154.764479                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data    41.217425                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.004723                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.001258                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::total     0.005981                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024          378                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::0          134                       # Occupied blocks per task id
@@ -602,51 +608,69 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::1          244
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.011536                       # Percentage of cache occupancy per task id
 system.cpu.l2cache.tags.tag_accesses             4165                       # Number of tag accesses
 system.cpu.l2cache.tags.data_accesses            4165                       # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.inst           39                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.inst           17                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data           22                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total             39                       # number of ReadReq hits
-system.cpu.l2cache.demand_hits::cpu.inst           39                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.inst           17                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data           22                       # number of demand (read+write) hits
 system.cpu.l2cache.demand_hits::total              39                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst           39                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.inst           17                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data           22                       # number of overall hits
 system.cpu.l2cache.overall_hits::total             39                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst          386                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.inst          305                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data           81                       # number of ReadReq misses
 system.cpu.l2cache.ReadReq_misses::total          386                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.inst           43                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data           43                       # number of ReadExReq misses
 system.cpu.l2cache.ReadExReq_misses::total           43                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst          429                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.inst          305                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data          124                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_misses::total           429                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst          429                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.inst          305                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data          124                       # number of overall misses
 system.cpu.l2cache.overall_misses::total          429                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     26149000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     20459750                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data      5689250                       # number of ReadReq miss cycles
 system.cpu.l2cache.ReadReq_miss_latency::total     26149000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst      2814500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      2814500                       # number of ReadExReq miss cycles
 system.cpu.l2cache.ReadExReq_miss_latency::total      2814500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     28963500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     20459750                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data      8503750                       # number of demand (read+write) miss cycles
 system.cpu.l2cache.demand_miss_latency::total     28963500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     28963500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     20459750                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data      8503750                       # number of overall miss cycles
 system.cpu.l2cache.overall_miss_latency::total     28963500                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst          425                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.inst          322                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data          103                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::total          425                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.inst           43                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data           43                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total           43                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst          468                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.inst          322                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data          146                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_accesses::total          468                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst          468                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst          322                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data          146                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::total          468                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.908235                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.947205                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.786408                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_miss_rate::total     0.908235                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst            1                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::total            1                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.916667                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.947205                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.849315                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::total     0.916667                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.916667                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.947205                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.849315                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.916667                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67743.523316                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67081.147541                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 70237.654321                       # average ReadReq miss latency
 system.cpu.l2cache.ReadReq_avg_miss_latency::total 67743.523316                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 65453.488372                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 65453.488372                       # average ReadExReq miss latency
 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65453.488372                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67513.986014                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67081.147541                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 68578.629032                       # average overall miss latency
 system.cpu.l2cache.demand_avg_miss_latency::total 67513.986014                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67513.986014                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67081.147541                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 68578.629032                       # average overall miss latency
 system.cpu.l2cache.overall_avg_miss_latency::total 67513.986014                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
@@ -656,43 +680,55 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            8                       # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.data            8                       # number of ReadReq MSHR hits
 system.cpu.l2cache.ReadReq_mshr_hits::total            8                       # number of ReadReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.inst            8                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data            8                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.demand_mshr_hits::total            8                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.inst            8                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.data            8                       # number of overall MSHR hits
 system.cpu.l2cache.overall_mshr_hits::total            8                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          378                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          305                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data           73                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadReq_mshr_misses::total          378                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst           43                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data           43                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total           43                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst          421                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst          305                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data          116                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::total          421                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst          421                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst          305                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data          116                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total          421                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     20940500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     16622750                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      4317750                       # number of ReadReq MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_latency::total     20940500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst      2273500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      2273500                       # number of ReadExReq MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      2273500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     23214000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     16622750                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      6591250                       # number of demand (read+write) MSHR miss cycles
 system.cpu.l2cache.demand_mshr_miss_latency::total     23214000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     23214000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     16622750                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      6591250                       # number of overall MSHR miss cycles
 system.cpu.l2cache.overall_mshr_miss_latency::total     23214000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.889412                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.947205                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.708738                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.889412                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.899573                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.947205                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.794521                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::total     0.899573                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.899573                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.947205                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.794521                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.899573                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55398.148148                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54500.819672                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59147.260274                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55398.148148                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 52872.093023                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 52872.093023                       # average ReadExReq mshr miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 52872.093023                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55140.142518                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54500.819672                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 56821.120690                       # average overall mshr miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55140.142518                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55140.142518                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54500.819672                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 56821.120690                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55140.142518                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.trans_dist::ReadReq            425                       # Transaction distribution
diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini
index 41775f550..64e1a1f99 100644
--- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini
@@ -161,6 +161,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
@@ -518,6 +519,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
@@ -584,6 +586,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=20
@@ -633,6 +636,7 @@ eventq_index=0
 type=LiveProcess
 cmd=hello
 cwd=
+drivers=
 egid=100
 env=
 errout=cerr
@@ -641,6 +645,7 @@ eventq_index=0
 executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/x86/linux/hello
 gid=100
 input=cin
+kvmInSE=false
 max_stack_size=67108864
 output=cout
 pid=100
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini
index 144007094..8f525a009 100644
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini
@@ -155,6 +155,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
@@ -502,6 +503,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=1
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
@@ -552,6 +554,7 @@ eventq_index=0
 type=LiveProcess
 cmd=test_atomic 4
 cwd=
+drivers=
 egid=100
 env=
 errout=cerr
@@ -560,6 +563,7 @@ eventq_index=0
 executable=/scratch/nilay/GEM5/gem5/tests/test-progs/m5threads/bin/sparc/linux/test_atomic
 gid=100
 input=cin
+kvmInSE=false
 max_stack_size=67108864
 output=cout
 pid=100
@@ -681,6 +685,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
@@ -1028,6 +1033,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=1
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
@@ -1186,6 +1192,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
@@ -1533,6 +1540,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=1
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
@@ -1691,6 +1699,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
@@ -2038,6 +2047,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=1
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=2
@@ -2106,6 +2116,7 @@ children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
 clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
 eventq_index=0
 forward_snoops=true
 hit_latency=20
@@ -2183,6 +2194,7 @@ clk_domain=system.clk_domain
 conf_table_reported=true
 device_bus_width=8
 device_rowbuffer_size=1024
+device_size=536870912
 devices_per_rank=8
 dll=true
 eventq_index=0