diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2011-07-10 12:56:09 -0500 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2011-07-10 12:56:09 -0500 |
| commit | 3ebfe2eb0124b0524952c59f04580a55eb36edff (patch) | |
| tree | 3d48c5d7bddaa51413b4504b7bc17635e67e14a7 /tests/quick | |
| parent | 3396fd9e84358346b60437a7635c9cc5f331017f (diff) | |
| download | gem5-3ebfe2eb0124b0524952c59f04580a55eb36edff.tar.xz | |
O3: Update stats for fetch and bp changes.
Diffstat (limited to 'tests/quick')
42 files changed, 5225 insertions, 5215 deletions
diff --git a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/config.ini b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/config.ini index 258f4e533..56fbbd75c 100644 --- a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/config.ini @@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem mem_mode=atomic +memories=system.physmem physmem=system.physmem work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -204,7 +205,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/hello/bin/alpha/linux/hello +executable=/chips/pd/randd/dist/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/simout b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/simout index cdb09d17e..d51796d4d 100755 --- a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/simout +++ b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 19 2011 23:40:02 -gem5 started Jun 20 2011 08:26:33 -gem5 executing on zooks +gem5 compiled Jul 8 2011 15:00:53 +gem5 started Jul 8 2011 15:20:58 +gem5 executing on u200439-lin.austin.arm.com command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/inorder-timing -re tests/run.py build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 21228000 because target called exit() +Exiting @ tick 21216000 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt index 3184d80aa..118e4e630 100644 --- a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt @@ -1,12 +1,12 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000021 # Number of seconds simulated -sim_ticks 21228000 # Number of ticks simulated +sim_ticks 21216000 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 45998 # Simulator instruction rate (inst/s) -host_tick_rate 152436103 # Simulator tick rate (ticks/s) -host_mem_usage 157012 # Number of bytes of host memory used -host_seconds 0.14 # Real time elapsed on the host +host_inst_rate 29106 # Simulator instruction rate (inst/s) +host_tick_rate 96412699 # Simulator tick rate (ticks/s) +host_mem_usage 242900 # Number of bytes of host memory used +host_seconds 0.22 # Real time elapsed on the host sim_insts 6404 # Number of instructions simulated system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -24,10 +24,10 @@ system.cpu.dtb.data_hits 2084 # DT system.cpu.dtb.data_misses 10 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations system.cpu.dtb.data_accesses 2094 # DTB accesses -system.cpu.itb.fetch_hits 932 # ITB hits +system.cpu.itb.fetch_hits 929 # ITB hits system.cpu.itb.fetch_misses 17 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 949 # ITB accesses +system.cpu.itb.fetch_accesses 946 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -41,16 +41,16 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 42457 # number of cpu cycles simulated +system.cpu.numCycles 42433 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 11420 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 11397 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode system.cpu.timesIdled 442 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 35048 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 7409 # Number of cycles cpu stages are processed. -system.cpu.activity 17.450597 # Percentage of cycles cpu is active +system.cpu.idleCycles 35050 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 7383 # Number of cycles cpu stages are processed. +system.cpu.activity 17.399194 # Percentage of cycles cpu is active system.cpu.comLoads 1185 # Number of Load instructions committed system.cpu.comStores 865 # Number of Store instructions committed system.cpu.comBranches 1051 # Number of Branches instructions committed @@ -61,79 +61,79 @@ system.cpu.comFloats 2 # Nu system.cpu.committedInsts 6404 # Number of Instructions Simulated (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread) system.cpu.committedInsts_total 6404 # Number of Instructions Simulated (Total) -system.cpu.cpi 6.629763 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 6.626015 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi no_value # CPI: Total SMT-CPI -system.cpu.cpi_total 6.629763 # CPI: Total CPI of All Threads -system.cpu.ipc 0.150835 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 6.626015 # CPI: Total CPI of All Threads +system.cpu.ipc 0.150920 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc no_value # IPC: Total SMT-IPC -system.cpu.ipc_total 0.150835 # IPC: Total IPC of All Threads -system.cpu.branch_predictor.lookups 1674 # Number of BP lookups -system.cpu.branch_predictor.condPredicted 1207 # Number of conditional branches predicted -system.cpu.branch_predictor.condIncorrect 720 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 1422 # Number of BTB lookups -system.cpu.branch_predictor.BTBHits 419 # Number of BTB hits +system.cpu.ipc_total 0.150920 # IPC: Total IPC of All Threads +system.cpu.branch_predictor.lookups 1670 # Number of BP lookups +system.cpu.branch_predictor.condPredicted 1199 # Number of conditional branches predicted +system.cpu.branch_predictor.condIncorrect 712 # Number of conditional branches incorrect +system.cpu.branch_predictor.BTBLookups 1410 # Number of BTB lookups +system.cpu.branch_predictor.BTBHits 414 # Number of BTB hits system.cpu.branch_predictor.usedRAS 126 # Number of times the RAS was used to get a target. system.cpu.branch_predictor.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 29.465541 # BTB Hit Percentage -system.cpu.branch_predictor.predictedTaken 570 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 1104 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 5167 # Number of Reads from Int. Register File +system.cpu.branch_predictor.BTBHitPct 29.361702 # BTB Hit Percentage +system.cpu.branch_predictor.predictedTaken 565 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 1105 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 5165 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 4580 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 9747 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.intRegFileAccesses 9745 # Total Accesses (Read+Write) to the Int. Register File system.cpu.regfile_manager.floatRegFileReads 8 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 2 # Number of Writes to FP Register File system.cpu.regfile_manager.floatRegFileAccesses 10 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 3004 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 2137 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 369 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 290 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 659 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 393 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 62.642586 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 4444 # Number of Instructions Executed. +system.cpu.regfile_manager.regForwards 3002 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 2138 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 357 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 294 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 651 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 401 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 61.882129 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 4447 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 1 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed -system.cpu.stage0.idleCycles 37460 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 4997 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 11.769555 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 38535 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 3922 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 9.237582 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 38269 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 4188 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 9.864098 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 41117 # Number of cycles 0 instructions are processed. +system.cpu.stage0.idleCycles 37465 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 4968 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 11.707869 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 38516 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 3917 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 9.231023 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 38252 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 4181 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 9.853180 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 41093 # Number of cycles 0 instructions are processed. system.cpu.stage3.runCycles 1340 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 3.156134 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 37979 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 4478 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 10.547142 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.utilization 3.157920 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 37964 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 4469 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 10.531897 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 138.808044 # Cycle average of tags in use -system.cpu.icache.total_refs 584 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 138.882502 # Cycle average of tags in use +system.cpu.icache.total_refs 581 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 301 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 1.940199 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 1.930233 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 138.808044 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.067777 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 584 # number of ReadReq hits -system.cpu.icache.demand_hits 584 # number of demand (read+write) hits -system.cpu.icache.overall_hits 584 # number of overall hits +system.cpu.icache.occ_blocks::0 138.882502 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.067814 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 581 # number of ReadReq hits +system.cpu.icache.demand_hits 581 # number of demand (read+write) hits +system.cpu.icache.overall_hits 581 # number of overall hits system.cpu.icache.ReadReq_misses 348 # number of ReadReq misses system.cpu.icache.demand_misses 348 # number of demand (read+write) misses system.cpu.icache.overall_misses 348 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 19242000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 19242000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 19242000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 932 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 932 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 932 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.373391 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.373391 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.373391 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 55293.103448 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 55293.103448 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 55293.103448 # average overall miss latency +system.cpu.icache.ReadReq_miss_latency 19241000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 19241000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 19241000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 929 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 929 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 929 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.374596 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.374596 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.374596 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 55290.229885 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 55290.229885 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 55290.229885 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -150,28 +150,28 @@ system.cpu.icache.ReadReq_mshr_misses 302 # nu system.cpu.icache.demand_mshr_misses 302 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses 302 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 16050000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 16050000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 16050000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 16049000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 16049000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 16049000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.324034 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.324034 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.324034 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 53145.695364 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 53145.695364 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 53145.695364 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate 0.325081 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.325081 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.325081 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 53142.384106 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 53142.384106 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 53142.384106 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 102.626911 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 102.671807 # Cycle average of tags in use system.cpu.dcache.total_refs 1703 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 168 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 10.136905 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 102.626911 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.025055 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 102.671807 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.025066 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits 1088 # number of ReadReq hits system.cpu.dcache.WriteReq_hits 615 # number of WriteReq hits system.cpu.dcache.demand_hits 1703 # number of demand (read+write) hits @@ -181,9 +181,9 @@ system.cpu.dcache.WriteReq_misses 250 # nu system.cpu.dcache.demand_misses 347 # number of demand (read+write) misses system.cpu.dcache.overall_misses 347 # number of overall misses system.cpu.dcache.ReadReq_miss_latency 5508500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 13555000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 19063500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 19063500 # number of overall miss cycles +system.cpu.dcache.WriteReq_miss_latency 13555500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 19064000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 19064000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses 1185 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 865 # number of WriteReq accesses(hits+misses) system.cpu.dcache.demand_accesses 2050 # number of demand (read+write) accesses @@ -193,9 +193,9 @@ system.cpu.dcache.WriteReq_miss_rate 0.289017 # mi system.cpu.dcache.demand_miss_rate 0.169268 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate 0.169268 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency 56788.659794 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 54220 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 54938.040346 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 54938.040346 # average overall miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 54222 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency 54939.481268 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 54939.481268 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 1656000 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -215,30 +215,30 @@ system.cpu.dcache.demand_mshr_misses 168 # nu system.cpu.dcache.overall_mshr_misses 168 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.ReadReq_mshr_miss_latency 5114000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 3909500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 9023500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 9023500 # number of overall MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 3910000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 9024000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 9024000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.080169 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate 0.084393 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate 0.081951 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate 0.081951 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53831.578947 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53554.794521 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 53711.309524 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 53711.309524 # average overall mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53561.643836 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 53714.285714 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 53714.285714 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 195.111607 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 195.209568 # Cycle average of tags in use system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 395 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.002532 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 195.111607 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.005954 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 195.209568 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.005957 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits 1 # number of ReadReq hits system.cpu.l2cache.demand_hits 1 # number of demand (read+write) hits system.cpu.l2cache.overall_hits 1 # number of overall hits @@ -246,8 +246,8 @@ system.cpu.l2cache.ReadReq_misses 396 # nu system.cpu.l2cache.ReadExReq_misses 73 # number of ReadExReq misses system.cpu.l2cache.demand_misses 469 # number of demand (read+write) misses system.cpu.l2cache.overall_misses 469 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 20702500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 3821500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 20702000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 3822000 # number of ReadExReq miss cycles system.cpu.l2cache.demand_miss_latency 24524000 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency 24524000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses 397 # number of ReadReq accesses(hits+misses) @@ -258,8 +258,8 @@ system.cpu.l2cache.ReadReq_miss_rate 0.997481 # mi system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate 0.997872 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate 0.997872 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 52279.040404 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 52349.315068 # average ReadExReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 52277.777778 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 52356.164384 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency 52289.978678 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency 52289.978678 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked @@ -278,19 +278,19 @@ system.cpu.l2cache.ReadExReq_mshr_misses 73 # nu system.cpu.l2cache.demand_mshr_misses 469 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses 469 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 15876500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 15877000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency 2942500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 18819000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 18819000 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 18819500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 18819500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.997481 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate 0.997872 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate 0.997872 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40092.171717 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40093.434343 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40308.219178 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40125.799574 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40125.799574 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40126.865672 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40126.865672 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini index 08baf7c22..03a16a5ea 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini @@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem mem_mode=atomic +memories=system.physmem physmem=system.physmem work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -498,7 +499,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello +executable=/chips/pd/randd/dist/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout b/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout index 6caee1c6f..f022a446d 100755 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 19 2011 06:59:13 -gem5 started Jun 19 2011 07:04:58 -gem5 executing on m60-009.pool -command line: build/ALPHA_SE/gem5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing +gem5 compiled Jul 8 2011 15:00:53 +gem5 started Jul 8 2011 15:20:58 +gem5 executing on u200439-lin.austin.arm.com +command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 12357500 because target called exit() +Exiting @ tick 12002500 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt index 42ab89f68..50d6ec22a 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt @@ -1,33 +1,33 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000012 # Number of seconds simulated -sim_ticks 12357500 # Number of ticks simulated +sim_ticks 12002500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 108363 # Simulator instruction rate (inst/s) -host_tick_rate 209619317 # Simulator tick rate (ticks/s) -host_mem_usage 192840 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host +host_inst_rate 25819 # Simulator instruction rate (inst/s) +host_tick_rate 48521023 # Simulator tick rate (ticks/s) +host_mem_usage 243716 # Number of bytes of host memory used +host_seconds 0.25 # Real time elapsed on the host sim_insts 6386 # Number of instructions simulated system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 1750 # DTB read hits -system.cpu.dtb.read_misses 36 # DTB read misses +system.cpu.dtb.read_hits 1863 # DTB read hits +system.cpu.dtb.read_misses 45 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 1786 # DTB read accesses -system.cpu.dtb.write_hits 1011 # DTB write hits -system.cpu.dtb.write_misses 25 # DTB write misses +system.cpu.dtb.read_accesses 1908 # DTB read accesses +system.cpu.dtb.write_hits 1047 # DTB write hits +system.cpu.dtb.write_misses 28 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 1036 # DTB write accesses -system.cpu.dtb.data_hits 2761 # DTB hits -system.cpu.dtb.data_misses 61 # DTB misses +system.cpu.dtb.write_accesses 1075 # DTB write accesses +system.cpu.dtb.data_hits 2910 # DTB hits +system.cpu.dtb.data_misses 73 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 2822 # DTB accesses -system.cpu.itb.fetch_hits 1711 # ITB hits -system.cpu.itb.fetch_misses 33 # ITB misses +system.cpu.dtb.data_accesses 2983 # DTB accesses +system.cpu.itb.fetch_hits 2044 # ITB hits +system.cpu.itb.fetch_misses 29 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 1744 # ITB accesses +system.cpu.itb.fetch_accesses 2073 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -41,243 +41,245 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 24716 # number of cpu cycles simulated +system.cpu.numCycles 24006 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 2180 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 1297 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 443 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 1765 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 670 # Number of BTB hits +system.cpu.BPredUnit.lookups 2516 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 1462 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 458 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 1947 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 723 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 306 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 65 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 1711 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 12863 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2180 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 976 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 2325 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 482 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 33 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.CacheLines 1711 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 248 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 12915 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.995974 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.389736 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 372 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 67 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 7155 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 14481 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2516 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 1095 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 2626 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1554 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 1112 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 24 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 631 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 2044 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 318 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 12602 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.149103 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.531397 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 10590 82.00% 82.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 233 1.80% 83.80% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 211 1.63% 85.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 179 1.39% 86.82% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 229 1.77% 88.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 156 1.21% 89.80% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 218 1.69% 91.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 125 0.97% 92.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 974 7.54% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 9976 79.16% 79.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 274 2.17% 81.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 231 1.83% 83.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 220 1.75% 84.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 235 1.86% 86.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 176 1.40% 88.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 257 2.04% 90.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 141 1.12% 91.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1092 8.67% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 12915 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.088202 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.520432 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8780 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 1035 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2228 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 47 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 825 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 181 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 75 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 12021 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 209 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 825 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 8928 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 337 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 406 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2118 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 301 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 11616 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 8 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 260 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 8669 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 14615 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 14598 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 12602 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.104807 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.603224 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 7976 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 1126 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2455 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 69 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 976 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 216 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 85 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 13403 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 215 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 976 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 8164 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 432 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 358 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2326 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 346 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 12866 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 11 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 291 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 9599 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 16086 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 16069 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 17 # Number of floating rename lookups system.cpu.rename.CommittedMaps 4583 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 4086 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 5016 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 28 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 22 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 754 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2144 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1195 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 0 # Number of conflicting loads. +system.cpu.rename.skidInsts 881 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2397 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1265 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 4 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 10562 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 25 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 9108 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 25 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 3797 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 2286 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 8 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 12915 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.705226 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.305176 # Number of insts issued each cycle +system.cpu.iq.iqInstsAdded 11578 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 27 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 9768 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 45 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 4900 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 2850 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 10 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 12602 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.775115 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.397410 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 8840 68.45% 68.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1652 12.79% 81.24% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 1039 8.04% 89.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 684 5.30% 94.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 367 2.84% 97.42% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 198 1.53% 98.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 88 0.68% 99.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 36 0.28% 99.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 11 0.09% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 8516 67.58% 67.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1470 11.66% 79.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 1066 8.46% 87.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 684 5.43% 93.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 441 3.50% 96.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 254 2.02% 98.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 129 1.02% 99.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 30 0.24% 99.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 12 0.10% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 12915 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 12602 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 1 1.14% 1.14% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.14% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 52 59.09% 60.23% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 35 39.77% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 13 12.38% 12.38% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 12.38% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 12.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 12.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 12.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 12.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 12.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 12.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 12.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 12.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 12.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 12.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 12.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 12.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 12.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 12.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 12.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 12.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 12.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 12.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 12.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 12.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 12.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 12.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 12.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 12.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 12.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 12.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 12.38% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 54 51.43% 63.81% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 38 36.19% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 6174 67.79% 67.81% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.82% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.84% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1875 20.59% 88.43% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1054 11.57% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 6583 67.39% 67.41% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.42% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.42% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.44% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2078 21.27% 88.72% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1102 11.28% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 9108 # Type of FU issued -system.cpu.iq.rate 0.368506 # Inst issue rate -system.cpu.iq.fu_busy_cnt 88 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.009662 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 31223 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 14386 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 8549 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 9768 # Type of FU issued +system.cpu.iq.rate 0.406898 # Inst issue rate +system.cpu.iq.fu_busy_cnt 105 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.010749 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 32267 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 16511 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 8987 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 21 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 10 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 9183 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 9860 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 11 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 44 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 61 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 959 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 6 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 16 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 330 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1212 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 21 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 400 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 825 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 67 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 9 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 10669 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 193 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2144 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1195 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 25 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 7 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 976 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 150 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 8 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 11685 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 148 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2397 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1265 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 27 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 5 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 16 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 125 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 304 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 429 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 8837 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1794 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 271 # Number of squashed instructions skipped in execute +system.cpu.iew.memOrderViolationEvents 21 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 118 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 327 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 445 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 9324 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1918 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 444 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 82 # number of nop insts executed -system.cpu.iew.exec_refs 2832 # number of memory reference insts executed -system.cpu.iew.exec_branches 1424 # Number of branches executed -system.cpu.iew.exec_stores 1038 # Number of stores executed -system.cpu.iew.exec_rate 0.357542 # Inst execution rate -system.cpu.iew.wb_sent 8658 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 8559 # cumulative count of insts written-back -system.cpu.iew.wb_producers 4429 # num instructions producing a value -system.cpu.iew.wb_consumers 5952 # num instructions consuming a value +system.cpu.iew.exec_nop 80 # number of nop insts executed +system.cpu.iew.exec_refs 2995 # number of memory reference insts executed +system.cpu.iew.exec_branches 1503 # Number of branches executed +system.cpu.iew.exec_stores 1077 # Number of stores executed +system.cpu.iew.exec_rate 0.388403 # Inst execution rate +system.cpu.iew.wb_sent 9127 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 8997 # cumulative count of insts written-back +system.cpu.iew.wb_producers 4717 # num instructions producing a value +system.cpu.iew.wb_consumers 6401 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.346294 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.744120 # average fanout of values written-back +system.cpu.iew.wb_rate 0.374781 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.736916 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 6403 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 4249 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 5279 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 369 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 12090 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.529611 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.331978 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 380 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 11626 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.550748 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.411308 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 9222 76.28% 76.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1613 13.34% 89.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 453 3.75% 93.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 264 2.18% 95.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 157 1.30% 96.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 121 1.00% 97.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 88 0.73% 98.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 45 0.37% 98.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 127 1.05% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 8945 76.94% 76.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1414 12.16% 89.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 463 3.98% 93.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 244 2.10% 95.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 156 1.34% 96.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 87 0.75% 97.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 110 0.95% 98.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 44 0.38% 98.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 163 1.40% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 12090 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 11626 # Number of insts commited each cycle system.cpu.commit.count 6403 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 2050 # Number of memory references committed @@ -287,50 +289,50 @@ system.cpu.commit.branches 1051 # Nu system.cpu.commit.fp_insts 10 # Number of committed floating point instructions. system.cpu.commit.int_insts 6321 # Number of committed integer instructions. system.cpu.commit.function_calls 127 # Number of function calls committed. -system.cpu.commit.bw_lim_events 127 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 163 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 22264 # The number of ROB reads -system.cpu.rob.rob_writes 22135 # The number of ROB writes -system.cpu.timesIdled 240 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 11801 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 22794 # The number of ROB reads +system.cpu.rob.rob_writes 24351 # The number of ROB writes +system.cpu.timesIdled 230 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 11404 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 6386 # Number of Instructions Simulated system.cpu.committedInsts_total 6386 # Number of Instructions Simulated -system.cpu.cpi 3.870341 # CPI: Cycles Per Instruction -system.cpu.cpi_total 3.870341 # CPI: Total CPI of All Threads -system.cpu.ipc 0.258375 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.258375 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 11291 # number of integer regfile reads -system.cpu.int_regfile_writes 6385 # number of integer regfile writes +system.cpu.cpi 3.759161 # CPI: Cycles Per Instruction +system.cpu.cpi_total 3.759161 # CPI: Total CPI of All Threads +system.cpu.ipc 0.266017 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.266017 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 11850 # number of integer regfile reads +system.cpu.int_regfile_writes 6735 # number of integer regfile writes system.cpu.fp_regfile_reads 8 # number of floating regfile reads system.cpu.fp_regfile_writes 2 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 157.666490 # Cycle average of tags in use -system.cpu.icache.total_refs 1301 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 307 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 4.237785 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 159.654959 # Cycle average of tags in use +system.cpu.icache.total_refs 1612 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 311 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 5.183280 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 157.666490 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.076986 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 1301 # number of ReadReq hits -system.cpu.icache.demand_hits 1301 # number of demand (read+write) hits -system.cpu.icache.overall_hits 1301 # number of overall hits -system.cpu.icache.ReadReq_misses 410 # number of ReadReq misses -system.cpu.icache.demand_misses 410 # number of demand (read+write) misses -system.cpu.icache.overall_misses 410 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 14727000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 14727000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 14727000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 1711 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 1711 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 1711 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.239626 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.239626 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.239626 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 35919.512195 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 35919.512195 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 35919.512195 # average overall miss latency +system.cpu.icache.occ_blocks::0 159.654959 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.077957 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 1612 # number of ReadReq hits +system.cpu.icache.demand_hits 1612 # number of demand (read+write) hits +system.cpu.icache.overall_hits 1612 # number of overall hits +system.cpu.icache.ReadReq_misses 432 # number of ReadReq misses +system.cpu.icache.demand_misses 432 # number of demand (read+write) misses +system.cpu.icache.overall_misses 432 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 15402000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 15402000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 15402000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 2044 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 2044 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 2044 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.211350 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.211350 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.211350 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 35652.777778 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 35652.777778 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 35652.777778 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -340,59 +342,59 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 103 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 103 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 103 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 307 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 307 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 307 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_hits 121 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 121 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 121 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 311 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 311 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 311 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 10832000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 10832000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 10832000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 10985500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 10985500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 10985500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.179427 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.179427 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.179427 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 35283.387622 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 35283.387622 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 35283.387622 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate 0.152153 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.152153 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.152153 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 35323.151125 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 35323.151125 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 35323.151125 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 109.940770 # Cycle average of tags in use -system.cpu.dcache.total_refs 2064 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 109.289403 # Cycle average of tags in use +system.cpu.dcache.total_refs 2155 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 174 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 11.862069 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 12.385057 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 109.940770 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.026841 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 1555 # number of ReadReq hits +system.cpu.dcache.occ_blocks::0 109.289403 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.026682 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 1646 # number of ReadReq hits system.cpu.dcache.WriteReq_hits 509 # number of WriteReq hits -system.cpu.dcache.demand_hits 2064 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 2064 # number of overall hits -system.cpu.dcache.ReadReq_misses 150 # number of ReadReq misses +system.cpu.dcache.demand_hits 2155 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 2155 # number of overall hits +system.cpu.dcache.ReadReq_misses 155 # number of ReadReq misses system.cpu.dcache.WriteReq_misses 356 # number of WriteReq misses -system.cpu.dcache.demand_misses 506 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 506 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 5422000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 12468000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 17890000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 17890000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 1705 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses 511 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 511 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 5502500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 12467500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 17970000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 17970000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 1801 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 865 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 2570 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 2570 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.087977 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses 2666 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 2666 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.086063 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate 0.411561 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.196887 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.196887 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 36146.666667 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 35022.471910 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 35355.731225 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 35355.731225 # average overall miss latency +system.cpu.dcache.demand_miss_rate 0.191673 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.191673 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 35500 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 35021.067416 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency 35166.340509 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 35166.340509 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -402,63 +404,63 @@ system.cpu.dcache.avg_blocked_cycles::no_targets no_value system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 49 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits 54 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits 283 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 332 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 332 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits 337 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 337 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses 101 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses 73 # number of WriteReq MSHR misses system.cpu.dcache.demand_mshr_misses 174 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses 174 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 3659000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 2619500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 6278500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 6278500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 3654000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 2611500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 6265500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 6265500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.059238 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate 0.056080 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate 0.084393 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.067704 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.067704 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 36227.722772 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35883.561644 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 36083.333333 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 36083.333333 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate 0.065266 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.065266 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 36178.217822 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35773.972603 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 36008.620690 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 36008.620690 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 219.485914 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 221.186144 # Cycle average of tags in use system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 407 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.002457 # Average number of references to valid blocks. +system.cpu.l2cache.sampled_refs 411 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.002433 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 219.485914 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.006698 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 221.186144 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.006750 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits 1 # number of ReadReq hits system.cpu.l2cache.demand_hits 1 # number of demand (read+write) hits system.cpu.l2cache.overall_hits 1 # number of overall hits -system.cpu.l2cache.ReadReq_misses 407 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses 411 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses 73 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 480 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 480 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 14004500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 2518000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 16522500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 16522500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 408 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.demand_misses 484 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 484 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 14128000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 2513500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 16641500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 16641500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 412 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses 73 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 481 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 481 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.997549 # miss rate for ReadReq accesses +system.cpu.l2cache.demand_accesses 485 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 485 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.997573 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.997921 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.997921 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34409.090909 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34493.150685 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34421.875000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34421.875000 # average overall miss latency +system.cpu.l2cache.demand_miss_rate 0.997938 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.997938 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34374.695864 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34431.506849 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34383.264463 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34383.264463 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -470,24 +472,24 @@ system.cpu.l2cache.cache_copies 0 # nu system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 407 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses 411 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses 73 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 480 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 480 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses 484 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 484 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 12710000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 2291000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 15001000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 15001000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 12819000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 2286000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 15105000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 15105000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.997549 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.997573 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.997921 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.997921 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31228.501229 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31383.561644 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31252.083333 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31252.083333 # average overall mshr miss latency +system.cpu.l2cache.demand_mshr_miss_rate 0.997938 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.997938 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31189.781022 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31315.068493 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31208.677686 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31208.677686 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini index 838834423..1c3640f5b 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini @@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem mem_mode=atomic +memories=system.physmem physmem=system.physmem work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -498,7 +499,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello +executable=/chips/pd/randd/dist/test-progs/hello/bin/alpha/tru64/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simerr b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simerr index 0659d557a..27f858d8f 100755 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simerr +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simerr @@ -1,7 +1,4 @@ warn: Sockets disabled, not accepting gdb connections -For more information see: http://www.m5sim.org/warn/d946bea6 -warn: Prefetch instrutions is Alpha do not do anything -For more information see: http://www.m5sim.org/warn/3e0eccba +warn: Prefetch instructions in Alpha do not do anything warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) -For more information see: http://www.m5sim.org/warn/5c5b547f hack: be nice to actually delete the event here diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout index 8a87312b4..74424d63b 100755 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout @@ -1,16 +1,12 @@ -M5 Simulator System +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Apr 21 2011 12:29:56 -M5 started Apr 21 2011 13:15:23 -M5 executing on maize -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing +gem5 compiled Jul 8 2011 15:00:53 +gem5 started Jul 8 2011 15:21:09 +gem5 executing on u200439-lin.austin.arm.com +command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 7289000 because target called exit() +Exiting @ tick 6921000 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt index b8b5c99cd..5e52ef944 100644 --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt @@ -1,494 +1,496 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 66320 # Simulator instruction rate (inst/s) -host_mem_usage 205872 # Number of bytes of host memory used -host_seconds 0.04 # Real time elapsed on the host -host_tick_rate 201598879 # Simulator tick rate (ticks/s) +sim_seconds 0.000007 # Number of seconds simulated +sim_ticks 6921000 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 33894 # Simulator instruction rate (inst/s) +host_tick_rate 98227338 # Simulator tick rate (ticks/s) +host_mem_usage 242788 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host sim_insts 2387 # Number of instructions simulated -sim_seconds 0.000007 # Number of seconds simulated -sim_ticks 7289000 # Number of ticks simulated +system.cpu.dtb.fetch_hits 0 # ITB hits +system.cpu.dtb.fetch_misses 0 # ITB misses +system.cpu.dtb.fetch_acv 0 # ITB acv +system.cpu.dtb.fetch_accesses 0 # ITB accesses +system.cpu.dtb.read_hits 720 # DTB read hits +system.cpu.dtb.read_misses 34 # DTB read misses +system.cpu.dtb.read_acv 1 # DTB read access violations +system.cpu.dtb.read_accesses 754 # DTB read accesses +system.cpu.dtb.write_hits 354 # DTB write hits +system.cpu.dtb.write_misses 22 # DTB write misses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_accesses 376 # DTB write accesses +system.cpu.dtb.data_hits 1074 # DTB hits +system.cpu.dtb.data_misses 56 # DTB misses +system.cpu.dtb.data_acv 1 # DTB access violations +system.cpu.dtb.data_accesses 1130 # DTB accesses +system.cpu.itb.fetch_hits 976 # ITB hits +system.cpu.itb.fetch_misses 30 # ITB misses +system.cpu.itb.fetch_acv 0 # ITB acv +system.cpu.itb.fetch_accesses 1006 # ITB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_acv 0 # DTB read access violations +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_acv 0 # DTB write access violations +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.data_hits 0 # DTB hits +system.cpu.itb.data_misses 0 # DTB misses +system.cpu.itb.data_acv 0 # DTB access violations +system.cpu.itb.data_accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 4 # Number of system calls +system.cpu.numCycles 13843 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.BPredUnit.lookups 1112 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 583 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 236 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 781 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 240 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 197 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 687 # Number of BTB lookups -system.cpu.BPredUnit.RASInCorrect 35 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 223 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 485 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 931 # Number of BP lookups -system.cpu.BPredUnit.usedRAS 174 # Number of times the RAS was used to get a target. -system.cpu.commit.branchMispredicts 146 # The number of times a branch was mispredicted -system.cpu.commit.branches 396 # Number of branches committed -system.cpu.commit.bw_lim_events 41 # number cycles where commit BW limit reached -system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits +system.cpu.BPredUnit.usedRAS 215 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 34 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 3787 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 6697 # Number of instructions fetch has processed +system.cpu.fetch.Branches 1112 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 455 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 1166 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 814 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 253 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 17 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 781 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 976 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 159 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 6557 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.021351 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.437035 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 5391 82.22% 82.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 67 1.02% 83.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 123 1.88% 85.12% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 97 1.48% 86.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 146 2.23% 88.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 50 0.76% 89.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 61 0.93% 90.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 83 1.27% 91.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 539 8.22% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 6557 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.080329 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.483782 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 4673 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 269 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 1132 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 7 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 476 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 152 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 80 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 6020 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 284 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 476 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 4772 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 89 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 147 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 1039 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 34 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 5743 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 15 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 11 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 4153 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 6495 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 6483 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 12 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 1768 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 2385 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 8 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 6 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 117 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 961 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 458 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 5 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 3 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 4907 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 6 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 3996 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 90 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 2355 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1385 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 6557 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.609425 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.316967 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 4952 75.52% 75.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 578 8.82% 84.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 360 5.49% 89.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 270 4.12% 93.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 209 3.19% 97.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 109 1.66% 98.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 54 0.82% 99.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 17 0.26% 99.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 8 0.12% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 6557 # Number of insts issued each cycle +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 1 2.27% 2.27% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 2.27% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 2.27% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.27% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.27% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.27% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 2.27% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.27% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 2.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 2.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.27% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 20 45.45% 47.73% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 23 52.27% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 2819 70.55% 70.55% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.03% 70.57% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.57% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.57% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.57% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.57% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.57% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.57% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 70.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 70.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 70.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 70.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.57% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 794 19.87% 90.44% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 382 9.56% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 3996 # Type of FU issued +system.cpu.iq.rate 0.288666 # Inst issue rate +system.cpu.iq.fu_busy_cnt 44 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.011011 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 14670 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 7267 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 3636 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 13 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 6 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 6 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 4033 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 7 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 32 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.squashedLoads 546 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 6 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 164 # Number of stores squashed +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewSquashCycles 476 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 79 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 7 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 5242 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 68 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 961 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 458 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 6 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 4 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 6 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 52 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 137 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 189 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 3843 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 755 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 153 # Number of squashed instructions skipped in execute +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.exec_nop 329 # number of nop insts executed +system.cpu.iew.exec_refs 1131 # number of memory reference insts executed +system.cpu.iew.exec_branches 644 # Number of branches executed +system.cpu.iew.exec_stores 376 # Number of stores executed +system.cpu.iew.exec_rate 0.277613 # Inst execution rate +system.cpu.iew.wb_sent 3725 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 3642 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1733 # num instructions producing a value +system.cpu.iew.wb_consumers 2231 # num instructions consuming a value +system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.wb_rate 0.263093 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.776782 # average fanout of values written-back +system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 2576 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 2657 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 1995 # The number of squashed insts skipped by commit -system.cpu.commit.committed_per_cycle::samples 6308 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.408370 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.199072 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 159 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 6081 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.423615 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.271187 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 5350 84.81% 84.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 259 4.11% 88.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 343 5.44% 94.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 133 2.11% 96.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 72 1.14% 97.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 64 1.01% 98.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 26 0.41% 99.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 20 0.32% 99.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 41 0.65% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 5177 85.13% 85.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 230 3.78% 88.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 323 5.31% 94.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 118 1.94% 96.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 67 1.10% 97.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 52 0.86% 98.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 37 0.61% 98.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 20 0.33% 99.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 57 0.94% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 6308 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 6081 # Number of insts commited each cycle system.cpu.commit.count 2576 # Number of instructions committed -system.cpu.commit.fp_insts 6 # Number of committed floating point instructions. -system.cpu.commit.function_calls 71 # Number of function calls committed. -system.cpu.commit.int_insts 2367 # Number of committed integer instructions. +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.refs 709 # Number of memory references committed system.cpu.commit.loads 415 # Number of loads committed system.cpu.commit.membars 0 # Number of memory barriers committed -system.cpu.commit.refs 709 # Number of memory references committed -system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.branches 396 # Number of branches committed +system.cpu.commit.fp_insts 6 # Number of committed floating point instructions. +system.cpu.commit.int_insts 2367 # Number of committed integer instructions. +system.cpu.commit.function_calls 71 # Number of function calls committed. +system.cpu.commit.bw_lim_events 57 # number cycles where commit BW limit reached +system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits +system.cpu.rob.rob_reads 11010 # The number of ROB reads +system.cpu.rob.rob_writes 10947 # The number of ROB writes +system.cpu.timesIdled 139 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 7286 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 2387 # Number of Instructions Simulated system.cpu.committedInsts_total 2387 # Number of Instructions Simulated -system.cpu.cpi 6.107667 # CPI: Cycles Per Instruction -system.cpu.cpi_total 6.107667 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 589 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 33939.814815 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35704.918033 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 481 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 3665500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.183362 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 108 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 47 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 2178000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.103565 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 61 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 294 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 38819.444444 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36145.833333 # average WriteReq mshr miss latency +system.cpu.cpi 5.799330 # CPI: Cycles Per Instruction +system.cpu.cpi_total 5.799330 # CPI: Total CPI of All Threads +system.cpu.ipc 0.172434 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.172434 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 4649 # number of integer regfile reads +system.cpu.int_regfile_writes 2817 # number of integer regfile writes +system.cpu.fp_regfile_reads 6 # number of floating regfile reads +system.cpu.misc_regfile_reads 1 # number of misc regfile reads +system.cpu.misc_regfile_writes 1 # number of misc regfile writes +system.cpu.icache.replacements 0 # number of replacements +system.cpu.icache.tagsinuse 92.452549 # Cycle average of tags in use +system.cpu.icache.total_refs 735 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 185 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 3.972973 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::0 92.452549 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.045143 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 735 # number of ReadReq hits +system.cpu.icache.demand_hits 735 # number of demand (read+write) hits +system.cpu.icache.overall_hits 735 # number of overall hits +system.cpu.icache.ReadReq_misses 241 # number of ReadReq misses +system.cpu.icache.demand_misses 241 # number of demand (read+write) misses +system.cpu.icache.overall_misses 241 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 8775500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 8775500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 8775500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 976 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 976 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 976 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.246926 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.246926 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.246926 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 36412.863071 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 36412.863071 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 36412.863071 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits 56 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 56 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 56 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 185 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 185 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 185 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.ReadReq_mshr_miss_latency 6554000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 6554000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 6554000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.189549 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.189549 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.189549 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 35427.027027 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 35427.027027 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 35427.027027 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 0 # number of replacements +system.cpu.dcache.tagsinuse 45.779373 # Cycle average of tags in use +system.cpu.dcache.total_refs 794 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 85 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 9.341176 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 45.779373 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.011177 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 572 # number of ReadReq hits system.cpu.dcache.WriteReq_hits 222 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 2795000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.244898 # miss rate for WriteReq accesses +system.cpu.dcache.demand_hits 794 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 794 # number of overall hits +system.cpu.dcache.ReadReq_misses 116 # number of ReadReq misses system.cpu.dcache.WriteReq_misses 72 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 48 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 867500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.081633 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 24 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 8.270588 # Average number of references to valid blocks. -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.demand_misses 188 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 188 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 3872000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 2816500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 6688500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 6688500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 688 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses 294 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses 982 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 982 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.168605 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.244898 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate 0.191446 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.191446 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 33379.310345 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 39118.055556 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency 35577.127660 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 35577.127660 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 883 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 35891.666667 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 35829.411765 # average overall mshr miss latency -system.cpu.dcache.demand_hits 703 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 6460500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.203851 # miss rate for demand accesses -system.cpu.dcache.demand_misses 180 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 95 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 3045500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.096263 # mshr miss rate for demand accesses +system.cpu.dcache.writebacks 0 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 55 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 48 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits 103 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 103 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 61 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 24 # number of WriteReq MSHR misses system.cpu.dcache.demand_mshr_misses 85 # number of demand (read+write) MSHR misses -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_blocks::0 46.556735 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.011366 # Average percentage of cache occupancy -system.cpu.dcache.overall_accesses 883 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 35891.666667 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 35829.411765 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 703 # number of overall hits -system.cpu.dcache.overall_miss_latency 6460500 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.203851 # miss rate for overall accesses -system.cpu.dcache.overall_misses 180 # number of overall misses -system.cpu.dcache.overall_mshr_hits 95 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 3045500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.096263 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 85 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.sampled_refs 85 # Sample count of references to valid blocks. +system.cpu.dcache.ReadReq_mshr_miss_latency 2165500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 872000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 3037500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 3037500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.088663 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate 0.081633 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate 0.086558 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.086558 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35500 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36333.333333 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 35735.294118 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 35735.294118 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 46.556735 # Cycle average of tags in use -system.cpu.dcache.total_refs 703 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.decode.BlockedCycles 217 # Number of cycles decode is blocked -system.cpu.decode.BranchMispred 79 # Number of times decode detected a branch misprediction -system.cpu.decode.BranchResolved 136 # Number of times decode resolved a branch -system.cpu.decode.DecodedInsts 5047 # Number of instructions handled by decode -system.cpu.decode.IdleCycles 5111 # Number of cycles decode is idle -system.cpu.decode.RunCycles 977 # Number of cycles decode is running -system.cpu.decode.SquashCycles 374 # Number of cycles decode is squashing -system.cpu.decode.SquashedInsts 284 # Number of squashed instructions handled by decode -system.cpu.decode.UnblockCycles 3 # Number of cycles decode is unblocking -system.cpu.dtb.data_accesses 1010 # DTB accesses -system.cpu.dtb.data_acv 1 # DTB access violations -system.cpu.dtb.data_hits 964 # DTB hits -system.cpu.dtb.data_misses 46 # DTB misses -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.read_accesses 644 # DTB read accesses -system.cpu.dtb.read_acv 1 # DTB read access violations -system.cpu.dtb.read_hits 617 # DTB read hits -system.cpu.dtb.read_misses 27 # DTB read misses -system.cpu.dtb.write_accesses 366 # DTB write accesses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 347 # DTB write hits -system.cpu.dtb.write_misses 19 # DTB write misses -system.cpu.fetch.Branches 931 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 777 # Number of cache lines fetched -system.cpu.fetch.Cycles 986 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 113 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 5745 # Number of instructions fetch has processed -system.cpu.fetch.MiscStallCycles 29 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.SquashCycles 246 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.063859 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 777 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 371 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 0.394060 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 6682 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.859773 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.273067 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 5696 85.24% 85.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 43 0.64% 85.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 112 1.68% 87.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 72 1.08% 88.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 123 1.84% 90.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 53 0.79% 91.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 50 0.75% 92.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 59 0.88% 92.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 474 7.09% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 6682 # Number of instructions fetched each cycle (Total) -system.cpu.fp_regfile_reads 6 # number of floating regfile reads -system.cpu.icache.ReadReq_accesses 777 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 36200.431034 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 35306.629834 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 545 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 8398500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.298584 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 232 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 51 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 6390500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.232947 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 181 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 3.011050 # Average number of references to valid blocks. -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 777 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 36200.431034 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 35306.629834 # average overall mshr miss latency -system.cpu.icache.demand_hits 545 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 8398500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.298584 # miss rate for demand accesses -system.cpu.icache.demand_misses 232 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 51 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 6390500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.232947 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 181 # number of demand (read+write) MSHR misses -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_blocks::0 90.511194 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.044195 # Average percentage of cache occupancy -system.cpu.icache.overall_accesses 777 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 36200.431034 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 35306.629834 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 545 # number of overall hits -system.cpu.icache.overall_miss_latency 8398500 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.298584 # miss rate for overall accesses -system.cpu.icache.overall_misses 232 # number of overall misses -system.cpu.icache.overall_mshr_hits 51 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 6390500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.232947 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 181 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.sampled_refs 181 # Sample count of references to valid blocks. -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 90.511194 # Cycle average of tags in use -system.cpu.icache.total_refs 545 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 7897 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.branchMispredicts 171 # Number of branch mispredicts detected at execute -system.cpu.iew.exec_branches 600 # Number of branches executed -system.cpu.iew.exec_nop 311 # number of nop insts executed -system.cpu.iew.exec_rate 0.241855 # Inst execution rate -system.cpu.iew.exec_refs 1011 # number of memory reference insts executed -system.cpu.iew.exec_stores 366 # Number of stores executed -system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.iewBlockCycles 48 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 779 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 6 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 58 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 428 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 4585 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 645 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 109 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 3526 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 374 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 3 # Number of cycles IEW is unblocking -system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread0.forwLoads 28 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread0.memOrderViolation 4 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.squashedLoads 364 # Number of loads squashed -system.cpu.iew.lsq.thread0.squashedStores 134 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 4 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 118 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 53 # Number of branches that were predicted taken incorrectly -system.cpu.iew.wb_consumers 1995 # num instructions consuming a value -system.cpu.iew.wb_count 3404 # cumulative count of insts written-back -system.cpu.iew.wb_fanout 0.790977 # average fanout of values written-back -system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.wb_producers 1578 # num instructions producing a value -system.cpu.iew.wb_rate 0.233487 # insts written-back per cycle -system.cpu.iew.wb_sent 3463 # cumulative count of insts sent to commit -system.cpu.int_regfile_reads 4291 # number of integer regfile reads -system.cpu.int_regfile_writes 2610 # number of integer regfile writes -system.cpu.ipc 0.163729 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.163729 # IPC: Total IPC of All Threads -system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 2594 71.36% 71.36% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.03% 71.39% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 71.39% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 71.39% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 71.39% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 71.39% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 71.39% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 71.39% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 71.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 71.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 71.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 71.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 71.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 71.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 71.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 71.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 71.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 71.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 71.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 71.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 71.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 71.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 71.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 71.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 71.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 71.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 71.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 71.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 71.39% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 669 18.40% 89.79% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 371 10.21% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 3635 # Type of FU issued -system.cpu.iq.fp_alu_accesses 7 # Number of floating point alu accesses -system.cpu.iq.fp_inst_queue_reads 13 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_wakeup_accesses 6 # Number of floating instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_writes 6 # Number of floating instruction queue writes -system.cpu.iq.fu_busy_cnt 32 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.008803 # FU busy rate (busy events/executed inst) -system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 1 3.12% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.12% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 9 28.12% 31.25% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 22 68.75% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.int_alu_accesses 3660 # Number of integer alu accesses -system.cpu.iq.int_inst_queue_reads 14000 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_wakeup_accesses 3398 # Number of integer instruction queue wakeup accesses -system.cpu.iq.int_inst_queue_writes 5975 # Number of integer instruction queue writes -system.cpu.iq.iqInstsAdded 4268 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 3635 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 6 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 1704 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 29 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 959 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.issued_per_cycle::samples 6682 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.543999 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.232060 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 5130 76.77% 76.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 639 9.56% 86.34% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 335 5.01% 91.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 242 3.62% 94.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 178 2.66% 97.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 94 1.41% 99.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 39 0.58% 99.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 16 0.24% 99.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 9 0.13% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 6682 # Number of insts issued each cycle -system.cpu.iq.rate 0.249331 # Inst issue rate -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.fetch_accesses 806 # ITB accesses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_hits 777 # ITB hits -system.cpu.itb.fetch_misses 29 # ITB misses -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.l2cache.ReadExReq_accesses 24 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 34604.166667 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 830500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.replacements 0 # number of replacements +system.cpu.l2cache.tagsinuse 121.331762 # Cycle average of tags in use +system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 246 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::0 121.331762 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.003703 # Average percentage of cache occupancy +system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 0 # number of overall hits +system.cpu.l2cache.ReadReq_misses 246 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses 24 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 756000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 24 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 242 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34326.446281 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31144.628099 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_miss_latency 8307000 # number of ReadReq miss cycles +system.cpu.l2cache.demand_misses 270 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 270 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 8443500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 831000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 9274500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 9274500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 246 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 24 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses 270 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 270 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 242 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 7537000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 242 # number of ReadReq MSHR misses -system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks. -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34323.170732 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34625 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34350 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34350 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 266 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34351.503759 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31176.691729 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 9137500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 266 # number of demand (read+write) misses +system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 8293000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 266 # number of demand (read+write) MSHR misses -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_blocks::0 119.871330 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.003658 # Average percentage of cache occupancy -system.cpu.l2cache.overall_accesses 266 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34351.503759 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31176.691729 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 0 # number of overall hits -system.cpu.l2cache.overall_miss_latency 9137500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 266 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 8293000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 266 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_misses 246 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 24 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 270 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 270 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 242 # Sample count of references to valid blocks. +system.cpu.l2cache.ReadReq_mshr_miss_latency 7659500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 756000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 8415500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 8415500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31136.178862 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31500 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31168.518519 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31168.518519 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 119.871330 # Cycle average of tags in use -system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.memDep0.conflictingLoads 4 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 779 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 428 # Number of stores inserted to the mem dependence unit. -system.cpu.misc_regfile_reads 1 # number of misc regfile reads -system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.numCycles 14579 # number of cpu cycles simulated -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.rename.BlockCycles 55 # Number of cycles rename is blocking -system.cpu.rename.CommittedMaps 1768 # Number of HB maps that are committed -system.cpu.rename.IQFullEvents 6 # Number of times rename has blocked due to IQ full -system.cpu.rename.IdleCycles 5189 # Number of cycles rename is idle -system.cpu.rename.LSQFullEvents 2 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenameLookups 5515 # Number of register rename lookups that rename has made -system.cpu.rename.RenamedInsts 4879 # Number of instructions processed by rename -system.cpu.rename.RenamedOperands 3490 # Number of destination operands rename has renamed -system.cpu.rename.RunCycles 901 # Number of cycles rename is running -system.cpu.rename.SquashCycles 374 # Number of cycles rename is squashing -system.cpu.rename.UnblockCycles 17 # Number of cycles rename is unblocking -system.cpu.rename.UndoneMaps 1722 # Number of HB maps that are undone due to squashing -system.cpu.rename.fp_rename_lookups 12 # Number of floating rename lookups -system.cpu.rename.int_rename_lookups 5503 # Number of integer rename lookups -system.cpu.rename.serializeStallCycles 146 # count of cycles rename stalled for serializing inst -system.cpu.rename.serializingInsts 8 # count of serializing insts renamed -system.cpu.rename.skidInsts 74 # count of insts added to the skid buffer -system.cpu.rename.tempSerializingInsts 6 # count of temporary serializing insts renamed -system.cpu.rob.rob_reads 10591 # The number of ROB reads -system.cpu.rob.rob_writes 9519 # The number of ROB writes -system.cpu.timesIdled 151 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.workload.num_syscalls 4 # Number of system calls +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/arm/linux/o3-timing/config.ini b/tests/quick/00.hello/ref/arm/linux/o3-timing/config.ini index 92bf445c8..b56607812 100644 --- a/tests/quick/00.hello/ref/arm/linux/o3-timing/config.ini +++ b/tests/quick/00.hello/ref/arm/linux/o3-timing/config.ini @@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem mem_mode=atomic +memories=system.physmem physmem=system.physmem work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -498,7 +499,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/arm/linux/hello +executable=/chips/pd/randd/dist/test-progs/hello/bin/arm/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/00.hello/ref/arm/linux/o3-timing/simerr b/tests/quick/00.hello/ref/arm/linux/o3-timing/simerr index eabe42249..e45cd058f 100755 --- a/tests/quick/00.hello/ref/arm/linux/o3-timing/simerr +++ b/tests/quick/00.hello/ref/arm/linux/o3-timing/simerr @@ -1,3 +1,2 @@ warn: Sockets disabled, not accepting gdb connections -For more information see: http://www.m5sim.org/warn/d946bea6 hack: be nice to actually delete the event here diff --git a/tests/quick/00.hello/ref/arm/linux/o3-timing/simout b/tests/quick/00.hello/ref/arm/linux/o3-timing/simout index 7a48bdd9d..357a5d59d 100755 --- a/tests/quick/00.hello/ref/arm/linux/o3-timing/simout +++ b/tests/quick/00.hello/ref/arm/linux/o3-timing/simout @@ -1,17 +1,11 @@ -Redirecting stdout to build/ARM_SE/tests/fast/quick/00.hello/arm/linux/o3-timing/simout -Redirecting stderr to build/ARM_SE/tests/fast/quick/00.hello/arm/linux/o3-timing/simerr -M5 Simulator System +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled May 16 2011 15:11:25 -M5 started May 16 2011 15:11:56 -M5 executing on nadc-0271 -command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/quick/00.hello/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/quick/00.hello/arm/linux/o3-timing +gem5 compiled Jul 8 2011 15:18:43 +gem5 started Jul 8 2011 15:23:20 +gem5 executing on u200439-lin.austin.arm.com +command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/quick/00.hello/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/quick/00.hello/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 10758500 because target called exit() +Exiting @ tick 9834500 because target called exit() diff --git a/tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt index b65280987..d884999d2 100644 --- a/tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt @@ -1,12 +1,12 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000011 # Number of seconds simulated -sim_ticks 10758500 # Number of ticks simulated +sim_seconds 0.000010 # Number of seconds simulated +sim_ticks 9834500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 88454 # Simulator instruction rate (inst/s) -host_tick_rate 165780634 # Simulator tick rate (ticks/s) -host_mem_usage 251164 # Number of bytes of host memory used -host_seconds 0.07 # Real time elapsed on the host +host_inst_rate 38040 # Simulator instruction rate (inst/s) +host_tick_rate 65174027 # Simulator tick rate (ticks/s) +host_mem_usage 253652 # Number of bytes of host memory used +host_seconds 0.15 # Real time elapsed on the host sim_insts 5739 # Number of instructions simulated system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses @@ -51,242 +51,244 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.numCycles 21518 # number of cpu cycles simulated +system.cpu.numCycles 19670 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 2191 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 1669 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 423 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 1853 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 732 # Number of BTB hits +system.cpu.BPredUnit.lookups 2538 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 1884 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 440 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 1886 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 760 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 242 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 63 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 1618 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 11168 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2191 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 974 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 2422 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 514 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.CacheLines 1618 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 231 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 11665 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.190999 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.598414 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 268 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 53 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 6290 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 12764 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2538 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 1028 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 2852 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1670 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 1030 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 31 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 2054 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 312 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 11334 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.423857 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.772019 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 9243 79.24% 79.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 226 1.94% 81.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 153 1.31% 82.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 215 1.84% 84.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 195 1.67% 86.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 261 2.24% 88.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 124 1.06% 89.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 97 0.83% 90.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1151 9.87% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 8482 74.84% 74.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 284 2.51% 77.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 192 1.69% 79.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 246 2.17% 81.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 242 2.14% 83.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 324 2.86% 86.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 124 1.09% 87.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 120 1.06% 88.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1320 11.65% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 11665 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.101822 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.519007 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 7384 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 1181 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2267 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 47 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 786 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 350 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 158 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 12143 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 552 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 786 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 7644 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 280 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 712 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2054 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 189 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 11385 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 38 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 124 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 11181 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 51901 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 51381 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 520 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 11334 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.129029 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.648907 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 6573 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 1079 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2654 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 60 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 968 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 421 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 167 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 14169 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 591 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 968 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 6862 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 248 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 651 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2422 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 183 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 13321 # Number of instructions processed by rename +system.cpu.rename.LSQFullEvents 164 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 12898 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 60750 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 59430 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1320 # Number of floating rename lookups system.cpu.rename.CommittedMaps 5684 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 5492 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 15 # count of serializing insts renamed +system.cpu.rename.UndoneMaps 7209 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 16 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 13 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 493 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2353 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1452 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 10217 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 24 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8487 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 21 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 3978 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 11076 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.issued_per_cycle::samples 11665 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.727561 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.389080 # Number of insts issued each cycle +system.cpu.rename.skidInsts 446 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2701 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1759 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 11 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 5 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 11506 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 25 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 9339 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 101 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 5207 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 14048 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 11334 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.823981 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.484525 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 8112 69.54% 69.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1403 12.03% 81.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 820 7.03% 88.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 520 4.46% 93.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 393 3.37% 96.43% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 236 2.02% 98.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 143 1.23% 99.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 30 0.26% 99.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 8 0.07% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 7613 67.17% 67.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1341 11.83% 79.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 855 7.54% 86.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 564 4.98% 91.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 476 4.20% 95.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 284 2.51% 98.23% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 147 1.30% 99.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 42 0.37% 99.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 12 0.11% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 11665 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 11334 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 11 6.01% 6.01% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 6.01% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 6.01% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.01% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.01% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.01% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 6.01% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.01% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 6.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 6.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.01% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.01% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 116 63.39% 69.40% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 56 30.60% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 6 2.79% 2.79% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 2.79% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 2.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 2.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 2.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 2.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.79% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 138 64.19% 66.98% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 71 33.02% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5246 61.81% 61.81% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 6 0.07% 61.88% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.88% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 61.88% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.88% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.88% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.88% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.88% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 61.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.92% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2078 24.48% 86.40% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1154 13.60% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 5727 61.32% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 7 0.07% 61.40% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.40% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 61.40% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.40% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.40% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.40% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.40% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 61.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.43% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2324 24.88% 86.32% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1278 13.68% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8487 # Type of FU issued -system.cpu.iq.rate 0.394414 # Inst issue rate -system.cpu.iq.fu_busy_cnt 183 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.021562 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 28807 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 14215 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 7753 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes +system.cpu.iq.FU_type_0::total 9339 # Type of FU issued +system.cpu.iq.rate 0.474784 # Inst issue rate +system.cpu.iq.fu_busy_cnt 215 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.023022 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 30256 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 16705 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 8361 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 72 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 48 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 8650 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 50 # Number of loads that had data forwarded from stores +system.cpu.iq.int_alu_accesses 9514 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 40 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 67 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1152 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1500 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 14 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 514 # Number of stores squashed +system.cpu.iew.lsq.thread0.memOrderViolation 19 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 821 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 786 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 166 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 27 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 10244 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 136 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2353 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1452 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 12 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 19 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 968 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 129 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 8 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 11534 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 218 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2701 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1759 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 13 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 14 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 128 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 243 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 371 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 8154 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1932 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 333 # Number of squashed instructions skipped in execute +system.cpu.iew.memOrderViolationEvents 19 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 95 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 303 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 398 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 8897 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2129 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 442 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 3 # number of nop insts executed -system.cpu.iew.exec_refs 3053 # number of memory reference insts executed -system.cpu.iew.exec_branches 1361 # Number of branches executed -system.cpu.iew.exec_stores 1121 # Number of stores executed -system.cpu.iew.exec_rate 0.378939 # Inst execution rate -system.cpu.iew.wb_sent 7896 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 7769 # cumulative count of insts written-back -system.cpu.iew.wb_producers 3570 # num instructions producing a value -system.cpu.iew.wb_consumers 7022 # num instructions consuming a value +system.cpu.iew.exec_refs 3351 # number of memory reference insts executed +system.cpu.iew.exec_branches 1479 # Number of branches executed +system.cpu.iew.exec_stores 1222 # Number of stores executed +system.cpu.iew.exec_rate 0.452313 # Inst execution rate +system.cpu.iew.wb_sent 8556 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 8377 # cumulative count of insts written-back +system.cpu.iew.wb_producers 3980 # num instructions producing a value +system.cpu.iew.wb_consumers 7830 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.361047 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.508402 # average fanout of values written-back +system.cpu.iew.wb_rate 0.425877 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.508301 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 5739 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 4400 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 5640 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 24 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 334 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 10880 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.527482 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.289859 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 351 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 10367 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.553583 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.355703 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 8406 77.26% 77.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1187 10.91% 88.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 477 4.38% 92.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 317 2.91% 95.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 170 1.56% 97.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 153 1.41% 98.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 62 0.57% 99.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 34 0.31% 99.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 74 0.68% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 8010 77.26% 77.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1098 10.59% 87.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 433 4.18% 92.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 284 2.74% 94.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 184 1.77% 96.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 168 1.62% 98.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 67 0.65% 98.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 39 0.38% 99.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 84 0.81% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 10880 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 10367 # Number of insts commited each cycle system.cpu.commit.count 5739 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 2139 # Number of memory references committed @@ -296,49 +298,49 @@ system.cpu.commit.branches 945 # Nu system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. system.cpu.commit.int_insts 4985 # Number of committed integer instructions. system.cpu.commit.function_calls 82 # Number of function calls committed. -system.cpu.commit.bw_lim_events 74 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 84 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 20788 # The number of ROB reads -system.cpu.rob.rob_writes 21080 # The number of ROB writes -system.cpu.timesIdled 199 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 9853 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 21505 # The number of ROB reads +system.cpu.rob.rob_writes 23748 # The number of ROB writes +system.cpu.timesIdled 180 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 8336 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5739 # Number of Instructions Simulated system.cpu.committedInsts_total 5739 # Number of Instructions Simulated -system.cpu.cpi 3.749434 # CPI: Cycles Per Instruction -system.cpu.cpi_total 3.749434 # CPI: Total CPI of All Threads -system.cpu.ipc 0.266707 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.266707 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 37248 # number of integer regfile reads -system.cpu.int_regfile_writes 7653 # number of integer regfile writes -system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 13970 # number of misc regfile reads +system.cpu.cpi 3.427426 # CPI: Cycles Per Instruction +system.cpu.cpi_total 3.427426 # CPI: Total CPI of All Threads +system.cpu.ipc 0.291764 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.291764 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 40468 # number of integer regfile reads +system.cpu.int_regfile_writes 8226 # number of integer regfile writes +system.cpu.fp_regfile_reads 29 # number of floating regfile reads +system.cpu.misc_regfile_reads 15801 # number of misc regfile reads system.cpu.misc_regfile_writes 24 # number of misc regfile writes system.cpu.icache.replacements 2 # number of replacements -system.cpu.icache.tagsinuse 146.709916 # Cycle average of tags in use -system.cpu.icache.total_refs 1288 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 285 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 4.519298 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 150.859133 # Cycle average of tags in use +system.cpu.icache.total_refs 1688 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 296 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 5.702703 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 146.709916 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.071636 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 1288 # number of ReadReq hits -system.cpu.icache.demand_hits 1288 # number of demand (read+write) hits -system.cpu.icache.overall_hits 1288 # number of overall hits -system.cpu.icache.ReadReq_misses 330 # number of ReadReq misses -system.cpu.icache.demand_misses 330 # number of demand (read+write) misses -system.cpu.icache.overall_misses 330 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 11562500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 11562500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 11562500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 1618 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 1618 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 1618 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.203956 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.203956 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.203956 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 35037.878788 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 35037.878788 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 35037.878788 # average overall miss latency +system.cpu.icache.occ_blocks::0 150.859133 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.073662 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 1688 # number of ReadReq hits +system.cpu.icache.demand_hits 1688 # number of demand (read+write) hits +system.cpu.icache.overall_hits 1688 # number of overall hits +system.cpu.icache.ReadReq_misses 366 # number of ReadReq misses +system.cpu.icache.demand_misses 366 # number of demand (read+write) misses +system.cpu.icache.overall_misses 366 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 12656500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 12656500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 12656500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 2054 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 2054 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 2054 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.178189 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.178189 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.178189 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 34580.601093 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 34580.601093 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 34580.601093 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -348,67 +350,67 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 45 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 45 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 45 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 285 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 285 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 285 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_hits 70 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 70 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 70 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 296 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 296 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 296 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 9568500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 9568500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 9568500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 9940500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 9940500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 9940500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.176143 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.176143 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.176143 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 33573.684211 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 33573.684211 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 33573.684211 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate 0.144109 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.144109 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.144109 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 33582.770270 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 33582.770270 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 33582.770270 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 89.574063 # Cycle average of tags in use -system.cpu.dcache.total_refs 2279 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 149 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 15.295302 # Average number of references to valid blocks. +system.cpu.dcache.tagsinuse 92.281770 # Cycle average of tags in use +system.cpu.dcache.total_refs 2420 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 156 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 15.512821 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 89.574063 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.021869 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 1637 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 622 # number of WriteReq hits +system.cpu.dcache.occ_blocks::0 92.281770 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.022530 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 1791 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 609 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits 9 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits 11 # number of StoreCondReq hits -system.cpu.dcache.demand_hits 2259 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 2259 # number of overall hits -system.cpu.dcache.ReadReq_misses 159 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 291 # number of WriteReq misses +system.cpu.dcache.demand_hits 2400 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 2400 # number of overall hits +system.cpu.dcache.ReadReq_misses 178 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 304 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses 450 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 450 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 5132500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 10420500 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses 482 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 482 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 5526000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 10705500 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency 76500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency 15553000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 15553000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 1796 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency 16231500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 16231500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 1969 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses 11 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 2709 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 2709 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.088530 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.318729 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses 2882 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 2882 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.090401 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.332968 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate 0.181818 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate 0.166113 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.166113 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 32279.874214 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 35809.278351 # average WriteReq miss latency +system.cpu.dcache.demand_miss_rate 0.167245 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.167245 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 31044.943820 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 35215.460526 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency 38250 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency 34562.222222 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 34562.222222 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency 33675.311203 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 33675.311203 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -418,64 +420,64 @@ system.cpu.dcache.avg_blocked_cycles::no_targets no_value system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 52 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 249 # number of WriteReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits 64 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 262 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits 301 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 301 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 107 # number of ReadReq MSHR misses +system.cpu.dcache.demand_mshr_hits 326 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 326 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 114 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses 42 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 149 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 149 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_misses 156 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 156 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 3099500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 1507500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 4607000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 4607000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 3236500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 1505000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 4741500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 4741500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.059577 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate 0.057897 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate 0.046002 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.055002 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.055002 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 28967.289720 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35892.857143 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 30919.463087 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 30919.463087 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate 0.054129 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.054129 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 28390.350877 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35833.333333 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 30394.230769 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 30394.230769 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 185.420659 # Cycle average of tags in use -system.cpu.l2cache.total_refs 39 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 347 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.112392 # Average number of references to valid blocks. +system.cpu.l2cache.tagsinuse 190.940380 # Cycle average of tags in use +system.cpu.l2cache.total_refs 43 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 362 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.118785 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 185.420659 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.005659 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 39 # number of ReadReq hits -system.cpu.l2cache.demand_hits 39 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 39 # number of overall hits -system.cpu.l2cache.ReadReq_misses 353 # number of ReadReq misses +system.cpu.l2cache.occ_blocks::0 190.940380 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.005827 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 43 # number of ReadReq hits +system.cpu.l2cache.demand_hits 43 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 43 # number of overall hits +system.cpu.l2cache.ReadReq_misses 367 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses 42 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 395 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 395 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 12138500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 1447000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 13585500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 13585500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 392 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.demand_misses 409 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 409 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 12612500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 1450500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 14063000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 14063000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 410 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses 42 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 434 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 434 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.900510 # miss rate for ReadReq accesses +system.cpu.l2cache.demand_accesses 452 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 452 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.895122 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.910138 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.910138 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34386.685552 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34452.380952 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34393.670886 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34393.670886 # average overall miss latency +system.cpu.l2cache.demand_miss_rate 0.904867 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.904867 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34366.485014 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34535.714286 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34383.863081 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34383.863081 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -485,27 +487,27 @@ system.cpu.l2cache.avg_blocked_cycles::no_targets no_value system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits 6 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits 6 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 6 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 347 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_hits 5 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits 5 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits 5 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses 362 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses 42 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 389 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 389 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses 404 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 404 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 10837500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 1315000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 12152500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 12152500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 11305500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 1317000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 12622500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 12622500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.885204 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.882927 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.896313 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.896313 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31231.988473 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31309.523810 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31240.359897 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31240.359897 # average overall mshr miss latency +system.cpu.l2cache.demand_mshr_miss_rate 0.893805 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.893805 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31230.662983 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31357.142857 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31243.811881 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31243.811881 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/quick/00.hello/ref/mips/linux/inorder-timing/simout b/tests/quick/00.hello/ref/mips/linux/inorder-timing/simout index 15c18bd45..ba028db41 100755 --- a/tests/quick/00.hello/ref/mips/linux/inorder-timing/simout +++ b/tests/quick/00.hello/ref/mips/linux/inorder-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 19 2011 14:43:48 -gem5 started Jun 19 2011 14:43:49 -gem5 executing on zooks -command line: build/MIPS_SE/gem5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/inorder-timing -re tests/run.py build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/inorder-timing +gem5 compiled Jul 8 2011 15:04:50 +gem5 started Jul 8 2011 15:22:23 +gem5 executing on u200439-lin.austin.arm.com +command line: build/MIPS_SE/gem5.opt -d build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/inorder-timing -re tests/run.py build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello World! -Exiting @ tick 19782000 because target called exit() +Exiting @ tick 19785000 because target called exit() diff --git a/tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt b/tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt index 340c12899..bde2424c6 100644 --- a/tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt +++ b/tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt @@ -1,12 +1,12 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000020 # Number of seconds simulated -sim_ticks 19782000 # Number of ticks simulated +sim_ticks 19785000 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 56447 # Simulator instruction rate (inst/s) -host_tick_rate 191567423 # Simulator tick rate (ticks/s) -host_mem_usage 158160 # Number of bytes of host memory used -host_seconds 0.10 # Real time elapsed on the host +host_inst_rate 27579 # Simulator instruction rate (inst/s) +host_tick_rate 93627553 # Simulator tick rate (ticks/s) +host_mem_usage 243928 # Number of bytes of host memory used +host_seconds 0.21 # Real time elapsed on the host sim_insts 5827 # Number of instructions simulated system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses @@ -27,16 +27,16 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 8 # Number of system calls -system.cpu.numCycles 39565 # number of cpu cycles simulated +system.cpu.numCycles 39571 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 9153 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 9159 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode system.cpu.timesIdled 403 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 34165 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 5400 # Number of cycles cpu stages are processed. -system.cpu.activity 13.648427 # Percentage of cycles cpu is active +system.cpu.idleCycles 34166 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 5405 # Number of cycles cpu stages are processed. +system.cpu.activity 13.658993 # Percentage of cycles cpu is active system.cpu.comLoads 1164 # Number of Load instructions committed system.cpu.comStores 925 # Number of Store instructions committed system.cpu.comBranches 916 # Number of Branches instructions committed @@ -47,79 +47,79 @@ system.cpu.comFloats 0 # Nu system.cpu.committedInsts 5827 # Number of Instructions Simulated (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread) system.cpu.committedInsts_total 5827 # Number of Instructions Simulated (Total) -system.cpu.cpi 6.789943 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 6.790973 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi no_value # CPI: Total SMT-CPI -system.cpu.cpi_total 6.789943 # CPI: Total CPI of All Threads -system.cpu.ipc 0.147277 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 6.790973 # CPI: Total CPI of All Threads +system.cpu.ipc 0.147254 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc no_value # IPC: Total SMT-IPC -system.cpu.ipc_total 0.147277 # IPC: Total IPC of All Threads -system.cpu.branch_predictor.lookups 1173 # Number of BP lookups -system.cpu.branch_predictor.condPredicted 886 # Number of conditional branches predicted -system.cpu.branch_predictor.condIncorrect 609 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 1011 # Number of BTB lookups -system.cpu.branch_predictor.BTBHits 413 # Number of BTB hits +system.cpu.ipc_total 0.147254 # IPC: Total IPC of All Threads +system.cpu.branch_predictor.lookups 1185 # Number of BP lookups +system.cpu.branch_predictor.condPredicted 896 # Number of conditional branches predicted +system.cpu.branch_predictor.condIncorrect 611 # Number of conditional branches incorrect +system.cpu.branch_predictor.BTBLookups 1035 # Number of BTB lookups +system.cpu.branch_predictor.BTBHits 443 # Number of BTB hits system.cpu.branch_predictor.usedRAS 86 # Number of times the RAS was used to get a target. system.cpu.branch_predictor.RASInCorrect 32 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 40.850643 # BTB Hit Percentage -system.cpu.branch_predictor.predictedTaken 506 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 667 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 5107 # Number of Reads from Int. Register File +system.cpu.branch_predictor.BTBHitPct 42.801932 # BTB Hit Percentage +system.cpu.branch_predictor.predictedTaken 536 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 649 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 5108 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 3408 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 8515 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.intRegFileAccesses 8516 # Total Accesses (Read+Write) to the Int. Register File system.cpu.regfile_manager.floatRegFileReads 3 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 1 # Number of Writes to FP Register File system.cpu.regfile_manager.floatRegFileAccesses 4 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 1342 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 2229 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 313 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 287 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 600 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 316 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 65.502183 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 3130 # Number of Instructions Executed. +system.cpu.regfile_manager.regForwards 1344 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 2228 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 317 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 285 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 602 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 314 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 65.720524 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 3132 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 3 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 1 # Number of Divide Operations Executed -system.cpu.stage0.idleCycles 35845 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 3720 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 9.402249 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 36724 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 2841 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 7.180589 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 36774 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 2791 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 7.054215 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 38322 # Number of cycles 0 instructions are processed. +system.cpu.stage0.idleCycles 35846 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 3725 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 9.413459 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 36723 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 2848 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 7.197190 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 36778 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 2793 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 7.058199 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 38328 # Number of cycles 0 instructions are processed. system.cpu.stage3.runCycles 1243 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 3.141666 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 36660 # Number of cycles 0 instructions are processed. +system.cpu.stage3.utilization 3.141189 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 36666 # Number of cycles 0 instructions are processed. system.cpu.stage4.runCycles 2905 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 7.342348 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.utilization 7.341235 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 13 # number of replacements -system.cpu.icache.tagsinuse 148.154290 # Cycle average of tags in use -system.cpu.icache.total_refs 442 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 148.138598 # Cycle average of tags in use +system.cpu.icache.total_refs 443 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 319 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 1.385580 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 1.388715 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 148.154290 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.072341 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 442 # number of ReadReq hits -system.cpu.icache.demand_hits 442 # number of demand (read+write) hits -system.cpu.icache.overall_hits 442 # number of overall hits +system.cpu.icache.occ_blocks::0 148.138598 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.072333 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 443 # number of ReadReq hits +system.cpu.icache.demand_hits 443 # number of demand (read+write) hits +system.cpu.icache.overall_hits 443 # number of overall hits system.cpu.icache.ReadReq_misses 341 # number of ReadReq misses system.cpu.icache.demand_misses 341 # number of demand (read+write) misses system.cpu.icache.overall_misses 341 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 19026500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 19026500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 19026500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 783 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 783 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 783 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.435504 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.435504 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.435504 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 55796.187683 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 55796.187683 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 55796.187683 # average overall miss latency +system.cpu.icache.ReadReq_miss_latency 19027500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 19027500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 19027500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 784 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 784 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 784 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.434949 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.434949 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.434949 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 55799.120235 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 55799.120235 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 55799.120235 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 29000 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -136,28 +136,28 @@ system.cpu.icache.ReadReq_mshr_misses 319 # nu system.cpu.icache.demand_mshr_misses 319 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses 319 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 16952000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 16952000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 16952000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 16952500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 16952500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 16952500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.407407 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.407407 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.407407 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 53141.065831 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 53141.065831 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 53141.065831 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate 0.406888 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.406888 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.406888 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 53142.633229 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 53142.633229 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 53142.633229 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 89.737794 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 89.732679 # Cycle average of tags in use system.cpu.dcache.total_refs 1838 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 13.318841 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 89.737794 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.021909 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 89.732679 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.021907 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits 1075 # number of ReadReq hits system.cpu.dcache.WriteReq_hits 763 # number of WriteReq hits system.cpu.dcache.demand_hits 1838 # number of demand (read+write) hits @@ -167,9 +167,9 @@ system.cpu.dcache.WriteReq_misses 162 # nu system.cpu.dcache.demand_misses 251 # number of demand (read+write) misses system.cpu.dcache.overall_misses 251 # number of overall misses system.cpu.dcache.ReadReq_miss_latency 5072500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 8910500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 13983000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 13983000 # number of overall miss cycles +system.cpu.dcache.WriteReq_miss_latency 8912000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 13984500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 13984500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses 1164 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 925 # number of WriteReq accesses(hits+misses) system.cpu.dcache.demand_accesses 2089 # number of demand (read+write) accesses @@ -179,9 +179,9 @@ system.cpu.dcache.WriteReq_miss_rate 0.175135 # mi system.cpu.dcache.demand_miss_rate 0.120153 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate 0.120153 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency 56994.382022 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 55003.086420 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 55709.163347 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 55709.163347 # average overall miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 55012.345679 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency 55715.139442 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 55715.139442 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 1153500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -201,30 +201,30 @@ system.cpu.dcache.demand_mshr_misses 138 # nu system.cpu.dcache.overall_mshr_misses 138 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.ReadReq_mshr_miss_latency 4702500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 2745500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 7448000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 7448000 # number of overall MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 2746000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 7448500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 7448500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.074742 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate 0.055135 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate 0.066060 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate 0.066060 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency 54051.724138 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53833.333333 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 53971.014493 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 53971.014493 # average overall mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53843.137255 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 53974.637681 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 53974.637681 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 205.489748 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 205.469583 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 404 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.004950 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 205.489748 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.006271 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 205.469583 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.006270 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits system.cpu.l2cache.overall_hits 2 # number of overall hits @@ -232,10 +232,10 @@ system.cpu.l2cache.ReadReq_misses 404 # nu system.cpu.l2cache.ReadExReq_misses 51 # number of ReadExReq misses system.cpu.l2cache.demand_misses 455 # number of demand (read+write) misses system.cpu.l2cache.overall_misses 455 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 21170000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 2682000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 23852000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 23852000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency 21170500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 2682500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 23853000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 23853000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses 406 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses 51 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses 457 # number of demand (read+write) accesses @@ -244,10 +244,10 @@ system.cpu.l2cache.ReadReq_miss_rate 0.995074 # mi system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate 0.995624 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate 0.995624 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 52400.990099 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 52588.235294 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 52421.978022 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 52421.978022 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 52402.227723 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 52598.039216 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 52424.175824 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 52424.175824 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked diff --git a/tests/quick/00.hello/ref/mips/linux/o3-timing/config.ini b/tests/quick/00.hello/ref/mips/linux/o3-timing/config.ini index 5fbba49b2..8bda4905e 100644 --- a/tests/quick/00.hello/ref/mips/linux/o3-timing/config.ini +++ b/tests/quick/00.hello/ref/mips/linux/o3-timing/config.ini @@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem mem_mode=atomic +memories=system.physmem physmem=system.physmem work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -498,7 +499,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/mips/linux/hello +executable=/chips/pd/randd/dist/test-progs/hello/bin/mips/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/00.hello/ref/mips/linux/o3-timing/simout b/tests/quick/00.hello/ref/mips/linux/o3-timing/simout index b9191e12f..d2612b5d7 100755 --- a/tests/quick/00.hello/ref/mips/linux/o3-timing/simout +++ b/tests/quick/00.hello/ref/mips/linux/o3-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 19 2011 07:04:09 -gem5 started Jun 19 2011 07:04:15 -gem5 executing on m60-009.pool -command line: build/MIPS_SE/gem5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/o3-timing -re tests/run.py build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/o3-timing +gem5 compiled Jul 8 2011 15:04:50 +gem5 started Jul 8 2011 15:22:25 +gem5 executing on u200439-lin.austin.arm.com +command line: build/MIPS_SE/gem5.opt -d build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/o3-timing -re tests/run.py build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello World! -Exiting @ tick 12793500 because target called exit() +Exiting @ tick 12285500 because target called exit() diff --git a/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt index ad65ae514..39498f791 100644 --- a/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt @@ -1,12 +1,12 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000013 # Number of seconds simulated -sim_ticks 12793500 # Number of ticks simulated +sim_seconds 0.000012 # Number of seconds simulated +sim_ticks 12285500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 95916 # Simulator instruction rate (inst/s) -host_tick_rate 237306997 # Simulator tick rate (ticks/s) -host_mem_usage 193796 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host +host_inst_rate 28817 # Simulator instruction rate (inst/s) +host_tick_rate 68479139 # Simulator tick rate (ticks/s) +host_mem_usage 244744 # Number of bytes of host memory used +host_seconds 0.18 # Real time elapsed on the host sim_insts 5169 # Number of instructions simulated system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses @@ -27,241 +27,244 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 8 # Number of system calls -system.cpu.numCycles 25588 # number of cpu cycles simulated +system.cpu.numCycles 24572 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 1716 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 1180 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 380 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 1503 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 531 # Number of BTB hits +system.cpu.BPredUnit.lookups 1982 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 1348 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 399 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 1584 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 496 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 206 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 66 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 1531 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 10867 # Number of instructions fetch has processed -system.cpu.fetch.Branches 1716 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 737 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 2794 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 387 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 15 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.CacheLines 1531 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 211 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 12856 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.845286 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.112165 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 251 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 71 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 7946 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 12305 # Number of instructions fetch has processed +system.cpu.fetch.Branches 1982 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 747 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 3034 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1194 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 756 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 145 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 1787 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 231 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 12667 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.971422 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.277830 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 10062 78.27% 78.27% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1173 9.12% 87.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 132 1.03% 88.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 122 0.95% 89.37% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 273 2.12% 91.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 123 0.96% 92.45% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 157 1.22% 93.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 97 0.75% 94.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 717 5.58% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 9633 76.05% 76.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1253 9.89% 85.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 111 0.88% 86.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 138 1.09% 87.91% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 289 2.28% 90.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 92 0.73% 90.91% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 132 1.04% 91.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 144 1.14% 93.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 875 6.91% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 12856 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.067063 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.424691 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8753 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 742 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2688 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 37 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 636 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 89 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 42 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 10279 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 153 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 636 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 8904 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 238 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 420 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2577 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 81 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 9880 # Number of instructions processed by rename -system.cpu.rename.LSQFullEvents 71 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 6029 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 11929 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 11924 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 12667 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.080661 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.500773 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8135 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 871 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2867 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 51 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 743 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 107 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 43 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 11479 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 162 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 743 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 8306 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 258 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 499 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2750 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 111 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 11058 # Number of instructions processed by rename +system.cpu.rename.LSQFullEvents 101 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 6730 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 13185 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 13180 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 5 # Number of floating rename lookups system.cpu.rename.CommittedMaps 3410 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 2619 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 15 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 10 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 193 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2109 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1127 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.UndoneMaps 3320 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 18 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 11 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 281 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2359 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1184 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 1 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 7965 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 10 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 7293 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 31 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 2360 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1480 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.issued_per_cycle::samples 12856 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.567284 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.210668 # Number of insts issued each cycle +system.cpu.iq.iqInstsAdded 8691 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 13 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 7857 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 51 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 3019 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1823 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 3 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 12667 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.620273 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.285525 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 9551 74.29% 74.29% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1436 11.17% 85.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 786 6.11% 91.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 503 3.91% 95.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 300 2.33% 97.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 160 1.24% 99.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 76 0.59% 99.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 32 0.25% 99.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 12 0.09% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 9298 73.40% 73.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1326 10.47% 83.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 831 6.56% 90.43% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 513 4.05% 94.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 361 2.85% 97.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 205 1.62% 98.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 85 0.67% 99.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 33 0.26% 99.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 15 0.12% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 12856 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 12667 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 7 4.90% 4.90% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 4.90% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 4.90% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.90% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.90% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.90% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 4.90% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.90% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 4.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 4.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.90% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 84 58.74% 63.64% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 52 36.36% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 3 2.07% 2.07% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 2.07% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 2.07% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.07% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.07% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.07% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 2.07% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.07% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 2.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 2.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.07% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 90 62.07% 64.14% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 52 35.86% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 4286 58.77% 58.77% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 4 0.05% 58.82% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 2 0.03% 58.85% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.03% 58.88% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 58.88% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 58.88% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 58.88% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 58.88% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 58.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 58.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 58.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 58.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 58.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 58.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 58.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 58.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 58.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 58.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 58.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 58.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 58.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 58.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 58.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 58.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 58.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 58.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 58.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 58.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 58.88% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1952 26.77% 85.64% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1047 14.36% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 4616 58.75% 58.75% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 4 0.05% 58.80% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 2 0.03% 58.83% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.03% 58.85% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 58.85% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 58.85% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 58.85% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 58.85% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 58.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 58.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 58.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 58.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 58.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 58.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 58.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 58.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 58.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 58.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 58.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 58.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 58.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 58.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 58.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 58.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 58.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 58.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 58.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 58.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 58.85% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2141 27.25% 86.10% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1092 13.90% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 7293 # Type of FU issued -system.cpu.iq.rate 0.285016 # Inst issue rate -system.cpu.iq.fu_busy_cnt 143 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.019608 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 27612 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 10338 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 6730 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 7857 # Type of FU issued +system.cpu.iq.rate 0.319754 # Inst issue rate +system.cpu.iq.fu_busy_cnt 145 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.018455 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 28573 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 11730 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 7154 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 4 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 2 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 7434 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 8000 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 2 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 59 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 65 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 945 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 5 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 202 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1195 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 9 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 259 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 636 # Number of cycles IEW is squashing +system.cpu.iew.iewSquashCycles 743 # Number of cycles IEW is squashing system.cpu.iew.iewBlockCycles 165 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 14 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 9195 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 198 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2109 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1127 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 10 # Number of dispatched non-speculative instructions +system.cpu.iew.iewUnblockCycles 13 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 10089 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 128 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2359 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1184 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 13 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 6 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 1 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 5 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 118 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 259 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 377 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 7077 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1877 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 216 # Number of squashed instructions skipped in execute +system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 9 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 107 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 309 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 416 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 7573 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2041 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 284 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1220 # number of nop insts executed -system.cpu.iew.exec_refs 2915 # number of memory reference insts executed -system.cpu.iew.exec_branches 1171 # Number of branches executed -system.cpu.iew.exec_stores 1038 # Number of stores executed -system.cpu.iew.exec_rate 0.276575 # Inst execution rate -system.cpu.iew.wb_sent 6801 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 6732 # cumulative count of insts written-back -system.cpu.iew.wb_producers 2555 # num instructions producing a value -system.cpu.iew.wb_consumers 3566 # num instructions consuming a value +system.cpu.iew.exec_nop 1385 # number of nop insts executed +system.cpu.iew.exec_refs 3109 # number of memory reference insts executed +system.cpu.iew.exec_branches 1276 # Number of branches executed +system.cpu.iew.exec_stores 1068 # Number of stores executed +system.cpu.iew.exec_rate 0.308196 # Inst execution rate +system.cpu.iew.wb_sent 7250 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 7156 # cumulative count of insts written-back +system.cpu.iew.wb_producers 2771 # num instructions producing a value +system.cpu.iew.wb_consumers 3964 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.263092 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.716489 # average fanout of values written-back +system.cpu.iew.wb_rate 0.291226 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.699041 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 5826 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 3363 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 4255 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 10 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 339 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 12220 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.476759 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.219720 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 357 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 11924 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.488594 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.274116 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 9742 79.72% 79.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 995 8.14% 87.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 703 5.75% 93.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 335 2.74% 96.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 169 1.38% 97.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 98 0.80% 98.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 69 0.56% 99.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 32 0.26% 99.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 77 0.63% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 9523 79.86% 79.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 968 8.12% 87.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 656 5.50% 93.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 322 2.70% 96.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 146 1.22% 97.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 102 0.86% 98.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 64 0.54% 98.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 42 0.35% 99.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 101 0.85% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 12220 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 11924 # Number of insts commited each cycle system.cpu.commit.count 5826 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 2089 # Number of memory references committed @@ -271,49 +274,49 @@ system.cpu.commit.branches 916 # Nu system.cpu.commit.fp_insts 2 # Number of committed floating point instructions. system.cpu.commit.int_insts 5124 # Number of committed integer instructions. system.cpu.commit.function_calls 87 # Number of function calls committed. -system.cpu.commit.bw_lim_events 77 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 101 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 21319 # The number of ROB reads -system.cpu.rob.rob_writes 19020 # The number of ROB writes -system.cpu.timesIdled 260 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 12732 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 21891 # The number of ROB reads +system.cpu.rob.rob_writes 20916 # The number of ROB writes +system.cpu.timesIdled 251 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 11905 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5169 # Number of Instructions Simulated system.cpu.committedInsts_total 5169 # Number of Instructions Simulated -system.cpu.cpi 4.950281 # CPI: Cycles Per Instruction -system.cpu.cpi_total 4.950281 # CPI: Total CPI of All Threads -system.cpu.ipc 0.202009 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.202009 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 9689 # number of integer regfile reads -system.cpu.int_regfile_writes 4703 # number of integer regfile writes +system.cpu.cpi 4.753724 # CPI: Cycles Per Instruction +system.cpu.cpi_total 4.753724 # CPI: Total CPI of All Threads +system.cpu.ipc 0.210361 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.210361 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 10347 # number of integer regfile reads +system.cpu.int_regfile_writes 5013 # number of integer regfile writes system.cpu.fp_regfile_reads 3 # number of floating regfile reads system.cpu.fp_regfile_writes 1 # number of floating regfile writes -system.cpu.misc_regfile_reads 134 # number of misc regfile reads -system.cpu.icache.replacements 15 # number of replacements -system.cpu.icache.tagsinuse 158.750706 # Cycle average of tags in use -system.cpu.icache.total_refs 1129 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 329 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 3.431611 # Average number of references to valid blocks. +system.cpu.misc_regfile_reads 154 # number of misc regfile reads +system.cpu.icache.replacements 17 # number of replacements +system.cpu.icache.tagsinuse 161.262110 # Cycle average of tags in use +system.cpu.icache.total_refs 1367 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 336 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 4.068452 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 158.750706 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.077515 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 1129 # number of ReadReq hits -system.cpu.icache.demand_hits 1129 # number of demand (read+write) hits -system.cpu.icache.overall_hits 1129 # number of overall hits -system.cpu.icache.ReadReq_misses 402 # number of ReadReq misses -system.cpu.icache.demand_misses 402 # number of demand (read+write) misses -system.cpu.icache.overall_misses 402 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 14594000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 14594000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 14594000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 1531 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 1531 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 1531 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.262573 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.262573 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.262573 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 36303.482587 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 36303.482587 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 36303.482587 # average overall miss latency +system.cpu.icache.occ_blocks::0 161.262110 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.078741 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 1367 # number of ReadReq hits +system.cpu.icache.demand_hits 1367 # number of demand (read+write) hits +system.cpu.icache.overall_hits 1367 # number of overall hits +system.cpu.icache.ReadReq_misses 420 # number of ReadReq misses +system.cpu.icache.demand_misses 420 # number of demand (read+write) misses +system.cpu.icache.overall_misses 420 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 15216000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 15216000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 15216000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 1787 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 1787 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 1787 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.235031 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.235031 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.235031 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 36228.571429 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 36228.571429 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 36228.571429 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -323,59 +326,59 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 73 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 73 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 73 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 329 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 329 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 329 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_hits 84 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 84 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 84 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 336 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 336 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 336 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 11520500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 11520500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 11520500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 11782000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 11782000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 11782000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.214892 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.214892 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.214892 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 35016.717325 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 35016.717325 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 35016.717325 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate 0.188025 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.188025 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.188025 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 35065.476190 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 35065.476190 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 35065.476190 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 91.720291 # Cycle average of tags in use -system.cpu.dcache.total_refs 2249 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 141 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 15.950355 # Average number of references to valid blocks. +system.cpu.dcache.tagsinuse 92.136669 # Cycle average of tags in use +system.cpu.dcache.total_refs 2391 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 142 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 16.838028 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 91.720291 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.022393 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 1670 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 579 # number of WriteReq hits -system.cpu.dcache.demand_hits 2249 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 2249 # number of overall hits -system.cpu.dcache.ReadReq_misses 128 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 346 # number of WriteReq misses -system.cpu.dcache.demand_misses 474 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 474 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 4624500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 11828500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 16453000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 16453000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 1798 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.occ_blocks::0 92.136669 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.022494 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 1813 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 578 # number of WriteReq hits +system.cpu.dcache.demand_hits 2391 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 2391 # number of overall hits +system.cpu.dcache.ReadReq_misses 135 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 347 # number of WriteReq misses +system.cpu.dcache.demand_misses 482 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 482 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 4832000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 11507500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 16339500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 16339500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 1948 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 925 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 2723 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 2723 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.071190 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.374054 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.174073 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.174073 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 36128.906250 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 34186.416185 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 34710.970464 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 34710.970464 # average overall miss latency +system.cpu.dcache.demand_accesses 2873 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 2873 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.069302 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.375135 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate 0.167769 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.167769 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 35792.592593 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 33162.824207 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency 33899.377593 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 33899.377593 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -385,63 +388,63 @@ system.cpu.dcache.avg_blocked_cycles::no_targets no_value system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 38 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 295 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 333 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 333 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 90 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_hits 44 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 296 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits 340 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 340 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 91 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses 51 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 141 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 141 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_misses 142 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 142 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 3234500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 1846500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 5081000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 5081000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 3272000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 1836500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 5108500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 5108500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.050056 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate 0.046715 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate 0.055135 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.051781 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.051781 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35938.888889 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36205.882353 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 36035.460993 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 36035.460993 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate 0.049426 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.049426 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35956.043956 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36009.803922 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 35975.352113 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 35975.352113 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 218.141494 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 221.568003 # Cycle average of tags in use system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 416 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.007212 # Average number of references to valid blocks. +system.cpu.l2cache.sampled_refs 424 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.007075 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 218.141494 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.006657 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 221.568003 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.006762 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits 3 # number of ReadReq hits system.cpu.l2cache.demand_hits 3 # number of demand (read+write) hits system.cpu.l2cache.overall_hits 3 # number of overall hits -system.cpu.l2cache.ReadReq_misses 416 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses 424 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses 51 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 467 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 467 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 14276000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 1769000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 16045000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 16045000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 419 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.demand_misses 475 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 475 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 14561000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 1761000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 16322000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 16322000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 427 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses 51 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 470 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 470 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.992840 # miss rate for ReadReq accesses +system.cpu.l2cache.demand_accesses 478 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 478 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.992974 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.993617 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.993617 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34317.307692 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34686.274510 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34357.601713 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34357.601713 # average overall miss latency +system.cpu.l2cache.demand_miss_rate 0.993724 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.993724 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34341.981132 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34529.411765 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34362.105263 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34362.105263 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -453,24 +456,24 @@ system.cpu.l2cache.cache_copies 0 # nu system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 416 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses 424 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses 51 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 467 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 467 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses 475 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 475 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 12950000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 1606000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 14556000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 14556000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 13198500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 1599500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 14798000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 14798000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.992840 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.992974 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.993617 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.993617 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31129.807692 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31490.196078 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31169.164882 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31169.164882 # average overall mshr miss latency +system.cpu.l2cache.demand_mshr_miss_rate 0.993724 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.993724 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31128.537736 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31362.745098 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31153.684211 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31153.684211 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/quick/00.hello/ref/power/linux/o3-timing/config.ini b/tests/quick/00.hello/ref/power/linux/o3-timing/config.ini index 228222f47..a3775a1dd 100644 --- a/tests/quick/00.hello/ref/power/linux/o3-timing/config.ini +++ b/tests/quick/00.hello/ref/power/linux/o3-timing/config.ini @@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem mem_mode=atomic +memories=system.physmem physmem=system.physmem work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -499,7 +500,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/power/linux/hello +executable=/chips/pd/randd/dist/test-progs/hello/bin/power/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/00.hello/ref/power/linux/o3-timing/simerr b/tests/quick/00.hello/ref/power/linux/o3-timing/simerr index 7f3c6560c..e45cd058f 100755 --- a/tests/quick/00.hello/ref/power/linux/o3-timing/simerr +++ b/tests/quick/00.hello/ref/power/linux/o3-timing/simerr @@ -1,5 +1,2 @@ warn: Sockets disabled, not accepting gdb connections -For more information see: http://www.m5sim.org/warn/d946bea6 -warn: allowing mmap of file @ fd 34160904. This will break if not /dev/zero. -For more information see: http://www.m5sim.org/warn/3a2134f6 hack: be nice to actually delete the event here diff --git a/tests/quick/00.hello/ref/power/linux/o3-timing/simout b/tests/quick/00.hello/ref/power/linux/o3-timing/simout index cc20667bc..3b8650bce 100755 --- a/tests/quick/00.hello/ref/power/linux/o3-timing/simout +++ b/tests/quick/00.hello/ref/power/linux/o3-timing/simout @@ -1,15 +1,11 @@ -M5 Simulator System +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Apr 21 2011 13:26:57 -M5 started Apr 21 2011 13:27:10 -M5 executing on maize -command line: build/POWER_SE/m5.fast -d build/POWER_SE/tests/fast/quick/00.hello/power/linux/o3-timing -re tests/run.py build/POWER_SE/tests/fast/quick/00.hello/power/linux/o3-timing +gem5 compiled Jul 8 2011 15:06:16 +gem5 started Jul 8 2011 15:22:37 +gem5 executing on u200439-lin.austin.arm.com +command line: build/POWER_SE/gem5.opt -d build/POWER_SE/tests/opt/quick/00.hello/power/linux/o3-timing -re tests/run.py build/POWER_SE/tests/opt/quick/00.hello/power/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 11695000 because target called exit() +Exiting @ tick 11010500 because target called exit() diff --git a/tests/quick/00.hello/ref/power/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/power/linux/o3-timing/stats.txt index 082e541b8..d012d707f 100644 --- a/tests/quick/00.hello/ref/power/linux/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/power/linux/o3-timing/stats.txt @@ -1,480 +1,481 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 98738 # Simulator instruction rate (inst/s) -host_mem_usage 204672 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host -host_tick_rate 198408181 # Simulator tick rate (ticks/s) +sim_seconds 0.000011 # Number of seconds simulated +sim_ticks 11010500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 36368 # Simulator instruction rate (inst/s) +host_tick_rate 69032646 # Simulator tick rate (ticks/s) +host_mem_usage 241332 # Number of bytes of host memory used +host_seconds 0.16 # Real time elapsed on the host sim_insts 5800 # Number of instructions simulated -sim_seconds 0.000012 # Number of seconds simulated -sim_ticks 11695000 # Number of ticks simulated +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 9 # Number of system calls +system.cpu.numCycles 22022 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.BPredUnit.lookups 2367 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 1975 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 402 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 1913 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 680 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 679 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 1865 # Number of BTB lookups -system.cpu.BPredUnit.RASInCorrect 31 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 388 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 1734 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 2075 # Number of BP lookups -system.cpu.BPredUnit.usedRAS 187 # Number of times the RAS was used to get a target. -system.cpu.commit.branchMispredicts 240 # The number of times a branch was mispredicted -system.cpu.commit.branches 1038 # Number of branches committed -system.cpu.commit.bw_lim_events 42 # number cycles where commit BW limit reached -system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits +system.cpu.BPredUnit.usedRAS 189 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 30 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 6529 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 13348 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2367 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 869 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 2278 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1276 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 941 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.CacheLines 1754 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 281 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 10610 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.258058 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.653017 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 8332 78.53% 78.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 151 1.42% 79.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 185 1.74% 81.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 141 1.33% 83.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 226 2.13% 85.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 137 1.29% 86.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 283 2.67% 89.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 123 1.16% 90.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1032 9.73% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 10610 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.107483 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.606121 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 6699 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 1011 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2107 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 82 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 711 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 304 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 152 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 11818 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 428 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 711 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 6902 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 392 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 350 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 1977 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 278 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 11283 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 7 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 220 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 9842 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 18439 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 18368 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 71 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 5007 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 4835 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 25 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 25 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 566 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 1897 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1627 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 48 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 44 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 10258 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 69 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 8750 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 64 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 4202 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3778 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 53 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 10610 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.824694 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.535023 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 7338 69.16% 69.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1037 9.77% 78.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 771 7.27% 86.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 497 4.68% 90.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 457 4.31% 95.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 303 2.86% 98.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 135 1.27% 99.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 49 0.46% 99.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 23 0.22% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 10610 # Number of insts issued each cycle +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 10 6.45% 6.45% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 6.45% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 6.45% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.45% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.45% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.45% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 6.45% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.45% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 6.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 6.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.45% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 68 43.87% 50.32% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 77 49.68% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 5520 63.09% 63.09% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 63.09% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 63.09% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 63.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 63.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 63.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 63.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 63.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 63.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 63.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 63.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 63.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 63.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 63.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 63.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 63.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 63.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 63.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 63.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 63.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 63.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 63.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 63.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 63.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 63.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 63.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 63.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 63.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 63.11% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 1751 20.01% 83.12% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1477 16.88% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 8750 # Type of FU issued +system.cpu.iq.rate 0.397330 # Inst issue rate +system.cpu.iq.fu_busy_cnt 155 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.017714 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 28255 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 14489 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 8028 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 74 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 52 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 30 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 8867 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 38 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 79 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.squashedLoads 935 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 19 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 581 # Number of stores squashed +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewSquashCycles 711 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 186 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 23 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 10327 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 43 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 1897 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1627 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 60 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 14 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 19 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 62 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 239 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 301 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 8358 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1644 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 392 # Number of squashed instructions skipped in execute +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.exec_nop 0 # number of nop insts executed +system.cpu.iew.exec_refs 3035 # number of memory reference insts executed +system.cpu.iew.exec_branches 1315 # Number of branches executed +system.cpu.iew.exec_stores 1391 # Number of stores executed +system.cpu.iew.exec_rate 0.379530 # Inst execution rate +system.cpu.iew.wb_sent 8174 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 8058 # cumulative count of insts written-back +system.cpu.iew.wb_producers 4233 # num instructions producing a value +system.cpu.iew.wb_consumers 6765 # num instructions consuming a value +system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.wb_rate 0.365907 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.625721 # average fanout of values written-back +system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 5800 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 4533 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 16 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 3301 # The number of squashed insts skipped by commit -system.cpu.commit.committed_per_cycle::samples 10395 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.557961 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.275569 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 252 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 9899 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.585918 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.365203 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 7869 75.70% 75.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1103 10.61% 86.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 649 6.24% 92.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 257 2.47% 95.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 223 2.15% 97.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 132 1.27% 98.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 100 0.96% 99.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 20 0.19% 99.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 42 0.40% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 7502 75.79% 75.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 985 9.95% 85.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 645 6.52% 92.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 262 2.65% 94.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 188 1.90% 96.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 118 1.19% 97.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 77 0.78% 98.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 41 0.41% 99.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 81 0.82% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 10395 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 9899 # Number of insts commited each cycle system.cpu.commit.count 5800 # Number of instructions committed -system.cpu.commit.fp_insts 22 # Number of committed floating point instructions. -system.cpu.commit.function_calls 103 # Number of function calls committed. -system.cpu.commit.int_insts 5706 # Number of committed integer instructions. +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.refs 2008 # Number of memory references committed system.cpu.commit.loads 962 # Number of loads committed system.cpu.commit.membars 7 # Number of memory barriers committed -system.cpu.commit.refs 2008 # Number of memory references committed -system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.branches 1038 # Number of branches committed +system.cpu.commit.fp_insts 22 # Number of committed floating point instructions. +system.cpu.commit.int_insts 5706 # Number of committed integer instructions. +system.cpu.commit.function_calls 103 # Number of function calls committed. +system.cpu.commit.bw_lim_events 81 # number cycles where commit BW limit reached +system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits +system.cpu.rob.rob_reads 20151 # The number of ROB reads +system.cpu.rob.rob_writes 21378 # The number of ROB writes +system.cpu.timesIdled 216 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 11412 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5800 # Number of Instructions Simulated system.cpu.committedInsts_total 5800 # Number of Instructions Simulated -system.cpu.cpi 4.032931 # CPI: Cycles Per Instruction -system.cpu.cpi_total 4.032931 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 1431 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 33954.022989 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34464.285714 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 1344 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 2954000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.060797 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 87 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 31 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 1930000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.039133 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 56 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 1046 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 33770.226537 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36291.666667 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 737 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 10435000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.295411 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 309 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 261 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 1742000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.045889 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 48 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 20.009615 # Average number of references to valid blocks. -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 2477 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 33810.606061 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 35307.692308 # average overall mshr miss latency -system.cpu.dcache.demand_hits 2081 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 13389000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.159871 # miss rate for demand accesses -system.cpu.dcache.demand_misses 396 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 292 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 3672000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.041986 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 104 # number of demand (read+write) MSHR misses -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_blocks::0 66.459259 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.016225 # Average percentage of cache occupancy -system.cpu.dcache.overall_accesses 2477 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 33810.606061 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 35307.692308 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 2081 # number of overall hits -system.cpu.dcache.overall_miss_latency 13389000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.159871 # miss rate for overall accesses -system.cpu.dcache.overall_misses 396 # number of overall misses -system.cpu.dcache.overall_mshr_hits 292 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 3672000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.041986 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 104 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.sampled_refs 104 # Sample count of references to valid blocks. -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 66.459259 # Cycle average of tags in use -system.cpu.dcache.total_refs 2081 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.decode.BlockedCycles 887 # Number of cycles decode is blocked -system.cpu.decode.BranchMispred 151 # Number of times decode detected a branch misprediction -system.cpu.decode.BranchResolved 265 # Number of times decode resolved a branch -system.cpu.decode.DecodedInsts 10261 # Number of instructions handled by decode -system.cpu.decode.IdleCycles 7524 # Number of cycles decode is idle -system.cpu.decode.RunCycles 1914 # Number of cycles decode is running -system.cpu.decode.SquashCycles 549 # Number of cycles decode is squashing -system.cpu.decode.SquashedInsts 421 # Number of squashed instructions handled by decode -system.cpu.decode.UnblockCycles 70 # Number of cycles decode is unblocking -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.fetch.Branches 2075 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 1460 # Number of cache lines fetched -system.cpu.fetch.Cycles 2040 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 218 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 11548 # Number of instructions fetch has processed -system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.SquashCycles 402 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.088709 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 1460 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 866 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 0.493694 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 10944 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.055190 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.449465 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 8904 81.36% 81.36% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 156 1.43% 82.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 186 1.70% 84.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 150 1.37% 85.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 199 1.82% 87.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 133 1.22% 88.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 272 2.49% 91.37% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 75 0.69% 92.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 869 7.94% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 10944 # Number of instructions fetched each cycle (Total) -system.cpu.fp_regfile_reads 25 # number of floating regfile reads +system.cpu.cpi 3.796897 # CPI: Cycles Per Instruction +system.cpu.cpi_total 3.796897 # CPI: Total CPI of All Threads +system.cpu.ipc 0.263373 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.263373 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 13256 # number of integer regfile reads +system.cpu.int_regfile_writes 7085 # number of integer regfile writes +system.cpu.fp_regfile_reads 28 # number of floating regfile reads system.cpu.fp_regfile_writes 2 # number of floating regfile writes -system.cpu.icache.ReadReq_accesses 1460 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 36594.488189 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 34774.774775 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 1079 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 13942500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.260959 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 381 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 48 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 11580000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.228082 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 333 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 3.240240 # Average number of references to valid blocks. -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.replacements 0 # number of replacements +system.cpu.icache.tagsinuse 169.489368 # Cycle average of tags in use +system.cpu.icache.total_refs 1334 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 351 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 3.800570 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::0 169.489368 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.082758 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 1334 # number of ReadReq hits +system.cpu.icache.demand_hits 1334 # number of demand (read+write) hits +system.cpu.icache.overall_hits 1334 # number of overall hits +system.cpu.icache.ReadReq_misses 420 # number of ReadReq misses +system.cpu.icache.demand_misses 420 # number of demand (read+write) misses +system.cpu.icache.overall_misses 420 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 15114500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 15114500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 15114500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 1754 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 1754 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 1754 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.239453 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.239453 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.239453 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 35986.904762 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 35986.904762 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 35986.904762 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 1460 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 36594.488189 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 34774.774775 # average overall mshr miss latency -system.cpu.icache.demand_hits 1079 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 13942500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.260959 # miss rate for demand accesses -system.cpu.icache.demand_misses 381 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 48 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 11580000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.228082 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 333 # number of demand (read+write) MSHR misses +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_blocks::0 161.104076 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.078664 # Average percentage of cache occupancy -system.cpu.icache.overall_accesses 1460 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 36594.488189 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 34774.774775 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 1079 # number of overall hits -system.cpu.icache.overall_miss_latency 13942500 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.260959 # miss rate for overall accesses -system.cpu.icache.overall_misses 381 # number of overall misses -system.cpu.icache.overall_mshr_hits 48 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 11580000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.228082 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 333 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.writebacks 0 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits 69 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 69 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 69 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 351 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 351 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 351 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.sampled_refs 333 # Sample count of references to valid blocks. +system.cpu.icache.ReadReq_mshr_miss_latency 12207500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 12207500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 12207500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.200114 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.200114 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.200114 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 34779.202279 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 34779.202279 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 34779.202279 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 161.104076 # Cycle average of tags in use -system.cpu.icache.total_refs 1079 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 12447 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.branchMispredicts 279 # Number of branch mispredicts detected at execute -system.cpu.iew.exec_branches 1262 # Number of branches executed -system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_rate 0.332008 # Inst execution rate -system.cpu.iew.exec_refs 2790 # number of memory reference insts executed -system.cpu.iew.exec_stores 1305 # Number of stores executed -system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.iewBlockCycles 130 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 1666 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 14 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 100 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 1436 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 9097 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 1485 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 289 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 7766 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 4 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 549 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 12 # Number of cycles IEW is unblocking -system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread0.forwLoads 29 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread0.memOrderViolation 13 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.squashedLoads 704 # Number of loads squashed -system.cpu.iew.lsq.thread0.squashedStores 390 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 13 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 202 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 77 # Number of branches that were predicted taken incorrectly -system.cpu.iew.wb_consumers 5916 # num instructions consuming a value -system.cpu.iew.wb_count 7563 # cumulative count of insts written-back -system.cpu.iew.wb_fanout 0.645030 # average fanout of values written-back -system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.wb_producers 3816 # num instructions producing a value -system.cpu.iew.wb_rate 0.323329 # insts written-back per cycle -system.cpu.iew.wb_sent 7623 # cumulative count of insts sent to commit -system.cpu.int_regfile_reads 12407 # number of integer regfile reads -system.cpu.int_regfile_writes 6585 # number of integer regfile writes -system.cpu.ipc 0.247959 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.247959 # IPC: Total IPC of All Threads -system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5116 63.51% 63.51% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 63.51% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 63.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 63.54% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 63.54% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 63.54% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 63.54% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 63.54% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 63.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 63.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 63.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 63.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 63.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 63.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 63.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 63.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 63.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 63.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 63.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 63.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 63.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 63.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 63.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 63.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 63.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 63.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 63.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 63.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 63.54% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1580 19.62% 83.15% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1357 16.85% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8055 # Type of FU issued -system.cpu.iq.fp_alu_accesses 31 # Number of floating point alu accesses -system.cpu.iq.fp_inst_queue_reads 59 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_wakeup_accesses 27 # Number of floating instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_writes 36 # Number of floating instruction queue writes -system.cpu.iq.fu_busy_cnt 152 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.018870 # FU busy rate (busy events/executed inst) -system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 11 7.24% 7.24% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 7.24% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 7.24% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.24% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.24% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.24% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 7.24% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.24% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 7.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 7.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 7.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 7.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 7.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 7.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 7.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 7.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 7.24% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 72 47.37% 54.61% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 69 45.39% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.int_alu_accesses 8176 # Number of integer alu accesses -system.cpu.iq.int_inst_queue_reads 27162 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_wakeup_accesses 7536 # Number of integer instruction queue wakeup accesses -system.cpu.iq.int_inst_queue_writes 11998 # Number of integer instruction queue writes -system.cpu.iq.iqInstsAdded 9075 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 8055 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 22 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 2924 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 15 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 6 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 2633 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.issued_per_cycle::samples 10944 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.736020 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.423307 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 7700 70.36% 70.36% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1176 10.75% 81.10% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 793 7.25% 88.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 485 4.43% 92.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 365 3.34% 96.12% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 233 2.13% 98.25% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 138 1.26% 99.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 47 0.43% 99.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 7 0.06% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 10944 # Number of insts issued each cycle -system.cpu.iq.rate 0.344363 # Inst issue rate -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 0 # number of replacements +system.cpu.dcache.tagsinuse 66.389041 # Cycle average of tags in use +system.cpu.dcache.total_refs 2180 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 105 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 20.761905 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 66.389041 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.016208 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 1445 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 735 # number of WriteReq hits +system.cpu.dcache.demand_hits 2180 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 2180 # number of overall hits +system.cpu.dcache.ReadReq_misses 90 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 311 # number of WriteReq misses +system.cpu.dcache.demand_misses 401 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 401 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 3011000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 10558500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 13569500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 13569500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 1535 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses 1046 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses 2581 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 2581 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.058632 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.297323 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate 0.155366 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.155366 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 33455.555556 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 33950.160772 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency 33839.152120 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 33839.152120 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks 0 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 33 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 263 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits 296 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 296 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 57 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 48 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses 105 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 105 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.ReadReq_mshr_miss_latency 1963500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 1750500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 3714000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 3714000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.037134 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate 0.045889 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate 0.040682 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.040682 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34447.368421 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36468.750000 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 35371.428571 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 35371.428571 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.replacements 0 # number of replacements +system.cpu.l2cache.tagsinuse 200.598447 # Cycle average of tags in use +system.cpu.l2cache.total_refs 9 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 399 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.022556 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::0 200.598447 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.006122 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 9 # number of ReadReq hits +system.cpu.l2cache.demand_hits 9 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 9 # number of overall hits +system.cpu.l2cache.ReadReq_misses 399 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses 48 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 447 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 447 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 13714000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 1678000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 15392000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 15392000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 408 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses 48 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 34937.500000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31770.833333 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 1677000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_accesses 456 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 456 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.977941 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 48 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 1525000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 48 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 389 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34322.834646 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31146.981627 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 8 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 13077000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.979434 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 381 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 11867000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.979434 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 381 # number of ReadReq MSHR misses -system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.020997 # Average number of references to valid blocks. -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.demand_miss_rate 0.980263 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.980263 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34370.927318 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34958.333333 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34434.004474 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34434.004474 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 437 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34391.608392 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31216.783217 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 8 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 14754000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.981693 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 429 # number of demand (read+write) misses +system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 13392000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.981693 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 429 # number of demand (read+write) MSHR misses -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_blocks::0 191.979751 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.005859 # Average percentage of cache occupancy -system.cpu.l2cache.overall_accesses 437 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34391.608392 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31216.783217 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 8 # number of overall hits -system.cpu.l2cache.overall_miss_latency 14754000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.981693 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 429 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 13392000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.981693 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 429 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_misses 399 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses 48 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses 447 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 447 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 381 # Sample count of references to valid blocks. +system.cpu.l2cache.ReadReq_mshr_miss_latency 12433500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 1526000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 13959500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 13959500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.977941 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate 0.980263 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.980263 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31161.654135 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31791.666667 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31229.306488 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31229.306488 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 191.979751 # Cycle average of tags in use -system.cpu.l2cache.total_refs 8 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.memDep0.conflictingLoads 48 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 28 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 1666 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1436 # Number of stores inserted to the mem dependence unit. -system.cpu.numCycles 23391 # number of cpu cycles simulated -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.rename.BlockCycles 314 # Number of cycles rename is blocking -system.cpu.rename.CommittedMaps 5007 # Number of HB maps that are committed -system.cpu.rename.IQFullEvents 7 # Number of times rename has blocked due to IQ full -system.cpu.rename.IdleCycles 7703 # Number of cycles rename is idle -system.cpu.rename.LSQFullEvents 194 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenameLookups 16001 # Number of register rename lookups that rename has made -system.cpu.rename.RenamedInsts 9789 # Number of instructions processed by rename -system.cpu.rename.RenamedOperands 8584 # Number of destination operands rename has renamed -system.cpu.rename.RunCycles 1797 # Number of cycles rename is running -system.cpu.rename.SquashCycles 549 # Number of cycles rename is squashing -system.cpu.rename.UnblockCycles 244 # Number of cycles rename is unblocking -system.cpu.rename.UndoneMaps 3577 # Number of HB maps that are undone due to squashing -system.cpu.rename.fp_rename_lookups 55 # Number of floating rename lookups -system.cpu.rename.int_rename_lookups 15946 # Number of integer rename lookups -system.cpu.rename.serializeStallCycles 337 # count of cycles rename stalled for serializing inst -system.cpu.rename.serializingInsts 22 # count of serializing insts renamed -system.cpu.rename.skidInsts 471 # count of insts added to the skid buffer -system.cpu.rename.tempSerializingInsts 22 # count of temporary serializing insts renamed -system.cpu.rob.rob_reads 19454 # The number of ROB reads -system.cpu.rob.rob_writes 18753 # The number of ROB writes -system.cpu.timesIdled 229 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.workload.num_syscalls 9 # Number of system calls +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/sparc/linux/inorder-timing/config.ini b/tests/quick/00.hello/ref/sparc/linux/inorder-timing/config.ini index 37073b2df..f7a4ddc40 100644 --- a/tests/quick/00.hello/ref/sparc/linux/inorder-timing/config.ini +++ b/tests/quick/00.hello/ref/sparc/linux/inorder-timing/config.ini @@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem mem_mode=atomic +memories=system.physmem physmem=system.physmem work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -204,7 +205,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/hello/bin/sparc/linux/hello +executable=/arm/scratch/sysexplr/dist/test-progs/hello/bin/sparc/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/00.hello/ref/sparc/linux/inorder-timing/simout b/tests/quick/00.hello/ref/sparc/linux/inorder-timing/simout index ca819dade..002338518 100755 --- a/tests/quick/00.hello/ref/sparc/linux/inorder-timing/simout +++ b/tests/quick/00.hello/ref/sparc/linux/inorder-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 20 2011 19:27:12 -gem5 started Jun 20 2011 19:28:17 -gem5 executing on zooks +gem5 compiled Jul 9 2011 14:58:11 +gem5 started Jul 9 2011 15:02:19 +gem5 executing on nadc-0321 command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/quick/00.hello/sparc/linux/inorder-timing -re tests/run.py build/SPARC_SE/tests/opt/quick/00.hello/sparc/linux/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... -Hello World!Exiting @ tick 18208500 because target called exit() +Hello World!Exiting @ tick 18201500 because target called exit() diff --git a/tests/quick/00.hello/ref/sparc/linux/inorder-timing/stats.txt b/tests/quick/00.hello/ref/sparc/linux/inorder-timing/stats.txt index 50ad2ecd7..1b5682411 100644 --- a/tests/quick/00.hello/ref/sparc/linux/inorder-timing/stats.txt +++ b/tests/quick/00.hello/ref/sparc/linux/inorder-timing/stats.txt @@ -1,24 +1,24 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000018 # Number of seconds simulated -sim_ticks 18208500 # Number of ticks simulated +sim_ticks 18201500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 40053 # Simulator instruction rate (inst/s) -host_tick_rate 136538838 # Simulator tick rate (ticks/s) -host_mem_usage 158968 # Number of bytes of host memory used -host_seconds 0.13 # Real time elapsed on the host +host_inst_rate 63270 # Simulator instruction rate (inst/s) +host_tick_rate 215616708 # Simulator tick rate (ticks/s) +host_mem_usage 249768 # Number of bytes of host memory used +host_seconds 0.08 # Real time elapsed on the host sim_insts 5340 # Number of instructions simulated system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.numCycles 36418 # number of cpu cycles simulated +system.cpu.numCycles 36404 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 9732 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 9720 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode system.cpu.timesIdled 421 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 30132 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 6286 # Number of cycles cpu stages are processed. -system.cpu.activity 17.260695 # Percentage of cycles cpu is active +system.cpu.idleCycles 30130 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 6274 # Number of cycles cpu stages are processed. +system.cpu.activity 17.234370 # Percentage of cycles cpu is active system.cpu.comLoads 716 # Number of Load instructions committed system.cpu.comStores 673 # Number of Store instructions committed system.cpu.comBranches 1116 # Number of Branches instructions committed @@ -29,79 +29,79 @@ system.cpu.comFloats 0 # Nu system.cpu.committedInsts 5340 # Number of Instructions Simulated (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread) system.cpu.committedInsts_total 5340 # Number of Instructions Simulated (Total) -system.cpu.cpi 6.819850 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 6.817228 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi no_value # CPI: Total SMT-CPI -system.cpu.cpi_total 6.819850 # CPI: Total CPI of All Threads -system.cpu.ipc 0.146631 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 6.817228 # CPI: Total CPI of All Threads +system.cpu.ipc 0.146687 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc no_value # IPC: Total SMT-IPC -system.cpu.ipc_total 0.146631 # IPC: Total IPC of All Threads -system.cpu.branch_predictor.lookups 1667 # Number of BP lookups -system.cpu.branch_predictor.condPredicted 1128 # Number of conditional branches predicted -system.cpu.branch_predictor.condIncorrect 904 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 1481 # Number of BTB lookups -system.cpu.branch_predictor.BTBHits 657 # Number of BTB hits +system.cpu.ipc_total 0.146687 # IPC: Total IPC of All Threads +system.cpu.branch_predictor.lookups 1662 # Number of BP lookups +system.cpu.branch_predictor.condPredicted 1123 # Number of conditional branches predicted +system.cpu.branch_predictor.condIncorrect 899 # Number of conditional branches incorrect +system.cpu.branch_predictor.BTBLookups 1455 # Number of BTB lookups +system.cpu.branch_predictor.BTBHits 643 # Number of BTB hits system.cpu.branch_predictor.usedRAS 67 # Number of times the RAS was used to get a target. system.cpu.branch_predictor.RASInCorrect 4 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 44.361918 # BTB Hit Percentage -system.cpu.branch_predictor.predictedTaken 724 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 943 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 5610 # Number of Reads from Int. Register File +system.cpu.branch_predictor.BTBHitPct 44.192440 # BTB Hit Percentage +system.cpu.branch_predictor.predictedTaken 710 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 952 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 5612 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 4000 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 9610 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.intRegFileAccesses 9612 # Total Accesses (Read+Write) to the Int. Register File system.cpu.regfile_manager.floatRegFileReads 0 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 0 # Number of Writes to FP Register File system.cpu.regfile_manager.floatRegFileAccesses 0 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 1749 # Number of Registers Read Through Forwarding Logic +system.cpu.regfile_manager.regForwards 1747 # Number of Registers Read Through Forwarding Logic system.cpu.agen_unit.agens 1473 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 407 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 434 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 841 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 275 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 75.358423 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 3970 # Number of Instructions Executed. +system.cpu.execution_unit.predictedTakenIncorrect 394 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 442 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 836 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 280 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 74.910394 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 3977 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 0 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed -system.cpu.stage0.idleCycles 31732 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 4686 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 12.867263 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 33196 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 3222 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 8.847273 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 33369 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 3049 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 8.372234 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 35435 # Number of cycles 0 instructions are processed. +system.cpu.stage0.idleCycles 31738 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 4666 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 12.817273 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 33193 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 3211 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 8.820459 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 33357 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 3047 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 8.369959 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 35421 # Number of cycles 0 instructions are processed. system.cpu.stage3.runCycles 983 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 2.699215 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 33245 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 3173 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 8.712724 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.utilization 2.700253 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 33233 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 3171 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 8.710581 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 136.664121 # Cycle average of tags in use +system.cpu.icache.tagsinuse 136.669321 # Cycle average of tags in use system.cpu.icache.total_refs 791 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 291 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 2.718213 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 136.664121 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.066731 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 136.669321 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.066733 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits 791 # number of ReadReq hits system.cpu.icache.demand_hits 791 # number of demand (read+write) hits system.cpu.icache.overall_hits 791 # number of overall hits system.cpu.icache.ReadReq_misses 347 # number of ReadReq misses system.cpu.icache.demand_misses 347 # number of demand (read+write) misses system.cpu.icache.overall_misses 347 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 19112000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 19112000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 19112000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency 19110500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 19110500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 19110500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses 1138 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses 1138 # number of demand (read+write) accesses system.cpu.icache.overall_accesses 1138 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate 0.304921 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate 0.304921 # miss rate for demand accesses system.cpu.icache.overall_miss_rate 0.304921 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 55077.809798 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 55077.809798 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 55077.809798 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency 55073.487032 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 55073.487032 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 55073.487032 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 104500 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -118,28 +118,28 @@ system.cpu.icache.ReadReq_mshr_misses 291 # nu system.cpu.icache.demand_mshr_misses 291 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses 291 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 15471500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 15471500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 15471500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 15470000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 15470000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 15470000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.255712 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate 0.255712 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate 0.255712 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 53166.666667 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 53166.666667 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 53166.666667 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 53161.512027 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 53161.512027 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 53161.512027 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 82.862842 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 82.859932 # Cycle average of tags in use system.cpu.dcache.total_refs 1049 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 135 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 7.770370 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 82.862842 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.020230 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 82.859932 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.020229 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits 657 # number of ReadReq hits system.cpu.dcache.WriteReq_hits 392 # number of WriteReq hits system.cpu.dcache.demand_hits 1049 # number of demand (read+write) hits @@ -200,12 +200,12 @@ system.cpu.dcache.mshr_cap_events 0 # nu system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 162.289874 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 162.297266 # Cycle average of tags in use system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 342 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.008772 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 162.289874 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::0 162.297266 # Average occupied blocks per context system.cpu.l2cache.occ_percent::0 0.004953 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits 3 # number of ReadReq hits system.cpu.l2cache.demand_hits 3 # number of demand (read+write) hits @@ -214,10 +214,10 @@ system.cpu.l2cache.ReadReq_misses 342 # nu system.cpu.l2cache.ReadExReq_misses 81 # number of ReadExReq misses system.cpu.l2cache.demand_misses 423 # number of demand (read+write) misses system.cpu.l2cache.overall_misses 423 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 17920000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 17918500 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency 4230500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 22150500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 22150500 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency 22149000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 22149000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses 345 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses 81 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses 426 # number of demand (read+write) accesses @@ -226,10 +226,10 @@ system.cpu.l2cache.ReadReq_miss_rate 0.991304 # mi system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate 0.992958 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate 0.992958 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 52397.660819 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 52393.274854 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency 52228.395062 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 52365.248227 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 52365.248227 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency 52361.702128 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 52361.702128 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked diff --git a/tests/quick/00.hello/ref/x86/linux/o3-timing/config.ini b/tests/quick/00.hello/ref/x86/linux/o3-timing/config.ini index cd8df9d09..7ab760d62 100644 --- a/tests/quick/00.hello/ref/x86/linux/o3-timing/config.ini +++ b/tests/quick/00.hello/ref/x86/linux/o3-timing/config.ini @@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem mem_mode=atomic +memories=system.physmem physmem=system.physmem work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -498,7 +499,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/x86/linux/hello +executable=/chips/pd/randd/dist/test-progs/hello/bin/x86/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/00.hello/ref/x86/linux/o3-timing/simout b/tests/quick/00.hello/ref/x86/linux/o3-timing/simout index 5486afb8d..e361952bb 100755 --- a/tests/quick/00.hello/ref/x86/linux/o3-timing/simout +++ b/tests/quick/00.hello/ref/x86/linux/o3-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 27 2011 02:06:34 -gem5 started Jun 27 2011 02:06:35 -gem5 executing on burrito -command line: build/X86_SE/gem5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/fast/quick/00.hello/x86/linux/o3-timing +gem5 compiled Jul 8 2011 15:18:15 +gem5 started Jul 8 2011 15:23:04 +gem5 executing on u200439-lin.austin.arm.com +command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/quick/00.hello/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/quick/00.hello/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 11369000 because target called exit() +Exiting @ tick 11102000 because target called exit() diff --git a/tests/quick/00.hello/ref/x86/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/x86/linux/o3-timing/stats.txt index aabbd6e7a..a1f123e22 100644 --- a/tests/quick/00.hello/ref/x86/linux/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/x86/linux/o3-timing/stats.txt @@ -1,249 +1,251 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000011 # Number of seconds simulated -sim_ticks 11369000 # Number of ticks simulated +sim_ticks 11102000 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 90859 # Simulator instruction rate (inst/s) -host_tick_rate 105280911 # Simulator tick rate (ticks/s) -host_mem_usage 225572 # Number of bytes of host memory used -host_seconds 0.11 # Real time elapsed on the host +host_inst_rate 58378 # Simulator instruction rate (inst/s) +host_tick_rate 66066423 # Simulator tick rate (ticks/s) +host_mem_usage 248304 # Number of bytes of host memory used +host_seconds 0.17 # Real time elapsed on the host sim_insts 9809 # Number of instructions simulated system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.numCycles 22739 # number of cpu cycles simulated +system.cpu.numCycles 22205 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 2757 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 2757 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 485 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 2530 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 929 # Number of BTB hits +system.cpu.BPredUnit.lookups 3070 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 3070 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 497 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 2745 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 1002 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 1700 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 12836 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2757 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 929 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 3597 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 497 # Number of cycles fetch has spent squashing +system.cpu.fetch.icacheStallCycles 5900 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 14062 # Number of instructions fetch has processed +system.cpu.fetch.Branches 3070 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 1002 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 3986 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2234 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 1500 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.CacheLines 1700 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 237 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 13282 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.734377 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.109101 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.PendingTrapStallCycles 9 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 1900 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 273 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 13123 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.933552 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.219407 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 9775 73.60% 73.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 168 1.26% 74.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 126 0.95% 75.81% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 226 1.70% 77.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 192 1.45% 78.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 168 1.26% 80.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 259 1.95% 82.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 168 1.26% 83.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 2200 16.56% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 9243 70.43% 70.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 169 1.29% 71.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 176 1.34% 73.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 241 1.84% 74.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 234 1.78% 76.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 195 1.49% 78.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 280 2.13% 80.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 141 1.07% 81.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 2444 18.62% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 13282 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.121245 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.564493 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 7076 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 1369 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 3285 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 77 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1475 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 22079 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 1475 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 7317 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 565 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 440 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 3105 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 380 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 21002 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 3 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 52 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 248 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 19737 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 44285 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 44269 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 13123 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.138257 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.633281 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 6251 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 1454 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 3582 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 112 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1724 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 24194 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 1724 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 6540 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 523 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 524 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 3382 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 430 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 22801 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 2 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 68 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 271 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 21341 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 47863 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 47847 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 16 # Number of floating rename lookups system.cpu.rename.CommittedMaps 9368 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 10369 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 32 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 31 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 1483 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2081 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1618 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 14 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 3 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 18991 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 33 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 16049 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 54 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 8636 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 10887 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 20 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 13282 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.208327 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.917321 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 11973 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 33 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 33 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 1611 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2253 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1786 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 13 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 5 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 20643 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 35 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 17013 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 65 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 10307 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 13151 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 22 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 13123 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.296426 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.004622 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 8198 61.72% 61.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1295 9.75% 71.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 980 7.38% 78.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 727 5.47% 84.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 779 5.87% 90.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 582 4.38% 94.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 507 3.82% 98.39% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 167 1.26% 99.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 47 0.35% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 8026 61.16% 61.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1107 8.44% 69.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 1007 7.67% 77.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 730 5.56% 82.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 676 5.15% 87.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 728 5.55% 93.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 620 4.72% 98.25% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 194 1.48% 99.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 35 0.27% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 13282 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 13123 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 101 68.71% 68.71% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 68.71% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 68.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 68.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 68.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 68.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 68.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 68.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 68.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 68.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 68.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 68.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 68.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 68.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 68.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 68.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 68.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 68.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 68.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 68.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 68.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 68.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 68.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 68.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 68.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 68.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 68.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 68.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 68.71% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 27 18.37% 87.07% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 19 12.93% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 95 66.90% 66.90% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 66.90% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 66.90% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 66.90% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 66.90% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 66.90% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 66.90% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 66.90% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 66.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 66.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 66.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 66.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 66.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 66.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 66.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 66.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 66.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 66.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 66.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 66.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 66.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 66.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 66.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 66.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.90% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 24 16.90% 83.80% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 23 16.20% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 4 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 12887 80.30% 80.32% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 80.32% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 80.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.32% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1771 11.03% 91.36% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1387 8.64% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 13681 80.41% 80.44% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 80.44% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 80.44% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.44% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.44% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.44% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.44% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.44% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.44% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 1854 10.90% 91.34% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1474 8.66% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 16049 # Type of FU issued -system.cpu.iq.rate 0.705792 # Inst issue rate -system.cpu.iq.fu_busy_cnt 147 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.009159 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 45572 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 27668 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 15040 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 9 # Number of floating instruction queue reads +system.cpu.iq.FU_type_0::total 17013 # Type of FU issued +system.cpu.iq.rate 0.766179 # Inst issue rate +system.cpu.iq.fu_busy_cnt 142 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.008347 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 47348 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 30994 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 15803 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 4 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 4 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 16187 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 5 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 69 # Number of loads that had data forwarded from stores +system.cpu.iq.int_alu_accesses 17147 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 4 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 80 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1025 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 12 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.squashedLoads 1197 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 13 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 14 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 684 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 852 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1475 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 187 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 20 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 19024 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 215 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2081 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1618 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 33 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 12 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 1724 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 144 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 16 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 20678 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 15 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2253 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1786 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 35 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 6 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 14 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 69 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 498 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 567 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 15360 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1657 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 689 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 66 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 524 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 590 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 16148 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1748 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 865 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 2952 # number of memory reference insts executed -system.cpu.iew.exec_branches 1546 # Number of branches executed -system.cpu.iew.exec_stores 1295 # Number of stores executed -system.cpu.iew.exec_rate 0.675491 # Inst execution rate -system.cpu.iew.wb_sent 15177 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 15044 # cumulative count of insts written-back -system.cpu.iew.wb_producers 9950 # num instructions producing a value -system.cpu.iew.wb_consumers 14675 # num instructions consuming a value +system.cpu.iew.exec_refs 3114 # number of memory reference insts executed +system.cpu.iew.exec_branches 1606 # Number of branches executed +system.cpu.iew.exec_stores 1366 # Number of stores executed +system.cpu.iew.exec_rate 0.727224 # Inst execution rate +system.cpu.iew.wb_sent 15964 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 15807 # cumulative count of insts written-back +system.cpu.iew.wb_producers 10570 # num instructions producing a value +system.cpu.iew.wb_consumers 15744 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.661595 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.678024 # average fanout of values written-back +system.cpu.iew.wb_rate 0.711867 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.671367 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 9809 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 9214 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 10868 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 13 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 485 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 11807 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.830778 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.597683 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 497 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 11399 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.860514 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.681683 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 8187 69.34% 69.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1225 10.38% 79.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 582 4.93% 84.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 958 8.11% 92.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 396 3.35% 96.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 132 1.12% 97.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 128 1.08% 98.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 58 0.49% 98.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 141 1.19% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 7958 69.81% 69.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1091 9.57% 79.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 577 5.06% 84.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 889 7.80% 92.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 346 3.04% 95.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 149 1.31% 96.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 139 1.22% 97.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 66 0.58% 98.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 184 1.61% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 11807 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 11399 # Number of insts commited each cycle system.cpu.commit.count 9809 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 1990 # Number of memory references committed @@ -253,48 +255,48 @@ system.cpu.commit.branches 1214 # Nu system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.int_insts 9714 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 141 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 184 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 30689 # The number of ROB reads -system.cpu.rob.rob_writes 39546 # The number of ROB writes -system.cpu.timesIdled 184 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 9457 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 31892 # The number of ROB reads +system.cpu.rob.rob_writes 43113 # The number of ROB writes +system.cpu.timesIdled 182 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 9082 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 9809 # Number of Instructions Simulated system.cpu.committedInsts_total 9809 # Number of Instructions Simulated -system.cpu.cpi 2.318177 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.318177 # CPI: Total CPI of All Threads -system.cpu.ipc 0.431373 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.431373 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 22959 # number of integer regfile reads -system.cpu.int_regfile_writes 13989 # number of integer regfile writes +system.cpu.cpi 2.263737 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.263737 # CPI: Total CPI of All Threads +system.cpu.ipc 0.441747 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.441747 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 23720 # number of integer regfile reads +system.cpu.int_regfile_writes 14686 # number of integer regfile writes system.cpu.fp_regfile_reads 4 # number of floating regfile reads -system.cpu.misc_regfile_reads 6812 # number of misc regfile reads +system.cpu.misc_regfile_reads 7234 # number of misc regfile reads system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 144.881621 # Cycle average of tags in use -system.cpu.icache.total_refs 1339 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 295 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 4.538983 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 145.121253 # Cycle average of tags in use +system.cpu.icache.total_refs 1536 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 298 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 5.154362 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 144.881621 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.070743 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 1339 # number of ReadReq hits -system.cpu.icache.demand_hits 1339 # number of demand (read+write) hits -system.cpu.icache.overall_hits 1339 # number of overall hits -system.cpu.icache.ReadReq_misses 361 # number of ReadReq misses -system.cpu.icache.demand_misses 361 # number of demand (read+write) misses -system.cpu.icache.overall_misses 361 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 13205500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 13205500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 13205500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 1700 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 1700 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 1700 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.212353 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.212353 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.212353 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 36580.332410 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 36580.332410 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 36580.332410 # average overall miss latency +system.cpu.icache.occ_blocks::0 145.121253 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.070860 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 1536 # number of ReadReq hits +system.cpu.icache.demand_hits 1536 # number of demand (read+write) hits +system.cpu.icache.overall_hits 1536 # number of overall hits +system.cpu.icache.ReadReq_misses 364 # number of ReadReq misses +system.cpu.icache.demand_misses 364 # number of demand (read+write) misses +system.cpu.icache.overall_misses 364 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 13311000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 13311000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 13311000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 1900 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 1900 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 1900 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.191579 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.191579 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.191579 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 36568.681319 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 36568.681319 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 36568.681319 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -307,56 +309,56 @@ system.cpu.icache.writebacks 0 # nu system.cpu.icache.ReadReq_mshr_hits 66 # number of ReadReq MSHR hits system.cpu.icache.demand_mshr_hits 66 # number of demand (read+write) MSHR hits system.cpu.icache.overall_mshr_hits 66 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 295 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 295 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 295 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_misses 298 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 298 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 298 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 10355500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 10355500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 10355500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 10465000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 10465000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 10465000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.173529 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.173529 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.173529 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 35103.389831 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 35103.389831 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 35103.389831 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate 0.156842 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.156842 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.156842 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 35117.449664 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 35117.449664 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 35117.449664 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 85.872025 # Cycle average of tags in use -system.cpu.dcache.total_refs 2039 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 143 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 14.258741 # Average number of references to valid blocks. +system.cpu.dcache.tagsinuse 85.500276 # Cycle average of tags in use +system.cpu.dcache.total_refs 2118 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 145 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 14.606897 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 85.872025 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.020965 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 1418 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 621 # number of WriteReq hits -system.cpu.dcache.demand_hits 2039 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 2039 # number of overall hits +system.cpu.dcache.occ_blocks::0 85.500276 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.020874 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 1500 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 618 # number of WriteReq hits +system.cpu.dcache.demand_hits 2118 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 2118 # number of overall hits system.cpu.dcache.ReadReq_misses 113 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 313 # number of WriteReq misses -system.cpu.dcache.demand_misses 426 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 426 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 3899000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 10668500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 14567500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 14567500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 1531 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_misses 316 # number of WriteReq misses +system.cpu.dcache.demand_misses 429 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 429 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 3938500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 10704500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 14643000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 14643000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 1613 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 934 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 2465 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 2465 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.073808 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.335118 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.172819 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.172819 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 34504.424779 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 34084.664537 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 34196.009390 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 34196.009390 # average overall miss latency +system.cpu.dcache.demand_accesses 2547 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 2547 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.070056 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.338330 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate 0.168433 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.168433 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 34853.982301 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 33875 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency 34132.867133 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 34132.867133 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -366,63 +368,63 @@ system.cpu.dcache.avg_blocked_cycles::no_targets no_value system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 46 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 236 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 282 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 282 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 67 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_hits 44 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 239 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits 283 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 283 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 69 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses 77 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 144 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 144 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_misses 146 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 146 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 2354500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 2772000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 5126500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 5126500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 2421500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 2762000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 5183500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 5183500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.043762 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate 0.042777 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate 0.082441 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.058418 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.058418 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35141.791045 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 35600.694444 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 35600.694444 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate 0.057322 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.057322 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35094.202899 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35870.129870 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 35503.424658 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 35503.424658 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 178.189347 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 178.583785 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 359 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.005571 # Average number of references to valid blocks. +system.cpu.l2cache.sampled_refs 364 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.005495 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 178.189347 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.005438 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 178.583785 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.005450 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits system.cpu.l2cache.overall_hits 2 # number of overall hits -system.cpu.l2cache.ReadReq_misses 360 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses 365 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses 77 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 437 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 437 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 12329000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 2664000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 14993000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 14993000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 362 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.demand_misses 442 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 442 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency 12493000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 2653500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 15146500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 15146500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 367 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses 77 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 439 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 439 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.994475 # miss rate for ReadReq accesses +system.cpu.l2cache.demand_accesses 444 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 444 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.994550 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.995444 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.995444 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34247.222222 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34597.402597 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34308.924485 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34308.924485 # average overall miss latency +system.cpu.l2cache.demand_miss_rate 0.995495 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.995495 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency 34227.397260 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34461.038961 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34268.099548 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34268.099548 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -434,24 +436,24 @@ system.cpu.l2cache.cache_copies 0 # nu system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 360 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses 365 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses 77 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 437 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 437 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses 442 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses 442 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 11174500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 2417500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 13592000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 13592000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 11328000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 2409500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 13737500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 13737500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.994475 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.994550 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.995444 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.995444 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31040.277778 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31396.103896 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31102.974828 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31102.974828 # average overall mshr miss latency +system.cpu.l2cache.demand_mshr_miss_rate 0.995495 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate 0.995495 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31035.616438 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31292.207792 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31080.316742 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31080.316742 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini index 2e792694f..62bbba21e 100644 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini @@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem mem_mode=atomic +memories=system.physmem physmem=system.physmem work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -498,7 +499,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello +executable=/chips/pd/randd/dist/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -517,7 +518,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello +executable=/chips/pd/randd/dist/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simerr b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simerr index eabe42249..e45cd058f 100755 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simerr +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simerr @@ -1,3 +1,2 @@ warn: Sockets disabled, not accepting gdb connections -For more information see: http://www.m5sim.org/warn/d946bea6 hack: be nice to actually delete the event here diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout index 5cdcc3460..f562f208e 100755 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout @@ -1,18 +1,14 @@ -M5 Simulator System +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. -Copyright (c) 2001-2008 -The Regents of The University of Michigan -All Rights Reserved - - -M5 compiled Apr 21 2011 12:29:56 -M5 started Apr 21 2011 13:15:44 -M5 executing on maize -command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/01.hello-2T-smt/alpha/linux/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/01.hello-2T-smt/alpha/linux/o3-timing +gem5 compiled Jul 8 2011 15:00:53 +gem5 started Jul 8 2011 15:21:20 +gem5 executing on u200439-lin.austin.arm.com +command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/quick/01.hello-2T-smt/alpha/linux/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/quick/01.hello-2T-smt/alpha/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. info: Increasing stack size by one page. Hello world! Hello world! -Exiting @ tick 14058000 because target called exit() +Exiting @ tick 13218000 because target called exit() diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt index fe96eb65d..ba1ddb358 100644 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt @@ -1,791 +1,790 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 78127 # Simulator instruction rate (inst/s) -host_mem_usage 207556 # Number of bytes of host memory used -host_seconds 0.16 # Real time elapsed on the host -host_tick_rate 85893759 # Simulator tick rate (ticks/s) +sim_seconds 0.000013 # Number of seconds simulated +sim_ticks 13218000 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 47211 # Simulator instruction rate (inst/s) +host_tick_rate 48851159 # Simulator tick rate (ticks/s) +host_mem_usage 244284 # Number of bytes of host memory used +host_seconds 0.27 # Real time elapsed on the host sim_insts 12773 # Number of instructions simulated -sim_seconds 0.000014 # Number of seconds simulated -sim_ticks 14058000 # Number of ticks simulated +system.cpu.dtb.fetch_hits 0 # ITB hits +system.cpu.dtb.fetch_misses 0 # ITB misses +system.cpu.dtb.fetch_acv 0 # ITB acv +system.cpu.dtb.fetch_accesses 0 # ITB accesses +system.cpu.dtb.read_hits 3714 # DTB read hits +system.cpu.dtb.read_misses 89 # DTB read misses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_accesses 3803 # DTB read accesses +system.cpu.dtb.write_hits 1992 # DTB write hits +system.cpu.dtb.write_misses 59 # DTB write misses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_accesses 2051 # DTB write accesses +system.cpu.dtb.data_hits 5706 # DTB hits +system.cpu.dtb.data_misses 148 # DTB misses +system.cpu.dtb.data_acv 0 # DTB access violations +system.cpu.dtb.data_accesses 5854 # DTB accesses +system.cpu.itb.fetch_hits 4085 # ITB hits +system.cpu.itb.fetch_misses 56 # ITB misses +system.cpu.itb.fetch_acv 0 # ITB acv +system.cpu.itb.fetch_accesses 4141 # ITB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_acv 0 # DTB read access violations +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_acv 0 # DTB write access violations +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.data_hits 0 # DTB hits +system.cpu.itb.data_misses 0 # DTB misses +system.cpu.itb.data_acv 0 # DTB access violations +system.cpu.itb.data_accesses 0 # DTB accesses +system.cpu.workload0.num_syscalls 17 # Number of system calls +system.cpu.workload1.num_syscalls 17 # Number of system calls +system.cpu.numCycles 26437 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.BPredUnit.lookups 5187 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 2958 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 1247 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 3609 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 1000 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 845 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 4555 # Number of BTB lookups -system.cpu.BPredUnit.RASInCorrect 177 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 1551 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 3023 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 5318 # Number of BP lookups -system.cpu.BPredUnit.usedRAS 660 # Number of times the RAS was used to get a target. -system.cpu.commit.branchMispredicts 1135 # The number of times a branch was mispredicted -system.cpu.commit.branches::0 1051 # Number of branches committed -system.cpu.commit.branches::1 1051 # Number of branches committed -system.cpu.commit.branches::total 2102 # Number of branches committed -system.cpu.commit.bw_lim_events 151 # number cycles where commit BW limit reached -system.cpu.commit.bw_limited::0 0 # number of insts not committed due to BW limits -system.cpu.commit.bw_limited::1 0 # number of insts not committed due to BW limits -system.cpu.commit.bw_limited::total 0 # number of insts not committed due to BW limits +system.cpu.BPredUnit.usedRAS 740 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 156 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 1108 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 29051 # Number of instructions fetch has processed +system.cpu.fetch.Branches 5187 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 1740 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 5000 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1319 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 44 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.CacheLines 4085 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 640 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 20361 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.426796 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.797497 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 15361 75.44% 75.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 451 2.22% 77.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 362 1.78% 79.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 388 1.91% 81.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 391 1.92% 83.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 325 1.60% 84.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 409 2.01% 86.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 323 1.59% 88.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 2351 11.55% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 20361 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.196202 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.098877 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 28250 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 5561 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 4330 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 453 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1870 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 485 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 311 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 25978 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 552 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1870 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 28803 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 2995 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 772 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 4141 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 1883 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 24541 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 11 # Number of times rename has blocked due to ROB full +system.cpu.rename.LSQFullEvents 1746 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 18357 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 30569 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 30535 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 34 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 9166 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 9191 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 52 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 40 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 4665 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2306 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1192 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. +system.cpu.memDep1.insertedLoads 2327 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep1.insertedStores 1184 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep1.conflictingLoads 3 # Number of conflicting loads. +system.cpu.memDep1.conflictingStores 0 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 22275 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 49 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 19420 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 71 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 8699 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 4701 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 15 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 20361 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.953784 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.476295 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 12146 59.65% 59.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 2930 14.39% 74.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 2237 10.99% 85.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 1382 6.79% 91.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 875 4.30% 96.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 479 2.35% 98.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 226 1.11% 99.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 69 0.34% 99.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 17 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 20361 # Number of insts issued each cycle +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 8 4.44% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.44% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 103 57.22% 61.67% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 69 38.33% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 6596 67.90% 67.92% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.93% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.93% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.95% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.95% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.95% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.95% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.95% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.95% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2046 21.06% 89.01% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1068 10.99% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 9715 # Type of FU issued +system.cpu.iq.FU_type_1::No_OpClass 2 0.02% 0.02% # Type of FU issued +system.cpu.iq.FU_type_1::IntAlu 6577 67.77% 67.79% # Type of FU issued +system.cpu.iq.FU_type_1::IntMult 1 0.01% 67.80% # Type of FU issued +system.cpu.iq.FU_type_1::IntDiv 0 0.00% 67.80% # Type of FU issued +system.cpu.iq.FU_type_1::FloatAdd 2 0.02% 67.82% # Type of FU issued +system.cpu.iq.FU_type_1::FloatCmp 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_1::FloatCvt 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_1::FloatMult 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_1::FloatDiv 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_1::FloatSqrt 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_1::SimdAdd 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_1::SimdAddAcc 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_1::SimdAlu 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_1::SimdCmp 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_1::SimdCvt 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_1::SimdMisc 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_1::SimdMult 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_1::SimdMultAcc 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_1::SimdShift 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_1::SimdShiftAcc 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_1::SimdSqrt 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatAdd 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatAlu 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatCmp 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatCvt 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatDiv 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatMisc 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatMult 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatMultAcc 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatSqrt 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_1::MemRead 2049 21.11% 88.93% # Type of FU issued +system.cpu.iq.FU_type_1::MemWrite 1074 11.07% 100.00% # Type of FU issued +system.cpu.iq.FU_type_1::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_1::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_1::total 9705 # Type of FU issued +system.cpu.iq.FU_type::No_OpClass 4 0.02% 0.02% # Type of FU issued +system.cpu.iq.FU_type::IntAlu 13173 67.83% 67.85% # Type of FU issued +system.cpu.iq.FU_type::IntMult 2 0.01% 67.86% # Type of FU issued +system.cpu.iq.FU_type::IntDiv 0 0.00% 67.86% # Type of FU issued +system.cpu.iq.FU_type::FloatAdd 4 0.02% 67.88% # Type of FU issued +system.cpu.iq.FU_type::FloatCmp 0 0.00% 67.88% # Type of FU issued +system.cpu.iq.FU_type::FloatCvt 0 0.00% 67.88% # Type of FU issued +system.cpu.iq.FU_type::FloatMult 0 0.00% 67.88% # Type of FU issued +system.cpu.iq.FU_type::FloatDiv 0 0.00% 67.88% # Type of FU issued +system.cpu.iq.FU_type::FloatSqrt 0 0.00% 67.88% # Type of FU issued +system.cpu.iq.FU_type::SimdAdd 0 0.00% 67.88% # Type of FU issued +system.cpu.iq.FU_type::SimdAddAcc 0 0.00% 67.88% # Type of FU issued +system.cpu.iq.FU_type::SimdAlu 0 0.00% 67.88% # Type of FU issued +system.cpu.iq.FU_type::SimdCmp 0 0.00% 67.88% # Type of FU issued +system.cpu.iq.FU_type::SimdCvt 0 0.00% 67.88% # Type of FU issued +system.cpu.iq.FU_type::SimdMisc 0 0.00% 67.88% # Type of FU issued +system.cpu.iq.FU_type::SimdMult 0 0.00% 67.88% # Type of FU issued +system.cpu.iq.FU_type::SimdMultAcc 0 0.00% 67.88% # Type of FU issued +system.cpu.iq.FU_type::SimdShift 0 0.00% 67.88% # Type of FU issued +system.cpu.iq.FU_type::SimdShiftAcc 0 0.00% 67.88% # Type of FU issued +system.cpu.iq.FU_type::SimdSqrt 0 0.00% 67.88% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatAdd 0 0.00% 67.88% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatAlu 0 0.00% 67.88% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatCmp 0 0.00% 67.88% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatCvt 0 0.00% 67.88% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatDiv 0 0.00% 67.88% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatMisc 0 0.00% 67.88% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatMult 0 0.00% 67.88% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatMultAcc 0 0.00% 67.88% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatSqrt 0 0.00% 67.88% # Type of FU issued +system.cpu.iq.FU_type::MemRead 4095 21.09% 88.97% # Type of FU issued +system.cpu.iq.FU_type::MemWrite 2142 11.03% 100.00% # Type of FU issued +system.cpu.iq.FU_type::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type::total 19420 # Type of FU issued +system.cpu.iq.rate 0.734577 # Inst issue rate +system.cpu.iq.fu_busy_cnt::0 90 # FU busy when requested +system.cpu.iq.fu_busy_cnt::1 90 # FU busy when requested +system.cpu.iq.fu_busy_cnt::total 180 # FU busy when requested +system.cpu.iq.fu_busy_rate::0 0.004634 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_busy_rate::1 0.004634 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_busy_rate::total 0.009269 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 59410 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 31025 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 17735 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 42 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 20 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 20 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 19574 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 22 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 48 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.squashedLoads 1121 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 16 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 327 # Number of stores squashed +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread1.forwLoads 64 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread1.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread1.squashedLoads 1142 # Number of loads squashed +system.cpu.iew.lsq.thread1.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread1.memOrderViolation 13 # Number of memory ordering violations +system.cpu.iew.lsq.thread1.squashedStores 319 # Number of stores squashed +system.cpu.iew.lsq.thread1.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread1.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread1.rescheduledLoads 1 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread1.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewSquashCycles 1870 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1204 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 65 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 22464 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 427 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 4633 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 2376 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 49 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 38 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 29 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 214 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 883 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1097 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 18405 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts::0 1891 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts::1 1918 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts::total 3809 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1015 # Number of squashed instructions skipped in execute +system.cpu.iew.exec_swp::0 0 # number of swp insts executed +system.cpu.iew.exec_swp::1 0 # number of swp insts executed +system.cpu.iew.exec_swp::total 0 # number of swp insts executed +system.cpu.iew.exec_nop::0 75 # number of nop insts executed +system.cpu.iew.exec_nop::1 65 # number of nop insts executed +system.cpu.iew.exec_nop::total 140 # number of nop insts executed +system.cpu.iew.exec_refs::0 2925 # number of memory reference insts executed +system.cpu.iew.exec_refs::1 2953 # number of memory reference insts executed +system.cpu.iew.exec_refs::total 5878 # number of memory reference insts executed +system.cpu.iew.exec_branches::0 1521 # Number of branches executed +system.cpu.iew.exec_branches::1 1527 # Number of branches executed +system.cpu.iew.exec_branches::total 3048 # Number of branches executed +system.cpu.iew.exec_stores::0 1034 # Number of stores executed +system.cpu.iew.exec_stores::1 1035 # Number of stores executed +system.cpu.iew.exec_stores::total 2069 # Number of stores executed +system.cpu.iew.exec_rate 0.696183 # Inst execution rate +system.cpu.iew.wb_sent::0 9003 # cumulative count of insts sent to commit +system.cpu.iew.wb_sent::1 9003 # cumulative count of insts sent to commit +system.cpu.iew.wb_sent::total 18006 # cumulative count of insts sent to commit +system.cpu.iew.wb_count::0 8892 # cumulative count of insts written-back +system.cpu.iew.wb_count::1 8863 # cumulative count of insts written-back +system.cpu.iew.wb_count::total 17755 # cumulative count of insts written-back +system.cpu.iew.wb_producers::0 4543 # num instructions producing a value +system.cpu.iew.wb_producers::1 4543 # num instructions producing a value +system.cpu.iew.wb_producers::total 9086 # num instructions producing a value +system.cpu.iew.wb_consumers::0 5945 # num instructions consuming a value +system.cpu.iew.wb_consumers::1 5949 # num instructions consuming a value +system.cpu.iew.wb_consumers::total 11894 # num instructions consuming a value +system.cpu.iew.wb_penalized::0 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.wb_penalized::1 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.wb_penalized::total 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.wb_rate::0 0.336347 # insts written-back per cycle +system.cpu.iew.wb_rate::1 0.335250 # insts written-back per cycle +system.cpu.iew.wb_rate::total 0.671597 # insts written-back per cycle +system.cpu.iew.wb_fanout::0 0.764172 # average fanout of values written-back +system.cpu.iew.wb_fanout::1 0.763658 # average fanout of values written-back +system.cpu.iew.wb_fanout::total 1.527829 # average fanout of values written-back +system.cpu.iew.wb_penalized_rate::0 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu.iew.wb_penalized_rate::1 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu.iew.wb_penalized_rate::total 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 12807 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 9583 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 34 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 10106 # The number of squashed insts skipped by commit -system.cpu.commit.committed_per_cycle::samples 22336 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.573379 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.337408 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 951 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 20336 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.629770 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.428976 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 16656 74.57% 74.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 2886 12.92% 87.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 1149 5.14% 92.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 571 2.56% 95.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 362 1.62% 96.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 238 1.07% 97.88% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 197 0.88% 98.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 126 0.56% 99.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 151 0.68% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 14766 72.61% 72.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 2895 14.24% 86.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 1050 5.16% 92.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 514 2.53% 94.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 350 1.72% 96.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 235 1.16% 97.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 212 1.04% 98.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 89 0.44% 98.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 225 1.11% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 22336 # Number of insts commited each cycle -system.cpu.commit.count::0 6404 # Number of instructions committed -system.cpu.commit.count::1 6403 # Number of instructions committed +system.cpu.commit.committed_per_cycle::total 20336 # Number of insts commited each cycle +system.cpu.commit.count::0 6403 # Number of instructions committed +system.cpu.commit.count::1 6404 # Number of instructions committed system.cpu.commit.count::total 12807 # Number of instructions committed -system.cpu.commit.fp_insts::0 10 # Number of committed floating point instructions. -system.cpu.commit.fp_insts::1 10 # Number of committed floating point instructions. -system.cpu.commit.fp_insts::total 20 # Number of committed floating point instructions. -system.cpu.commit.function_calls::0 127 # Number of function calls committed. -system.cpu.commit.function_calls::1 127 # Number of function calls committed. -system.cpu.commit.function_calls::total 254 # Number of function calls committed. -system.cpu.commit.int_insts::0 6321 # Number of committed integer instructions. -system.cpu.commit.int_insts::1 6321 # Number of committed integer instructions. -system.cpu.commit.int_insts::total 12642 # Number of committed integer instructions. +system.cpu.commit.swp_count::0 0 # Number of s/w prefetches committed +system.cpu.commit.swp_count::1 0 # Number of s/w prefetches committed +system.cpu.commit.swp_count::total 0 # Number of s/w prefetches committed +system.cpu.commit.refs::0 2050 # Number of memory references committed +system.cpu.commit.refs::1 2050 # Number of memory references committed +system.cpu.commit.refs::total 4100 # Number of memory references committed system.cpu.commit.loads::0 1185 # Number of loads committed system.cpu.commit.loads::1 1185 # Number of loads committed system.cpu.commit.loads::total 2370 # Number of loads committed system.cpu.commit.membars::0 0 # Number of memory barriers committed system.cpu.commit.membars::1 0 # Number of memory barriers committed system.cpu.commit.membars::total 0 # Number of memory barriers committed -system.cpu.commit.refs::0 2050 # Number of memory references committed -system.cpu.commit.refs::1 2050 # Number of memory references committed -system.cpu.commit.refs::total 4100 # Number of memory references committed -system.cpu.commit.swp_count::0 0 # Number of s/w prefetches committed -system.cpu.commit.swp_count::1 0 # Number of s/w prefetches committed -system.cpu.commit.swp_count::total 0 # Number of s/w prefetches committed -system.cpu.committedInsts::0 6387 # Number of Instructions Simulated -system.cpu.committedInsts::1 6386 # Number of Instructions Simulated +system.cpu.commit.branches::0 1051 # Number of branches committed +system.cpu.commit.branches::1 1051 # Number of branches committed +system.cpu.commit.branches::total 2102 # Number of branches committed +system.cpu.commit.fp_insts::0 10 # Number of committed floating point instructions. +system.cpu.commit.fp_insts::1 10 # Number of committed floating point instructions. +system.cpu.commit.fp_insts::total 20 # Number of committed floating point instructions. +system.cpu.commit.int_insts::0 6321 # Number of committed integer instructions. +system.cpu.commit.int_insts::1 6321 # Number of committed integer instructions. +system.cpu.commit.int_insts::total 12642 # Number of committed integer instructions. +system.cpu.commit.function_calls::0 127 # Number of function calls committed. +system.cpu.commit.function_calls::1 127 # Number of function calls committed. +system.cpu.commit.function_calls::total 254 # Number of function calls committed. +system.cpu.commit.bw_lim_events 225 # number cycles where commit BW limit reached +system.cpu.commit.bw_limited::0 0 # number of insts not committed due to BW limits +system.cpu.commit.bw_limited::1 0 # number of insts not committed due to BW limits +system.cpu.commit.bw_limited::total 0 # number of insts not committed due to BW limits +system.cpu.rob.rob_reads 101662 # The number of ROB reads +system.cpu.rob.rob_writes 46661 # The number of ROB writes +system.cpu.timesIdled 242 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 6076 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts::0 6386 # Number of Instructions Simulated +system.cpu.committedInsts::1 6387 # Number of Instructions Simulated system.cpu.committedInsts_total 12773 # Number of Instructions Simulated -system.cpu.cpi::0 4.402223 # CPI: Cycles Per Instruction -system.cpu.cpi::1 4.402913 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.201284 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 3727 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency::0 36433.554817 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 36433.554817 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::0 36821.782178 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 3426 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency::0 10966500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 10966500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.080762 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 301 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits::0 99 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 99 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency::0 7438000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 7438000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.054199 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054199 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses::0 202 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 202 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 1730 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency::0 32498.595506 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 32498.595506 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::0 35993.150685 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 1018 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency::0 23139000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 23139000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.411561 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 712 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits::0 566 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 566 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency::0 5255000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5255000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.084393 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses::0 146 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 146 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 12.770115 # Average number of references to valid blocks. -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 5457 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency::0 33667.818361 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::1 0 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 33667.818361 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::0 36474.137931 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::1 no_value # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total no_value # average overall mshr miss latency -system.cpu.dcache.demand_hits 4444 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency::0 34105500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::1 0 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 34105500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.185633 # miss rate for demand accesses -system.cpu.dcache.demand_misses 1013 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits::0 665 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::1 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 665 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency::0 12693000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::1 0 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 12693000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate::0 0.063771 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.063771 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses::0 348 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::1 0 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 348 # number of demand (read+write) MSHR misses -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.mshr_cap_events::0 0 # number of times MSHR cap was activated -system.cpu.dcache.mshr_cap_events::1 0 # number of times MSHR cap was activated -system.cpu.dcache.mshr_cap_events::total 0 # number of times MSHR cap was activated -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_blocks::0 220.347711 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.053796 # Average percentage of cache occupancy -system.cpu.dcache.overall_accesses 5457 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency::0 33667.818361 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::1 0 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 33667.818361 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::0 36474.137931 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::1 no_value # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total no_value # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::0 no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::1 no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 4444 # number of overall hits -system.cpu.dcache.overall_miss_latency::0 34105500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::1 0 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 34105500 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.185633 # miss rate for overall accesses -system.cpu.dcache.overall_misses 1013 # number of overall misses -system.cpu.dcache.overall_mshr_hits::0 665 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::1 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 665 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency::0 12693000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::1 0 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 12693000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate::0 0.063771 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.063771 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses::0 348 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::1 0 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 348 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency::0 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::1 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_misses::0 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.overall_mshr_uncacheable_misses::1 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.overall_mshr_uncacheable_misses::total 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements::0 0 # number of replacements -system.cpu.dcache.replacements::1 0 # number of replacements -system.cpu.dcache.replacements::total 0 # number of replacements -system.cpu.dcache.sampled_refs 348 # Sample count of references to valid blocks. -system.cpu.dcache.soft_prefetch_mshr_full::0 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.soft_prefetch_mshr_full::1 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.soft_prefetch_mshr_full::total 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 220.347711 # Cycle average of tags in use -system.cpu.dcache.total_refs 4444 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks::0 0 # number of writebacks -system.cpu.dcache.writebacks::1 0 # number of writebacks -system.cpu.dcache.writebacks::total 0 # number of writebacks -system.cpu.decode.BlockedCycles 4700 # Number of cycles decode is blocked -system.cpu.decode.BranchMispred 432 # Number of times decode detected a branch misprediction -system.cpu.decode.BranchResolved 582 # Number of times decode resolved a branch -system.cpu.decode.DecodedInsts 26467 # Number of instructions handled by decode -system.cpu.decode.IdleCycles 33032 # Number of cycles decode is idle -system.cpu.decode.RunCycles 4744 # Number of cycles decode is running -system.cpu.decode.SquashCycles 1971 # Number of cycles decode is squashing -system.cpu.decode.SquashedInsts 600 # Number of squashed instructions handled by decode -system.cpu.decode.UnblockCycles 114 # Number of cycles decode is unblocking -system.cpu.dtb.data_accesses 6011 # DTB accesses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_hits 5860 # DTB hits -system.cpu.dtb.data_misses 151 # DTB misses -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.read_accesses 3932 # DTB read accesses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_hits 3840 # DTB read hits -system.cpu.dtb.read_misses 92 # DTB read misses -system.cpu.dtb.write_accesses 2079 # DTB write accesses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 2020 # DTB write hits -system.cpu.dtb.write_misses 59 # DTB write misses -system.cpu.fetch.Branches 5318 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 3965 # Number of cache lines fetched -system.cpu.fetch.Cycles 5044 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 575 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 29681 # Number of instructions fetch has processed -system.cpu.fetch.MiscStallCycles 55 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.SquashCycles 1624 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.189138 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 3965 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 1505 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.055625 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 22371 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.326762 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.728526 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 17327 77.45% 77.45% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 412 1.84% 79.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 325 1.45% 80.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 422 1.89% 82.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 410 1.83% 84.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 313 1.40% 85.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 439 1.96% 87.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 270 1.21% 89.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 2453 10.97% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 22371 # Number of instructions fetched each cycle (Total) +system.cpu.cpi::0 4.139837 # CPI: Cycles Per Instruction +system.cpu.cpi::1 4.139189 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.069757 # CPI: Total CPI of All Threads +system.cpu.ipc::0 0.241555 # IPC: Instructions Per Cycle +system.cpu.ipc::1 0.241593 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.483149 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 23349 # number of integer regfile reads +system.cpu.int_regfile_writes 13299 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads system.cpu.fp_regfile_writes 4 # number of floating regfile writes -system.cpu.icache.ReadReq_accesses 3965 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency::0 36242.350061 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 36242.350061 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::0 35491.100324 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 3148 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency::0 29610000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 29610000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.206053 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 817 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits::0 199 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 199 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency::0 21933500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 21933500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::0 0.155864 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.155864 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses::0 618 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 618 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 5.093851 # Average number of references to valid blocks. -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.misc_regfile_reads 2 # number of misc regfile reads +system.cpu.misc_regfile_writes 2 # number of misc regfile writes +system.cpu.icache.replacements::0 6 # number of replacements +system.cpu.icache.replacements::1 0 # number of replacements +system.cpu.icache.replacements::total 6 # number of replacements +system.cpu.icache.tagsinuse 314.403866 # Cycle average of tags in use +system.cpu.icache.total_refs 3230 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 626 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 5.159744 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::0 314.403866 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.153518 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 3230 # number of ReadReq hits +system.cpu.icache.demand_hits 3230 # number of demand (read+write) hits +system.cpu.icache.overall_hits 3230 # number of overall hits +system.cpu.icache.ReadReq_misses 855 # number of ReadReq misses +system.cpu.icache.demand_misses 855 # number of demand (read+write) misses +system.cpu.icache.overall_misses 855 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::0 30717000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 30717000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::0 30717000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::1 0 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 30717000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::0 30717000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::1 0 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 30717000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 4085 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 4085 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 4085 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.209302 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.209302 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.209302 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::0 35926.315789 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 35926.315789 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::0 35926.315789 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::1 0 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 35926.315789 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::0 35926.315789 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::1 0 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 35926.315789 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 3965 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency::0 36242.350061 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::1 0 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 36242.350061 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::0 35491.100324 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::1 no_value # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total no_value # average overall mshr miss latency -system.cpu.icache.demand_hits 3148 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency::0 29610000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::1 0 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 29610000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.206053 # miss rate for demand accesses -system.cpu.icache.demand_misses 817 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits::0 199 # number of demand (read+write) MSHR hits +system.cpu.icache.writebacks::0 0 # number of writebacks +system.cpu.icache.writebacks::1 0 # number of writebacks +system.cpu.icache.writebacks::total 0 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::0 229 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 229 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::0 229 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_hits::1 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 199 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency::0 21933500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_hits::total 229 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::0 229 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::1 0 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 229 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::0 626 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 626 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::0 626 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::1 0 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 626 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::0 626 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::1 0 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 626 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_misses::0 0 # number of overall MSHR uncacheable misses +system.cpu.icache.overall_mshr_uncacheable_misses::1 0 # number of overall MSHR uncacheable misses +system.cpu.icache.overall_mshr_uncacheable_misses::total 0 # number of overall MSHR uncacheable misses +system.cpu.icache.ReadReq_mshr_miss_latency::0 22275500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 22275500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::0 22275500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::1 0 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 21933500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate::0 0.155864 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_latency::total 22275500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::0 22275500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::1 0 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 22275500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_uncacheable_latency::0 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::1 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::total 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate::0 0.153244 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.153244 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::0 0.153244 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.155864 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses::0 618 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::1 0 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 618 # number of demand (read+write) MSHR misses -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.mshr_cap_events::0 0 # number of times MSHR cap was activated -system.cpu.icache.mshr_cap_events::1 0 # number of times MSHR cap was activated -system.cpu.icache.mshr_cap_events::total 0 # number of times MSHR cap was activated -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_blocks::0 318.780075 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.155654 # Average percentage of cache occupancy -system.cpu.icache.overall_accesses 3965 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency::0 36242.350061 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::1 0 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 36242.350061 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::0 35491.100324 # average overall mshr miss latency +system.cpu.icache.demand_mshr_miss_rate::total 0.153244 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::0 0.153244 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.153244 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::0 35583.865815 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::0 35583.865815 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::1 no_value # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total no_value # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::0 35583.865815 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::1 no_value # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total no_value # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::0 no_value # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::1 no_value # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 3148 # number of overall hits -system.cpu.icache.overall_miss_latency::0 29610000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::1 0 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 29610000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.206053 # miss rate for overall accesses -system.cpu.icache.overall_misses 817 # number of overall misses -system.cpu.icache.overall_mshr_hits::0 199 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::1 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 199 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency::0 21933500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::1 0 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 21933500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate::0 0.155864 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.155864 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses::0 618 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::1 0 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 618 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_latency::0 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::1 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_misses::0 0 # number of overall MSHR uncacheable misses -system.cpu.icache.overall_mshr_uncacheable_misses::1 0 # number of overall MSHR uncacheable misses -system.cpu.icache.overall_mshr_uncacheable_misses::total 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements::0 6 # number of replacements -system.cpu.icache.replacements::1 0 # number of replacements -system.cpu.icache.replacements::total 6 # number of replacements -system.cpu.icache.sampled_refs 618 # Sample count of references to valid blocks. +system.cpu.icache.mshr_cap_events::0 0 # number of times MSHR cap was activated +system.cpu.icache.mshr_cap_events::1 0 # number of times MSHR cap was activated +system.cpu.icache.mshr_cap_events::total 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full::0 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.soft_prefetch_mshr_full::1 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.soft_prefetch_mshr_full::total 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 318.780075 # Cycle average of tags in use -system.cpu.icache.total_refs 3148 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.writebacks::0 0 # number of writebacks -system.cpu.icache.writebacks::1 0 # number of writebacks -system.cpu.icache.writebacks::total 0 # number of writebacks -system.cpu.idleCycles 5746 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.branchMispredicts 1313 # Number of branch mispredicts detected at execute -system.cpu.iew.exec_branches::0 1549 # Number of branches executed -system.cpu.iew.exec_branches::1 1545 # Number of branches executed -system.cpu.iew.exec_branches::total 3094 # Number of branches executed -system.cpu.iew.exec_nop::0 67 # number of nop insts executed -system.cpu.iew.exec_nop::1 70 # number of nop insts executed -system.cpu.iew.exec_nop::total 137 # number of nop insts executed -system.cpu.iew.exec_rate 0.665505 # Inst execution rate -system.cpu.iew.exec_refs::0 3042 # number of memory reference insts executed -system.cpu.iew.exec_refs::1 2988 # number of memory reference insts executed -system.cpu.iew.exec_refs::total 6030 # number of memory reference insts executed -system.cpu.iew.exec_stores::0 1059 # Number of stores executed -system.cpu.iew.exec_stores::1 1037 # Number of stores executed -system.cpu.iew.exec_stores::total 2096 # Number of stores executed -system.cpu.iew.exec_swp::0 0 # number of swp insts executed -system.cpu.iew.exec_swp::1 0 # number of swp insts executed -system.cpu.iew.exec_swp::total 0 # number of swp insts executed -system.cpu.iew.iewBlockCycles 965 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 4691 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 46 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 813 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 2450 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 22978 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts::0 1983 # Number of load instructions executed -system.cpu.iew.iewExecLoadInsts::1 1951 # Number of load instructions executed -system.cpu.iew.iewExecLoadInsts::total 3934 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1099 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 18712 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 39 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 3 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 1971 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 59 # Number of cycles IEW is unblocking -system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread0.forwLoads 56 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread0.memOrderViolation 15 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.squashedLoads 1178 # Number of loads squashed -system.cpu.iew.lsq.thread0.squashedStores 386 # Number of stores squashed -system.cpu.iew.lsq.thread1.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread1.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread1.forwLoads 55 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread1.ignoredResponses 10 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread1.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread1.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread1.memOrderViolation 13 # Number of memory ordering violations -system.cpu.iew.lsq.thread1.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread1.squashedLoads 1143 # Number of loads squashed -system.cpu.iew.lsq.thread1.squashedStores 334 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 28 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 1056 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 257 # Number of branches that were predicted taken incorrectly -system.cpu.iew.wb_consumers::0 5857 # num instructions consuming a value -system.cpu.iew.wb_consumers::1 5876 # num instructions consuming a value -system.cpu.iew.wb_consumers::total 11733 # num instructions consuming a value -system.cpu.iew.wb_count::0 9007 # cumulative count of insts written-back -system.cpu.iew.wb_count::1 9010 # cumulative count of insts written-back -system.cpu.iew.wb_count::total 18017 # cumulative count of insts written-back -system.cpu.iew.wb_fanout::0 0.769336 # average fanout of values written-back -system.cpu.iew.wb_fanout::1 0.769401 # average fanout of values written-back -system.cpu.iew.wb_fanout::total 1.538737 # average fanout of values written-back -system.cpu.iew.wb_penalized::0 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_penalized::1 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_penalized::total 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_penalized_rate::0 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.wb_penalized_rate::1 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.wb_penalized_rate::total 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.wb_producers::0 4506 # num instructions producing a value -system.cpu.iew.wb_producers::1 4521 # num instructions producing a value -system.cpu.iew.wb_producers::total 9027 # num instructions producing a value -system.cpu.iew.wb_rate::0 0.320340 # insts written-back per cycle -system.cpu.iew.wb_rate::1 0.320447 # insts written-back per cycle -system.cpu.iew.wb_rate::total 0.640787 # insts written-back per cycle -system.cpu.iew.wb_sent::0 9150 # cumulative count of insts sent to commit -system.cpu.iew.wb_sent::1 9113 # cumulative count of insts sent to commit -system.cpu.iew.wb_sent::total 18263 # cumulative count of insts sent to commit -system.cpu.int_regfile_reads 23704 # number of integer regfile reads -system.cpu.int_regfile_writes 13551 # number of integer regfile writes -system.cpu.ipc::0 0.227158 # IPC: Instructions Per Cycle -system.cpu.ipc::1 0.227122 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.454280 # IPC: Total IPC of All Threads -system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 6672 67.35% 67.37% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.38% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.38% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.40% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.40% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.40% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.40% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.40% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.40% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2121 21.41% 88.81% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1109 11.19% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 9907 # Type of FU issued -system.cpu.iq.FU_type_1::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_1::IntAlu 6738 68.03% 68.05% # Type of FU issued -system.cpu.iq.FU_type_1::IntMult 1 0.01% 68.06% # Type of FU issued -system.cpu.iq.FU_type_1::IntDiv 0 0.00% 68.06% # Type of FU issued -system.cpu.iq.FU_type_1::FloatAdd 2 0.02% 68.08% # Type of FU issued -system.cpu.iq.FU_type_1::FloatCmp 0 0.00% 68.08% # Type of FU issued -system.cpu.iq.FU_type_1::FloatCvt 0 0.00% 68.08% # Type of FU issued -system.cpu.iq.FU_type_1::FloatMult 0 0.00% 68.08% # Type of FU issued -system.cpu.iq.FU_type_1::FloatDiv 0 0.00% 68.08% # Type of FU issued -system.cpu.iq.FU_type_1::FloatSqrt 0 0.00% 68.08% # Type of FU issued -system.cpu.iq.FU_type_1::SimdAdd 0 0.00% 68.08% # Type of FU issued -system.cpu.iq.FU_type_1::SimdAddAcc 0 0.00% 68.08% # Type of FU issued -system.cpu.iq.FU_type_1::SimdAlu 0 0.00% 68.08% # Type of FU issued -system.cpu.iq.FU_type_1::SimdCmp 0 0.00% 68.08% # Type of FU issued -system.cpu.iq.FU_type_1::SimdCvt 0 0.00% 68.08% # Type of FU issued -system.cpu.iq.FU_type_1::SimdMisc 0 0.00% 68.08% # Type of FU issued -system.cpu.iq.FU_type_1::SimdMult 0 0.00% 68.08% # Type of FU issued -system.cpu.iq.FU_type_1::SimdMultAcc 0 0.00% 68.08% # Type of FU issued -system.cpu.iq.FU_type_1::SimdShift 0 0.00% 68.08% # Type of FU issued -system.cpu.iq.FU_type_1::SimdShiftAcc 0 0.00% 68.08% # Type of FU issued -system.cpu.iq.FU_type_1::SimdSqrt 0 0.00% 68.08% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatAdd 0 0.00% 68.08% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatAlu 0 0.00% 68.08% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatCmp 0 0.00% 68.08% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatCvt 0 0.00% 68.08% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatDiv 0 0.00% 68.08% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatMisc 0 0.00% 68.08% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatMult 0 0.00% 68.08% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatMultAcc 0 0.00% 68.08% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatSqrt 0 0.00% 68.08% # Type of FU issued -system.cpu.iq.FU_type_1::MemRead 2064 20.84% 88.92% # Type of FU issued -system.cpu.iq.FU_type_1::MemWrite 1097 11.08% 100.00% # Type of FU issued -system.cpu.iq.FU_type_1::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_1::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_1::total 9904 # Type of FU issued -system.cpu.iq.FU_type::No_OpClass 4 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type::IntAlu 13410 67.69% 67.71% # Type of FU issued -system.cpu.iq.FU_type::IntMult 2 0.01% 67.72% # Type of FU issued -system.cpu.iq.FU_type::IntDiv 0 0.00% 67.72% # Type of FU issued -system.cpu.iq.FU_type::FloatAdd 4 0.02% 67.74% # Type of FU issued -system.cpu.iq.FU_type::FloatCmp 0 0.00% 67.74% # Type of FU issued -system.cpu.iq.FU_type::FloatCvt 0 0.00% 67.74% # Type of FU issued -system.cpu.iq.FU_type::FloatMult 0 0.00% 67.74% # Type of FU issued -system.cpu.iq.FU_type::FloatDiv 0 0.00% 67.74% # Type of FU issued -system.cpu.iq.FU_type::FloatSqrt 0 0.00% 67.74% # Type of FU issued -system.cpu.iq.FU_type::SimdAdd 0 0.00% 67.74% # Type of FU issued -system.cpu.iq.FU_type::SimdAddAcc 0 0.00% 67.74% # Type of FU issued -system.cpu.iq.FU_type::SimdAlu 0 0.00% 67.74% # Type of FU issued -system.cpu.iq.FU_type::SimdCmp 0 0.00% 67.74% # Type of FU issued -system.cpu.iq.FU_type::SimdCvt 0 0.00% 67.74% # Type of FU issued -system.cpu.iq.FU_type::SimdMisc 0 0.00% 67.74% # Type of FU issued -system.cpu.iq.FU_type::SimdMult 0 0.00% 67.74% # Type of FU issued -system.cpu.iq.FU_type::SimdMultAcc 0 0.00% 67.74% # Type of FU issued -system.cpu.iq.FU_type::SimdShift 0 0.00% 67.74% # Type of FU issued -system.cpu.iq.FU_type::SimdShiftAcc 0 0.00% 67.74% # Type of FU issued -system.cpu.iq.FU_type::SimdSqrt 0 0.00% 67.74% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatAdd 0 0.00% 67.74% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatAlu 0 0.00% 67.74% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatCmp 0 0.00% 67.74% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatCvt 0 0.00% 67.74% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatDiv 0 0.00% 67.74% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatMisc 0 0.00% 67.74% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatMult 0 0.00% 67.74% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatMultAcc 0 0.00% 67.74% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatSqrt 0 0.00% 67.74% # Type of FU issued -system.cpu.iq.FU_type::MemRead 4185 21.12% 88.86% # Type of FU issued -system.cpu.iq.FU_type::MemWrite 2206 11.14% 100.00% # Type of FU issued -system.cpu.iq.FU_type::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type::total 19811 # Type of FU issued -system.cpu.iq.fp_alu_accesses 22 # Number of floating point alu accesses -system.cpu.iq.fp_inst_queue_reads 42 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_wakeup_accesses 20 # Number of floating instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_writes 20 # Number of floating instruction queue writes -system.cpu.iq.fu_busy_cnt::0 76 # FU busy when requested -system.cpu.iq.fu_busy_cnt::1 88 # FU busy when requested -system.cpu.iq.fu_busy_cnt::total 164 # FU busy when requested -system.cpu.iq.fu_busy_rate::0 0.003836 # FU busy rate (busy events/executed inst) -system.cpu.iq.fu_busy_rate::1 0.004442 # FU busy rate (busy events/executed inst) -system.cpu.iq.fu_busy_rate::total 0.008278 # FU busy rate (busy events/executed inst) -system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 10 6.10% 6.10% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 6.10% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 6.10% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.10% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.10% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.10% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 6.10% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.10% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 6.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 6.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.10% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.10% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 90 54.88% 60.98% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 64 39.02% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.int_alu_accesses 19949 # Number of integer alu accesses -system.cpu.iq.int_inst_queue_reads 62191 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_wakeup_accesses 17997 # Number of integer instruction queue wakeup accesses -system.cpu.iq.int_inst_queue_writes 31607 # Number of integer instruction queue writes -system.cpu.iq.iqInstsAdded 22795 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 19811 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 46 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 8766 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 76 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 4974 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.issued_per_cycle::samples 22371 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.885566 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.449509 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 13920 62.22% 62.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 3143 14.05% 76.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 2295 10.26% 86.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 1308 5.85% 92.38% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 818 3.66% 96.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 557 2.49% 98.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 231 1.03% 99.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 81 0.36% 99.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 18 0.08% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 22371 # Number of insts issued each cycle -system.cpu.iq.rate 0.704592 # Inst issue rate -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.fetch_accesses 4020 # ITB accesses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_hits 3965 # ITB hits -system.cpu.itb.fetch_misses 55 # ITB misses -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements::0 0 # number of replacements +system.cpu.dcache.replacements::1 0 # number of replacements +system.cpu.dcache.replacements::total 0 # number of replacements +system.cpu.dcache.tagsinuse 216.203520 # Cycle average of tags in use +system.cpu.dcache.total_refs 4314 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 347 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 12.432277 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::0 216.203520 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.052784 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 3294 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits 1020 # number of WriteReq hits +system.cpu.dcache.demand_hits 4314 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 4314 # number of overall hits +system.cpu.dcache.ReadReq_misses 306 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses 710 # number of WriteReq misses +system.cpu.dcache.demand_misses 1016 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 1016 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::0 11205000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11205000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::0 24076500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 24076500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::0 35281500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::1 0 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 35281500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::0 35281500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::1 0 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 35281500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 3600 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses 1730 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses 5330 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 5330 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.085000 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.410405 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate 0.190619 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.190619 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::0 36617.647059 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 36617.647059 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::0 33910.563380 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 33910.563380 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::0 34725.885827 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::1 0 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 34725.885827 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::0 34725.885827 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::1 0 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 34725.885827 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::0 0 # number of writebacks +system.cpu.dcache.writebacks::1 0 # number of writebacks +system.cpu.dcache.writebacks::total 0 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::0 105 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 105 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::0 564 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 564 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::0 669 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::1 0 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 669 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::0 669 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::1 0 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 669 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::0 201 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 201 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::0 146 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 146 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::0 347 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::1 0 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 347 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::0 347 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::1 0 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 347 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_misses::0 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.overall_mshr_uncacheable_misses::1 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.overall_mshr_uncacheable_misses::total 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.ReadReq_mshr_miss_latency::0 7390000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 7390000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::0 5293000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5293000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::0 12683000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::1 0 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 12683000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::0 12683000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::1 0 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12683000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::0 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::1 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.055833 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.055833 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.084393 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::0 0.065103 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.065103 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::0 0.065103 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.065103 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::0 36766.169154 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::0 36253.424658 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::0 36550.432277 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::1 no_value # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total no_value # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::0 36550.432277 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::1 no_value # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total no_value # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::0 no_value # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::1 no_value # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total no_value # average overall mshr uncacheable latency +system.cpu.dcache.mshr_cap_events::0 0 # number of times MSHR cap was activated +system.cpu.dcache.mshr_cap_events::1 0 # number of times MSHR cap was activated +system.cpu.dcache.mshr_cap_events::total 0 # number of times MSHR cap was activated +system.cpu.dcache.soft_prefetch_mshr_full::0 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.soft_prefetch_mshr_full::1 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.soft_prefetch_mshr_full::total 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.replacements::0 0 # number of replacements +system.cpu.l2cache.replacements::1 0 # number of replacements +system.cpu.l2cache.replacements::total 0 # number of replacements +system.cpu.l2cache.tagsinuse 435.485428 # Cycle average of tags in use +system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 825 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.002424 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::0 435.485428 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.013290 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits +system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits 2 # number of overall hits +system.cpu.l2cache.ReadReq_misses 825 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses 146 # number of ReadExReq misses +system.cpu.l2cache.demand_misses 971 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses 971 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::0 28485000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 28485000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::0 5065500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5065500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::0 33550500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::1 0 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 33550500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::0 33550500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::1 0 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 33550500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses 827 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses 146 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency::0 34506.849315 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34506.849315 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::0 31441.780822 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency::0 5038000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5038000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_accesses 973 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses 973 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate 0.997582 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 146 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::0 4590500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4590500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::0 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses::0 146 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 146 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 820 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency::0 34518.948655 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 34518.948655 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::0 31380.195599 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency::0 28236500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 28236500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.997561 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 818 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::0 25669000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25669000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::0 0.997561 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997561 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses::0 818 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 818 # number of ReadReq MSHR misses -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 6750 # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.002445 # Average number of references to valid blocks. +system.cpu.l2cache.demand_miss_rate 0.997945 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate 0.997945 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::0 34527.272727 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 34527.272727 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::0 34695.205479 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34695.205479 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::0 34552.523172 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::1 0 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 34552.523172 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::0 34552.523172 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::1 0 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 34552.523172 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 21000 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 4 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_mshrs 27000 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 5250 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 966 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency::0 34517.116183 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::1 0 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 34517.116183 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::0 31389.522822 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::1 no_value # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total no_value # average overall mshr miss latency -system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency::0 33274500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::1 0 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 33274500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.997930 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 964 # number of demand (read+write) misses +system.cpu.l2cache.writebacks::0 0 # number of writebacks +system.cpu.l2cache.writebacks::1 0 # number of writebacks +system.cpu.l2cache.writebacks::total 0 # number of writebacks system.cpu.l2cache.demand_mshr_hits::0 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::1 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::total 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency::0 30259500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::1 0 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 30259500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate::0 0.997930 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.997930 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses::0 964 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::1 0 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 964 # number of demand (read+write) MSHR misses -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.mshr_cap_events::0 0 # number of times MSHR cap was activated -system.cpu.l2cache.mshr_cap_events::1 0 # number of times MSHR cap was activated -system.cpu.l2cache.mshr_cap_events::total 0 # number of times MSHR cap was activated -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_blocks::0 441.662390 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.013478 # Average percentage of cache occupancy -system.cpu.l2cache.overall_accesses 966 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency::0 34517.116183 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::1 0 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 34517.116183 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::0 31389.522822 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::1 no_value # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total no_value # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::0 no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::1 no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 2 # number of overall hits -system.cpu.l2cache.overall_miss_latency::0 33274500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::1 0 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 33274500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.997930 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 964 # number of overall misses system.cpu.l2cache.overall_mshr_hits::0 0 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::1 0 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency::0 30259500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::1 0 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 30259500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate::0 0.997930 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.997930 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses::0 964 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::0 825 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 825 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::0 146 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 146 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::0 971 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::1 0 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 971 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::0 971 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::1 0 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 964 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_latency::0 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::1 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_misses::total 971 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses::0 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.overall_mshr_uncacheable_misses::1 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.overall_mshr_uncacheable_misses::total 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements::0 0 # number of replacements -system.cpu.l2cache.replacements::1 0 # number of replacements -system.cpu.l2cache.replacements::total 0 # number of replacements -system.cpu.l2cache.sampled_refs 818 # Sample count of references to valid blocks. +system.cpu.l2cache.ReadReq_mshr_miss_latency::0 25905000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25905000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::0 4613500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4613500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::0 30518500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::1 0 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 30518500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::0 30518500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::1 0 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 30518500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::0 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::1 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 0 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::0 0.997582 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997582 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::0 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::0 0.997945 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.997945 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::0 0.997945 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.997945 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::0 31400 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::0 31599.315068 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::0 31429.969104 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::1 no_value # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total no_value # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::0 31429.969104 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::1 no_value # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total no_value # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::0 no_value # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::1 no_value # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total no_value # average overall mshr uncacheable latency +system.cpu.l2cache.mshr_cap_events::0 0 # number of times MSHR cap was activated +system.cpu.l2cache.mshr_cap_events::1 0 # number of times MSHR cap was activated +system.cpu.l2cache.mshr_cap_events::total 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full::0 0 # number of mshr full events for SW prefetching instrutions system.cpu.l2cache.soft_prefetch_mshr_full::1 0 # number of mshr full events for SW prefetching instrutions system.cpu.l2cache.soft_prefetch_mshr_full::total 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 441.662390 # Cycle average of tags in use -system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks::0 0 # number of writebacks -system.cpu.l2cache.writebacks::1 0 # number of writebacks -system.cpu.l2cache.writebacks::total 0 # number of writebacks -system.cpu.memDep0.conflictingLoads 12 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 2363 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1251 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep1.conflictingLoads 0 # Number of conflicting loads. -system.cpu.memDep1.conflictingStores 0 # Number of conflicting stores. -system.cpu.memDep1.insertedLoads 2328 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep1.insertedStores 1199 # Number of stores inserted to the mem dependence unit. -system.cpu.misc_regfile_reads 2 # number of misc regfile reads -system.cpu.misc_regfile_writes 2 # number of misc regfile writes -system.cpu.numCycles 28117 # number of cpu cycles simulated -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.rename.BlockCycles 2820 # Number of cycles rename is blocking -system.cpu.rename.CommittedMaps 9166 # Number of HB maps that are committed -system.cpu.rename.IQFullEvents 4 # Number of times rename has blocked due to IQ full -system.cpu.rename.IdleCycles 33480 # Number of cycles rename is idle -system.cpu.rename.LSQFullEvents 1251 # Number of times rename has blocked due to LSQ full -system.cpu.rename.ROBFullEvents 2 # Number of times rename has blocked due to ROB full -system.cpu.rename.RenameLookups 31536 # Number of register rename lookups that rename has made -system.cpu.rename.RenamedInsts 25241 # Number of instructions processed by rename -system.cpu.rename.RenamedOperands 18899 # Number of destination operands rename has renamed -system.cpu.rename.RunCycles 4323 # Number of cycles rename is running -system.cpu.rename.SquashCycles 1971 # Number of cycles rename is squashing -system.cpu.rename.UnblockCycles 1300 # Number of cycles rename is unblocking -system.cpu.rename.UndoneMaps 9733 # Number of HB maps that are undone due to squashing -system.cpu.rename.fp_rename_lookups 34 # Number of floating rename lookups -system.cpu.rename.int_rename_lookups 31502 # Number of integer rename lookups -system.cpu.rename.serializeStallCycles 667 # count of cycles rename stalled for serializing inst -system.cpu.rename.serializingInsts 50 # count of serializing insts renamed -system.cpu.rename.skidInsts 3351 # count of insts added to the skid buffer -system.cpu.rename.tempSerializingInsts 38 # count of temporary serializing insts renamed -system.cpu.rob.rob_reads 106938 # The number of ROB reads -system.cpu.rob.rob_writes 47804 # The number of ROB writes -system.cpu.timesIdled 269 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.workload0.num_syscalls 17 # Number of system calls -system.cpu.workload1.num_syscalls 17 # Number of system calls +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/02.insttest/ref/sparc/linux/inorder-timing/config.ini b/tests/quick/02.insttest/ref/sparc/linux/inorder-timing/config.ini index e8057b6e2..7ee142626 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/inorder-timing/config.ini +++ b/tests/quick/02.insttest/ref/sparc/linux/inorder-timing/config.ini @@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem mem_mode=atomic +memories=system.physmem physmem=system.physmem work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -204,7 +205,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/insttest/bin/sparc/linux/insttest +executable=/arm/scratch/sysexplr/dist/test-progs/insttest/bin/sparc/linux/insttest gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/02.insttest/ref/sparc/linux/inorder-timing/simout b/tests/quick/02.insttest/ref/sparc/linux/inorder-timing/simout index 2a38cfdfa..64331370b 100755 --- a/tests/quick/02.insttest/ref/sparc/linux/inorder-timing/simout +++ b/tests/quick/02.insttest/ref/sparc/linux/inorder-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 20 2011 19:27:12 -gem5 started Jun 20 2011 20:17:56 -gem5 executing on zooks +gem5 compiled Jul 9 2011 14:58:11 +gem5 started Jul 9 2011 15:02:19 +gem5 executing on nadc-0321 command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/quick/02.insttest/sparc/linux/inorder-timing -re tests/run.py build/SPARC_SE/tests/opt/quick/02.insttest/sparc/linux/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -18,4 +18,4 @@ LDTX: Passed LDTW: Passed STTW: Passed Done -Exiting @ tick 25074500 because target called exit() +Exiting @ tick 25058500 because target called exit() diff --git a/tests/quick/02.insttest/ref/sparc/linux/inorder-timing/stats.txt b/tests/quick/02.insttest/ref/sparc/linux/inorder-timing/stats.txt index 99673e355..10d7a8655 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/inorder-timing/stats.txt +++ b/tests/quick/02.insttest/ref/sparc/linux/inorder-timing/stats.txt @@ -1,24 +1,24 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000025 # Number of seconds simulated -sim_ticks 25074500 # Number of ticks simulated +sim_ticks 25058500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 12169 # Simulator instruction rate (inst/s) -host_tick_rate 20106315 # Simulator tick rate (ticks/s) -host_mem_usage 158720 # Number of bytes of host memory used -host_seconds 1.25 # Real time elapsed on the host +host_inst_rate 66853 # Simulator instruction rate (inst/s) +host_tick_rate 110387436 # Simulator tick rate (ticks/s) +host_mem_usage 249432 # Number of bytes of host memory used +host_seconds 0.23 # Real time elapsed on the host sim_insts 15175 # Number of instructions simulated system.cpu.workload.num_syscalls 18 # Number of system calls -system.cpu.numCycles 50150 # number of cpu cycles simulated +system.cpu.numCycles 50118 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 22024 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 21993 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode system.cpu.timesIdled 454 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 32481 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 17669 # Number of cycles cpu stages are processed. -system.cpu.activity 35.232303 # Percentage of cycles cpu is active +system.cpu.idleCycles 32493 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 17625 # Number of cycles cpu stages are processed. +system.cpu.activity 35.167006 # Percentage of cycles cpu is active system.cpu.comLoads 2226 # Number of Load instructions committed system.cpu.comStores 1448 # Number of Store instructions committed system.cpu.comBranches 3359 # Number of Branches instructions committed @@ -29,79 +29,79 @@ system.cpu.comFloats 0 # Nu system.cpu.committedInsts 15175 # Number of Instructions Simulated (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread) system.cpu.committedInsts_total 15175 # Number of Instructions Simulated (Total) -system.cpu.cpi 3.304778 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 3.302669 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi no_value # CPI: Total SMT-CPI -system.cpu.cpi_total 3.304778 # CPI: Total CPI of All Threads -system.cpu.ipc 0.302592 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 3.302669 # CPI: Total CPI of All Threads +system.cpu.ipc 0.302785 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc no_value # IPC: Total SMT-IPC -system.cpu.ipc_total 0.302592 # IPC: Total IPC of All Threads -system.cpu.branch_predictor.lookups 5200 # Number of BP lookups -system.cpu.branch_predictor.condPredicted 3649 # Number of conditional branches predicted -system.cpu.branch_predictor.condIncorrect 2386 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 4558 # Number of BTB lookups -system.cpu.branch_predictor.BTBHits 2986 # Number of BTB hits +system.cpu.ipc_total 0.302785 # IPC: Total IPC of All Threads +system.cpu.branch_predictor.lookups 5166 # Number of BP lookups +system.cpu.branch_predictor.condPredicted 3601 # Number of conditional branches predicted +system.cpu.branch_predictor.condIncorrect 2377 # Number of conditional branches incorrect +system.cpu.branch_predictor.BTBLookups 4346 # Number of BTB lookups +system.cpu.branch_predictor.BTBHits 2912 # Number of BTB hits system.cpu.branch_predictor.usedRAS 172 # Number of times the RAS was used to get a target. system.cpu.branch_predictor.RASInCorrect 5 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 65.511189 # BTB Hit Percentage -system.cpu.branch_predictor.predictedTaken 3158 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 2042 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 14332 # Number of Reads from Int. Register File +system.cpu.branch_predictor.BTBHitPct 67.004142 # BTB Hit Percentage +system.cpu.branch_predictor.predictedTaken 3084 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 2082 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 14334 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 11111 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 25443 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.intRegFileAccesses 25445 # Total Accesses (Read+Write) to the Int. Register File system.cpu.regfile_manager.floatRegFileReads 0 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 0 # Number of Writes to FP Register File system.cpu.regfile_manager.floatRegFileAccesses 0 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 5213 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 3843 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 1633 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 690 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 2323 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 1036 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 69.157487 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 11042 # Number of Instructions Executed. +system.cpu.regfile_manager.regForwards 5192 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 3845 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 1598 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 716 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 2314 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 1045 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 68.889550 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 11051 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 0 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed -system.cpu.stage0.idleCycles 36479 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 13671 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 27.260219 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 40783 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 9367 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 18.677966 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 41319 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 8831 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 17.609172 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 47266 # Number of cycles 0 instructions are processed. +system.cpu.stage0.idleCycles 36528 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 13590 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 27.116006 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 40773 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 9345 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 18.645995 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 41295 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 8823 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 17.604453 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 47234 # Number of cycles 0 instructions are processed. system.cpu.stage3.runCycles 2884 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 5.750748 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 40819 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 9331 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 18.606181 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.utilization 5.754420 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 40795 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 9323 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 18.602099 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 165.662451 # Cycle average of tags in use -system.cpu.icache.total_refs 3061 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 165.645515 # Cycle average of tags in use +system.cpu.icache.total_refs 3085 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 299 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 10.237458 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 10.317726 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 165.662451 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.080890 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 3061 # number of ReadReq hits -system.cpu.icache.demand_hits 3061 # number of demand (read+write) hits -system.cpu.icache.overall_hits 3061 # number of overall hits +system.cpu.icache.occ_blocks::0 165.645515 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.080882 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 3085 # number of ReadReq hits +system.cpu.icache.demand_hits 3085 # number of demand (read+write) hits +system.cpu.icache.overall_hits 3085 # number of overall hits system.cpu.icache.ReadReq_misses 366 # number of ReadReq misses system.cpu.icache.demand_misses 366 # number of demand (read+write) misses system.cpu.icache.overall_misses 366 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 20101500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 20101500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 20101500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 3427 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 3427 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 3427 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.106799 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.106799 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.106799 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 54922.131148 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 54922.131148 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 54922.131148 # average overall miss latency +system.cpu.icache.ReadReq_miss_latency 20100000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 20100000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 20100000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 3451 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 3451 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 3451 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.106056 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.106056 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.106056 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 54918.032787 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 54918.032787 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 54918.032787 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 19500 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -118,28 +118,28 @@ system.cpu.icache.ReadReq_mshr_misses 301 # nu system.cpu.icache.demand_mshr_misses 301 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses 301 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 15873500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 15873500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 15873500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 15872000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 15872000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 15872000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.087832 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.087832 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.087832 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 52735.880399 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 52735.880399 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 52735.880399 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate 0.087221 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.087221 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.087221 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 52730.897010 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 52730.897010 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 52730.897010 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 97.092985 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 97.082868 # Cycle average of tags in use system.cpu.dcache.total_refs 3316 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 24.028986 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 97.092985 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.023704 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 97.082868 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.023702 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits 2168 # number of ReadReq hits system.cpu.dcache.WriteReq_hits 1142 # number of WriteReq hits system.cpu.dcache.SwapReq_hits 6 # number of SwapReq hits @@ -149,10 +149,10 @@ system.cpu.dcache.ReadReq_misses 58 # nu system.cpu.dcache.WriteReq_misses 300 # number of WriteReq misses system.cpu.dcache.demand_misses 358 # number of demand (read+write) misses system.cpu.dcache.overall_misses 358 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 3281500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 3282500 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency 16398000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 19679500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 19679500 # number of overall miss cycles +system.cpu.dcache.demand_miss_latency 19680500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 19680500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses 2226 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 1442 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SwapReq_accesses 6 # number of SwapReq accesses(hits+misses) @@ -162,10 +162,10 @@ system.cpu.dcache.ReadReq_miss_rate 0.026056 # mi system.cpu.dcache.WriteReq_miss_rate 0.208044 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate 0.097601 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate 0.097601 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 56577.586207 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 56594.827586 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency 54660 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 54970.670391 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 54970.670391 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency 54973.463687 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 54973.463687 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 2208000 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -184,30 +184,30 @@ system.cpu.dcache.WriteReq_mshr_misses 85 # nu system.cpu.dcache.demand_mshr_misses 138 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses 138 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 2837000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 2838000 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency 4545000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 7382000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 7382000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 7383000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 7383000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.023810 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate 0.058946 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate 0.037623 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate 0.037623 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53528.301887 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53547.169811 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53470.588235 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 53492.753623 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 53492.753623 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 53500 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 53500 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 196.326094 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 196.307447 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 350 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.005714 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 196.326094 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::0 196.307447 # Average occupied blocks per context system.cpu.l2cache.occ_percent::0 0.005991 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits @@ -248,19 +248,19 @@ system.cpu.l2cache.ReadExReq_mshr_misses 85 # nu system.cpu.l2cache.demand_mshr_misses 437 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses 437 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 14049000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 14048500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency 3416000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 17465000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 17465000 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 17464500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 17464500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.994350 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate 0.995444 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate 0.995444 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 39911.931818 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 39910.511364 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40188.235294 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 39965.675057 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 39965.675057 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 39964.530892 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 39964.530892 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini index 8343b4558..9574fc9f3 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini +++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini @@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem mem_mode=atomic +memories=system.physmem physmem=system.physmem work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -498,7 +499,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/insttest/bin/sparc/linux/insttest +executable=/chips/pd/randd/dist/test-progs/insttest/bin/sparc/linux/insttest gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout index 99d6fe91b..636722350 100755 --- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout +++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 10 2011 22:06:52 -gem5 started Jun 10 2011 22:07:32 -gem5 executing on zooks +gem5 compiled Jul 8 2011 15:08:13 +gem5 started Jul 8 2011 15:22:48 +gem5 executing on u200439-lin.austin.arm.com command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/quick/02.insttest/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/opt/quick/02.insttest/sparc/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -18,4 +18,4 @@ LDTX: Passed LDTW: Passed STTW: Passed Done -Exiting @ tick 19016500 because target called exit() +Exiting @ tick 18121000 because target called exit() diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt index 9c30078fb..34c9dc344 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt @@ -1,247 +1,249 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000019 # Number of seconds simulated -sim_ticks 19016500 # Number of ticks simulated +sim_seconds 0.000018 # Number of seconds simulated +sim_ticks 18121000 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 51742 # Simulator instruction rate (inst/s) -host_tick_rate 68090181 # Simulator tick rate (ticks/s) -host_mem_usage 162768 # Number of bytes of host memory used -host_seconds 0.28 # Real time elapsed on the host +host_inst_rate 13353 # Simulator instruction rate (inst/s) +host_tick_rate 16745708 # Simulator tick rate (ticks/s) +host_mem_usage 246680 # Number of bytes of host memory used +host_seconds 1.08 # Real time elapsed on the host sim_insts 14449 # Number of instructions simulated system.cpu.workload.num_syscalls 18 # Number of system calls -system.cpu.numCycles 38034 # number of cpu cycles simulated +system.cpu.numCycles 36243 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 5148 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 3432 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 838 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 4682 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 2465 # Number of BTB hits +system.cpu.BPredUnit.lookups 5652 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 3765 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 848 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 5024 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 2638 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 337 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 167 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 4256 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 23684 # Number of instructions fetch has processed -system.cpu.fetch.Branches 5148 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 2802 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 7695 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 937 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 28 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.CacheLines 4256 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 353 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 29221 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.810513 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.905949 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 357 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 168 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 10750 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 25938 # Number of instructions fetch has processed +system.cpu.fetch.Branches 5652 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 2995 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 8192 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2326 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 6715 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 641 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 4621 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 374 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 27680 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.937066 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.038861 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 21526 73.67% 73.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 3882 13.28% 86.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 537 1.84% 88.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 503 1.72% 90.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 680 2.33% 92.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 525 1.80% 94.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 239 0.82% 95.45% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 192 0.66% 96.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1137 3.89% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 19488 70.40% 70.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 4056 14.65% 85.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 538 1.94% 87.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 473 1.71% 88.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 725 2.62% 91.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 641 2.32% 93.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 275 0.99% 94.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 240 0.87% 95.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1244 4.49% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 29221 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.135353 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.622706 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 13502 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 6935 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 7417 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 107 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1260 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 23270 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 1260 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 13958 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 243 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 6236 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 7103 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 421 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 21729 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 1 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 112 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 19486 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 40358 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 40358 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 27680 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.155947 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.715669 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 11171 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 7401 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 7541 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 189 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1378 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 24386 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 1378 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 11668 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 225 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 6686 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 7269 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 454 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 22625 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 3 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 135 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 20272 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 41976 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 41976 # Number of integer rename lookups system.cpu.rename.CommittedMaps 13832 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 5654 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 629 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 601 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 2349 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 3050 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1902 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 8 # Number of conflicting loads. +system.cpu.rename.UndoneMaps 6440 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 639 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 632 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 2436 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 3146 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 2001 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 7 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 18598 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 570 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 18016 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 71 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 3968 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3549 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 95 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 29221 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.616543 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.185129 # Number of insts issued each cycle +system.cpu.iq.iqInstsAdded 19436 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 615 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 18669 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 81 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 4953 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 4052 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 140 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 27680 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.674458 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.255150 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 20388 69.77% 69.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 4239 14.51% 84.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 1899 6.50% 90.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 1712 5.86% 96.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 440 1.51% 98.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 282 0.97% 99.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 168 0.57% 99.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 79 0.27% 99.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 14 0.05% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 19155 69.20% 69.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 3456 12.49% 81.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 2226 8.04% 89.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 1550 5.60% 95.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 660 2.38% 97.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 386 1.39% 99.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 197 0.71% 99.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 41 0.15% 99.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 9 0.03% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 29221 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 27680 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 26 21.14% 21.14% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 21.14% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 21.14% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 21.14% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 21.14% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 21.14% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 21.14% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 21.14% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 21.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 21.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 21.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 21.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 21.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 21.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 21.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 21.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 21.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 21.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 21.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 21.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 21.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 21.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 21.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 21.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 21.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 21.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 21.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 21.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 21.14% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 29 23.58% 44.72% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 68 55.28% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 35 25.18% 25.18% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 25.18% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 25.18% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 25.18% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 25.18% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 25.18% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 25.18% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 25.18% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 25.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 25.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 25.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 25.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 25.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 25.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 25.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 25.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 25.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 25.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 25.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 25.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 25.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 25.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 25.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 25.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 25.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 25.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 25.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.18% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 25.18% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 26 18.71% 43.88% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 78 56.12% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 13295 73.80% 73.80% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 73.80% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 73.80% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 73.80% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 73.80% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 73.80% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 73.80% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 73.80% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 73.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 73.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 73.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 73.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 73.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 73.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 73.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 73.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 73.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 73.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 73.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 73.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 73.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 73.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 73.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 73.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 73.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 73.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 73.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 73.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 73.80% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2920 16.21% 90.00% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1801 10.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 13814 73.99% 73.99% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 73.99% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 73.99% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 73.99% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 73.99% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 73.99% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 73.99% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 73.99% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 73.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 73.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 73.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 73.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 73.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 73.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 73.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 73.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 73.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 73.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 73.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 73.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 73.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 73.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 73.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 73.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 73.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 73.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 73.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 73.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 73.99% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2983 15.98% 89.97% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1872 10.03% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 18016 # Type of FU issued -system.cpu.iq.rate 0.473681 # Inst issue rate -system.cpu.iq.fu_busy_cnt 123 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.006827 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 65447 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 23160 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 17101 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 18669 # Type of FU issued +system.cpu.iq.rate 0.515106 # Inst issue rate +system.cpu.iq.fu_busy_cnt 139 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.007445 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 65238 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 25029 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 17501 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 18139 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 18808 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 30 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 32 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 824 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 30 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 454 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 920 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 32 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 553 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1260 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 132 # Number of cycles IEW is blocking +system.cpu.iew.iewSquashCycles 1378 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 96 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 10 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 20254 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 413 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 3050 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1902 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 570 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewDispatchedInsts 21162 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 247 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 3146 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 2001 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 615 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 30 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 372 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 553 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 925 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 17560 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2852 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 456 # Number of squashed instructions skipped in execute +system.cpu.iew.memOrderViolationEvents 32 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 371 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 577 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 948 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 17934 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2892 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 735 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1086 # number of nop insts executed -system.cpu.iew.exec_refs 4598 # number of memory reference insts executed -system.cpu.iew.exec_branches 3866 # Number of branches executed -system.cpu.iew.exec_stores 1746 # Number of stores executed -system.cpu.iew.exec_rate 0.461692 # Inst execution rate -system.cpu.iew.wb_sent 17276 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 17101 # cumulative count of insts written-back -system.cpu.iew.wb_producers 7938 # num instructions producing a value -system.cpu.iew.wb_consumers 9273 # num instructions consuming a value +system.cpu.iew.exec_nop 1111 # number of nop insts executed +system.cpu.iew.exec_refs 4666 # number of memory reference insts executed +system.cpu.iew.exec_branches 3968 # Number of branches executed +system.cpu.iew.exec_stores 1774 # Number of stores executed +system.cpu.iew.exec_rate 0.494827 # Inst execution rate +system.cpu.iew.wb_sent 17667 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 17501 # cumulative count of insts written-back +system.cpu.iew.wb_producers 8169 # num instructions producing a value +system.cpu.iew.wb_consumers 9773 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.449624 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.856034 # average fanout of values written-back +system.cpu.iew.wb_rate 0.482879 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.835874 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 15175 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 5063 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 5911 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 475 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 838 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 27978 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.542390 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.183434 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 848 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 26319 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.576580 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.276701 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 20215 72.25% 72.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 4492 16.06% 88.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 1466 5.24% 93.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 768 2.75% 96.29% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 366 1.31% 97.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 259 0.93% 98.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 283 1.01% 99.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 42 0.15% 99.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 87 0.31% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 19114 72.62% 72.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 4004 15.21% 87.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 1216 4.62% 92.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 789 3.00% 95.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 371 1.41% 96.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 322 1.22% 98.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 345 1.31% 99.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 56 0.21% 99.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 102 0.39% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 27978 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 26319 # Number of insts commited each cycle system.cpu.commit.count 15175 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 3674 # Number of memory references committed @@ -251,48 +253,48 @@ system.cpu.commit.branches 3359 # Nu system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.int_insts 12186 # Number of committed integer instructions. system.cpu.commit.function_calls 187 # Number of function calls committed. -system.cpu.commit.bw_lim_events 87 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 102 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 47306 # The number of ROB reads -system.cpu.rob.rob_writes 41741 # The number of ROB writes -system.cpu.timesIdled 186 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 8813 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 46480 # The number of ROB reads +system.cpu.rob.rob_writes 43556 # The number of ROB writes +system.cpu.timesIdled 180 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 8563 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 14449 # Number of Instructions Simulated system.cpu.committedInsts_total 14449 # Number of Instructions Simulated -system.cpu.cpi 2.632293 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.632293 # CPI: Total CPI of All Threads -system.cpu.ipc 0.379897 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.379897 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 28130 # number of integer regfile reads -system.cpu.int_regfile_writes 15668 # number of integer regfile writes -system.cpu.misc_regfile_reads 6217 # number of misc regfile reads +system.cpu.cpi 2.508340 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.508340 # CPI: Total CPI of All Threads +system.cpu.ipc 0.398670 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.398670 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 28668 # number of integer regfile reads +system.cpu.int_regfile_writes 15998 # number of integer regfile writes +system.cpu.misc_regfile_reads 6298 # number of misc regfile reads system.cpu.misc_regfile_writes 569 # number of misc regfile writes system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 195.108308 # Cycle average of tags in use -system.cpu.icache.total_refs 3800 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 193.254298 # Cycle average of tags in use +system.cpu.icache.total_refs 4159 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 332 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 11.445783 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 12.527108 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 195.108308 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.095268 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 3800 # number of ReadReq hits -system.cpu.icache.demand_hits 3800 # number of demand (read+write) hits -system.cpu.icache.overall_hits 3800 # number of overall hits -system.cpu.icache.ReadReq_misses 456 # number of ReadReq misses -system.cpu.icache.demand_misses 456 # number of demand (read+write) misses -system.cpu.icache.overall_misses 456 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 15987000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 15987000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 15987000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 4256 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 4256 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 4256 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.107143 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.107143 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.107143 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 35059.210526 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 35059.210526 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 35059.210526 # average overall miss latency +system.cpu.icache.occ_blocks::0 193.254298 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.094362 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits 4159 # number of ReadReq hits +system.cpu.icache.demand_hits 4159 # number of demand (read+write) hits +system.cpu.icache.overall_hits 4159 # number of overall hits +system.cpu.icache.ReadReq_misses 462 # number of ReadReq misses +system.cpu.icache.demand_misses 462 # number of demand (read+write) misses +system.cpu.icache.overall_misses 462 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 16041500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 16041500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 16041500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses 4621 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses 4621 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses 4621 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate 0.099978 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate 0.099978 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate 0.099978 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency 34721.861472 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency 34721.861472 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 34721.861472 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -302,61 +304,61 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 124 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 124 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 124 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits 130 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 130 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 130 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses 332 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses 332 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses 332 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 11676000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 11676000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 11676000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 11653500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 11653500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 11653500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.078008 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.078008 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.078008 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 35168.674699 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 35168.674699 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 35168.674699 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate 0.071846 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate 0.071846 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate 0.071846 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 35100.903614 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 35100.903614 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 35100.903614 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 102.568719 # Cycle average of tags in use -system.cpu.dcache.total_refs 3697 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 102.161362 # Cycle average of tags in use +system.cpu.dcache.total_refs 3736 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 146 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 25.321918 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 25.589041 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 102.568719 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.025041 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 2657 # number of ReadReq hits +system.cpu.dcache.occ_blocks::0 102.161362 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.024942 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits 2696 # number of ReadReq hits system.cpu.dcache.WriteReq_hits 1034 # number of WriteReq hits system.cpu.dcache.SwapReq_hits 6 # number of SwapReq hits -system.cpu.dcache.demand_hits 3691 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 3691 # number of overall hits -system.cpu.dcache.ReadReq_misses 115 # number of ReadReq misses +system.cpu.dcache.demand_hits 3730 # number of demand (read+write) hits +system.cpu.dcache.overall_hits 3730 # number of overall hits +system.cpu.dcache.ReadReq_misses 114 # number of ReadReq misses system.cpu.dcache.WriteReq_misses 408 # number of WriteReq misses -system.cpu.dcache.demand_misses 523 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 523 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 4005000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 14642500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 18647500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 18647500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 2772 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses 522 # number of demand (read+write) misses +system.cpu.dcache.overall_misses 522 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 3994500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 14649500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency 18644000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 18644000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses 2810 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 1442 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SwapReq_accesses 6 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 4214 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 4214 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.041486 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses 4252 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses 4252 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate 0.040569 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate 0.282940 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.124110 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.124110 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 34826.086957 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 35888.480392 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 35654.875717 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 35654.875717 # average overall miss latency +system.cpu.dcache.demand_miss_rate 0.122766 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate 0.122766 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency 35039.473684 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 35905.637255 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency 35716.475096 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency 35716.475096 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -366,40 +368,40 @@ system.cpu.dcache.avg_blocked_cycles::no_targets no_value system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 52 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits 51 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits 325 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 377 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 377 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits 376 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 376 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses 63 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses 83 # number of WriteReq MSHR misses system.cpu.dcache.demand_mshr_misses 146 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses 146 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 2242500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 2973500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 5216000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 5216000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 2241500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 2985000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 5226500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 5226500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.022727 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate 0.022420 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate 0.057559 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.034646 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.034646 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35595.238095 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35825.301205 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 35726.027397 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 35726.027397 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate 0.034337 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate 0.034337 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35579.365079 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35963.855422 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 35797.945205 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 35797.945205 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 230.191737 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 228.417094 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 393 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.005089 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 230.191737 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.007025 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 228.417094 # Average occupied blocks per context +system.cpu.l2cache.occ_percent::0 0.006971 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits system.cpu.l2cache.overall_hits 2 # number of overall hits @@ -407,10 +409,10 @@ system.cpu.l2cache.ReadReq_misses 393 # nu system.cpu.l2cache.ReadExReq_misses 83 # number of ReadExReq misses system.cpu.l2cache.demand_misses 476 # number of demand (read+write) misses system.cpu.l2cache.overall_misses 476 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 13493000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 2870000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 16363000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 16363000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency 13475000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 2872000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency 16347000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency 16347000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses 395 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses 83 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses 478 # number of demand (read+write) accesses @@ -419,10 +421,10 @@ system.cpu.l2cache.ReadReq_miss_rate 0.994937 # mi system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate 0.995816 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate 0.995816 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34333.333333 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34578.313253 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34376.050420 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34376.050420 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 34287.531807 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34602.409639 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency 34342.436975 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency 34342.436975 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -439,19 +441,19 @@ system.cpu.l2cache.ReadExReq_mshr_misses 83 # nu system.cpu.l2cache.demand_mshr_misses 476 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses 476 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 12217500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 2610000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 14827500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 14827500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 12215000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 2608500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 14823500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 14823500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.994937 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate 0.995816 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate 0.995816 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31087.786260 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31445.783133 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31150.210084 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31150.210084 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31081.424936 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31427.710843 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31141.806723 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31141.806723 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini index 138610412..14fd2a611 100644 --- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini +++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini @@ -9,6 +9,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu0 cpu1 cpu2 cpu3 l2c membus physmem toL2Bus mem_mode=timing +memories=system.physmem physmem=system.physmem work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 @@ -456,7 +457,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/m5threads/bin/sparc/linux/test_atomic +executable=/chips/pd/randd/dist/test-progs/m5threads/bin/sparc/linux/test_atomic gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout index e4939da40..c3cdcc73a 100755 --- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout +++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout @@ -1,33 +1,33 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 10 2011 22:06:52 -gem5 started Jun 10 2011 22:06:57 -gem5 executing on zooks +gem5 compiled Jul 8 2011 15:08:13 +gem5 started Jul 8 2011 15:22:59 +gem5 executing on u200439-lin.austin.arm.com command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/o3-timing-mp -re tests/run.py build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/o3-timing-mp Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Init done [Iteration 1, Thread 2] Got lock [Iteration 1, Thread 2] Critical section done, previously next=0, now next=2 -[Iteration 1, Thread 3] Got lock -[Iteration 1, Thread 3] Critical section done, previously next=2, now next=3 [Iteration 1, Thread 1] Got lock -[Iteration 1, Thread 1] Critical section done, previously next=3, now next=1 +[Iteration 1, Thread 1] Critical section done, previously next=2, now next=1 +[Iteration 1, Thread 3] Got lock +[Iteration 1, Thread 3] Critical section done, previously next=1, now next=3 Iteration 1 completed -[Iteration 2, Thread 1] Got lock -[Iteration 2, Thread 1] Critical section done, previously next=0, now next=1 [Iteration 2, Thread 3] Got lock -[Iteration 2, Thread 3] Critical section done, previously next=1, now next=3 +[Iteration 2, Thread 3] Critical section done, previously next=0, now next=3 [Iteration 2, Thread 2] Got lock [Iteration 2, Thread 2] Critical section done, previously next=3, now next=2 +[Iteration 2, Thread 1] Got lock +[Iteration 2, Thread 1] Critical section done, previously next=2, now next=1 Iteration 2 completed +[Iteration 3, Thread 1] Got lock +[Iteration 3, Thread 1] Critical section done, previously next=0, now next=1 [Iteration 3, Thread 2] Got lock -[Iteration 3, Thread 2] Critical section done, previously next=0, now next=2 +[Iteration 3, Thread 2] Critical section done, previously next=1, now next=2 [Iteration 3, Thread 3] Got lock [Iteration 3, Thread 3] Critical section done, previously next=2, now next=3 -[Iteration 3, Thread 1] Got lock -[Iteration 3, Thread 1] Critical section done, previously next=3, now next=1 Iteration 3 completed [Iteration 4, Thread 1] Got lock [Iteration 4, Thread 1] Critical section done, previously next=0, now next=1 @@ -45,17 +45,17 @@ Iteration 4 completed Iteration 5 completed [Iteration 6, Thread 1] Got lock [Iteration 6, Thread 1] Critical section done, previously next=0, now next=1 -[Iteration 6, Thread 2] Got lock -[Iteration 6, Thread 2] Critical section done, previously next=1, now next=2 [Iteration 6, Thread 3] Got lock -[Iteration 6, Thread 3] Critical section done, previously next=2, now next=3 +[Iteration 6, Thread 3] Critical section done, previously next=1, now next=3 +[Iteration 6, Thread 2] Got lock +[Iteration 6, Thread 2] Critical section done, previously next=3, now next=2 Iteration 6 completed [Iteration 7, Thread 1] Got lock [Iteration 7, Thread 1] Critical section done, previously next=0, now next=1 -[Iteration 7, Thread 3] Got lock -[Iteration 7, Thread 3] Critical section done, previously next=1, now next=3 [Iteration 7, Thread 2] Got lock -[Iteration 7, Thread 2] Critical section done, previously next=3, now next=2 +[Iteration 7, Thread 2] Critical section done, previously next=1, now next=2 +[Iteration 7, Thread 3] Got lock +[Iteration 7, Thread 3] Critical section done, previously next=2, now next=3 Iteration 7 completed [Iteration 8, Thread 2] Got lock [Iteration 8, Thread 2] Critical section done, previously next=0, now next=2 @@ -64,19 +64,19 @@ Iteration 7 completed [Iteration 8, Thread 1] Got lock [Iteration 8, Thread 1] Critical section done, previously next=3, now next=1 Iteration 8 completed -[Iteration 9, Thread 3] Got lock -[Iteration 9, Thread 3] Critical section done, previously next=0, now next=3 -[Iteration 9, Thread 2] Got lock -[Iteration 9, Thread 2] Critical section done, previously next=3, now next=2 [Iteration 9, Thread 1] Got lock -[Iteration 9, Thread 1] Critical section done, previously next=2, now next=1 +[Iteration 9, Thread 1] Critical section done, previously next=0, now next=1 +[Iteration 9, Thread 2] Got lock +[Iteration 9, Thread 2] Critical section done, previously next=1, now next=2 +[Iteration 9, Thread 3] Got lock +[Iteration 9, Thread 3] Critical section done, previously next=2, now next=3 Iteration 9 completed +[Iteration 10, Thread 3] Got lock +[Iteration 10, Thread 3] Critical section done, previously next=0, now next=3 [Iteration 10, Thread 1] Got lock -[Iteration 10, Thread 1] Critical section done, previously next=0, now next=1 +[Iteration 10, Thread 1] Critical section done, previously next=3, now next=1 [Iteration 10, Thread 2] Got lock [Iteration 10, Thread 2] Critical section done, previously next=1, now next=2 -[Iteration 10, Thread 3] Got lock -[Iteration 10, Thread 3] Critical section done, previously next=2, now next=3 Iteration 10 completed PASSED :-) -Exiting @ tick 117354500 because target called exit() +Exiting @ tick 104204500 because target called exit() diff --git a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt index 0e7434ae8..80611aaa5 100644 --- a/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt +++ b/tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt @@ -1,693 +1,698 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000117 # Number of seconds simulated -sim_ticks 117354500 # Number of ticks simulated +sim_seconds 0.000104 # Number of seconds simulated +sim_ticks 104204500 # Number of ticks simulated sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 90067 # Simulator instruction rate (inst/s) -host_tick_rate 9199514 # Simulator tick rate (ticks/s) -host_mem_usage 171836 # Number of bytes of host memory used -host_seconds 12.76 # Real time elapsed on the host -sim_insts 1148940 # Number of instructions simulated +host_inst_rate 98850 # Simulator instruction rate (inst/s) +host_tick_rate 10137150 # Simulator tick rate (ticks/s) +host_mem_usage 260004 # Number of bytes of host memory used +host_seconds 10.28 # Real time elapsed on the host +sim_insts 1016120 # Number of instructions simulated system.cpu0.workload.num_syscalls 89 # Number of system calls -system.cpu0.numCycles 234710 # number of cpu cycles simulated +system.cpu0.numCycles 208410 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.BPredUnit.lookups 91844 # Number of BP lookups -system.cpu0.BPredUnit.condPredicted 90062 # Number of conditional branches predicted -system.cpu0.BPredUnit.condIncorrect 1094 # Number of conditional branches incorrect -system.cpu0.BPredUnit.BTBLookups 91032 # Number of BTB lookups -system.cpu0.BPredUnit.BTBHits 88645 # Number of BTB hits +system.cpu0.BPredUnit.lookups 80590 # Number of BP lookups +system.cpu0.BPredUnit.condPredicted 78618 # Number of conditional branches predicted +system.cpu0.BPredUnit.condIncorrect 1041 # Number of conditional branches incorrect +system.cpu0.BPredUnit.BTBLookups 79686 # Number of BTB lookups +system.cpu0.BPredUnit.BTBHits 77242 # Number of BTB hits system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.BPredUnit.usedRAS 397 # Number of times the RAS was used to get a target. +system.cpu0.BPredUnit.usedRAS 414 # Number of times the RAS was used to get a target. system.cpu0.BPredUnit.RASInCorrect 132 # Number of incorrect RAS predictions. -system.cpu0.fetch.icacheStallCycles 5189 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 547166 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 91844 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 89042 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 180871 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1241 # Number of cycles fetch has spent squashing -system.cpu0.fetch.MiscStallCycles 39 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.CacheLines 5189 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 438 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.rateDist::samples 216259 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 2.530142 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.183723 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 16537 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 478571 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 80590 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 77656 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 158025 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 3261 # Number of cycles fetch has spent squashing +system.cpu0.fetch.BlockedCycles 12770 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 1227 # Number of stall cycles due to pending traps +system.cpu0.fetch.CacheLines 5521 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 450 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.rateDist::samples 190625 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 2.510536 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.192774 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 35388 16.36% 16.36% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 90011 41.62% 57.99% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 494 0.23% 58.21% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 785 0.36% 58.58% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 592 0.27% 58.85% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 86207 39.86% 98.71% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 812 0.38% 99.09% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 223 0.10% 99.19% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 1747 0.81% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 32600 17.10% 17.10% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 78462 41.16% 58.26% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 548 0.29% 58.55% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 1030 0.54% 59.09% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 642 0.34% 59.43% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 74529 39.10% 98.52% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 776 0.41% 98.93% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 250 0.13% 99.06% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 1788 0.94% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 216259 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.391308 # Number of branch fetches per cycle -system.cpu0.fetch.rate 2.331243 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 20008 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 13629 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 180385 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 202 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 2035 # Number of cycles decode is squashing -system.cpu0.decode.DecodedInsts 546099 # Number of instructions handled by decode -system.cpu0.rename.SquashCycles 2035 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 20667 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 1184 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 11729 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 179959 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 685 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 543550 # Number of instructions processed by rename -system.cpu0.rename.IQFullEvents 6 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 277 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.RenamedOperands 370143 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 1084537 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 1084537 # Number of integer rename lookups -system.cpu0.rename.CommittedMaps 360120 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 10023 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 796 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 810 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 3593 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 175288 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 88379 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 85877 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 85749 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 454609 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 808 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 453072 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 92 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 8037 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 6746 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 249 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 216259 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 2.095043 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.058701 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 190625 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.386690 # Number of branch fetches per cycle +system.cpu0.fetch.rate 2.296296 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 16909 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 14231 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 157125 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 299 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 2061 # Number of cycles decode is squashing +system.cpu0.decode.DecodedInsts 476395 # Number of instructions handled by decode +system.cpu0.rename.SquashCycles 2061 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 17525 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 1226 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 12360 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 156835 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 618 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 473886 # Number of instructions processed by rename +system.cpu0.rename.IQFullEvents 5 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 214 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.RenamedOperands 323802 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 945058 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 945058 # Number of integer rename lookups +system.cpu0.rename.CommittedMaps 313352 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 10450 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 798 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 821 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 3525 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 151968 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 76679 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 74216 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 74111 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 396475 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 848 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 394743 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 99 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 8405 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 7242 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 289 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 190625 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 2.070783 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.085610 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 33498 15.49% 15.49% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 5606 2.59% 18.08% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 87868 40.63% 58.71% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 86822 40.15% 98.86% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 1462 0.68% 99.54% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 715 0.33% 99.87% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 184 0.09% 99.95% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 95 0.04% 100.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 9 0.00% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 31655 16.61% 16.61% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 5136 2.69% 19.30% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 75959 39.85% 59.15% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 75246 39.47% 98.62% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 1565 0.82% 99.44% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 775 0.41% 99.85% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 215 0.11% 99.96% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 66 0.03% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 8 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 216259 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 190625 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 33 15.71% 15.71% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 15.71% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 15.71% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 15.71% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 15.71% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 15.71% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 15.71% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 15.71% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 15.71% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 15.71% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 15.71% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 15.71% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 15.71% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 15.71% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 15.71% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 15.71% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 15.71% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 15.71% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 15.71% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 15.71% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 15.71% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 15.71% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 15.71% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 15.71% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 15.71% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 15.71% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 15.71% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 15.71% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 15.71% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 75 35.71% 51.43% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 102 48.57% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 35 15.42% 15.42% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 15.42% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 15.42% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 15.42% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 15.42% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 15.42% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 15.42% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 15.42% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 15.42% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 15.42% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 15.42% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 15.42% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 15.42% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 15.42% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 15.42% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 15.42% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 15.42% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 15.42% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 15.42% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 15.42% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 15.42% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 15.42% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 15.42% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 15.42% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 15.42% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 15.42% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 15.42% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 15.42% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 15.42% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 74 32.60% 48.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 118 51.98% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 190073 41.95% 41.95% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 0 0.00% 41.95% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 41.95% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 41.95% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 41.95% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 41.95% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 41.95% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 41.95% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 41.95% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 41.95% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 41.95% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 41.95% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 41.95% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 41.95% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 41.95% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 41.95% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 41.95% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 41.95% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 41.95% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 41.95% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 41.95% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 41.95% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 41.95% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 41.95% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 41.95% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 41.95% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 41.95% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 41.95% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 41.95% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 175045 38.64% 80.59% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 87954 19.41% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 166789 42.25% 42.25% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.25% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.25% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.25% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.25% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.25% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.25% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.25% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.25% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.25% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.25% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.25% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.25% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.25% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.25% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.25% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.25% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.25% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.25% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.25% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.25% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.25% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.25% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.25% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.25% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.25% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.25% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.25% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.25% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 151686 38.43% 80.68% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 76268 19.32% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 453072 # Type of FU issued -system.cpu0.iq.rate 1.930348 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 210 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.000464 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 1122705 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 463496 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 451578 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.FU_type_0::total 394743 # Type of FU issued +system.cpu0.iq.rate 1.894069 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 227 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.000575 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 980437 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 405782 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 393268 # Number of integer instruction queue wakeup accesses system.cpu0.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu0.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu0.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 453282 # Number of integer alu accesses +system.cpu0.iq.int_alu_accesses 394970 # Number of integer alu accesses system.cpu0.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 85551 # Number of loads that had data forwarded from stores +system.cpu0.iew.lsq.thread0.forwLoads 73850 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1644 # Number of loads squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1708 # Number of loads squashed system.cpu0.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 44 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 1051 # Number of stores squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 55 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 1043 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu0.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu0.iew.lsq.thread0.cacheBlocked 18 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 2035 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 809 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 21 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 541811 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 507 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 175288 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 88379 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 716 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 21 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewSquashCycles 2061 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 862 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 25 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 472051 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 355 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 151968 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 76679 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 747 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 23 # Number of times the IQ has become full, causing a stall system.cpu0.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 44 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 486 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 773 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 1259 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 452172 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 174750 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 900 # Number of squashed instructions skipped in execute +system.cpu0.iew.memOrderViolationEvents 55 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 456 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 747 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 1203 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 393858 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 151382 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 885 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 86394 # number of nop insts executed -system.cpu0.iew.exec_refs 262594 # number of memory reference insts executed -system.cpu0.iew.exec_branches 89995 # Number of branches executed -system.cpu0.iew.exec_stores 87844 # Number of stores executed -system.cpu0.iew.exec_rate 1.926514 # Inst execution rate -system.cpu0.iew.wb_sent 451822 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 451578 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 267957 # num instructions producing a value -system.cpu0.iew.wb_consumers 269862 # num instructions consuming a value +system.cpu0.iew.exec_nop 74728 # number of nop insts executed +system.cpu0.iew.exec_refs 227540 # number of memory reference insts executed +system.cpu0.iew.exec_branches 78360 # Number of branches executed +system.cpu0.iew.exec_stores 76158 # Number of stores executed +system.cpu0.iew.exec_rate 1.889823 # Inst execution rate +system.cpu0.iew.wb_sent 393529 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 393268 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 233079 # num instructions producing a value +system.cpu0.iew.wb_consumers 235200 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 1.923983 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.992941 # average fanout of values written-back +system.cpu0.iew.wb_rate 1.886992 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.990982 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitCommittedInsts 532525 # The number of committed instructions -system.cpu0.commit.commitSquashedInsts 9290 # The number of squashed insts skipped by commit +system.cpu0.commit.commitCommittedInsts 462373 # The number of committed instructions +system.cpu0.commit.commitSquashedInsts 9639 # The number of squashed insts skipped by commit system.cpu0.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 1094 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 214241 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 2.485635 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 2.121796 # Number of insts commited each cycle +system.cpu0.commit.branchMispredicts 1041 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 188581 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 2.451854 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 2.134496 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 33798 15.78% 15.78% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 90322 42.16% 57.93% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 2486 1.16% 59.10% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 740 0.35% 59.44% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 737 0.34% 59.78% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 85412 39.87% 99.65% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 444 0.21% 99.86% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 77 0.04% 99.89% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 225 0.11% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 32178 17.06% 17.06% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 78251 41.49% 58.56% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 2149 1.14% 59.70% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 733 0.39% 60.09% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 648 0.34% 60.43% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 73572 39.01% 99.44% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 474 0.25% 99.69% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 279 0.15% 99.84% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 297 0.16% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 214241 # Number of insts commited each cycle -system.cpu0.commit.count 532525 # Number of instructions committed +system.cpu0.commit.committed_per_cycle::total 188581 # Number of insts commited each cycle +system.cpu0.commit.count 462373 # Number of instructions committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 260972 # Number of memory references committed -system.cpu0.commit.loads 173644 # Number of loads committed +system.cpu0.commit.refs 225896 # Number of memory references committed +system.cpu0.commit.loads 150260 # Number of loads committed system.cpu0.commit.membars 84 # Number of memory barriers committed -system.cpu0.commit.branches 89216 # Number of branches committed +system.cpu0.commit.branches 77524 # Number of branches committed system.cpu0.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 358450 # Number of committed integer instructions. +system.cpu0.commit.int_insts 311682 # Number of committed integer instructions. system.cpu0.commit.function_calls 223 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 225 # number cycles where commit BW limit reached +system.cpu0.commit.bw_lim_events 297 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 754670 # The number of ROB reads -system.cpu0.rob.rob_writes 1085676 # The number of ROB writes -system.cpu0.timesIdled 336 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 18451 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.committedInsts 446494 # Number of Instructions Simulated -system.cpu0.committedInsts_total 446494 # Number of Instructions Simulated -system.cpu0.cpi 0.525673 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 0.525673 # CPI: Total CPI of All Threads -system.cpu0.ipc 1.902322 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 1.902322 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 809682 # number of integer regfile reads -system.cpu0.int_regfile_writes 364308 # number of integer regfile writes +system.cpu0.rob.rob_reads 659135 # The number of ROB reads +system.cpu0.rob.rob_writes 946098 # The number of ROB writes +system.cpu0.timesIdled 320 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 17785 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.committedInsts 388034 # Number of Instructions Simulated +system.cpu0.committedInsts_total 388034 # Number of Instructions Simulated +system.cpu0.cpi 0.537092 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 0.537092 # CPI: Total CPI of All Threads +system.cpu0.ipc 1.861878 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 1.861878 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 704687 # number of integer regfile reads +system.cpu0.int_regfile_writes 317694 # number of integer regfile writes system.cpu0.fp_regfile_reads 192 # number of floating regfile reads -system.cpu0.misc_regfile_reads 264341 # number of misc regfile reads +system.cpu0.misc_regfile_reads 229306 # number of misc regfile reads system.cpu0.misc_regfile_writes 564 # number of misc regfile writes -system.cpu0.icache.replacements 291 # number of replacements -system.cpu0.icache.tagsinuse 245.354699 # Cycle average of tags in use -system.cpu0.icache.total_refs 4480 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 576 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 7.777778 # Average number of references to valid blocks. +system.cpu0.icache.replacements 294 # number of replacements +system.cpu0.icache.tagsinuse 244.310261 # Cycle average of tags in use +system.cpu0.icache.total_refs 4819 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 581 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 8.294320 # Average number of references to valid blocks. system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::0 245.354699 # Average occupied blocks per context -system.cpu0.icache.occ_percent::0 0.479208 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits 4480 # number of ReadReq hits -system.cpu0.icache.demand_hits 4480 # number of demand (read+write) hits -system.cpu0.icache.overall_hits 4480 # number of overall hits -system.cpu0.icache.ReadReq_misses 709 # number of ReadReq misses -system.cpu0.icache.demand_misses 709 # number of demand (read+write) misses -system.cpu0.icache.overall_misses 709 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency 27352000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency 27352000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency 27352000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses 5189 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses 5189 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses 5189 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate 0.136635 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate 0.136635 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate 0.136635 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency 38578.279267 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency 38578.279267 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency 38578.279267 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 16000 # number of cycles access was blocked +system.cpu0.icache.occ_blocks::0 244.310261 # Average occupied blocks per context +system.cpu0.icache.occ_percent::0 0.477168 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits 4819 # number of ReadReq hits +system.cpu0.icache.demand_hits 4819 # number of demand (read+write) hits +system.cpu0.icache.overall_hits 4819 # number of overall hits +system.cpu0.icache.ReadReq_misses 702 # number of ReadReq misses +system.cpu0.icache.demand_misses 702 # number of demand (read+write) misses +system.cpu0.icache.overall_misses 702 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency 27601000 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency 27601000 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency 27601000 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses 5521 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses 5521 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses 5521 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate 0.127151 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate 0.127151 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate 0.127151 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency 39317.663818 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency 39317.663818 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency 39317.663818 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 15500 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 16000 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 15500 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed system.cpu0.icache.writebacks 0 # number of writebacks -system.cpu0.icache.ReadReq_mshr_hits 132 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits 132 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits 132 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses 577 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses 577 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses 577 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_hits 120 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits 120 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits 120 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses 582 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses 582 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses 582 # number of overall MSHR misses system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency 21152000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency 21152000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency 21152000 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency 21371000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency 21371000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency 21371000 # number of overall MSHR miss cycles system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate 0.111197 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate 0.111197 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate 0.111197 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency 36658.578856 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency 36658.578856 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency 36658.578856 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate 0.105416 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate 0.105416 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate 0.105416 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency 36719.931271 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency 36719.931271 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency 36719.931271 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.dcache.replacements 9 # number of replacements -system.cpu0.dcache.tagsinuse 140.104909 # Cycle average of tags in use -system.cpu0.dcache.total_refs 105362 # Total number of references to valid blocks. +system.cpu0.dcache.tagsinuse 139.593674 # Cycle average of tags in use +system.cpu0.dcache.total_refs 95831 # Total number of references to valid blocks. system.cpu0.dcache.sampled_refs 174 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 605.528736 # Average number of references to valid blocks. +system.cpu0.dcache.avg_refs 550.752874 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::0 141.224248 # Average occupied blocks per context -system.cpu0.dcache.occ_blocks::1 -1.119339 # Average occupied blocks per context -system.cpu0.dcache.occ_percent::0 0.275829 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::1 -0.002186 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits 88681 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits 86746 # number of WriteReq hits -system.cpu0.dcache.SwapReq_hits 16 # number of SwapReq hits -system.cpu0.dcache.demand_hits 175427 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits 175427 # number of overall hits -system.cpu0.dcache.ReadReq_misses 467 # number of ReadReq misses +system.cpu0.dcache.occ_blocks::0 140.420812 # Average occupied blocks per context +system.cpu0.dcache.occ_blocks::1 -0.827138 # Average occupied blocks per context +system.cpu0.dcache.occ_percent::0 0.274259 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::1 -0.001616 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits 76983 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits 75054 # number of WriteReq hits +system.cpu0.dcache.SwapReq_hits 23 # number of SwapReq hits +system.cpu0.dcache.demand_hits 152037 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits 152037 # number of overall hits +system.cpu0.dcache.ReadReq_misses 495 # number of ReadReq misses system.cpu0.dcache.WriteReq_misses 540 # number of WriteReq misses -system.cpu0.dcache.SwapReq_misses 26 # number of SwapReq misses -system.cpu0.dcache.demand_misses 1007 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses 1007 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency 13105000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency 24852484 # number of WriteReq miss cycles -system.cpu0.dcache.SwapReq_miss_latency 437000 # number of SwapReq miss cycles -system.cpu0.dcache.demand_miss_latency 37957484 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency 37957484 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses 89148 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses 87286 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SwapReq_misses 19 # number of SwapReq misses +system.cpu0.dcache.demand_misses 1035 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses 1035 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency 13943500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency 24690984 # number of WriteReq miss cycles +system.cpu0.dcache.SwapReq_miss_latency 375000 # number of SwapReq miss cycles +system.cpu0.dcache.demand_miss_latency 38634484 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency 38634484 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses 77478 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses 75594 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses 42 # number of SwapReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses 176434 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses 176434 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate 0.005238 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate 0.006187 # miss rate for WriteReq accesses -system.cpu0.dcache.SwapReq_miss_rate 0.619048 # miss rate for SwapReq accesses -system.cpu0.dcache.demand_miss_rate 0.005708 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate 0.005708 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency 28062.098501 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency 46023.118519 # average WriteReq miss latency -system.cpu0.dcache.SwapReq_avg_miss_latency 16807.692308 # average SwapReq miss latency -system.cpu0.dcache.demand_avg_miss_latency 37693.628600 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency 37693.628600 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 173500 # number of cycles access was blocked +system.cpu0.dcache.demand_accesses 153072 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses 153072 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate 0.006389 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate 0.007143 # miss rate for WriteReq accesses +system.cpu0.dcache.SwapReq_miss_rate 0.452381 # miss rate for SwapReq accesses +system.cpu0.dcache.demand_miss_rate 0.006762 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate 0.006762 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency 28168.686869 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency 45724.044444 # average WriteReq miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency 19736.842105 # average SwapReq miss latency +system.cpu0.dcache.demand_avg_miss_latency 37328.003865 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency 37328.003865 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 180500 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 26 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 21 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 6673.076923 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 8595.238095 # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed system.cpu0.dcache.writebacks 6 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits 284 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits 365 # number of WriteReq MSHR hits -system.cpu0.dcache.demand_mshr_hits 649 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits 649 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses 183 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses 175 # number of WriteReq MSHR misses -system.cpu0.dcache.SwapReq_mshr_misses 26 # number of SwapReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_hits 308 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits 369 # number of WriteReq MSHR hits +system.cpu0.dcache.demand_mshr_hits 677 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits 677 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses 187 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses 171 # number of WriteReq MSHR misses +system.cpu0.dcache.SwapReq_mshr_misses 19 # number of SwapReq MSHR misses system.cpu0.dcache.demand_mshr_misses 358 # number of demand (read+write) MSHR misses system.cpu0.dcache.overall_mshr_misses 358 # number of overall MSHR misses system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency 5054000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency 6424000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_latency 359000 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency 11478000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency 11478000 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency 5126500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency 6255000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency 318000 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency 11381500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency 11381500 # number of overall MSHR miss cycles system.cpu0.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate 0.002053 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate 0.002005 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SwapReq_mshr_miss_rate 0.619048 # mshr miss rate for SwapReq accesses -system.cpu0.dcache.demand_mshr_miss_rate 0.002029 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate 0.002029 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 27617.486339 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 36708.571429 # average WriteReq mshr miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency 13807.692308 # average SwapReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency 32061.452514 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency 32061.452514 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_mshr_miss_rate 0.002414 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate 0.002262 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SwapReq_mshr_miss_rate 0.452381 # mshr miss rate for SwapReq accesses +system.cpu0.dcache.demand_mshr_miss_rate 0.002339 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate 0.002339 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 27414.438503 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 36578.947368 # average WriteReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency 16736.842105 # average SwapReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency 31791.899441 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency 31791.899441 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.numCycles 199395 # number of cpu cycles simulated +system.cpu1.numCycles 174065 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.BPredUnit.lookups 54492 # Number of BP lookups -system.cpu1.BPredUnit.condPredicted 52165 # Number of conditional branches predicted -system.cpu1.BPredUnit.condIncorrect 1102 # Number of conditional branches incorrect -system.cpu1.BPredUnit.BTBLookups 53937 # Number of BTB lookups -system.cpu1.BPredUnit.BTBHits 51730 # Number of BTB hits +system.cpu1.BPredUnit.lookups 53680 # Number of BP lookups +system.cpu1.BPredUnit.condPredicted 51050 # Number of conditional branches predicted +system.cpu1.BPredUnit.condIncorrect 1082 # Number of conditional branches incorrect +system.cpu1.BPredUnit.BTBLookups 49680 # Number of BTB lookups +system.cpu1.BPredUnit.BTBHits 47696 # Number of BTB hits system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.BPredUnit.usedRAS 504 # Number of times the RAS was used to get a target. +system.cpu1.BPredUnit.usedRAS 674 # Number of times the RAS was used to get a target. system.cpu1.BPredUnit.RASInCorrect 232 # Number of incorrect RAS predictions. -system.cpu1.fetch.icacheStallCycles 21267 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 303560 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 54492 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 52234 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 111140 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 1177 # Number of cycles fetch has spent squashing -system.cpu1.fetch.MiscStallCycles 22 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.CacheLines 21267 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 240 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 196288 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.546503 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.023941 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 25860 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 302062 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 53680 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 48370 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 105407 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 3162 # Number of cycles fetch has spent squashing +system.cpu1.fetch.BlockedCycles 31070 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.NoActiveThreadStallCycles 6439 # Number of stall cycles due to no active thread to fetch from +system.cpu1.fetch.PendingTrapStallCycles 670 # Number of stall cycles due to pending traps +system.cpu1.fetch.CacheLines 17358 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 181 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 171455 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.761757 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.155300 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 85148 43.38% 43.38% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 57550 29.32% 72.70% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 7358 3.75% 76.45% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 2678 1.36% 77.81% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1913 0.97% 78.79% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 37446 19.08% 97.86% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 2461 1.25% 99.12% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 260 0.13% 99.25% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 1474 0.75% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 66048 38.52% 38.52% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 53266 31.07% 69.59% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 5206 3.04% 72.63% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 3414 1.99% 74.62% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 592 0.35% 74.96% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 38163 22.26% 97.22% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 1383 0.81% 98.03% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 403 0.24% 98.26% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 2980 1.74% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 196288 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.273287 # Number of branch fetches per cycle -system.cpu1.fetch.rate 1.522405 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 56178 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 20903 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 104877 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 5862 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 1747 # Number of cycles decode is squashing -system.cpu1.decode.DecodedInsts 302339 # Number of instructions handled by decode -system.cpu1.rename.SquashCycles 1747 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 56804 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 7350 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 12853 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 110244 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 569 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 300619 # Number of instructions processed by rename -system.cpu1.rename.IQFullEvents 47 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 45 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.RenamedOperands 206640 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 572225 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 572225 # Number of integer rename lookups -system.cpu1.rename.CommittedMaps 198555 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 8085 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 945 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 1003 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 2692 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 86261 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 40322 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 42289 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 35840 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 247735 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 7474 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 252580 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 2 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 6388 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 5920 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 555 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 196288 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 1.286783 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.284176 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 171455 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.308391 # Number of branch fetches per cycle +system.cpu1.fetch.rate 1.735340 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 30212 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 28102 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 100316 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 4382 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 2004 # Number of cycles decode is squashing +system.cpu1.decode.DecodedInsts 299336 # Number of instructions handled by decode +system.cpu1.rename.SquashCycles 2004 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 30858 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 13502 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 13779 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 96392 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 8481 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 297385 # Number of instructions processed by rename +system.cpu1.rename.IQFullEvents 26 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 56 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.RenamedOperands 208391 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 574206 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 574206 # Number of integer rename lookups +system.cpu1.rename.CommittedMaps 198747 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 9644 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 1073 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 1204 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 11164 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 85765 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 40966 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 40880 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 36423 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 247992 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 5619 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 250090 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 3 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 8378 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 7678 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 648 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 171455 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 1.458633 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.309488 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 81418 41.48% 41.48% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 28257 14.40% 55.87% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 42150 21.47% 77.35% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 39998 20.38% 97.73% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 2642 1.35% 99.07% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1578 0.80% 99.88% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 154 0.08% 99.95% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 81 0.04% 99.99% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 10 0.01% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 63066 36.78% 36.78% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 20362 11.88% 48.66% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 40913 23.86% 72.52% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 42366 24.71% 97.23% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 3338 1.95% 99.18% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1156 0.67% 99.85% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 160 0.09% 99.95% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 40 0.02% 99.97% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 54 0.03% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 196288 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 171455 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 11 5.79% 5.79% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 5.79% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 5.79% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 5.79% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 5.79% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 5.79% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 5.79% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 5.79% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 5.79% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 5.79% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 5.79% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 5.79% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 5.79% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 5.79% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 5.79% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 5.79% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 5.79% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 5.79% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 5.79% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 5.79% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 5.79% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 5.79% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 5.79% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 5.79% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 5.79% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 5.79% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 5.79% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.79% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 5.79% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 48 25.26% 31.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 131 68.95% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 12 4.58% 4.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 4.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 4.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 4.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 4.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 4.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 4.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 4.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 4.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 4.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 4.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 4.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 4.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 4.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 4.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 4.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 4.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 4.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 4.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 4.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 4.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 4.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 4.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 4.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 4.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 4.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 4.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 4.58% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 60 22.90% 27.48% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 190 72.52% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 120684 47.78% 47.78% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 0 0.00% 47.78% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.78% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.78% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.78% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.78% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.78% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.78% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.78% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.78% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.78% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.78% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.78% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.78% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 47.78% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.78% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.78% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 47.78% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 47.78% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.78% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.78% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.78% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.78% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.78% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.78% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 47.78% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.78% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.78% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.78% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 91955 36.41% 84.19% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 39941 15.81% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 120097 48.02% 48.02% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 0 0.00% 48.02% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 48.02% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 48.02% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 48.02% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 48.02% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 48.02% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 48.02% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 48.02% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 48.02% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 48.02% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 48.02% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 48.02% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 48.02% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 48.02% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 48.02% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 48.02% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 48.02% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.02% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 48.02% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.02% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.02% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.02% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.02% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.02% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.02% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 48.02% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.02% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.02% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 89434 35.76% 83.78% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 40559 16.22% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 252580 # Type of FU issued -system.cpu1.iq.rate 1.266732 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 190 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.000752 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 701640 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 261627 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 251253 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.FU_type_0::total 250090 # Type of FU issued +system.cpu1.iq.rate 1.436762 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 262 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.001048 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 671900 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 262020 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 248980 # Number of integer instruction queue wakeup accesses system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu1.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 252770 # Number of integer alu accesses +system.cpu1.iq.int_alu_accesses 250352 # Number of integer alu accesses system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 35691 # Number of loads that had data forwarded from stores +system.cpu1.iew.lsq.thread0.forwLoads 36283 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 1436 # Number of loads squashed +system.cpu1.iew.lsq.thread0.squashedLoads 1818 # Number of loads squashed system.cpu1.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 30 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 758 # Number of stores squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 31 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 869 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu1.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu1.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 1747 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 1477 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 46 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 298452 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 533 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 86261 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 40322 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 920 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 42 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewSquashCycles 2004 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 1662 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 52 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 295488 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 312 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 85765 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 40966 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 1034 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 50 # Number of times the IQ has become full, causing a stall system.cpu1.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 30 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 1025 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 178 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 1203 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 251613 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 85566 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 967 # Number of squashed instructions skipped in execute +system.cpu1.iew.memOrderViolationEvents 31 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 608 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 631 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 1239 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 249342 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 84980 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 748 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 43243 # number of nop insts executed -system.cpu1.iew.exec_refs 125476 # number of memory reference insts executed -system.cpu1.iew.exec_branches 52279 # Number of branches executed -system.cpu1.iew.exec_stores 39910 # Number of stores executed -system.cpu1.iew.exec_rate 1.261882 # Inst execution rate -system.cpu1.iew.wb_sent 251386 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 251253 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 141847 # num instructions producing a value -system.cpu1.iew.wb_consumers 145498 # num instructions consuming a value +system.cpu1.iew.exec_nop 41877 # number of nop insts executed +system.cpu1.iew.exec_refs 125494 # number of memory reference insts executed +system.cpu1.iew.exec_branches 50909 # Number of branches executed +system.cpu1.iew.exec_stores 40514 # Number of stores executed +system.cpu1.iew.exec_rate 1.432465 # Inst execution rate +system.cpu1.iew.wb_sent 249148 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 248980 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 142220 # num instructions producing a value +system.cpu1.iew.wb_consumers 146685 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 1.260077 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.974907 # average fanout of values written-back +system.cpu1.iew.wb_rate 1.430385 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.969561 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitCommittedInsts 290439 # The number of committed instructions -system.cpu1.commit.commitSquashedInsts 8011 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 6919 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 1102 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 187821 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 1.546361 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.941498 # Number of insts commited each cycle +system.cpu1.commit.commitCommittedInsts 285859 # The number of committed instructions +system.cpu1.commit.commitSquashedInsts 9624 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 4971 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 1082 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 163013 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 1.753596 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 2.061352 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 80077 42.63% 42.63% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 52511 27.96% 70.59% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 7488 3.99% 74.58% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 7738 4.12% 78.70% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 2462 1.31% 80.01% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 36475 19.42% 99.43% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 459 0.24% 99.67% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 127 0.07% 99.74% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 484 0.26% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 61328 37.62% 37.62% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 49151 30.15% 67.77% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 5963 3.66% 71.43% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 5859 3.59% 75.03% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1587 0.97% 76.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 36625 22.47% 98.47% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 608 0.37% 98.84% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 1052 0.65% 99.48% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 840 0.52% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 187821 # Number of insts commited each cycle -system.cpu1.commit.count 290439 # Number of instructions committed +system.cpu1.commit.committed_per_cycle::total 163013 # Number of insts commited each cycle +system.cpu1.commit.count 285859 # Number of instructions committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 124389 # Number of memory references committed -system.cpu1.commit.loads 84825 # Number of loads committed -system.cpu1.commit.membars 6207 # Number of memory barriers committed -system.cpu1.commit.branches 51732 # Number of branches committed +system.cpu1.commit.refs 124044 # Number of memory references committed +system.cpu1.commit.loads 83947 # Number of loads committed +system.cpu1.commit.membars 4259 # Number of memory barriers committed +system.cpu1.commit.branches 50321 # Number of branches committed system.cpu1.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 198246 # Number of committed integer instructions. +system.cpu1.commit.int_insts 196488 # Number of committed integer instructions. system.cpu1.commit.function_calls 322 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 484 # number cycles where commit BW limit reached +system.cpu1.commit.bw_lim_events 840 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 485200 # The number of ROB reads -system.cpu1.rob.rob_writes 598649 # The number of ROB writes -system.cpu1.timesIdled 276 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 3107 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.committedInsts 241708 # Number of Instructions Simulated -system.cpu1.committedInsts_total 241708 # Number of Instructions Simulated -system.cpu1.cpi 0.824942 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 0.824942 # CPI: Total CPI of All Threads -system.cpu1.ipc 1.212207 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 1.212207 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 433901 # number of integer regfile reads -system.cpu1.int_regfile_writes 201135 # number of integer regfile writes +system.cpu1.rob.rob_reads 457069 # The number of ROB reads +system.cpu1.rob.rob_writes 592971 # The number of ROB writes +system.cpu1.timesIdled 229 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 2610 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.committedInsts 240487 # Number of Instructions Simulated +system.cpu1.committedInsts_total 240487 # Number of Instructions Simulated +system.cpu1.cpi 0.723802 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 0.723802 # CPI: Total CPI of All Threads +system.cpu1.ipc 1.381593 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 1.381593 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 434614 # number of integer regfile reads +system.cpu1.int_regfile_writes 202365 # number of integer regfile writes system.cpu1.fp_regfile_writes 64 # number of floating regfile writes -system.cpu1.misc_regfile_reads 127021 # number of misc regfile reads +system.cpu1.misc_regfile_reads 127051 # number of misc regfile reads system.cpu1.misc_regfile_writes 646 # number of misc regfile writes -system.cpu1.icache.replacements 335 # number of replacements -system.cpu1.icache.tagsinuse 81.445548 # Cycle average of tags in use -system.cpu1.icache.total_refs 20780 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 442 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 47.013575 # Average number of references to valid blocks. +system.cpu1.icache.replacements 317 # number of replacements +system.cpu1.icache.tagsinuse 84.485339 # Cycle average of tags in use +system.cpu1.icache.total_refs 16887 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 427 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 39.548009 # Average number of references to valid blocks. system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::0 81.445548 # Average occupied blocks per context -system.cpu1.icache.occ_percent::0 0.159073 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits 20780 # number of ReadReq hits -system.cpu1.icache.demand_hits 20780 # number of demand (read+write) hits -system.cpu1.icache.overall_hits 20780 # number of overall hits -system.cpu1.icache.ReadReq_misses 487 # number of ReadReq misses -system.cpu1.icache.demand_misses 487 # number of demand (read+write) misses -system.cpu1.icache.overall_misses 487 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency 7348000 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency 7348000 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency 7348000 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses 21267 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses 21267 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses 21267 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate 0.022899 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate 0.022899 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate 0.022899 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency 15088.295688 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency 15088.295688 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency 15088.295688 # average overall miss latency +system.cpu1.icache.occ_blocks::0 84.485339 # Average occupied blocks per context +system.cpu1.icache.occ_percent::0 0.165010 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits 16887 # number of ReadReq hits +system.cpu1.icache.demand_hits 16887 # number of demand (read+write) hits +system.cpu1.icache.overall_hits 16887 # number of overall hits +system.cpu1.icache.ReadReq_misses 471 # number of ReadReq misses +system.cpu1.icache.demand_misses 471 # number of demand (read+write) misses +system.cpu1.icache.overall_misses 471 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency 7156000 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency 7156000 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency 7156000 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses 17358 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses 17358 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses 17358 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate 0.027134 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate 0.027134 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate 0.027134 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency 15193.205945 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency 15193.205945 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency 15193.205945 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -697,67 +702,67 @@ system.cpu1.icache.avg_blocked_cycles::no_targets no_value system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed system.cpu1.icache.writebacks 0 # number of writebacks -system.cpu1.icache.ReadReq_mshr_hits 45 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits 45 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits 45 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses 442 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses 442 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses 442 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_hits 44 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits 44 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits 44 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses 427 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses 427 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses 427 # number of overall MSHR misses system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.icache.ReadReq_mshr_miss_latency 5515000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency 5515000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency 5515000 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency 5329000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency 5329000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency 5329000 # number of overall MSHR miss cycles system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate 0.020783 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate 0.020783 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate 0.020783 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency 12477.375566 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency 12477.375566 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency 12477.375566 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_miss_rate 0.024600 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate 0.024600 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate 0.024600 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency 12480.093677 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency 12480.093677 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency 12480.093677 # average overall mshr miss latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dcache.replacements 2 # number of replacements -system.cpu1.dcache.tagsinuse 15.853389 # Cycle average of tags in use -system.cpu1.dcache.total_refs 45287 # Total number of references to valid blocks. +system.cpu1.dcache.tagsinuse 18.326142 # Cycle average of tags in use +system.cpu1.dcache.total_refs 46034 # Total number of references to valid blocks. system.cpu1.dcache.sampled_refs 29 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 1561.620690 # Average number of references to valid blocks. +system.cpu1.dcache.avg_refs 1587.379310 # Average number of references to valid blocks. system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::0 24.109583 # Average occupied blocks per context -system.cpu1.dcache.occ_blocks::1 -8.256194 # Average occupied blocks per context -system.cpu1.dcache.occ_percent::0 0.047089 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::1 -0.016125 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits 49422 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits 39377 # number of WriteReq hits -system.cpu1.dcache.SwapReq_hits 14 # number of SwapReq hits -system.cpu1.dcache.demand_hits 88799 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits 88799 # number of overall hits -system.cpu1.dcache.ReadReq_misses 438 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses 121 # number of WriteReq misses -system.cpu1.dcache.SwapReq_misses 52 # number of SwapReq misses -system.cpu1.dcache.demand_misses 559 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses 559 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency 9255000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency 2991000 # number of WriteReq miss cycles -system.cpu1.dcache.SwapReq_miss_latency 1250500 # number of SwapReq miss cycles -system.cpu1.dcache.demand_miss_latency 12246000 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency 12246000 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses 49860 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses 39498 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.occ_blocks::0 24.418432 # Average occupied blocks per context +system.cpu1.dcache.occ_blocks::1 -6.092290 # Average occupied blocks per context +system.cpu1.dcache.occ_percent::0 0.047692 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::1 -0.011899 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits 48212 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits 39908 # number of WriteReq hits +system.cpu1.dcache.SwapReq_hits 12 # number of SwapReq hits +system.cpu1.dcache.demand_hits 88120 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits 88120 # number of overall hits +system.cpu1.dcache.ReadReq_misses 470 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses 123 # number of WriteReq misses +system.cpu1.dcache.SwapReq_misses 54 # number of SwapReq misses +system.cpu1.dcache.demand_misses 593 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses 593 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency 9944500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency 2927000 # number of WriteReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency 1215000 # number of SwapReq miss cycles +system.cpu1.dcache.demand_miss_latency 12871500 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency 12871500 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses 48682 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses 40031 # number of WriteReq accesses(hits+misses) system.cpu1.dcache.SwapReq_accesses 66 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses 89358 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses 89358 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate 0.008785 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate 0.003063 # miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_miss_rate 0.787879 # miss rate for SwapReq accesses -system.cpu1.dcache.demand_miss_rate 0.006256 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate 0.006256 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency 21130.136986 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency 24719.008264 # average WriteReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency 24048.076923 # average SwapReq miss latency -system.cpu1.dcache.demand_avg_miss_latency 21906.976744 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency 21906.976744 # average overall miss latency +system.cpu1.dcache.demand_accesses 88713 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses 88713 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate 0.009654 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate 0.003073 # miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_miss_rate 0.818182 # miss rate for SwapReq accesses +system.cpu1.dcache.demand_miss_rate 0.006684 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate 0.006684 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency 21158.510638 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency 23796.747967 # average WriteReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency 22500 # average SwapReq miss latency +system.cpu1.dcache.demand_avg_miss_latency 21705.733558 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency 21705.733558 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -767,391 +772,394 @@ system.cpu1.dcache.avg_blocked_cycles::no_targets no_value system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed system.cpu1.dcache.writebacks 1 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits 282 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits 318 # number of ReadReq MSHR hits system.cpu1.dcache.WriteReq_mshr_hits 18 # number of WriteReq MSHR hits -system.cpu1.dcache.demand_mshr_hits 300 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits 300 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses 156 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses 103 # number of WriteReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses 52 # number of SwapReq MSHR misses -system.cpu1.dcache.demand_mshr_misses 259 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses 259 # number of overall MSHR misses +system.cpu1.dcache.demand_mshr_hits 336 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits 336 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses 152 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses 105 # number of WriteReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses 54 # number of SwapReq MSHR misses +system.cpu1.dcache.demand_mshr_misses 257 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses 257 # number of overall MSHR misses system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency 2111500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency 1675000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency 1094500 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency 3786500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency 3786500 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency 1992500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency 1603000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency 1053000 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency 3595500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency 3595500 # number of overall MSHR miss cycles system.cpu1.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate 0.003129 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate 0.002608 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate 0.787879 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.demand_mshr_miss_rate 0.002898 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate 0.002898 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 13535.256410 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 16262.135922 # average WriteReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency 21048.076923 # average SwapReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency 14619.691120 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency 14619.691120 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_mshr_miss_rate 0.003122 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate 0.002623 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate 0.818182 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.demand_mshr_miss_rate 0.002897 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate 0.002897 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 13108.552632 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 15266.666667 # average WriteReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency 19500 # average SwapReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency 13990.272374 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency 13990.272374 # average overall mshr miss latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.numCycles 199106 # number of cpu cycles simulated +system.cpu2.numCycles 173778 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.BPredUnit.lookups 57971 # Number of BP lookups -system.cpu2.BPredUnit.condPredicted 55658 # Number of conditional branches predicted -system.cpu2.BPredUnit.condIncorrect 1119 # Number of conditional branches incorrect -system.cpu2.BPredUnit.BTBLookups 57356 # Number of BTB lookups -system.cpu2.BPredUnit.BTBHits 55221 # Number of BTB hits +system.cpu2.BPredUnit.lookups 50805 # Number of BP lookups +system.cpu2.BPredUnit.condPredicted 48180 # Number of conditional branches predicted +system.cpu2.BPredUnit.condIncorrect 1153 # Number of conditional branches incorrect +system.cpu2.BPredUnit.BTBLookups 47027 # Number of BTB lookups +system.cpu2.BPredUnit.BTBHits 44960 # Number of BTB hits system.cpu2.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.BPredUnit.usedRAS 508 # Number of times the RAS was used to get a target. +system.cpu2.BPredUnit.usedRAS 640 # Number of times the RAS was used to get a target. system.cpu2.BPredUnit.RASInCorrect 232 # Number of incorrect RAS predictions. -system.cpu2.fetch.icacheStallCycles 18228 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 327195 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 57971 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 55729 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 116612 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 1192 # Number of cycles fetch has spent squashing -system.cpu2.fetch.MiscStallCycles 32 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.CacheLines 18228 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 237 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.rateDist::samples 193972 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.686816 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.080601 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 27007 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 283163 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 50805 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 45600 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 99886 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 3304 # Number of cycles fetch has spent squashing +system.cpu2.fetch.BlockedCycles 32566 # Number of cycles fetch has spent blocked +system.cpu2.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.NoActiveThreadStallCycles 6449 # Number of stall cycles due to no active thread to fetch from +system.cpu2.fetch.PendingTrapStallCycles 778 # Number of stall cycles due to pending traps +system.cpu2.fetch.CacheLines 18144 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 200 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.rateDist::samples 168765 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.677854 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.125811 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 77360 39.88% 39.88% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 59528 30.69% 70.57% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 5848 3.01% 73.59% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 2830 1.46% 75.04% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 1905 0.98% 76.03% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 42329 21.82% 97.85% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 2448 1.26% 99.11% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 264 0.14% 99.25% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 1460 0.75% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 68879 40.81% 40.81% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 50491 29.92% 70.73% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 5634 3.34% 74.07% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 3757 2.23% 76.30% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 707 0.42% 76.71% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 34670 20.54% 97.26% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 1324 0.78% 98.04% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 413 0.24% 98.29% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 2890 1.71% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 193972 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.291156 # Number of branch fetches per cycle -system.cpu2.fetch.rate 1.643321 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 48904 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 20328 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 111841 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 4382 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 1806 # Number of cycles decode is squashing -system.cpu2.decode.DecodedInsts 325997 # Number of instructions handled by decode -system.cpu2.rename.SquashCycles 1806 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 49533 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 6147 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 13457 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 115712 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 606 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 324330 # Number of instructions processed by rename -system.cpu2.rename.IQFullEvents 65 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LSQFullEvents 45 # Number of times rename has blocked due to LSQ full -system.cpu2.rename.RenamedOperands 224740 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 625107 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 625107 # Number of integer rename lookups -system.cpu2.rename.CommittedMaps 216561 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 8179 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 949 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 1011 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 2760 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 94652 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 45182 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 45774 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 40713 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 269361 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 6099 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 272571 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 1 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 6651 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 6299 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 621 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 193972 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.405208 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.293243 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 168765 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.292356 # Number of branch fetches per cycle +system.cpu2.fetch.rate 1.629453 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 31662 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 29441 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 94497 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 4642 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 2074 # Number of cycles decode is squashing +system.cpu2.decode.DecodedInsts 280431 # Number of instructions handled by decode +system.cpu2.rename.SquashCycles 2074 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 32376 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 14418 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 14186 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 90338 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 8924 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 278200 # Number of instructions processed by rename +system.cpu2.rename.IQFullEvents 53 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LSQFullEvents 43 # Number of times rename has blocked due to LSQ full +system.cpu2.rename.RenamedOperands 195247 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 534109 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 534109 # Number of integer rename lookups +system.cpu2.rename.CommittedMaps 184829 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 10418 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 1050 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 1186 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 11541 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 79019 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 37409 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 37644 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 32854 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 231381 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 5925 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 233568 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 3 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 8776 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 8266 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 641 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 168765 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.383984 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.307813 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 73708 38.00% 38.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 23872 12.31% 50.31% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 47052 24.26% 74.56% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 44924 23.16% 97.72% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 2620 1.35% 99.07% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 1535 0.79% 99.87% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 168 0.09% 99.95% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 84 0.04% 100.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 9 0.00% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 66154 39.20% 39.20% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 21382 12.67% 51.87% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 37723 22.35% 74.22% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 38911 23.06% 97.28% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 3386 2.01% 99.28% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 949 0.56% 99.85% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 160 0.09% 99.94% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 42 0.02% 99.97% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 58 0.03% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 193972 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 168765 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 12 5.97% 5.97% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 5.97% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 5.97% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 5.97% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 5.97% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 5.97% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 5.97% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 5.97% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 5.97% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 5.97% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 5.97% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 5.97% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 5.97% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 5.97% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 5.97% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 5.97% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 5.97% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 5.97% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 5.97% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 5.97% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 5.97% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 5.97% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 5.97% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 5.97% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 5.97% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 5.97% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 5.97% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.97% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 5.97% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 58 28.86% 34.83% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 131 65.17% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 19 7.28% 7.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 7.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 7.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 7.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 7.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 7.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 7.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 7.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 7.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 7.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 7.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 7.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 7.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 7.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 7.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 7.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 7.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 7.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 7.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 7.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 7.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 7.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 7.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 7.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 7.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 7.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 7.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 7.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 52 19.92% 27.20% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 190 72.80% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 128963 47.31% 47.31% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 0 0.00% 47.31% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 47.31% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 47.31% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 47.31% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 47.31% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 47.31% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 47.31% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 47.31% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 47.31% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 47.31% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 47.31% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 47.31% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 47.31% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 47.31% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 47.31% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 47.31% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 47.31% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 47.31% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 47.31% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.31% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.31% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.31% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.31% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.31% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 47.31% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 47.31% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.31% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.31% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 98810 36.25% 83.56% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 44798 16.44% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 113638 48.65% 48.65% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 0 0.00% 48.65% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 48.65% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 48.65% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 48.65% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 48.65% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 48.65% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 48.65% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 48.65% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 48.65% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 48.65% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 48.65% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 48.65% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 48.65% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 48.65% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 48.65% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 48.65% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 48.65% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.65% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 48.65% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.65% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.65% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.65% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.65% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.65% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.65% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 48.65% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.65% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.65% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 82927 35.50% 84.16% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 37003 15.84% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 272571 # Type of FU issued -system.cpu2.iq.rate 1.368974 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 201 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.000737 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 739316 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 282139 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 271248 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.FU_type_0::total 233568 # Type of FU issued +system.cpu2.iq.rate 1.344060 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 261 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.001117 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 636165 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 246114 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 232313 # Number of integer instruction queue wakeup accesses system.cpu2.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu2.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu2.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 272772 # Number of integer alu accesses +system.cpu2.iq.int_alu_accesses 233829 # Number of integer alu accesses system.cpu2.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 40559 # Number of loads that had data forwarded from stores +system.cpu2.iew.lsq.thread0.forwLoads 32721 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 1552 # Number of loads squashed +system.cpu2.iew.lsq.thread0.squashedLoads 1885 # Number of loads squashed system.cpu2.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 28 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 752 # Number of stores squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 32 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 861 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu2.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu2.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 1806 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 1706 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 63 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 322227 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 522 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 94652 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 45182 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 927 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 55 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewSquashCycles 2074 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 1817 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 62 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 275982 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 400 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 79019 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 37409 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 998 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 54 # Number of times the IQ has become full, causing a stall system.cpu2.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 28 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 1035 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 187 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 1222 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 271613 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 93867 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 958 # Number of squashed instructions skipped in execute +system.cpu2.iew.memOrderViolationEvents 32 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 681 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 621 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 1302 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 232725 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 78144 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 843 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 46767 # number of nop insts executed -system.cpu2.iew.exec_refs 138637 # number of memory reference insts executed -system.cpu2.iew.exec_branches 55708 # Number of branches executed -system.cpu2.iew.exec_stores 44770 # Number of stores executed -system.cpu2.iew.exec_rate 1.364163 # Inst execution rate -system.cpu2.iew.wb_sent 271381 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 271248 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 155012 # num instructions producing a value -system.cpu2.iew.wb_consumers 158673 # num instructions consuming a value +system.cpu2.iew.exec_nop 38676 # number of nop insts executed +system.cpu2.iew.exec_refs 115111 # number of memory reference insts executed +system.cpu2.iew.exec_branches 47758 # Number of branches executed +system.cpu2.iew.exec_stores 36967 # Number of stores executed +system.cpu2.iew.exec_rate 1.339209 # Inst execution rate +system.cpu2.iew.wb_sent 232494 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 232313 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 131935 # num instructions producing a value +system.cpu2.iew.wb_consumers 136342 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 1.362330 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.976927 # average fanout of values written-back +system.cpu2.iew.wb_rate 1.336838 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.967677 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitCommittedInsts 313840 # The number of committed instructions -system.cpu2.commit.commitSquashedInsts 8384 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 5478 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 1119 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 185456 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.692261 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.994391 # Number of insts commited each cycle +system.cpu2.commit.commitCommittedInsts 265754 # The number of committed instructions +system.cpu2.commit.commitSquashedInsts 10224 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 5284 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 1153 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 160243 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.658444 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 2.033027 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 70838 38.20% 38.20% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 55984 30.19% 68.38% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 7465 4.03% 72.41% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 6288 3.39% 75.80% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 2454 1.32% 77.12% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 41414 22.33% 99.45% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 401 0.22% 99.67% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 126 0.07% 99.74% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 486 0.26% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 64923 40.52% 40.52% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 46026 28.72% 69.24% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 5970 3.73% 72.96% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 6149 3.84% 76.80% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 1628 1.02% 77.82% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 33154 20.69% 98.51% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 514 0.32% 98.83% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 1057 0.66% 99.49% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 822 0.51% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 185456 # Number of insts commited each cycle -system.cpu2.commit.count 313840 # Number of instructions committed +system.cpu2.commit.committed_per_cycle::total 160243 # Number of insts commited each cycle +system.cpu2.commit.count 265754 # Number of instructions committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 137530 # Number of memory references committed -system.cpu2.commit.loads 93100 # Number of loads committed -system.cpu2.commit.membars 4761 # Number of memory barriers committed -system.cpu2.commit.branches 55156 # Number of branches committed +system.cpu2.commit.refs 113682 # Number of memory references committed +system.cpu2.commit.loads 77134 # Number of loads committed +system.cpu2.commit.membars 4565 # Number of memory barriers committed +system.cpu2.commit.branches 47078 # Number of branches committed system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 214804 # Number of committed integer instructions. +system.cpu2.commit.int_insts 182876 # Number of committed integer instructions. system.cpu2.commit.function_calls 322 # Number of function calls committed. -system.cpu2.commit.bw_lim_events 486 # number cycles where commit BW limit reached +system.cpu2.commit.bw_lim_events 822 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 506607 # The number of ROB reads -system.cpu2.rob.rob_writes 646257 # The number of ROB writes -system.cpu2.timesIdled 280 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 5134 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.committedInsts 263136 # Number of Instructions Simulated -system.cpu2.committedInsts_total 263136 # Number of Instructions Simulated -system.cpu2.cpi 0.756666 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 0.756666 # CPI: Total CPI of All Threads -system.cpu2.ipc 1.321587 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 1.321587 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 473358 # number of integer regfile reads -system.cpu2.int_regfile_writes 219156 # number of integer regfile writes +system.cpu2.rob.rob_reads 434812 # The number of ROB reads +system.cpu2.rob.rob_writes 554033 # The number of ROB writes +system.cpu2.timesIdled 231 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 5013 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.committedInsts 223326 # Number of Instructions Simulated +system.cpu2.committedInsts_total 223326 # Number of Instructions Simulated +system.cpu2.cpi 0.778136 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 0.778136 # CPI: Total CPI of All Threads +system.cpu2.ipc 1.285122 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 1.285122 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 403849 # number of integer regfile reads +system.cpu2.int_regfile_writes 188623 # number of integer regfile writes system.cpu2.fp_regfile_writes 64 # number of floating regfile writes -system.cpu2.misc_regfile_reads 140181 # number of misc regfile reads +system.cpu2.misc_regfile_reads 116687 # number of misc regfile reads system.cpu2.misc_regfile_writes 646 # number of misc regfile writes -system.cpu2.icache.replacements 333 # number of replacements -system.cpu2.icache.tagsinuse 86.095246 # Cycle average of tags in use -system.cpu2.icache.total_refs 17739 # Total number of references to valid blocks. -system.cpu2.icache.sampled_refs 438 # Sample count of references to valid blocks. -system.cpu2.icache.avg_refs 40.500000 # Average number of references to valid blocks. +system.cpu2.icache.replacements 323 # number of replacements +system.cpu2.icache.tagsinuse 85.152335 # Cycle average of tags in use +system.cpu2.icache.total_refs 17658 # Total number of references to valid blocks. +system.cpu2.icache.sampled_refs 429 # Sample count of references to valid blocks. +system.cpu2.icache.avg_refs 41.160839 # Average number of references to valid blocks. system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.icache.occ_blocks::0 86.095246 # Average occupied blocks per context -system.cpu2.icache.occ_percent::0 0.168155 # Average percentage of cache occupancy -system.cpu2.icache.ReadReq_hits 17739 # number of ReadReq hits -system.cpu2.icache.demand_hits 17739 # number of demand (read+write) hits -system.cpu2.icache.overall_hits 17739 # number of overall hits -system.cpu2.icache.ReadReq_misses 489 # number of ReadReq misses -system.cpu2.icache.demand_misses 489 # number of demand (read+write) misses -system.cpu2.icache.overall_misses 489 # number of overall misses -system.cpu2.icache.ReadReq_miss_latency 10440000 # number of ReadReq miss cycles -system.cpu2.icache.demand_miss_latency 10440000 # number of demand (read+write) miss cycles -system.cpu2.icache.overall_miss_latency 10440000 # number of overall miss cycles -system.cpu2.icache.ReadReq_accesses 18228 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.demand_accesses 18228 # number of demand (read+write) accesses -system.cpu2.icache.overall_accesses 18228 # number of overall (read+write) accesses -system.cpu2.icache.ReadReq_miss_rate 0.026827 # miss rate for ReadReq accesses -system.cpu2.icache.demand_miss_rate 0.026827 # miss rate for demand accesses -system.cpu2.icache.overall_miss_rate 0.026827 # miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_miss_latency 21349.693252 # average ReadReq miss latency -system.cpu2.icache.demand_avg_miss_latency 21349.693252 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency 21349.693252 # average overall miss latency -system.cpu2.icache.blocked_cycles::no_mshrs 32500 # number of cycles access was blocked +system.cpu2.icache.occ_blocks::0 85.152335 # Average occupied blocks per context +system.cpu2.icache.occ_percent::0 0.166313 # Average percentage of cache occupancy +system.cpu2.icache.ReadReq_hits 17658 # number of ReadReq hits +system.cpu2.icache.demand_hits 17658 # number of demand (read+write) hits +system.cpu2.icache.overall_hits 17658 # number of overall hits +system.cpu2.icache.ReadReq_misses 486 # number of ReadReq misses +system.cpu2.icache.demand_misses 486 # number of demand (read+write) misses +system.cpu2.icache.overall_misses 486 # number of overall misses +system.cpu2.icache.ReadReq_miss_latency 10409000 # number of ReadReq miss cycles +system.cpu2.icache.demand_miss_latency 10409000 # number of demand (read+write) miss cycles +system.cpu2.icache.overall_miss_latency 10409000 # number of overall miss cycles +system.cpu2.icache.ReadReq_accesses 18144 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.demand_accesses 18144 # number of demand (read+write) accesses +system.cpu2.icache.overall_accesses 18144 # number of overall (read+write) accesses +system.cpu2.icache.ReadReq_miss_rate 0.026786 # miss rate for ReadReq accesses +system.cpu2.icache.demand_miss_rate 0.026786 # miss rate for demand accesses +system.cpu2.icache.overall_miss_rate 0.026786 # miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_miss_latency 21417.695473 # average ReadReq miss latency +system.cpu2.icache.demand_avg_miss_latency 21417.695473 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency 21417.695473 # average overall miss latency +system.cpu2.icache.blocked_cycles::no_mshrs 33000 # number of cycles access was blocked system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.icache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu2.icache.avg_blocked_cycles::no_mshrs 32500 # average number of cycles each access was blocked +system.cpu2.icache.avg_blocked_cycles::no_mshrs 33000 # average number of cycles each access was blocked system.cpu2.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu2.icache.fast_writes 0 # number of fast writes performed system.cpu2.icache.cache_copies 0 # number of cache copies performed system.cpu2.icache.writebacks 0 # number of writebacks -system.cpu2.icache.ReadReq_mshr_hits 51 # number of ReadReq MSHR hits -system.cpu2.icache.demand_mshr_hits 51 # number of demand (read+write) MSHR hits -system.cpu2.icache.overall_mshr_hits 51 # number of overall MSHR hits -system.cpu2.icache.ReadReq_mshr_misses 438 # number of ReadReq MSHR misses -system.cpu2.icache.demand_mshr_misses 438 # number of demand (read+write) MSHR misses -system.cpu2.icache.overall_mshr_misses 438 # number of overall MSHR misses +system.cpu2.icache.ReadReq_mshr_hits 57 # number of ReadReq MSHR hits +system.cpu2.icache.demand_mshr_hits 57 # number of demand (read+write) MSHR hits +system.cpu2.icache.overall_mshr_hits 57 # number of overall MSHR hits +system.cpu2.icache.ReadReq_mshr_misses 429 # number of ReadReq MSHR misses +system.cpu2.icache.demand_mshr_misses 429 # number of demand (read+write) MSHR misses +system.cpu2.icache.overall_mshr_misses 429 # number of overall MSHR misses system.cpu2.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu2.icache.ReadReq_mshr_miss_latency 8036500 # number of ReadReq MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency 8036500 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency 8036500 # number of overall MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_latency 7965500 # number of ReadReq MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency 7965500 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency 7965500 # number of overall MSHR miss cycles system.cpu2.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu2.icache.ReadReq_mshr_miss_rate 0.024029 # mshr miss rate for ReadReq accesses -system.cpu2.icache.demand_mshr_miss_rate 0.024029 # mshr miss rate for demand accesses -system.cpu2.icache.overall_mshr_miss_rate 0.024029 # mshr miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_mshr_miss_latency 18348.173516 # average ReadReq mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency 18348.173516 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency 18348.173516 # average overall mshr miss latency +system.cpu2.icache.ReadReq_mshr_miss_rate 0.023644 # mshr miss rate for ReadReq accesses +system.cpu2.icache.demand_mshr_miss_rate 0.023644 # mshr miss rate for demand accesses +system.cpu2.icache.overall_mshr_miss_rate 0.023644 # mshr miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_mshr_miss_latency 18567.599068 # average ReadReq mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency 18567.599068 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency 18567.599068 # average overall mshr miss latency system.cpu2.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu2.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu2.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu2.dcache.replacements 2 # number of replacements -system.cpu2.dcache.tagsinuse 18.718664 # Cycle average of tags in use -system.cpu2.dcache.total_refs 50172 # Total number of references to valid blocks. -system.cpu2.dcache.sampled_refs 30 # Sample count of references to valid blocks. -system.cpu2.dcache.avg_refs 1672.400000 # Average number of references to valid blocks. +system.cpu2.dcache.tagsinuse 18.333268 # Cycle average of tags in use +system.cpu2.dcache.total_refs 42495 # Total number of references to valid blocks. +system.cpu2.dcache.sampled_refs 31 # Sample count of references to valid blocks. +system.cpu2.dcache.avg_refs 1370.806452 # Average number of references to valid blocks. system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.dcache.occ_blocks::0 27.030706 # Average occupied blocks per context -system.cpu2.dcache.occ_blocks::1 -8.312042 # Average occupied blocks per context -system.cpu2.dcache.occ_percent::0 0.052794 # Average percentage of cache occupancy -system.cpu2.dcache.occ_percent::1 -0.016234 # Average percentage of cache occupancy -system.cpu2.dcache.ReadReq_hits 52844 # number of ReadReq hits -system.cpu2.dcache.WriteReq_hits 44237 # number of WriteReq hits +system.cpu2.dcache.occ_blocks::0 26.478684 # Average occupied blocks per context +system.cpu2.dcache.occ_blocks::1 -8.145416 # Average occupied blocks per context +system.cpu2.dcache.occ_percent::0 0.051716 # Average percentage of cache occupancy +system.cpu2.dcache.occ_percent::1 -0.015909 # Average percentage of cache occupancy +system.cpu2.dcache.ReadReq_hits 44951 # number of ReadReq hits +system.cpu2.dcache.WriteReq_hits 36350 # number of WriteReq hits system.cpu2.dcache.SwapReq_hits 12 # number of SwapReq hits -system.cpu2.dcache.demand_hits 97081 # number of demand (read+write) hits -system.cpu2.dcache.overall_hits 97081 # number of overall hits -system.cpu2.dcache.ReadReq_misses 446 # number of ReadReq misses -system.cpu2.dcache.WriteReq_misses 122 # number of WriteReq misses -system.cpu2.dcache.SwapReq_misses 59 # number of SwapReq misses -system.cpu2.dcache.demand_misses 568 # number of demand (read+write) misses -system.cpu2.dcache.overall_misses 568 # number of overall misses -system.cpu2.dcache.ReadReq_miss_latency 10164500 # number of ReadReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency 2987000 # number of WriteReq miss cycles -system.cpu2.dcache.SwapReq_miss_latency 1380500 # number of SwapReq miss cycles -system.cpu2.dcache.demand_miss_latency 13151500 # number of demand (read+write) miss cycles -system.cpu2.dcache.overall_miss_latency 13151500 # number of overall miss cycles -system.cpu2.dcache.ReadReq_accesses 53290 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses 44359 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_accesses 71 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.demand_accesses 97649 # number of demand (read+write) accesses -system.cpu2.dcache.overall_accesses 97649 # number of overall (read+write) accesses -system.cpu2.dcache.ReadReq_miss_rate 0.008369 # miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_miss_rate 0.002750 # miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_miss_rate 0.830986 # miss rate for SwapReq accesses -system.cpu2.dcache.demand_miss_rate 0.005817 # miss rate for demand accesses -system.cpu2.dcache.overall_miss_rate 0.005817 # miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_miss_latency 22790.358744 # average ReadReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency 24483.606557 # average WriteReq miss latency -system.cpu2.dcache.SwapReq_avg_miss_latency 23398.305085 # average SwapReq miss latency -system.cpu2.dcache.demand_avg_miss_latency 23154.049296 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency 23154.049296 # average overall miss latency +system.cpu2.dcache.demand_hits 81301 # number of demand (read+write) hits +system.cpu2.dcache.overall_hits 81301 # number of overall hits +system.cpu2.dcache.ReadReq_misses 454 # number of ReadReq misses +system.cpu2.dcache.WriteReq_misses 125 # number of WriteReq misses +system.cpu2.dcache.SwapReq_misses 61 # number of SwapReq misses +system.cpu2.dcache.demand_misses 579 # number of demand (read+write) misses +system.cpu2.dcache.overall_misses 579 # number of overall misses +system.cpu2.dcache.ReadReq_miss_latency 10292500 # number of ReadReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency 2895500 # number of WriteReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency 1389500 # number of SwapReq miss cycles +system.cpu2.dcache.demand_miss_latency 13188000 # number of demand (read+write) miss cycles +system.cpu2.dcache.overall_miss_latency 13188000 # number of overall miss cycles +system.cpu2.dcache.ReadReq_accesses 45405 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses 36475 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses 73 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.demand_accesses 81880 # number of demand (read+write) accesses +system.cpu2.dcache.overall_accesses 81880 # number of overall (read+write) accesses +system.cpu2.dcache.ReadReq_miss_rate 0.009999 # miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_miss_rate 0.003427 # miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_miss_rate 0.835616 # miss rate for SwapReq accesses +system.cpu2.dcache.demand_miss_rate 0.007071 # miss rate for demand accesses +system.cpu2.dcache.overall_miss_rate 0.007071 # miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_miss_latency 22670.704846 # average ReadReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency 23164 # average WriteReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency 22778.688525 # average SwapReq miss latency +system.cpu2.dcache.demand_avg_miss_latency 22777.202073 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency 22777.202073 # average overall miss latency system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1161,321 +1169,324 @@ system.cpu2.dcache.avg_blocked_cycles::no_targets no_value system.cpu2.dcache.fast_writes 0 # number of fast writes performed system.cpu2.dcache.cache_copies 0 # number of cache copies performed system.cpu2.dcache.writebacks 1 # number of writebacks -system.cpu2.dcache.ReadReq_mshr_hits 286 # number of ReadReq MSHR hits +system.cpu2.dcache.ReadReq_mshr_hits 289 # number of ReadReq MSHR hits system.cpu2.dcache.WriteReq_mshr_hits 18 # number of WriteReq MSHR hits -system.cpu2.dcache.demand_mshr_hits 304 # number of demand (read+write) MSHR hits -system.cpu2.dcache.overall_mshr_hits 304 # number of overall MSHR hits -system.cpu2.dcache.ReadReq_mshr_misses 160 # number of ReadReq MSHR misses -system.cpu2.dcache.WriteReq_mshr_misses 104 # number of WriteReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses 59 # number of SwapReq MSHR misses -system.cpu2.dcache.demand_mshr_misses 264 # number of demand (read+write) MSHR misses -system.cpu2.dcache.overall_mshr_misses 264 # number of overall MSHR misses +system.cpu2.dcache.demand_mshr_hits 307 # number of demand (read+write) MSHR hits +system.cpu2.dcache.overall_mshr_hits 307 # number of overall MSHR hits +system.cpu2.dcache.ReadReq_mshr_misses 165 # number of ReadReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses 107 # number of WriteReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses 61 # number of SwapReq MSHR misses +system.cpu2.dcache.demand_mshr_misses 272 # number of demand (read+write) MSHR misses +system.cpu2.dcache.overall_mshr_misses 272 # number of overall MSHR misses system.cpu2.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu2.dcache.ReadReq_mshr_miss_latency 2394500 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency 1669000 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency 1203500 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency 4063500 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency 4063500 # number of overall MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_latency 2342500 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency 1563000 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency 1206500 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency 3905500 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency 3905500 # number of overall MSHR miss cycles system.cpu2.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu2.dcache.ReadReq_mshr_miss_rate 0.003002 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate 0.002345 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate 0.830986 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.demand_mshr_miss_rate 0.002704 # mshr miss rate for demand accesses -system.cpu2.dcache.overall_mshr_miss_rate 0.002704 # mshr miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency 14965.625000 # average ReadReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency 16048.076923 # average WriteReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency 20398.305085 # average SwapReq mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency 15392.045455 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency 15392.045455 # average overall mshr miss latency +system.cpu2.dcache.ReadReq_mshr_miss_rate 0.003634 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate 0.002934 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate 0.835616 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.demand_mshr_miss_rate 0.003322 # mshr miss rate for demand accesses +system.cpu2.dcache.overall_mshr_miss_rate 0.003322 # mshr miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency 14196.969697 # average ReadReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency 14607.476636 # average WriteReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency 19778.688525 # average SwapReq mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency 14358.455882 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency 14358.455882 # average overall mshr miss latency system.cpu2.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu2.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu2.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.numCycles 198838 # number of cpu cycles simulated +system.cpu3.numCycles 173512 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu3.BPredUnit.lookups 46930 # Number of BP lookups -system.cpu3.BPredUnit.condPredicted 44609 # Number of conditional branches predicted -system.cpu3.BPredUnit.condIncorrect 1124 # Number of conditional branches incorrect -system.cpu3.BPredUnit.BTBLookups 46370 # Number of BTB lookups -system.cpu3.BPredUnit.BTBHits 44223 # Number of BTB hits +system.cpu3.BPredUnit.lookups 40530 # Number of BP lookups +system.cpu3.BPredUnit.condPredicted 37937 # Number of conditional branches predicted +system.cpu3.BPredUnit.condIncorrect 1057 # Number of conditional branches incorrect +system.cpu3.BPredUnit.BTBLookups 36753 # Number of BTB lookups +system.cpu3.BPredUnit.BTBHits 34800 # Number of BTB hits system.cpu3.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu3.BPredUnit.usedRAS 506 # Number of times the RAS was used to get a target. +system.cpu3.BPredUnit.usedRAS 627 # Number of times the RAS was used to get a target. system.cpu3.BPredUnit.RASInCorrect 232 # Number of incorrect RAS predictions. -system.cpu3.fetch.icacheStallCycles 25370 # Number of cycles fetch is stalled on an Icache miss -system.cpu3.fetch.Insts 254105 # Number of instructions fetch has processed -system.cpu3.fetch.Branches 46930 # Number of branches that fetch encountered -system.cpu3.fetch.predictedBranches 44729 # Number of branches that fetch has predicted taken -system.cpu3.fetch.Cycles 98091 # Number of cycles fetch has run and was not squashing or blocked -system.cpu3.fetch.SquashCycles 1197 # Number of cycles fetch has spent squashing -system.cpu3.fetch.MiscStallCycles 24 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu3.fetch.CacheLines 25370 # Number of cache lines fetched -system.cpu3.fetch.IcacheSquashes 235 # Number of outstanding Icache misses that were squashed -system.cpu3.fetch.rateDist::samples 195684 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::mean 1.298548 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::stdev 1.898359 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.icacheStallCycles 33125 # Number of cycles fetch is stalled on an Icache miss +system.cpu3.fetch.Insts 215867 # Number of instructions fetch has processed +system.cpu3.fetch.Branches 40530 # Number of branches that fetch encountered +system.cpu3.fetch.predictedBranches 35427 # Number of branches that fetch has predicted taken +system.cpu3.fetch.Cycles 83007 # Number of cycles fetch has run and was not squashing or blocked +system.cpu3.fetch.SquashCycles 3046 # Number of cycles fetch has spent squashing +system.cpu3.fetch.BlockedCycles 45401 # Number of cycles fetch has spent blocked +system.cpu3.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu3.fetch.NoActiveThreadStallCycles 6445 # Number of stall cycles due to no active thread to fetch from +system.cpu3.fetch.PendingTrapStallCycles 706 # Number of stall cycles due to pending traps +system.cpu3.fetch.CacheLines 24871 # Number of cache lines fetched +system.cpu3.fetch.IcacheSquashes 171 # Number of outstanding Icache misses that were squashed +system.cpu3.fetch.rateDist::samples 170604 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::mean 1.265310 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::stdev 1.931210 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::0 97593 49.87% 49.87% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::1 52035 26.59% 76.46% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::2 9385 4.80% 81.26% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::3 2730 1.40% 82.66% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::4 1923 0.98% 83.64% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::5 27840 14.23% 97.86% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::6 2474 1.26% 99.13% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::7 258 0.13% 99.26% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::8 1446 0.74% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::0 87597 51.35% 51.35% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::1 43833 25.69% 77.04% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::2 8987 5.27% 82.31% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::3 3510 2.06% 84.36% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::4 653 0.38% 84.75% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::5 21422 12.56% 97.30% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::6 1319 0.77% 98.08% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::7 370 0.22% 98.29% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::8 2913 1.71% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::total 195684 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.branchRate 0.236021 # Number of branch fetches per cycle -system.cpu3.fetch.rate 1.277950 # Number of inst fetches per cycle -system.cpu3.decode.IdleCycles 66043 # Number of cycles decode is idle -system.cpu3.decode.BlockedCycles 23415 # Number of cycles decode is blocked -system.cpu3.decode.RunCycles 90085 # Number of cycles decode is running -system.cpu3.decode.UnblockCycles 7606 # Number of cycles decode is unblocking -system.cpu3.decode.SquashCycles 1806 # Number of cycles decode is squashing -system.cpu3.decode.DecodedInsts 252876 # Number of instructions handled by decode -system.cpu3.rename.SquashCycles 1806 # Number of cycles rename is squashing -system.cpu3.rename.IdleCycles 66691 # Number of cycles rename is idle -system.cpu3.rename.BlockCycles 9403 # Number of cycles rename is blocking -system.cpu3.rename.serializeStallCycles 13294 # count of cycles rename stalled for serializing inst -system.cpu3.rename.RunCycles 97176 # Number of cycles rename is running -system.cpu3.rename.UnblockCycles 585 # Number of cycles rename is unblocking -system.cpu3.rename.RenamedInsts 251157 # Number of instructions processed by rename -system.cpu3.rename.IQFullEvents 61 # Number of times rename has blocked due to IQ full -system.cpu3.rename.LSQFullEvents 39 # Number of times rename has blocked due to LSQ full -system.cpu3.rename.RenamedOperands 170213 # Number of destination operands rename has renamed -system.cpu3.rename.RenameLookups 465014 # Number of register rename lookups that rename has made -system.cpu3.rename.int_rename_lookups 465014 # Number of integer rename lookups -system.cpu3.rename.CommittedMaps 162080 # Number of HB maps that are committed -system.cpu3.rename.UndoneMaps 8133 # Number of HB maps that are undone due to squashing -system.cpu3.rename.serializingInsts 958 # count of serializing insts renamed -system.cpu3.rename.tempSerializingInsts 1016 # count of temporary serializing insts renamed -system.cpu3.rename.skidInsts 2718 # count of insts added to the skid buffer -system.cpu3.memDep0.insertedLoads 69072 # Number of loads inserted to the mem dependence unit. -system.cpu3.memDep0.insertedStores 30693 # Number of stores inserted to the mem dependence unit. -system.cpu3.memDep0.conflictingLoads 34709 # Number of conflicting loads. -system.cpu3.memDep0.conflictingStores 26217 # Number of conflicting stores. -system.cpu3.iq.iqInstsAdded 203693 # Number of instructions added to the IQ (excludes non-spec) -system.cpu3.iq.iqNonSpecInstsAdded 9545 # Number of non-speculative instructions added to the IQ -system.cpu3.iq.iqInstsIssued 210364 # Number of instructions issued -system.cpu3.iq.iqSquashedInstsIssued 2 # Number of squashed instructions issued -system.cpu3.iq.iqSquashedInstsExamined 6526 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu3.iq.iqSquashedOperandsExamined 6179 # Number of squashed operands that are examined and possibly removed from graph -system.cpu3.iq.iqSquashedNonSpecRemoved 647 # Number of squashed non-spec instructions that were removed -system.cpu3.iq.issued_per_cycle::samples 195684 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::mean 1.075019 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::stdev 1.244116 # Number of insts issued each cycle +system.cpu3.fetch.rateDist::total 170604 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.branchRate 0.233586 # Number of branch fetches per cycle +system.cpu3.fetch.rate 1.244104 # Number of inst fetches per cycle +system.cpu3.decode.IdleCycles 41023 # Number of cycles decode is idle +system.cpu3.decode.BlockedCycles 38920 # Number of cycles decode is blocked +system.cpu3.decode.RunCycles 74503 # Number of cycles decode is running +system.cpu3.decode.UnblockCycles 7798 # Number of cycles decode is unblocking +system.cpu3.decode.SquashCycles 1915 # Number of cycles decode is squashing +system.cpu3.decode.DecodedInsts 213126 # Number of instructions handled by decode +system.cpu3.rename.SquashCycles 1915 # Number of cycles rename is squashing +system.cpu3.rename.IdleCycles 41660 # Number of cycles rename is idle +system.cpu3.rename.BlockCycles 23650 # Number of cycles rename is blocking +system.cpu3.rename.serializeStallCycles 14461 # count of cycles rename stalled for serializing inst +system.cpu3.rename.RunCycles 67213 # Number of cycles rename is running +system.cpu3.rename.UnblockCycles 15260 # Number of cycles rename is unblocking +system.cpu3.rename.RenamedInsts 211303 # Number of instructions processed by rename +system.cpu3.rename.IQFullEvents 13 # Number of times rename has blocked due to IQ full +system.cpu3.rename.LSQFullEvents 40 # Number of times rename has blocked due to LSQ full +system.cpu3.rename.RenamedOperands 145000 # Number of destination operands rename has renamed +system.cpu3.rename.RenameLookups 387654 # Number of register rename lookups that rename has made +system.cpu3.rename.int_rename_lookups 387654 # Number of integer rename lookups +system.cpu3.rename.CommittedMaps 135623 # Number of HB maps that are committed +system.cpu3.rename.UndoneMaps 9377 # Number of HB maps that are undone due to squashing +system.cpu3.rename.serializingInsts 1053 # count of serializing insts renamed +system.cpu3.rename.tempSerializingInsts 1194 # count of temporary serializing insts renamed +system.cpu3.rename.skidInsts 17810 # count of insts added to the skid buffer +system.cpu3.memDep0.insertedLoads 55847 # Number of loads inserted to the mem dependence unit. +system.cpu3.memDep0.insertedStores 24229 # Number of stores inserted to the mem dependence unit. +system.cpu3.memDep0.conflictingLoads 27736 # Number of conflicting loads. +system.cpu3.memDep0.conflictingStores 19680 # Number of conflicting stores. +system.cpu3.iq.iqInstsAdded 171446 # Number of instructions added to the IQ (excludes non-spec) +system.cpu3.iq.iqNonSpecInstsAdded 9173 # Number of non-speculative instructions added to the IQ +system.cpu3.iq.iqInstsIssued 177208 # Number of instructions issued +system.cpu3.iq.iqSquashedInstsIssued 3 # Number of squashed instructions issued +system.cpu3.iq.iqSquashedInstsExamined 8093 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu3.iq.iqSquashedOperandsExamined 7434 # Number of squashed operands that are examined and possibly removed from graph +system.cpu3.iq.iqSquashedNonSpecRemoved 618 # Number of squashed non-spec instructions that were removed +system.cpu3.iq.issued_per_cycle::samples 170604 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::mean 1.038710 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::stdev 1.248224 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::0 94148 48.11% 48.11% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::1 34086 17.42% 65.53% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::2 32603 16.66% 82.19% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::3 30459 15.57% 97.76% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::4 2587 1.32% 99.08% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::5 1559 0.80% 99.88% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::6 152 0.08% 99.95% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::7 80 0.04% 99.99% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::8 10 0.01% 100.00% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::0 84759 49.68% 49.68% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::1 31065 18.21% 67.89% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::2 24373 14.29% 82.18% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::3 25865 15.16% 97.34% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::4 3284 1.92% 99.26% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::5 1031 0.60% 99.87% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::6 132 0.08% 99.94% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::7 41 0.02% 99.97% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::8 54 0.03% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::total 195684 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::total 170604 # Number of insts issued each cycle system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntAlu 11 5.67% 5.67% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntMult 0 0.00% 5.67% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntDiv 0 0.00% 5.67% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatAdd 0 0.00% 5.67% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCmp 0 0.00% 5.67% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCvt 0 0.00% 5.67% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatMult 0 0.00% 5.67% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatDiv 0 0.00% 5.67% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 5.67% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAdd 0 0.00% 5.67% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 5.67% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAlu 0 0.00% 5.67% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCmp 0 0.00% 5.67% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCvt 0 0.00% 5.67% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMisc 0 0.00% 5.67% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMult 0 0.00% 5.67% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 5.67% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShift 0 0.00% 5.67% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 5.67% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 5.67% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 5.67% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 5.67% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 5.67% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 5.67% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 5.67% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 5.67% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 5.67% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.67% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 5.67% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemRead 52 26.80% 32.47% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemWrite 131 67.53% 100.00% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntAlu 11 4.47% 4.47% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntMult 0 0.00% 4.47% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntDiv 0 0.00% 4.47% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatAdd 0 0.00% 4.47% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCmp 0 0.00% 4.47% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCvt 0 0.00% 4.47% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatMult 0 0.00% 4.47% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatDiv 0 0.00% 4.47% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 4.47% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAdd 0 0.00% 4.47% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 4.47% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAlu 0 0.00% 4.47% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCmp 0 0.00% 4.47% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCvt 0 0.00% 4.47% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMisc 0 0.00% 4.47% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMult 0 0.00% 4.47% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 4.47% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShift 0 0.00% 4.47% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 4.47% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 4.47% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 4.47% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 4.47% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 4.47% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 4.47% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 4.47% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 4.47% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 4.47% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.47% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 4.47% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemRead 45 18.29% 22.76% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemWrite 190 77.24% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu3.iq.FU_type_0::IntAlu 103392 49.15% 49.15% # Type of FU issued -system.cpu3.iq.FU_type_0::IntMult 0 0.00% 49.15% # Type of FU issued -system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 49.15% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 49.15% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 49.15% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 49.15% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 49.15% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 49.15% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 49.15% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 49.15% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 49.15% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 49.15% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 49.15% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 49.15% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 49.15% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 49.15% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 49.15% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 49.15% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.15% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 49.15% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.15% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.15% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.15% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.15% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.15% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.15% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 49.15% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.15% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.15% # Type of FU issued -system.cpu3.iq.FU_type_0::MemRead 76648 36.44% 85.58% # Type of FU issued -system.cpu3.iq.FU_type_0::MemWrite 30324 14.42% 100.00% # Type of FU issued +system.cpu3.iq.FU_type_0::IntAlu 90240 50.92% 50.92% # Type of FU issued +system.cpu3.iq.FU_type_0::IntMult 0 0.00% 50.92% # Type of FU issued +system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 50.92% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 50.92% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 50.92% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 50.92% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 50.92% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 50.92% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 50.92% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 50.92% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 50.92% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 50.92% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 50.92% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 50.92% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 50.92% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 50.92% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 50.92% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 50.92% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 50.92% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 50.92% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 50.92% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 50.92% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 50.92% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 50.92% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 50.92% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 50.92% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 50.92% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 50.92% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 50.92% # Type of FU issued +system.cpu3.iq.FU_type_0::MemRead 63111 35.61% 86.54% # Type of FU issued +system.cpu3.iq.FU_type_0::MemWrite 23857 13.46% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu3.iq.FU_type_0::total 210364 # Type of FU issued -system.cpu3.iq.rate 1.057967 # Inst issue rate -system.cpu3.iq.fu_busy_cnt 194 # FU busy when requested -system.cpu3.iq.fu_busy_rate 0.000922 # FU busy rate (busy events/executed inst) -system.cpu3.iq.int_inst_queue_reads 616608 # Number of integer instruction queue reads -system.cpu3.iq.int_inst_queue_writes 219792 # Number of integer instruction queue writes -system.cpu3.iq.int_inst_queue_wakeup_accesses 209060 # Number of integer instruction queue wakeup accesses +system.cpu3.iq.FU_type_0::total 177208 # Type of FU issued +system.cpu3.iq.rate 1.021301 # Inst issue rate +system.cpu3.iq.fu_busy_cnt 246 # FU busy when requested +system.cpu3.iq.fu_busy_rate 0.001388 # FU busy rate (busy events/executed inst) +system.cpu3.iq.int_inst_queue_reads 525269 # Number of integer instruction queue reads +system.cpu3.iq.int_inst_queue_writes 188741 # Number of integer instruction queue writes +system.cpu3.iq.int_inst_queue_wakeup_accesses 176086 # Number of integer instruction queue wakeup accesses system.cpu3.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu3.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu3.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu3.iq.int_alu_accesses 210558 # Number of integer alu accesses +system.cpu3.iq.int_alu_accesses 177454 # Number of integer alu accesses system.cpu3.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu3.iew.lsq.thread0.forwLoads 26077 # Number of loads that had data forwarded from stores +system.cpu3.iew.lsq.thread0.forwLoads 19589 # Number of loads that had data forwarded from stores system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu3.iew.lsq.thread0.squashedLoads 1504 # Number of loads squashed +system.cpu3.iew.lsq.thread0.squashedLoads 1676 # Number of loads squashed system.cpu3.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed -system.cpu3.iew.lsq.thread0.memOrderViolation 28 # Number of memory ordering violations -system.cpu3.iew.lsq.thread0.squashedStores 734 # Number of stores squashed +system.cpu3.iew.lsq.thread0.memOrderViolation 29 # Number of memory ordering violations +system.cpu3.iew.lsq.thread0.squashedStores 799 # Number of stores squashed system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu3.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu3.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu3.iew.iewSquashCycles 1806 # Number of cycles IEW is squashing -system.cpu3.iew.iewBlockCycles 1713 # Number of cycles IEW is blocking -system.cpu3.iew.iewUnblockCycles 59 # Number of cycles IEW is unblocking -system.cpu3.iew.iewDispatchedInsts 248952 # Number of instructions dispatched to IQ -system.cpu3.iew.iewDispSquashedInsts 576 # Number of squashed instructions skipped by dispatch -system.cpu3.iew.iewDispLoadInsts 69072 # Number of dispatched load instructions -system.cpu3.iew.iewDispStoreInsts 30693 # Number of dispatched store instructions -system.cpu3.iew.iewDispNonSpecInsts 930 # Number of dispatched non-speculative instructions -system.cpu3.iew.iewIQFullEvents 49 # Number of times the IQ has become full, causing a stall +system.cpu3.iew.iewSquashCycles 1915 # Number of cycles IEW is squashing +system.cpu3.iew.iewBlockCycles 1524 # Number of cycles IEW is blocking +system.cpu3.iew.iewUnblockCycles 35 # Number of cycles IEW is unblocking +system.cpu3.iew.iewDispatchedInsts 209347 # Number of instructions dispatched to IQ +system.cpu3.iew.iewDispSquashedInsts 383 # Number of squashed instructions skipped by dispatch +system.cpu3.iew.iewDispLoadInsts 55847 # Number of dispatched load instructions +system.cpu3.iew.iewDispStoreInsts 24229 # Number of dispatched store instructions +system.cpu3.iew.iewDispNonSpecInsts 987 # Number of dispatched non-speculative instructions +system.cpu3.iew.iewIQFullEvents 33 # Number of times the IQ has become full, causing a stall system.cpu3.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu3.iew.memOrderViolationEvents 28 # Number of memory order violations -system.cpu3.iew.predictedTakenIncorrect 1047 # Number of branches that were predicted taken incorrectly -system.cpu3.iew.predictedNotTakenIncorrect 172 # Number of branches that were predicted not taken incorrectly -system.cpu3.iew.branchMispredicts 1219 # Number of branch mispredicts detected at execute -system.cpu3.iew.iewExecutedInsts 209414 # Number of executed instructions -system.cpu3.iew.iewExecLoadInsts 68288 # Number of load instructions executed -system.cpu3.iew.iewExecSquashedInsts 950 # Number of squashed instructions skipped in execute +system.cpu3.iew.memOrderViolationEvents 29 # Number of memory order violations +system.cpu3.iew.predictedTakenIncorrect 624 # Number of branches that were predicted taken incorrectly +system.cpu3.iew.predictedNotTakenIncorrect 548 # Number of branches that were predicted not taken incorrectly +system.cpu3.iew.branchMispredicts 1172 # Number of branch mispredicts detected at execute +system.cpu3.iew.iewExecutedInsts 176425 # Number of executed instructions +system.cpu3.iew.iewExecLoadInsts 55052 # Number of load instructions executed +system.cpu3.iew.iewExecSquashedInsts 783 # Number of squashed instructions skipped in execute system.cpu3.iew.exec_swp 0 # number of swp insts executed -system.cpu3.iew.exec_nop 35714 # number of nop insts executed -system.cpu3.iew.exec_refs 98584 # number of memory reference insts executed -system.cpu3.iew.exec_branches 44648 # Number of branches executed -system.cpu3.iew.exec_stores 30296 # Number of stores executed -system.cpu3.iew.exec_rate 1.053189 # Inst execution rate -system.cpu3.iew.wb_sent 209192 # cumulative count of insts sent to commit -system.cpu3.iew.wb_count 209060 # cumulative count of insts written-back -system.cpu3.iew.wb_producers 114958 # num instructions producing a value -system.cpu3.iew.wb_consumers 118605 # num instructions consuming a value +system.cpu3.iew.exec_nop 28728 # number of nop insts executed +system.cpu3.iew.exec_refs 78879 # number of memory reference insts executed +system.cpu3.iew.exec_branches 37783 # Number of branches executed +system.cpu3.iew.exec_stores 23827 # Number of stores executed +system.cpu3.iew.exec_rate 1.016788 # Inst execution rate +system.cpu3.iew.wb_sent 176246 # cumulative count of insts sent to commit +system.cpu3.iew.wb_count 176086 # cumulative count of insts written-back +system.cpu3.iew.wb_producers 95644 # num instructions producing a value +system.cpu3.iew.wb_consumers 99967 # num instructions consuming a value system.cpu3.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu3.iew.wb_rate 1.051409 # insts written-back per cycle -system.cpu3.iew.wb_fanout 0.969251 # average fanout of values written-back +system.cpu3.iew.wb_rate 1.014835 # insts written-back per cycle +system.cpu3.iew.wb_fanout 0.956756 # average fanout of values written-back system.cpu3.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu3.commit.commitCommittedInsts 240668 # The number of committed instructions -system.cpu3.commit.commitSquashedInsts 8282 # The number of squashed insts skipped by commit -system.cpu3.commit.commitNonSpecStalls 8898 # The number of times commit has been forced to stall to communicate backwards -system.cpu3.commit.branchMispredicts 1124 # The number of times a branch was mispredicted -system.cpu3.commit.committed_per_cycle::samples 187150 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::mean 1.285963 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::stdev 1.815684 # Number of insts commited each cycle +system.cpu3.commit.commitCommittedInsts 200126 # The number of committed instructions +system.cpu3.commit.commitSquashedInsts 9211 # The number of squashed insts skipped by commit +system.cpu3.commit.commitNonSpecStalls 8555 # The number of times commit has been forced to stall to communicate backwards +system.cpu3.commit.branchMispredicts 1057 # The number of times a branch was mispredicted +system.cpu3.commit.committed_per_cycle::samples 162245 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::mean 1.233480 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::stdev 1.839252 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::0 94628 50.56% 50.56% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::1 44931 24.01% 74.57% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::2 7495 4.00% 78.58% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::3 9690 5.18% 83.75% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::4 2458 1.31% 85.07% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::5 26940 14.39% 99.46% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::6 395 0.21% 99.67% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::7 129 0.07% 99.74% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::8 484 0.26% 100.00% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::0 86736 53.46% 53.46% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::1 36031 22.21% 75.67% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::2 6002 3.70% 79.37% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::3 9421 5.81% 85.17% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::4 1631 1.01% 86.18% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::5 19977 12.31% 98.49% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::6 548 0.34% 98.83% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::7 1061 0.65% 99.48% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::8 838 0.52% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::total 187150 # Number of insts commited each cycle -system.cpu3.commit.count 240668 # Number of instructions committed +system.cpu3.commit.committed_per_cycle::total 162245 # Number of insts commited each cycle +system.cpu3.commit.count 200126 # Number of instructions committed system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu3.commit.refs 97527 # Number of memory references committed -system.cpu3.commit.loads 67568 # Number of loads committed -system.cpu3.commit.membars 8180 # Number of memory barriers committed -system.cpu3.commit.branches 44100 # Number of branches committed +system.cpu3.commit.refs 77601 # Number of memory references committed +system.cpu3.commit.loads 54171 # Number of loads committed +system.cpu3.commit.membars 7839 # Number of memory barriers committed +system.cpu3.commit.branches 37226 # Number of branches committed system.cpu3.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu3.commit.int_insts 163745 # Number of committed integer instructions. +system.cpu3.commit.int_insts 136949 # Number of committed integer instructions. system.cpu3.commit.function_calls 322 # Number of function calls committed. -system.cpu3.commit.bw_lim_events 484 # number cycles where commit BW limit reached +system.cpu3.commit.bw_lim_events 838 # number cycles where commit BW limit reached system.cpu3.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu3.rob.rob_reads 435029 # The number of ROB reads -system.cpu3.rob.rob_writes 499708 # The number of ROB writes -system.cpu3.timesIdled 278 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu3.idleCycles 3154 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu3.committedInsts 197602 # Number of Instructions Simulated -system.cpu3.committedInsts_total 197602 # Number of Instructions Simulated -system.cpu3.cpi 1.006255 # CPI: Cycles Per Instruction -system.cpu3.cpi_total 1.006255 # CPI: Total CPI of All Threads -system.cpu3.ipc 0.993784 # IPC: Instructions Per Cycle -system.cpu3.ipc_total 0.993784 # IPC: Total IPC of All Threads -system.cpu3.int_regfile_reads 353198 # number of integer regfile reads -system.cpu3.int_regfile_writes 164587 # number of integer regfile writes +system.cpu3.rob.rob_reads 370157 # The number of ROB reads +system.cpu3.rob.rob_writes 420591 # The number of ROB writes +system.cpu3.timesIdled 233 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu3.idleCycles 2908 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu3.committedInsts 164273 # Number of Instructions Simulated +system.cpu3.committedInsts_total 164273 # Number of Instructions Simulated +system.cpu3.cpi 1.056242 # CPI: Cycles Per Instruction +system.cpu3.cpi_total 1.056242 # CPI: Total CPI of All Threads +system.cpu3.ipc 0.946753 # IPC: Instructions Per Cycle +system.cpu3.ipc_total 0.946753 # IPC: Total IPC of All Threads +system.cpu3.int_regfile_reads 294835 # number of integer regfile reads +system.cpu3.int_regfile_writes 139001 # number of integer regfile writes system.cpu3.fp_regfile_writes 64 # number of floating regfile writes -system.cpu3.misc_regfile_reads 100115 # number of misc regfile reads +system.cpu3.misc_regfile_reads 80433 # number of misc regfile reads system.cpu3.misc_regfile_writes 646 # number of misc regfile writes -system.cpu3.icache.replacements 334 # number of replacements -system.cpu3.icache.tagsinuse 83.539668 # Cycle average of tags in use -system.cpu3.icache.total_refs 24889 # Total number of references to valid blocks. -system.cpu3.icache.sampled_refs 440 # Sample count of references to valid blocks. -system.cpu3.icache.avg_refs 56.565909 # Average number of references to valid blocks. +system.cpu3.icache.replacements 318 # number of replacements +system.cpu3.icache.tagsinuse 80.013522 # Cycle average of tags in use +system.cpu3.icache.total_refs 24405 # Total number of references to valid blocks. +system.cpu3.icache.sampled_refs 426 # Sample count of references to valid blocks. +system.cpu3.icache.avg_refs 57.288732 # Average number of references to valid blocks. system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.icache.occ_blocks::0 83.539668 # Average occupied blocks per context -system.cpu3.icache.occ_percent::0 0.163163 # Average percentage of cache occupancy -system.cpu3.icache.ReadReq_hits 24889 # number of ReadReq hits -system.cpu3.icache.demand_hits 24889 # number of demand (read+write) hits -system.cpu3.icache.overall_hits 24889 # number of overall hits -system.cpu3.icache.ReadReq_misses 481 # number of ReadReq misses -system.cpu3.icache.demand_misses 481 # number of demand (read+write) misses -system.cpu3.icache.overall_misses 481 # number of overall misses -system.cpu3.icache.ReadReq_miss_latency 6766000 # number of ReadReq miss cycles -system.cpu3.icache.demand_miss_latency 6766000 # number of demand (read+write) miss cycles -system.cpu3.icache.overall_miss_latency 6766000 # number of overall miss cycles -system.cpu3.icache.ReadReq_accesses 25370 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.demand_accesses 25370 # number of demand (read+write) accesses -system.cpu3.icache.overall_accesses 25370 # number of overall (read+write) accesses -system.cpu3.icache.ReadReq_miss_rate 0.018959 # miss rate for ReadReq accesses -system.cpu3.icache.demand_miss_rate 0.018959 # miss rate for demand accesses -system.cpu3.icache.overall_miss_rate 0.018959 # miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_miss_latency 14066.528067 # average ReadReq miss latency -system.cpu3.icache.demand_avg_miss_latency 14066.528067 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency 14066.528067 # average overall miss latency +system.cpu3.icache.occ_blocks::0 80.013522 # Average occupied blocks per context +system.cpu3.icache.occ_percent::0 0.156276 # Average percentage of cache occupancy +system.cpu3.icache.ReadReq_hits 24405 # number of ReadReq hits +system.cpu3.icache.demand_hits 24405 # number of demand (read+write) hits +system.cpu3.icache.overall_hits 24405 # number of overall hits +system.cpu3.icache.ReadReq_misses 466 # number of ReadReq misses +system.cpu3.icache.demand_misses 466 # number of demand (read+write) misses +system.cpu3.icache.overall_misses 466 # number of overall misses +system.cpu3.icache.ReadReq_miss_latency 6656500 # number of ReadReq miss cycles +system.cpu3.icache.demand_miss_latency 6656500 # number of demand (read+write) miss cycles +system.cpu3.icache.overall_miss_latency 6656500 # number of overall miss cycles +system.cpu3.icache.ReadReq_accesses 24871 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.demand_accesses 24871 # number of demand (read+write) accesses +system.cpu3.icache.overall_accesses 24871 # number of overall (read+write) accesses +system.cpu3.icache.ReadReq_miss_rate 0.018737 # miss rate for ReadReq accesses +system.cpu3.icache.demand_miss_rate 0.018737 # miss rate for demand accesses +system.cpu3.icache.overall_miss_rate 0.018737 # miss rate for overall accesses +system.cpu3.icache.ReadReq_avg_miss_latency 14284.334764 # average ReadReq miss latency +system.cpu3.icache.demand_avg_miss_latency 14284.334764 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency 14284.334764 # average overall miss latency system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1485,67 +1496,67 @@ system.cpu3.icache.avg_blocked_cycles::no_targets no_value system.cpu3.icache.fast_writes 0 # number of fast writes performed system.cpu3.icache.cache_copies 0 # number of cache copies performed system.cpu3.icache.writebacks 0 # number of writebacks -system.cpu3.icache.ReadReq_mshr_hits 41 # number of ReadReq MSHR hits -system.cpu3.icache.demand_mshr_hits 41 # number of demand (read+write) MSHR hits -system.cpu3.icache.overall_mshr_hits 41 # number of overall MSHR hits -system.cpu3.icache.ReadReq_mshr_misses 440 # number of ReadReq MSHR misses -system.cpu3.icache.demand_mshr_misses 440 # number of demand (read+write) MSHR misses -system.cpu3.icache.overall_mshr_misses 440 # number of overall MSHR misses +system.cpu3.icache.ReadReq_mshr_hits 40 # number of ReadReq MSHR hits +system.cpu3.icache.demand_mshr_hits 40 # number of demand (read+write) MSHR hits +system.cpu3.icache.overall_mshr_hits 40 # number of overall MSHR hits +system.cpu3.icache.ReadReq_mshr_misses 426 # number of ReadReq MSHR misses +system.cpu3.icache.demand_mshr_misses 426 # number of demand (read+write) MSHR misses +system.cpu3.icache.overall_mshr_misses 426 # number of overall MSHR misses system.cpu3.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu3.icache.ReadReq_mshr_miss_latency 5068000 # number of ReadReq MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency 5068000 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency 5068000 # number of overall MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_latency 4959000 # number of ReadReq MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency 4959000 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency 4959000 # number of overall MSHR miss cycles system.cpu3.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu3.icache.ReadReq_mshr_miss_rate 0.017343 # mshr miss rate for ReadReq accesses -system.cpu3.icache.demand_mshr_miss_rate 0.017343 # mshr miss rate for demand accesses -system.cpu3.icache.overall_mshr_miss_rate 0.017343 # mshr miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_mshr_miss_latency 11518.181818 # average ReadReq mshr miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency 11518.181818 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency 11518.181818 # average overall mshr miss latency +system.cpu3.icache.ReadReq_mshr_miss_rate 0.017128 # mshr miss rate for ReadReq accesses +system.cpu3.icache.demand_mshr_miss_rate 0.017128 # mshr miss rate for demand accesses +system.cpu3.icache.overall_mshr_miss_rate 0.017128 # mshr miss rate for overall accesses +system.cpu3.icache.ReadReq_avg_mshr_miss_latency 11640.845070 # average ReadReq mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency 11640.845070 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency 11640.845070 # average overall mshr miss latency system.cpu3.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu3.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu3.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu3.dcache.replacements 2 # number of replacements -system.cpu3.dcache.tagsinuse 16.417900 # Cycle average of tags in use -system.cpu3.dcache.total_refs 35718 # Total number of references to valid blocks. -system.cpu3.dcache.sampled_refs 30 # Sample count of references to valid blocks. -system.cpu3.dcache.avg_refs 1190.600000 # Average number of references to valid blocks. +system.cpu3.dcache.tagsinuse 15.701328 # Cycle average of tags in use +system.cpu3.dcache.total_refs 29297 # Total number of references to valid blocks. +system.cpu3.dcache.sampled_refs 29 # Sample count of references to valid blocks. +system.cpu3.dcache.avg_refs 1010.241379 # Average number of references to valid blocks. system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.dcache.occ_blocks::0 24.989455 # Average occupied blocks per context -system.cpu3.dcache.occ_blocks::1 -8.571555 # Average occupied blocks per context -system.cpu3.dcache.occ_percent::0 0.048808 # Average percentage of cache occupancy -system.cpu3.dcache.occ_percent::1 -0.016741 # Average percentage of cache occupancy -system.cpu3.dcache.ReadReq_hits 41747 # number of ReadReq hits -system.cpu3.dcache.WriteReq_hits 29763 # number of WriteReq hits -system.cpu3.dcache.SwapReq_hits 14 # number of SwapReq hits -system.cpu3.dcache.demand_hits 71510 # number of demand (read+write) hits -system.cpu3.dcache.overall_hits 71510 # number of overall hits -system.cpu3.dcache.ReadReq_misses 446 # number of ReadReq misses -system.cpu3.dcache.WriteReq_misses 124 # number of WriteReq misses -system.cpu3.dcache.SwapReq_misses 58 # number of SwapReq misses -system.cpu3.dcache.demand_misses 570 # number of demand (read+write) misses -system.cpu3.dcache.overall_misses 570 # number of overall misses -system.cpu3.dcache.ReadReq_miss_latency 9927500 # number of ReadReq miss cycles -system.cpu3.dcache.WriteReq_miss_latency 2778000 # number of WriteReq miss cycles -system.cpu3.dcache.SwapReq_miss_latency 1471000 # number of SwapReq miss cycles -system.cpu3.dcache.demand_miss_latency 12705500 # number of demand (read+write) miss cycles -system.cpu3.dcache.overall_miss_latency 12705500 # number of overall miss cycles -system.cpu3.dcache.ReadReq_accesses 42193 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses 29887 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.SwapReq_accesses 72 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.demand_accesses 72080 # number of demand (read+write) accesses -system.cpu3.dcache.overall_accesses 72080 # number of overall (read+write) accesses -system.cpu3.dcache.ReadReq_miss_rate 0.010570 # miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_miss_rate 0.004149 # miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_miss_rate 0.805556 # miss rate for SwapReq accesses -system.cpu3.dcache.demand_miss_rate 0.007908 # miss rate for demand accesses -system.cpu3.dcache.overall_miss_rate 0.007908 # miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_miss_latency 22258.968610 # average ReadReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency 22403.225806 # average WriteReq miss latency -system.cpu3.dcache.SwapReq_avg_miss_latency 25362.068966 # average SwapReq miss latency -system.cpu3.dcache.demand_avg_miss_latency 22290.350877 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency 22290.350877 # average overall miss latency +system.cpu3.dcache.occ_blocks::0 23.466885 # Average occupied blocks per context +system.cpu3.dcache.occ_blocks::1 -7.765557 # Average occupied blocks per context +system.cpu3.dcache.occ_percent::0 0.045834 # Average percentage of cache occupancy +system.cpu3.dcache.occ_percent::1 -0.015167 # Average percentage of cache occupancy +system.cpu3.dcache.ReadReq_hits 35023 # number of ReadReq hits +system.cpu3.dcache.WriteReq_hits 23239 # number of WriteReq hits +system.cpu3.dcache.SwapReq_hits 16 # number of SwapReq hits +system.cpu3.dcache.demand_hits 58262 # number of demand (read+write) hits +system.cpu3.dcache.overall_hits 58262 # number of overall hits +system.cpu3.dcache.ReadReq_misses 421 # number of ReadReq misses +system.cpu3.dcache.WriteReq_misses 121 # number of WriteReq misses +system.cpu3.dcache.SwapReq_misses 54 # number of SwapReq misses +system.cpu3.dcache.demand_misses 542 # number of demand (read+write) misses +system.cpu3.dcache.overall_misses 542 # number of overall misses +system.cpu3.dcache.ReadReq_miss_latency 8723500 # number of ReadReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency 2943500 # number of WriteReq miss cycles +system.cpu3.dcache.SwapReq_miss_latency 1375000 # number of SwapReq miss cycles +system.cpu3.dcache.demand_miss_latency 11667000 # number of demand (read+write) miss cycles +system.cpu3.dcache.overall_miss_latency 11667000 # number of overall miss cycles +system.cpu3.dcache.ReadReq_accesses 35444 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses 23360 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.SwapReq_accesses 70 # number of SwapReq accesses(hits+misses) +system.cpu3.dcache.demand_accesses 58804 # number of demand (read+write) accesses +system.cpu3.dcache.overall_accesses 58804 # number of overall (read+write) accesses +system.cpu3.dcache.ReadReq_miss_rate 0.011878 # miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_miss_rate 0.005180 # miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_miss_rate 0.771429 # miss rate for SwapReq accesses +system.cpu3.dcache.demand_miss_rate 0.009217 # miss rate for demand accesses +system.cpu3.dcache.overall_miss_rate 0.009217 # miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_miss_latency 20720.902613 # average ReadReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency 24326.446281 # average WriteReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency 25462.962963 # average SwapReq miss latency +system.cpu3.dcache.demand_avg_miss_latency 21525.830258 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency 21525.830258 # average overall miss latency system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1555,178 +1566,178 @@ system.cpu3.dcache.avg_blocked_cycles::no_targets no_value system.cpu3.dcache.fast_writes 0 # number of fast writes performed system.cpu3.dcache.cache_copies 0 # number of cache copies performed system.cpu3.dcache.writebacks 1 # number of writebacks -system.cpu3.dcache.ReadReq_mshr_hits 272 # number of ReadReq MSHR hits +system.cpu3.dcache.ReadReq_mshr_hits 256 # number of ReadReq MSHR hits system.cpu3.dcache.WriteReq_mshr_hits 19 # number of WriteReq MSHR hits -system.cpu3.dcache.demand_mshr_hits 291 # number of demand (read+write) MSHR hits -system.cpu3.dcache.overall_mshr_hits 291 # number of overall MSHR hits -system.cpu3.dcache.ReadReq_mshr_misses 174 # number of ReadReq MSHR misses -system.cpu3.dcache.WriteReq_mshr_misses 105 # number of WriteReq MSHR misses -system.cpu3.dcache.SwapReq_mshr_misses 58 # number of SwapReq MSHR misses -system.cpu3.dcache.demand_mshr_misses 279 # number of demand (read+write) MSHR misses -system.cpu3.dcache.overall_mshr_misses 279 # number of overall MSHR misses +system.cpu3.dcache.demand_mshr_hits 275 # number of demand (read+write) MSHR hits +system.cpu3.dcache.overall_mshr_hits 275 # number of overall MSHR hits +system.cpu3.dcache.ReadReq_mshr_misses 165 # number of ReadReq MSHR misses +system.cpu3.dcache.WriteReq_mshr_misses 102 # number of WriteReq MSHR misses +system.cpu3.dcache.SwapReq_mshr_misses 54 # number of SwapReq MSHR misses +system.cpu3.dcache.demand_mshr_misses 267 # number of demand (read+write) MSHR misses +system.cpu3.dcache.overall_mshr_misses 267 # number of overall MSHR misses system.cpu3.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu3.dcache.ReadReq_mshr_miss_latency 2494000 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency 1504000 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency 1297000 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency 3998000 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency 3998000 # number of overall MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_latency 2157000 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency 1669000 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.SwapReq_mshr_miss_latency 1213000 # number of SwapReq MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency 3826000 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency 3826000 # number of overall MSHR miss cycles system.cpu3.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu3.dcache.ReadReq_mshr_miss_rate 0.004124 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate 0.003513 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_mshr_miss_rate 0.805556 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.demand_mshr_miss_rate 0.003871 # mshr miss rate for demand accesses -system.cpu3.dcache.overall_mshr_miss_rate 0.003871 # mshr miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency 14333.333333 # average ReadReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency 14323.809524 # average WriteReq mshr miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency 22362.068966 # average SwapReq mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency 14329.749104 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency 14329.749104 # average overall mshr miss latency +system.cpu3.dcache.ReadReq_mshr_miss_rate 0.004655 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_rate 0.004366 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_mshr_miss_rate 0.771429 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.demand_mshr_miss_rate 0.004541 # mshr miss rate for demand accesses +system.cpu3.dcache.overall_mshr_miss_rate 0.004541 # mshr miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency 13072.727273 # average ReadReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency 16362.745098 # average WriteReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency 22462.962963 # average SwapReq mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency 14329.588015 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency 14329.588015 # average overall mshr miss latency system.cpu3.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu3.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu3.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.l2c.replacements 0 # number of replacements -system.l2c.tagsinuse 428.707153 # Cycle average of tags in use -system.l2c.total_refs 1488 # Total number of references to valid blocks. -system.l2c.sampled_refs 521 # Sample count of references to valid blocks. -system.l2c.avg_refs 2.856046 # Average number of references to valid blocks. +system.l2c.tagsinuse 428.144160 # Cycle average of tags in use +system.l2c.total_refs 1448 # Total number of references to valid blocks. +system.l2c.sampled_refs 527 # Sample count of references to valid blocks. +system.l2c.avg_refs 2.747628 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::0 348.158908 # Average occupied blocks per context -system.l2c.occ_blocks::1 9.356931 # Average occupied blocks per context -system.l2c.occ_blocks::2 63.539276 # Average occupied blocks per context -system.l2c.occ_blocks::3 2.442412 # Average occupied blocks per context -system.l2c.occ_blocks::4 5.209626 # Average occupied blocks per context -system.l2c.occ_percent::0 0.005312 # Average percentage of cache occupancy -system.l2c.occ_percent::1 0.000143 # Average percentage of cache occupancy -system.l2c.occ_percent::2 0.000970 # Average percentage of cache occupancy +system.l2c.occ_blocks::0 347.119372 # Average occupied blocks per context +system.l2c.occ_blocks::1 10.560700 # Average occupied blocks per context +system.l2c.occ_blocks::2 63.080596 # Average occupied blocks per context +system.l2c.occ_blocks::3 2.422702 # Average occupied blocks per context +system.l2c.occ_blocks::4 4.960789 # Average occupied blocks per context +system.l2c.occ_percent::0 0.005297 # Average percentage of cache occupancy +system.l2c.occ_percent::1 0.000161 # Average percentage of cache occupancy +system.l2c.occ_percent::2 0.000963 # Average percentage of cache occupancy system.l2c.occ_percent::3 0.000037 # Average percentage of cache occupancy -system.l2c.occ_percent::4 0.000079 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::0 232 # number of ReadReq hits -system.l2c.ReadReq_hits::1 440 # number of ReadReq hits -system.l2c.ReadReq_hits::2 370 # number of ReadReq hits -system.l2c.ReadReq_hits::3 449 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1491 # number of ReadReq hits +system.l2c.occ_percent::4 0.000076 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::0 233 # number of ReadReq hits +system.l2c.ReadReq_hits::1 425 # number of ReadReq hits +system.l2c.ReadReq_hits::2 360 # number of ReadReq hits +system.l2c.ReadReq_hits::3 433 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1451 # number of ReadReq hits system.l2c.Writeback_hits::0 9 # number of Writeback hits system.l2c.Writeback_hits::total 9 # number of Writeback hits system.l2c.UpgradeReq_hits::0 3 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 3 # number of UpgradeReq hits -system.l2c.demand_hits::0 232 # number of demand (read+write) hits -system.l2c.demand_hits::1 440 # number of demand (read+write) hits -system.l2c.demand_hits::2 370 # number of demand (read+write) hits -system.l2c.demand_hits::3 449 # number of demand (read+write) hits -system.l2c.demand_hits::total 1491 # number of demand (read+write) hits -system.l2c.overall_hits::0 232 # number of overall hits -system.l2c.overall_hits::1 440 # number of overall hits -system.l2c.overall_hits::2 370 # number of overall hits -system.l2c.overall_hits::3 449 # number of overall hits -system.l2c.overall_hits::total 1491 # number of overall hits -system.l2c.ReadReq_misses::0 425 # number of ReadReq misses +system.l2c.demand_hits::0 233 # number of demand (read+write) hits +system.l2c.demand_hits::1 425 # number of demand (read+write) hits +system.l2c.demand_hits::2 360 # number of demand (read+write) hits +system.l2c.demand_hits::3 433 # number of demand (read+write) hits +system.l2c.demand_hits::total 1451 # number of demand (read+write) hits +system.l2c.overall_hits::0 233 # number of overall hits +system.l2c.overall_hits::1 425 # number of overall hits +system.l2c.overall_hits::2 360 # number of overall hits +system.l2c.overall_hits::3 433 # number of overall hits +system.l2c.overall_hits::total 1451 # number of overall hits +system.l2c.ReadReq_misses::0 429 # number of ReadReq misses system.l2c.ReadReq_misses::1 15 # number of ReadReq misses -system.l2c.ReadReq_misses::2 82 # number of ReadReq misses -system.l2c.ReadReq_misses::3 4 # number of ReadReq misses -system.l2c.ReadReq_misses::total 526 # number of ReadReq misses -system.l2c.UpgradeReq_misses::0 26 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::1 25 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::2 23 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::3 19 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 93 # number of UpgradeReq misses +system.l2c.ReadReq_misses::2 83 # number of ReadReq misses +system.l2c.ReadReq_misses::3 6 # number of ReadReq misses +system.l2c.ReadReq_misses::total 533 # number of ReadReq misses +system.l2c.UpgradeReq_misses::0 21 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::1 23 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::2 19 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::3 24 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 87 # number of UpgradeReq misses system.l2c.ReadExReq_misses::0 94 # number of ReadExReq misses system.l2c.ReadExReq_misses::1 12 # number of ReadExReq misses system.l2c.ReadExReq_misses::2 13 # number of ReadExReq misses system.l2c.ReadExReq_misses::3 12 # number of ReadExReq misses system.l2c.ReadExReq_misses::total 131 # number of ReadExReq misses -system.l2c.demand_misses::0 519 # number of demand (read+write) misses +system.l2c.demand_misses::0 523 # number of demand (read+write) misses system.l2c.demand_misses::1 27 # number of demand (read+write) misses -system.l2c.demand_misses::2 95 # number of demand (read+write) misses -system.l2c.demand_misses::3 16 # number of demand (read+write) misses -system.l2c.demand_misses::total 657 # number of demand (read+write) misses -system.l2c.overall_misses::0 519 # number of overall misses +system.l2c.demand_misses::2 96 # number of demand (read+write) misses +system.l2c.demand_misses::3 18 # number of demand (read+write) misses +system.l2c.demand_misses::total 664 # number of demand (read+write) misses +system.l2c.overall_misses::0 523 # number of overall misses system.l2c.overall_misses::1 27 # number of overall misses -system.l2c.overall_misses::2 95 # number of overall misses -system.l2c.overall_misses::3 16 # number of overall misses -system.l2c.overall_misses::total 657 # number of overall misses -system.l2c.ReadReq_miss_latency 27341000 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency 156000 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency 6879000 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency 34220000 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency 34220000 # number of overall miss cycles -system.l2c.ReadReq_accesses::0 657 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::1 455 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::2 452 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::3 453 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2017 # number of ReadReq accesses(hits+misses) +system.l2c.overall_misses::2 96 # number of overall misses +system.l2c.overall_misses::3 18 # number of overall misses +system.l2c.overall_misses::total 664 # number of overall misses +system.l2c.ReadReq_miss_latency 27698500 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency 157500 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency 6878000 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency 34576500 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency 34576500 # number of overall miss cycles +system.l2c.ReadReq_accesses::0 662 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::1 440 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::2 443 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::3 439 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1984 # number of ReadReq accesses(hits+misses) system.l2c.Writeback_accesses::0 9 # number of Writeback accesses(hits+misses) system.l2c.Writeback_accesses::total 9 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::0 29 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::1 25 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::2 23 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::3 19 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 96 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::0 24 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::1 23 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::2 19 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::3 24 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 90 # number of UpgradeReq accesses(hits+misses) system.l2c.ReadExReq_accesses::0 94 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::1 12 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::2 13 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::3 12 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::total 131 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::0 751 # number of demand (read+write) accesses -system.l2c.demand_accesses::1 467 # number of demand (read+write) accesses -system.l2c.demand_accesses::2 465 # number of demand (read+write) accesses -system.l2c.demand_accesses::3 465 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2148 # number of demand (read+write) accesses -system.l2c.overall_accesses::0 751 # number of overall (read+write) accesses -system.l2c.overall_accesses::1 467 # number of overall (read+write) accesses -system.l2c.overall_accesses::2 465 # number of overall (read+write) accesses -system.l2c.overall_accesses::3 465 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2148 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::0 0.646880 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::1 0.032967 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::2 0.181416 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::3 0.008830 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.870093 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::0 0.896552 # miss rate for UpgradeReq accesses +system.l2c.demand_accesses::0 756 # number of demand (read+write) accesses +system.l2c.demand_accesses::1 452 # number of demand (read+write) accesses +system.l2c.demand_accesses::2 456 # number of demand (read+write) accesses +system.l2c.demand_accesses::3 451 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2115 # number of demand (read+write) accesses +system.l2c.overall_accesses::0 756 # number of overall (read+write) accesses +system.l2c.overall_accesses::1 452 # number of overall (read+write) accesses +system.l2c.overall_accesses::2 456 # number of overall (read+write) accesses +system.l2c.overall_accesses::3 451 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2115 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::0 0.648036 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::1 0.034091 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::2 0.187359 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::3 0.013667 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.883154 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::0 0.875000 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::1 1 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::2 1 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::3 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 3.896552 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 3.875000 # miss rate for UpgradeReq accesses system.l2c.ReadExReq_miss_rate::0 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::1 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::2 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::3 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::total 4 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::0 0.691079 # miss rate for demand accesses -system.l2c.demand_miss_rate::1 0.057816 # miss rate for demand accesses -system.l2c.demand_miss_rate::2 0.204301 # miss rate for demand accesses -system.l2c.demand_miss_rate::3 0.034409 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.987604 # miss rate for demand accesses -system.l2c.overall_miss_rate::0 0.691079 # miss rate for overall accesses -system.l2c.overall_miss_rate::1 0.057816 # miss rate for overall accesses -system.l2c.overall_miss_rate::2 0.204301 # miss rate for overall accesses -system.l2c.overall_miss_rate::3 0.034409 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.987604 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::0 64331.764706 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::1 1822733.333333 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::2 333426.829268 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::3 6835250 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 9055741.927308 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::0 6000 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::1 6240 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::2 6782.608696 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::3 8210.526316 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 27233.135011 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::0 73180.851064 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::1 573250 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::2 529153.846154 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::3 573250 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 1748834.697218 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::0 65934.489403 # average overall miss latency -system.l2c.demand_avg_miss_latency::1 1267407.407407 # average overall miss latency -system.l2c.demand_avg_miss_latency::2 360210.526316 # average overall miss latency -system.l2c.demand_avg_miss_latency::3 2138750 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 3832302.423126 # average overall miss latency -system.l2c.overall_avg_miss_latency::0 65934.489403 # average overall miss latency -system.l2c.overall_avg_miss_latency::1 1267407.407407 # average overall miss latency -system.l2c.overall_avg_miss_latency::2 360210.526316 # average overall miss latency -system.l2c.overall_avg_miss_latency::3 2138750 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 3832302.423126 # average overall miss latency +system.l2c.demand_miss_rate::0 0.691799 # miss rate for demand accesses +system.l2c.demand_miss_rate::1 0.059735 # miss rate for demand accesses +system.l2c.demand_miss_rate::2 0.210526 # miss rate for demand accesses +system.l2c.demand_miss_rate::3 0.039911 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 1.001971 # miss rate for demand accesses +system.l2c.overall_miss_rate::0 0.691799 # miss rate for overall accesses +system.l2c.overall_miss_rate::1 0.059735 # miss rate for overall accesses +system.l2c.overall_miss_rate::2 0.210526 # miss rate for overall accesses +system.l2c.overall_miss_rate::3 0.039911 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 1.001971 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::0 64565.268065 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::1 1846566.666667 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::2 333716.867470 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::3 4616416.666667 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 6861265.468868 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::0 7500 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::1 6847.826087 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::2 8289.473684 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::3 6562.500000 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 29199.799771 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::0 73170.212766 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::1 573166.666667 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::2 529076.923077 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::3 573166.666667 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 1748580.469176 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::0 66111.854685 # average overall miss latency +system.l2c.demand_avg_miss_latency::1 1280611.111111 # average overall miss latency +system.l2c.demand_avg_miss_latency::2 360171.875000 # average overall miss latency +system.l2c.demand_avg_miss_latency::3 1920916.666667 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 3627811.507462 # average overall miss latency +system.l2c.overall_avg_miss_latency::0 66111.854685 # average overall miss latency +system.l2c.overall_avg_miss_latency::1 1280611.111111 # average overall miss latency +system.l2c.overall_avg_miss_latency::2 360171.875000 # average overall miss latency +system.l2c.overall_avg_miss_latency::3 1920916.666667 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 3627811.507462 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1736,51 +1747,51 @@ system.l2c.avg_blocked_cycles::no_targets no_value # a system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed system.l2c.writebacks 0 # number of writebacks -system.l2c.ReadReq_mshr_hits 7 # number of ReadReq MSHR hits -system.l2c.demand_mshr_hits 7 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits 7 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses 519 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses 93 # number of UpgradeReq MSHR misses +system.l2c.ReadReq_mshr_hits 8 # number of ReadReq MSHR hits +system.l2c.demand_mshr_hits 8 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits 8 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses 525 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses 87 # number of UpgradeReq MSHR misses system.l2c.ReadExReq_mshr_misses 131 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses 650 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses 650 # number of overall MSHR misses +system.l2c.demand_mshr_misses 656 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses 656 # number of overall MSHR misses system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.ReadReq_mshr_miss_latency 20754000 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency 3720500 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency 20993500 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency 3480000 # number of UpgradeReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_latency 5279000 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency 26033000 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency 26033000 # number of overall MSHR miss cycles +system.l2c.demand_mshr_miss_latency 26272500 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency 26272500 # number of overall MSHR miss cycles system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::0 0.789954 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::1 1.140659 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::2 1.148230 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::3 1.145695 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 4.224539 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::0 3.206897 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::1 3.720000 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::2 4.043478 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::3 4.894737 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 15.865112 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadReq_mshr_miss_rate::0 0.793051 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::1 1.193182 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::2 1.185102 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::3 1.195900 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 4.367235 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::0 3.625000 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::1 3.782609 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::2 4.578947 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::3 3.625000 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 15.611556 # mshr miss rate for UpgradeReq accesses system.l2c.ReadExReq_mshr_miss_rate::0 1.393617 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::1 10.916667 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::2 10.076923 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::3 10.916667 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total 33.303873 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::0 0.865513 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::1 1.391863 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::2 1.397849 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::3 1.397849 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 5.053075 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::0 0.865513 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::1 1.391863 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::2 1.397849 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::3 1.397849 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 5.053075 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency 39988.439306 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 40005.376344 # average UpgradeReq mshr miss latency +system.l2c.demand_mshr_miss_rate::0 0.867725 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::1 1.451327 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::2 1.438596 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::3 1.454545 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 5.212194 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::0 0.867725 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::1 1.451327 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::2 1.438596 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::3 1.454545 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 5.212194 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency 39987.619048 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency 40297.709924 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency 40050.769231 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency 40050.769231 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency 40049.542683 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency 40049.542683 # average overall mshr miss latency system.l2c.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions |