diff options
| author | Nilay Vaish <nilay@cs.wisc.edu> | 2013-01-15 07:43:23 -0600 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2013-01-15 07:43:23 -0600 |
| commit | 4526f330622f1406fecccedf1ad9a911c6dea305 (patch) | |
| tree | e924318390cfc5e361b4fbaa25b61cda1dcc777b /tests/quick | |
| parent | f2bcf4f01ce00f98cbbfe4320a919b431637e550 (diff) | |
| download | gem5-4526f330622f1406fecccedf1ad9a911c6dea305.tar.xz | |
x86 regressions: updates due to new instructions and cpuid
Diffstat (limited to 'tests/quick')
4 files changed, 176 insertions, 226 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini index 34779af67..12b6dc7b6 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini @@ -19,6 +19,7 @@ intel_mp_table=system.intel_mp_table kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9 load_addr_mask=18446744073709551615 mem_mode=atomic +mem_ranges=0:134217727 memories=system.physmem num_work_ids=16 readfile=tests/halt.sh @@ -72,11 +73,10 @@ slave=system.membus.master[1] [system.cpu] type=AtomicSimpleCPU -children=dcache dtb dtb_walker_cache icache interrupts itb itb_walker_cache l2cache toL2Bus tracer +children=dcache dtb dtb_walker_cache icache interrupts isa itb itb_walker_cache l2cache toL2Bus tracer checker=Null clock=500 cpu_id=0 -defer_registration=false do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true @@ -85,6 +85,7 @@ fastmem=false function_trace=false function_trace_start=0 interrupts=system.cpu.interrupts +isa=system.cpu.isa itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -95,6 +96,7 @@ profile=0 progress_interval=0 simulate_data_stalls=false simulate_inst_stalls=false +switched_out=false system=system tracer=system.cpu.tracer width=1 @@ -109,21 +111,16 @@ assoc=4 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=32768 -subblock_size=0 system=system tgts_per_mshr=20 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port @@ -148,21 +145,16 @@ assoc=2 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=10 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=1024 -subblock_size=0 system=system tgts_per_mshr=12 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.dtb.walker.port @@ -175,21 +167,16 @@ assoc=1 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=32768 -subblock_size=0 system=system tgts_per_mshr=20 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port @@ -202,10 +189,13 @@ int_latency=1000 pio_addr=2305843009213693952 pio_latency=100000 system=system -int_master=system.membus.slave[4] +int_master=system.membus.slave[3] int_slave=system.membus.master[3] pio=system.membus.master[2] +[system.cpu.isa] +type=X86ISA + [system.cpu.itb] type=X86TLB children=walker @@ -225,21 +215,16 @@ assoc=2 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=10 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=1024 -subblock_size=0 system=system tgts_per_mshr=12 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.itb.walker.port @@ -252,25 +237,20 @@ assoc=8 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=20 is_top_level=false max_miss_count=0 mshrs=20 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=20 size=4194304 -subblock_size=0 system=system tgts_per_mshr=12 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.toL2Bus.master[0] -mem_side=system.membus.slave[3] +mem_side=system.membus.slave[2] [system.cpu.toL2Bus] type=CoherentBus @@ -666,25 +646,20 @@ assoc=8 block_size=64 clock=1000 forward_snoops=false -hash_delay=1 hit_latency=50 is_top_level=true max_miss_count=0 mshrs=20 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=50 size=1024 -subblock_size=0 system=system tgts_per_mshr=12 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.iobus.master[18] -mem_side=system.membus.slave[2] +mem_side=system.membus.slave[4] [system.membus] type=CoherentBus @@ -696,7 +671,7 @@ use_default_range=false width=8 default=system.membus.badaddr_responder.pio master=system.physmem.port system.bridge.slave system.cpu.interrupts.pio system.cpu.interrupts.int_slave -slave=system.apicbridge.master system.system_port system.iocache.mem_side system.cpu.l2cache.mem_side system.cpu.interrupts.int_master +slave=system.apicbridge.master system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master system.iocache.mem_side [system.membus.badaddr_responder] type=IsaFake diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt index 867a605e4..4d2d6b5c4 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 5.112041 # Number of seconds simulated -sim_ticks 5112040968500 # Number of ticks simulated -final_tick 5112040968500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 5112040970500 # Number of ticks simulated +final_tick 5112040970500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 468346 # Simulator instruction rate (inst/s) -host_op_rate 958973 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 11982395829 # Simulator tick rate (ticks/s) -host_mem_usage 354180 # Number of bytes of host memory used -host_seconds 426.63 # Real time elapsed on the host -sim_insts 199810236 # Number of instructions simulated -sim_ops 409125920 # Number of ops (including micro ops) simulated +host_inst_rate 1661898 # Simulator instruction rate (inst/s) +host_op_rate 3402855 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 42518772648 # Simulator tick rate (ticks/s) +host_mem_usage 621064 # Number of bytes of host memory used +host_seconds 120.23 # Real time elapsed on the host +sim_insts 199810242 # Number of instructions simulated +sim_ops 409125923 # Number of ops (including micro ops) simulated system.physmem.bytes_read::pc.south_bridge.ide 2464640 # Number of bytes read from this memory system.physmem.bytes_read::cpu.dtb.walker 128 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory @@ -209,7 +209,7 @@ system.iocache.tagsinuse 0.042402 # Cy system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.sampled_refs 47585 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 4994776680059 # Cycle when the warmup percentage was hit. +system.iocache.warmup_cycle 4994776682059 # Cycle when the warmup percentage was hit. system.iocache.occ_blocks::pc.south_bridge.ide 0.042402 # Average occupied blocks per requestor system.iocache.occ_percent::pc.south_bridge.ide 0.002650 # Average percentage of cache occupancy system.iocache.occ_percent::total 0.002650 # Average percentage of cache occupancy @@ -260,57 +260,57 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.cpu.numCycles 10224081960 # number of cpu cycles simulated +system.cpu.numCycles 10224081964 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 199810236 # Number of instructions committed -system.cpu.committedOps 409125920 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 374289911 # Number of integer alu accesses +system.cpu.committedInsts 199810242 # Number of instructions committed +system.cpu.committedOps 409125923 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 374289914 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu.num_func_calls 0 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 39954536 # number of instructions that are conditional controls -system.cpu.num_int_insts 374289911 # number of integer instructions +system.cpu.num_conditional_control_insts 39954535 # number of instructions that are conditional controls +system.cpu.num_int_insts 374289914 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 915450709 # number of times the integer registers were read -system.cpu.num_int_register_writes 480322748 # number of times the integer registers were written +system.cpu.num_int_register_reads 915450706 # number of times the integer registers were read +system.cpu.num_int_register_writes 480322745 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 35624588 # number of memory refs +system.cpu.num_mem_refs 35624590 # number of memory refs system.cpu.num_load_insts 27216588 # Number of load instructions -system.cpu.num_store_insts 8408000 # Number of store instructions -system.cpu.num_idle_cycles 9770609595.971962 # Number of idle cycles -system.cpu.num_busy_cycles 453472364.028039 # Number of busy cycles +system.cpu.num_store_insts 8408002 # Number of store instructions +system.cpu.num_idle_cycles 9770609597.971960 # Number of idle cycles +system.cpu.num_busy_cycles 453472366.028039 # Number of busy cycles system.cpu.not_idle_fraction 0.044353 # Percentage of non-idle cycles system.cpu.idle_fraction 0.955647 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu.icache.replacements 790732 # number of replacements -system.cpu.icache.tagsinuse 510.627676 # Cycle average of tags in use -system.cpu.icache.total_refs 243360722 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 510.627675 # Cycle average of tags in use +system.cpu.icache.total_refs 243360727 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 791244 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 307.567226 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 148763110500 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 510.627676 # Average occupied blocks per requestor +system.cpu.icache.avg_refs 307.567232 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 148763114500 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 510.627675 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.997320 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.997320 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 243360722 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 243360722 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 243360722 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 243360722 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 243360722 # number of overall hits -system.cpu.icache.overall_hits::total 243360722 # number of overall hits +system.cpu.icache.ReadReq_hits::cpu.inst 243360727 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 243360727 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 243360727 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 243360727 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 243360727 # number of overall hits +system.cpu.icache.overall_hits::total 243360727 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 791251 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 791251 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 791251 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 791251 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 791251 # number of overall misses system.cpu.icache.overall_misses::total 791251 # number of overall misses -system.cpu.icache.ReadReq_accesses::cpu.inst 244151973 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 244151973 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 244151973 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 244151973 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 244151973 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 244151973 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_accesses::cpu.inst 244151978 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 244151978 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 244151978 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 244151978 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 244151978 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 244151978 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003241 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.003241 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.003241 # miss rate for demand accesses @@ -331,7 +331,7 @@ system.cpu.itb_walker_cache.tagsinuse 3.026483 # Cy system.cpu.itb_walker_cache.total_refs 8029 # Total number of references to valid blocks. system.cpu.itb_walker_cache.sampled_refs 3346 # Sample count of references to valid blocks. system.cpu.itb_walker_cache.avg_refs 2.399582 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.warmup_cycle 5102019608500 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.warmup_cycle 5102019610500 # Cycle when the warmup percentage was hit. system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 3.026483 # Average occupied blocks per requestor system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.189155 # Average percentage of cache occupancy system.cpu.itb_walker_cache.occ_percent::total 0.189155 # Average percentage of cache occupancy @@ -379,7 +379,7 @@ system.cpu.dtb_walker_cache.tagsinuse 5.013746 # Cy system.cpu.dtb_walker_cache.total_refs 13015 # Total number of references to valid blocks. system.cpu.dtb_walker_cache.sampled_refs 7611 # Sample count of references to valid blocks. system.cpu.dtb_walker_cache.avg_refs 1.710025 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.warmup_cycle 5101206384000 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.warmup_cycle 5101206386000 # Cycle when the warmup percentage was hit. system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 5.013746 # Average occupied blocks per requestor system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.313359 # Average percentage of cache occupancy system.cpu.dtb_walker_cache.occ_percent::total 0.313359 # Average percentage of cache occupancy @@ -420,21 +420,21 @@ system.cpu.dtb_walker_cache.writebacks::total 2556 system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 1621135 # number of replacements system.cpu.dcache.tagsinuse 511.999456 # Cycle average of tags in use -system.cpu.dcache.total_refs 20140429 # Total number of references to valid blocks. +system.cpu.dcache.total_refs 20140431 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 1621647 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 12.419737 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 12.419738 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 7549500 # Cycle when the warmup percentage was hit. system.cpu.dcache.occ_blocks::cpu.data 511.999456 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999999 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999999 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 12055941 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 12055941 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8082226 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8082226 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 20138167 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 20138167 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 20138167 # number of overall hits -system.cpu.dcache.overall_hits::total 20138167 # number of overall hits +system.cpu.dcache.WriteReq_hits::cpu.data 8082228 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8082228 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 20138169 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 20138169 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 20138169 # number of overall hits +system.cpu.dcache.overall_hits::total 20138169 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 1308091 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 1308091 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 315828 # number of WriteReq misses @@ -445,12 +445,12 @@ system.cpu.dcache.overall_misses::cpu.data 1623919 # system.cpu.dcache.overall_misses::total 1623919 # number of overall misses system.cpu.dcache.ReadReq_accesses::cpu.data 13364032 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 13364032 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 8398054 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8398054 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 21762086 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21762086 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 21762086 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21762086 # number of overall (read+write) accesses +system.cpu.dcache.WriteReq_accesses::cpu.data 8398056 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 8398056 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 21762088 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 21762088 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 21762088 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 21762088 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097881 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.097881 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037607 # miss rate for WriteReq accesses @@ -471,16 +471,16 @@ system.cpu.dcache.writebacks::writebacks 1534848 # nu system.cpu.dcache.writebacks::total 1534848 # number of writebacks system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 106558 # number of replacements -system.cpu.l2cache.tagsinuse 64822.149247 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 64822.149219 # Cycle average of tags in use system.cpu.l2cache.total_refs 3456224 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 170677 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 20.250086 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 51981.453140 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::writebacks 51981.453118 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.dtb.walker 0.004954 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.132114 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 2434.994083 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 10405.564957 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 2434.994082 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 10405.564951 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.793174 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini index f706fe351..378234e02 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini @@ -19,6 +19,7 @@ intel_mp_table=system.intel_mp_table kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9 load_addr_mask=18446744073709551615 mem_mode=timing +mem_ranges=0:134217727 memories=system.physmem num_work_ids=16 readfile=tests/halt.sh @@ -72,11 +73,10 @@ slave=system.membus.master[1] [system.cpu] type=TimingSimpleCPU -children=dcache dtb dtb_walker_cache icache interrupts itb itb_walker_cache l2cache toL2Bus tracer +children=dcache dtb dtb_walker_cache icache interrupts isa itb itb_walker_cache l2cache toL2Bus tracer checker=Null clock=500 cpu_id=0 -defer_registration=false do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true @@ -84,6 +84,7 @@ dtb=system.cpu.dtb function_trace=false function_trace_start=0 interrupts=system.cpu.interrupts +isa=system.cpu.isa itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -92,6 +93,7 @@ max_loads_any_thread=0 numThreads=1 profile=0 progress_interval=0 +switched_out=false system=system tracer=system.cpu.tracer workload= @@ -105,21 +107,16 @@ assoc=4 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=32768 -subblock_size=0 system=system tgts_per_mshr=20 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port @@ -144,21 +141,16 @@ assoc=2 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=10 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=1024 -subblock_size=0 system=system tgts_per_mshr=12 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.dtb.walker.port @@ -171,21 +163,16 @@ assoc=1 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=32768 -subblock_size=0 system=system tgts_per_mshr=20 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port @@ -198,10 +185,13 @@ int_latency=1000 pio_addr=2305843009213693952 pio_latency=100000 system=system -int_master=system.membus.slave[4] +int_master=system.membus.slave[3] int_slave=system.membus.master[3] pio=system.membus.master[2] +[system.cpu.isa] +type=X86ISA + [system.cpu.itb] type=X86TLB children=walker @@ -221,21 +211,16 @@ assoc=2 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=10 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=1024 -subblock_size=0 system=system tgts_per_mshr=12 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.itb.walker.port @@ -248,25 +233,20 @@ assoc=8 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=20 is_top_level=false max_miss_count=0 mshrs=20 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=20 size=4194304 -subblock_size=0 system=system tgts_per_mshr=12 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.toL2Bus.master[0] -mem_side=system.membus.slave[3] +mem_side=system.membus.slave[2] [system.cpu.toL2Bus] type=CoherentBus @@ -662,25 +642,20 @@ assoc=8 block_size=64 clock=1000 forward_snoops=false -hash_delay=1 hit_latency=50 is_top_level=true max_miss_count=0 mshrs=20 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=50 size=1024 -subblock_size=0 system=system tgts_per_mshr=12 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.iobus.master[18] -mem_side=system.membus.slave[2] +mem_side=system.membus.slave[4] [system.membus] type=CoherentBus @@ -692,7 +667,7 @@ use_default_range=false width=8 default=system.membus.badaddr_responder.pio master=system.physmem.port system.bridge.slave system.cpu.interrupts.pio system.cpu.interrupts.int_slave -slave=system.apicbridge.master system.system_port system.iocache.mem_side system.cpu.l2cache.mem_side system.cpu.interrupts.int_master +slave=system.apicbridge.master system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master system.iocache.mem_side [system.membus.badaddr_responder] type=IsaFake diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt index b63186d21..5586ee7f0 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt @@ -4,13 +4,13 @@ sim_seconds 5.191113 # Nu sim_ticks 5191112864000 # Number of ticks simulated final_tick 5191112864000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1106680 # Simulator instruction rate (inst/s) -host_op_rate 2133324 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 44796411922 # Simulator tick rate (ticks/s) -host_mem_usage 384016 # Number of bytes of host memory used -host_seconds 115.88 # Real time elapsed on the host -sim_insts 128244614 # Number of instructions simulated -sim_ops 247214600 # Number of ops (including micro ops) simulated +host_inst_rate 1076481 # Simulator instruction rate (inst/s) +host_op_rate 2075111 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 43574012985 # Simulator tick rate (ticks/s) +host_mem_usage 651144 # Number of bytes of host memory used +host_seconds 119.13 # Real time elapsed on the host +sim_insts 128244620 # Number of instructions simulated +sim_ops 247214608 # Number of ops (including micro ops) simulated system.physmem.bytes_read::pc.south_bridge.ide 2852352 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 825984 # Number of bytes read from this memory @@ -179,14 +179,14 @@ system.physmem.wrQLenPdf::29 1 # Wh system.physmem.wrQLenPdf::30 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 2876233269 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 6438459269 # Sum of mem lat for all requests +system.physmem.totQLat 2876225269 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 6438451269 # Sum of mem lat for all requests system.physmem.totBusLat 793712000 # Total cycles spent in databus access system.physmem.totBankLat 2768514000 # Total cycles spent in bank access -system.physmem.avgQLat 14495.10 # Average queueing delay per request +system.physmem.avgQLat 14495.06 # Average queueing delay per request system.physmem.avgBankLat 13952.23 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 32447.33 # Average memory access latency +system.physmem.avgMemAccLat 32447.29 # Average memory access latency system.physmem.avgRdBW 2.45 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 1.57 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 2.45 # Average consumed read bandwidth in MB/s @@ -307,21 +307,21 @@ system.pc.south_bridge.ide.disks1.dma_write_txs 1 system.cpu.numCycles 10382225728 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 128244614 # Number of instructions committed -system.cpu.committedOps 247214600 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 231949861 # Number of integer alu accesses +system.cpu.committedInsts 128244620 # Number of instructions committed +system.cpu.committedOps 247214608 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 231949869 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu.num_func_calls 0 # number of times a function call or return occured system.cpu.num_conditional_control_insts 23149723 # number of instructions that are conditional controls -system.cpu.num_int_insts 231949861 # number of integer instructions +system.cpu.num_int_insts 231949869 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 566905512 # number of times the integer registers were read -system.cpu.num_int_register_writes 293156466 # number of times the integer registers were written +system.cpu.num_int_register_reads 566905534 # number of times the integer registers were read +system.cpu.num_int_register_writes 293156476 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 22227093 # number of memory refs +system.cpu.num_mem_refs 22227095 # number of memory refs system.cpu.num_load_insts 13866667 # Number of load instructions -system.cpu.num_store_insts 8360426 # Number of store instructions +system.cpu.num_store_insts 8360428 # Number of store instructions system.cpu.num_idle_cycles 9781583060.998116 # Number of idle cycles system.cpu.num_busy_cycles 600642667.001884 # Number of busy cycles system.cpu.not_idle_fraction 0.057853 # Percentage of non-idle cycles @@ -330,19 +330,19 @@ system.cpu.kern.inst.arm 0 # nu system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu.icache.replacements 790930 # number of replacements system.cpu.icache.tagsinuse 510.376048 # Cycle average of tags in use -system.cpu.icache.total_refs 144455339 # Total number of references to valid blocks. +system.cpu.icache.total_refs 144455345 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 791442 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 182.521700 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 182.521707 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 159759301000 # Cycle when the warmup percentage was hit. system.cpu.icache.occ_blocks::cpu.inst 510.376048 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.996828 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.996828 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 144455339 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 144455339 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 144455339 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 144455339 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 144455339 # number of overall hits -system.cpu.icache.overall_hits::total 144455339 # number of overall hits +system.cpu.icache.ReadReq_hits::cpu.inst 144455345 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 144455345 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 144455345 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 144455345 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 144455345 # number of overall hits +system.cpu.icache.overall_hits::total 144455345 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 791449 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 791449 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 791449 # number of demand (read+write) misses @@ -355,12 +355,12 @@ system.cpu.icache.demand_miss_latency::cpu.inst 10871281000 system.cpu.icache.demand_miss_latency::total 10871281000 # number of demand (read+write) miss cycles system.cpu.icache.overall_miss_latency::cpu.inst 10871281000 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 10871281000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 145246788 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 145246788 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 145246788 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 145246788 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 145246788 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 145246788 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_accesses::cpu.inst 145246794 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 145246794 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 145246794 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 145246794 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 145246794 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 145246794 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005449 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.005449 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.005449 # miss rate for demand accesses @@ -572,21 +572,21 @@ system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 8766.151838 system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 1620901 # number of replacements system.cpu.dcache.tagsinuse 511.997778 # Cycle average of tags in use -system.cpu.dcache.total_refs 20018688 # Total number of references to valid blocks. +system.cpu.dcache.total_refs 20018690 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 1621413 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 12.346446 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 12.346447 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 38749000 # Cycle when the warmup percentage was hit. system.cpu.dcache.occ_blocks::cpu.data 511.997778 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999996 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999996 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 11981580 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 11981580 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8034926 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8034926 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 20016506 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 20016506 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 20016506 # number of overall hits -system.cpu.dcache.overall_hits::total 20016506 # number of overall hits +system.cpu.dcache.WriteReq_hits::cpu.data 8034928 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8034928 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 20016508 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 20016508 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 20016508 # number of overall hits +system.cpu.dcache.overall_hits::total 20016508 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 1308145 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 1308145 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 315486 # number of WriteReq misses @@ -595,22 +595,22 @@ system.cpu.dcache.demand_misses::cpu.data 1623631 # n system.cpu.dcache.demand_misses::total 1623631 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 1623631 # number of overall misses system.cpu.dcache.overall_misses::total 1623631 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 18313644000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 18313644000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 18313636000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 18313636000 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 8702717500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 8702717500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 27016361500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 27016361500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 27016361500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 27016361500 # number of overall miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 27016353500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 27016353500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 27016353500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 27016353500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 13289725 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 13289725 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 8350412 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8350412 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 21640137 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21640137 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 21640137 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21640137 # number of overall (read+write) accesses +system.cpu.dcache.WriteReq_accesses::cpu.data 8350414 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 8350414 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 21640139 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 21640139 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 21640139 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 21640139 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098433 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.098433 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037781 # miss rate for WriteReq accesses @@ -619,14 +619,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.075029 system.cpu.dcache.demand_miss_rate::total 0.075029 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.075029 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.075029 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13999.704926 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13999.704926 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13999.698810 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13999.698810 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27585.114712 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 27585.114712 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 16639.471345 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 16639.471345 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 16639.471345 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 16639.471345 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 16639.466418 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 16639.466418 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 16639.466418 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 16639.466418 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -645,14 +645,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1623631 system.cpu.dcache.demand_mshr_misses::total 1623631 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 1623631 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 1623631 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 15697354000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 15697354000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 15697346000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 15697346000 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8071745500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 8071745500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23769099500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 23769099500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23769099500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 23769099500 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23769091500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 23769091500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23769091500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 23769091500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 94147176000 # number of ReadReq MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 94147176000 # number of ReadReq MSHR uncacheable cycles system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2469978500 # number of WriteReq MSHR uncacheable cycles @@ -667,14 +667,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.075029 system.cpu.dcache.demand_mshr_miss_rate::total 0.075029 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.075029 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.075029 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11999.704926 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11999.704926 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11999.698810 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11999.698810 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25585.114712 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25585.114712 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14639.471345 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 14639.471345 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14639.471345 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 14639.471345 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14639.466418 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 14639.466418 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14639.466418 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 14639.466418 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -736,20 +736,20 @@ system.cpu.l2cache.overall_misses::cpu.data 141963 # system.cpu.l2cache.overall_misses::total 154875 # number of overall misses system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 345000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 711631000 # number of ReadReq miss cycles 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system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6912 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3081 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.inst 791436 # number of ReadReq accesses(hits+misses) @@ -789,20 +789,20 @@ system.cpu.l2cache.overall_miss_rate::cpu.data 0.087598 system.cpu.l2cache.overall_miss_rate::total 0.063944 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 69000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 55135.275432 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 56258.660711 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 55909.505382 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 56258.379348 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 55909.311888 # average ReadReq miss latency system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 12405.223881 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 12405.223881 # average UpgradeReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50416.132300 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50416.132300 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 69000 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 55135.275432 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 51586.300656 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 51882.627926 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 51586.244303 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 51882.576271 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 69000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 55135.275432 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 51586.300656 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 51882.627926 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 51586.244303 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 51882.576271 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -831,20 +831,20 @@ system.cpu.l2cache.overall_mshr_misses::cpu.data 141963 system.cpu.l2cache.overall_mshr_misses::total 154875 # number of overall MSHR misses system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 280010 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 544173395 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1230984255 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1775437660 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1230976255 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1775429660 # number of ReadReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 14316322 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 14316322 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4249333352 # number of ReadExReq MSHR miss cycles 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-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5480317607 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 6024771012 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5480309607 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 6024763012 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 86592298500 # number of ReadReq MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 86592298500 # number of ReadReq MSHR uncacheable cycles system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2307004500 # number of WriteReq MSHR uncacheable cycles @@ -869,20 +869,20 @@ system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.087598 system.cpu.l2cache.overall_mshr_miss_rate::total 0.063944 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 56002 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 42161.105989 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 43294.209369 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 42942.016205 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 43293.928006 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 42941.822711 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10683.822388 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10683.822388 # average UpgradeReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 37429.167198 # average ReadExReq mshr miss latency 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