diff options
| author | Nathan Binkert <nate@binkert.org> | 2008-07-24 16:31:54 -0700 |
|---|---|---|
| committer | Nathan Binkert <nate@binkert.org> | 2008-07-24 16:31:54 -0700 |
| commit | 0622eec53ae87e008a8d5e0e685321c69ea401d3 (patch) | |
| tree | a11ed967728a45a162e601263db3c161fe3ec82d /tests/quick | |
| parent | f3a3ab7f2cfdae687a1dc07dff10c7fa4bde921c (diff) | |
| download | gem5-0622eec53ae87e008a8d5e0e685321c69ea401d3.tar.xz | |
regress: update regressions for tty emulation fix.
Diffstat (limited to 'tests/quick')
30 files changed, 1307 insertions, 1295 deletions
diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini index 3db01031d..f857ba9ca 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini @@ -368,6 +368,7 @@ cmd=hello cwd= egid=100 env= +errout=cerr euid=100 executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello gid=100 diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt index cd104d2c8..dd4839763 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt @@ -1,111 +1,111 @@ ---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 574 # Number of BTB hits -global.BPredUnit.BTBLookups 1715 # Number of BTB lookups -global.BPredUnit.RASInCorrect 66 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 425 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 1184 # Number of conditional branches predicted -global.BPredUnit.lookups 2013 # Number of BP lookups -global.BPredUnit.usedRAS 270 # Number of times the RAS was used to get a target. -host_inst_rate 44727 # Simulator instruction rate (inst/s) -host_mem_usage 151980 # Number of bytes of host memory used -host_seconds 0.13 # Real time elapsed on the host -host_tick_rate 42091644 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 22 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 117 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 2013 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 1228 # Number of stores inserted to the mem dependence unit. +global.BPredUnit.BTBHits 665 # Number of BTB hits +global.BPredUnit.BTBLookups 1852 # Number of BTB lookups +global.BPredUnit.RASInCorrect 67 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 424 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 1300 # Number of conditional branches predicted +global.BPredUnit.lookups 2168 # Number of BP lookups +global.BPredUnit.usedRAS 288 # Number of times the RAS was used to get a target. +host_inst_rate 54768 # Simulator instruction rate (inst/s) +host_mem_usage 209744 # Number of bytes of host memory used +host_seconds 0.12 # Real time elapsed on the host +host_tick_rate 47820234 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 35 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 112 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 2210 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 1280 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 5623 # Number of instructions simulated -sim_seconds 0.000005 # Number of seconds simulated -sim_ticks 5303000 # Number of ticks simulated -system.cpu.commit.COM:branches 862 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 89 # number cycles where commit BW limit reached +sim_insts 6297 # Number of instructions simulated +sim_seconds 0.000006 # Number of seconds simulated +sim_ticks 5506500 # Number of ticks simulated +system.cpu.commit.COM:branches 1012 # Number of branches committed +system.cpu.commit.COM:bw_lim_events 113 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 9365 +system.cpu.commit.COM:committed_per_cycle.samples 9764 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 7035 7512.01% - 1 1204 1285.64% - 2 411 438.87% - 3 192 205.02% - 4 145 154.83% - 5 90 96.10% - 6 97 103.58% - 7 102 108.92% - 8 89 95.03% + 0 7128 7300.29% + 1 1385 1418.48% + 2 452 462.93% + 3 225 230.44% + 4 157 160.79% + 5 102 104.47% + 6 106 108.56% + 7 96 98.32% + 8 113 115.73% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist -system.cpu.commit.COM:count 5640 # Number of instructions committed -system.cpu.commit.COM:loads 979 # Number of loads committed +system.cpu.commit.COM:count 6314 # Number of instructions committed +system.cpu.commit.COM:loads 1168 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed -system.cpu.commit.COM:refs 1791 # Number of memory references committed +system.cpu.commit.COM:refs 2030 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 353 # The number of times a branch was mispredicted -system.cpu.commit.commitCommittedInsts 5640 # The number of committed instructions +system.cpu.commit.branchMispredicts 352 # The number of times a branch was mispredicted +system.cpu.commit.commitCommittedInsts 6314 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 4190 # The number of squashed insts skipped by commit -system.cpu.committedInsts 5623 # Number of Instructions Simulated -system.cpu.committedInsts_total 5623 # Number of Instructions Simulated -system.cpu.cpi 1.886360 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.886360 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 1566 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 10875.939850 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 8494.897959 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 1433 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 1446500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.084930 # miss rate for ReadReq accesses +system.cpu.commit.commitSquashedInsts 4192 # The number of squashed insts skipped by commit +system.cpu.committedInsts 6297 # Number of Instructions Simulated +system.cpu.committedInsts_total 6297 # Number of Instructions Simulated +system.cpu.cpi 1.749087 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.749087 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 1758 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 10996.240602 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 8551.020408 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 1625 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 1462500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.075654 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 133 # number of ReadReq misses system.cpu.dcache.ReadReq_mshr_hits 35 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 832500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.062580 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency 838000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.055745 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 98 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 812 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 8648.247978 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 7436.781609 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 441 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 3208500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.456897 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 371 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 284 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 647000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.107143 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_accesses 862 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 8662.162162 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 7459.770115 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 492 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 3205000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.429234 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 370 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 283 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 649000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.100928 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 87 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 11.188235 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 12.605882 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 2378 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 9236.111111 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 7997.297297 # average overall mshr miss latency -system.cpu.dcache.demand_hits 1874 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 4655000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.211943 # miss rate for demand accesses -system.cpu.dcache.demand_misses 504 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 319 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 1479500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.077796 # mshr miss rate for demand accesses +system.cpu.dcache.demand_accesses 2620 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 9279.324056 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 8037.837838 # average overall mshr miss latency +system.cpu.dcache.demand_hits 2117 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 4667500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.191985 # miss rate for demand accesses +system.cpu.dcache.demand_misses 503 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 318 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 1487000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.070611 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 185 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 2378 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 9236.111111 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 7997.297297 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 2620 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 9279.324056 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 8037.837838 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 1874 # number of overall hits -system.cpu.dcache.overall_miss_latency 4655000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.211943 # miss rate for overall accesses -system.cpu.dcache.overall_misses 504 # number of overall misses -system.cpu.dcache.overall_mshr_hits 319 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 1479500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.077796 # mshr miss rate for overall accesses +system.cpu.dcache.overall_hits 2117 # number of overall hits +system.cpu.dcache.overall_miss_latency 4667500 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.191985 # miss rate for overall accesses +system.cpu.dcache.overall_misses 503 # number of overall misses +system.cpu.dcache.overall_mshr_hits 318 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 1487000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.070611 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 185 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses @@ -121,101 +121,101 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 170 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 107.937594 # Cycle average of tags in use -system.cpu.dcache.total_refs 1902 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 109.392910 # Cycle average of tags in use +system.cpu.dcache.total_refs 2143 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks system.cpu.decode.DECODE:BlockedCycles 463 # Number of cycles decode is blocked system.cpu.decode.DECODE:BranchMispred 79 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 163 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 11516 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 6794 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 2076 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 792 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 231 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:BranchResolved 170 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 12212 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 7007 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 2262 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 791 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 224 # Number of squashed instructions handled by decode system.cpu.decode.DECODE:UnblockCycles 33 # Number of cycles decode is unblocking -system.cpu.dtb.accesses 2663 # DTB accesses +system.cpu.dtb.accesses 2901 # DTB accesses system.cpu.dtb.acv 0 # DTB access violations -system.cpu.dtb.hits 2604 # DTB hits -system.cpu.dtb.misses 59 # DTB misses -system.cpu.dtb.read_accesses 1652 # DTB read accesses +system.cpu.dtb.hits 2837 # DTB hits +system.cpu.dtb.misses 64 # DTB misses +system.cpu.dtb.read_accesses 1842 # DTB read accesses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_hits 1614 # DTB read hits -system.cpu.dtb.read_misses 38 # DTB read misses -system.cpu.dtb.write_accesses 1011 # DTB write accesses +system.cpu.dtb.read_hits 1799 # DTB read hits +system.cpu.dtb.read_misses 43 # DTB read misses +system.cpu.dtb.write_accesses 1059 # DTB write accesses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 990 # DTB write hits +system.cpu.dtb.write_hits 1038 # DTB write hits system.cpu.dtb.write_misses 21 # DTB write misses -system.cpu.fetch.Branches 2013 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 1565 # Number of cache lines fetched -system.cpu.fetch.Cycles 3769 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 233 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 12458 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2168 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 1670 # Number of cache lines fetched +system.cpu.fetch.Cycles 4064 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 235 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 13177 # Number of instructions fetch has processed system.cpu.fetch.SquashCycles 485 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.189780 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 1565 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 844 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.174507 # Number of inst fetches per cycle +system.cpu.fetch.branchRate 0.196840 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 1670 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 953 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.196386 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 10158 +system.cpu.fetch.rateDist.samples 10556 system.cpu.fetch.rateDist.min_value 0 - 0 7986 7861.78% - 1 184 181.14% - 2 171 168.34% - 3 148 145.70% - 4 221 217.56% - 5 166 163.42% - 6 188 185.08% - 7 106 104.35% - 8 988 972.63% + 0 8192 7760.52% + 1 236 223.57% + 2 214 202.73% + 3 172 162.94% + 4 242 229.25% + 5 149 141.15% + 6 203 192.31% + 7 118 111.78% + 8 1030 975.75% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 1565 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 9178.260870 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 6606.451613 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 1220 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 3166500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.220447 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_accesses 1670 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 9198.550725 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 6610.932476 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 1325 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 3173500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.206587 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 345 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 35 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 2048000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.198083 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 310 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_hits 34 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 2056000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.186228 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 311 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 3.935484 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 4.260450 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 1565 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 9178.260870 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 6606.451613 # average overall mshr miss latency -system.cpu.icache.demand_hits 1220 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 3166500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.220447 # miss rate for demand accesses +system.cpu.icache.demand_accesses 1670 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 9198.550725 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 6610.932476 # average overall mshr miss latency +system.cpu.icache.demand_hits 1325 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 3173500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.206587 # miss rate for demand accesses system.cpu.icache.demand_misses 345 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 35 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 2048000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.198083 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 310 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_hits 34 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 2056000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.186228 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 311 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 1565 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 9178.260870 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 6606.451613 # average overall mshr miss latency +system.cpu.icache.overall_accesses 1670 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 9198.550725 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 6610.932476 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 1220 # number of overall hits -system.cpu.icache.overall_miss_latency 3166500 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.220447 # miss rate for overall accesses +system.cpu.icache.overall_hits 1325 # number of overall hits +system.cpu.icache.overall_miss_latency 3173500 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.206587 # miss rate for overall accesses system.cpu.icache.overall_misses 345 # number of overall misses -system.cpu.icache.overall_mshr_hits 35 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 2048000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.198083 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 310 # number of overall MSHR misses +system.cpu.icache.overall_mshr_hits 34 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 2056000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.186228 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 311 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -228,61 +228,61 @@ system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.sampled_refs 310 # Sample count of references to valid blocks. +system.cpu.icache.sampled_refs 311 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 162.483905 # Cycle average of tags in use -system.cpu.icache.total_refs 1220 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 166.219676 # Cycle average of tags in use +system.cpu.icache.total_refs 1325 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 449 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 1210 # Number of branches executed -system.cpu.iew.EXEC:nop 70 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.759310 # Inst execution rate -system.cpu.iew.EXEC:refs 2668 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 1014 # Number of stores executed +system.cpu.idleCycles 458 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 1365 # Number of branches executed +system.cpu.iew.EXEC:nop 69 # number of nop insts executed +system.cpu.iew.EXEC:rate 0.792628 # Inst execution rate +system.cpu.iew.EXEC:refs 2907 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 1061 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 5427 # num instructions consuming a value -system.cpu.iew.WB:count 7728 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.742583 # average fanout of values written-back +system.cpu.iew.WB:consumers 5886 # num instructions consuming a value +system.cpu.iew.WB:count 8407 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.745158 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 4030 # num instructions producing a value -system.cpu.iew.WB:rate 0.728575 # insts written-back per cycle -system.cpu.iew.WB:sent 7840 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 420 # Number of branch mispredicts detected at execute +system.cpu.iew.WB:producers 4386 # num instructions producing a value +system.cpu.iew.WB:rate 0.763301 # insts written-back per cycle +system.cpu.iew.WB:sent 8526 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 417 # Number of branch mispredicts detected at execute system.cpu.iew.iewBlockCycles 4 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 2013 # Number of dispatched load instructions +system.cpu.iew.iewDispLoadInsts 2210 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 24 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 185 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 1228 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 9927 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 1654 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 350 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 8054 # Number of executed instructions +system.cpu.iew.iewDispSquashedInsts 183 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 1280 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 10601 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 1846 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 353 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 8730 # Number of executed instructions system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 792 # Number of cycles IEW is squashing +system.cpu.iew.iewSquashCycles 791 # Number of cycles IEW is squashing system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 47 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.forwLoads 40 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread.0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 68 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.memOrderViolation 67 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 1034 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 416 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 68 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 297 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.lsq.thread.0.squashedLoads 1042 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 418 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 67 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 294 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 123 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.530122 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.530122 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 8404 # Type of FU issued +system.cpu.ipc 0.571727 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.571727 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 9083 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist No_OpClass 2 0.02% # Type of FU issued - IntAlu 5587 66.48% # Type of FU issued + IntAlu 6020 66.28% # Type of FU issued IntMult 1 0.01% # Type of FU issued IntDiv 0 0.00% # Type of FU issued FloatAdd 2 0.02% # Type of FU issued @@ -291,16 +291,16 @@ system.cpu.iq.ISSUE:FU_type_0.start_dist FloatMult 0 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 1774 21.11% # Type of FU issued - MemWrite 1038 12.35% # Type of FU issued + MemRead 1973 21.72% # Type of FU issued + MemWrite 1085 11.95% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 103 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.012256 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_cnt 107 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.011780 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist No_OpClass 0 0.00% # attempts to use FU when none available - IntAlu 1 0.97% # attempts to use FU when none available + IntAlu 1 0.93% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available FloatAdd 0 0.00% # attempts to use FU when none available @@ -309,38 +309,38 @@ system.cpu.iq.ISSUE:fu_full.start_dist FloatMult 0 0.00% # attempts to use FU when none available FloatDiv 0 0.00% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 68 66.02% # attempts to use FU when none available - MemWrite 34 33.01% # attempts to use FU when none available + MemRead 72 67.29% # attempts to use FU when none available + MemWrite 34 31.78% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 10158 +system.cpu.iq.ISSUE:issued_per_cycle.samples 10556 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 6739 6634.18% - 1 1163 1144.91% - 2 838 824.97% - 3 636 626.11% - 4 450 443.00% - 5 195 191.97% - 6 92 90.57% - 7 30 29.53% - 8 15 14.77% + 0 6842 6481.62% + 1 1288 1220.16% + 2 888 841.23% + 3 723 684.92% + 4 456 431.98% + 5 198 187.57% + 6 106 100.42% + 7 40 37.89% + 8 15 14.21% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 0.792307 # Inst issue rate -system.cpu.iq.iqInstsAdded 9833 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 8404 # Number of instructions issued +system.cpu.iq.ISSUE:rate 0.824678 # Inst issue rate +system.cpu.iq.iqInstsAdded 10508 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 9083 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 24 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 3830 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 24 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 3829 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 25 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 7 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 2411 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.itb.accesses 1597 # ITB accesses +system.cpu.iq.iqSquashedOperandsExamined 2415 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.itb.accesses 1700 # ITB accesses system.cpu.itb.acv 0 # ITB acv -system.cpu.itb.hits 1565 # ITB hits -system.cpu.itb.misses 32 # ITB misses +system.cpu.itb.hits 1670 # ITB hits +system.cpu.itb.misses 30 # ITB misses system.cpu.l2cache.ReadExReq_accesses 72 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_avg_miss_latency 6111.111111 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 3111.111111 # average ReadExReq mshr miss latency @@ -350,59 +350,59 @@ system.cpu.l2cache.ReadExReq_misses 72 # nu system.cpu.l2cache.ReadExReq_mshr_miss_latency 224000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 72 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 408 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 5733.415233 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2733.415233 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_accesses 409 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 5746.323529 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2746.323529 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 1 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 2333500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.997549 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 407 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1112500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.997549 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 407 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_miss_latency 2344500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.997555 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 408 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 1120500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.997555 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 408 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 15 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 5433.333333 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2433.333333 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 81500 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_avg_miss_latency 5633.333333 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2633.333333 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 84500 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_misses 15 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 36500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 39500 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_misses 15 # number of UpgradeReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.002551 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.002545 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 480 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 5790.187891 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 2790.187891 # average overall mshr miss latency +system.cpu.l2cache.demand_accesses 481 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 5801.041667 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 2801.041667 # average overall mshr miss latency system.cpu.l2cache.demand_hits 1 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 2773500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.997917 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 479 # number of demand (read+write) misses +system.cpu.l2cache.demand_miss_latency 2784500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.997921 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 480 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 1336500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.997917 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 479 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 1344500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.997921 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 480 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 480 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 5790.187891 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 2790.187891 # average overall mshr miss latency +system.cpu.l2cache.overall_accesses 481 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 5801.041667 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 2801.041667 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 1 # number of overall hits -system.cpu.l2cache.overall_miss_latency 2773500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.997917 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 479 # number of overall misses +system.cpu.l2cache.overall_miss_latency 2784500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.997921 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 480 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 1336500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.997917 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 479 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 1344500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.997921 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 480 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -415,29 +415,29 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 392 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 393 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 215.878593 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 220.053695 # Cycle average of tags in use system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 10607 # number of cpu cycles simulated +system.cpu.numCycles 11014 # number of cpu cycles simulated system.cpu.rename.RENAME:BlockCycles 85 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 4051 # Number of HB maps that are committed -system.cpu.rename.RENAME:IdleCycles 6962 # Number of cycles rename is idle +system.cpu.rename.RENAME:CommittedMaps 4537 # Number of HB maps that are committed +system.cpu.rename.RENAME:IdleCycles 7177 # Number of cycles rename is idle system.cpu.rename.RENAME:LSQFullEvents 73 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 14001 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 10976 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 8169 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 1922 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 792 # Number of cycles rename is squashing +system.cpu.rename.RENAME:RenameLookups 14809 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 11658 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 8660 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 2106 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 791 # Number of cycles rename is squashing system.cpu.rename.RENAME:UnblockCycles 116 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 4118 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:UndoneMaps 4123 # Number of HB maps that are undone due to squashing system.cpu.rename.RENAME:serializeStallCycles 281 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializingInsts 27 # count of serializing insts renamed system.cpu.rename.RENAME:skidInsts 539 # count of insts added to the skid buffer system.cpu.rename.RENAME:tempSerializingInsts 21 # count of temporary serializing insts renamed -system.cpu.timesIdled 79 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.timesIdled 80 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 17 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout index 05d3c33eb..2c5a26de6 100644 --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 21 2008 20:12:56 -M5 started Mon Jul 21 20:18:02 2008 -M5 executing on zizzer -M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881 -M5 commit date Tue Jul 15 14:38:51 2008 -0400 +M5 compiled Jul 23 2008 15:48:11 +M5 started Wed Jul 23 15:48:39 2008 +M5 executing on blue +M5 revision 5515:47bf96eec2c6221cf91de8a078897c1b5e46cfbf +M5 commit date Wed Jul 23 15:35:08 2008 -0700 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing tests/run.py quick/00.hello/alpha/linux/o3-timing Global frequency set at 1000000000000 ticks per second Hello world! -Exiting @ tick 5303000 because target called exit() +Exiting @ tick 5506500 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini index e68e8bc1c..5214649cb 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini +++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini @@ -51,6 +51,7 @@ cmd=hello cwd= egid=100 env= +errout=cerr euid=100 executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello gid=100 diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt index c89057e77..6f4810c44 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt @@ -1,34 +1,34 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 274181 # Simulator instruction rate (inst/s) -host_mem_usage 172576 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host -host_tick_rate 135418658 # Simulator tick rate (ticks/s) +host_inst_rate 74368 # Simulator instruction rate (inst/s) +host_mem_usage 201628 # Number of bytes of host memory used +host_seconds 0.09 # Real time elapsed on the host +host_tick_rate 37260110 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 5641 # Number of instructions simulated +sim_insts 6315 # Number of instructions simulated sim_seconds 0.000003 # Number of seconds simulated -sim_ticks 2833500 # Number of ticks simulated -system.cpu.dtb.accesses 1801 # DTB accesses +sim_ticks 3170500 # Number of ticks simulated +system.cpu.dtb.accesses 2040 # DTB accesses system.cpu.dtb.acv 0 # DTB access violations -system.cpu.dtb.hits 1791 # DTB hits +system.cpu.dtb.hits 2030 # DTB hits system.cpu.dtb.misses 10 # DTB misses -system.cpu.dtb.read_accesses 986 # DTB read accesses +system.cpu.dtb.read_accesses 1175 # DTB read accesses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_hits 979 # DTB read hits +system.cpu.dtb.read_hits 1168 # DTB read hits system.cpu.dtb.read_misses 7 # DTB read misses -system.cpu.dtb.write_accesses 815 # DTB write accesses +system.cpu.dtb.write_accesses 865 # DTB write accesses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 812 # DTB write hits +system.cpu.dtb.write_hits 862 # DTB write hits system.cpu.dtb.write_misses 3 # DTB write misses system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.itb.accesses 5668 # ITB accesses +system.cpu.itb.accesses 6342 # ITB accesses system.cpu.itb.acv 0 # ITB acv -system.cpu.itb.hits 5651 # ITB hits +system.cpu.itb.hits 6325 # ITB hits system.cpu.itb.misses 17 # ITB misses system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 5668 # number of cpu cycles simulated -system.cpu.num_insts 5641 # Number of instructions executed -system.cpu.num_refs 1801 # Number of memory references +system.cpu.numCycles 6342 # number of cpu cycles simulated +system.cpu.num_insts 6315 # Number of instructions executed +system.cpu.num_refs 2040 # Number of memory references system.cpu.workload.PROG:num_syscalls 17 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout index ae7c0fe57..7e1e7de26 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout +++ b/tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 21 2008 20:12:56 -M5 started Mon Jul 21 20:13:07 2008 -M5 executing on zizzer -M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881 -M5 commit date Tue Jul 15 14:38:51 2008 -0400 +M5 compiled Jul 23 2008 15:48:11 +M5 started Wed Jul 23 15:50:09 2008 +M5 executing on blue +M5 revision 5515:47bf96eec2c6221cf91de8a078897c1b5e46cfbf +M5 commit date Wed Jul 23 15:35:08 2008 -0700 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-atomic tests/run.py quick/00.hello/alpha/linux/simple-atomic Global frequency set at 1000000000000 ticks per second Hello world! -Exiting @ tick 2833500 because target called exit() +Exiting @ tick 3170500 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini index bbb328185..43431aef9 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini @@ -166,6 +166,7 @@ cmd=hello cwd= egid=100 env= +errout=cerr euid=100 executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello gid=100 diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt index d791e0a2e..22e685732 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt @@ -1,66 +1,66 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 11324 # Simulator instruction rate (inst/s) -host_mem_usage 193960 # Number of bytes of host memory used -host_seconds 0.50 # Real time elapsed on the host -host_tick_rate 38693743 # Simulator tick rate (ticks/s) +host_inst_rate 65172 # Simulator instruction rate (inst/s) +host_mem_usage 209040 # Number of bytes of host memory used +host_seconds 0.10 # Real time elapsed on the host +host_tick_rate 208535003 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 5641 # Number of instructions simulated -sim_seconds 0.000019 # Number of seconds simulated -sim_ticks 19285000 # Number of ticks simulated -system.cpu.dcache.ReadReq_accesses 979 # number of ReadReq accesses(hits+misses) +sim_insts 6315 # Number of instructions simulated +sim_seconds 0.000020 # Number of seconds simulated +sim_ticks 20250000 # Number of ticks simulated +system.cpu.dcache.ReadReq_accesses 1168 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 27000 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 24000 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 887 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits 1076 # number of ReadReq hits system.cpu.dcache.ReadReq_miss_latency 2484000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.093973 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate 0.078767 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 92 # number of ReadReq misses system.cpu.dcache.ReadReq_mshr_miss_latency 2208000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.093973 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate 0.078767 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 92 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 812 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses 862 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_avg_miss_latency 27000 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency 24000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 725 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits 775 # number of WriteReq hits system.cpu.dcache.WriteReq_miss_latency 2349000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.107143 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.100928 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 87 # number of WriteReq misses system.cpu.dcache.WriteReq_mshr_miss_latency 2088000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.107143 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate 0.100928 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 87 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 9.854545 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 11.303030 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 1791 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses 2030 # number of demand (read+write) accesses system.cpu.dcache.demand_avg_miss_latency 27000 # average overall miss latency system.cpu.dcache.demand_avg_mshr_miss_latency 24000 # average overall mshr miss latency -system.cpu.dcache.demand_hits 1612 # number of demand (read+write) hits +system.cpu.dcache.demand_hits 1851 # number of demand (read+write) hits system.cpu.dcache.demand_miss_latency 4833000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.099944 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate 0.088177 # miss rate for demand accesses system.cpu.dcache.demand_misses 179 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_miss_latency 4296000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.099944 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate 0.088177 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 179 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 1791 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses 2030 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 27000 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 24000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 1612 # number of overall hits +system.cpu.dcache.overall_hits 1851 # number of overall hits system.cpu.dcache.overall_miss_latency 4833000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.099944 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate 0.088177 # miss rate for overall accesses system.cpu.dcache.overall_misses 179 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.dcache.overall_mshr_miss_latency 4296000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.099944 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate 0.088177 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 179 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses @@ -76,66 +76,66 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 165 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 102.207107 # Cycle average of tags in use -system.cpu.dcache.total_refs 1626 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 104.470522 # Cycle average of tags in use +system.cpu.dcache.total_refs 1865 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.dtb.accesses 1801 # DTB accesses +system.cpu.dtb.accesses 2040 # DTB accesses system.cpu.dtb.acv 0 # DTB access violations -system.cpu.dtb.hits 1791 # DTB hits +system.cpu.dtb.hits 2030 # DTB hits system.cpu.dtb.misses 10 # DTB misses -system.cpu.dtb.read_accesses 986 # DTB read accesses +system.cpu.dtb.read_accesses 1175 # DTB read accesses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_hits 979 # DTB read hits +system.cpu.dtb.read_hits 1168 # DTB read hits system.cpu.dtb.read_misses 7 # DTB read misses -system.cpu.dtb.write_accesses 815 # DTB write accesses +system.cpu.dtb.write_accesses 865 # DTB write accesses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 812 # DTB write hits +system.cpu.dtb.write_hits 862 # DTB write hits system.cpu.dtb.write_misses 3 # DTB write misses -system.cpu.icache.ReadReq_accesses 5652 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 26953.068592 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 23953.068592 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 5375 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 7466000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.049009 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 277 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 6635000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.049009 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 277 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_accesses 6326 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 26953.405018 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 23953.405018 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 6047 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 7520000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.044104 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 279 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency 6683000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.044104 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 279 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 19.404332 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 21.673835 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 5652 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 26953.068592 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 23953.068592 # average overall mshr miss latency -system.cpu.icache.demand_hits 5375 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 7466000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.049009 # miss rate for demand accesses -system.cpu.icache.demand_misses 277 # number of demand (read+write) misses +system.cpu.icache.demand_accesses 6326 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 26953.405018 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 23953.405018 # average overall mshr miss latency +system.cpu.icache.demand_hits 6047 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 7520000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.044104 # miss rate for demand accesses +system.cpu.icache.demand_misses 279 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 6635000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.049009 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 277 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_miss_latency 6683000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.044104 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 279 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 5652 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 26953.068592 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 23953.068592 # average overall mshr miss latency +system.cpu.icache.overall_accesses 6326 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 26953.405018 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 23953.405018 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 5375 # number of overall hits -system.cpu.icache.overall_miss_latency 7466000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.049009 # miss rate for overall accesses -system.cpu.icache.overall_misses 277 # number of overall misses +system.cpu.icache.overall_hits 6047 # number of overall hits +system.cpu.icache.overall_miss_latency 7520000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.044104 # miss rate for overall accesses +system.cpu.icache.overall_misses 279 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 6635000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.049009 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 277 # number of overall MSHR misses +system.cpu.icache.overall_mshr_miss_latency 6683000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.044104 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 279 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -148,16 +148,16 @@ system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.sampled_refs 277 # Sample count of references to valid blocks. +system.cpu.icache.sampled_refs 279 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 127.893604 # Cycle average of tags in use -system.cpu.icache.total_refs 5375 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 133.005587 # Cycle average of tags in use +system.cpu.icache.total_refs 6047 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.itb.accesses 5669 # ITB accesses +system.cpu.itb.accesses 6343 # ITB accesses system.cpu.itb.acv 0 # ITB acv -system.cpu.itb.hits 5652 # ITB hits +system.cpu.itb.hits 6326 # ITB hits system.cpu.itb.misses 17 # ITB misses system.cpu.l2cache.ReadExReq_accesses 73 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_avg_miss_latency 23000 # average ReadExReq miss latency @@ -168,16 +168,16 @@ system.cpu.l2cache.ReadExReq_misses 73 # nu system.cpu.l2cache.ReadExReq_mshr_miss_latency 803000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 73 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 369 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses 371 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_avg_miss_latency 23000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 1 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 8464000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.997290 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 368 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 4048000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.997290 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 368 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_miss_latency 8510000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.997305 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 370 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 4070000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.997305 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 370 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 14 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_avg_miss_latency 23000 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency @@ -189,38 +189,38 @@ system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 system.cpu.l2cache.UpgradeReq_mshr_misses 14 # number of UpgradeReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.002825 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.002809 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 442 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses 444 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 23000 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.demand_hits 1 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 10143000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.997738 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 441 # number of demand (read+write) misses +system.cpu.l2cache.demand_miss_latency 10189000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.997748 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 443 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 4851000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.997738 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 441 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 4873000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.997748 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 443 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 442 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses 444 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 23000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 1 # number of overall hits -system.cpu.l2cache.overall_miss_latency 10143000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.997738 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 441 # number of overall misses +system.cpu.l2cache.overall_miss_latency 10189000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.997748 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 443 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 4851000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.997738 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 441 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 4873000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.997748 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 443 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -233,16 +233,16 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 354 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 356 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 177.260989 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 183.192305 # Cycle average of tags in use system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 38570 # number of cpu cycles simulated -system.cpu.num_insts 5641 # Number of instructions executed -system.cpu.num_refs 1801 # Number of memory references +system.cpu.numCycles 40500 # number of cpu cycles simulated +system.cpu.num_insts 6315 # Number of instructions executed +system.cpu.num_refs 2040 # Number of memory references system.cpu.workload.PROG:num_syscalls 17 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout index c8cf5ab9d..a4ec269db 100644 --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 21 2008 20:12:56 -M5 started Mon Jul 21 20:14:04 2008 -M5 executing on zizzer -M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881 -M5 commit date Tue Jul 15 14:38:51 2008 -0400 +M5 compiled Jul 23 2008 15:48:11 +M5 started Wed Jul 23 15:50:09 2008 +M5 executing on blue +M5 revision 5515:47bf96eec2c6221cf91de8a078897c1b5e46cfbf +M5 commit date Wed Jul 23 15:35:08 2008 -0700 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing tests/run.py quick/00.hello/alpha/linux/simple-timing Global frequency set at 1000000000000 ticks per second Hello world! -Exiting @ tick 19285000 because target called exit() +Exiting @ tick 20250000 because target called exit() diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini index d13eeb4e2..a80c5cabd 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini @@ -51,6 +51,7 @@ cmd=hello cwd= egid=100 env= +errout=cerr euid=100 executable=/dist/m5/regression/test-progs/hello/bin/sparc/linux/hello gid=100 diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/m5stats.txt b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/m5stats.txt index 9a9ac5a12..c2853cc3f 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/m5stats.txt +++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/m5stats.txt @@ -1,18 +1,18 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1230 # Simulator instruction rate (inst/s) -host_mem_usage 173824 # Number of bytes of host memory used -host_seconds 3.93 # Real time elapsed on the host -host_tick_rate 622698 # Simulator tick rate (ticks/s) +host_inst_rate 31798 # Simulator instruction rate (inst/s) +host_mem_usage 202884 # Number of bytes of host memory used +host_seconds 0.17 # Real time elapsed on the host +host_tick_rate 16065810 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 4833 # Number of instructions simulated -sim_seconds 0.000002 # Number of seconds simulated -sim_ticks 2447500 # Number of ticks simulated +sim_insts 5340 # Number of instructions simulated +sim_seconds 0.000003 # Number of seconds simulated +sim_ticks 2701000 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 4896 # number of cpu cycles simulated -system.cpu.num_insts 4833 # Number of instructions executed -system.cpu.num_refs 1282 # Number of memory references +system.cpu.numCycles 5403 # number of cpu cycles simulated +system.cpu.num_insts 5340 # Number of instructions executed +system.cpu.num_refs 1402 # Number of memory references system.cpu.workload.PROG:num_syscalls 11 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout index b07b710c8..c0e107ab6 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout +++ b/tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 21 2008 20:33:06 -M5 started Mon Jul 21 20:33:18 2008 -M5 executing on zizzer -M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881 -M5 commit date Tue Jul 15 14:38:51 2008 -0400 +M5 compiled Jul 23 2008 16:00:51 +M5 started Wed Jul 23 16:00:55 2008 +M5 executing on blue +M5 revision 5515:47bf96eec2c6221cf91de8a078897c1b5e46cfbf +M5 commit date Wed Jul 23 15:35:08 2008 -0700 command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-atomic tests/run.py quick/00.hello/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second -Hello World!Exiting @ tick 2447500 because target called exit() +Hello World!Exiting @ tick 2701000 because target called exit() diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini b/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini index 092061e7f..834e9fbf3 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini +++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini @@ -166,6 +166,7 @@ cmd=hello cwd= egid=100 env= +errout=cerr euid=100 executable=/dist/m5/regression/test-progs/hello/bin/sparc/linux/hello gid=100 diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/m5stats.txt b/tests/quick/00.hello/ref/sparc/linux/simple-timing/m5stats.txt index 08e810a08..132891c92 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/m5stats.txt +++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/m5stats.txt @@ -1,66 +1,66 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 153074 # Simulator instruction rate (inst/s) -host_mem_usage 195092 # Number of bytes of host memory used -host_seconds 0.03 # Real time elapsed on the host -host_tick_rate 524572616 # Simulator tick rate (ticks/s) +host_inst_rate 56962 # Simulator instruction rate (inst/s) +host_mem_usage 210220 # Number of bytes of host memory used +host_seconds 0.09 # Real time elapsed on the host +host_tick_rate 184294275 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 4833 # Number of instructions simulated +sim_insts 5340 # Number of instructions simulated sim_seconds 0.000017 # Number of seconds simulated -sim_ticks 16662000 # Number of ticks simulated -system.cpu.dcache.ReadReq_accesses 608 # number of ReadReq accesses(hits+misses) +sim_ticks 17315000 # Number of ticks simulated +system.cpu.dcache.ReadReq_accesses 716 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 26759.259259 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 23759.259259 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 554 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits 662 # number of ReadReq hits system.cpu.dcache.ReadReq_miss_latency 1445000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.088816 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate 0.075419 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 54 # number of ReadReq misses system.cpu.dcache.ReadReq_mshr_miss_latency 1283000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.088816 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate 0.075419 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 54 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 661 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses 673 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_avg_miss_latency 27000 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency 24000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 565 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits 577 # number of WriteReq hits system.cpu.dcache.WriteReq_miss_latency 2592000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.145234 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate 0.142645 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 96 # number of WriteReq misses system.cpu.dcache.WriteReq_mshr_miss_latency 2304000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.145234 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate 0.142645 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 96 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 8.400000 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 9.288889 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 1269 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses 1389 # number of demand (read+write) accesses system.cpu.dcache.demand_avg_miss_latency 26913.333333 # average overall miss latency system.cpu.dcache.demand_avg_mshr_miss_latency 23913.333333 # average overall mshr miss latency -system.cpu.dcache.demand_hits 1119 # number of demand (read+write) hits +system.cpu.dcache.demand_hits 1239 # number of demand (read+write) hits system.cpu.dcache.demand_miss_latency 4037000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.118203 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate 0.107991 # miss rate for demand accesses system.cpu.dcache.demand_misses 150 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_miss_latency 3587000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.118203 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate 0.107991 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 150 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 1269 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses 1389 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 26913.333333 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 23913.333333 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 1119 # number of overall hits +system.cpu.dcache.overall_hits 1239 # number of overall hits system.cpu.dcache.overall_miss_latency 4037000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.118203 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate 0.107991 # miss rate for overall accesses system.cpu.dcache.overall_misses 150 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.dcache.overall_mshr_miss_latency 3587000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.118203 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate 0.107991 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 150 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses @@ -76,54 +76,54 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 135 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 81.706581 # Cycle average of tags in use -system.cpu.dcache.total_refs 1134 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 83.359749 # Cycle average of tags in use +system.cpu.dcache.total_refs 1254 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_accesses 4877 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 26898.437500 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 23898.437500 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 4621 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 6886000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.052491 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 256 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 6118000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.052491 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 256 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_accesses 5384 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 26898.832685 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 23898.832685 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 5127 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 6913000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.047734 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 257 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency 6142000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.047734 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 257 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 18.050781 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 19.949416 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 4877 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 26898.437500 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 23898.437500 # average overall mshr miss latency -system.cpu.icache.demand_hits 4621 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 6886000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.052491 # miss rate for demand accesses -system.cpu.icache.demand_misses 256 # number of demand (read+write) misses +system.cpu.icache.demand_accesses 5384 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 26898.832685 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 23898.832685 # average overall mshr miss latency +system.cpu.icache.demand_hits 5127 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 6913000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.047734 # miss rate for demand accesses +system.cpu.icache.demand_misses 257 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 6118000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.052491 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 256 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_miss_latency 6142000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.047734 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 257 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 4877 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 26898.437500 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 23898.437500 # average overall mshr miss latency +system.cpu.icache.overall_accesses 5384 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 26898.832685 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 23898.832685 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 4621 # number of overall hits -system.cpu.icache.overall_miss_latency 6886000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.052491 # miss rate for overall accesses -system.cpu.icache.overall_misses 256 # number of overall misses +system.cpu.icache.overall_hits 5127 # number of overall hits +system.cpu.icache.overall_miss_latency 6913000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.047734 # miss rate for overall accesses +system.cpu.icache.overall_misses 257 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 6118000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.052491 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 256 # number of overall MSHR misses +system.cpu.icache.overall_mshr_miss_latency 6142000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.047734 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 257 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -136,10 +136,10 @@ system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.sampled_refs 256 # Sample count of references to valid blocks. +system.cpu.icache.sampled_refs 257 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 115.043041 # Cycle average of tags in use -system.cpu.icache.total_refs 4621 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 118.738905 # Cycle average of tags in use +system.cpu.icache.total_refs 5127 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles @@ -152,16 +152,16 @@ system.cpu.l2cache.ReadExReq_misses 81 # nu system.cpu.l2cache.ReadExReq_mshr_miss_latency 891000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 81 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 310 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses 311 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_avg_miss_latency 23000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 3 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 7061000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.990323 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 307 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 3377000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.990323 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 307 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_miss_latency 7084000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.990354 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 308 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 3388000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.990354 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 308 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 15 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_avg_miss_latency 23000 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency @@ -173,38 +173,38 @@ system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 system.cpu.l2cache.UpgradeReq_mshr_misses 15 # number of UpgradeReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.010274 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.010239 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 391 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses 392 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 23000 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.demand_hits 3 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 8924000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.992327 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 388 # number of demand (read+write) misses +system.cpu.l2cache.demand_miss_latency 8947000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.992347 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 389 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 4268000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.992327 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 388 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 4279000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.992347 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 389 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 391 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses 392 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 23000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 3 # number of overall hits -system.cpu.l2cache.overall_miss_latency 8924000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.992327 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 388 # number of overall misses +system.cpu.l2cache.overall_miss_latency 8947000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.992347 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 389 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 4268000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.992327 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 388 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 4279000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.992347 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 389 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -217,16 +217,16 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 292 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 293 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 133.841445 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 138.022706 # Cycle average of tags in use system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 33324 # number of cpu cycles simulated -system.cpu.num_insts 4833 # Number of instructions executed -system.cpu.num_refs 1282 # Number of memory references +system.cpu.numCycles 34630 # number of cpu cycles simulated +system.cpu.num_insts 5340 # Number of instructions executed +system.cpu.num_refs 1402 # Number of memory references system.cpu.workload.PROG:num_syscalls 11 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/sparc/linux/simple-timing/stdout b/tests/quick/00.hello/ref/sparc/linux/simple-timing/stdout index 4d51e2838..9fab97574 100644 --- a/tests/quick/00.hello/ref/sparc/linux/simple-timing/stdout +++ b/tests/quick/00.hello/ref/sparc/linux/simple-timing/stdout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 21 2008 20:33:06 -M5 started Mon Jul 21 20:33:08 2008 -M5 executing on zizzer -M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881 -M5 commit date Tue Jul 15 14:38:51 2008 -0400 +M5 compiled Jul 23 2008 16:00:51 +M5 started Wed Jul 23 16:00:56 2008 +M5 executing on blue +M5 revision 5515:47bf96eec2c6221cf91de8a078897c1b5e46cfbf +M5 commit date Wed Jul 23 15:35:08 2008 -0700 command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-timing tests/run.py quick/00.hello/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second -Hello World!Exiting @ tick 16662000 because target called exit() +Hello World!Exiting @ tick 17315000 because target called exit() diff --git a/tests/quick/00.hello/ref/x86/linux/simple-atomic/config.ini b/tests/quick/00.hello/ref/x86/linux/simple-atomic/config.ini index 569d4b220..40d1ca238 100644 --- a/tests/quick/00.hello/ref/x86/linux/simple-atomic/config.ini +++ b/tests/quick/00.hello/ref/x86/linux/simple-atomic/config.ini @@ -51,6 +51,7 @@ cmd=hello cwd= egid=100 env= +errout=cerr euid=100 executable=/dist/m5/regression/test-progs/hello/bin/x86/linux/hello gid=100 diff --git a/tests/quick/00.hello/ref/x86/linux/simple-atomic/m5stats.txt b/tests/quick/00.hello/ref/x86/linux/simple-atomic/m5stats.txt index 5fd208e3f..ef5ccc7e6 100644 --- a/tests/quick/00.hello/ref/x86/linux/simple-atomic/m5stats.txt +++ b/tests/quick/00.hello/ref/x86/linux/simple-atomic/m5stats.txt @@ -1,18 +1,18 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 13744 # Simulator instruction rate (inst/s) -host_mem_usage 186320 # Number of bytes of host memory used -host_seconds 0.62 # Real time elapsed on the host -host_tick_rate 7996070 # Simulator tick rate (ticks/s) +host_inst_rate 69477 # Simulator instruction rate (inst/s) +host_mem_usage 201612 # Number of bytes of host memory used +host_seconds 0.14 # Real time elapsed on the host +host_tick_rate 40336760 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 8475 # Number of instructions simulated -sim_seconds 0.000005 # Number of seconds simulated -sim_ticks 4932000 # Number of ticks simulated +sim_insts 9511 # Number of instructions simulated +sim_seconds 0.000006 # Number of seconds simulated +sim_ticks 5529000 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 9865 # number of cpu cycles simulated -system.cpu.num_insts 8475 # Number of instructions executed -system.cpu.num_refs 1765 # Number of memory references +system.cpu.numCycles 11059 # number of cpu cycles simulated +system.cpu.num_insts 9511 # Number of instructions executed +system.cpu.num_refs 2003 # Number of memory references system.cpu.workload.PROG:num_syscalls 11 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/x86/linux/simple-atomic/stdout b/tests/quick/00.hello/ref/x86/linux/simple-atomic/stdout index 99e187690..ada9a56fb 100644 --- a/tests/quick/00.hello/ref/x86/linux/simple-atomic/stdout +++ b/tests/quick/00.hello/ref/x86/linux/simple-atomic/stdout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 21 2008 20:45:28 -M5 started Mon Jul 21 20:50:18 2008 -M5 executing on zizzer -M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881 -M5 commit date Tue Jul 15 14:38:51 2008 -0400 +M5 compiled Jul 23 2008 16:08:41 +M5 started Wed Jul 23 16:14:28 2008 +M5 executing on blue +M5 revision 5515:47bf96eec2c6221cf91de8a078897c1b5e46cfbf +M5 commit date Wed Jul 23 15:35:08 2008 -0700 command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-atomic tests/run.py quick/00.hello/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second Hello world! -Exiting @ tick 4932000 because target called exit() +Exiting @ tick 5529000 because target called exit() diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini index ca040dc25..fc5cea346 100644 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini @@ -368,6 +368,7 @@ cmd=hello cwd= egid=100 env= +errout=cerr euid=100 executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello gid=100 @@ -386,6 +387,7 @@ cmd=hello cwd= egid=100 env= +errout=cerr euid=100 executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello gid=100 diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt index 4a5d707e1..28f9f7577 100644 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt @@ -1,193 +1,193 @@ ---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 722 # Number of BTB hits -global.BPredUnit.BTBLookups 3569 # Number of BTB lookups -global.BPredUnit.RASInCorrect 133 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 1125 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 2392 # Number of conditional branches predicted -global.BPredUnit.lookups 4127 # Number of BP lookups -global.BPredUnit.usedRAS 550 # Number of times the RAS was used to get a target. -host_inst_rate 41846 # Simulator instruction rate (inst/s) -host_mem_usage 152588 # Number of bytes of host memory used -host_seconds 0.27 # Real time elapsed on the host -host_tick_rate 23650670 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 18 # Number of conflicting loads. -memdepunit.memDep.conflictingLoads 17 # Number of conflicting loads. -memdepunit.memDep.conflictingStores 33 # Number of conflicting stores. -memdepunit.memDep.conflictingStores 36 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 1975 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedLoads 2036 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 1163 # Number of stores inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 1158 # Number of stores inserted to the mem dependence unit. +global.BPredUnit.BTBHits 817 # Number of BTB hits +global.BPredUnit.BTBLookups 4239 # Number of BTB lookups +global.BPredUnit.RASInCorrect 150 # Number of incorrect RAS predictions. +global.BPredUnit.condIncorrect 1415 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 2870 # Number of conditional branches predicted +global.BPredUnit.lookups 4960 # Number of BP lookups +global.BPredUnit.usedRAS 590 # Number of times the RAS was used to get a target. +host_inst_rate 59476 # Simulator instruction rate (inst/s) +host_mem_usage 210328 # Number of bytes of host memory used +host_seconds 0.21 # Real time elapsed on the host +host_tick_rate 33433367 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 22 # Number of conflicting loads. +memdepunit.memDep.conflictingLoads 46 # Number of conflicting loads. +memdepunit.memDep.conflictingStores 29 # Number of conflicting stores. +memdepunit.memDep.conflictingStores 54 # Number of conflicting stores. +memdepunit.memDep.insertedLoads 2257 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedLoads 2354 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 1267 # Number of stores inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 1298 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 11247 # Number of instructions simulated -sim_seconds 0.000006 # Number of seconds simulated -sim_ticks 6363000 # Number of ticks simulated -system.cpu.commit.COM:branches 1724 # Number of branches committed -system.cpu.commit.COM:branches_0 862 # Number of branches committed -system.cpu.commit.COM:branches_1 862 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 145 # number cycles where commit BW limit reached +sim_insts 12595 # Number of instructions simulated +sim_seconds 0.000007 # Number of seconds simulated +sim_ticks 7085500 # Number of ticks simulated +system.cpu.commit.COM:branches 2024 # Number of branches committed +system.cpu.commit.COM:branches_0 1012 # Number of branches committed +system.cpu.commit.COM:branches_1 1012 # Number of branches committed +system.cpu.commit.COM:bw_lim_events 152 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:bw_limited_0 0 # number of insts not committed due to BW limits system.cpu.commit.COM:bw_limited_1 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 12623 +system.cpu.commit.COM:committed_per_cycle.samples 14074 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 7897 6256.04% - 1 2220 1758.69% - 2 993 786.66% - 3 507 401.65% - 4 332 263.01% - 5 219 173.49% - 6 199 157.65% - 7 111 87.93% - 8 145 114.87% + 0 8763 6226.37% + 1 2528 1796.22% + 2 1133 805.03% + 3 504 358.11% + 4 369 262.19% + 5 263 186.87% + 6 218 154.90% + 7 144 102.32% + 8 152 108.00% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist -system.cpu.commit.COM:count 11281 # Number of instructions committed -system.cpu.commit.COM:count_0 5640 # Number of instructions committed -system.cpu.commit.COM:count_1 5641 # Number of instructions committed -system.cpu.commit.COM:loads 1958 # Number of loads committed -system.cpu.commit.COM:loads_0 979 # Number of loads committed -system.cpu.commit.COM:loads_1 979 # Number of loads committed +system.cpu.commit.COM:count 12629 # Number of instructions committed +system.cpu.commit.COM:count_0 6314 # Number of instructions committed +system.cpu.commit.COM:count_1 6315 # Number of instructions committed +system.cpu.commit.COM:loads 2336 # Number of loads committed +system.cpu.commit.COM:loads_0 1168 # Number of loads committed +system.cpu.commit.COM:loads_1 1168 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:membars_0 0 # Number of memory barriers committed system.cpu.commit.COM:membars_1 0 # Number of memory barriers committed -system.cpu.commit.COM:refs 3582 # Number of memory references committed -system.cpu.commit.COM:refs_0 1791 # Number of memory references committed -system.cpu.commit.COM:refs_1 1791 # Number of memory references committed +system.cpu.commit.COM:refs 4060 # Number of memory references committed +system.cpu.commit.COM:refs_0 2030 # Number of memory references committed +system.cpu.commit.COM:refs_1 2030 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed system.cpu.commit.COM:swp_count_0 0 # Number of s/w prefetches committed system.cpu.commit.COM:swp_count_1 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 885 # The number of times a branch was mispredicted -system.cpu.commit.commitCommittedInsts 11281 # The number of committed instructions +system.cpu.commit.branchMispredicts 1036 # The number of times a branch was mispredicted +system.cpu.commit.commitCommittedInsts 12629 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 34 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 8502 # The number of squashed insts skipped by commit -system.cpu.committedInsts_0 5623 # Number of Instructions Simulated -system.cpu.committedInsts_1 5624 # Number of Instructions Simulated -system.cpu.committedInsts_total 11247 # Number of Instructions Simulated -system.cpu.cpi_0 2.263383 # CPI: Cycles Per Instruction -system.cpu.cpi_1 2.262980 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.131591 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 3079 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses_0 3079 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency_0 12116.724739 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency_0 10527.918782 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 2792 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits_0 2792 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 3477500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency_0 3477500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate_0 0.093212 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 287 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses_0 287 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 90 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits_0 90 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 2074000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency_0 2074000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate_0 0.063982 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 197 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses_0 197 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 1624 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses_0 1624 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency_0 9139.837398 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency_0 8686.781609 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 1009 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits_0 1009 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 5621000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency_0 5621000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate_0 0.378695 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 615 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses_0 615 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 441 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits_0 441 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 1511500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency_0 1511500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate_0 0.107143 # mshr miss rate for WriteReq accesses +system.cpu.commit.commitSquashedInsts 9674 # The number of squashed insts skipped by commit +system.cpu.committedInsts_0 6297 # Number of Instructions Simulated +system.cpu.committedInsts_1 6298 # Number of Instructions Simulated +system.cpu.committedInsts_total 12595 # Number of Instructions Simulated +system.cpu.cpi_0 2.250596 # CPI: Cycles Per Instruction +system.cpu.cpi_1 2.250238 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.125208 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 3671 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses_0 3671 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency_0 12250.889680 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency_0 10641.025641 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 3390 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits_0 3390 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 3442500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency_0 3442500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate_0 0.076546 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 281 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses_0 281 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 86 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits_0 86 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 2075000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency_0 2075000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate_0 0.053119 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 195 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses_0 195 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 1724 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses_0 1724 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency_0 9093.800979 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency_0 8701.149425 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 1111 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits_0 1111 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 5574500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency_0 5574500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate_0 0.355568 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 613 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses_0 613 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 439 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits_0 439 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 1514000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency_0 1514000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate_0 0.100928 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 174 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses_0 174 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 11.266082 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 13.379412 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 4703 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses_0 4703 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses 5395 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses_0 5395 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses_1 0 # number of demand (read+write) accesses system.cpu.dcache.demand_avg_miss_latency <err: div-0> # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency_0 10087.028825 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency_0 10086.129754 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency_1 <err: div-0> # average overall miss latency system.cpu.dcache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency_0 9664.420485 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency_0 9726.287263 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency -system.cpu.dcache.demand_hits 3801 # number of demand (read+write) hits -system.cpu.dcache.demand_hits_0 3801 # number of demand (read+write) hits +system.cpu.dcache.demand_hits 4501 # number of demand (read+write) hits +system.cpu.dcache.demand_hits_0 4501 # number of demand (read+write) hits system.cpu.dcache.demand_hits_1 0 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 9098500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency_0 9098500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 9017000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency_0 9017000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency_1 0 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate <err: div-0> # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate_0 0.191792 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate_0 0.165709 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate_1 <err: div-0> # miss rate for demand accesses -system.cpu.dcache.demand_misses 902 # number of demand (read+write) misses -system.cpu.dcache.demand_misses_0 902 # number of demand (read+write) misses +system.cpu.dcache.demand_misses 894 # number of demand (read+write) misses +system.cpu.dcache.demand_misses_0 894 # number of demand (read+write) misses system.cpu.dcache.demand_misses_1 0 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 531 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits_0 531 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits 525 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits_0 525 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits_1 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 3585500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency_0 3585500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 3589000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency_0 3589000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency_1 0 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate <err: div-0> # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate_0 0.078886 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate_0 0.068397 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate_1 <err: div-0> # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 371 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses_0 371 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses 369 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses_0 369 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses_1 0 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.mshr_cap_events_0 0 # number of times MSHR cap was activated system.cpu.dcache.mshr_cap_events_1 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 4703 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses_0 4703 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses 5395 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses_0 5395 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses_1 0 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency <err: div-0> # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency_0 10087.028825 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency_0 10086.129754 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency_1 <err: div-0> # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency_0 9664.420485 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency_0 9726.287263 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency_0 <err: div-0> # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency_1 <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 3801 # number of overall hits -system.cpu.dcache.overall_hits_0 3801 # number of overall hits +system.cpu.dcache.overall_hits 4501 # number of overall hits +system.cpu.dcache.overall_hits_0 4501 # number of overall hits system.cpu.dcache.overall_hits_1 0 # number of overall hits -system.cpu.dcache.overall_miss_latency 9098500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency_0 9098500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 9017000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency_0 9017000 # number of overall miss cycles system.cpu.dcache.overall_miss_latency_1 0 # number of overall miss cycles system.cpu.dcache.overall_miss_rate <err: div-0> # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate_0 0.191792 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate_0 0.165709 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate_1 <err: div-0> # miss rate for overall accesses -system.cpu.dcache.overall_misses 902 # number of overall misses -system.cpu.dcache.overall_misses_0 902 # number of overall misses +system.cpu.dcache.overall_misses 894 # number of overall misses +system.cpu.dcache.overall_misses_0 894 # number of overall misses system.cpu.dcache.overall_misses_1 0 # number of overall misses -system.cpu.dcache.overall_mshr_hits 531 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits_0 531 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits 525 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits_0 525 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits_1 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 3585500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency_0 3585500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 3589000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency_0 3589000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency_1 0 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate <err: div-0> # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate_0 0.078886 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate_0 0.068397 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate_1 <err: div-0> # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 371 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses_0 371 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses 369 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses_0 369 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses_1 0 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_latency_0 0 # number of overall MSHR uncacheable cycles @@ -207,161 +207,161 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.replacements_0 0 # number of replacements system.cpu.dcache.replacements_1 0 # number of replacements -system.cpu.dcache.sampled_refs 342 # Sample count of references to valid blocks. +system.cpu.dcache.sampled_refs 340 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.soft_prefetch_mshr_full_0 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.soft_prefetch_mshr_full_1 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 214.045910 # Cycle average of tags in use -system.cpu.dcache.total_refs 3853 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 223.357154 # Cycle average of tags in use +system.cpu.dcache.total_refs 4549 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks system.cpu.dcache.writebacks_0 0 # number of writebacks system.cpu.dcache.writebacks_1 0 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 2156 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 253 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 362 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 22792 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 17306 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 3860 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 1667 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 387 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:BlockedCycles 2189 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 393 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 537 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 25750 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 19285 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 4519 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 1860 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 557 # Number of squashed instructions handled by decode system.cpu.decode.DECODE:UnblockCycles 183 # Number of cycles decode is unblocking -system.cpu.dtb.accesses 5201 # DTB accesses +system.cpu.dtb.accesses 5942 # DTB accesses system.cpu.dtb.acv 0 # DTB access violations -system.cpu.dtb.hits 5076 # DTB hits +system.cpu.dtb.hits 5817 # DTB hits system.cpu.dtb.misses 125 # DTB misses -system.cpu.dtb.read_accesses 3261 # DTB read accesses +system.cpu.dtb.read_accesses 3857 # DTB read accesses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_hits 3178 # DTB read hits -system.cpu.dtb.read_misses 83 # DTB read misses -system.cpu.dtb.write_accesses 1940 # DTB write accesses +system.cpu.dtb.read_hits 3775 # DTB read hits +system.cpu.dtb.read_misses 82 # DTB read misses +system.cpu.dtb.write_accesses 2085 # DTB write accesses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 1898 # DTB write hits -system.cpu.dtb.write_misses 42 # DTB write misses -system.cpu.fetch.Branches 4127 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 3105 # Number of cache lines fetched -system.cpu.fetch.Cycles 7305 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 481 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 25026 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 1246 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.324271 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 3105 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 1272 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.966371 # Number of inst fetches per cycle +system.cpu.dtb.write_hits 2042 # DTB write hits +system.cpu.dtb.write_misses 43 # DTB write misses +system.cpu.fetch.Branches 4960 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 3670 # Number of cache lines fetched +system.cpu.fetch.Cycles 8581 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 538 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 28943 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 1537 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.349986 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 3670 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 1407 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 2.042266 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 12676 +system.cpu.fetch.rateDist.samples 14126 system.cpu.fetch.rateDist.min_value 0 - 0 8531 6730.04% - 1 309 243.77% - 2 245 193.28% - 3 260 205.11% - 4 342 269.80% - 5 308 242.98% - 6 324 255.60% - 7 261 205.90% - 8 2096 1653.52% + 0 9265 6558.83% + 1 397 281.04% + 2 297 210.25% + 3 373 264.05% + 4 393 278.21% + 5 288 203.88% + 6 408 288.83% + 7 267 189.01% + 8 2438 1725.90% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 3105 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses_0 3105 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency_0 10171.875000 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency_0 7742.694805 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 2401 # number of ReadReq hits -system.cpu.icache.ReadReq_hits_0 2401 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 7161000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency_0 7161000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate_0 0.226731 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_accesses 3670 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses_0 3670 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency_0 10197.443182 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency_0 7726.171244 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 2966 # number of ReadReq hits +system.cpu.icache.ReadReq_hits_0 2966 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 7179000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency_0 7179000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate_0 0.191826 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 704 # number of ReadReq misses system.cpu.icache.ReadReq_misses_0 704 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 88 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits_0 88 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 4769500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency_0 4769500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate_0 0.198390 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 616 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses_0 616 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_hits 85 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits_0 85 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 4782500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency_0 4782500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate_0 0.168665 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 619 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses_0 619 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 3.897727 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 4.791599 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 3105 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses_0 3105 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses 3670 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses_0 3670 # number of demand (read+write) accesses system.cpu.icache.demand_accesses_1 0 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency <err: div-0> # average overall miss latency -system.cpu.icache.demand_avg_miss_latency_0 10171.875000 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency_0 10197.443182 # average overall miss latency system.cpu.icache.demand_avg_miss_latency_1 <err: div-0> # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency_0 7742.694805 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency_0 7726.171244 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency -system.cpu.icache.demand_hits 2401 # number of demand (read+write) hits -system.cpu.icache.demand_hits_0 2401 # number of demand (read+write) hits +system.cpu.icache.demand_hits 2966 # number of demand (read+write) hits +system.cpu.icache.demand_hits_0 2966 # number of demand (read+write) hits system.cpu.icache.demand_hits_1 0 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 7161000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency_0 7161000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 7179000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency_0 7179000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency_1 0 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate <err: div-0> # miss rate for demand accesses -system.cpu.icache.demand_miss_rate_0 0.226731 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate_0 0.191826 # miss rate for demand accesses system.cpu.icache.demand_miss_rate_1 <err: div-0> # miss rate for demand accesses system.cpu.icache.demand_misses 704 # number of demand (read+write) misses system.cpu.icache.demand_misses_0 704 # number of demand (read+write) misses system.cpu.icache.demand_misses_1 0 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 88 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits_0 88 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits 85 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits_0 85 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_hits_1 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 4769500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency_0 4769500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 4782500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency_0 4782500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency_1 0 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate <err: div-0> # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate_0 0.198390 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate_0 0.168665 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate_1 <err: div-0> # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 616 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses_0 616 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses 619 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses_0 619 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses_1 0 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.mshr_cap_events_0 0 # number of times MSHR cap was activated system.cpu.icache.mshr_cap_events_1 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 3105 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses_0 3105 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses 3670 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses_0 3670 # number of overall (read+write) accesses system.cpu.icache.overall_accesses_1 0 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency <err: div-0> # average overall miss latency -system.cpu.icache.overall_avg_miss_latency_0 10171.875000 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency_0 10197.443182 # average overall miss latency system.cpu.icache.overall_avg_miss_latency_1 <err: div-0> # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency_0 7742.694805 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency_0 7726.171244 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency_0 <err: div-0> # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency_1 <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 2401 # number of overall hits -system.cpu.icache.overall_hits_0 2401 # number of overall hits +system.cpu.icache.overall_hits 2966 # number of overall hits +system.cpu.icache.overall_hits_0 2966 # number of overall hits system.cpu.icache.overall_hits_1 0 # number of overall hits -system.cpu.icache.overall_miss_latency 7161000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency_0 7161000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 7179000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency_0 7179000 # number of overall miss cycles system.cpu.icache.overall_miss_latency_1 0 # number of overall miss cycles system.cpu.icache.overall_miss_rate <err: div-0> # miss rate for overall accesses -system.cpu.icache.overall_miss_rate_0 0.226731 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate_0 0.191826 # miss rate for overall accesses system.cpu.icache.overall_miss_rate_1 <err: div-0> # miss rate for overall accesses system.cpu.icache.overall_misses 704 # number of overall misses system.cpu.icache.overall_misses_0 704 # number of overall misses system.cpu.icache.overall_misses_1 0 # number of overall misses -system.cpu.icache.overall_mshr_hits 88 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits_0 88 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits 85 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits_0 85 # number of overall MSHR hits system.cpu.icache.overall_mshr_hits_1 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 4769500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency_0 4769500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 4782500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency_0 4782500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency_1 0 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate <err: div-0> # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate_0 0.198390 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate_0 0.168665 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate_1 <err: div-0> # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 616 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses_0 616 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses 619 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses_0 619 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses_1 0 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency_0 0 # number of overall MSHR uncacheable cycles @@ -378,107 +378,107 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0 system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 6 # number of replacements -system.cpu.icache.replacements_0 6 # number of replacements +system.cpu.icache.replacements 7 # number of replacements +system.cpu.icache.replacements_0 7 # number of replacements system.cpu.icache.replacements_1 0 # number of replacements -system.cpu.icache.sampled_refs 616 # Sample count of references to valid blocks. +system.cpu.icache.sampled_refs 619 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.soft_prefetch_mshr_full_0 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.soft_prefetch_mshr_full_1 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 313.697202 # Cycle average of tags in use -system.cpu.icache.total_refs 2401 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 335.078862 # Cycle average of tags in use +system.cpu.icache.total_refs 2966 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.icache.writebacks_0 0 # number of writebacks system.cpu.icache.writebacks_1 0 # number of writebacks -system.cpu.idleCycles 51 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 2444 # Number of branches executed -system.cpu.iew.EXEC:branches_0 1228 # Number of branches executed -system.cpu.iew.EXEC:branches_1 1216 # Number of branches executed -system.cpu.iew.EXEC:nop 128 # number of nop insts executed -system.cpu.iew.EXEC:nop_0 67 # number of nop insts executed -system.cpu.iew.EXEC:nop_1 61 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.267070 # Inst execution rate -system.cpu.iew.EXEC:refs 5219 # number of memory reference insts executed -system.cpu.iew.EXEC:refs_0 2580 # number of memory reference insts executed -system.cpu.iew.EXEC:refs_1 2639 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 1956 # Number of stores executed -system.cpu.iew.EXEC:stores_0 977 # Number of stores executed -system.cpu.iew.EXEC:stores_1 979 # Number of stores executed +system.cpu.idleCycles 46 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 2896 # Number of branches executed +system.cpu.iew.EXEC:branches_0 1452 # Number of branches executed +system.cpu.iew.EXEC:branches_1 1444 # Number of branches executed +system.cpu.iew.EXEC:nop 125 # number of nop insts executed +system.cpu.iew.EXEC:nop_0 66 # number of nop insts executed +system.cpu.iew.EXEC:nop_1 59 # number of nop insts executed +system.cpu.iew.EXEC:rate 1.282811 # Inst execution rate +system.cpu.iew.EXEC:refs 5961 # number of memory reference insts executed +system.cpu.iew.EXEC:refs_0 2937 # number of memory reference insts executed +system.cpu.iew.EXEC:refs_1 3024 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 2102 # Number of stores executed +system.cpu.iew.EXEC:stores_0 1047 # Number of stores executed +system.cpu.iew.EXEC:stores_1 1055 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed system.cpu.iew.EXEC:swp_0 0 # number of swp insts executed system.cpu.iew.EXEC:swp_1 0 # number of swp insts executed -system.cpu.iew.WB:consumers 10432 # num instructions consuming a value -system.cpu.iew.WB:consumers_0 5228 # num instructions consuming a value -system.cpu.iew.WB:consumers_1 5204 # num instructions consuming a value -system.cpu.iew.WB:count 15495 # cumulative count of insts written-back -system.cpu.iew.WB:count_0 7763 # cumulative count of insts written-back -system.cpu.iew.WB:count_1 7732 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 1.540838 # average fanout of values written-back -system.cpu.iew.WB:fanout_0 0.769893 # average fanout of values written-back -system.cpu.iew.WB:fanout_1 0.770945 # average fanout of values written-back +system.cpu.iew.WB:consumers 11655 # num instructions consuming a value +system.cpu.iew.WB:consumers_0 5835 # num instructions consuming a value +system.cpu.iew.WB:consumers_1 5820 # num instructions consuming a value +system.cpu.iew.WB:count 17454 # cumulative count of insts written-back +system.cpu.iew.WB:count_0 8729 # cumulative count of insts written-back +system.cpu.iew.WB:count_1 8725 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 1.541828 # average fanout of values written-back +system.cpu.iew.WB:fanout_0 0.770865 # average fanout of values written-back +system.cpu.iew.WB:fanout_1 0.770962 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_0 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_1 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.WB:penalized_rate_0 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.WB:penalized_rate_1 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 8037 # num instructions producing a value -system.cpu.iew.WB:producers_0 4025 # num instructions producing a value -system.cpu.iew.WB:producers_1 4012 # num instructions producing a value -system.cpu.iew.WB:rate 1.217490 # insts written-back per cycle -system.cpu.iew.WB:rate_0 0.609963 # insts written-back per cycle -system.cpu.iew.WB:rate_1 0.607527 # insts written-back per cycle -system.cpu.iew.WB:sent 15706 # cumulative count of insts sent to commit -system.cpu.iew.WB:sent_0 7855 # cumulative count of insts sent to commit -system.cpu.iew.WB:sent_1 7851 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 1023 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 34 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 4011 # Number of dispatched load instructions +system.cpu.iew.WB:producers 8985 # num instructions producing a value +system.cpu.iew.WB:producers_0 4498 # num instructions producing a value +system.cpu.iew.WB:producers_1 4487 # num instructions producing a value +system.cpu.iew.WB:rate 1.231583 # insts written-back per cycle +system.cpu.iew.WB:rate_0 0.615933 # insts written-back per cycle +system.cpu.iew.WB:rate_1 0.615651 # insts written-back per cycle +system.cpu.iew.WB:sent 17676 # cumulative count of insts sent to commit +system.cpu.iew.WB:sent_0 8819 # cumulative count of insts sent to commit +system.cpu.iew.WB:sent_1 8857 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 1177 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 39 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 4611 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 45 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 445 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 2321 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 19928 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 3263 # Number of load instructions executed -system.cpu.iew.iewExecLoadInsts_0 1603 # Number of load instructions executed -system.cpu.iew.iewExecLoadInsts_1 1660 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 892 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 16126 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 15 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewDispSquashedInsts 648 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 2565 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 22432 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 3859 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts_0 1890 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts_1 1969 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1127 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 18180 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 18 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 1667 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 15 # Number of cycles IEW is unblocking +system.cpu.iew.iewSquashCycles 1860 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 18 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 44 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.forwLoads 45 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread.0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 66 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.memOrderViolation 67 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 996 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 351 # Number of stores squashed +system.cpu.iew.lsq.thread.0.squashedLoads 1089 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 405 # Number of stores squashed system.cpu.iew.lsq.thread.1.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.1.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.1.forwLoads 53 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.1.ignoredResponses 9 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.1.forwLoads 57 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.1.ignoredResponses 8 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.1.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.1.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.1.memOrderViolation 67 # Number of memory ordering violations +system.cpu.iew.lsq.thread.1.memOrderViolation 70 # Number of memory ordering violations system.cpu.iew.lsq.thread.1.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.1.squashedLoads 1057 # Number of loads squashed -system.cpu.iew.lsq.thread.1.squashedStores 346 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 133 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 810 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 213 # Number of branches that were predicted taken incorrectly -system.cpu.ipc_0 0.441817 # IPC: Instructions Per Cycle -system.cpu.ipc_1 0.441895 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.883712 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 8497 # Type of FU issued +system.cpu.iew.lsq.thread.1.squashedLoads 1186 # Number of loads squashed +system.cpu.iew.lsq.thread.1.squashedStores 436 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 137 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 950 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 227 # Number of branches that were predicted taken incorrectly +system.cpu.ipc_0 0.444327 # IPC: Instructions Per Cycle +system.cpu.ipc_1 0.444397 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.888724 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 9630 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist No_OpClass 2 0.02% # Type of FU issued - IntAlu 5747 67.64% # Type of FU issued + IntAlu 6491 67.40% # Type of FU issued IntMult 1 0.01% # Type of FU issued IntDiv 0 0.00% # Type of FU issued FloatAdd 2 0.02% # Type of FU issued @@ -487,15 +487,15 @@ system.cpu.iq.ISSUE:FU_type_0.start_dist FloatMult 0 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 1738 20.45% # Type of FU issued - MemWrite 1007 11.85% # Type of FU issued + MemRead 2024 21.02% # Type of FU issued + MemWrite 1110 11.53% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:FU_type_1 8521 # Type of FU issued +system.cpu.iq.ISSUE:FU_type_1 9677 # Type of FU issued system.cpu.iq.ISSUE:FU_type_1.start_dist No_OpClass 2 0.02% # Type of FU issued - IntAlu 5702 66.92% # Type of FU issued + IntAlu 6446 66.61% # Type of FU issued IntMult 1 0.01% # Type of FU issued IntDiv 0 0.00% # Type of FU issued FloatAdd 2 0.02% # Type of FU issued @@ -504,15 +504,15 @@ system.cpu.iq.ISSUE:FU_type_1.start_dist FloatMult 0 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 1797 21.09% # Type of FU issued - MemWrite 1017 11.94% # Type of FU issued + MemRead 2105 21.75% # Type of FU issued + MemWrite 1121 11.58% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_1.end_dist -system.cpu.iq.ISSUE:FU_type 17018 # Type of FU issued +system.cpu.iq.ISSUE:FU_type 19307 # Type of FU issued system.cpu.iq.ISSUE:FU_type.start_dist No_OpClass 4 0.02% # Type of FU issued - IntAlu 11449 67.28% # Type of FU issued + IntAlu 12937 67.01% # Type of FU issued IntMult 2 0.01% # Type of FU issued IntDiv 0 0.00% # Type of FU issued FloatAdd 4 0.02% # Type of FU issued @@ -521,20 +521,20 @@ system.cpu.iq.ISSUE:FU_type.start_dist FloatMult 0 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 3535 20.77% # Type of FU issued - MemWrite 2024 11.89% # Type of FU issued + MemRead 4129 21.39% # Type of FU issued + MemWrite 2231 11.56% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 180 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_cnt_0 83 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_cnt_1 97 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.010577 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_busy_rate_0 0.004877 # FU busy rate (busy events/executed inst) -system.cpu.iq.ISSUE:fu_busy_rate_1 0.005700 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_cnt 191 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_cnt_0 88 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_cnt_1 103 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.009893 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_rate_0 0.004558 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_rate_1 0.005335 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist No_OpClass 0 0.00% # attempts to use FU when none available - IntAlu 9 5.00% # attempts to use FU when none available + IntAlu 10 5.24% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available FloatAdd 0 0.00% # attempts to use FU when none available @@ -543,107 +543,107 @@ system.cpu.iq.ISSUE:fu_full.start_dist FloatMult 0 0.00% # attempts to use FU when none available FloatDiv 0 0.00% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 107 59.44% # attempts to use FU when none available - MemWrite 64 35.56% # attempts to use FU when none available + MemRead 116 60.73% # attempts to use FU when none available + MemWrite 65 34.03% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 12676 +system.cpu.iq.ISSUE:issued_per_cycle.samples 14126 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 6060 4780.69% - 1 2068 1631.43% - 2 1684 1328.49% - 3 1173 925.37% - 4 835 658.73% - 5 514 405.49% - 6 255 201.17% - 7 73 57.59% - 8 14 11.04% + 0 6647 4705.51% + 1 2379 1684.13% + 2 1804 1277.08% + 3 1327 939.40% + 4 983 695.88% + 5 624 441.74% + 6 265 187.60% + 7 79 55.93% + 8 18 12.74% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 1.337157 # Inst issue rate -system.cpu.iq.iqInstsAdded 19755 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 17018 # Number of instructions issued +system.cpu.iq.ISSUE:rate 1.362334 # Inst issue rate +system.cpu.iq.iqInstsAdded 22262 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 19307 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 45 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 7576 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 42 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 8627 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 40 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 11 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 4636 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.itb.accesses 3160 # ITB accesses +system.cpu.iq.iqSquashedOperandsExamined 5151 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.itb.accesses 3720 # ITB accesses system.cpu.itb.acv 0 # ITB acv -system.cpu.itb.hits 3105 # ITB hits -system.cpu.itb.misses 55 # ITB misses +system.cpu.itb.hits 3670 # ITB hits +system.cpu.itb.misses 50 # ITB misses system.cpu.l2cache.ReadExReq_accesses 145 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses_0 145 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency_0 6844.827586 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency_0 3844.827586 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 992500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency_0 992500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_avg_miss_latency_0 6824.137931 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency_0 3824.137931 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 989500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency_0 989500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate_0 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 145 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses_0 145 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 557500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency_0 557500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 554500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency_0 554500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate_0 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 145 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses_0 145 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 813 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses_0 813 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency_0 6525.277435 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency_0 3525.277435 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits_0 2 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 5292000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency_0 5292000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate_0 0.997540 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_accesses 814 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses_0 814 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency_0 6515.413070 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency_0 3515.413070 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 3 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits_0 3 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 5284000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency_0 5284000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate_0 0.996314 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 811 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses_0 811 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 2859000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency_0 2859000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate_0 0.997540 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_latency 2851000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency_0 2851000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate_0 0.996314 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 811 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses_0 811 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 29 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses_0 29 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency_0 6103.448276 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency_0 3103.448276 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 177000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency_0 177000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_avg_miss_latency_0 6344.827586 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency_0 3344.827586 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 184000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency_0 184000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate_0 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_misses 29 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses_0 29 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 90000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency_0 90000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 97000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency_0 97000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate_0 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_misses 29 # number of UpgradeReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses_0 29 # number of UpgradeReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.002558 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.003836 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 958 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses_0 958 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses 959 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses_0 959 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses_1 0 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency <err: div-0> # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency_0 6573.744770 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency_0 6562.238494 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency_1 <err: div-0> # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency_0 3573.744770 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency_0 3562.238494 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency -system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits_0 2 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits 3 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits_0 3 # number of demand (read+write) hits system.cpu.l2cache.demand_hits_1 0 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 6284500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency_0 6284500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 6273500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency_0 6273500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency_1 0 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate <err: div-0> # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate_0 0.997912 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate_0 0.996872 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate_1 <err: div-0> # miss rate for demand accesses system.cpu.l2cache.demand_misses 956 # number of demand (read+write) misses system.cpu.l2cache.demand_misses_0 956 # number of demand (read+write) misses @@ -651,11 +651,11 @@ system.cpu.l2cache.demand_misses_1 0 # nu system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits_0 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits_1 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 3416500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency_0 3416500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 3405500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency_0 3405500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency_1 0 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate <err: div-0> # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate_0 0.997912 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate_0 0.996872 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate_1 <err: div-0> # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 956 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses_0 956 # number of demand (read+write) MSHR misses @@ -665,26 +665,26 @@ system.cpu.l2cache.mshr_cap_events 0 # nu system.cpu.l2cache.mshr_cap_events_0 0 # number of times MSHR cap was activated system.cpu.l2cache.mshr_cap_events_1 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 958 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses_0 958 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses 959 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses_0 959 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses_1 0 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency <err: div-0> # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency_0 6573.744770 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency_0 6562.238494 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency_1 <err: div-0> # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency_0 3573.744770 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency_0 3562.238494 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency_1 <err: div-0> # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency_0 <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency_1 <err: div-0> # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 2 # number of overall hits -system.cpu.l2cache.overall_hits_0 2 # number of overall hits +system.cpu.l2cache.overall_hits 3 # number of overall hits +system.cpu.l2cache.overall_hits_0 3 # number of overall hits system.cpu.l2cache.overall_hits_1 0 # number of overall hits -system.cpu.l2cache.overall_miss_latency 6284500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency_0 6284500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 6273500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency_0 6273500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency_1 0 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate <err: div-0> # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate_0 0.997912 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate_0 0.996872 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate_1 <err: div-0> # miss rate for overall accesses system.cpu.l2cache.overall_misses 956 # number of overall misses system.cpu.l2cache.overall_misses_0 956 # number of overall misses @@ -692,11 +692,11 @@ system.cpu.l2cache.overall_misses_1 0 # nu system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits_0 0 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits_1 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 3416500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency_0 3416500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 3405500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency_0 3405500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency_1 0 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate <err: div-0> # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate_0 0.997912 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate_0 0.996872 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate_1 <err: div-0> # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 956 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses_0 956 # number of overall MSHR misses @@ -723,29 +723,30 @@ system.cpu.l2cache.sampled_refs 782 # Sa system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.l2cache.soft_prefetch_mshr_full_0 0 # number of mshr full events for SW prefetching instrutions system.cpu.l2cache.soft_prefetch_mshr_full_1 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 419.781607 # Cycle average of tags in use -system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 444.416250 # Cycle average of tags in use +system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.l2cache.writebacks_0 0 # number of writebacks system.cpu.l2cache.writebacks_1 0 # number of writebacks -system.cpu.numCycles 12727 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 743 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 8102 # Number of HB maps that are committed -system.cpu.rename.RENAME:IdleCycles 17661 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 854 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 27553 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 21741 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 16306 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 3686 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 1667 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 906 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 8204 # Number of HB maps that are undone due to squashing +system.cpu.numCycles 14172 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 760 # Number of cycles rename is blocking +system.cpu.rename.RENAME:CommittedMaps 9074 # Number of HB maps that are committed +system.cpu.rename.RENAME:IQFullEvents 2 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 19739 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 868 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:RenameLookups 30813 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 24390 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 18197 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 4242 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 1860 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 926 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 9123 # Number of HB maps that are undone due to squashing system.cpu.rename.RENAME:serializeStallCycles 509 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializingInsts 48 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 2494 # count of insts added to the skid buffer +system.cpu.rename.RENAME:skidInsts 2524 # count of insts added to the skid buffer system.cpu.rename.RENAME:tempSerializingInsts 36 # count of temporary serializing insts renamed -system.cpu.timesIdled 16 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.timesIdled 15 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload0.PROG:num_syscalls 17 # Number of system calls system.cpu.workload1.PROG:num_syscalls 17 # Number of system calls diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout index 1b77a8f81..1c27475d4 100644 --- a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout +++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout @@ -5,13 +5,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 21 2008 20:12:56 -M5 started Mon Jul 21 20:12:59 2008 -M5 executing on zizzer -M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881 -M5 commit date Tue Jul 15 14:38:51 2008 -0400 +M5 compiled Jul 23 2008 15:48:11 +M5 started Wed Jul 23 15:49:40 2008 +M5 executing on blue +M5 revision 5515:47bf96eec2c6221cf91de8a078897c1b5e46cfbf +M5 commit date Wed Jul 23 15:35:08 2008 -0700 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/01.hello-2T-smt/alpha/linux/o3-timing tests/run.py quick/01.hello-2T-smt/alpha/linux/o3-timing Global frequency set at 1000000000000 ticks per second Hello world! Hello world! -Exiting @ tick 6363000 because target called exit() +Exiting @ tick 7085500 because target called exit() diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini index e981744fd..13cb0931f 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini +++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini @@ -368,6 +368,7 @@ cmd=insttest cwd= egid=100 env= +errout=cerr euid=100 executable=/dist/m5/regression/test-progs/insttest/bin/sparc/linux/insttest gid=100 diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/m5stats.txt b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/m5stats.txt index 29c5e75be..d4ce934cb 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/m5stats.txt +++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/m5stats.txt @@ -1,114 +1,114 @@ ---------- Begin Simulation Statistics ---------- global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -global.BPredUnit.BTBHits 2713 # Number of BTB hits -global.BPredUnit.BTBLookups 6851 # Number of BTB lookups +global.BPredUnit.BTBHits 4364 # Number of BTB hits +global.BPredUnit.BTBLookups 10024 # Number of BTB lookups global.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -global.BPredUnit.condIncorrect 2011 # Number of conditional branches incorrect -global.BPredUnit.condPredicted 7546 # Number of conditional branches predicted -global.BPredUnit.lookups 7546 # Number of BP lookups +global.BPredUnit.condIncorrect 2911 # Number of conditional branches incorrect +global.BPredUnit.condPredicted 11601 # Number of conditional branches predicted +global.BPredUnit.lookups 11601 # Number of BP lookups global.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. -host_inst_rate 33487 # Simulator instruction rate (inst/s) -host_mem_usage 153160 # Number of bytes of host memory used -host_seconds 0.31 # Real time elapsed on the host -host_tick_rate 49468437 # Simulator tick rate (ticks/s) -memdepunit.memDep.conflictingLoads 15 # Number of conflicting loads. +host_inst_rate 6832 # Simulator instruction rate (inst/s) +host_mem_usage 210732 # Number of bytes of host memory used +host_seconds 2.11 # Real time elapsed on the host +host_tick_rate 10370738 # Simulator tick rate (ticks/s) +memdepunit.memDep.conflictingLoads 29 # Number of conflicting loads. memdepunit.memDep.conflictingStores 0 # Number of conflicting stores. -memdepunit.memDep.insertedLoads 3058 # Number of loads inserted to the mem dependence unit. -memdepunit.memDep.insertedStores 2926 # Number of stores inserted to the mem dependence unit. +memdepunit.memDep.insertedLoads 4977 # Number of loads inserted to the mem dependence unit. +memdepunit.memDep.insertedStores 3503 # Number of stores inserted to the mem dependence unit. sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 10411 # Number of instructions simulated -sim_seconds 0.000015 # Number of seconds simulated -sim_ticks 15392500 # Number of ticks simulated -system.cpu.commit.COM:branches 2152 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 88 # number cycles where commit BW limit reached +sim_insts 14449 # Number of instructions simulated +sim_seconds 0.000022 # Number of seconds simulated +sim_ticks 21933500 # Number of ticks simulated +system.cpu.commit.COM:branches 3359 # Number of branches committed +system.cpu.commit.COM:bw_lim_events 105 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle.samples 27698 +system.cpu.commit.COM:committed_per_cycle.samples 39346 system.cpu.commit.COM:committed_per_cycle.min_value 0 - 0 22133 7990.83% - 1 3105 1121.02% - 2 1159 418.44% - 3 591 213.37% - 4 306 110.48% - 5 82 29.61% - 6 196 70.76% - 7 38 13.72% - 8 88 31.77% + 0 31195 7928.38% + 1 4789 1217.15% + 2 1729 439.43% + 3 717 182.23% + 4 416 105.73% + 5 147 37.36% + 6 198 50.32% + 7 50 12.71% + 8 105 26.69% system.cpu.commit.COM:committed_per_cycle.max_value 8 system.cpu.commit.COM:committed_per_cycle.end_dist -system.cpu.commit.COM:count 10976 # Number of instructions committed -system.cpu.commit.COM:loads 1462 # Number of loads committed +system.cpu.commit.COM:count 15175 # Number of instructions committed +system.cpu.commit.COM:loads 2226 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed -system.cpu.commit.COM:refs 2760 # Number of memory references committed +system.cpu.commit.COM:refs 3674 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 2011 # The number of times a branch was mispredicted -system.cpu.commit.commitCommittedInsts 10976 # The number of committed instructions -system.cpu.commit.commitNonSpecStalls 329 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 13116 # The number of squashed insts skipped by commit -system.cpu.committedInsts 10411 # Number of Instructions Simulated -system.cpu.committedInsts_total 10411 # Number of Instructions Simulated -system.cpu.cpi 2.957065 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.957065 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 2297 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 9364.130435 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7068.181818 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 2205 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 861500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.040052 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 92 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 26 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 466500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.028733 # mshr miss rate for ReadReq accesses +system.cpu.commit.branchMispredicts 2911 # The number of times a branch was mispredicted +system.cpu.commit.commitCommittedInsts 15175 # The number of committed instructions +system.cpu.commit.commitNonSpecStalls 475 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 20100 # The number of squashed insts skipped by commit +system.cpu.committedInsts 14449 # Number of Instructions Simulated +system.cpu.committedInsts_total 14449 # Number of Instructions Simulated +system.cpu.cpi 3.036058 # CPI: Cycles Per Instruction +system.cpu.cpi_total 3.036058 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 3844 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 9408.602151 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7113.636364 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 3751 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 875000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.024194 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 93 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 27 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 469500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.017170 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 66 # number of ReadReq MSHR misses system.cpu.dcache.SwapReq_accesses 6 # number of SwapReq accesses(hits+misses) system.cpu.dcache.SwapReq_hits 6 # number of SwapReq hits -system.cpu.dcache.WriteReq_accesses 1292 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 9880.434783 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 6966.666667 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 1062 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 2272500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.178019 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 230 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 125 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 731500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.081269 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 105 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_accesses 1442 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 9957.589286 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 7000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 1218 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 2230500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.155340 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 224 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 122 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 714000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.070735 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 102 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 21.736842 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 33.590604 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 3589 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 9732.919255 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 7005.847953 # average overall mshr miss latency -system.cpu.dcache.demand_hits 3267 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 3134000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.089719 # miss rate for demand accesses -system.cpu.dcache.demand_misses 322 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 151 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 1198000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.047646 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 171 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 5286 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 9796.529968 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 7044.642857 # average overall mshr miss latency +system.cpu.dcache.demand_hits 4969 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 3105500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.059970 # miss rate for demand accesses +system.cpu.dcache.demand_misses 317 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 149 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 1183500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.031782 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 168 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 3589 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 9732.919255 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 7005.847953 # average overall mshr miss latency +system.cpu.dcache.overall_accesses 5286 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 9796.529968 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 7044.642857 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 3267 # number of overall hits -system.cpu.dcache.overall_miss_latency 3134000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.089719 # miss rate for overall accesses -system.cpu.dcache.overall_misses 322 # number of overall misses -system.cpu.dcache.overall_mshr_hits 151 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 1198000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.047646 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 171 # number of overall MSHR misses +system.cpu.dcache.overall_hits 4969 # number of overall hits +system.cpu.dcache.overall_miss_latency 3105500 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.059970 # miss rate for overall accesses +system.cpu.dcache.overall_misses 317 # number of overall misses +system.cpu.dcache.overall_mshr_hits 149 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 1183500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.031782 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 168 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -121,88 +121,88 @@ system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.sampled_refs 152 # Sample count of references to valid blocks. +system.cpu.dcache.sampled_refs 149 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 110.780967 # Cycle average of tags in use -system.cpu.dcache.total_refs 3304 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 114.768529 # Cycle average of tags in use +system.cpu.dcache.total_refs 5005 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 4065 # Number of cycles decode is blocked -system.cpu.decode.DECODE:DecodedInsts 37568 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 13467 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 10101 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 2901 # Number of cycles decode is squashing -system.cpu.decode.DECODE:UnblockCycles 65 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 7546 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 4905 # Number of cache lines fetched -system.cpu.fetch.Cycles 16129 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 609 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 41611 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 2098 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.245111 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 4905 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 2713 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.351621 # Number of inst fetches per cycle +system.cpu.decode.DECODE:BlockedCycles 5414 # Number of cycles decode is blocked +system.cpu.decode.DECODE:DecodedInsts 52959 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 18733 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 15067 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 4338 # Number of cycles decode is squashing +system.cpu.decode.DECODE:UnblockCycles 132 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 11601 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 7392 # Number of cache lines fetched +system.cpu.fetch.Cycles 24155 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 764 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 59501 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 3008 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.264452 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 7392 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 4364 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.356365 # Number of inst fetches per cycle system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist.samples 30599 +system.cpu.fetch.rateDist.samples 43684 system.cpu.fetch.rateDist.min_value 0 - 0 19398 6339.42% - 1 4890 1598.09% - 2 619 202.29% - 3 711 232.36% - 4 788 257.52% - 5 642 209.81% - 6 612 200.01% - 7 196 64.05% - 8 2743 896.43% + 0 26944 6167.93% + 1 7490 1714.59% + 2 1209 276.76% + 3 1044 238.99% + 4 1055 241.51% + 5 1191 272.64% + 6 698 159.78% + 7 326 74.63% + 8 3727 853.17% system.cpu.fetch.rateDist.max_value 8 system.cpu.fetch.rateDist.end_dist -system.cpu.icache.ReadReq_accesses 4905 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 8897.590361 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 6462.162162 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 4490 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 3692500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.084608 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 415 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 45 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 2391000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.075433 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 370 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_accesses 7392 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 8917.690418 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 6472.527473 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 6985 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 3629500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.055060 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 407 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 43 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 2356000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.049242 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 364 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 12.135135 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 19.189560 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 4905 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 8897.590361 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 6462.162162 # average overall mshr miss latency -system.cpu.icache.demand_hits 4490 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 3692500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.084608 # miss rate for demand accesses -system.cpu.icache.demand_misses 415 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 45 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 2391000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.075433 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 370 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 7392 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 8917.690418 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 6472.527473 # average overall mshr miss latency +system.cpu.icache.demand_hits 6985 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 3629500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.055060 # miss rate for demand accesses +system.cpu.icache.demand_misses 407 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 43 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 2356000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.049242 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 364 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 4905 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 8897.590361 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 6462.162162 # average overall mshr miss latency +system.cpu.icache.overall_accesses 7392 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 8917.690418 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 6472.527473 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 4490 # number of overall hits -system.cpu.icache.overall_miss_latency 3692500 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.084608 # miss rate for overall accesses -system.cpu.icache.overall_misses 415 # number of overall misses -system.cpu.icache.overall_mshr_hits 45 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 2391000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.075433 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 370 # number of overall MSHR misses +system.cpu.icache.overall_hits 6985 # number of overall hits +system.cpu.icache.overall_miss_latency 3629500 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.055060 # miss rate for overall accesses +system.cpu.icache.overall_misses 407 # number of overall misses +system.cpu.icache.overall_mshr_hits 43 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 2356000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.049242 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 364 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -215,61 +215,61 @@ system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.icache.replacements 1 # number of replacements -system.cpu.icache.sampled_refs 370 # Sample count of references to valid blocks. +system.cpu.icache.sampled_refs 364 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 230.770092 # Cycle average of tags in use -system.cpu.icache.total_refs 4490 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 247.187481 # Cycle average of tags in use +system.cpu.icache.total_refs 6985 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 187 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 3077 # Number of branches executed -system.cpu.iew.EXEC:nop 1794 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.558825 # Inst execution rate -system.cpu.iew.EXEC:refs 4529 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 2104 # Number of stores executed +system.cpu.idleCycles 184 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 4855 # Number of branches executed +system.cpu.iew.EXEC:nop 2093 # number of nop insts executed +system.cpu.iew.EXEC:rate 0.570211 # Inst execution rate +system.cpu.iew.EXEC:refs 6456 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 2482 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 9158 # num instructions consuming a value -system.cpu.iew.WB:count 16580 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.828347 # average fanout of values written-back +system.cpu.iew.WB:consumers 13185 # num instructions consuming a value +system.cpu.iew.WB:count 24031 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.826773 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 7586 # num instructions producing a value -system.cpu.iew.WB:rate 0.538556 # insts written-back per cycle -system.cpu.iew.WB:sent 16781 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 2212 # Number of branch mispredicts detected at execute +system.cpu.iew.WB:producers 10901 # num instructions producing a value +system.cpu.iew.WB:rate 0.547802 # insts written-back per cycle +system.cpu.iew.WB:sent 24254 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 3206 # Number of branch mispredicts detected at execute system.cpu.iew.iewBlockCycles 0 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 3058 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 612 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 2936 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 2926 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 24197 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 2425 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2802 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 17204 # Number of executed instructions +system.cpu.iew.iewDispLoadInsts 4977 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 772 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 3232 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 3503 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 35402 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 3974 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 4417 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 25014 # Number of executed instructions system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 2901 # Number of cycles IEW is squashing +system.cpu.iew.iewSquashCycles 4338 # Number of cycles IEW is squashing system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 47 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 8 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.forwLoads 46 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 7 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 57 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.memOrderViolation 58 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 1596 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 1628 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 57 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 689 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 1523 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.338173 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.338173 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0 20006 # Type of FU issued +system.cpu.iew.lsq.thread.0.squashedLoads 2751 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 2055 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 58 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 769 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 2437 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 0.329374 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.329374 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0 29431 # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.start_dist No_OpClass 0 0.00% # Type of FU issued - IntAlu 14491 72.43% # Type of FU issued + IntAlu 21547 73.21% # Type of FU issued IntMult 0 0.00% # Type of FU issued IntDiv 0 0.00% # Type of FU issued FloatAdd 0 0.00% # Type of FU issued @@ -278,16 +278,16 @@ system.cpu.iq.ISSUE:FU_type_0.start_dist FloatMult 0 0.00% # Type of FU issued FloatDiv 0 0.00% # Type of FU issued FloatSqrt 0 0.00% # Type of FU issued - MemRead 2890 14.45% # Type of FU issued - MemWrite 2625 13.12% # Type of FU issued + MemRead 4739 16.10% # Type of FU issued + MemWrite 3145 10.69% # Type of FU issued IprAccess 0 0.00% # Type of FU issued InstPrefetch 0 0.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0.end_dist -system.cpu.iq.ISSUE:fu_busy_cnt 187 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.009347 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:fu_busy_cnt 188 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.006388 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full.start_dist No_OpClass 0 0.00% # attempts to use FU when none available - IntAlu 51 27.27% # attempts to use FU when none available + IntAlu 49 26.06% # attempts to use FU when none available IntMult 0 0.00% # attempts to use FU when none available IntDiv 0 0.00% # attempts to use FU when none available FloatAdd 0 0.00% # attempts to use FU when none available @@ -296,96 +296,96 @@ system.cpu.iq.ISSUE:fu_full.start_dist FloatMult 0 0.00% # attempts to use FU when none available FloatDiv 0 0.00% # attempts to use FU when none available FloatSqrt 0 0.00% # attempts to use FU when none available - MemRead 24 12.83% # attempts to use FU when none available - MemWrite 112 59.89% # attempts to use FU when none available + MemRead 25 13.30% # attempts to use FU when none available + MemWrite 114 60.64% # attempts to use FU when none available IprAccess 0 0.00% # attempts to use FU when none available InstPrefetch 0 0.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full.end_dist system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle.samples 30599 +system.cpu.iq.ISSUE:issued_per_cycle.samples 43684 system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 - 0 21747 7107.10% - 1 3624 1184.35% - 2 2137 698.39% - 3 1557 508.84% - 4 751 245.43% - 5 397 129.74% - 6 290 94.77% - 7 60 19.61% - 8 36 11.77% + 0 30754 7040.11% + 1 5431 1243.25% + 2 3052 698.65% + 3 2131 487.82% + 4 1026 234.87% + 5 660 151.09% + 6 361 82.64% + 7 219 50.13% + 8 50 11.45% system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 system.cpu.iq.ISSUE:issued_per_cycle.end_dist -system.cpu.iq.ISSUE:rate 0.649841 # Inst issue rate -system.cpu.iq.iqInstsAdded 21791 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 20006 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 612 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 10183 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 106 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 283 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 8044 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadExReq_accesses 86 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 5755.813953 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2755.813953 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 495000 # number of ReadExReq miss cycles +system.cpu.iq.ISSUE:rate 0.670899 # Inst issue rate +system.cpu.iq.iqInstsAdded 32537 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 29431 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 772 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 16058 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 100 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 297 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 12535 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadExReq_accesses 83 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 5795.180723 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2795.180723 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 481000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 86 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 237000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_misses 83 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 232000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 86 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 436 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 5417.824074 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2417.824074 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_misses 83 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 430 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 5433.098592 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2433.098592 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 4 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 2340500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.990826 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 432 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1044500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.990826 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 432 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_miss_latency 2314500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.990698 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 426 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 1036500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.990698 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 426 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 19 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_avg_miss_latency 5631.578947 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2631.578947 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_miss_latency 107000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_avg_miss_latency 5578.947368 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2578.947368 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_miss_latency 106000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_misses 19 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency 50000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency 49000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_misses 19 # number of UpgradeReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.009685 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.009828 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 522 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 5473.938224 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 2473.938224 # average overall mshr miss latency +system.cpu.l2cache.demand_accesses 513 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 5492.141454 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 2492.141454 # average overall mshr miss latency system.cpu.l2cache.demand_hits 4 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 2835500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.992337 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 518 # number of demand (read+write) misses +system.cpu.l2cache.demand_miss_latency 2795500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.992203 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 509 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 1281500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.992337 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 518 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 1268500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.992203 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 509 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 522 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 5473.938224 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 2473.938224 # average overall mshr miss latency +system.cpu.l2cache.overall_accesses 513 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 5492.141454 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 2492.141454 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 4 # number of overall hits -system.cpu.l2cache.overall_miss_latency 2835500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.992337 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 518 # number of overall misses +system.cpu.l2cache.overall_miss_latency 2795500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.992203 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 509 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 1281500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.992337 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 518 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 1268500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.992203 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 509 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -398,27 +398,27 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 413 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 407 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 257.005987 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 273.898723 # Cycle average of tags in use system.cpu.l2cache.total_refs 4 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 30786 # number of cpu cycles simulated -system.cpu.rename.RENAME:CommittedMaps 9868 # Number of HB maps that are committed -system.cpu.rename.RENAME:IdleCycles 14813 # Number of cycles rename is idle -system.cpu.rename.RENAME:RenameLookups 51330 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 29671 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 24234 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 8843 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 2901 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 230 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 14366 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 3812 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 646 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 4446 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 683 # count of temporary serializing insts renamed +system.cpu.numCycles 43868 # number of cpu cycles simulated +system.cpu.rename.RENAME:CommittedMaps 13832 # Number of HB maps that are committed +system.cpu.rename.RENAME:IdleCycles 20565 # Number of cycles rename is idle +system.cpu.rename.RENAME:RenameLookups 76206 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 43436 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 36362 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 13390 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 4338 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 306 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 22530 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 5085 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 899 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 5188 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 833 # count of temporary serializing insts renamed system.cpu.timesIdled 58 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.workload.PROG:num_syscalls 8 # Number of system calls +system.cpu.workload.PROG:num_syscalls 18 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stdout b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stdout index e6fab5604..502cab72d 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stdout +++ b/tests/quick/02.insttest/ref/sparc/linux/o3-timing/stdout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 21 2008 20:33:06 -M5 started Mon Jul 21 20:33:19 2008 -M5 executing on zizzer -M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881 -M5 commit date Tue Jul 15 14:38:51 2008 -0400 +M5 compiled Jul 23 2008 16:00:51 +M5 started Wed Jul 23 16:00:53 2008 +M5 executing on blue +M5 revision 5515:47bf96eec2c6221cf91de8a078897c1b5e46cfbf +M5 commit date Wed Jul 23 15:35:08 2008 -0700 command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/o3-timing tests/run.py quick/02.insttest/sparc/linux/o3-timing Global frequency set at 1000000000000 ticks per second Begining test of difficult SPARC instructions... @@ -23,4 +23,4 @@ LDTX: Passed LDTW: Passed STTW: Passed Done -Exiting @ tick 15392500 because target called exit() +Exiting @ tick 21933500 because target called exit() diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.ini b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.ini index ba8f324ab..fe774ce88 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.ini @@ -51,6 +51,7 @@ cmd=insttest cwd= egid=100 env= +errout=cerr euid=100 executable=/dist/m5/regression/test-progs/insttest/bin/sparc/linux/insttest gid=100 diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/m5stats.txt b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/m5stats.txt index da5a7c7d1..8d9b3b609 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/m5stats.txt +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/m5stats.txt @@ -1,18 +1,18 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2595 # Simulator instruction rate (inst/s) -host_mem_usage 173616 # Number of bytes of host memory used -host_seconds 4.23 # Real time elapsed on the host -host_tick_rate 1303618 # Simulator tick rate (ticks/s) +host_inst_rate 15225 # Simulator instruction rate (inst/s) +host_mem_usage 202592 # Number of bytes of host memory used +host_seconds 1.00 # Real time elapsed on the host +host_tick_rate 7641899 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 10976 # Number of instructions simulated -sim_seconds 0.000006 # Number of seconds simulated -sim_ticks 5514000 # Number of ticks simulated +sim_insts 15175 # Number of instructions simulated +sim_seconds 0.000008 # Number of seconds simulated +sim_ticks 7618500 # Number of ticks simulated system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 11029 # number of cpu cycles simulated -system.cpu.num_insts 10976 # Number of instructions executed -system.cpu.num_refs 2770 # Number of memory references -system.cpu.workload.PROG:num_syscalls 8 # Number of system calls +system.cpu.numCycles 15238 # number of cpu cycles simulated +system.cpu.num_insts 15175 # Number of instructions executed +system.cpu.num_refs 3684 # Number of memory references +system.cpu.workload.PROG:num_syscalls 18 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stdout b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stdout index 6632a0f07..91b36f948 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stdout +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stdout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 21 2008 20:33:06 -M5 started Mon Jul 21 20:33:18 2008 -M5 executing on zizzer -M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881 -M5 commit date Tue Jul 15 14:38:51 2008 -0400 +M5 compiled Jul 23 2008 16:00:51 +M5 started Wed Jul 23 16:02:07 2008 +M5 executing on blue +M5 revision 5515:47bf96eec2c6221cf91de8a078897c1b5e46cfbf +M5 commit date Wed Jul 23 15:35:08 2008 -0700 command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-atomic tests/run.py quick/02.insttest/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second Begining test of difficult SPARC instructions... @@ -23,4 +23,4 @@ LDTX: Passed LDTW: Passed STTW: Passed Done -Exiting @ tick 5514000 because target called exit() +Exiting @ tick 7618500 because target called exit() diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini index fa313ad0d..d0972f695 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini @@ -166,6 +166,7 @@ cmd=insttest cwd= egid=100 env= +errout=cerr euid=100 executable=/dist/m5/regression/test-progs/insttest/bin/sparc/linux/insttest gid=100 diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/m5stats.txt b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/m5stats.txt index 882e0c177..27bd0c98d 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/m5stats.txt +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/m5stats.txt @@ -1,69 +1,69 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 23807 # Simulator instruction rate (inst/s) -host_mem_usage 194964 # Number of bytes of host memory used -host_seconds 0.46 # Real time elapsed on the host -host_tick_rate 54716973 # Simulator tick rate (ticks/s) +host_inst_rate 26211 # Simulator instruction rate (inst/s) +host_mem_usage 210104 # Number of bytes of host memory used +host_seconds 0.58 # Real time elapsed on the host +host_tick_rate 52105150 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 10976 # Number of instructions simulated -sim_seconds 0.000025 # Number of seconds simulated -sim_ticks 25237000 # Number of ticks simulated -system.cpu.dcache.ReadReq_accesses 1462 # number of ReadReq accesses(hits+misses) +sim_insts 15175 # Number of instructions simulated +sim_seconds 0.000030 # Number of seconds simulated +sim_ticks 30178000 # Number of ticks simulated +system.cpu.dcache.ReadReq_accesses 2226 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_avg_miss_latency 27000 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 24000 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 1408 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 1458000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.036936 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 54 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 1296000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.036936 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 54 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_hits 2173 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 1431000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.023810 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 53 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 1272000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.023810 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 53 # number of ReadReq MSHR misses system.cpu.dcache.SwapReq_accesses 6 # number of SwapReq accesses(hits+misses) system.cpu.dcache.SwapReq_hits 6 # number of SwapReq hits -system.cpu.dcache.WriteReq_accesses 1292 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses 1442 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_avg_miss_latency 27000 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency 24000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 1187 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 2835000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.081269 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 105 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 2520000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.081269 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 105 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_hits 1340 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 2754000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.070735 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 102 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 2448000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.070735 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 102 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 18.436620 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 25.623188 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 2754 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses 3668 # number of demand (read+write) accesses system.cpu.dcache.demand_avg_miss_latency 27000 # average overall miss latency system.cpu.dcache.demand_avg_mshr_miss_latency 24000 # average overall mshr miss latency -system.cpu.dcache.demand_hits 2595 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 4293000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.057734 # miss rate for demand accesses -system.cpu.dcache.demand_misses 159 # number of demand (read+write) misses +system.cpu.dcache.demand_hits 3513 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 4185000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.042257 # miss rate for demand accesses +system.cpu.dcache.demand_misses 155 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 3816000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.057734 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 159 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_miss_latency 3720000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.042257 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 155 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 2754 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses 3668 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency 27000 # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 24000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 2595 # number of overall hits -system.cpu.dcache.overall_miss_latency 4293000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.057734 # miss rate for overall accesses -system.cpu.dcache.overall_misses 159 # number of overall misses +system.cpu.dcache.overall_hits 3513 # number of overall hits +system.cpu.dcache.overall_miss_latency 4185000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.042257 # miss rate for overall accesses +system.cpu.dcache.overall_misses 155 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 3816000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.057734 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 159 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_miss_latency 3720000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.042257 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 155 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -76,56 +76,56 @@ system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.sampled_refs 142 # Sample count of references to valid blocks. +system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 99.913779 # Cycle average of tags in use -system.cpu.dcache.total_refs 2618 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 102.837167 # Cycle average of tags in use +system.cpu.dcache.total_refs 3536 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_accesses 11012 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 26908.127208 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 23908.127208 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 10729 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 7615000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.025699 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 283 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 6766000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.025699 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 283 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_accesses 15221 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 26907.142857 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 23907.142857 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 14941 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 7534000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.018396 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 280 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency 6694000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.018396 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 280 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.icache.avg_refs 37.911661 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 53.360714 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 11012 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 26908.127208 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 23908.127208 # average overall mshr miss latency -system.cpu.icache.demand_hits 10729 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 7615000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.025699 # miss rate for demand accesses -system.cpu.icache.demand_misses 283 # number of demand (read+write) misses +system.cpu.icache.demand_accesses 15221 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 26907.142857 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 23907.142857 # average overall mshr miss latency +system.cpu.icache.demand_hits 14941 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 7534000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.018396 # miss rate for demand accesses +system.cpu.icache.demand_misses 280 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 6766000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.025699 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 283 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_miss_latency 6694000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.018396 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 280 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 11012 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 26908.127208 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 23908.127208 # average overall mshr miss latency +system.cpu.icache.overall_accesses 15221 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 26907.142857 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 23907.142857 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 10729 # number of overall hits -system.cpu.icache.overall_miss_latency 7615000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.025699 # miss rate for overall accesses -system.cpu.icache.overall_misses 283 # number of overall misses +system.cpu.icache.overall_hits 14941 # number of overall hits +system.cpu.icache.overall_miss_latency 7534000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.018396 # miss rate for overall accesses +system.cpu.icache.overall_misses 280 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 6766000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.025699 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 283 # number of overall MSHR misses +system.cpu.icache.overall_mshr_miss_latency 6694000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.018396 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 280 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -138,32 +138,32 @@ system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.sampled_refs 283 # Sample count of references to valid blocks. +system.cpu.icache.sampled_refs 280 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 154.924957 # Cycle average of tags in use -system.cpu.icache.total_refs 10729 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 165.376172 # Cycle average of tags in use +system.cpu.icache.total_refs 14941 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.l2cache.ReadExReq_accesses 88 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses 85 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_avg_miss_latency 23000 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 2024000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 1955000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 88 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 968000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_misses 85 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 935000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 88 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 337 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_mshr_misses 85 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 333 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_avg_miss_latency 23000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 7705000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.994065 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 335 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 3685000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.994065 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 335 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_miss_latency 7613000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.993994 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 331 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 3641000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.993994 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 331 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_accesses 17 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_avg_miss_latency 23000 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency @@ -175,38 +175,38 @@ system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 system.cpu.l2cache.UpgradeReq_mshr_misses 17 # number of UpgradeReq MSHR misses system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.006289 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.006369 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 425 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses 418 # number of demand (read+write) accesses system.cpu.l2cache.demand_avg_miss_latency 23000 # average overall miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 9729000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.995294 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 423 # number of demand (read+write) misses +system.cpu.l2cache.demand_miss_latency 9568000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.995215 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 416 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 4653000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.995294 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 423 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 4576000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.995215 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 416 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 425 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses 418 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 23000 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 2 # number of overall hits -system.cpu.l2cache.overall_miss_latency 9729000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.995294 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 423 # number of overall misses +system.cpu.l2cache.overall_miss_latency 9568000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.995215 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 416 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 4653000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.995294 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 423 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 4576000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.995215 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 416 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -219,16 +219,16 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 318 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 314 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 176.975795 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 187.735043 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 50474 # number of cpu cycles simulated -system.cpu.num_insts 10976 # Number of instructions executed -system.cpu.num_refs 2770 # Number of memory references -system.cpu.workload.PROG:num_syscalls 8 # Number of system calls +system.cpu.numCycles 60356 # number of cpu cycles simulated +system.cpu.num_insts 15175 # Number of instructions executed +system.cpu.num_refs 3684 # Number of memory references +system.cpu.workload.PROG:num_syscalls 18 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stdout b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stdout index e7f5d2afa..2511a0e62 100644 --- a/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stdout +++ b/tests/quick/02.insttest/ref/sparc/linux/simple-timing/stdout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Jul 21 2008 20:33:06 -M5 started Mon Jul 21 20:33:19 2008 -M5 executing on zizzer -M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881 -M5 commit date Tue Jul 15 14:38:51 2008 -0400 +M5 compiled Jul 23 2008 16:00:51 +M5 started Wed Jul 23 16:03:20 2008 +M5 executing on blue +M5 revision 5515:47bf96eec2c6221cf91de8a078897c1b5e46cfbf +M5 commit date Wed Jul 23 15:35:08 2008 -0700 command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-timing tests/run.py quick/02.insttest/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second Begining test of difficult SPARC instructions... @@ -23,4 +23,4 @@ LDTX: Passed LDTW: Passed STTW: Passed Done -Exiting @ tick 25237000 because target called exit() +Exiting @ tick 30178000 because target called exit() |