diff options
| author | Nilay Vaish <nilay@cs.wisc.edu> | 2013-03-29 14:05:36 -0500 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2013-03-29 14:05:36 -0500 |
| commit | 26e96b90e15cab3f2ae645e236da590527a64f75 (patch) | |
| tree | 9a1e74eab8239b9db337a784f8b881ed9d3f7e4d /tests/quick | |
| parent | ac778b1d02b0e7674811ab2a7463add16a430b36 (diff) | |
| download | gem5-26e96b90e15cab3f2ae645e236da590527a64f75.tar.xz | |
regressions: updates due to changes to o3 cpu, x86 memory map
Diffstat (limited to 'tests/quick')
8 files changed, 1060 insertions, 1068 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini index 527c82daf..33d5e9d03 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini @@ -185,7 +185,7 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=X86LocalApic -clock=500 +clock=8000 int_latency=1000 pio_addr=2305843009213693952 pio_latency=100000 @@ -258,6 +258,7 @@ type=CoherentBus block_size=64 clock=500 header_cycles=1 +system=system use_default_range=false width=32 master=system.cpu.l2cache.cpu_side @@ -268,17 +269,23 @@ type=ExeTracer [system.e820_table] type=X86E820Table -children=entries0 entries1 -entries=system.e820_table.entries0 system.e820_table.entries1 +children=entries0 entries1 entries2 +entries=system.e820_table.entries0 system.e820_table.entries1 system.e820_table.entries2 [system.e820_table.entries0] type=X86E820Entry addr=0 -range_type=2 -size=1048576 +range_type=1 +size=654336 [system.e820_table.entries1] type=X86E820Entry +addr=654336 +range_type=2 +size=394240 + +[system.e820_table.entries2] +type=X86E820Entry addr=1048576 range_type=1 size=133169152 @@ -668,6 +675,7 @@ children=badaddr_responder block_size=64 clock=1000 header_cycles=1 +system=system use_default_range=false width=8 default=system.membus.badaddr_responder.pio @@ -1127,25 +1135,28 @@ pio=system.iobus.master[9] [system.physmem] type=SimpleDRAM +activation_limit=4 addr_mapping=openmap banks_per_rank=8 +channels=1 clock=1000 conf_table_reported=false in_addr_map=true -lines_per_rowbuffer=64 -mem_sched_policy=fcfs +lines_per_rowbuffer=32 +mem_sched_policy=frfcfs null=false page_policy=open range=0:134217727 ranks_per_channel=2 read_buffer_size=32 -tBURST=4000 -tCL=14000 -tRCD=14000 +tBURST=5000 +tCL=13750 +tRCD=13750 tREFI=7800000 tRFC=300000 -tRP=14000 -tWTR=1000 +tRP=13750 +tWTR=7500 +tXAW=40000 write_buffer_size=32 write_thresh_perc=70 zero=false diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simerr b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simerr index a77b4f0ee..efd8a125a 100755 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simerr +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simerr @@ -1,3 +1,4 @@ +warn: add_child('terminal'): child 'terminal' already has parent warn: Sockets disabled, not accepting terminal connections warn: Reading current count from inactive timer. warn: Sockets disabled, not accepting gdb connections diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout index c7231a234..f095afad7 100755 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout @@ -3,13 +3,12 @@ Redirecting stderr to build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-si gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2013 16:30:44 -gem5 started Jan 23 2013 18:32:27 +gem5 compiled Mar 28 2013 09:59:18 +gem5 started Mar 28 2013 09:59:40 gem5 executing on ribera.cs.wisc.edu command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-atomic -re tests/run.py build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-atomic -warning: add_child('terminal'): child 'terminal' already has parent Global frequency set at 1000000000000 ticks per second info: kernel located at: /scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9 0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 5112040970500 because m5_exit instruction encountered +Exiting @ tick 5112099860500 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt index fb87772ef..55530e4a5 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt @@ -1,51 +1,51 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.112041 # Number of seconds simulated -sim_ticks 5112040970500 # Number of ticks simulated -final_tick 5112040970500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.112100 # Number of seconds simulated +sim_ticks 5112099860500 # Number of ticks simulated +final_tick 5112099860500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1074050 # Simulator instruction rate (inst/s) -host_op_rate 2199194 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 27479001055 # Simulator tick rate (ticks/s) -host_mem_usage 583620 # Number of bytes of host memory used -host_seconds 186.03 # Real time elapsed on the host -sim_insts 199810242 # Number of instructions simulated -sim_ops 409125913 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::pc.south_bridge.ide 2464640 # Number of bytes read from this memory +host_inst_rate 1028107 # Simulator instruction rate (inst/s) +host_op_rate 2105009 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 26291327617 # Simulator tick rate (ticks/s) +host_mem_usage 628192 # Number of bytes of host memory used +host_seconds 194.44 # Real time elapsed on the host +sim_insts 199905607 # Number of instructions simulated +sim_ops 409299132 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::pc.south_bridge.ide 2420928 # Number of bytes read from this memory system.physmem.bytes_read::cpu.dtb.walker 128 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 853824 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10600128 # Number of bytes read from this memory -system.physmem.bytes_read::total 13919040 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 853824 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 853824 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9292608 # Number of bytes written to this memory -system.physmem.bytes_written::total 9292608 # Number of bytes written to this memory -system.physmem.num_reads::pc.south_bridge.ide 38510 # Number of read requests responded to by this memory +system.physmem.bytes_read::cpu.inst 852736 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10605184 # Number of bytes read from this memory +system.physmem.bytes_read::total 13879296 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 852736 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 852736 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9264448 # Number of bytes written to this memory +system.physmem.bytes_written::total 9264448 # Number of bytes written to this memory +system.physmem.num_reads::pc.south_bridge.ide 37827 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.dtb.walker 2 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 13341 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 165627 # Number of read requests responded to by this memory -system.physmem.num_reads::total 217485 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 145197 # Number of write requests responded to by this memory -system.physmem.num_writes::total 145197 # Number of write requests responded to by this memory -system.physmem.bw_read::pc.south_bridge.ide 482124 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu.inst 13324 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 165706 # Number of read requests responded to by this memory +system.physmem.num_reads::total 216864 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 144757 # Number of write requests responded to by this memory +system.physmem.num_writes::total 144757 # Number of write requests responded to by this memory +system.physmem.bw_read::pc.south_bridge.ide 473568 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.dtb.walker 25 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 63 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 167022 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2073561 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2722795 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 167022 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 167022 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1817788 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1817788 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1817788 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 482124 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 166807 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2074526 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2714989 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 166807 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 166807 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1812259 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1812259 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1812259 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 473568 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 25 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 63 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 167022 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2073561 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4540583 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 166807 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2074526 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4527248 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 0 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 0 # Reqs generatd by CPU via cache - shady @@ -189,31 +189,31 @@ system.physmem.writeRowHits 0 # Nu system.physmem.readRowHitRate nan # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes system.physmem.avgGap nan # Average gap between requests -system.iocache.replacements 47569 # number of replacements -system.iocache.tagsinuse 0.042402 # Cycle average of tags in use +system.iocache.replacements 47568 # number of replacements +system.iocache.tagsinuse 0.042441 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 47585 # Sample count of references to valid blocks. +system.iocache.sampled_refs 47584 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 4994776682059 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::pc.south_bridge.ide 0.042402 # Average occupied blocks per requestor -system.iocache.occ_percent::pc.south_bridge.ide 0.002650 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.002650 # Average percentage of cache occupancy -system.iocache.ReadReq_misses::pc.south_bridge.ide 904 # number of ReadReq misses -system.iocache.ReadReq_misses::total 904 # number of ReadReq misses +system.iocache.warmup_cycle 4994822603059 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::pc.south_bridge.ide 0.042441 # Average occupied blocks per requestor +system.iocache.occ_percent::pc.south_bridge.ide 0.002653 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.002653 # Average percentage of cache occupancy +system.iocache.ReadReq_misses::pc.south_bridge.ide 903 # number of ReadReq misses +system.iocache.ReadReq_misses::total 903 # number of ReadReq misses system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses -system.iocache.demand_misses::pc.south_bridge.ide 47624 # number of demand (read+write) misses -system.iocache.demand_misses::total 47624 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 47624 # number of overall misses -system.iocache.overall_misses::total 47624 # number of overall misses -system.iocache.ReadReq_accesses::pc.south_bridge.ide 904 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 904 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::pc.south_bridge.ide 47623 # number of demand (read+write) misses +system.iocache.demand_misses::total 47623 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 47623 # number of overall misses +system.iocache.overall_misses::total 47623 # number of overall misses +system.iocache.ReadReq_accesses::pc.south_bridge.ide 903 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 903 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 47624 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 47624 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 47624 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 47624 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 47623 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 47623 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 47623 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 47623 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses @@ -245,63 +245,63 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.cpu.numCycles 10224081964 # number of cpu cycles simulated +system.cpu.numCycles 10224199744 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 199810242 # Number of instructions committed -system.cpu.committedOps 409125913 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 374289904 # Number of integer alu accesses +system.cpu.committedInsts 199905607 # Number of instructions committed +system.cpu.committedOps 409299132 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 374462045 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu.num_func_calls 0 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 39954533 # number of instructions that are conditional controls -system.cpu.num_int_insts 374289904 # number of integer instructions +system.cpu.num_conditional_control_insts 39972114 # number of instructions that are conditional controls +system.cpu.num_int_insts 374462045 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 915450656 # number of times the integer registers were read -system.cpu.num_int_register_writes 480322719 # number of times the integer registers were written +system.cpu.num_int_register_reads 915890298 # number of times the integer registers were read +system.cpu.num_int_register_writes 480542887 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 35624590 # number of memory refs -system.cpu.num_load_insts 27216588 # Number of load instructions -system.cpu.num_store_insts 8408002 # Number of store instructions -system.cpu.num_idle_cycles 9770609609.165962 # Number of idle cycles -system.cpu.num_busy_cycles 453472354.834038 # Number of busy cycles -system.cpu.not_idle_fraction 0.044353 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.955647 # Percentage of idle cycles +system.cpu.num_mem_refs 35654170 # number of memory refs +system.cpu.num_load_insts 27234345 # Number of load instructions +system.cpu.num_store_insts 8419825 # Number of store instructions +system.cpu.num_idle_cycles 9770518400.401503 # Number of idle cycles +system.cpu.num_busy_cycles 453681343.598497 # Number of busy cycles +system.cpu.not_idle_fraction 0.044373 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.955627 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu.icache.replacements 790732 # number of replacements -system.cpu.icache.tagsinuse 510.627675 # Cycle average of tags in use -system.cpu.icache.total_refs 243360727 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 791244 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 307.567232 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 148763114500 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 510.627675 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.997320 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.997320 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 243360727 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 243360727 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 243360727 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 243360727 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 243360727 # number of overall hits -system.cpu.icache.overall_hits::total 243360727 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 791251 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 791251 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 791251 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 791251 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 791251 # number of overall misses -system.cpu.icache.overall_misses::total 791251 # number of overall misses -system.cpu.icache.ReadReq_accesses::cpu.inst 244151978 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 244151978 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 244151978 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 244151978 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 244151978 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 244151978 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003241 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.003241 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.003241 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.003241 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.003241 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.003241 # miss rate for overall accesses +system.cpu.icache.replacements 790584 # number of replacements +system.cpu.icache.tagsinuse 510.666660 # Cycle average of tags in use +system.cpu.icache.total_refs 243492014 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 791096 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 307.790728 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 148824778500 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 510.666660 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.997396 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.997396 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 243492014 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 243492014 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 243492014 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 243492014 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 243492014 # number of overall hits +system.cpu.icache.overall_hits::total 243492014 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 791103 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 791103 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 791103 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 791103 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 791103 # number of overall misses +system.cpu.icache.overall_misses::total 791103 # number of overall misses +system.cpu.icache.ReadReq_accesses::cpu.inst 244283117 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 244283117 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 244283117 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 244283117 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 244283117 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 244283117 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003238 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.003238 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.003238 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.003238 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.003238 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.003238 # miss rate for overall accesses system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -311,43 +311,43 @@ system.cpu.icache.avg_blocked_cycles::no_targets nan system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.itb_walker_cache.replacements 3335 # number of replacements -system.cpu.itb_walker_cache.tagsinuse 3.026483 # Cycle average of tags in use -system.cpu.itb_walker_cache.total_refs 8029 # Total number of references to valid blocks. -system.cpu.itb_walker_cache.sampled_refs 3346 # Sample count of references to valid blocks. -system.cpu.itb_walker_cache.avg_refs 2.399582 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.warmup_cycle 5102019607500 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 3.026483 # Average occupied blocks per requestor -system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.189155 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.occ_percent::total 0.189155 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 8031 # number of ReadReq hits -system.cpu.itb_walker_cache.ReadReq_hits::total 8031 # number of ReadReq hits +system.cpu.itb_walker_cache.replacements 3477 # number of replacements +system.cpu.itb_walker_cache.tagsinuse 3.026333 # Cycle average of tags in use +system.cpu.itb_walker_cache.total_refs 7886 # Total number of references to valid blocks. +system.cpu.itb_walker_cache.sampled_refs 3489 # Sample count of references to valid blocks. +system.cpu.itb_walker_cache.avg_refs 2.260246 # Average number of references to valid blocks. +system.cpu.itb_walker_cache.warmup_cycle 5102064745500 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 3.026333 # Average occupied blocks per requestor +system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.189146 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.occ_percent::total 0.189146 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7887 # number of ReadReq hits +system.cpu.itb_walker_cache.ReadReq_hits::total 7887 # number of ReadReq hits system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits -system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 8033 # number of demand (read+write) hits -system.cpu.itb_walker_cache.demand_hits::total 8033 # number of demand (read+write) hits -system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 8033 # number of overall hits -system.cpu.itb_walker_cache.overall_hits::total 8033 # number of overall hits -system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4194 # number of ReadReq misses -system.cpu.itb_walker_cache.ReadReq_misses::total 4194 # number of ReadReq misses -system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4194 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_misses::total 4194 # number of demand (read+write) misses -system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4194 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::total 4194 # number of overall misses -system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12225 # number of ReadReq accesses(hits+misses) -system.cpu.itb_walker_cache.ReadReq_accesses::total 12225 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7889 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::total 7889 # number of demand (read+write) hits +system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7889 # number of overall hits +system.cpu.itb_walker_cache.overall_hits::total 7889 # number of overall hits +system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4332 # number of ReadReq misses +system.cpu.itb_walker_cache.ReadReq_misses::total 4332 # number of ReadReq misses +system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4332 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::total 4332 # number of demand (read+write) misses +system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4332 # number of overall misses +system.cpu.itb_walker_cache.overall_misses::total 4332 # number of overall misses +system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12219 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.ReadReq_accesses::total 12219 # number of ReadReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) -system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12227 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::total 12227 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12227 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::total 12227 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.343067 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.343067 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.343011 # miss rate for demand accesses -system.cpu.itb_walker_cache.demand_miss_rate::total 0.343011 # miss rate for demand accesses -system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.343011 # miss rate for overall accesses -system.cpu.itb_walker_cache.overall_miss_rate::total 0.343011 # miss rate for overall accesses +system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12221 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::total 12221 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12221 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::total 12221 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.354530 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.354530 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.354472 # miss rate for demand accesses +system.cpu.itb_walker_cache.demand_miss_rate::total 0.354472 # miss rate for demand accesses +system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.354472 # miss rate for overall accesses +system.cpu.itb_walker_cache.overall_miss_rate::total 0.354472 # miss rate for overall accesses system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -356,42 +356,42 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks::writebacks 593 # number of writebacks -system.cpu.itb_walker_cache.writebacks::total 593 # number of writebacks +system.cpu.itb_walker_cache.writebacks::writebacks 526 # number of writebacks +system.cpu.itb_walker_cache.writebacks::total 526 # number of writebacks system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.replacements 7597 # number of replacements -system.cpu.dtb_walker_cache.tagsinuse 5.013746 # Cycle average of tags in use -system.cpu.dtb_walker_cache.total_refs 13015 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.sampled_refs 7611 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.avg_refs 1.710025 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.warmup_cycle 5101206385500 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 5.013746 # Average occupied blocks per requestor -system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.313359 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.occ_percent::total 0.313359 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13017 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 13017 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13017 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 13017 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13017 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 13017 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8791 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 8791 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8791 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 8791 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8791 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 8791 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21808 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 21808 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21808 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 21808 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21808 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 21808 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.403109 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.403109 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.403109 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.403109 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.403109 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.403109 # miss rate for overall accesses +system.cpu.dtb_walker_cache.replacements 7629 # number of replacements +system.cpu.dtb_walker_cache.tagsinuse 5.014191 # Cycle average of tags in use +system.cpu.dtb_walker_cache.total_refs 12947 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.sampled_refs 7641 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.avg_refs 1.694412 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.warmup_cycle 5100425401500 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 5.014191 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.313387 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.occ_percent::total 0.313387 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 12955 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 12955 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 12955 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 12955 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 12955 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 12955 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8819 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 8819 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8819 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 8819 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8819 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 8819 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21774 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 21774 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21774 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 21774 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21774 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 21774 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.405024 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.405024 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.405024 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.405024 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.405024 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.405024 # miss rate for overall accesses system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -400,50 +400,50 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 2556 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 2556 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::writebacks 2413 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 2413 # number of writebacks system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1621135 # number of replacements -system.cpu.dcache.tagsinuse 511.999456 # Cycle average of tags in use -system.cpu.dcache.total_refs 20140431 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1621647 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 12.419738 # Average number of references to valid blocks. +system.cpu.dcache.replacements 1621965 # number of replacements +system.cpu.dcache.tagsinuse 511.999425 # Cycle average of tags in use +system.cpu.dcache.total_refs 20168700 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1622477 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 12.430808 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 7549500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.999456 # Average occupied blocks per requestor +system.cpu.dcache.occ_blocks::cpu.data 511.999425 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999999 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999999 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 12055941 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 12055941 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8082228 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8082228 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 20138169 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 20138169 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 20138169 # number of overall hits -system.cpu.dcache.overall_hits::total 20138169 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1308091 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1308091 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 315828 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 315828 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1623919 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1623919 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1623919 # number of overall misses -system.cpu.dcache.overall_misses::total 1623919 # number of overall misses -system.cpu.dcache.ReadReq_accesses::cpu.data 13364032 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 13364032 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 8398056 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8398056 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 21762088 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21762088 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 21762088 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21762088 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097881 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.097881 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037607 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.037607 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.074621 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.074621 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.074621 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.074621 # miss rate for overall accesses +system.cpu.dcache.ReadReq_hits::cpu.data 12073043 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 12073043 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 8093389 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8093389 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 20166432 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 20166432 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 20166432 # number of overall hits +system.cpu.dcache.overall_hits::total 20166432 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1308511 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1308511 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 316250 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 316250 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1624761 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1624761 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1624761 # number of overall misses +system.cpu.dcache.overall_misses::total 1624761 # number of overall misses +system.cpu.dcache.ReadReq_accesses::cpu.data 13381554 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 13381554 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 8409639 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 8409639 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 21791193 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 21791193 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 21791193 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 21791193 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097785 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.097785 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037606 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.037606 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.074560 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.074560 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.074560 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.074560 # miss rate for overall accesses system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -452,106 +452,106 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # 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number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6580 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 2705 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 791238 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1621024 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2421547 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000304 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001848 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016862 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.024614 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.021599 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.984649 # 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number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 791090 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1621856 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2422256 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000308 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001781 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016844 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.024657 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.021620 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.989029 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.989029 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.428028 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.428028 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000308 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001781 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016844 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.102746 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.074299 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000308 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001781 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016844 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.102746 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.074299 # miss rate for overall accesses system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -560,8 +560,8 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 98530 # number of writebacks -system.cpu.l2cache.writebacks::total 98530 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 98090 # number of writebacks +system.cpu.l2cache.writebacks::total 98090 # number of writebacks system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini index f5bfaf68d..640918742 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini @@ -181,7 +181,7 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=X86LocalApic -clock=500 +clock=8000 int_latency=1000 pio_addr=2305843009213693952 pio_latency=100000 @@ -254,6 +254,7 @@ type=CoherentBus block_size=64 clock=500 header_cycles=1 +system=system use_default_range=false width=32 master=system.cpu.l2cache.cpu_side @@ -264,17 +265,23 @@ type=ExeTracer [system.e820_table] type=X86E820Table -children=entries0 entries1 -entries=system.e820_table.entries0 system.e820_table.entries1 +children=entries0 entries1 entries2 +entries=system.e820_table.entries0 system.e820_table.entries1 system.e820_table.entries2 [system.e820_table.entries0] type=X86E820Entry addr=0 -range_type=2 -size=1048576 +range_type=1 +size=654336 [system.e820_table.entries1] type=X86E820Entry +addr=654336 +range_type=2 +size=394240 + +[system.e820_table.entries2] +type=X86E820Entry addr=1048576 range_type=1 size=133169152 @@ -664,6 +671,7 @@ children=badaddr_responder block_size=64 clock=1000 header_cycles=1 +system=system use_default_range=false width=8 default=system.membus.badaddr_responder.pio @@ -1123,25 +1131,28 @@ pio=system.iobus.master[9] [system.physmem] type=SimpleDRAM +activation_limit=4 addr_mapping=openmap banks_per_rank=8 +channels=1 clock=1000 conf_table_reported=false in_addr_map=true -lines_per_rowbuffer=64 -mem_sched_policy=fcfs +lines_per_rowbuffer=32 +mem_sched_policy=frfcfs null=false page_policy=open range=0:134217727 ranks_per_channel=2 read_buffer_size=32 -tBURST=4000 -tCL=14000 -tRCD=14000 +tBURST=5000 +tCL=13750 +tRCD=13750 tREFI=7800000 tRFC=300000 -tRP=14000 -tWTR=1000 +tRP=13750 +tWTR=7500 +tXAW=40000 write_buffer_size=32 write_thresh_perc=70 zero=false diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simerr b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simerr index a77b4f0ee..efd8a125a 100755 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simerr +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simerr @@ -1,3 +1,4 @@ +warn: add_child('terminal'): child 'terminal' already has parent warn: Sockets disabled, not accepting terminal connections warn: Reading current count from inactive timer. warn: Sockets disabled, not accepting gdb connections diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout index 0439ed364..3bb47e888 100755 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout @@ -3,13 +3,12 @@ Redirecting stderr to build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-si gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2013 16:30:44 -gem5 started Jan 23 2013 18:02:27 +gem5 compiled Mar 28 2013 09:59:18 +gem5 started Mar 28 2013 09:59:40 gem5 executing on ribera.cs.wisc.edu command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-timing -re tests/run.py build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-timing -warning: add_child('terminal'): child 'terminal' already has parent Global frequency set at 1000000000000 ticks per second info: kernel located at: /scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9 0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 5191112864000 because m5_exit instruction encountered +Exiting @ tick 5191816279000 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt index 064236544..00dd0b701 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt @@ -1,130 +1,126 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.195162 # Number of seconds simulated -sim_ticks 5195162021000 # Number of ticks simulated -final_tick 5195162021000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.191816 # Number of seconds simulated +sim_ticks 5191816279000 # Number of ticks simulated +final_tick 5191816279000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 434432 # Simulator instruction rate (inst/s) -host_op_rate 837466 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 17594801878 # Simulator tick rate (ticks/s) -host_mem_usage 611684 # Number of bytes of host memory used -host_seconds 295.27 # Real time elapsed on the host -sim_insts 128273373 # Number of instructions simulated -sim_ops 247275988 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::pc.south_bridge.ide 2861312 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 64 # Number of bytes read from this memory +host_inst_rate 631596 # Simulator instruction rate (inst/s) +host_op_rate 1217489 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 25553396248 # Simulator tick rate (ticks/s) +host_mem_usage 629228 # Number of bytes of host memory used +host_seconds 203.18 # Real time elapsed on the host +sim_insts 128324646 # Number of instructions simulated +sim_ops 247363464 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::pc.south_bridge.ide 2859648 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 823744 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9012160 # Number of bytes read from this memory -system.physmem.bytes_read::total 12697600 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 823744 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 823744 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8123136 # Number of bytes written to this memory -system.physmem.bytes_written::total 8123136 # Number of bytes written to this memory -system.physmem.num_reads::pc.south_bridge.ide 44708 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 1 # Number of read requests responded to by this memory +system.physmem.bytes_read::cpu.inst 823360 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9009408 # Number of bytes read from this memory +system.physmem.bytes_read::total 12692736 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 823360 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 823360 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8106432 # Number of bytes written to this memory +system.physmem.bytes_written::total 8106432 # Number of bytes written to this memory +system.physmem.num_reads::pc.south_bridge.ide 44682 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12871 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 140815 # Number of read requests responded to by this memory -system.physmem.num_reads::total 198400 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 126924 # Number of write requests responded to by this memory -system.physmem.num_writes::total 126924 # Number of write requests responded to by this memory -system.physmem.bw_read::pc.south_bridge.ide 550765 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 12 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu.inst 12865 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 140772 # Number of read requests responded to by this memory +system.physmem.num_reads::total 198324 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 126663 # Number of write requests responded to by this memory +system.physmem.num_writes::total 126663 # Number of write requests responded to by this memory +system.physmem.bw_read::pc.south_bridge.ide 550799 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 158560 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1734722 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2444120 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 158560 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 158560 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1563596 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1563596 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1563596 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 550765 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 12 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 158588 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1735309 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2444758 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 158588 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 158588 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1561387 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1561387 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1561387 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 550799 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 158560 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1734722 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4007716 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 198400 # Total number of read requests seen -system.physmem.writeReqs 126924 # Total number of write requests seen -system.physmem.cpureqs 326952 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 12697600 # Total number of bytes read from memory -system.physmem.bytesWritten 8123136 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 12697600 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 8123136 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 57 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 1624 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 12569 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 12080 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 12234 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 12524 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 12268 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 12127 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 12566 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 12719 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 12479 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 12349 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 12465 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 12500 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 12468 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 12050 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 12371 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 12574 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 8012 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 7683 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 7790 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 8089 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 7865 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 7679 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 8084 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 8243 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 8069 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 7980 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 7953 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 7969 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 7935 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 7628 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 7886 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 8059 # Track writes on a per bank basis +system.physmem.bw_total::cpu.inst 158588 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1735309 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4006145 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 198324 # Total number of read requests seen +system.physmem.writeReqs 126663 # Total number of write requests seen +system.physmem.cpureqs 326610 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 12692736 # Total number of bytes read from memory +system.physmem.bytesWritten 8106432 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 12692736 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 8106432 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 80 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 1618 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 12615 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 12250 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 12267 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 12575 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 12362 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 12187 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 12619 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 12562 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 12247 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 11965 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 12423 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 12610 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 12268 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 12172 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 12546 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 12576 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 8002 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 7779 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 7802 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 8120 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 7982 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 7804 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 8130 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 8156 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 7749 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 7475 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 7958 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 8068 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 7819 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 7741 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 7995 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 8083 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 4 # Number of times wr buffer was full causing retry -system.physmem.totGap 5195161957500 # Total gap between requests +system.physmem.numWrRetry 5 # Number of times wr buffer was full causing retry +system.physmem.totGap 5191816215500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 198400 # Categorize read packet sizes +system.physmem.readPktSize::6 198324 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 126924 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 155109 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 8773 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 6640 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3418 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3389 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2825 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2250 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2164 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 2085 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 2006 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1319 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1198 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1104 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1044 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 968 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 978 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 1114 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 1077 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 526 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 320 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 36 # What read queue length does an incoming req see +system.physmem.writePktSize::6 126663 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 155046 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 8732 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 6675 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3414 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3394 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2806 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2216 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2153 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 2094 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 2013 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1298 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1183 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1113 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1034 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 959 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 975 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 1125 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 1097 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 541 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 344 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 32 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -136,46 +132,46 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 4196 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4527 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 5315 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 5432 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 5480 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 5508 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 5513 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 5513 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 5514 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 5519 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 5518 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 5518 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 5518 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 5518 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 5518 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 5518 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 5518 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5518 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5518 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5518 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5518 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5518 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5518 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 1323 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 992 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 204 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 87 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 39 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 4186 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 4510 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 5285 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 5419 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 5454 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 5493 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 5497 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 5499 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 5502 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 5507 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 5507 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 5507 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 5507 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 5507 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 5507 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 5507 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 5507 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5507 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5507 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5507 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5507 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5507 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5507 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 1322 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 998 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 222 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 88 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 8 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 5 # What write queue length does an incoming req see -system.physmem.totQLat 4118897499 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 7915241249 # Sum of mem lat for all requests -system.physmem.totBusLat 991715000 # Total cycles spent in databus access -system.physmem.totBankLat 2804628750 # Total cycles spent in bank access -system.physmem.avgQLat 20766.54 # Average queueing delay per request -system.physmem.avgBankLat 14140.30 # Average bank access latency per request +system.physmem.totQLat 4084993999 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 7884046499 # Sum of mem lat for all requests +system.physmem.totBusLat 991220000 # Total cycles spent in databus access +system.physmem.totBankLat 2807832500 # Total cycles spent in bank access +system.physmem.avgQLat 20605.89 # Average queueing delay per request +system.physmem.avgBankLat 14163.52 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 39906.83 # Average memory access latency +system.physmem.avgMemAccLat 39769.41 # Average memory access latency system.physmem.avgRdBW 2.44 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 1.56 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 2.44 # Average consumed read bandwidth in MB/s @@ -183,45 +179,45 @@ system.physmem.avgConsumedWrBW 1.56 # Av system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time -system.physmem.avgWrQLen 12.66 # Average write queue length over time -system.physmem.readRowHits 175593 # Number of row buffer hits during reads -system.physmem.writeRowHits 94810 # Number of row buffer hits during writes -system.physmem.readRowHitRate 88.53 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 74.70 # Row buffer hit rate for writes -system.physmem.avgGap 15969193.66 # Average gap between requests -system.iocache.replacements 47509 # number of replacements -system.iocache.tagsinuse 0.124742 # Cycle average of tags in use +system.physmem.avgWrQLen 8.79 # Average write queue length over time +system.physmem.readRowHits 175346 # Number of row buffer hits during reads +system.physmem.writeRowHits 94626 # Number of row buffer hits during writes +system.physmem.readRowHitRate 88.45 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 74.71 # Row buffer hit rate for writes +system.physmem.avgGap 15975458.14 # Average gap between requests +system.iocache.replacements 47501 # number of replacements +system.iocache.tagsinuse 0.114811 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 47525 # Sample count of references to valid blocks. +system.iocache.sampled_refs 47517 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 5044527520000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::pc.south_bridge.ide 0.124742 # Average occupied blocks per requestor -system.iocache.occ_percent::pc.south_bridge.ide 0.007796 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.007796 # Average percentage of cache occupancy -system.iocache.ReadReq_misses::pc.south_bridge.ide 844 # number of ReadReq misses -system.iocache.ReadReq_misses::total 844 # number of ReadReq misses +system.iocache.warmup_cycle 5044702860000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::pc.south_bridge.ide 0.114811 # Average occupied blocks per requestor +system.iocache.occ_percent::pc.south_bridge.ide 0.007176 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.007176 # Average percentage of cache occupancy +system.iocache.ReadReq_misses::pc.south_bridge.ide 836 # number of ReadReq misses +system.iocache.ReadReq_misses::total 836 # number of ReadReq misses system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses -system.iocache.demand_misses::pc.south_bridge.ide 47564 # number of demand (read+write) misses -system.iocache.demand_misses::total 47564 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 47564 # number of overall misses -system.iocache.overall_misses::total 47564 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 137986397 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 137986397 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 10732360679 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 10732360679 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 10870347076 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 10870347076 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 10870347076 # number of overall miss cycles -system.iocache.overall_miss_latency::total 10870347076 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 844 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 844 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::pc.south_bridge.ide 47556 # number of demand (read+write) misses +system.iocache.demand_misses::total 47556 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 47556 # number of overall misses +system.iocache.overall_misses::total 47556 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 136123397 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 136123397 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 10718582907 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 10718582907 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 10854706304 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 10854706304 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 10854706304 # number of overall miss cycles +system.iocache.overall_miss_latency::total 10854706304 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 836 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 836 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 47564 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 47564 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 47564 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 47564 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 47556 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 47556 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 47556 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 47556 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses @@ -230,40 +226,40 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 163490.991706 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 163490.991706 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 229716.624122 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 229716.624122 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 228541.482550 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 228541.482550 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 228541.482550 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 228541.482550 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 175903 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 162827.029904 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 162827.029904 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 229421.723181 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 229421.723181 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 228251.036757 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 228251.036757 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 228251.036757 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 228251.036757 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 175533 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 16290 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 16256 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 10.798220 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 10.798044 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 46667 # number of writebacks system.iocache.writebacks::total 46667 # number of writebacks -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 844 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 844 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 836 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 836 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 47564 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 47564 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 47564 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 47564 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 94077427 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 94077427 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 8301562585 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 8301562585 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 8395640012 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 8395640012 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 8395640012 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 8395640012 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::pc.south_bridge.ide 47556 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 47556 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 47556 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 47556 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 92629177 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 92629177 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 8287786786 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 8287786786 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 8380415963 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 8380415963 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 8380415963 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 8380415963 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses @@ -272,14 +268,14 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 111466.145735 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 111466.145735 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 177687.555330 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 177687.555330 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 176512.488689 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 176512.488689 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 176512.488689 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 176512.488689 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 110800.450957 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 110800.450957 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 177392.696618 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 177392.696618 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 176222.053221 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 176222.053221 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 176222.053221 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 176222.053221 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). @@ -293,75 +289,75 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.cpu.numCycles 10390324042 # number of cpu cycles simulated +system.cpu.numCycles 10383632558 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 128273373 # Number of instructions committed -system.cpu.committedOps 247275988 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 232011695 # Number of integer alu accesses +system.cpu.committedInsts 128324646 # Number of instructions committed +system.cpu.committedOps 247363464 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 232097683 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu.num_func_calls 0 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 23157364 # number of instructions that are conditional controls -system.cpu.num_int_insts 232011695 # number of integer instructions +system.cpu.num_conditional_control_insts 23165556 # number of instructions that are conditional controls +system.cpu.num_int_insts 232097683 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 567056109 # number of times the integer registers were read -system.cpu.num_int_register_writes 293242196 # number of times the integer registers were written +system.cpu.num_int_register_reads 567280399 # number of times the integer registers were read +system.cpu.num_int_register_writes 293347970 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 22232145 # number of memory refs -system.cpu.num_load_insts 13871789 # Number of load instructions -system.cpu.num_store_insts 8360356 # Number of store instructions -system.cpu.num_idle_cycles 9789660715.998116 # Number of idle cycles -system.cpu.num_busy_cycles 600663326.001884 # Number of busy cycles -system.cpu.not_idle_fraction 0.057810 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.942190 # Percentage of idle cycles +system.cpu.num_mem_refs 22249385 # number of memory refs +system.cpu.num_load_insts 13880834 # Number of load instructions +system.cpu.num_store_insts 8368551 # Number of store instructions +system.cpu.num_idle_cycles 9782435662.998116 # Number of idle cycles +system.cpu.num_busy_cycles 601196895.001884 # Number of busy cycles +system.cpu.not_idle_fraction 0.057899 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.942101 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu.icache.replacements 791527 # number of replacements -system.cpu.icache.tagsinuse 510.376104 # Cycle average of tags in use -system.cpu.icache.total_refs 144497724 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 792039 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 182.437638 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 159800886000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 510.376104 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.996828 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.996828 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 144497724 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 144497724 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 144497724 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 144497724 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 144497724 # number of overall hits -system.cpu.icache.overall_hits::total 144497724 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 792046 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 792046 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 792046 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 792046 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 792046 # number of overall misses -system.cpu.icache.overall_misses::total 792046 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 10958971500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 10958971500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 10958971500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 10958971500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 10958971500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 10958971500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 145289770 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 145289770 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 145289770 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 145289770 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 145289770 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 145289770 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005451 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.005451 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.005451 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.005451 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.005451 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.005451 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13836.281605 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13836.281605 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13836.281605 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13836.281605 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13836.281605 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13836.281605 # average overall miss latency +system.cpu.icache.replacements 795387 # number of replacements +system.cpu.icache.tagsinuse 510.410338 # Cycle average of tags in use +system.cpu.icache.total_refs 144562130 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 795899 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 181.633763 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 160005789000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 510.410338 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.996895 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.996895 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 144562130 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 144562130 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 144562130 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 144562130 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 144562130 # number of overall hits +system.cpu.icache.overall_hits::total 144562130 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 795906 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 795906 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 795906 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 795906 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 795906 # number of overall misses +system.cpu.icache.overall_misses::total 795906 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 11017856500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 11017856500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 11017856500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 11017856500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 11017856500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 11017856500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 145358036 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 145358036 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 145358036 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 145358036 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 145358036 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 145358036 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005475 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.005475 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.005475 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.005475 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.005475 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.005475 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13843.163012 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13843.163012 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13843.163012 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13843.163012 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13843.163012 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13843.163012 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -370,80 +366,80 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 792046 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 792046 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 792046 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 792046 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 792046 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 792046 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9374879500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 9374879500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9374879500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 9374879500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9374879500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 9374879500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005451 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005451 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005451 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.005451 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005451 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.005451 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11836.281605 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11836.281605 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11836.281605 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11836.281605 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11836.281605 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11836.281605 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 795906 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 795906 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 795906 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 795906 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 795906 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 795906 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9426044500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 9426044500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9426044500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 9426044500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9426044500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 9426044500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005475 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005475 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005475 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.005475 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005475 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.005475 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11843.163012 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11843.163012 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11843.163012 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11843.163012 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11843.163012 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11843.163012 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.itb_walker_cache.replacements 3425 # number of replacements -system.cpu.itb_walker_cache.tagsinuse 3.077880 # Cycle average of tags in use -system.cpu.itb_walker_cache.total_refs 8006 # Total number of references to valid blocks. -system.cpu.itb_walker_cache.sampled_refs 3437 # Sample count of references to valid blocks. -system.cpu.itb_walker_cache.avg_refs 2.329357 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.warmup_cycle 5164120857000 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 3.077880 # Average occupied blocks per requestor -system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.192367 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.occ_percent::total 0.192367 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 8004 # number of ReadReq hits -system.cpu.itb_walker_cache.ReadReq_hits::total 8004 # number of ReadReq hits +system.cpu.itb_walker_cache.replacements 3694 # number of replacements +system.cpu.itb_walker_cache.tagsinuse 3.067610 # Cycle average of tags in use +system.cpu.itb_walker_cache.total_refs 7642 # Total number of references to valid blocks. +system.cpu.itb_walker_cache.sampled_refs 3706 # Sample count of references to valid blocks. +system.cpu.itb_walker_cache.avg_refs 2.062062 # Average number of references to valid blocks. +system.cpu.itb_walker_cache.warmup_cycle 5165748244000 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 3.067610 # Average occupied blocks per requestor +system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.191726 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.occ_percent::total 0.191726 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7663 # number of ReadReq hits +system.cpu.itb_walker_cache.ReadReq_hits::total 7663 # number of ReadReq hits system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits -system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 8006 # number of demand (read+write) hits -system.cpu.itb_walker_cache.demand_hits::total 8006 # number of demand (read+write) hits -system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 8006 # number of overall hits -system.cpu.itb_walker_cache.overall_hits::total 8006 # number of overall hits -system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4287 # number of ReadReq misses -system.cpu.itb_walker_cache.ReadReq_misses::total 4287 # number of ReadReq misses -system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4287 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_misses::total 4287 # number of demand (read+write) misses -system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4287 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::total 4287 # number of overall misses -system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 42274000 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.ReadReq_miss_latency::total 42274000 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 42274000 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::total 42274000 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 42274000 # number of overall miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::total 42274000 # number of overall miss cycles -system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12291 # number of ReadReq accesses(hits+misses) -system.cpu.itb_walker_cache.ReadReq_accesses::total 12291 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7665 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::total 7665 # number of demand (read+write) hits +system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7665 # number of overall hits +system.cpu.itb_walker_cache.overall_hits::total 7665 # number of overall hits +system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4553 # number of ReadReq misses +system.cpu.itb_walker_cache.ReadReq_misses::total 4553 # number of ReadReq misses +system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4553 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::total 4553 # number of demand (read+write) misses +system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4553 # number of overall misses +system.cpu.itb_walker_cache.overall_misses::total 4553 # number of overall misses +system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 46128000 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.ReadReq_miss_latency::total 46128000 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 46128000 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::total 46128000 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 46128000 # number of overall miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::total 46128000 # number of overall miss cycles +system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12216 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.ReadReq_accesses::total 12216 # number of ReadReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) -system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12293 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::total 12293 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12293 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::total 12293 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.348792 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.348792 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.348735 # miss rate for demand accesses -system.cpu.itb_walker_cache.demand_miss_rate::total 0.348735 # miss rate for demand accesses -system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.348735 # miss rate for overall accesses -system.cpu.itb_walker_cache.overall_miss_rate::total 0.348735 # miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 9860.975041 # average ReadReq miss latency -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 9860.975041 # average ReadReq miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 9860.975041 # average overall miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::total 9860.975041 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 9860.975041 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::total 9860.975041 # average overall miss latency +system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12218 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::total 12218 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12218 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::total 12218 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.372708 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.372708 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.372647 # miss rate for demand accesses +system.cpu.itb_walker_cache.demand_miss_rate::total 0.372647 # miss rate for demand accesses +system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.372647 # miss rate for overall accesses +system.cpu.itb_walker_cache.overall_miss_rate::total 0.372647 # miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 10131.341972 # average ReadReq miss latency +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 10131.341972 # average ReadReq miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 10131.341972 # average overall miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::total 10131.341972 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 10131.341972 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::total 10131.341972 # average overall miss latency system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -452,78 +448,78 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks::writebacks 641 # number of writebacks -system.cpu.itb_walker_cache.writebacks::total 641 # number of writebacks -system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 4287 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 4287 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 4287 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::total 4287 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 4287 # number of overall MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::total 4287 # number of overall MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 33700000 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 33700000 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 33700000 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 33700000 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 33700000 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 33700000 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.348792 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.348792 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.348735 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.348735 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.348735 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.348735 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 7860.975041 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 7860.975041 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 7860.975041 # average overall mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 7860.975041 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 7860.975041 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 7860.975041 # average overall mshr miss latency +system.cpu.itb_walker_cache.writebacks::writebacks 782 # number of writebacks +system.cpu.itb_walker_cache.writebacks::total 782 # number of writebacks +system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 4553 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 4553 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 4553 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::total 4553 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 4553 # number of overall MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::total 4553 # number of overall MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 37022000 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 37022000 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 37022000 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 37022000 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 37022000 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 37022000 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.372708 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.372708 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.372647 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.372647 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.372647 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.372647 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 8131.341972 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8131.341972 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 8131.341972 # average overall mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 8131.341972 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 8131.341972 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 8131.341972 # average overall mshr miss latency system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.replacements 7539 # number of replacements -system.cpu.dtb_walker_cache.tagsinuse 5.062514 # Cycle average of tags in use -system.cpu.dtb_walker_cache.total_refs 13178 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.sampled_refs 7553 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.avg_refs 1.744737 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.warmup_cycle 5159123845000 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 5.062514 # Average occupied blocks per requestor -system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.316407 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.occ_percent::total 0.316407 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13180 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 13180 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13180 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 13180 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13180 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 13180 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8726 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 8726 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8726 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 8726 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8726 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 8726 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 92094500 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 92094500 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 92094500 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::total 92094500 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 92094500 # number of overall miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::total 92094500 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21906 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 21906 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21906 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 21906 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21906 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 21906 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.398338 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.398338 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.398338 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.398338 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.398338 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.398338 # miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10554.033922 # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10554.033922 # average ReadReq miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10554.033922 # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10554.033922 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10554.033922 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10554.033922 # average overall miss latency +system.cpu.dtb_walker_cache.replacements 8348 # number of replacements +system.cpu.dtb_walker_cache.tagsinuse 5.050573 # Cycle average of tags in use +system.cpu.dtb_walker_cache.total_refs 12635 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.sampled_refs 8361 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.avg_refs 1.511183 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.warmup_cycle 5162441732000 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 5.050573 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.315661 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.occ_percent::total 0.315661 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 12638 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 12638 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 12638 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 12638 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 12638 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 12638 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 9544 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 9544 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 9544 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 9544 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 9544 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 9544 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 102265000 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 102265000 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 102265000 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::total 102265000 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 102265000 # number of overall miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::total 102265000 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 22182 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 22182 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 22182 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 22182 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 22182 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 22182 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.430259 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.430259 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.430259 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.430259 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.430259 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.430259 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10715.108969 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10715.108969 # average ReadReq miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10715.108969 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10715.108969 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10715.108969 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10715.108969 # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -532,90 +528,90 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 2713 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 2713 # number of writebacks -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 8726 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 8726 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 8726 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::total 8726 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 8726 # number of overall MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::total 8726 # number of overall MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 74642500 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 74642500 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 74642500 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 74642500 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 74642500 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 74642500 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.398338 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.398338 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.398338 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.398338 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.398338 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.398338 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 8554.033922 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8554.033922 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 8554.033922 # average overall mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 8554.033922 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 8554.033922 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 8554.033922 # average overall mshr miss latency +system.cpu.dtb_walker_cache.writebacks::writebacks 3309 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 3309 # number of writebacks +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 9544 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 9544 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 9544 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::total 9544 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 9544 # number of overall MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::total 9544 # number of overall MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 83177000 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 83177000 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 83177000 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 83177000 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 83177000 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 83177000 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.430259 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.430259 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.430259 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.430259 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.430259 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.430259 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 8715.108969 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8715.108969 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 8715.108969 # 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Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1620731 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 12.365534 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 39012000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.997766 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999996 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999996 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 11988260 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 11988260 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8035474 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8035474 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 20023734 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 20023734 # 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average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27176.640583 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 27176.640583 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 16591.443443 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 16591.443443 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 16591.443443 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 16591.443443 # average overall miss latency +system.cpu.dcache.occ_blocks::cpu.data 511.997551 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999995 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999995 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 11996661 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 11996661 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 8042358 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8042358 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 20039019 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 20039019 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 20039019 # number of overall hits +system.cpu.dcache.overall_hits::total 20039019 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1307017 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1307017 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 315944 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 315944 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1622961 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1622961 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1622961 # 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number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 8358302 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 8358302 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 21661980 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 21661980 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 21661980 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 21661980 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098245 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.098245 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037800 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.037800 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.074922 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.074922 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.074922 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.074922 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14030.785751 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14030.785751 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27121.869698 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 27121.869698 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 16579.244665 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 16579.244665 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 16579.244665 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 16579.244665 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -624,46 +620,46 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1536058 # number of writebacks -system.cpu.dcache.writebacks::total 1536058 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1306617 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1306617 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 314888 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 314888 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1621505 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1621505 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1621505 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1621505 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 15732276500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 15732276500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7927822000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 7927822000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23660098500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 23660098500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23660098500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 23660098500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 94145949000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 94145949000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2467833000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2467833000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 96613782000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 96613782000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.098280 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.098280 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037710 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037710 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.074913 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.074913 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074913 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.074913 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12040.465186 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12040.465186 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25176.640583 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25176.640583 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14591.443443 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 14591.443443 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14591.443443 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 14591.443443 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 1537528 # number of writebacks +system.cpu.dcache.writebacks::total 1537528 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1307017 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1307017 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 315944 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 315944 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1622961 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1622961 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1622961 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1622961 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 15724441500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 15724441500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7937104000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 7937104000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23661545500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 23661545500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23661545500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 23661545500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 94200592000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 94200592000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2523051000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2523051000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 96723643000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 96723643000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.098245 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.098245 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037800 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037800 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.074922 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.074922 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074922 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.074922 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12030.785751 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12030.785751 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25121.869698 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25121.869698 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14579.244665 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 14579.244665 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14579.244665 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 14579.244665 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -671,141 +667,127 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 86864 # number of replacements -system.cpu.l2cache.tagsinuse 64770.428854 # Cycle average of tags in use -system.cpu.l2cache.total_refs 3484759 # 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