diff options
| author | Gabe Black <gabeblack@google.com> | 2017-03-29 18:50:49 -0700 |
|---|---|---|
| committer | Gabe Black <gabeblack@google.com> | 2017-04-05 18:39:08 +0000 |
| commit | 1297ee31f652e0ae0b2a6664b206f44ba8bcdcb0 (patch) | |
| tree | 81caab6a29daef750bf2cdad2626e39ed168129b /tests/quick | |
| parent | 33c48b50cdaa4ba498022c1441bed3dbdc5064c1 (diff) | |
| download | gem5-1297ee31f652e0ae0b2a6664b206f44ba8bcdcb0.tar.xz | |
stats: Update ARM FS stats.
The change below changed the behavior of interrupts on ARM and changed the
stats for the 10.linux-boot regression.
commit 746e2f3c27ad83c36b7bc3b8bd3c92004fcf995b
Author: Sudhanshu Jha <sudhanshu.jha@arm.com>
Date: Mon Feb 27 10:29:56 2017 +0000
arm, kmi: Clear interrupts in KMI devices
Change-Id: Ie1cfc26777f6ed2d3fd4340175941fda1fdb5b6a
Reviewed-on: https://gem5-review.googlesource.com/2653
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Diffstat (limited to 'tests/quick')
8 files changed, 4767 insertions, 4774 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini index 8acd582b2..4448abd9b 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini @@ -12,12 +12,12 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain atags_addr=134217728 -boot_loader=/dist/m5/system/binaries/boot_emm.arm +boot_loader=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/boot_emm.arm boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1 cache_line_size=64 clk_domain=system.clk_domain default_p_state=UNDEFINED -dtb_filename=/dist/m5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb +dtb_filename=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb early_kernel_symbols=false enable_context_switch_stats_dump=false eventq_index=0 @@ -30,7 +30,7 @@ have_security=false have_virtualization=false highest_el_is_64=false init_param=0 -kernel=/dist/m5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5 +kernel=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5 kernel_addr_check=true load_addr_mask=268435455 load_offset=2147483648 @@ -49,7 +49,7 @@ panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 power_model=Null -readfile=/z/powerjg/gem5-upstream/tests/testing/../halt.sh +readfile=/usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../halt.sh reset_addr_64=0 symbolfile= thermal_components= @@ -99,7 +99,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage eventq_index=0 -image_file=/dist/m5/system/disks/linux-aarch32-ael.img +image_file=/usr/local/google/home/gabeblack/gem5/dist/m5/system/disks/linux-aarch32-ael.img read_only=true [system.clk_domain] @@ -144,6 +144,7 @@ progress_interval=0 simpoint_start_insts= socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu0.tracer workload= @@ -314,8 +315,6 @@ id_aa64isar0_el1=0 id_aa64isar1_el1=0 id_aa64mmfr0_el1=15728642 id_aa64mmfr1_el1=0 -id_aa64pfr0_el1=34 -id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 @@ -326,8 +325,6 @@ id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 id_mmfr3=34611729 -id_pfr0=49 -id_pfr1=4113 midr=1091551472 pmu=Null system=system @@ -528,6 +525,7 @@ progress_interval=0 simpoint_start_insts= socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu1.tracer workload= @@ -698,8 +696,6 @@ id_aa64isar0_el1=0 id_aa64isar1_el1=0 id_aa64mmfr0_el1=15728642 id_aa64mmfr1_el1=0 -id_aa64pfr0_el1=34 -id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 @@ -710,8 +706,6 @@ id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 id_mmfr3=34611729 -id_pfr0=49 -id_pfr1=4113 midr=1091551472 pmu=Null system=system diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simerr b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simerr index 2d943ab5b..8afd31f96 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simerr +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simerr @@ -1,10 +1,15 @@ warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes) +info: kernel located at: /usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5 warn: Sockets disabled, not accepting vnc client connections warn: Sockets disabled, not accepting terminal connections warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Using bootloader at address 0x10 +info: Using kernel entry physical address at 0x80008000 +info: Loading DTB file: /usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb at address 0x88000000 warn: Existing EnergyCtrl, but no enabled DVFSHandler found. +info: Entering event queue @ 0. Starting simulation... warn: Not doing anything for miscreg ACTLR warn: Not doing anything for write of miscreg ACTLR warn: The clidr register always reports 0 caches. @@ -25,9 +30,24 @@ warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 warn: Not doing anything for miscreg ACTLR warn: Not doing anything for write of miscreg ACTLR warn: instruction 'mcr bpiall' unimplemented +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 warn: CP14 unimplemented crn[1], opc1[0], crm[3], opc2[4] warn: CP14 unimplemented crn[1], opc1[0], crm[0], opc2[4] warn: CP14 unimplemented crn[0], opc1[0], crm[7], opc2[0] diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout index f67601b8a..b4daff1c0 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout @@ -3,30 +3,10 @@ Redirecting stderr to build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realv gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Nov 29 2016 19:03:48 -gem5 started Nov 29 2016 19:04:20 -gem5 executing on zizzer, pid 5756 -command line: /z/powerjg/gem5-upstream/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual +gem5 compiled Mar 29 2017 18:44:23 +gem5 started Mar 29 2017 18:44:38 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 53279 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/m5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5 -info: Using bootloader at address 0x10 -info: Using kernel entry physical address at 0x80008000 -info: Loading DTB file: /dist/m5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb at address 0x88000000 -info: Entering event queue @ 0. Starting simulation... -info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 -info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 -info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 -info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 -info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 -info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 -info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 -info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 -info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 -info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 -info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 -info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 -info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 -info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 -info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 -Exiting @ tick 2870988926500 because m5_exit instruction encountered +Exiting @ tick 2871012355500 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt index 24ac1035d..3c2692874 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt @@ -1,3154 +1,3156 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.870996 # Number of seconds simulated -sim_ticks 2870995800500 # Number of ticks simulated -final_tick 2870995800500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1013503 # Simulator instruction rate (inst/s) -host_op_rate 1225877 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 22160332076 # Simulator tick rate (ticks/s) -host_mem_usage 622032 # Number of bytes of host memory used -host_seconds 129.56 # Real time elapsed on the host -sim_insts 131304972 # Number of instructions simulated -sim_ops 158819278 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu0.dtb.walker 448 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 1181796 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 1294372 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 8555136 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 152212 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 573844 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 414464 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 12173424 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 1181796 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 152212 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1334008 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8754752 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory -system.physmem.bytes_written::total 8772316 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 7 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 26919 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 20744 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 133674 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2533 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 8987 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 6476 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 199358 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 136793 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory -system.physmem.num_writes::total 141184 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 156 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 45 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 411633 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 450844 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 2979850 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 22 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 53017 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 199876 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 144362 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 334 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4240140 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 411633 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 53017 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 464650 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3049378 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 6104 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3055496 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3049378 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 156 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 45 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 411633 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 456948 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 2979850 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 22 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 53017 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 199890 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 144362 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 334 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7295636 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 199358 # Number of read requests accepted -system.physmem.writeReqs 141184 # Number of write requests accepted -system.physmem.readBursts 199358 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 141184 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 12748800 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 10112 # Total number of bytes read from write queue -system.physmem.bytesWritten 8785280 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 12173424 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 8772316 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 158 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 3897 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 11937 # Per bank write bursts -system.physmem.perBankRdBursts::1 11961 # Per bank write bursts -system.physmem.perBankRdBursts::2 12063 # Per bank write bursts -system.physmem.perBankRdBursts::3 12015 # Per bank write bursts -system.physmem.perBankRdBursts::4 20362 # Per bank write bursts -system.physmem.perBankRdBursts::5 11984 # Per bank write bursts -system.physmem.perBankRdBursts::6 12067 # Per bank write bursts -system.physmem.perBankRdBursts::7 12160 # Per bank write bursts -system.physmem.perBankRdBursts::8 12406 # Per bank write bursts -system.physmem.perBankRdBursts::9 12763 # Per bank write bursts -system.physmem.perBankRdBursts::10 11654 # Per bank write bursts -system.physmem.perBankRdBursts::11 11199 # Per bank write bursts -system.physmem.perBankRdBursts::12 11763 # Per bank write bursts -system.physmem.perBankRdBursts::13 11689 # Per bank write bursts -system.physmem.perBankRdBursts::14 11766 # Per bank write bursts -system.physmem.perBankRdBursts::15 11411 # Per bank write bursts -system.physmem.perBankWrBursts::0 8587 # Per bank write bursts -system.physmem.perBankWrBursts::1 8807 # Per bank write bursts -system.physmem.perBankWrBursts::2 8988 # Per bank write bursts -system.physmem.perBankWrBursts::3 8742 # Per bank write bursts -system.physmem.perBankWrBursts::4 8269 # Per bank write bursts -system.physmem.perBankWrBursts::5 8555 # Per bank write bursts -system.physmem.perBankWrBursts::6 8883 # Per bank write bursts -system.physmem.perBankWrBursts::7 8651 # Per bank write bursts -system.physmem.perBankWrBursts::8 8881 # Per bank write bursts -system.physmem.perBankWrBursts::9 9204 # Per bank write bursts -system.physmem.perBankWrBursts::10 8442 # Per bank write bursts -system.physmem.perBankWrBursts::11 8330 # Per bank write bursts -system.physmem.perBankWrBursts::12 8611 # Per bank write bursts -system.physmem.perBankWrBursts::13 8076 # Per bank write bursts -system.physmem.perBankWrBursts::14 8388 # Per bank write bursts -system.physmem.perBankWrBursts::15 7856 # Per bank write bursts -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 86 # Number of times write queue was full causing retry -system.physmem.totGap 2870994769000 # Total gap between requests -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 9732 # Read request sizes (log2) -system.physmem.readPktSize::3 28 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 189598 # Read request sizes (log2) -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 4391 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 136793 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 136138 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 17236 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 10604 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 8747 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 7299 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 5883 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 5032 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 4260 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3698 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 128 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 84 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 51 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 24 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 8 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2554 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3487 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4394 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5386 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6479 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6593 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7546 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8490 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 8347 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 9668 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 9980 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8490 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8119 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 8411 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 9434 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7894 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7591 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 637 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 442 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 414 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 292 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 241 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 248 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 218 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 227 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 239 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 215 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 211 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 252 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 243 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 237 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 193 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 151 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 181 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 201 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 201 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 162 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 225 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 193 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 209 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 221 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 146 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 250 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 145 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 135 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 244 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 85519 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 251.803880 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 143.212865 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 307.683468 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 42851 50.11% 50.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 18042 21.10% 71.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6336 7.41% 78.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3652 4.27% 82.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2667 3.12% 86.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1677 1.96% 87.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 875 1.02% 88.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 945 1.11% 90.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8474 9.91% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 85519 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6795 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 29.315232 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 564.685462 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6793 99.97% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-4095 1 0.01% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::45056-47103 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6795 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6795 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.201619 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.574221 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 13.473858 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5740 84.47% 84.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 356 5.24% 89.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 65 0.96% 90.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 46 0.68% 91.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 271 3.99% 95.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 21 0.31% 95.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 19 0.28% 95.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 18 0.26% 96.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 11 0.16% 96.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 7 0.10% 96.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 2 0.03% 96.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 7 0.10% 96.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 153 2.25% 98.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 7 0.10% 98.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 9 0.13% 99.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 5 0.07% 99.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 7 0.10% 99.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 2 0.03% 99.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 1 0.01% 99.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 3 0.04% 99.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 3 0.04% 99.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 1 0.01% 99.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 4 0.06% 99.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 2 0.03% 99.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 3 0.04% 99.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 2 0.03% 99.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 10 0.15% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 1 0.01% 99.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 3 0.04% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 2 0.03% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 2 0.03% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 1 0.01% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 1 0.01% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 3 0.04% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 2 0.03% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 2 0.03% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-195 2 0.03% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::196-199 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6795 # Writes before turning the bus around for reads -system.physmem.totQLat 9377591483 # Total ticks spent queuing -system.physmem.totMemAccLat 13112591483 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 996000000 # Total ticks spent in databus transfers -system.physmem.avgQLat 47076.26 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 65826.26 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 4.44 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.06 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 4.24 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.06 # Average system write bandwidth in MiByte/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.06 # Data bus utilization in percentage -system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.87 # Average write queue length when enqueuing -system.physmem.readRowHits 166242 # Number of row buffer hits during reads -system.physmem.writeRowHits 84708 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.45 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 61.70 # Row buffer hit rate for writes -system.physmem.avgGap 8430662.79 # Average gap between requests -system.physmem.pageHitRate 74.58 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 309183420 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 164331090 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 746479860 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 362696040 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 6139024320.000001 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 5630456580 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 369226560 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 11487380430 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 9121751040 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 675280298985 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 709613489745 # Total energy per rank (pJ) -system.physmem_0.averagePower 247.166328 # Core power per rank (mW) -system.physmem_0.totalIdleTime 2857680941179 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 688127950 # Time in different power states -system.physmem_0.memoryStateTime::REF 2609960000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 2808734663750 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 23754548081 # Time in different power states -system.physmem_0.memoryStateTime::ACT 10016707371 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 25191793348 # Time in different power states -system.physmem_1.actEnergy 301429380 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 160213515 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 675808140 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 353853360 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 6242283840.000001 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 5675698050 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 365488800 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 11403357870 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 9537644640 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 675067441050 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 709786212765 # Total energy per rank (pJ) -system.physmem_1.averagePower 247.226489 # Core power per rank (mW) -system.physmem_1.totalIdleTime 2857340478310 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 678311229 # Time in different power states -system.physmem_1.memoryStateTime::REF 2653946000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 2807745675250 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 24837614861 # Time in different power states -system.physmem_1.memoryStateTime::ACT 10072973461 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 25007279699 # Time in different power states -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states -system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 7 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::cpu1.inst 17 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 24 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 7 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu1.inst 17 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 24 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 7 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu1.inst 17 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 24 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states -system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). -system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). -system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. -system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. -system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states -system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states -system.cpu0.dtb.walker.walks 7823 # Table walker walks requested -system.cpu0.dtb.walker.walksShort 7823 # Table walker walks initiated with short descriptors -system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 1468 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 6355 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walkWaitTime::samples 7823 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 7823 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 7823 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 6429 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 12550.163322 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 11491.858959 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 6296.322703 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-16383 5867 91.26% 91.26% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::16384-32767 463 7.20% 98.46% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::32768-49151 86 1.34% 99.80% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::49152-65535 8 0.12% 99.92% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::81920-98303 1 0.02% 99.94% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::98304-114687 3 0.05% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::212992-229375 1 0.02% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 6429 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 1181300000 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0 1181300000 100.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 1181300000 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 5000 77.77% 77.77% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 1429 22.23% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 6429 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 7823 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 7823 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6429 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6429 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 14252 # Table walker requests started/completed, data/inst -system.cpu0.dtb.inst_hits 0 # ITB inst hits -system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 25081905 # DTB read hits -system.cpu0.dtb.read_misses 6707 # DTB read misses -system.cpu0.dtb.write_hits 18693539 # DTB write hits -system.cpu0.dtb.write_misses 1116 # DTB write misses -system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed -system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3387 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 1738 # Number of TLB faults due to prefetch -system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 282 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 25088612 # DTB read accesses -system.cpu0.dtb.write_accesses 18694655 # DTB write accesses -system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 43775444 # DTB hits -system.cpu0.dtb.misses 7823 # DTB misses -system.cpu0.dtb.accesses 43783267 # DTB accesses -system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states -system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states -system.cpu0.itb.walker.walks 3349 # Table walker walks requested -system.cpu0.itb.walker.walksShort 3349 # Table walker walks initiated with short descriptors -system.cpu0.itb.walker.walksShortTerminationLevel::Level1 299 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3050 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walkWaitTime::samples 3349 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 3349 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 3349 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 2333 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 12879.339906 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 12002.998619 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 5903.446394 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-8191 363 15.56% 15.56% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::8192-16383 1682 72.10% 87.66% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::16384-24575 212 9.09% 96.74% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::24576-32767 37 1.59% 98.33% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::32768-40959 36 1.54% 99.87% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::49152-57343 1 0.04% 99.91% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::98304-106495 1 0.04% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::122880-131071 1 0.04% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 2333 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples 1180899500 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 1180899500 100.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 1180899500 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 2034 87.18% 87.18% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::1M 299 12.82% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 2333 # Table walker page sizes translated -system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3349 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3349 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2333 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2333 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 5682 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 118659015 # ITB inst hits -system.cpu0.itb.inst_misses 3349 # ITB inst misses -system.cpu0.itb.read_hits 0 # DTB read hits -system.cpu0.itb.read_misses 0 # DTB read misses -system.cpu0.itb.write_hits 0 # DTB write hits -system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed -system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2087 # Number of entries that have been flushed from TLB -system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu0.itb.read_accesses 0 # DTB read accesses -system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 118662364 # ITB inst accesses -system.cpu0.itb.hits 118659015 # DTB hits -system.cpu0.itb.misses 3349 # DTB misses -system.cpu0.itb.accesses 118662364 # DTB accesses -system.cpu0.numPwrStateTransitions 3724 # Number of power state transitions -system.cpu0.pwrStateClkGateDist::samples 1862 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::mean 1466902343.272825 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::stdev 23730658455.603134 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::underflows 1082 58.11% 58.11% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1000-5e+10 775 41.62% 99.73% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.05% 99.79% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 4 0.21% 100.00% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::max_value 499963373360 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::total 1862 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateResidencyTicks::ON 139623637326 # Cumulative time (in ticks) in various power states -system.cpu0.pwrStateResidencyTicks::CLK_GATED 2731372163174 # Cumulative time (in ticks) in various power states -system.cpu0.numCycles 5741991601 # number of cpu cycles simulated -system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 1862 # number of quiesce instructions executed -system.cpu0.committedInsts 114996919 # Number of instructions committed -system.cpu0.committedOps 138962993 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 122999157 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 9755 # Number of float alu accesses -system.cpu0.num_func_calls 12659267 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 15643522 # number of instructions that are conditional controls -system.cpu0.num_int_insts 122999157 # number of integer instructions -system.cpu0.num_fp_insts 9755 # number of float instructions -system.cpu0.num_int_register_reads 226444380 # number of times the integer registers were read -system.cpu0.num_int_register_writes 85465434 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 7495 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 2264 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 503448381 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 52091583 # number of times the CC registers were written -system.cpu0.num_mem_refs 44908198 # number of memory refs -system.cpu0.num_load_insts 25331105 # Number of load instructions -system.cpu0.num_store_insts 19577093 # Number of store instructions -system.cpu0.num_idle_cycles 5462744326.346097 # Number of idle cycles -system.cpu0.num_busy_cycles 279247274.653903 # Number of busy cycles -system.cpu0.not_idle_fraction 0.048632 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.951368 # Percentage of idle cycles -system.cpu0.Branches 29039529 # Number of branches fetched -system.cpu0.op_class::No_OpClass 2273 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 97695313 68.45% 68.45% # Class of executed instruction -system.cpu0.op_class::IntMult 108459 0.08% 68.53% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::FloatMultAcc 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::FloatMisc 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 7991 0.01% 68.53% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.53% # Class of executed instruction -system.cpu0.op_class::MemRead 25328849 17.75% 86.28% # Class of executed instruction -system.cpu0.op_class::MemWrite 19569598 13.71% 99.99% # Class of executed instruction -system.cpu0.op_class::FloatMemRead 2256 0.00% 99.99% # Class of executed instruction -system.cpu0.op_class::FloatMemWrite 7495 0.01% 100.00% # Class of executed instruction -system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 142722234 # Class of executed instruction -system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.tags.replacements 690121 # number of replacements -system.cpu0.dcache.tags.tagsinuse 498.373175 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 42907120 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 690633 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 62.127237 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 1207348000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 498.373175 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.973385 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.973385 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 101 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 323 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 88 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 88185256 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 88185256 # Number of data accesses -system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.ReadReq_hits::cpu0.data 23824030 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 23824030 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 17964029 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 17964029 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 318863 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 318863 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 364525 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 364525 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 361510 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 361510 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 41788059 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 41788059 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 42106922 # number of overall hits -system.cpu0.dcache.overall_hits::total 42106922 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 394827 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 394827 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 324085 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 324085 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 127008 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 127008 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21435 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 21435 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 19554 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 19554 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 718912 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 718912 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 845920 # number of overall misses -system.cpu0.dcache.overall_misses::total 845920 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5517390500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 5517390500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 6298218500 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 6298218500 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 337010500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 337010500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 458737500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 458737500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1113000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1113000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 11815609000 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 11815609000 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 11815609000 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 11815609000 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 24218857 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 24218857 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 18288114 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 18288114 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 445871 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 445871 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 385960 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 385960 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381064 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 381064 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 42506971 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 42506971 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 42952842 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 42952842 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.016302 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.016302 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.017721 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.017721 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.284854 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.284854 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.055537 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.055537 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.051314 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051314 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.016913 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.016913 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.019694 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.019694 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13974.197560 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 13974.197560 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 19433.847602 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 19433.847602 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15722.439935 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15722.439935 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23460.033753 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23460.033753 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency -system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16435.403777 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 16435.403777 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 13967.761727 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 13967.761727 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 690121 # number of writebacks -system.cpu0.dcache.writebacks::total 690121 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 25200 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 25200 # number of ReadReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 15056 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 15056 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 25200 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 25200 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 25200 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 25200 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 369627 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 369627 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 324085 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 324085 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 100010 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 100010 # number of SoftPFReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6379 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6379 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 19554 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 19554 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 693712 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 693712 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 793722 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 793722 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 31768 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31768 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 28446 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 28446 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 60214 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 60214 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4739955500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4739955500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5974133500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5974133500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1650418500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1650418500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 101003000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 101003000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 439215500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 439215500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1081000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1081000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10714089000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 10714089000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 12364507500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 12364507500 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6631169500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6631169500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6631169500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6631169500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.015262 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.015262 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.017721 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017721 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.224303 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.224303 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016528 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016528 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051314 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051314 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016320 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.016320 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.018479 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.018479 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12823.618134 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12823.618134 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 18433.847602 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 18433.847602 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16502.534747 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16502.534747 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15833.672989 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15833.672989 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22461.670246 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22461.670246 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 15444.577865 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15444.577865 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15577.881802 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15577.881802 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208737.392974 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208737.392974 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 110126.706414 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 110126.706414 # average overall mshr uncacheable latency -system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states -system.cpu0.icache.tags.replacements 1095423 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.436912 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 117563071 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1095935 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 107.271938 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 14178985000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.436912 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998900 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.998900 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 85 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 213 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 214 # Occupied blocks per task id -system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 238413974 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 238413974 # Number of data accesses -system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states -system.cpu0.icache.ReadReq_hits::cpu0.inst 117563071 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 117563071 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 117563071 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 117563071 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 117563071 # number of overall hits -system.cpu0.icache.overall_hits::total 117563071 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 1095944 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1095944 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 1095944 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1095944 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 1095944 # number of overall misses -system.cpu0.icache.overall_misses::total 1095944 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 11846969000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 11846969000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 11846969000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 11846969000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 11846969000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 11846969000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 118659015 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 118659015 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 118659015 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 118659015 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 118659015 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 118659015 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.009236 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.009236 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.009236 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.009236 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.009236 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.009236 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10809.830612 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 10809.830612 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10809.830612 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 10809.830612 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10809.830612 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 10809.830612 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.writebacks::writebacks 1095423 # number of writebacks -system.cpu0.icache.writebacks::total 1095423 # number of writebacks -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1095944 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 1095944 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 1095944 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 1095944 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 1095944 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 1095944 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 9022 # number of ReadReq MSHR uncacheable -system.cpu0.icache.ReadReq_mshr_uncacheable::total 9022 # number of ReadReq MSHR uncacheable -system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 9022 # number of overall MSHR uncacheable misses -system.cpu0.icache.overall_mshr_uncacheable_misses::total 9022 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 11298997000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 11298997000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 11298997000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 11298997000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 11298997000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 11298997000 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 863305500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 863305500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 863305500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 863305500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.009236 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009236 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.009236 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.009236 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.009236 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.009236 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10309.830612 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10309.830612 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10309.830612 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 10309.830612 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10309.830612 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 10309.830612 # average overall mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 95688.927067 # average ReadReq mshr uncacheable latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 95688.927067 # average ReadReq mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 95688.927067 # average overall mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 95688.927067 # average overall mshr uncacheable latency -system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.prefetcher.num_hwpf_issued 1843455 # number of hwpf issued -system.cpu0.l2cache.prefetcher.pfIdentified 1843489 # number of prefetch candidates identified -system.cpu0.l2cache.prefetcher.pfBufferHit 30 # number of redundant prefetches already in prefetch queue -system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped -system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu0.l2cache.prefetcher.pfSpanPage 237167 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.tags.replacements 260392 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 15616.554479 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 1673878 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 276011 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 6.064534 # Average number of references to valid blocks. -system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 14458.510897 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 1.380966 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.135465 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1156.527151 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.882477 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000084 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000008 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.070589 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.953159 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 316 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 3 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15300 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 10 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 27 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 129 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 150 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 2 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 176 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 827 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 6046 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 6216 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2035 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.019287 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000183 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.933838 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 60952812 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 60952812 # Number of data accesses -system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 9949 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 4513 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 14462 # number of ReadReq hits -system.cpu0.l2cache.WritebackDirty_hits::writebacks 474087 # number of WritebackDirty hits -system.cpu0.l2cache.WritebackDirty_hits::total 474087 # number of WritebackDirty hits -system.cpu0.l2cache.WritebackClean_hits::writebacks 1283679 # number of WritebackClean hits -system.cpu0.l2cache.WritebackClean_hits::total 1283679 # number of WritebackClean hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.data 226501 # number of ReadExReq hits -system.cpu0.l2cache.ReadExReq_hits::total 226501 # number of ReadExReq hits -system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1033387 # number of ReadCleanReq hits -system.cpu0.l2cache.ReadCleanReq_hits::total 1033387 # number of ReadCleanReq hits -system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 374984 # number of ReadSharedReq hits -system.cpu0.l2cache.ReadSharedReq_hits::total 374984 # number of ReadSharedReq hits -system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 9949 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 4513 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 1033387 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.data 601485 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 1649334 # number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 9949 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 4513 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 1033387 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.data 601485 # number of overall hits -system.cpu0.l2cache.overall_hits::total 1649334 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 333 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 154 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 487 # number of ReadReq misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 54609 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 54609 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 19552 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::total 19552 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 2 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::total 2 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.ReadExReq_misses::cpu0.data 42975 # number of ReadExReq misses -system.cpu0.l2cache.ReadExReq_misses::total 42975 # number of ReadExReq misses -system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 62557 # number of ReadCleanReq misses -system.cpu0.l2cache.ReadCleanReq_misses::total 62557 # number of ReadCleanReq misses -system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 101032 # number of ReadSharedReq misses -system.cpu0.l2cache.ReadSharedReq_misses::total 101032 # number of ReadSharedReq misses -system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 333 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.itb.walker 154 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.inst 62557 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.data 144007 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::total 207051 # number of demand (read+write) misses -system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 333 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.itb.walker 154 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.inst 62557 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.data 144007 # number of overall misses -system.cpu0.l2cache.overall_misses::total 207051 # number of overall misses -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 8868000 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 3618500 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::total 12486500 # number of ReadReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 29801000 # number of UpgradeReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::total 29801000 # number of UpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 8716000 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 8716000 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 1032499 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 1032499 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 2749345500 # number of ReadExReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::total 2749345500 # number of ReadExReq miss cycles -system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 3431495000 # number of ReadCleanReq miss cycles -system.cpu0.l2cache.ReadCleanReq_miss_latency::total 3431495000 # number of ReadCleanReq miss cycles -system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 3333037000 # number of ReadSharedReq miss cycles -system.cpu0.l2cache.ReadSharedReq_miss_latency::total 3333037000 # number of ReadSharedReq miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 8868000 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 3618500 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.inst 3431495000 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.data 6082382500 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::total 9526364000 # number of demand (read+write) miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 8868000 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 3618500 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.inst 3431495000 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.data 6082382500 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::total 9526364000 # number of overall miss cycles -system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 10282 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 4667 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::total 14949 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.WritebackDirty_accesses::writebacks 474087 # number of WritebackDirty accesses(hits+misses) -system.cpu0.l2cache.WritebackDirty_accesses::total 474087 # number of WritebackDirty accesses(hits+misses) -system.cpu0.l2cache.WritebackClean_accesses::writebacks 1283679 # number of WritebackClean accesses(hits+misses) -system.cpu0.l2cache.WritebackClean_accesses::total 1283679 # number of WritebackClean accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 54609 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::total 54609 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 19552 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::total 19552 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 2 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 2 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 269476 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::total 269476 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 1095944 # number of ReadCleanReq accesses(hits+misses) -system.cpu0.l2cache.ReadCleanReq_accesses::total 1095944 # number of ReadCleanReq accesses(hits+misses) -system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 476016 # number of ReadSharedReq accesses(hits+misses) -system.cpu0.l2cache.ReadSharedReq_accesses::total 476016 # number of ReadSharedReq accesses(hits+misses) -system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 10282 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 4667 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.inst 1095944 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.data 745492 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::total 1856385 # number of demand (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 10282 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 4667 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.inst 1095944 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.data 745492 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::total 1856385 # number of overall (read+write) accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.032387 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.032998 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::total 0.032577 # miss rate for ReadReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 1 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.159476 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::total 0.159476 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.057080 # miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.057080 # miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.212245 # miss rate for ReadSharedReq accesses -system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.212245 # miss rate for ReadSharedReq accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.032387 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.032998 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.057080 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.193170 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::total 0.111535 # miss rate for demand accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.032387 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.032998 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.057080 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.193170 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::total 0.111535 # miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 26630.630631 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 23496.753247 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::total 25639.630390 # average ReadReq miss latency -system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 545.715908 # average UpgradeReq miss latency -system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 545.715908 # average UpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 445.785597 # average SCUpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 445.785597 # average SCUpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 516249.500000 # average SCUpgradeFailReq miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 516249.500000 # average SCUpgradeFailReq miss latency -system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 63975.462478 # average ReadExReq miss latency -system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 63975.462478 # average ReadExReq miss latency -system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 54853.893249 # average ReadCleanReq miss latency -system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 54853.893249 # average ReadCleanReq miss latency -system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 32989.914087 # average ReadSharedReq miss latency -system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 32989.914087 # average ReadSharedReq miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 26630.630631 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 23496.753247 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 54853.893249 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 42236.714188 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::total 46009.746391 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 26630.630631 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 23496.753247 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 54853.893249 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 42236.714188 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::total 46009.746391 # average overall miss latency -system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.l2cache.unused_prefetches 10486 # number of HardPF blocks evicted w/o reference -system.cpu0.l2cache.writebacks::writebacks 227470 # number of writebacks -system.cpu0.l2cache.writebacks::total 227470 # number of writebacks -system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 1575 # number of ReadExReq MSHR hits -system.cpu0.l2cache.ReadExReq_mshr_hits::total 1575 # number of ReadExReq MSHR hits -system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 30 # number of ReadSharedReq MSHR hits -system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 30 # number of ReadSharedReq MSHR hits -system.cpu0.l2cache.demand_mshr_hits::cpu0.data 1605 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.demand_mshr_hits::total 1605 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.overall_mshr_hits::cpu0.data 1605 # number of overall MSHR hits -system.cpu0.l2cache.overall_mshr_hits::total 1605 # number of overall MSHR hits -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 333 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 154 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::total 487 # number of ReadReq MSHR misses -system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 261736 # number of HardPFReq MSHR misses -system.cpu0.l2cache.HardPFReq_mshr_misses::total 261736 # number of HardPFReq MSHR misses -system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 54609 # number of UpgradeReq MSHR misses -system.cpu0.l2cache.UpgradeReq_mshr_misses::total 54609 # number of UpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 19552 # number of SCUpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 19552 # number of SCUpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 2 # number of SCUpgradeFailReq MSHR misses -system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 2 # number of SCUpgradeFailReq MSHR misses -system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 41400 # number of ReadExReq MSHR misses -system.cpu0.l2cache.ReadExReq_mshr_misses::total 41400 # number of ReadExReq MSHR misses -system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 62557 # number of ReadCleanReq MSHR misses -system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 62557 # number of ReadCleanReq MSHR misses -system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 101002 # number of ReadSharedReq MSHR misses -system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 101002 # number of ReadSharedReq MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 333 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 154 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 62557 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.data 142402 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::total 205446 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 333 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 154 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 62557 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.data 142402 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 261736 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::total 467182 # number of overall MSHR misses -system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 9022 # number of ReadReq MSHR uncacheable -system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 31768 # number of ReadReq MSHR uncacheable -system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 40790 # number of ReadReq MSHR uncacheable -system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 28446 # number of WriteReq MSHR uncacheable -system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 28446 # number of WriteReq MSHR uncacheable -system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 9022 # number of overall MSHR uncacheable misses -system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 60214 # number of overall MSHR uncacheable misses -system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 69236 # number of overall MSHR uncacheable misses -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 6870000 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 2694500 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 9564500 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 16748653122 # number of HardPFReq MSHR miss cycles -system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 16748653122 # number of HardPFReq MSHR miss cycles -system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 936375500 # number of UpgradeReq MSHR miss cycles -system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 936375500 # number of UpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 292739000 # number of SCUpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 292739000 # number of SCUpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 840499 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 840499 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 2221757000 # number of ReadExReq MSHR miss cycles -system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 2221757000 # number of ReadExReq MSHR miss cycles -system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 3056153000 # number of ReadCleanReq MSHR miss cycles -system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 3056153000 # number of ReadCleanReq MSHR miss cycles -system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 2721461500 # number of ReadSharedReq MSHR miss cycles -system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 2721461500 # number of ReadSharedReq MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 6870000 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 2694500 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 3056153000 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 4943218500 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::total 8008936000 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 6870000 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 2694500 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 3056153000 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 4943218500 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 16748653122 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::total 24757589122 # number of overall MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 795640500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 6376615000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 7172255500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 795640500 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 6376615000 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 7172255500 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.032387 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.032998 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.032577 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses -system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.153631 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.153631 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.057080 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.057080 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.212182 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.212182 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.032387 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.032998 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.057080 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.191017 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.110670 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.032387 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.032998 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.057080 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.191017 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.251662 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 20630.630631 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17496.753247 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 19639.630390 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 63990.636068 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 63990.636068 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17146.908019 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17146.908019 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14972.330196 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14972.330196 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 420249.500000 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 420249.500000 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 53665.628019 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 53665.628019 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 48853.893249 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 48853.893249 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 26944.629809 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 26944.629809 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 20630.630631 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17496.753247 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 48853.893249 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 34713.125518 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 38983.168326 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 20630.630631 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17496.753247 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 48853.893249 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 34713.125518 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 63990.636068 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 52993.456773 # average overall mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 88188.927067 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200724.471166 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 175833.672469 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 88188.927067 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 105899.209486 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 103591.419204 # average overall mshr uncacheable latency -system.cpu0.toL2Bus.snoop_filter.tot_requests 3713043 # Total number of requests made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_requests 1871637 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 27791 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.snoop_filter.tot_snoops 210694 # Total number of snoops made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 209047 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 1647 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states -system.cpu0.toL2Bus.trans_dist::ReadReq 61395 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 1681090 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 28446 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 28446 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackDirty 701864 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackClean 1311457 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::CleanEvict 80209 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 307976 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 86960 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 41708 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 111633 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 49 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 79 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 288540 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 285048 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1095944 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadSharedReq 562349 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateReq 3227 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateResp 12 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3305355 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2550756 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 11066 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 24460 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 5891637 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 140283576 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 96129280 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 18668 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 41128 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 236472652 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 885693 # Total snoops (count) -system.cpu0.toL2Bus.snoopTraffic 18656572 # Total snoop traffic (bytes) -system.cpu0.toL2Bus.snoop_fanout::samples 2784580 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 0.090516 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.288973 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::0 2534179 91.01% 91.01% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 248754 8.93% 99.94% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 1647 0.06% 100.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 2784580 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 3695245998 # Layer occupancy (ticks) -system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 113887546 # Layer occupancy (ticks) -system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 1652938000 # Layer occupancy (ticks) -system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 1201348488 # Layer occupancy (ticks) -system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 6399000 # Layer occupancy (ticks) -system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 14180994 # Layer occupancy (ticks) -system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states -system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states -system.cpu1.dtb.walker.walks 3368 # Table walker walks requested -system.cpu1.dtb.walker.walksShort 3368 # Table walker walks initiated with short descriptors -system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 669 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 2699 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walkWaitTime::samples 3368 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 3368 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 3368 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 2598 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 12496.920708 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 11544.208502 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 5669.313441 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-8191 611 23.52% 23.52% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::8192-16383 1671 64.32% 87.84% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::16384-24575 230 8.85% 96.69% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::24576-32767 69 2.66% 99.35% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::32768-40959 10 0.38% 99.73% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::40960-49151 3 0.12% 99.85% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::49152-57343 2 0.08% 99.92% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::57344-65535 1 0.04% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::98304-106495 1 0.04% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 2598 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples -1937787828 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 -1937787828 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total -1937787828 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 1937 74.56% 74.56% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::1M 661 25.44% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 2598 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 3368 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 3368 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2598 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2598 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 5966 # Table walker requests started/completed, data/inst -system.cpu1.dtb.inst_hits 0 # ITB inst hits -system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 3952331 # DTB read hits -system.cpu1.dtb.read_misses 2852 # DTB read misses -system.cpu1.dtb.write_hits 3427850 # DTB write hits -system.cpu1.dtb.write_misses 516 # DTB write misses -system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed -system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1975 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 341 # Number of TLB faults due to prefetch -system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 163 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 3955183 # DTB read accesses -system.cpu1.dtb.write_accesses 3428366 # DTB write accesses -system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 7380181 # DTB hits -system.cpu1.dtb.misses 3368 # DTB misses -system.cpu1.dtb.accesses 7383549 # DTB accesses -system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states -system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states -system.cpu1.itb.walker.walks 1746 # Table walker walks requested -system.cpu1.itb.walker.walksShort 1746 # Table walker walks initiated with short descriptors -system.cpu1.itb.walker.walksShortTerminationLevel::Level1 168 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksShortTerminationLevel::Level2 1578 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 1746 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 1746 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 1746 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 1107 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 12746.160795 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 11849.716682 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 5651.710937 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::4096-8191 170 15.36% 15.36% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::8192-12287 628 56.73% 72.09% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::12288-16383 162 14.63% 86.72% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::16384-20479 49 4.43% 91.15% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::20480-24575 38 3.43% 94.58% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::24576-28671 32 2.89% 97.47% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::28672-32767 17 1.54% 99.01% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::32768-36863 4 0.36% 99.37% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::36864-40959 1 0.09% 99.46% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::40960-45055 4 0.36% 99.82% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::45056-49151 1 0.09% 99.91% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::49152-53247 1 0.09% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 1107 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples -1938367828 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 -1938367828 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total -1938367828 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 939 84.82% 84.82% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::1M 168 15.18% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 1107 # Table walker page sizes translated -system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 1746 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 1746 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1107 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1107 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 2853 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 16663369 # ITB inst hits -system.cpu1.itb.inst_misses 1746 # ITB inst misses -system.cpu1.itb.read_hits 0 # DTB read hits -system.cpu1.itb.read_misses 0 # DTB read misses -system.cpu1.itb.write_hits 0 # DTB write hits -system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed -system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1084 # Number of entries that have been flushed from TLB -system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu1.itb.read_accesses 0 # DTB read accesses -system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 16665115 # ITB inst accesses -system.cpu1.itb.hits 16663369 # DTB hits -system.cpu1.itb.misses 1746 # DTB misses -system.cpu1.itb.accesses 16665115 # DTB accesses -system.cpu1.numPwrStateTransitions 5435 # Number of power state transitions -system.cpu1.pwrStateClkGateDist::samples 2718 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::mean 1046549937.704562 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::stdev 25917662670.452511 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::underflows 1945 71.56% 71.56% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1000-5e+10 767 28.22% 99.78% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::5e+10-1e+11 2 0.07% 99.85% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 1 0.04% 99.89% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::5e+11-5.5e+11 1 0.04% 99.93% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::8e+11-8.5e+11 1 0.04% 99.96% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::9e+11-9.5e+11 1 0.04% 100.00% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::max_value 929980418584 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::total 2718 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateResidencyTicks::ON 26473069819 # Cumulative time (in ticks) in various power states -system.cpu1.pwrStateResidencyTicks::CLK_GATED 2844522730681 # Cumulative time (in ticks) in various power states -system.cpu1.numCycles 5741059879 # number of cpu cycles simulated -system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2718 # number of quiesce instructions executed -system.cpu1.committedInsts 16308053 # Number of instructions committed -system.cpu1.committedOps 19856285 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 17888019 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 1792 # Number of float alu accesses -system.cpu1.num_func_calls 1028859 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1844250 # number of instructions that are conditional controls -system.cpu1.num_int_insts 17888019 # number of integer instructions -system.cpu1.num_fp_insts 1792 # number of float instructions -system.cpu1.num_int_register_reads 32444258 # number of times the integer registers were read -system.cpu1.num_int_register_writes 12537466 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 1276 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 516 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 72543530 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 6508973 # number of times the CC registers were written -system.cpu1.num_mem_refs 7613771 # number of memory refs -system.cpu1.num_load_insts 4063495 # Number of load instructions -system.cpu1.num_store_insts 3550276 # Number of store instructions -system.cpu1.num_idle_cycles 5688122330.646462 # Number of idle cycles -system.cpu1.num_busy_cycles 52937548.353538 # Number of busy cycles -system.cpu1.not_idle_fraction 0.009221 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.990779 # Percentage of idle cycles -system.cpu1.Branches 2952894 # Number of branches fetched -system.cpu1.op_class::No_OpClass 66 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 12563541 62.17% 62.17% # Class of executed instruction -system.cpu1.op_class::IntMult 26310 0.13% 62.30% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 62.30% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 62.30% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 62.30% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 62.30% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 62.30% # Class of executed instruction -system.cpu1.op_class::FloatMultAcc 0 0.00% 62.30% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 62.30% # Class of executed instruction -system.cpu1.op_class::FloatMisc 0 0.00% 62.30% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 62.30% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 62.30% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 62.30% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 62.30% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 62.30% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 62.30% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 62.30% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 62.30% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 62.30% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 62.30% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 62.30% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 62.30% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 62.30% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 62.30% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 62.30% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 62.30% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 62.30% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 3279 0.02% 62.32% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 62.32% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 62.32% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 62.32% # Class of executed instruction -system.cpu1.op_class::MemRead 4062979 20.11% 82.43% # Class of executed instruction -system.cpu1.op_class::MemWrite 3549000 17.56% 99.99% # Class of executed instruction -system.cpu1.op_class::FloatMemRead 516 0.00% 99.99% # Class of executed instruction -system.cpu1.op_class::FloatMemWrite 1276 0.01% 100.00% # Class of executed instruction -system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 20206967 # Class of executed instruction -system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.tags.replacements 187241 # number of replacements -system.cpu1.dcache.tags.tagsinuse 470.165247 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 7113602 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 187604 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 37.918179 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 128171950500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 470.165247 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.918291 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.918291 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 363 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 290 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::3 73 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.708984 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 14979376 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 14979376 # Number of data accesses -system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.ReadReq_hits::cpu1.data 3640649 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 3640649 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 3239316 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 3239316 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 49005 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 49005 # number of SoftPFReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 78940 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 78940 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 70837 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 70837 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 6879965 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 6879965 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 6928970 # number of overall hits -system.cpu1.dcache.overall_hits::total 6928970 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 133578 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 133578 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 91863 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 91863 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30193 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 30193 # number of SoftPFReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 16916 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 16916 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23207 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 23207 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 225441 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 225441 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 255634 # number of overall misses -system.cpu1.dcache.overall_misses::total 255634 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2045952000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 2045952000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2531885000 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 2531885000 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 322352500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 322352500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 544400500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 544400500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 2036500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 2036500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 4577837000 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 4577837000 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 4577837000 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 4577837000 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 3774227 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 3774227 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 3331179 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 3331179 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 79198 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 79198 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 95856 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 95856 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 94044 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 94044 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 7105406 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 7105406 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 7184604 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 7184604 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.035392 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.035392 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.027577 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.027577 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.381234 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.381234 # miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.176473 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.176473 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.246767 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.246767 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.031728 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.031728 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.035581 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.035581 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15316.534160 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 15316.534160 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 27561.531846 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 27561.531846 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19056.071175 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19056.071175 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23458.460809 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23458.460809 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency -system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20306.142184 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 20306.142184 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17907.778308 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 17907.778308 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.dcache.writebacks::writebacks 187241 # number of writebacks -system.cpu1.dcache.writebacks::total 187241 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 248 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 248 # number of ReadReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 11947 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 11947 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 248 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 248 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 248 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 248 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 133330 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 133330 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 91863 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 91863 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 29503 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 29503 # number of SoftPFReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4969 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4969 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23207 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 23207 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 225193 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 225193 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 254696 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 254696 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 3077 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.ReadReq_mshr_uncacheable::total 3077 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2432 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2432 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 5509 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 5509 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1901282500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1901282500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2440022000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2440022000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 505317500 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 505317500 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 91175500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 91175500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 521240500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 521240500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1989500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1989500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4341304500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 4341304500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4846622000 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 4846622000 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 442663500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 442663500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 442663500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 442663500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035326 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035326 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027577 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027577 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.372522 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.372522 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.051838 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.051838 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.246767 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.246767 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031693 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.031693 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035450 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.035450 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14259.975249 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14259.975249 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26561.531846 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 26561.531846 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17127.664983 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17127.664983 # average SoftPFReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 18348.862950 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 18348.862950 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22460.486060 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22460.486060 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19278.150298 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19278.150298 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19029.046393 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19029.046393 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 143862.040949 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 143862.040949 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 80352.786350 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 80352.786350 # average overall mshr uncacheable latency -system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states -system.cpu1.icache.tags.replacements 503470 # number of replacements -system.cpu1.icache.tags.tagsinuse 498.455555 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 16159382 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 503982 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 32.063411 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 85409649000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.455555 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.973546 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.973546 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 390 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::3 118 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::4 4 # Occupied blocks per task id -system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 33830710 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 33830710 # Number of data accesses -system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states -system.cpu1.icache.ReadReq_hits::cpu1.inst 16159382 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 16159382 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 16159382 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 16159382 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 16159382 # number of overall hits -system.cpu1.icache.overall_hits::total 16159382 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 503982 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 503982 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 503982 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 503982 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 503982 # number of overall misses -system.cpu1.icache.overall_misses::total 503982 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4760681000 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 4760681000 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 4760681000 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 4760681000 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 4760681000 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 4760681000 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 16663364 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 16663364 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 16663364 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 16663364 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 16663364 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 16663364 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.030245 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.030245 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.030245 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.030245 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.030245 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.030245 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9446.132997 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 9446.132997 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9446.132997 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 9446.132997 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9446.132997 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 9446.132997 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.icache.writebacks::writebacks 503470 # number of writebacks -system.cpu1.icache.writebacks::total 503470 # number of writebacks -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 503982 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 503982 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 503982 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 503982 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 503982 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 503982 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 177 # number of ReadReq MSHR uncacheable -system.cpu1.icache.ReadReq_mshr_uncacheable::total 177 # number of ReadReq MSHR uncacheable -system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 177 # number of overall MSHR uncacheable misses -system.cpu1.icache.overall_mshr_uncacheable_misses::total 177 # number of overall MSHR uncacheable misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4508690000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 4508690000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4508690000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 4508690000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4508690000 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 4508690000 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 17068500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 17068500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 17068500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 17068500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.030245 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.030245 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.030245 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.030245 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.030245 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.030245 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8946.132997 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8946.132997 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8946.132997 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 8946.132997 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8946.132997 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 8946.132997 # average overall mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 96432.203390 # average ReadReq mshr uncacheable latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 96432.203390 # average ReadReq mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 96432.203390 # average overall mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 96432.203390 # average overall mshr uncacheable latency -system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.prefetcher.num_hwpf_issued 202393 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 202393 # number of prefetch candidates identified -system.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue -system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped -system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 60767 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.tags.replacements 44084 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 14674.344516 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 603056 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 58488 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 10.310765 # Average number of references to valid blocks. -system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 14288.601821 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 2.272921 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.058859 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 381.410915 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.872107 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000139 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000126 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.023279 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.895651 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 311 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14077 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 5 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 14 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 292 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 4 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 12 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 892 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 2699 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 10486 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.018982 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.000977 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.859192 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 24261935 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 24261935 # Number of data accesses -system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3748 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1963 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 5711 # number of ReadReq hits -system.cpu1.l2cache.WritebackDirty_hits::writebacks 114339 # number of WritebackDirty hits -system.cpu1.l2cache.WritebackDirty_hits::total 114339 # number of WritebackDirty hits -system.cpu1.l2cache.WritebackClean_hits::writebacks 565289 # number of WritebackClean hits -system.cpu1.l2cache.WritebackClean_hits::total 565289 # number of WritebackClean hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 27869 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 27869 # number of ReadExReq hits -system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 482614 # number of ReadCleanReq hits -system.cpu1.l2cache.ReadCleanReq_hits::total 482614 # number of ReadCleanReq hits -system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 98302 # number of ReadSharedReq hits -system.cpu1.l2cache.ReadSharedReq_hits::total 98302 # number of ReadSharedReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 3748 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 1963 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 482614 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.data 126171 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 614496 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 3748 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 1963 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 482614 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 126171 # number of overall hits -system.cpu1.l2cache.overall_hits::total 614496 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 433 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 316 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 749 # number of ReadReq misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 29344 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 29344 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 23201 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 23201 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 6 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::total 6 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.data 34650 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 34650 # number of ReadExReq misses -system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 21368 # number of ReadCleanReq misses -system.cpu1.l2cache.ReadCleanReq_misses::total 21368 # number of ReadCleanReq misses -system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 69500 # number of ReadSharedReq misses -system.cpu1.l2cache.ReadSharedReq_misses::total 69500 # number of ReadSharedReq misses -system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 433 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.itb.walker 316 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.inst 21368 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.data 104150 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::total 126267 # number of demand (read+write) misses -system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 433 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.itb.walker 316 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.inst 21368 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.data 104150 # number of overall misses -system.cpu1.l2cache.overall_misses::total 126267 # number of overall misses -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 8916500 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 6346000 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::total 15262500 # number of ReadReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 14232000 # number of UpgradeReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::total 14232000 # number of UpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 17729000 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 17729000 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 1919000 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 1919000 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1493005000 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::total 1493005000 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 842821500 # number of ReadCleanReq miss cycles -system.cpu1.l2cache.ReadCleanReq_miss_latency::total 842821500 # number of ReadCleanReq miss cycles -system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 1603059500 # number of ReadSharedReq miss cycles -system.cpu1.l2cache.ReadSharedReq_miss_latency::total 1603059500 # number of ReadSharedReq miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 8916500 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 6346000 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.inst 842821500 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.data 3096064500 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::total 3954148500 # number of demand (read+write) miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 8916500 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 6346000 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.inst 842821500 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.data 3096064500 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::total 3954148500 # number of overall miss cycles -system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 4181 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2279 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::total 6460 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.WritebackDirty_accesses::writebacks 114339 # number of WritebackDirty accesses(hits+misses) -system.cpu1.l2cache.WritebackDirty_accesses::total 114339 # number of WritebackDirty accesses(hits+misses) -system.cpu1.l2cache.WritebackClean_accesses::writebacks 565289 # number of WritebackClean accesses(hits+misses) -system.cpu1.l2cache.WritebackClean_accesses::total 565289 # number of WritebackClean accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 29344 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::total 29344 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23201 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::total 23201 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 6 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 6 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 62519 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::total 62519 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 503982 # number of ReadCleanReq accesses(hits+misses) -system.cpu1.l2cache.ReadCleanReq_accesses::total 503982 # number of ReadCleanReq accesses(hits+misses) -system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 167802 # number of ReadSharedReq accesses(hits+misses) -system.cpu1.l2cache.ReadSharedReq_accesses::total 167802 # number of ReadSharedReq accesses(hits+misses) -system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 4181 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2279 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.inst 503982 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.data 230321 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::total 740763 # number of demand (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 4181 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2279 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.inst 503982 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.data 230321 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::total 740763 # number of overall (read+write) accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.103564 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.138657 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::total 0.115944 # miss rate for ReadReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.554232 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::total 0.554232 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.042398 # miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.042398 # miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.414179 # miss rate for ReadSharedReq accesses -system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.414179 # miss rate for ReadSharedReq accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.103564 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.138657 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.042398 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.452195 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::total 0.170455 # miss rate for demand accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.103564 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.138657 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.042398 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.452195 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::total 0.170455 # miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 20592.378753 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20082.278481 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::total 20377.169559 # average ReadReq miss latency -system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 485.005453 # average UpgradeReq miss latency -system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 485.005453 # average UpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 764.148097 # average SCUpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 764.148097 # average SCUpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 319833.333333 # average SCUpgradeFailReq miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 319833.333333 # average SCUpgradeFailReq miss latency -system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 43088.167388 # average ReadExReq miss latency -system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 43088.167388 # average ReadExReq miss latency -system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 39443.162673 # average ReadCleanReq miss latency -system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 39443.162673 # average ReadCleanReq miss latency -system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 23065.604317 # average ReadSharedReq miss latency -system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 23065.604317 # average ReadSharedReq miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 20592.378753 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20082.278481 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 39443.162673 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 29726.975516 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::total 31315.771342 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 20592.378753 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20082.278481 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 39443.162673 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 29726.975516 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::total 31315.771342 # average overall miss latency -system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.l2cache.unused_prefetches 850 # number of HardPF blocks evicted w/o reference -system.cpu1.l2cache.writebacks::writebacks 33278 # number of writebacks -system.cpu1.l2cache.writebacks::total 33278 # number of writebacks -system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 91 # number of ReadExReq MSHR hits -system.cpu1.l2cache.ReadExReq_mshr_hits::total 91 # number of ReadExReq MSHR hits -system.cpu1.l2cache.demand_mshr_hits::cpu1.data 91 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.demand_mshr_hits::total 91 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.overall_mshr_hits::cpu1.data 91 # number of overall MSHR hits -system.cpu1.l2cache.overall_mshr_hits::total 91 # number of overall MSHR hits -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 433 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 316 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::total 749 # number of ReadReq MSHR misses -system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 26693 # number of HardPFReq MSHR misses -system.cpu1.l2cache.HardPFReq_mshr_misses::total 26693 # number of HardPFReq MSHR misses -system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 29344 # number of UpgradeReq MSHR misses -system.cpu1.l2cache.UpgradeReq_mshr_misses::total 29344 # number of UpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 23201 # number of SCUpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 23201 # number of SCUpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 6 # number of SCUpgradeFailReq MSHR misses -system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 6 # number of SCUpgradeFailReq MSHR misses -system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 34559 # number of ReadExReq MSHR misses -system.cpu1.l2cache.ReadExReq_mshr_misses::total 34559 # number of ReadExReq MSHR misses -system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 21368 # number of ReadCleanReq MSHR misses -system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 21368 # number of ReadCleanReq MSHR misses -system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 69500 # number of ReadSharedReq MSHR misses -system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 69500 # number of ReadSharedReq MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 433 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 316 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 21368 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.data 104059 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::total 126176 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 433 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 316 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 21368 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.data 104059 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 26693 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::total 152869 # number of overall MSHR misses -system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 177 # number of ReadReq MSHR uncacheable -system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 3077 # number of ReadReq MSHR uncacheable -system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 3254 # number of ReadReq MSHR uncacheable -system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 2432 # number of WriteReq MSHR uncacheable -system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 2432 # number of WriteReq MSHR uncacheable -system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 177 # number of overall MSHR uncacheable misses -system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 5509 # number of overall MSHR uncacheable misses -system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 5686 # number of overall MSHR uncacheable misses -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 6318500 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 4450000 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 10768500 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 957745966 # number of HardPFReq MSHR miss cycles -system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 957745966 # number of HardPFReq MSHR miss cycles -system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 449306000 # number of UpgradeReq MSHR miss cycles -system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 449306000 # number of UpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 347204000 # number of SCUpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 347204000 # number of SCUpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 1637000 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1637000 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1274798000 # number of ReadExReq MSHR miss cycles -system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1274798000 # number of ReadExReq MSHR miss cycles -system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 714613500 # number of ReadCleanReq MSHR miss cycles -system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 714613500 # number of ReadCleanReq MSHR miss cycles -system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 1186059500 # number of ReadSharedReq MSHR miss cycles -system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 1186059500 # number of ReadSharedReq MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 6318500 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 4450000 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 714613500 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2460857500 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::total 3186239500 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 6318500 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 4450000 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 714613500 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2460857500 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 957745966 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::total 4143985466 # number of overall MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 15741000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 417705000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 433446000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 15741000 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 417705000 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 433446000 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.103564 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.138657 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.115944 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses -system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.552776 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.552776 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.042398 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.042398 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.414179 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.414179 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.103564 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.138657 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.042398 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.451800 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.170332 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.103564 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.138657 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.042398 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.451800 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.206367 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 14592.378753 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14082.278481 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 14377.169559 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 35880.042183 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 35880.042183 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 15311.682116 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15311.682116 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14965.044610 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14965.044610 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 272833.333333 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 272833.333333 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 36887.583553 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 36887.583553 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 33443.162673 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 33443.162673 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 17065.604317 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 17065.604317 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 14592.378753 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14082.278481 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 33443.162673 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 23648.675271 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 25252.341967 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 14592.378753 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14082.278481 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 33443.162673 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 23648.675271 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 35880.042183 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 27108.082515 # average overall mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 88932.203390 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 135750.731232 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 133204.056546 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 88932.203390 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 75822.290797 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 76230.390433 # average overall mshr uncacheable latency -system.cpu1.toL2Bus.snoop_filter.tot_requests 1483973 # Total number of requests made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_requests 749706 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 11083 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.snoop_filter.tot_snoops 112750 # Total number of snoops made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 104482 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 8268 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states -system.cpu1.toL2Bus.trans_dist::ReadReq 12645 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 721727 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 2432 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 2432 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackDirty 148874 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackClean 576372 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::CleanEvict 28336 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 31823 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 70615 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 40952 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 85036 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 38 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 79 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 69693 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 67178 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadCleanReq 503982 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadSharedReq 263487 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateReq 292 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1511788 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 838524 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 5603 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 10248 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 2366163 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 64477636 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 29432570 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 9116 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 16724 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 93936046 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 334351 # Total snoops (count) -system.cpu1.toL2Bus.snoopTraffic 4909260 # Total snoop traffic (bytes) -system.cpu1.toL2Bus.snoop_fanout::samples 1058830 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 0.130816 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.359612 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::0 928586 87.70% 87.70% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 121976 11.52% 99.22% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 8268 0.78% 100.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 1058830 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 1438248000 # Layer occupancy (ticks) -system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 79282585 # Layer occupancy (ticks) -system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 756150000 # Layer occupancy (ticks) -system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 376097000 # Layer occupancy (ticks) -system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 3324000 # Layer occupancy (ticks) -system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 6067998 # Layer occupancy (ticks) -system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states -system.iobus.trans_dist::ReadReq 31015 # Transaction distribution -system.iobus.trans_dist::ReadResp 31015 # Transaction distribution -system.iobus.trans_dist::WriteReq 59423 # Transaction distribution -system.iobus.trans_dist::WriteResp 59423 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56604 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 107918 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72958 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 72958 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 180876 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71548 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 162798 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321272 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 2321272 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2484070 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 48604000 # Layer occupancy (ticks) -system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 106000 # Layer occupancy (ticks) -system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 319500 # Layer occupancy (ticks) -system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 31000 # Layer occupancy (ticks) -system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer4.occupancy 15000 # Layer occupancy (ticks) -system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 92500 # Layer occupancy (ticks) -system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer8.occupancy 623000 # Layer occupancy (ticks) -system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 22500 # Layer occupancy (ticks) -system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 10500 # Layer occupancy (ticks) -system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks) -system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer15.occupancy 11000 # Layer occupancy (ticks) -system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 46500 # Layer occupancy (ticks) -system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 11000 # Layer occupancy (ticks) -system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 10500 # Layer occupancy (ticks) -system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer19.occupancy 2500 # Layer occupancy (ticks) -system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer20.occupancy 9000 # Layer occupancy (ticks) -system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer21.occupancy 10500 # Layer occupancy (ticks) -system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 6201500 # Layer occupancy (ticks) -system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 32041500 # Layer occupancy (ticks) -system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 187869528 # Layer occupancy (ticks) -system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 84719000 # Layer occupancy (ticks) -system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36782000 # Layer occupancy (ticks) -system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states -system.iocache.tags.replacements 36445 # number of replacements -system.iocache.tags.tagsinuse 14.382505 # Cycle average of tags in use -system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 36461 # Sample count of references to valid blocks. -system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 290037968000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 14.382505 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.898907 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.898907 # Average percentage of cache occupancy -system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id -system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id -system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 328311 # Number of tag accesses -system.iocache.tags.data_accesses 328311 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states -system.iocache.ReadReq_misses::realview.ide 255 # number of ReadReq misses -system.iocache.ReadReq_misses::total 255 # number of ReadReq misses -system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses -system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses -system.iocache.demand_misses::realview.ide 36479 # number of demand (read+write) misses -system.iocache.demand_misses::total 36479 # number of demand (read+write) misses -system.iocache.overall_misses::realview.ide 36479 # number of overall misses -system.iocache.overall_misses::total 36479 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 41042377 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 41042377 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 4379492151 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4379492151 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 4420534528 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 4420534528 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 4420534528 # number of overall miss cycles -system.iocache.overall_miss_latency::total 4420534528 # number of overall miss cycles -system.iocache.ReadReq_accesses::realview.ide 255 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 255 # number of ReadReq accesses(hits+misses) -system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) -system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::realview.ide 36479 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 36479 # number of demand (read+write) accesses -system.iocache.overall_accesses::realview.ide 36479 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 36479 # number of overall (read+write) accesses -system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses -system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses -system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses -system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses -system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses -system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses -system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 160950.498039 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 160950.498039 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120900.291271 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 120900.291271 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 121180.255161 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 121180.255161 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 121180.255161 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 121180.255161 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 298 # number of cycles access was blocked -system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 9 # number of cycles access was blocked -system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 33.111111 # average number of cycles each access was blocked -system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.writebacks::writebacks 36190 # number of writebacks -system.iocache.writebacks::total 36190 # number of writebacks -system.iocache.ReadReq_mshr_misses::realview.ide 255 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 255 # number of ReadReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::realview.ide 36479 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 36479 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::realview.ide 36479 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 36479 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 28292377 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 28292377 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2566405842 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2566405842 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 2594698219 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 2594698219 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 2594698219 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 2594698219 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses -system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses -system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses -system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 110950.498039 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 110950.498039 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70848.217811 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70848.217811 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 71128.545711 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 71128.545711 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 71128.545711 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 71128.545711 # average overall mshr miss latency -system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states -system.l2c.tags.replacements 137345 # number of replacements -system.l2c.tags.tagsinuse 65074.392349 # Cycle average of tags in use -system.l2c.tags.total_refs 526935 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 202695 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 2.599645 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 103119965000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 6537.248776 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 4.009779 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.050987 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 7065.227850 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 6920.254188 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 37485.581661 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.954844 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 1513.426266 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 3159.258777 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 2388.379223 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.099751 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000061 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000001 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.107807 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.105595 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.571985 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000015 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.023093 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.048206 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.036444 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.992956 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 34308 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 8 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 31034 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::1 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 136 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 4715 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 29456 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 8 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 1168 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 29797 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.523499 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.000122 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.473541 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 6118121 # Number of tag accesses -system.l2c.tags.data_accesses 6118121 # Number of data accesses -system.l2c.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states -system.l2c.WritebackDirty_hits::writebacks 260748 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 260748 # number of WritebackDirty hits -system.l2c.UpgradeReq_hits::cpu0.data 39886 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 4893 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 44779 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 2390 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 2219 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 4609 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 3995 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 1504 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 5499 # number of ReadExReq hits -system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 159 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.itb.walker 75 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.inst 44649 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 52745 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 45897 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 46 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.itb.walker 28 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.inst 18994 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 11024 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 5470 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 179087 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.dtb.walker 159 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 75 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 44649 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 56740 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 45897 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 46 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 28 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 18994 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 12528 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 5470 # number of demand (read+write) hits -system.l2c.demand_hits::total 184586 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 159 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 75 # number of overall hits -system.l2c.overall_hits::cpu0.inst 44649 # number of overall hits -system.l2c.overall_hits::cpu0.data 56740 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 45897 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 46 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 28 # number of overall hits -system.l2c.overall_hits::cpu1.inst 18994 # number of overall hits -system.l2c.overall_hits::cpu1.data 12528 # number of overall hits -system.l2c.overall_hits::cpu1.l2cache.prefetcher 5470 # number of overall hits -system.l2c.overall_hits::total 184586 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0.data 631 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 289 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 920 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 83 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 96 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 179 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 11301 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 8030 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 19331 # number of ReadExReq misses -system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 7 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.itb.walker 2 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.inst 17908 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.data 9085 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 133844 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 1 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.inst 2374 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.data 942 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 6476 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 170639 # number of ReadSharedReq misses -system.l2c.demand_misses::cpu0.dtb.walker 7 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 17908 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 20386 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.l2cache.prefetcher 133844 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 2374 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 8972 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.l2cache.prefetcher 6476 # number of demand (read+write) misses -system.l2c.demand_misses::total 189970 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 7 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses -system.l2c.overall_misses::cpu0.inst 17908 # number of overall misses -system.l2c.overall_misses::cpu0.data 20386 # number of overall misses -system.l2c.overall_misses::cpu0.l2cache.prefetcher 133844 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu1.inst 2374 # number of overall misses -system.l2c.overall_misses::cpu1.data 8972 # number of overall misses -system.l2c.overall_misses::cpu1.l2cache.prefetcher 6476 # number of overall misses -system.l2c.overall_misses::total 189970 # number of overall misses -system.l2c.UpgradeReq_miss_latency::cpu0.data 10365500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 935500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 11301000 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 563000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 162500 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 725500 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 1654925500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 828235000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 2483160500 # number of ReadExReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 1167000 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 185500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.inst 1949681500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.data 1106313500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 15937420718 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 90000 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.inst 261013000 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.data 123092000 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 836855283 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::total 20215818501 # number of ReadSharedReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 1167000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.itb.walker 185500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 1949681500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 2761239000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 15937420718 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 90000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 261013000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 951327000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 836855283 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 22698979001 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.dtb.walker 1167000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.itb.walker 185500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 1949681500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 2761239000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 15937420718 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 90000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 261013000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 951327000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 836855283 # number of overall miss cycles -system.l2c.overall_miss_latency::total 22698979001 # number of overall miss cycles -system.l2c.WritebackDirty_accesses::writebacks 260748 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackDirty_accesses::total 260748 # number of WritebackDirty accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 40517 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 5182 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 45699 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 2473 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 2315 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 4788 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 15296 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 9534 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 24830 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 166 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 77 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.inst 62557 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.data 61830 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 179741 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 47 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 28 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.inst 21368 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.data 11966 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 11946 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::total 349726 # number of ReadSharedReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 166 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 77 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 62557 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 77126 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.l2cache.prefetcher 179741 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 47 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 28 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 21368 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 21500 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.l2cache.prefetcher 11946 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 374556 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 166 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 77 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 62557 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 77126 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.l2cache.prefetcher 179741 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 47 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 28 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 21368 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 21500 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.l2cache.prefetcher 11946 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 374556 # number of overall (read+write) accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.015574 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.055770 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.020132 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.033562 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.041469 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.037385 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.738821 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.842249 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.778534 # miss rate for ReadExReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.042169 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.025974 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.286267 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.146935 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.744649 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.021277 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.111101 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.078723 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.542106 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::total 0.487922 # miss rate for ReadSharedReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.042169 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.025974 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.286267 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.264321 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.744649 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.021277 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.111101 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.417302 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.542106 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.507187 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.042169 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.025974 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.286267 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.264321 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.744649 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.021277 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.111101 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.417302 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.542106 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.507187 # miss rate for overall accesses -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 16427.099842 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 3237.024221 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 12283.695652 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 6783.132530 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 1692.708333 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 4053.072626 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 146440.624723 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 103142.590286 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 128454.839377 # average ReadExReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 166714.285714 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 92750 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 108872.096270 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 121773.637865 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 119074.599668 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 90000 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 109946.503791 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 130670.912951 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 129224.101760 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::total 118471.266832 # average ReadSharedReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 166714.285714 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.itb.walker 92750 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 108872.096270 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 135447.807319 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 119074.599668 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 90000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 109946.503791 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 106032.880071 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 129224.101760 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 119487.176928 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 166714.285714 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.itb.walker 92750 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 108872.096270 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 135447.807319 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 119074.599668 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 90000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 109946.503791 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 106032.880071 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 129224.101760 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 119487.176928 # average overall miss latency -system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2c.writebacks::writebacks 100603 # number of writebacks -system.l2c.writebacks::total 100603 # number of writebacks -system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 4 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 6 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::total 10 # number of ReadSharedReq MSHR hits -system.l2c.demand_mshr_hits::cpu0.inst 4 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.inst 6 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 10 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu0.inst 4 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.inst 6 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 10 # number of overall MSHR hits -system.l2c.CleanEvict_mshr_misses::writebacks 3738 # number of CleanEvict MSHR misses -system.l2c.CleanEvict_mshr_misses::total 3738 # number of CleanEvict MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 631 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 289 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 920 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 83 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 96 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 179 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 11301 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 8030 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 19331 # number of ReadExReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 7 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 2 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 17904 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu0.data 9085 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 133844 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 1 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 2368 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu1.data 942 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 6476 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::total 170629 # number of ReadSharedReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.dtb.walker 7 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.itb.walker 2 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 17904 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 20386 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 133844 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.dtb.walker 1 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 2368 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 8972 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 6476 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 189960 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.dtb.walker 7 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 17904 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 20386 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 133844 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.dtb.walker 1 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 2368 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 8972 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 6476 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 189960 # number of overall MSHR misses -system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 9022 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu0.data 31768 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 177 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu1.data 3074 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::total 44041 # number of ReadReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu0.data 28446 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu1.data 2432 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::total 30878 # number of WriteReq MSHR uncacheable -system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 9022 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu0.data 60214 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 177 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu1.data 5506 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::total 74919 # number of overall MSHR uncacheable misses -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 14735500 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 6305500 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 21041000 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 2194500 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 2340500 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 4535000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 1541915500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 747935000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 2289850500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 1097000 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 165500 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 1770529000 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 1015463500 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 14598976726 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 80000 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 236880000 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 113671002 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 772093287 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::total 18508956015 # number of ReadSharedReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 1097000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 165500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 1770529000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 2557379000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 14598976726 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 80000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 236880000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 861606002 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 772093287 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 20798806515 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 1097000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 165500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 1770529000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 2557379000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 14598976726 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 80000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 236880000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 861606002 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 772093287 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 20798806515 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 633244000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5804773000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 12555000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 362314500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 6812886500 # number of ReadReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 633244000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 5804773000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 12555000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 362314500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 6812886500 # number of overall MSHR uncacheable cycles -system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses -system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.015574 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.055770 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.020132 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.033562 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.041469 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.037385 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.738821 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.842249 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.778534 # mshr miss rate for ReadExReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.042169 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.025974 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.286203 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.146935 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.744649 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.021277 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.110820 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.078723 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.542106 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::total 0.487893 # mshr miss rate for ReadSharedReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.042169 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.025974 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.286203 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.264321 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.744649 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.021277 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.110820 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.417302 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.542106 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.507160 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.042169 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.025974 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.286203 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.264321 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.744649 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.021277 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.110820 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.417302 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.542106 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.507160 # mshr miss rate for overall accesses -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 23352.614897 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 21818.339100 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 22870.652174 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 26439.759036 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24380.208333 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 25335.195531 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 136440.624723 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 93142.590286 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 118454.839377 # average ReadExReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 156714.285714 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 82750 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 98890.136282 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 111773.637865 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109074.569843 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 80000 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 100033.783784 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 120669.853503 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 119223.793545 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 108474.854890 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 156714.285714 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 82750 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 98890.136282 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 125447.807319 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109074.569843 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 80000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 100033.783784 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 96032.768836 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 119223.793545 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 109490.453332 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 156714.285714 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 82750 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 98890.136282 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 125447.807319 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109074.569843 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 80000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 100033.783784 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 96032.768836 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 119223.793545 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 109490.453332 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 70188.871647 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182723.904558 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 70932.203390 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 117864.183474 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 154694.182693 # average ReadReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 70188.871647 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 96402.381506 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 70932.203390 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 65803.577915 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 90936.698301 # average overall mshr uncacheable latency -system.membus.snoop_filter.tot_requests 502698 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 282285 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 634 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 44041 # Transaction distribution -system.membus.trans_dist::ReadResp 214925 # Transaction distribution -system.membus.trans_dist::WriteReq 30878 # Transaction distribution -system.membus.trans_dist::WriteResp 30878 # Transaction distribution -system.membus.trans_dist::WritebackDirty 136793 # Transaction distribution -system.membus.trans_dist::CleanEvict 16421 # Transaction distribution -system.membus.trans_dist::UpgradeReq 64440 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 38073 # Transaction distribution -system.membus.trans_dist::UpgradeResp 16 # Transaction distribution -system.membus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution -system.membus.trans_dist::ReadExReq 39751 # Transaction distribution -system.membus.trans_dist::ReadExResp 19302 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 170884 # Transaction distribution -system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.membus.trans_dist::InvalidateResp 4530 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107918 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13584 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 647548 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 769084 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72939 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 72939 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 842023 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162798 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27168 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18628620 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 18818654 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 21135774 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 126969 # Total snoops (count) -system.membus.snoopTraffic 37632 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 424292 # Request fanout histogram -system.membus.snoop_fanout::mean 0.012213 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.109837 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 419110 98.78% 98.78% # Request fanout histogram -system.membus.snoop_fanout::1 5182 1.22% 100.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 424292 # Request fanout histogram -system.membus.reqLayer0.occupancy 88179000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 19000 # Layer occupancy (ticks) -system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 11330000 # Layer occupancy (ticks) -system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 970733801 # Layer occupancy (ticks) -system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1113560532 # Layer occupancy (ticks) -system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 7243389 # Layer occupancy (ticks) -system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states -system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks -system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks -system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks -system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks -system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks -system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states -system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA -system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA -system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA -system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA -system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU -system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post -system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR -system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU -system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post -system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR -system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU -system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post -system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR -system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU -system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post -system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR -system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU -system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post -system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR -system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU -system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post -system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR -system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU -system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post -system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR -system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU -system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post -system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR -system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post -system.realview.ethernet.postedInterrupts 0 # number of posts to CPU -system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states -system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks -system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks -system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks -system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states -system.toL2Bus.snoop_filter.tot_requests 1013922 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 527446 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 187526 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 29573 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 28355 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 1218 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2870995800500 # Cumulative time (in ticks) in various power states -system.toL2Bus.trans_dist::ReadReq 44044 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 511645 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 30878 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 30878 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 361351 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 119836 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 109190 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 42682 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 151872 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 79 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 79 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 50757 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 50757 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 467605 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 4574 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateResp 3427 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1275330 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 317115 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 1592445 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 35259052 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 5662514 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 40921566 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 390876 # Total snoops (count) -system.toL2Bus.snoopTraffic 15646988 # Total snoop traffic (bytes) -system.toL2Bus.snoop_fanout::samples 887171 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.397282 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.492133 # Request fanout histogram -system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 535932 60.41% 60.41% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 350021 39.45% 99.86% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 1218 0.14% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 887171 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 894860010 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 2155585 # Layer occupancy (ticks) -system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 676392933 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 238880542 # Layer occupancy (ticks) -system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +sim_seconds 2.871012 +sim_ticks 2871012355500 +final_tick 2871012355500 +sim_freq 1000000000000 +host_inst_rate 1070603 +host_op_rate 1294963 +host_tick_rate 23409963735 +host_mem_usage 628644 +host_seconds 122.64 +sim_insts 131299345 +sim_ops 158815094 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 2871012355500 +system.physmem.bytes_read::cpu0.dtb.walker 448 +system.physmem.bytes_read::cpu0.itb.walker 128 +system.physmem.bytes_read::cpu0.inst 1181348 +system.physmem.bytes_read::cpu0.data 1294820 +system.physmem.bytes_read::cpu0.l2cache.prefetcher 8551616 +system.physmem.bytes_read::cpu1.dtb.walker 64 +system.physmem.bytes_read::cpu1.inst 152660 +system.physmem.bytes_read::cpu1.data 573908 +system.physmem.bytes_read::cpu1.l2cache.prefetcher 413696 +system.physmem.bytes_read::realview.ide 960 +system.physmem.bytes_read::total 12169648 +system.physmem.bytes_inst_read::cpu0.inst 1181348 +system.physmem.bytes_inst_read::cpu1.inst 152660 +system.physmem.bytes_inst_read::total 1334008 +system.physmem.bytes_written::writebacks 8749184 +system.physmem.bytes_written::cpu0.data 17524 +system.physmem.bytes_written::cpu1.data 40 +system.physmem.bytes_written::total 8766748 +system.physmem.num_reads::cpu0.dtb.walker 7 +system.physmem.num_reads::cpu0.itb.walker 2 +system.physmem.num_reads::cpu0.inst 26912 +system.physmem.num_reads::cpu0.data 20751 +system.physmem.num_reads::cpu0.l2cache.prefetcher 133619 +system.physmem.num_reads::cpu1.dtb.walker 1 +system.physmem.num_reads::cpu1.inst 2540 +system.physmem.num_reads::cpu1.data 8988 +system.physmem.num_reads::cpu1.l2cache.prefetcher 6464 +system.physmem.num_reads::realview.ide 15 +system.physmem.num_reads::total 199299 +system.physmem.num_writes::writebacks 136706 +system.physmem.num_writes::cpu0.data 4381 +system.physmem.num_writes::cpu1.data 10 +system.physmem.num_writes::total 141097 +system.physmem.bw_read::cpu0.dtb.walker 156 +system.physmem.bw_read::cpu0.itb.walker 45 +system.physmem.bw_read::cpu0.inst 411474 +system.physmem.bw_read::cpu0.data 450998 +system.physmem.bw_read::cpu0.l2cache.prefetcher 2978606 +system.physmem.bw_read::cpu1.dtb.walker 22 +system.physmem.bw_read::cpu1.inst 53173 +system.physmem.bw_read::cpu1.data 199897 +system.physmem.bw_read::cpu1.l2cache.prefetcher 144094 +system.physmem.bw_read::realview.ide 334 +system.physmem.bw_read::total 4238800 +system.physmem.bw_inst_read::cpu0.inst 411474 +system.physmem.bw_inst_read::cpu1.inst 53173 +system.physmem.bw_inst_read::total 464647 +system.physmem.bw_write::writebacks 3047421 +system.physmem.bw_write::cpu0.data 6104 +system.physmem.bw_write::cpu1.data 14 +system.physmem.bw_write::total 3053539 +system.physmem.bw_total::writebacks 3047421 +system.physmem.bw_total::cpu0.dtb.walker 156 +system.physmem.bw_total::cpu0.itb.walker 45 +system.physmem.bw_total::cpu0.inst 411474 +system.physmem.bw_total::cpu0.data 457101 +system.physmem.bw_total::cpu0.l2cache.prefetcher 2978606 +system.physmem.bw_total::cpu1.dtb.walker 22 +system.physmem.bw_total::cpu1.inst 53173 +system.physmem.bw_total::cpu1.data 199911 +system.physmem.bw_total::cpu1.l2cache.prefetcher 144094 +system.physmem.bw_total::realview.ide 334 +system.physmem.bw_total::total 7292339 +system.physmem.readReqs 199299 +system.physmem.writeReqs 141097 +system.physmem.readBursts 199299 +system.physmem.writeBursts 141097 +system.physmem.bytesReadDRAM 12744832 +system.physmem.bytesReadWrQ 10304 +system.physmem.bytesWritten 8779712 +system.physmem.bytesReadSys 12169648 +system.physmem.bytesWrittenSys 8766748 +system.physmem.servicedByWrQ 161 +system.physmem.mergedWrBursts 3897 +system.physmem.neitherReadNorWriteReqs 0 +system.physmem.perBankRdBursts::0 11941 +system.physmem.perBankRdBursts::1 11941 +system.physmem.perBankRdBursts::2 12061 +system.physmem.perBankRdBursts::3 12014 +system.physmem.perBankRdBursts::4 20277 +system.physmem.perBankRdBursts::5 11993 +system.physmem.perBankRdBursts::6 12082 +system.physmem.perBankRdBursts::7 12163 +system.physmem.perBankRdBursts::8 12412 +system.physmem.perBankRdBursts::9 12768 +system.physmem.perBankRdBursts::10 11659 +system.physmem.perBankRdBursts::11 11203 +system.physmem.perBankRdBursts::12 11765 +system.physmem.perBankRdBursts::13 11689 +system.physmem.perBankRdBursts::14 11759 +system.physmem.perBankRdBursts::15 11411 +system.physmem.perBankWrBursts::0 8593 +system.physmem.perBankWrBursts::1 8809 +system.physmem.perBankWrBursts::2 8990 +system.physmem.perBankWrBursts::3 8736 +system.physmem.perBankWrBursts::4 8204 +system.physmem.perBankWrBursts::5 8547 +system.physmem.perBankWrBursts::6 8879 +system.physmem.perBankWrBursts::7 8644 +system.physmem.perBankWrBursts::8 8884 +system.physmem.perBankWrBursts::9 9196 +system.physmem.perBankWrBursts::10 8452 +system.physmem.perBankWrBursts::11 8329 +system.physmem.perBankWrBursts::12 8624 +system.physmem.perBankWrBursts::13 8076 +system.physmem.perBankWrBursts::14 8386 +system.physmem.perBankWrBursts::15 7834 +system.physmem.numRdRetry 0 +system.physmem.numWrRetry 79 +system.physmem.totGap 2871011323500 +system.physmem.readPktSize::0 0 +system.physmem.readPktSize::1 0 +system.physmem.readPktSize::2 9732 +system.physmem.readPktSize::3 28 +system.physmem.readPktSize::4 0 +system.physmem.readPktSize::5 0 +system.physmem.readPktSize::6 189539 +system.physmem.writePktSize::0 0 +system.physmem.writePktSize::1 0 +system.physmem.writePktSize::2 4391 +system.physmem.writePktSize::3 0 +system.physmem.writePktSize::4 0 +system.physmem.writePktSize::5 0 +system.physmem.writePktSize::6 136706 +system.physmem.rdQLenPdf::0 135966 +system.physmem.rdQLenPdf::1 17240 +system.physmem.rdQLenPdf::2 10602 +system.physmem.rdQLenPdf::3 8757 +system.physmem.rdQLenPdf::4 7338 +system.physmem.rdQLenPdf::5 5891 +system.physmem.rdQLenPdf::6 5065 +system.physmem.rdQLenPdf::7 4253 +system.physmem.rdQLenPdf::8 3715 +system.physmem.rdQLenPdf::9 134 +system.physmem.rdQLenPdf::10 84 +system.physmem.rdQLenPdf::11 52 +system.physmem.rdQLenPdf::12 25 +system.physmem.rdQLenPdf::13 7 +system.physmem.rdQLenPdf::14 3 +system.physmem.rdQLenPdf::15 2 +system.physmem.rdQLenPdf::16 2 +system.physmem.rdQLenPdf::17 2 +system.physmem.rdQLenPdf::18 0 +system.physmem.rdQLenPdf::19 0 +system.physmem.rdQLenPdf::20 0 +system.physmem.rdQLenPdf::21 0 +system.physmem.rdQLenPdf::22 0 +system.physmem.rdQLenPdf::23 0 +system.physmem.rdQLenPdf::24 0 +system.physmem.rdQLenPdf::25 0 +system.physmem.rdQLenPdf::26 0 +system.physmem.rdQLenPdf::27 0 +system.physmem.rdQLenPdf::28 0 +system.physmem.rdQLenPdf::29 0 +system.physmem.rdQLenPdf::30 0 +system.physmem.rdQLenPdf::31 0 +system.physmem.wrQLenPdf::0 1 +system.physmem.wrQLenPdf::1 1 +system.physmem.wrQLenPdf::2 1 +system.physmem.wrQLenPdf::3 1 +system.physmem.wrQLenPdf::4 1 +system.physmem.wrQLenPdf::5 1 +system.physmem.wrQLenPdf::6 1 +system.physmem.wrQLenPdf::7 1 +system.physmem.wrQLenPdf::8 1 +system.physmem.wrQLenPdf::9 1 +system.physmem.wrQLenPdf::10 1 +system.physmem.wrQLenPdf::11 1 +system.physmem.wrQLenPdf::12 1 +system.physmem.wrQLenPdf::13 1 +system.physmem.wrQLenPdf::14 1 +system.physmem.wrQLenPdf::15 2529 +system.physmem.wrQLenPdf::16 3481 +system.physmem.wrQLenPdf::17 4419 +system.physmem.wrQLenPdf::18 5391 +system.physmem.wrQLenPdf::19 6442 +system.physmem.wrQLenPdf::20 6509 +system.physmem.wrQLenPdf::21 7071 +system.physmem.wrQLenPdf::22 7524 +system.physmem.wrQLenPdf::23 8510 +system.physmem.wrQLenPdf::24 8349 +system.physmem.wrQLenPdf::25 9606 +system.physmem.wrQLenPdf::26 10061 +system.physmem.wrQLenPdf::27 8512 +system.physmem.wrQLenPdf::28 8112 +system.physmem.wrQLenPdf::29 8311 +system.physmem.wrQLenPdf::30 9404 +system.physmem.wrQLenPdf::31 7883 +system.physmem.wrQLenPdf::32 7638 +system.physmem.wrQLenPdf::33 727 +system.physmem.wrQLenPdf::34 448 +system.physmem.wrQLenPdf::35 388 +system.physmem.wrQLenPdf::36 335 +system.physmem.wrQLenPdf::37 256 +system.physmem.wrQLenPdf::38 272 +system.physmem.wrQLenPdf::39 265 +system.physmem.wrQLenPdf::40 225 +system.physmem.wrQLenPdf::41 178 +system.physmem.wrQLenPdf::42 199 +system.physmem.wrQLenPdf::43 179 +system.physmem.wrQLenPdf::44 202 +system.physmem.wrQLenPdf::45 241 +system.physmem.wrQLenPdf::46 234 +system.physmem.wrQLenPdf::47 176 +system.physmem.wrQLenPdf::48 183 +system.physmem.wrQLenPdf::49 185 +system.physmem.wrQLenPdf::50 199 +system.physmem.wrQLenPdf::51 165 +system.physmem.wrQLenPdf::52 205 +system.physmem.wrQLenPdf::53 189 +system.physmem.wrQLenPdf::54 159 +system.physmem.wrQLenPdf::55 158 +system.physmem.wrQLenPdf::56 255 +system.physmem.wrQLenPdf::57 220 +system.physmem.wrQLenPdf::58 143 +system.physmem.wrQLenPdf::59 244 +system.physmem.wrQLenPdf::60 209 +system.physmem.wrQLenPdf::61 180 +system.physmem.wrQLenPdf::62 157 +system.physmem.wrQLenPdf::63 257 +system.physmem.bytesPerActivate::samples 85488 +system.physmem.bytesPerActivate::mean 251.783642 +system.physmem.bytesPerActivate::gmean 143.209500 +system.physmem.bytesPerActivate::stdev 307.626161 +system.physmem.bytesPerActivate::0-127 42834 50.11% 50.11% +system.physmem.bytesPerActivate::128-255 18033 21.09% 71.20% +system.physmem.bytesPerActivate::256-383 6282 7.35% 78.55% +system.physmem.bytesPerActivate::384-511 3726 4.36% 82.91% +system.physmem.bytesPerActivate::512-639 2666 3.12% 86.02% +system.physmem.bytesPerActivate::640-767 1646 1.93% 87.95% +system.physmem.bytesPerActivate::768-895 883 1.03% 88.98% +system.physmem.bytesPerActivate::896-1023 975 1.14% 90.12% +system.physmem.bytesPerActivate::1024-1151 8443 9.88% 100.00% +system.physmem.bytesPerActivate::total 85488 +system.physmem.rdPerTurnAround::samples 6782 +system.physmem.rdPerTurnAround::mean 29.362430 +system.physmem.rdPerTurnAround::stdev 565.225219 +system.physmem.rdPerTurnAround::0-2047 6780 99.97% 99.97% +system.physmem.rdPerTurnAround::2048-4095 1 0.01% 99.99% +system.physmem.rdPerTurnAround::45056-47103 1 0.01% 100.00% +system.physmem.rdPerTurnAround::total 6782 +system.physmem.wrPerTurnAround::samples 6782 +system.physmem.wrPerTurnAround::mean 20.227514 +system.physmem.wrPerTurnAround::gmean 18.570606 +system.physmem.wrPerTurnAround::stdev 13.781277 +system.physmem.wrPerTurnAround::16-19 5756 84.87% 84.87% +system.physmem.wrPerTurnAround::20-23 321 4.73% 89.60% +system.physmem.wrPerTurnAround::24-27 54 0.80% 90.40% +system.physmem.wrPerTurnAround::28-31 63 0.93% 91.33% +system.physmem.wrPerTurnAround::32-35 275 4.05% 95.38% +system.physmem.wrPerTurnAround::36-39 22 0.32% 95.71% +system.physmem.wrPerTurnAround::40-43 19 0.28% 95.99% +system.physmem.wrPerTurnAround::44-47 12 0.18% 96.17% +system.physmem.wrPerTurnAround::48-51 17 0.25% 96.42% +system.physmem.wrPerTurnAround::52-55 2 0.03% 96.45% +system.physmem.wrPerTurnAround::56-59 1 0.01% 96.46% +system.physmem.wrPerTurnAround::60-63 11 0.16% 96.62% +system.physmem.wrPerTurnAround::64-67 152 2.24% 98.86% +system.physmem.wrPerTurnAround::68-71 7 0.10% 98.97% +system.physmem.wrPerTurnAround::72-75 10 0.15% 99.12% +system.physmem.wrPerTurnAround::76-79 5 0.07% 99.19% +system.physmem.wrPerTurnAround::80-83 2 0.03% 99.22% +system.physmem.wrPerTurnAround::84-87 1 0.01% 99.23% +system.physmem.wrPerTurnAround::88-91 1 0.01% 99.25% +system.physmem.wrPerTurnAround::92-95 2 0.03% 99.28% +system.physmem.wrPerTurnAround::96-99 3 0.04% 99.32% +system.physmem.wrPerTurnAround::100-103 2 0.03% 99.35% +system.physmem.wrPerTurnAround::104-107 1 0.01% 99.37% +system.physmem.wrPerTurnAround::108-111 5 0.07% 99.44% +system.physmem.wrPerTurnAround::112-115 2 0.03% 99.47% +system.physmem.wrPerTurnAround::120-123 1 0.01% 99.48% +system.physmem.wrPerTurnAround::124-127 2 0.03% 99.51% +system.physmem.wrPerTurnAround::128-131 8 0.12% 99.63% +system.physmem.wrPerTurnAround::132-135 3 0.04% 99.68% +system.physmem.wrPerTurnAround::136-139 5 0.07% 99.75% +system.physmem.wrPerTurnAround::144-147 2 0.03% 99.78% +system.physmem.wrPerTurnAround::156-159 3 0.04% 99.82% +system.physmem.wrPerTurnAround::160-163 2 0.03% 99.85% +system.physmem.wrPerTurnAround::164-167 1 0.01% 99.87% +system.physmem.wrPerTurnAround::172-175 3 0.04% 99.91% +system.physmem.wrPerTurnAround::180-183 1 0.01% 99.93% +system.physmem.wrPerTurnAround::188-191 1 0.01% 99.94% +system.physmem.wrPerTurnAround::192-195 4 0.06% 100.00% +system.physmem.wrPerTurnAround::total 6782 +system.physmem.totQLat 9440334255 +system.physmem.totMemAccLat 13174171755 +system.physmem.totBusLat 995690000 +system.physmem.avgQLat 47405.99 +system.physmem.avgBusLat 5000.00 +system.physmem.avgMemAccLat 66155.99 +system.physmem.avgRdBW 4.44 +system.physmem.avgWrBW 3.06 +system.physmem.avgRdBWSys 4.24 +system.physmem.avgWrBWSys 3.05 +system.physmem.peakBW 12800.00 +system.physmem.busUtil 0.06 +system.physmem.busUtilRead 0.03 +system.physmem.busUtilWrite 0.02 +system.physmem.avgRdQLen 1.05 +system.physmem.avgWrQLen 22.72 +system.physmem.readRowHits 166173 +system.physmem.writeRowHits 84659 +system.physmem.readRowHitRate 83.45 +system.physmem.writeRowHitRate 61.70 +system.physmem.avgGap 8434327.44 +system.physmem.pageHitRate 74.58 +system.physmem_0.actEnergy 308819280 +system.physmem_0.preEnergy 164137545 +system.physmem_0.readEnergy 745930080 +system.physmem_0.writeEnergy 362278440 +system.physmem_0.refreshEnergy 6150087840.000001 +system.physmem_0.actBackEnergy 5622831690 +system.physmem_0.preBackEnergy 364043040 +system.physmem_0.actPowerDownEnergy 11524806630 +system.physmem_0.prePowerDownEnergy 9158295840 +system.physmem_0.selfRefreshEnergy 675248492655 +system.physmem_0.totalEnergy 709652557290 +system.physmem_0.averagePower 247.178510 +system.physmem_0.totalIdleTime 2857727193718 +system.physmem_0.memoryStateTime::IDLE 674787943 +system.physmem_0.memoryStateTime::REF 2614676000 +system.physmem_0.memoryStateTime::SREF 2808603815500 +system.physmem_0.memoryStateTime::PRE_PDN 23849720592 +system.physmem_0.memoryStateTime::ACT 9995633339 +system.physmem_0.memoryStateTime::ACT_PDN 25273722126 +system.physmem_1.actEnergy 301572180 +system.physmem_1.preEnergy 160289415 +system.physmem_1.readEnergy 675915240 +system.physmem_1.writeEnergy 353816820 +system.physmem_1.refreshEnergy 6255191280.000001 +system.physmem_1.actBackEnergy 5736132870 +system.physmem_1.preBackEnergy 359474400 +system.physmem_1.actPowerDownEnergy 11377384680 +system.physmem_1.prePowerDownEnergy 9560351520 +system.physmem_1.selfRefreshEnergy 675046333020 +system.physmem_1.totalEnergy 709829884665 +system.physmem_1.averagePower 247.240275 +system.physmem_1.totalIdleTime 2857311193722 +system.physmem_1.memoryStateTime::IDLE 664285239 +system.physmem_1.memoryStateTime::REF 2659412000 +system.physmem_1.memoryStateTime::SREF 2807642220500 +system.physmem_1.memoryStateTime::PRE_PDN 24896771092 +system.physmem_1.memoryStateTime::ACT 10199382539 +system.physmem_1.memoryStateTime::ACT_PDN 24950284130 +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2871012355500 +system.realview.nvmem.bytes_read::cpu0.inst 20 +system.realview.nvmem.bytes_read::cpu1.inst 48 +system.realview.nvmem.bytes_read::total 68 +system.realview.nvmem.bytes_inst_read::cpu0.inst 20 +system.realview.nvmem.bytes_inst_read::cpu1.inst 48 +system.realview.nvmem.bytes_inst_read::total 68 +system.realview.nvmem.num_reads::cpu0.inst 5 +system.realview.nvmem.num_reads::cpu1.inst 12 +system.realview.nvmem.num_reads::total 17 +system.realview.nvmem.bw_read::cpu0.inst 7 +system.realview.nvmem.bw_read::cpu1.inst 17 +system.realview.nvmem.bw_read::total 24 +system.realview.nvmem.bw_inst_read::cpu0.inst 7 +system.realview.nvmem.bw_inst_read::cpu1.inst 17 +system.realview.nvmem.bw_inst_read::total 24 +system.realview.nvmem.bw_total::cpu0.inst 7 +system.realview.nvmem.bw_total::cpu1.inst 17 +system.realview.nvmem.bw_total::total 24 +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2871012355500 +system.pwrStateResidencyTicks::UNDEFINED 2871012355500 +system.bridge.pwrStateResidencyTicks::UNDEFINED 2871012355500 +system.cf0.dma_read_full_pages 0 +system.cf0.dma_read_bytes 1024 +system.cf0.dma_read_txs 1 +system.cf0.dma_write_full_pages 540 +system.cf0.dma_write_bytes 2318336 +system.cf0.dma_write_txs 631 +system.cpu_clk_domain.clock 500 +system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2871012355500 +system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 +system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 +system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 +system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 +system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 +system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 +system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 +system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 +system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 +system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 +system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 +system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 +system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 +system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 +system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 +system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 +system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 +system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 +system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 +system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 +system.cpu0.dstage2_mmu.stage2_tlb.hits 0 +system.cpu0.dstage2_mmu.stage2_tlb.misses 0 +system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 +system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2871012355500 +system.cpu0.dtb.walker.walks 7823 +system.cpu0.dtb.walker.walksShort 7823 +system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 1470 +system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 6353 +system.cpu0.dtb.walker.walkWaitTime::samples 7823 +system.cpu0.dtb.walker.walkWaitTime::0 7823 100.00% 100.00% +system.cpu0.dtb.walker.walkWaitTime::total 7823 +system.cpu0.dtb.walker.walkCompletionTime::samples 6429 +system.cpu0.dtb.walker.walkCompletionTime::mean 12399.906673 +system.cpu0.dtb.walker.walkCompletionTime::gmean 11403.406906 +system.cpu0.dtb.walker.walkCompletionTime::stdev 6039.827624 +system.cpu0.dtb.walker.walkCompletionTime::0-16383 5900 91.77% 91.77% +system.cpu0.dtb.walker.walkCompletionTime::16384-32767 462 7.19% 98.96% +system.cpu0.dtb.walker.walkCompletionTime::32768-49151 57 0.89% 99.84% +system.cpu0.dtb.walker.walkCompletionTime::49152-65535 5 0.08% 99.92% +system.cpu0.dtb.walker.walkCompletionTime::81920-98303 1 0.02% 99.94% +system.cpu0.dtb.walker.walkCompletionTime::98304-114687 3 0.05% 99.98% +system.cpu0.dtb.walker.walkCompletionTime::212992-229375 1 0.02% 100.00% +system.cpu0.dtb.walker.walkCompletionTime::total 6429 +system.cpu0.dtb.walker.walksPending::samples 1181300000 +system.cpu0.dtb.walker.walksPending::0 1181300000 100.00% 100.00% +system.cpu0.dtb.walker.walksPending::total 1181300000 +system.cpu0.dtb.walker.walkPageSizes::4K 4998 77.74% 77.74% +system.cpu0.dtb.walker.walkPageSizes::1M 1431 22.26% 100.00% +system.cpu0.dtb.walker.walkPageSizes::total 6429 +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 7823 +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 7823 +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6429 +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6429 +system.cpu0.dtb.walker.walkRequestOrigin::total 14252 +system.cpu0.dtb.inst_hits 0 +system.cpu0.dtb.inst_misses 0 +system.cpu0.dtb.read_hits 25079832 +system.cpu0.dtb.read_misses 6706 +system.cpu0.dtb.write_hits 18692115 +system.cpu0.dtb.write_misses 1117 +system.cpu0.dtb.flush_tlb 66 +system.cpu0.dtb.flush_tlb_mva 917 +system.cpu0.dtb.flush_tlb_mva_asid 0 +system.cpu0.dtb.flush_tlb_asid 0 +system.cpu0.dtb.flush_entries 3388 +system.cpu0.dtb.align_faults 0 +system.cpu0.dtb.prefetch_faults 1745 +system.cpu0.dtb.domain_faults 0 +system.cpu0.dtb.perms_faults 282 +system.cpu0.dtb.read_accesses 25086538 +system.cpu0.dtb.write_accesses 18693232 +system.cpu0.dtb.inst_accesses 0 +system.cpu0.dtb.hits 43771947 +system.cpu0.dtb.misses 7823 +system.cpu0.dtb.accesses 43779770 +system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2871012355500 +system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 +system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 +system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 +system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 +system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 +system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 +system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 +system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 +system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 +system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 +system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 +system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 +system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 +system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 +system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 +system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 +system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 +system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 +system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 +system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 +system.cpu0.istage2_mmu.stage2_tlb.hits 0 +system.cpu0.istage2_mmu.stage2_tlb.misses 0 +system.cpu0.istage2_mmu.stage2_tlb.accesses 0 +system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2871012355500 +system.cpu0.itb.walker.walks 3349 +system.cpu0.itb.walker.walksShort 3349 +system.cpu0.itb.walker.walksShortTerminationLevel::Level1 299 +system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3050 +system.cpu0.itb.walker.walkWaitTime::samples 3349 +system.cpu0.itb.walker.walkWaitTime::0 3349 100.00% 100.00% +system.cpu0.itb.walker.walkWaitTime::total 3349 +system.cpu0.itb.walker.walkCompletionTime::samples 2333 +system.cpu0.itb.walker.walkCompletionTime::mean 13009.858551 +system.cpu0.itb.walker.walkCompletionTime::gmean 12064.182996 +system.cpu0.itb.walker.walkCompletionTime::stdev 6171.150068 +system.cpu0.itb.walker.walkCompletionTime::0-8191 364 15.60% 15.60% +system.cpu0.itb.walker.walkCompletionTime::8192-16383 1659 71.11% 86.71% +system.cpu0.itb.walker.walkCompletionTime::16384-24575 218 9.34% 96.06% +system.cpu0.itb.walker.walkCompletionTime::24576-32767 44 1.89% 97.94% +system.cpu0.itb.walker.walkCompletionTime::32768-40959 45 1.93% 99.87% +system.cpu0.itb.walker.walkCompletionTime::49152-57343 1 0.04% 99.91% +system.cpu0.itb.walker.walkCompletionTime::98304-106495 1 0.04% 99.96% +system.cpu0.itb.walker.walkCompletionTime::122880-131071 1 0.04% 100.00% +system.cpu0.itb.walker.walkCompletionTime::total 2333 +system.cpu0.itb.walker.walksPending::samples 1180899500 +system.cpu0.itb.walker.walksPending::0 1180899500 100.00% 100.00% +system.cpu0.itb.walker.walksPending::total 1180899500 +system.cpu0.itb.walker.walkPageSizes::4K 2034 87.18% 87.18% +system.cpu0.itb.walker.walkPageSizes::1M 299 12.82% 100.00% +system.cpu0.itb.walker.walkPageSizes::total 2333 +system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3349 +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3349 +system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2333 +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2333 +system.cpu0.itb.walker.walkRequestOrigin::total 5682 +system.cpu0.itb.inst_hits 118651077 +system.cpu0.itb.inst_misses 3349 +system.cpu0.itb.read_hits 0 +system.cpu0.itb.read_misses 0 +system.cpu0.itb.write_hits 0 +system.cpu0.itb.write_misses 0 +system.cpu0.itb.flush_tlb 66 +system.cpu0.itb.flush_tlb_mva 917 +system.cpu0.itb.flush_tlb_mva_asid 0 +system.cpu0.itb.flush_tlb_asid 0 +system.cpu0.itb.flush_entries 2087 +system.cpu0.itb.align_faults 0 +system.cpu0.itb.prefetch_faults 0 +system.cpu0.itb.domain_faults 0 +system.cpu0.itb.perms_faults 0 +system.cpu0.itb.read_accesses 0 +system.cpu0.itb.write_accesses 0 +system.cpu0.itb.inst_accesses 118654426 +system.cpu0.itb.hits 118651077 +system.cpu0.itb.misses 3349 +system.cpu0.itb.accesses 118654426 +system.cpu0.numPwrStateTransitions 3724 +system.cpu0.pwrStateClkGateDist::samples 1862 +system.cpu0.pwrStateClkGateDist::mean 1466914321.975295 +system.cpu0.pwrStateClkGateDist::stdev 23730695905.598595 +system.cpu0.pwrStateClkGateDist::underflows 1082 58.11% 58.11% +system.cpu0.pwrStateClkGateDist::1000-5e+10 775 41.62% 99.73% +system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.05% 99.79% +system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 4 0.21% 100.00% +system.cpu0.pwrStateClkGateDist::min_value 501 +system.cpu0.pwrStateClkGateDist::max_value 499964525704 +system.cpu0.pwrStateClkGateDist::total 1862 +system.cpu0.pwrStateResidencyTicks::ON 139617887982 +system.cpu0.pwrStateResidencyTicks::CLK_GATED 2731394467518 +system.cpu0.numCycles 5742024711 +system.cpu0.numWorkItemsStarted 0 +system.cpu0.numWorkItemsCompleted 0 +system.cpu0.kern.inst.arm 0 +system.cpu0.kern.inst.quiesce 1862 +system.cpu0.committedInsts 114989095 +system.cpu0.committedOps 138953395 +system.cpu0.num_int_alu_accesses 122990229 +system.cpu0.num_fp_alu_accesses 9755 +system.cpu0.num_func_calls 12658538 +system.cpu0.num_conditional_control_insts 15642727 +system.cpu0.num_int_insts 122990229 +system.cpu0.num_fp_insts 9755 +system.cpu0.num_int_register_reads 226428267 +system.cpu0.num_int_register_writes 85458801 +system.cpu0.num_fp_register_reads 7495 +system.cpu0.num_fp_register_writes 2264 +system.cpu0.num_cc_register_reads 503412465 +system.cpu0.num_cc_register_writes 52088929 +system.cpu0.num_mem_refs 44904529 +system.cpu0.num_load_insts 25328869 +system.cpu0.num_store_insts 19575660 +system.cpu0.num_idle_cycles 5462788935.034097 +system.cpu0.num_busy_cycles 279235775.965903 +system.cpu0.not_idle_fraction 0.048630 +system.cpu0.idle_fraction 0.951370 +system.cpu0.Branches 29038037 +system.cpu0.op_class::No_OpClass 2273 0.00% 0.00% +system.cpu0.op_class::IntAlu 97689121 68.45% 68.45% +system.cpu0.op_class::IntMult 108461 0.08% 68.53% +system.cpu0.op_class::IntDiv 0 0.00% 68.53% +system.cpu0.op_class::FloatAdd 0 0.00% 68.53% +system.cpu0.op_class::FloatCmp 0 0.00% 68.53% +system.cpu0.op_class::FloatCvt 0 0.00% 68.53% +system.cpu0.op_class::FloatMult 0 0.00% 68.53% +system.cpu0.op_class::FloatMultAcc 0 0.00% 68.53% +system.cpu0.op_class::FloatDiv 0 0.00% 68.53% +system.cpu0.op_class::FloatMisc 0 0.00% 68.53% +system.cpu0.op_class::FloatSqrt 0 0.00% 68.53% +system.cpu0.op_class::SimdAdd 0 0.00% 68.53% +system.cpu0.op_class::SimdAddAcc 0 0.00% 68.53% +system.cpu0.op_class::SimdAlu 0 0.00% 68.53% +system.cpu0.op_class::SimdCmp 0 0.00% 68.53% +system.cpu0.op_class::SimdCvt 0 0.00% 68.53% +system.cpu0.op_class::SimdMisc 0 0.00% 68.53% +system.cpu0.op_class::SimdMult 0 0.00% 68.53% +system.cpu0.op_class::SimdMultAcc 0 0.00% 68.53% +system.cpu0.op_class::SimdShift 0 0.00% 68.53% +system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.53% +system.cpu0.op_class::SimdSqrt 0 0.00% 68.53% +system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.53% +system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.53% +system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.53% +system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.53% +system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.53% +system.cpu0.op_class::SimdFloatMisc 7991 0.01% 68.53% +system.cpu0.op_class::SimdFloatMult 0 0.00% 68.53% +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.53% +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.53% +system.cpu0.op_class::MemRead 25326613 17.75% 86.28% +system.cpu0.op_class::MemWrite 19568165 13.71% 99.99% +system.cpu0.op_class::FloatMemRead 2256 0.00% 99.99% +system.cpu0.op_class::FloatMemWrite 7495 0.01% 100.00% +system.cpu0.op_class::IprAccess 0 0.00% 100.00% +system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% +system.cpu0.op_class::total 142712375 +system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2871012355500 +system.cpu0.dcache.tags.replacements 689805 +system.cpu0.dcache.tags.tagsinuse 498.372694 +system.cpu0.dcache.tags.total_refs 42903858 +system.cpu0.dcache.tags.sampled_refs 690317 +system.cpu0.dcache.tags.avg_refs 62.150951 +system.cpu0.dcache.tags.warmup_cycle 1207348000 +system.cpu0.dcache.tags.occ_blocks::cpu0.data 498.372694 +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.973384 +system.cpu0.dcache.tags.occ_percent::total 0.973384 +system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 101 +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 316 +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 95 +system.cpu0.dcache.tags.occ_task_id_percent::1024 1 +system.cpu0.dcache.tags.tag_accesses 88178135 +system.cpu0.dcache.tags.data_accesses 88178135 +system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2871012355500 +system.cpu0.dcache.ReadReq_hits::cpu0.data 23822310 +system.cpu0.dcache.ReadReq_hits::total 23822310 +system.cpu0.dcache.WriteReq_hits::cpu0.data 17962514 +system.cpu0.dcache.WriteReq_hits::total 17962514 +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 318853 +system.cpu0.dcache.SoftPFReq_hits::total 318853 +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 364520 +system.cpu0.dcache.LoadLockedReq_hits::total 364520 +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 361475 +system.cpu0.dcache.StoreCondReq_hits::total 361475 +system.cpu0.dcache.demand_hits::cpu0.data 41784824 +system.cpu0.dcache.demand_hits::total 41784824 +system.cpu0.dcache.overall_hits::cpu0.data 42103677 +system.cpu0.dcache.overall_hits::total 42103677 +system.cpu0.dcache.ReadReq_misses::cpu0.data 394535 +system.cpu0.dcache.ReadReq_misses::total 394535 +system.cpu0.dcache.WriteReq_misses::cpu0.data 324202 +system.cpu0.dcache.WriteReq_misses::total 324202 +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 126994 +system.cpu0.dcache.SoftPFReq_misses::total 126994 +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21422 +system.cpu0.dcache.LoadLockedReq_misses::total 21422 +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 19571 +system.cpu0.dcache.StoreCondReq_misses::total 19571 +system.cpu0.dcache.demand_misses::cpu0.data 718737 +system.cpu0.dcache.demand_misses::total 718737 +system.cpu0.dcache.overall_misses::cpu0.data 845731 +system.cpu0.dcache.overall_misses::total 845731 +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5513220000 +system.cpu0.dcache.ReadReq_miss_latency::total 5513220000 +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 6311049000 +system.cpu0.dcache.WriteReq_miss_latency::total 6311049000 +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 337488500 +system.cpu0.dcache.LoadLockedReq_miss_latency::total 337488500 +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 459190500 +system.cpu0.dcache.StoreCondReq_miss_latency::total 459190500 +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1100000 +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1100000 +system.cpu0.dcache.demand_miss_latency::cpu0.data 11824269000 +system.cpu0.dcache.demand_miss_latency::total 11824269000 +system.cpu0.dcache.overall_miss_latency::cpu0.data 11824269000 +system.cpu0.dcache.overall_miss_latency::total 11824269000 +system.cpu0.dcache.ReadReq_accesses::cpu0.data 24216845 +system.cpu0.dcache.ReadReq_accesses::total 24216845 +system.cpu0.dcache.WriteReq_accesses::cpu0.data 18286716 +system.cpu0.dcache.WriteReq_accesses::total 18286716 +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 445847 +system.cpu0.dcache.SoftPFReq_accesses::total 445847 +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 385942 +system.cpu0.dcache.LoadLockedReq_accesses::total 385942 +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381046 +system.cpu0.dcache.StoreCondReq_accesses::total 381046 +system.cpu0.dcache.demand_accesses::cpu0.data 42503561 +system.cpu0.dcache.demand_accesses::total 42503561 +system.cpu0.dcache.overall_accesses::cpu0.data 42949408 +system.cpu0.dcache.overall_accesses::total 42949408 +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.016292 +system.cpu0.dcache.ReadReq_miss_rate::total 0.016292 +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.017729 +system.cpu0.dcache.WriteReq_miss_rate::total 0.017729 +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.284838 +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.284838 +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.055506 +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.055506 +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.051361 +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051361 +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.016910 +system.cpu0.dcache.demand_miss_rate::total 0.016910 +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.019691 +system.cpu0.dcache.overall_miss_rate::total 0.019691 +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13973.969356 +system.cpu0.dcache.ReadReq_avg_miss_latency::total 13973.969356 +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 19466.409831 +system.cpu0.dcache.WriteReq_avg_miss_latency::total 19466.409831 +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15754.294650 +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15754.294650 +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23462.802105 +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23462.802105 +system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf +system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16451.454426 +system.cpu0.dcache.demand_avg_miss_latency::total 16451.454426 +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 13981.122839 +system.cpu0.dcache.overall_avg_miss_latency::total 13981.122839 +system.cpu0.dcache.blocked_cycles::no_mshrs 0 +system.cpu0.dcache.blocked_cycles::no_targets 0 +system.cpu0.dcache.blocked::no_mshrs 0 +system.cpu0.dcache.blocked::no_targets 0 +system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan +system.cpu0.dcache.avg_blocked_cycles::no_targets nan +system.cpu0.dcache.writebacks::writebacks 689805 +system.cpu0.dcache.writebacks::total 689805 +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 25204 +system.cpu0.dcache.ReadReq_mshr_hits::total 25204 +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 15035 +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 15035 +system.cpu0.dcache.demand_mshr_hits::cpu0.data 25204 +system.cpu0.dcache.demand_mshr_hits::total 25204 +system.cpu0.dcache.overall_mshr_hits::cpu0.data 25204 +system.cpu0.dcache.overall_mshr_hits::total 25204 +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 369331 +system.cpu0.dcache.ReadReq_mshr_misses::total 369331 +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 324202 +system.cpu0.dcache.WriteReq_mshr_misses::total 324202 +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 100006 +system.cpu0.dcache.SoftPFReq_mshr_misses::total 100006 +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6387 +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6387 +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 19571 +system.cpu0.dcache.StoreCondReq_mshr_misses::total 19571 +system.cpu0.dcache.demand_mshr_misses::cpu0.data 693533 +system.cpu0.dcache.demand_mshr_misses::total 693533 +system.cpu0.dcache.overall_mshr_misses::cpu0.data 793539 +system.cpu0.dcache.overall_mshr_misses::total 793539 +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 31749 +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31749 +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 28437 +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 28437 +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 60186 +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 60186 +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4735470000 +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4735470000 +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5986847000 +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5986847000 +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1652052500 +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1652052500 +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 101426000 +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 101426000 +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 439651500 +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 439651500 +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1068000 +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1068000 +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10722317000 +system.cpu0.dcache.demand_mshr_miss_latency::total 10722317000 +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 12374369500 +system.cpu0.dcache.overall_mshr_miss_latency::total 12374369500 +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6628151500 +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6628151500 +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6628151500 +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6628151500 +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.015251 +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.015251 +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.017729 +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017729 +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.224306 +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.224306 +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016549 +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016549 +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051361 +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051361 +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016317 +system.cpu0.dcache.demand_mshr_miss_rate::total 0.016317 +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.018476 +system.cpu0.dcache.overall_mshr_miss_rate::total 0.018476 +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12821.750679 +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12821.750679 +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 18466.409831 +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 18466.409831 +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16519.533828 +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16519.533828 +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15880.068890 +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15880.068890 +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22464.437177 +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22464.437177 +system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf +system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 15460.427983 +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15460.427983 +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15593.902127 +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15593.902127 +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208767.252512 +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208767.252512 +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 110127.795501 +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 110127.795501 +system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2871012355500 +system.cpu0.icache.tags.replacements 1095179 +system.cpu0.icache.tags.tagsinuse 511.436914 +system.cpu0.icache.tags.total_refs 117555377 +system.cpu0.icache.tags.sampled_refs 1095691 +system.cpu0.icache.tags.avg_refs 107.288804 +system.cpu0.icache.tags.warmup_cycle 14178985000 +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.436914 +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998900 +system.cpu0.icache.tags.occ_percent::total 0.998900 +system.cpu0.icache.tags.occ_task_id_blocks::1024 512 +system.cpu0.icache.tags.age_task_id_blocks_1024::0 85 +system.cpu0.icache.tags.age_task_id_blocks_1024::1 212 +system.cpu0.icache.tags.age_task_id_blocks_1024::2 215 +system.cpu0.icache.tags.occ_task_id_percent::1024 1 +system.cpu0.icache.tags.tag_accesses 238397854 +system.cpu0.icache.tags.data_accesses 238397854 +system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2871012355500 +system.cpu0.icache.ReadReq_hits::cpu0.inst 117555377 +system.cpu0.icache.ReadReq_hits::total 117555377 +system.cpu0.icache.demand_hits::cpu0.inst 117555377 +system.cpu0.icache.demand_hits::total 117555377 +system.cpu0.icache.overall_hits::cpu0.inst 117555377 +system.cpu0.icache.overall_hits::total 117555377 +system.cpu0.icache.ReadReq_misses::cpu0.inst 1095700 +system.cpu0.icache.ReadReq_misses::total 1095700 +system.cpu0.icache.demand_misses::cpu0.inst 1095700 +system.cpu0.icache.demand_misses::total 1095700 +system.cpu0.icache.overall_misses::cpu0.inst 1095700 +system.cpu0.icache.overall_misses::total 1095700 +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 11843020000 +system.cpu0.icache.ReadReq_miss_latency::total 11843020000 +system.cpu0.icache.demand_miss_latency::cpu0.inst 11843020000 +system.cpu0.icache.demand_miss_latency::total 11843020000 +system.cpu0.icache.overall_miss_latency::cpu0.inst 11843020000 +system.cpu0.icache.overall_miss_latency::total 11843020000 +system.cpu0.icache.ReadReq_accesses::cpu0.inst 118651077 +system.cpu0.icache.ReadReq_accesses::total 118651077 +system.cpu0.icache.demand_accesses::cpu0.inst 118651077 +system.cpu0.icache.demand_accesses::total 118651077 +system.cpu0.icache.overall_accesses::cpu0.inst 118651077 +system.cpu0.icache.overall_accesses::total 118651077 +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.009235 +system.cpu0.icache.ReadReq_miss_rate::total 0.009235 +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.009235 +system.cpu0.icache.demand_miss_rate::total 0.009235 +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.009235 +system.cpu0.icache.overall_miss_rate::total 0.009235 +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10808.633750 +system.cpu0.icache.ReadReq_avg_miss_latency::total 10808.633750 +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10808.633750 +system.cpu0.icache.demand_avg_miss_latency::total 10808.633750 +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10808.633750 +system.cpu0.icache.overall_avg_miss_latency::total 10808.633750 +system.cpu0.icache.blocked_cycles::no_mshrs 0 +system.cpu0.icache.blocked_cycles::no_targets 0 +system.cpu0.icache.blocked::no_mshrs 0 +system.cpu0.icache.blocked::no_targets 0 +system.cpu0.icache.avg_blocked_cycles::no_mshrs nan +system.cpu0.icache.avg_blocked_cycles::no_targets nan +system.cpu0.icache.writebacks::writebacks 1095179 +system.cpu0.icache.writebacks::total 1095179 +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1095700 +system.cpu0.icache.ReadReq_mshr_misses::total 1095700 +system.cpu0.icache.demand_mshr_misses::cpu0.inst 1095700 +system.cpu0.icache.demand_mshr_misses::total 1095700 +system.cpu0.icache.overall_mshr_misses::cpu0.inst 1095700 +system.cpu0.icache.overall_mshr_misses::total 1095700 +system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 9022 +system.cpu0.icache.ReadReq_mshr_uncacheable::total 9022 +system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 9022 +system.cpu0.icache.overall_mshr_uncacheable_misses::total 9022 +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 11295170000 +system.cpu0.icache.ReadReq_mshr_miss_latency::total 11295170000 +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 11295170000 +system.cpu0.icache.demand_mshr_miss_latency::total 11295170000 +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 11295170000 +system.cpu0.icache.overall_mshr_miss_latency::total 11295170000 +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 863305500 +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 863305500 +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 863305500 +system.cpu0.icache.overall_mshr_uncacheable_latency::total 863305500 +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.009235 +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009235 +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.009235 +system.cpu0.icache.demand_mshr_miss_rate::total 0.009235 +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.009235 +system.cpu0.icache.overall_mshr_miss_rate::total 0.009235 +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10308.633750 +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10308.633750 +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10308.633750 +system.cpu0.icache.demand_avg_mshr_miss_latency::total 10308.633750 +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10308.633750 +system.cpu0.icache.overall_avg_mshr_miss_latency::total 10308.633750 +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 95688.927067 +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 95688.927067 +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 95688.927067 +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 95688.927067 +system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2871012355500 +system.cpu0.l2cache.prefetcher.num_hwpf_issued 1843113 +system.cpu0.l2cache.prefetcher.pfIdentified 1843139 +system.cpu0.l2cache.prefetcher.pfBufferHit 23 +system.cpu0.l2cache.prefetcher.pfInCache 0 +system.cpu0.l2cache.prefetcher.pfRemovedFull 0 +system.cpu0.l2cache.prefetcher.pfSpanPage 237133 +system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2871012355500 +system.cpu0.l2cache.tags.replacements 260188 +system.cpu0.l2cache.tags.tagsinuse 15622.540020 +system.cpu0.l2cache.tags.total_refs 1673934 +system.cpu0.l2cache.tags.sampled_refs 275818 +system.cpu0.l2cache.tags.avg_refs 6.068980 +system.cpu0.l2cache.tags.warmup_cycle 0 +system.cpu0.l2cache.tags.occ_blocks::writebacks 14428.533255 +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 1.383166 +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.133380 +system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1192.490219 +system.cpu0.l2cache.tags.occ_percent::writebacks 0.880648 +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000084 +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000008 +system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.072784 +system.cpu0.l2cache.tags.occ_percent::total 0.953524 +system.cpu0.l2cache.tags.occ_task_id_blocks::1022 319 +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 8 +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15303 +system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 5 +system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 19 +system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 135 +system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 160 +system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 1 +system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 1 +system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 3 +system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 3 +system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 180 +system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 824 +system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 6032 +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 6210 +system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2057 +system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.019470 +system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000488 +system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.934021 +system.cpu0.l2cache.tags.tag_accesses 60936102 +system.cpu0.l2cache.tags.data_accesses 60936102 +system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 2871012355500 +system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 9959 +system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 4459 +system.cpu0.l2cache.ReadReq_hits::total 14418 +system.cpu0.l2cache.WritebackDirty_hits::writebacks 473817 +system.cpu0.l2cache.WritebackDirty_hits::total 473817 +system.cpu0.l2cache.WritebackClean_hits::writebacks 1283425 +system.cpu0.l2cache.WritebackClean_hits::total 1283425 +system.cpu0.l2cache.ReadExReq_hits::cpu0.data 226628 +system.cpu0.l2cache.ReadExReq_hits::total 226628 +system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1033356 +system.cpu0.l2cache.ReadCleanReq_hits::total 1033356 +system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 374606 +system.cpu0.l2cache.ReadSharedReq_hits::total 374606 +system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 9959 +system.cpu0.l2cache.demand_hits::cpu0.itb.walker 4459 +system.cpu0.l2cache.demand_hits::cpu0.inst 1033356 +system.cpu0.l2cache.demand_hits::cpu0.data 601234 +system.cpu0.l2cache.demand_hits::total 1649008 +system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 9959 +system.cpu0.l2cache.overall_hits::cpu0.itb.walker 4459 +system.cpu0.l2cache.overall_hits::cpu0.inst 1033356 +system.cpu0.l2cache.overall_hits::cpu0.data 601234 +system.cpu0.l2cache.overall_hits::total 1649008 +system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 299 +system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 184 +system.cpu0.l2cache.ReadReq_misses::total 483 +system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 54615 +system.cpu0.l2cache.UpgradeReq_misses::total 54615 +system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 19569 +system.cpu0.l2cache.SCUpgradeReq_misses::total 19569 +system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 2 +system.cpu0.l2cache.SCUpgradeFailReq_misses::total 2 +system.cpu0.l2cache.ReadExReq_misses::cpu0.data 42959 +system.cpu0.l2cache.ReadExReq_misses::total 42959 +system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 62344 +system.cpu0.l2cache.ReadCleanReq_misses::total 62344 +system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 101118 +system.cpu0.l2cache.ReadSharedReq_misses::total 101118 +system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 299 +system.cpu0.l2cache.demand_misses::cpu0.itb.walker 184 +system.cpu0.l2cache.demand_misses::cpu0.inst 62344 +system.cpu0.l2cache.demand_misses::cpu0.data 144077 +system.cpu0.l2cache.demand_misses::total 206904 +system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 299 +system.cpu0.l2cache.overall_misses::cpu0.itb.walker 184 +system.cpu0.l2cache.overall_misses::cpu0.inst 62344 +system.cpu0.l2cache.overall_misses::cpu0.data 144077 +system.cpu0.l2cache.overall_misses::total 206904 +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 7929000 +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 4346000 +system.cpu0.l2cache.ReadReq_miss_latency::total 12275000 +system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 29867500 +system.cpu0.l2cache.UpgradeReq_miss_latency::total 29867500 +system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 9063000 +system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 9063000 +system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 1019499 +system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 1019499 +system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 2761074000 +system.cpu0.l2cache.ReadExReq_miss_latency::total 2761074000 +system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 3428129000 +system.cpu0.l2cache.ReadCleanReq_miss_latency::total 3428129000 +system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 3333472000 +system.cpu0.l2cache.ReadSharedReq_miss_latency::total 3333472000 +system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 7929000 +system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 4346000 +system.cpu0.l2cache.demand_miss_latency::cpu0.inst 3428129000 +system.cpu0.l2cache.demand_miss_latency::cpu0.data 6094546000 +system.cpu0.l2cache.demand_miss_latency::total 9534950000 +system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 7929000 +system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 4346000 +system.cpu0.l2cache.overall_miss_latency::cpu0.inst 3428129000 +system.cpu0.l2cache.overall_miss_latency::cpu0.data 6094546000 +system.cpu0.l2cache.overall_miss_latency::total 9534950000 +system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 10258 +system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 4643 +system.cpu0.l2cache.ReadReq_accesses::total 14901 +system.cpu0.l2cache.WritebackDirty_accesses::writebacks 473817 +system.cpu0.l2cache.WritebackDirty_accesses::total 473817 +system.cpu0.l2cache.WritebackClean_accesses::writebacks 1283425 +system.cpu0.l2cache.WritebackClean_accesses::total 1283425 +system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 54615 +system.cpu0.l2cache.UpgradeReq_accesses::total 54615 +system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 19569 +system.cpu0.l2cache.SCUpgradeReq_accesses::total 19569 +system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 2 +system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 2 +system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 269587 +system.cpu0.l2cache.ReadExReq_accesses::total 269587 +system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 1095700 +system.cpu0.l2cache.ReadCleanReq_accesses::total 1095700 +system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 475724 +system.cpu0.l2cache.ReadSharedReq_accesses::total 475724 +system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 10258 +system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 4643 +system.cpu0.l2cache.demand_accesses::cpu0.inst 1095700 +system.cpu0.l2cache.demand_accesses::cpu0.data 745311 +system.cpu0.l2cache.demand_accesses::total 1855912 +system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 10258 +system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 4643 +system.cpu0.l2cache.overall_accesses::cpu0.inst 1095700 +system.cpu0.l2cache.overall_accesses::cpu0.data 745311 +system.cpu0.l2cache.overall_accesses::total 1855912 +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.029148 +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.039630 +system.cpu0.l2cache.ReadReq_miss_rate::total 0.032414 +system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 1 +system.cpu0.l2cache.UpgradeReq_miss_rate::total 1 +system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 +system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 +system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 +system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 +system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.159351 +system.cpu0.l2cache.ReadExReq_miss_rate::total 0.159351 +system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.056899 +system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.056899 +system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.212556 +system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.212556 +system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.029148 +system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.039630 +system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.056899 +system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.193311 +system.cpu0.l2cache.demand_miss_rate::total 0.111484 +system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.029148 +system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.039630 +system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.056899 +system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.193311 +system.cpu0.l2cache.overall_miss_rate::total 0.111484 +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 26518.394649 +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 23619.565217 +system.cpu0.l2cache.ReadReq_avg_miss_latency::total 25414.078675 +system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 546.873570 +system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 546.873570 +system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 463.130461 +system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 463.130461 +system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 509749.500000 +system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 509749.500000 +system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 64272.306152 +system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 64272.306152 +system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 54987.312332 +system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 54987.312332 +system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 32966.158350 +system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 32966.158350 +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 26518.394649 +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 23619.565217 +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 54987.312332 +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 42300.617031 +system.cpu0.l2cache.demand_avg_miss_latency::total 46083.932645 +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 26518.394649 +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 23619.565217 +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 54987.312332 +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 42300.617031 +system.cpu0.l2cache.overall_avg_miss_latency::total 46083.932645 +system.cpu0.l2cache.blocked_cycles::no_mshrs 0 +system.cpu0.l2cache.blocked_cycles::no_targets 0 +system.cpu0.l2cache.blocked::no_mshrs 0 +system.cpu0.l2cache.blocked::no_targets 0 +system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan +system.cpu0.l2cache.avg_blocked_cycles::no_targets nan +system.cpu0.l2cache.unused_prefetches 10455 +system.cpu0.l2cache.writebacks::writebacks 227367 +system.cpu0.l2cache.writebacks::total 227367 +system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 1570 +system.cpu0.l2cache.ReadExReq_mshr_hits::total 1570 +system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 31 +system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 31 +system.cpu0.l2cache.demand_mshr_hits::cpu0.data 1601 +system.cpu0.l2cache.demand_mshr_hits::total 1601 +system.cpu0.l2cache.overall_mshr_hits::cpu0.data 1601 +system.cpu0.l2cache.overall_mshr_hits::total 1601 +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 299 +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 184 +system.cpu0.l2cache.ReadReq_mshr_misses::total 483 +system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 261615 +system.cpu0.l2cache.HardPFReq_mshr_misses::total 261615 +system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 54615 +system.cpu0.l2cache.UpgradeReq_mshr_misses::total 54615 +system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 19569 +system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 19569 +system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 2 +system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 2 +system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 41389 +system.cpu0.l2cache.ReadExReq_mshr_misses::total 41389 +system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 62344 +system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 62344 +system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 101087 +system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 101087 +system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 299 +system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 184 +system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 62344 +system.cpu0.l2cache.demand_mshr_misses::cpu0.data 142476 +system.cpu0.l2cache.demand_mshr_misses::total 205303 +system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 299 +system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 184 +system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 62344 +system.cpu0.l2cache.overall_mshr_misses::cpu0.data 142476 +system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 261615 +system.cpu0.l2cache.overall_mshr_misses::total 466918 +system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 9022 +system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 31749 +system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 40771 +system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 28437 +system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 28437 +system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 9022 +system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 60186 +system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 69208 +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 6135000 +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 3242000 +system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 9377000 +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 16780241511 +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 16780241511 +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 936352000 +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 936352000 +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 293047000 +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 293047000 +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 827499 +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 827499 +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 2230059000 +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 2230059000 +system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 3054065000 +system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 3054065000 +system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 2721246000 +system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 2721246000 +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 6135000 +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 3242000 +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 3054065000 +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 4951305000 +system.cpu0.l2cache.demand_mshr_miss_latency::total 8014747000 +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 6135000 +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 3242000 +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 3054065000 +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 4951305000 +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 16780241511 +system.cpu0.l2cache.overall_mshr_miss_latency::total 24794988511 +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 795640500 +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 6373749000 +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 7169389500 +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 795640500 +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 6373749000 +system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 7169389500 +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.029148 +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.039630 +system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.032414 +system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf +system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 1 +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 1 +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.153527 +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.153527 +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.056899 +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.056899 +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.212491 +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.212491 +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.029148 +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.039630 +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.056899 +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.191163 +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.110621 +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.029148 +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.039630 +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.056899 +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.191163 +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.251584 +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 20518.394649 +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17619.565217 +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 19414.078675 +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 64140.976286 +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 64140.976286 +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17144.593976 +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17144.593976 +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14975.062599 +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14975.062599 +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 413749.500000 +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 413749.500000 +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 53880.475489 +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 53880.475489 +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 48987.312332 +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 48987.312332 +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 26919.841325 +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 26919.841325 +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 20518.394649 +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17619.565217 +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 48987.312332 +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 34751.852944 +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 39038.625836 +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 20518.394649 +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17619.565217 +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 48987.312332 +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 34751.852944 +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 64140.976286 +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 53103.518200 +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 88188.927067 +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200754.322971 +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 175845.318977 +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 88188.927067 +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 105900.857342 +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 103591.918564 +system.cpu0.toL2Bus.snoop_filter.tot_requests 3711991 +system.cpu0.toL2Bus.snoop_filter.hit_single_requests 1871014 +system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 27755 +system.cpu0.toL2Bus.snoop_filter.tot_snoops 210749 +system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 209099 +system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 1650 +system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2871012355500 +system.cpu0.toL2Bus.trans_dist::ReadReq 61374 +system.cpu0.toL2Bus.trans_dist::ReadResp 1680590 +system.cpu0.toL2Bus.trans_dist::WriteReq 28437 +system.cpu0.toL2Bus.trans_dist::WriteResp 28437 +system.cpu0.toL2Bus.trans_dist::WritebackDirty 701494 +system.cpu0.toL2Bus.trans_dist::WritebackClean 1311167 +system.cpu0.toL2Bus.trans_dist::CleanEvict 80057 +system.cpu0.toL2Bus.trans_dist::HardPFReq 307806 +system.cpu0.toL2Bus.trans_dist::HardPFResp 1 +system.cpu0.toL2Bus.trans_dist::UpgradeReq 87002 +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 41728 +system.cpu0.toL2Bus.trans_dist::UpgradeResp 111716 +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 47 +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 77 +system.cpu0.toL2Bus.trans_dist::ReadExReq 288659 +system.cpu0.toL2Bus.trans_dist::ReadExResp 285181 +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1095700 +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 562192 +system.cpu0.toL2Bus.trans_dist::InvalidateReq 3242 +system.cpu0.toL2Bus.trans_dist::InvalidateResp 12 +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3304623 +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2550205 +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 11042 +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 24434 +system.cpu0.toL2Bus.pkt_count::total 5890304 +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 140252344 +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 96102318 +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 18572 +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 41032 +system.cpu0.toL2Bus.pkt_size::total 236414266 +system.cpu0.toL2Bus.snoops 885649 +system.cpu0.toL2Bus.snoopTraffic 18655284 +system.cpu0.toL2Bus.snoop_fanout::samples 2783921 +system.cpu0.toL2Bus.snoop_fanout::mean 0.090513 +system.cpu0.toL2Bus.snoop_fanout::stdev 0.288974 +system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% +system.cpu0.toL2Bus.snoop_fanout::0 2533590 91.01% 91.01% +system.cpu0.toL2Bus.snoop_fanout::1 248681 8.93% 99.94% +system.cpu0.toL2Bus.snoop_fanout::2 1650 0.06% 100.00% +system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% +system.cpu0.toL2Bus.snoop_fanout::min_value 0 +system.cpu0.toL2Bus.snoop_fanout::max_value 2 +system.cpu0.toL2Bus.snoop_fanout::total 2783921 +system.cpu0.toL2Bus.reqLayer0.occupancy 3694185498 +system.cpu0.toL2Bus.reqLayer0.utilization 0.1 +system.cpu0.toL2Bus.snoopLayer0.occupancy 114034527 +system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 +system.cpu0.toL2Bus.respLayer0.occupancy 1652572000 +system.cpu0.toL2Bus.respLayer0.utilization 0.1 +system.cpu0.toL2Bus.respLayer1.occupancy 1201064489 +system.cpu0.toL2Bus.respLayer1.utilization 0.0 +system.cpu0.toL2Bus.respLayer2.occupancy 6399000 +system.cpu0.toL2Bus.respLayer2.utilization 0.0 +system.cpu0.toL2Bus.respLayer3.occupancy 14180491 +system.cpu0.toL2Bus.respLayer3.utilization 0.0 +system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2871012355500 +system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 +system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 +system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 +system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 +system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 +system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 +system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 +system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 +system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 +system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 +system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 +system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 +system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 +system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 +system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 +system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 +system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 +system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 +system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 +system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 +system.cpu1.dstage2_mmu.stage2_tlb.hits 0 +system.cpu1.dstage2_mmu.stage2_tlb.misses 0 +system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 +system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2871012355500 +system.cpu1.dtb.walker.walks 3373 +system.cpu1.dtb.walker.walksShort 3373 +system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 671 +system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 2702 +system.cpu1.dtb.walker.walkWaitTime::samples 3373 +system.cpu1.dtb.walker.walkWaitTime::0 3373 100.00% 100.00% +system.cpu1.dtb.walker.walkWaitTime::total 3373 +system.cpu1.dtb.walker.walkCompletionTime::samples 2603 +system.cpu1.dtb.walker.walkCompletionTime::mean 12478.486362 +system.cpu1.dtb.walker.walkCompletionTime::gmean 11546.344109 +system.cpu1.dtb.walker.walkCompletionTime::stdev 5610.903902 +system.cpu1.dtb.walker.walkCompletionTime::0-8191 607 23.32% 23.32% +system.cpu1.dtb.walker.walkCompletionTime::8192-16383 1682 64.62% 87.94% +system.cpu1.dtb.walker.walkCompletionTime::16384-24575 233 8.95% 96.89% +system.cpu1.dtb.walker.walkCompletionTime::24576-32767 66 2.54% 99.42% +system.cpu1.dtb.walker.walkCompletionTime::32768-40959 9 0.35% 99.77% +system.cpu1.dtb.walker.walkCompletionTime::40960-49151 3 0.12% 99.88% +system.cpu1.dtb.walker.walkCompletionTime::57344-65535 2 0.08% 99.96% +system.cpu1.dtb.walker.walkCompletionTime::98304-106495 1 0.04% 100.00% +system.cpu1.dtb.walker.walkCompletionTime::total 2603 +system.cpu1.dtb.walker.walksPending::samples -1937787828 +system.cpu1.dtb.walker.walksPending::0 -1937787828 100.00% 100.00% +system.cpu1.dtb.walker.walksPending::total -1937787828 +system.cpu1.dtb.walker.walkPageSizes::4K 1940 74.53% 74.53% +system.cpu1.dtb.walker.walkPageSizes::1M 663 25.47% 100.00% +system.cpu1.dtb.walker.walkPageSizes::total 2603 +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 3373 +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 3373 +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2603 +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2603 +system.cpu1.dtb.walker.walkRequestOrigin::total 5976 +system.cpu1.dtb.inst_hits 0 +system.cpu1.dtb.inst_misses 0 +system.cpu1.dtb.read_hits 3953610 +system.cpu1.dtb.read_misses 2858 +system.cpu1.dtb.write_hits 3430069 +system.cpu1.dtb.write_misses 515 +system.cpu1.dtb.flush_tlb 66 +system.cpu1.dtb.flush_tlb_mva 917 +system.cpu1.dtb.flush_tlb_mva_asid 0 +system.cpu1.dtb.flush_tlb_asid 0 +system.cpu1.dtb.flush_entries 1978 +system.cpu1.dtb.align_faults 0 +system.cpu1.dtb.prefetch_faults 342 +system.cpu1.dtb.domain_faults 0 +system.cpu1.dtb.perms_faults 163 +system.cpu1.dtb.read_accesses 3956468 +system.cpu1.dtb.write_accesses 3430584 +system.cpu1.dtb.inst_accesses 0 +system.cpu1.dtb.hits 7383679 +system.cpu1.dtb.misses 3373 +system.cpu1.dtb.accesses 7387052 +system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2871012355500 +system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 +system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 +system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 +system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 +system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 +system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 +system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 +system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 +system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 +system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 +system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 +system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 +system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 +system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 +system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 +system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 +system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 +system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 +system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 +system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 +system.cpu1.istage2_mmu.stage2_tlb.hits 0 +system.cpu1.istage2_mmu.stage2_tlb.misses 0 +system.cpu1.istage2_mmu.stage2_tlb.accesses 0 +system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2871012355500 +system.cpu1.itb.walker.walks 1746 +system.cpu1.itb.walker.walksShort 1746 +system.cpu1.itb.walker.walksShortTerminationLevel::Level1 168 +system.cpu1.itb.walker.walksShortTerminationLevel::Level2 1578 +system.cpu1.itb.walker.walkWaitTime::samples 1746 +system.cpu1.itb.walker.walkWaitTime::0 1746 100.00% 100.00% +system.cpu1.itb.walker.walkWaitTime::total 1746 +system.cpu1.itb.walker.walkCompletionTime::samples 1107 +system.cpu1.itb.walker.walkCompletionTime::mean 12838.301716 +system.cpu1.itb.walker.walkCompletionTime::gmean 11944.354322 +system.cpu1.itb.walker.walkCompletionTime::stdev 5752.116994 +system.cpu1.itb.walker.walkCompletionTime::4096-8191 161 14.54% 14.54% +system.cpu1.itb.walker.walkCompletionTime::8192-12287 638 57.63% 72.18% +system.cpu1.itb.walker.walkCompletionTime::12288-16383 160 14.45% 86.63% +system.cpu1.itb.walker.walkCompletionTime::16384-20479 48 4.34% 90.97% +system.cpu1.itb.walker.walkCompletionTime::20480-24575 40 3.61% 94.58% +system.cpu1.itb.walker.walkCompletionTime::24576-28671 29 2.62% 97.20% +system.cpu1.itb.walker.walkCompletionTime::28672-32767 16 1.45% 98.64% +system.cpu1.itb.walker.walkCompletionTime::32768-36863 6 0.54% 99.19% +system.cpu1.itb.walker.walkCompletionTime::36864-40959 3 0.27% 99.46% +system.cpu1.itb.walker.walkCompletionTime::40960-45055 4 0.36% 99.82% +system.cpu1.itb.walker.walkCompletionTime::49152-53247 2 0.18% 100.00% +system.cpu1.itb.walker.walkCompletionTime::total 1107 +system.cpu1.itb.walker.walksPending::samples -1938367828 +system.cpu1.itb.walker.walksPending::0 -1938367828 100.00% 100.00% +system.cpu1.itb.walker.walksPending::total -1938367828 +system.cpu1.itb.walker.walkPageSizes::4K 939 84.82% 84.82% +system.cpu1.itb.walker.walkPageSizes::1M 168 15.18% 100.00% +system.cpu1.itb.walker.walkPageSizes::total 1107 +system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 1746 +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 1746 +system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1107 +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1107 +system.cpu1.itb.walker.walkRequestOrigin::total 2853 +system.cpu1.itb.inst_hits 16665543 +system.cpu1.itb.inst_misses 1746 +system.cpu1.itb.read_hits 0 +system.cpu1.itb.read_misses 0 +system.cpu1.itb.write_hits 0 +system.cpu1.itb.write_misses 0 +system.cpu1.itb.flush_tlb 66 +system.cpu1.itb.flush_tlb_mva 917 +system.cpu1.itb.flush_tlb_mva_asid 0 +system.cpu1.itb.flush_tlb_asid 0 +system.cpu1.itb.flush_entries 1084 +system.cpu1.itb.align_faults 0 +system.cpu1.itb.prefetch_faults 0 +system.cpu1.itb.domain_faults 0 +system.cpu1.itb.perms_faults 0 +system.cpu1.itb.read_accesses 0 +system.cpu1.itb.write_accesses 0 +system.cpu1.itb.inst_accesses 16667289 +system.cpu1.itb.hits 16665543 +system.cpu1.itb.misses 1746 +system.cpu1.itb.accesses 16667289 +system.cpu1.numPwrStateTransitions 5457 +system.cpu1.pwrStateClkGateDist::samples 2729 +system.cpu1.pwrStateClkGateDist::mean 1042331816.440454 +system.cpu1.pwrStateClkGateDist::stdev 25865412745.750839 +system.cpu1.pwrStateClkGateDist::underflows 1950 71.45% 71.45% +system.cpu1.pwrStateClkGateDist::1000-5e+10 773 28.33% 99.78% +system.cpu1.pwrStateClkGateDist::5e+10-1e+11 2 0.07% 99.85% +system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 1 0.04% 99.89% +system.cpu1.pwrStateClkGateDist::5e+11-5.5e+11 1 0.04% 99.93% +system.cpu1.pwrStateClkGateDist::8e+11-8.5e+11 1 0.04% 99.96% +system.cpu1.pwrStateClkGateDist::9e+11-9.5e+11 1 0.04% 100.00% +system.cpu1.pwrStateClkGateDist::min_value 501 +system.cpu1.pwrStateClkGateDist::max_value 929980418584 +system.cpu1.pwrStateClkGateDist::total 2729 +system.cpu1.pwrStateResidencyTicks::ON 26488828434 +system.cpu1.pwrStateResidencyTicks::CLK_GATED 2844523527066 +system.cpu1.numCycles 5741091540 +system.cpu1.numWorkItemsStarted 0 +system.cpu1.numWorkItemsCompleted 0 +system.cpu1.kern.inst.arm 0 +system.cpu1.kern.inst.quiesce 2729 +system.cpu1.committedInsts 16310250 +system.cpu1.committedOps 19861699 +system.cpu1.num_int_alu_accesses 17893275 +system.cpu1.num_fp_alu_accesses 1792 +system.cpu1.num_func_calls 1028889 +system.cpu1.num_conditional_control_insts 1844355 +system.cpu1.num_int_insts 17893275 +system.cpu1.num_fp_insts 1792 +system.cpu1.num_int_register_reads 32455374 +system.cpu1.num_int_register_writes 12541370 +system.cpu1.num_fp_register_reads 1276 +system.cpu1.num_fp_register_writes 516 +system.cpu1.num_cc_register_reads 72563559 +system.cpu1.num_cc_register_writes 6509295 +system.cpu1.num_mem_refs 7617254 +system.cpu1.num_load_insts 4064765 +system.cpu1.num_store_insts 3552489 +system.cpu1.num_idle_cycles 5688122492.849936 +system.cpu1.num_busy_cycles 52969047.150064 +system.cpu1.not_idle_fraction 0.009226 +system.cpu1.idle_fraction 0.990774 +system.cpu1.Branches 2953035 +system.cpu1.op_class::No_OpClass 66 0.00% 0.00% +system.cpu1.op_class::IntAlu 12565444 62.17% 62.17% +system.cpu1.op_class::IntMult 26315 0.13% 62.30% +system.cpu1.op_class::IntDiv 0 0.00% 62.30% +system.cpu1.op_class::FloatAdd 0 0.00% 62.30% +system.cpu1.op_class::FloatCmp 0 0.00% 62.30% +system.cpu1.op_class::FloatCvt 0 0.00% 62.30% +system.cpu1.op_class::FloatMult 0 0.00% 62.30% +system.cpu1.op_class::FloatMultAcc 0 0.00% 62.30% +system.cpu1.op_class::FloatDiv 0 0.00% 62.30% +system.cpu1.op_class::FloatMisc 0 0.00% 62.30% +system.cpu1.op_class::FloatSqrt 0 0.00% 62.30% +system.cpu1.op_class::SimdAdd 0 0.00% 62.30% +system.cpu1.op_class::SimdAddAcc 0 0.00% 62.30% +system.cpu1.op_class::SimdAlu 0 0.00% 62.30% +system.cpu1.op_class::SimdCmp 0 0.00% 62.30% +system.cpu1.op_class::SimdCvt 0 0.00% 62.30% +system.cpu1.op_class::SimdMisc 0 0.00% 62.30% +system.cpu1.op_class::SimdMult 0 0.00% 62.30% +system.cpu1.op_class::SimdMultAcc 0 0.00% 62.30% +system.cpu1.op_class::SimdShift 0 0.00% 62.30% +system.cpu1.op_class::SimdShiftAcc 0 0.00% 62.30% +system.cpu1.op_class::SimdSqrt 0 0.00% 62.30% +system.cpu1.op_class::SimdFloatAdd 0 0.00% 62.30% +system.cpu1.op_class::SimdFloatAlu 0 0.00% 62.30% +system.cpu1.op_class::SimdFloatCmp 0 0.00% 62.30% +system.cpu1.op_class::SimdFloatCvt 0 0.00% 62.30% +system.cpu1.op_class::SimdFloatDiv 0 0.00% 62.30% +system.cpu1.op_class::SimdFloatMisc 3279 0.02% 62.31% +system.cpu1.op_class::SimdFloatMult 0 0.00% 62.31% +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 62.31% +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 62.31% +system.cpu1.op_class::MemRead 4064249 20.11% 82.42% +system.cpu1.op_class::MemWrite 3551213 17.57% 99.99% +system.cpu1.op_class::FloatMemRead 516 0.00% 99.99% +system.cpu1.op_class::FloatMemWrite 1276 0.01% 100.00% +system.cpu1.op_class::IprAccess 0 0.00% 100.00% +system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% +system.cpu1.op_class::total 20212358 +system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2871012355500 +system.cpu1.dcache.tags.replacements 187431 +system.cpu1.dcache.tags.tagsinuse 470.676841 +system.cpu1.dcache.tags.total_refs 7112504 +system.cpu1.dcache.tags.sampled_refs 187790 +system.cpu1.dcache.tags.avg_refs 37.874775 +system.cpu1.dcache.tags.warmup_cycle 128171950500 +system.cpu1.dcache.tags.occ_blocks::cpu1.data 470.676841 +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.919291 +system.cpu1.dcache.tags.occ_percent::total 0.919291 +system.cpu1.dcache.tags.occ_task_id_blocks::1024 359 +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 326 +system.cpu1.dcache.tags.age_task_id_blocks_1024::3 33 +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.701172 +system.cpu1.dcache.tags.tag_accesses 14986603 +system.cpu1.dcache.tags.data_accesses 14986603 +system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 2871012355500 +system.cpu1.dcache.ReadReq_hits::cpu1.data 3641806 +system.cpu1.dcache.ReadReq_hits::total 3641806 +system.cpu1.dcache.WriteReq_hits::cpu1.data 3241391 +system.cpu1.dcache.WriteReq_hits::total 3241391 +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 49016 +system.cpu1.dcache.SoftPFReq_hits::total 49016 +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 78939 +system.cpu1.dcache.LoadLockedReq_hits::total 78939 +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 70838 +system.cpu1.dcache.StoreCondReq_hits::total 70838 +system.cpu1.dcache.demand_hits::cpu1.data 6883197 +system.cpu1.dcache.demand_hits::total 6883197 +system.cpu1.dcache.overall_hits::cpu1.data 6932213 +system.cpu1.dcache.overall_hits::total 6932213 +system.cpu1.dcache.ReadReq_misses::cpu1.data 133558 +system.cpu1.dcache.ReadReq_misses::total 133558 +system.cpu1.dcache.WriteReq_misses::cpu1.data 91998 +system.cpu1.dcache.WriteReq_misses::total 91998 +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30315 +system.cpu1.dcache.SoftPFReq_misses::total 30315 +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 16925 +system.cpu1.dcache.LoadLockedReq_misses::total 16925 +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23216 +system.cpu1.dcache.StoreCondReq_misses::total 23216 +system.cpu1.dcache.demand_misses::cpu1.data 225556 +system.cpu1.dcache.demand_misses::total 225556 +system.cpu1.dcache.overall_misses::cpu1.data 255871 +system.cpu1.dcache.overall_misses::total 255871 +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2046359000 +system.cpu1.dcache.ReadReq_miss_latency::total 2046359000 +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2539064000 +system.cpu1.dcache.WriteReq_miss_latency::total 2539064000 +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 322888000 +system.cpu1.dcache.LoadLockedReq_miss_latency::total 322888000 +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 544466000 +system.cpu1.dcache.StoreCondReq_miss_latency::total 544466000 +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1954500 +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1954500 +system.cpu1.dcache.demand_miss_latency::cpu1.data 4585423000 +system.cpu1.dcache.demand_miss_latency::total 4585423000 +system.cpu1.dcache.overall_miss_latency::cpu1.data 4585423000 +system.cpu1.dcache.overall_miss_latency::total 4585423000 +system.cpu1.dcache.ReadReq_accesses::cpu1.data 3775364 +system.cpu1.dcache.ReadReq_accesses::total 3775364 +system.cpu1.dcache.WriteReq_accesses::cpu1.data 3333389 +system.cpu1.dcache.WriteReq_accesses::total 3333389 +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 79331 +system.cpu1.dcache.SoftPFReq_accesses::total 79331 +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 95864 +system.cpu1.dcache.LoadLockedReq_accesses::total 95864 +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 94054 +system.cpu1.dcache.StoreCondReq_accesses::total 94054 +system.cpu1.dcache.demand_accesses::cpu1.data 7108753 +system.cpu1.dcache.demand_accesses::total 7108753 +system.cpu1.dcache.overall_accesses::cpu1.data 7188084 +system.cpu1.dcache.overall_accesses::total 7188084 +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.035376 +system.cpu1.dcache.ReadReq_miss_rate::total 0.035376 +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.027599 +system.cpu1.dcache.WriteReq_miss_rate::total 0.027599 +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.382133 +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.382133 +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.176552 +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.176552 +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.246837 +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.246837 +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.031729 +system.cpu1.dcache.demand_miss_rate::total 0.031729 +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.035597 +system.cpu1.dcache.overall_miss_rate::total 0.035597 +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15321.875140 +system.cpu1.dcache.ReadReq_avg_miss_latency::total 15321.875140 +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 27599.121720 +system.cpu1.dcache.WriteReq_avg_miss_latency::total 27599.121720 +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19077.577548 +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19077.577548 +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23452.188146 +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23452.188146 +system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf +system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20329.421518 +system.cpu1.dcache.demand_avg_miss_latency::total 20329.421518 +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17920.839017 +system.cpu1.dcache.overall_avg_miss_latency::total 17920.839017 +system.cpu1.dcache.blocked_cycles::no_mshrs 0 +system.cpu1.dcache.blocked_cycles::no_targets 0 +system.cpu1.dcache.blocked::no_mshrs 0 +system.cpu1.dcache.blocked::no_targets 0 +system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan +system.cpu1.dcache.avg_blocked_cycles::no_targets nan +system.cpu1.dcache.writebacks::writebacks 187431 +system.cpu1.dcache.writebacks::total 187431 +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 249 +system.cpu1.dcache.ReadReq_mshr_hits::total 249 +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 11949 +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 11949 +system.cpu1.dcache.demand_mshr_hits::cpu1.data 249 +system.cpu1.dcache.demand_mshr_hits::total 249 +system.cpu1.dcache.overall_mshr_hits::cpu1.data 249 +system.cpu1.dcache.overall_mshr_hits::total 249 +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 133309 +system.cpu1.dcache.ReadReq_mshr_misses::total 133309 +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 91998 +system.cpu1.dcache.WriteReq_mshr_misses::total 91998 +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 29631 +system.cpu1.dcache.SoftPFReq_mshr_misses::total 29631 +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4976 +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4976 +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23216 +system.cpu1.dcache.StoreCondReq_mshr_misses::total 23216 +system.cpu1.dcache.demand_mshr_misses::cpu1.data 225307 +system.cpu1.dcache.demand_mshr_misses::total 225307 +system.cpu1.dcache.overall_mshr_misses::cpu1.data 254938 +system.cpu1.dcache.overall_mshr_misses::total 254938 +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 3078 +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 3078 +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2433 +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2433 +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 5511 +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 5511 +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1902134500 +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1902134500 +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2447066000 +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2447066000 +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 508307000 +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 508307000 +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 91230500 +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 91230500 +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 521295000 +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 521295000 +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1909500 +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1909500 +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4349200500 +system.cpu1.dcache.demand_mshr_miss_latency::total 4349200500 +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4857507500 +system.cpu1.dcache.overall_mshr_miss_latency::total 4857507500 +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 442716500 +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 442716500 +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 442716500 +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 442716500 +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035310 +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035310 +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027599 +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027599 +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.373511 +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.373511 +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.051907 +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.051907 +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.246837 +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.246837 +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031694 +system.cpu1.dcache.demand_mshr_miss_rate::total 0.031694 +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035467 +system.cpu1.dcache.overall_mshr_miss_rate::total 0.035467 +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14268.612772 +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14268.612772 +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26599.121720 +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 26599.121720 +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17154.567851 +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17154.567851 +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 18334.103698 +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 18334.103698 +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22454.126465 +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22454.126465 +system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf +system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19303.441526 +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19303.441526 +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19053.681679 +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19053.681679 +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 143832.521118 +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 143832.521118 +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 80333.242606 +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 80333.242606 +system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 2871012355500 +system.cpu1.icache.tags.replacements 503490 +system.cpu1.icache.tags.tagsinuse 498.455633 +system.cpu1.icache.tags.total_refs 16161536 +system.cpu1.icache.tags.sampled_refs 504002 +system.cpu1.icache.tags.avg_refs 32.066412 +system.cpu1.icache.tags.warmup_cycle 85409649000 +system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.455633 +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.973546 +system.cpu1.icache.tags.occ_percent::total 0.973546 +system.cpu1.icache.tags.occ_task_id_blocks::1024 512 +system.cpu1.icache.tags.age_task_id_blocks_1024::2 390 +system.cpu1.icache.tags.age_task_id_blocks_1024::3 118 +system.cpu1.icache.tags.age_task_id_blocks_1024::4 4 +system.cpu1.icache.tags.occ_task_id_percent::1024 1 +system.cpu1.icache.tags.tag_accesses 33835078 +system.cpu1.icache.tags.data_accesses 33835078 +system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 2871012355500 +system.cpu1.icache.ReadReq_hits::cpu1.inst 16161536 +system.cpu1.icache.ReadReq_hits::total 16161536 +system.cpu1.icache.demand_hits::cpu1.inst 16161536 +system.cpu1.icache.demand_hits::total 16161536 +system.cpu1.icache.overall_hits::cpu1.inst 16161536 +system.cpu1.icache.overall_hits::total 16161536 +system.cpu1.icache.ReadReq_misses::cpu1.inst 504002 +system.cpu1.icache.ReadReq_misses::total 504002 +system.cpu1.icache.demand_misses::cpu1.inst 504002 +system.cpu1.icache.demand_misses::total 504002 +system.cpu1.icache.overall_misses::cpu1.inst 504002 +system.cpu1.icache.overall_misses::total 504002 +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4763497000 +system.cpu1.icache.ReadReq_miss_latency::total 4763497000 +system.cpu1.icache.demand_miss_latency::cpu1.inst 4763497000 +system.cpu1.icache.demand_miss_latency::total 4763497000 +system.cpu1.icache.overall_miss_latency::cpu1.inst 4763497000 +system.cpu1.icache.overall_miss_latency::total 4763497000 +system.cpu1.icache.ReadReq_accesses::cpu1.inst 16665538 +system.cpu1.icache.ReadReq_accesses::total 16665538 +system.cpu1.icache.demand_accesses::cpu1.inst 16665538 +system.cpu1.icache.demand_accesses::total 16665538 +system.cpu1.icache.overall_accesses::cpu1.inst 16665538 +system.cpu1.icache.overall_accesses::total 16665538 +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.030242 +system.cpu1.icache.ReadReq_miss_rate::total 0.030242 +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.030242 +system.cpu1.icache.demand_miss_rate::total 0.030242 +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.030242 +system.cpu1.icache.overall_miss_rate::total 0.030242 +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9451.345431 +system.cpu1.icache.ReadReq_avg_miss_latency::total 9451.345431 +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9451.345431 +system.cpu1.icache.demand_avg_miss_latency::total 9451.345431 +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9451.345431 +system.cpu1.icache.overall_avg_miss_latency::total 9451.345431 +system.cpu1.icache.blocked_cycles::no_mshrs 0 +system.cpu1.icache.blocked_cycles::no_targets 0 +system.cpu1.icache.blocked::no_mshrs 0 +system.cpu1.icache.blocked::no_targets 0 +system.cpu1.icache.avg_blocked_cycles::no_mshrs nan +system.cpu1.icache.avg_blocked_cycles::no_targets nan +system.cpu1.icache.writebacks::writebacks 503490 +system.cpu1.icache.writebacks::total 503490 +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 504002 +system.cpu1.icache.ReadReq_mshr_misses::total 504002 +system.cpu1.icache.demand_mshr_misses::cpu1.inst 504002 +system.cpu1.icache.demand_mshr_misses::total 504002 +system.cpu1.icache.overall_mshr_misses::cpu1.inst 504002 +system.cpu1.icache.overall_mshr_misses::total 504002 +system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 177 +system.cpu1.icache.ReadReq_mshr_uncacheable::total 177 +system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 177 +system.cpu1.icache.overall_mshr_uncacheable_misses::total 177 +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4511496000 +system.cpu1.icache.ReadReq_mshr_miss_latency::total 4511496000 +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4511496000 +system.cpu1.icache.demand_mshr_miss_latency::total 4511496000 +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4511496000 +system.cpu1.icache.overall_mshr_miss_latency::total 4511496000 +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 17068500 +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 17068500 +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 17068500 +system.cpu1.icache.overall_mshr_uncacheable_latency::total 17068500 +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.030242 +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.030242 +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.030242 +system.cpu1.icache.demand_mshr_miss_rate::total 0.030242 +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.030242 +system.cpu1.icache.overall_mshr_miss_rate::total 0.030242 +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8951.345431 +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8951.345431 +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8951.345431 +system.cpu1.icache.demand_avg_mshr_miss_latency::total 8951.345431 +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8951.345431 +system.cpu1.icache.overall_avg_mshr_miss_latency::total 8951.345431 +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 96432.203390 +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 96432.203390 +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 96432.203390 +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 96432.203390 +system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2871012355500 +system.cpu1.l2cache.prefetcher.num_hwpf_issued 202572 +system.cpu1.l2cache.prefetcher.pfIdentified 202572 +system.cpu1.l2cache.prefetcher.pfBufferHit 0 +system.cpu1.l2cache.prefetcher.pfInCache 0 +system.cpu1.l2cache.prefetcher.pfRemovedFull 0 +system.cpu1.l2cache.prefetcher.pfSpanPage 60748 +system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2871012355500 +system.cpu1.l2cache.tags.replacements 44193 +system.cpu1.l2cache.tags.tagsinuse 14678.581969 +system.cpu1.l2cache.tags.total_refs 602717 +system.cpu1.l2cache.tags.sampled_refs 58543 +system.cpu1.l2cache.tags.avg_refs 10.295287 +system.cpu1.l2cache.tags.warmup_cycle 0 +system.cpu1.l2cache.tags.occ_blocks::writebacks 14292.757866 +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 2.261567 +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.050949 +system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 381.511587 +system.cpu1.l2cache.tags.occ_percent::writebacks 0.872361 +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000138 +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000125 +system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.023286 +system.cpu1.l2cache.tags.occ_percent::total 0.895910 +system.cpu1.l2cache.tags.occ_task_id_blocks::1022 311 +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 13 +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14026 +system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 4 +system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 28 +system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 279 +system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 5 +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 8 +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 960 +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 2474 +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 10592 +system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.018982 +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.000793 +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.856079 +system.cpu1.l2cache.tags.tag_accesses 24270441 +system.cpu1.l2cache.tags.data_accesses 24270441 +system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 2871012355500 +system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3759 +system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1985 +system.cpu1.l2cache.ReadReq_hits::total 5744 +system.cpu1.l2cache.WritebackDirty_hits::writebacks 114489 +system.cpu1.l2cache.WritebackDirty_hits::total 114489 +system.cpu1.l2cache.WritebackClean_hits::writebacks 565349 +system.cpu1.l2cache.WritebackClean_hits::total 565349 +system.cpu1.l2cache.ReadExReq_hits::cpu1.data 27975 +system.cpu1.l2cache.ReadExReq_hits::total 27975 +system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 482558 +system.cpu1.l2cache.ReadCleanReq_hits::total 482558 +system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 98301 +system.cpu1.l2cache.ReadSharedReq_hits::total 98301 +system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 3759 +system.cpu1.l2cache.demand_hits::cpu1.itb.walker 1985 +system.cpu1.l2cache.demand_hits::cpu1.inst 482558 +system.cpu1.l2cache.demand_hits::cpu1.data 126276 +system.cpu1.l2cache.demand_hits::total 614578 +system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 3759 +system.cpu1.l2cache.overall_hits::cpu1.itb.walker 1985 +system.cpu1.l2cache.overall_hits::cpu1.inst 482558 +system.cpu1.l2cache.overall_hits::cpu1.data 126276 +system.cpu1.l2cache.overall_hits::total 614578 +system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 437 +system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 314 +system.cpu1.l2cache.ReadReq_misses::total 751 +system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 29360 +system.cpu1.l2cache.UpgradeReq_misses::total 29360 +system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 23211 +system.cpu1.l2cache.SCUpgradeReq_misses::total 23211 +system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 5 +system.cpu1.l2cache.SCUpgradeFailReq_misses::total 5 +system.cpu1.l2cache.ReadExReq_misses::cpu1.data 34663 +system.cpu1.l2cache.ReadExReq_misses::total 34663 +system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 21444 +system.cpu1.l2cache.ReadCleanReq_misses::total 21444 +system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 69615 +system.cpu1.l2cache.ReadSharedReq_misses::total 69615 +system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 437 +system.cpu1.l2cache.demand_misses::cpu1.itb.walker 314 +system.cpu1.l2cache.demand_misses::cpu1.inst 21444 +system.cpu1.l2cache.demand_misses::cpu1.data 104278 +system.cpu1.l2cache.demand_misses::total 126473 +system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 437 +system.cpu1.l2cache.overall_misses::cpu1.itb.walker 314 +system.cpu1.l2cache.overall_misses::cpu1.inst 21444 +system.cpu1.l2cache.overall_misses::cpu1.data 104278 +system.cpu1.l2cache.overall_misses::total 126473 +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 8992000 +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 6332500 +system.cpu1.l2cache.ReadReq_miss_latency::total 15324500 +system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 14822500 +system.cpu1.l2cache.UpgradeReq_miss_latency::total 14822500 +system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 17672000 +system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 17672000 +system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 1842000 +system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 1842000 +system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1499437000 +system.cpu1.l2cache.ReadExReq_miss_latency::total 1499437000 +system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 845964500 +system.cpu1.l2cache.ReadCleanReq_miss_latency::total 845964500 +system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 1606802500 +system.cpu1.l2cache.ReadSharedReq_miss_latency::total 1606802500 +system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 8992000 +system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 6332500 +system.cpu1.l2cache.demand_miss_latency::cpu1.inst 845964500 +system.cpu1.l2cache.demand_miss_latency::cpu1.data 3106239500 +system.cpu1.l2cache.demand_miss_latency::total 3967528500 +system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 8992000 +system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 6332500 +system.cpu1.l2cache.overall_miss_latency::cpu1.inst 845964500 +system.cpu1.l2cache.overall_miss_latency::cpu1.data 3106239500 +system.cpu1.l2cache.overall_miss_latency::total 3967528500 +system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 4196 +system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2299 +system.cpu1.l2cache.ReadReq_accesses::total 6495 +system.cpu1.l2cache.WritebackDirty_accesses::writebacks 114489 +system.cpu1.l2cache.WritebackDirty_accesses::total 114489 +system.cpu1.l2cache.WritebackClean_accesses::writebacks 565349 +system.cpu1.l2cache.WritebackClean_accesses::total 565349 +system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 29360 +system.cpu1.l2cache.UpgradeReq_accesses::total 29360 +system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23211 +system.cpu1.l2cache.SCUpgradeReq_accesses::total 23211 +system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 5 +system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 5 +system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 62638 +system.cpu1.l2cache.ReadExReq_accesses::total 62638 +system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 504002 +system.cpu1.l2cache.ReadCleanReq_accesses::total 504002 +system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 167916 +system.cpu1.l2cache.ReadSharedReq_accesses::total 167916 +system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 4196 +system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2299 +system.cpu1.l2cache.demand_accesses::cpu1.inst 504002 +system.cpu1.l2cache.demand_accesses::cpu1.data 230554 +system.cpu1.l2cache.demand_accesses::total 741051 +system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 4196 +system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2299 +system.cpu1.l2cache.overall_accesses::cpu1.inst 504002 +system.cpu1.l2cache.overall_accesses::cpu1.data 230554 +system.cpu1.l2cache.overall_accesses::total 741051 +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.104147 +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.136581 +system.cpu1.l2cache.ReadReq_miss_rate::total 0.115627 +system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 1 +system.cpu1.l2cache.UpgradeReq_miss_rate::total 1 +system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 +system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 +system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 +system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 +system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.553386 +system.cpu1.l2cache.ReadExReq_miss_rate::total 0.553386 +system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.042547 +system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.042547 +system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.414582 +system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.414582 +system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.104147 +system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.136581 +system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.042547 +system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.452293 +system.cpu1.l2cache.demand_miss_rate::total 0.170667 +system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.104147 +system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.136581 +system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.042547 +system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.452293 +system.cpu1.l2cache.overall_miss_rate::total 0.170667 +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 20576.659039 +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20167.197452 +system.cpu1.l2cache.ReadReq_avg_miss_latency::total 20405.459387 +system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 504.853542 +system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 504.853542 +system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 761.363147 +system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 761.363147 +system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 368400 +system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 368400 +system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 43257.565704 +system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 43257.565704 +system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 39449.939377 +system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 39449.939377 +system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 23081.268405 +system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 23081.268405 +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 20576.659039 +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20167.197452 +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 39449.939377 +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 29788.061720 +system.cpu1.l2cache.demand_avg_miss_latency::total 31370.557352 +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 20576.659039 +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20167.197452 +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 39449.939377 +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 29788.061720 +system.cpu1.l2cache.overall_avg_miss_latency::total 31370.557352 +system.cpu1.l2cache.blocked_cycles::no_mshrs 0 +system.cpu1.l2cache.blocked_cycles::no_targets 0 +system.cpu1.l2cache.blocked::no_mshrs 0 +system.cpu1.l2cache.blocked::no_targets 0 +system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan +system.cpu1.l2cache.avg_blocked_cycles::no_targets nan +system.cpu1.l2cache.unused_prefetches 793 +system.cpu1.l2cache.writebacks::writebacks 33199 +system.cpu1.l2cache.writebacks::total 33199 +system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 92 +system.cpu1.l2cache.ReadExReq_mshr_hits::total 92 +system.cpu1.l2cache.demand_mshr_hits::cpu1.data 92 +system.cpu1.l2cache.demand_mshr_hits::total 92 +system.cpu1.l2cache.overall_mshr_hits::cpu1.data 92 +system.cpu1.l2cache.overall_mshr_hits::total 92 +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 437 +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 314 +system.cpu1.l2cache.ReadReq_mshr_misses::total 751 +system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 26784 +system.cpu1.l2cache.HardPFReq_mshr_misses::total 26784 +system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 29360 +system.cpu1.l2cache.UpgradeReq_mshr_misses::total 29360 +system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 23211 +system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 23211 +system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 5 +system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 5 +system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 34571 +system.cpu1.l2cache.ReadExReq_mshr_misses::total 34571 +system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 21444 +system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 21444 +system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 69615 +system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 69615 +system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 437 +system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 314 +system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 21444 +system.cpu1.l2cache.demand_mshr_misses::cpu1.data 104186 +system.cpu1.l2cache.demand_mshr_misses::total 126381 +system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 437 +system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 314 +system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 21444 +system.cpu1.l2cache.overall_mshr_misses::cpu1.data 104186 +system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 26784 +system.cpu1.l2cache.overall_mshr_misses::total 153165 +system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 177 +system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 3078 +system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 3255 +system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 2433 +system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 2433 +system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 177 +system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 5511 +system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 5688 +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 6370000 +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 4448500 +system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 10818500 +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 966158428 +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 966158428 +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 448928000 +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 448928000 +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 347176000 +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 347176000 +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 1572000 +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1572000 +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1280853500 +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1280853500 +system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 717300500 +system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 717300500 +system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 1189112500 +system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 1189112500 +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 6370000 +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 4448500 +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 717300500 +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2469966000 +system.cpu1.l2cache.demand_mshr_miss_latency::total 3198085000 +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 6370000 +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 4448500 +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 717300500 +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2469966000 +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 966158428 +system.cpu1.l2cache.overall_mshr_miss_latency::total 4164243428 +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 15741000 +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 417750000 +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 433491000 +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 15741000 +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 417750000 +system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 433491000 +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.104147 +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.136581 +system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.115627 +system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf +system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 1 +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 1 +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.551917 +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.551917 +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.042547 +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.042547 +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.414582 +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.414582 +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.104147 +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.136581 +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.042547 +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.451894 +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.170543 +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.104147 +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.136581 +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.042547 +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.451894 +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.206686 +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 14576.659039 +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14167.197452 +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 14405.459387 +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 36072.223268 +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 36072.223268 +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 15290.463215 +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15290.463215 +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14957.390892 +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14957.390892 +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 314400 +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 314400 +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 37049.940702 +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 37049.940702 +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 33449.939377 +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 33449.939377 +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 17081.268405 +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 17081.268405 +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 14576.659039 +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14167.197452 +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 33449.939377 +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 23707.273530 +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 25305.109154 +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 14576.659039 +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14167.197452 +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 33449.939377 +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 23707.273530 +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 36072.223268 +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 27187.956961 +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 88932.203390 +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 135721.247563 +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 133176.958525 +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 88932.203390 +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 75802.939575 +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 76211.497890 +system.cpu1.toL2Bus.snoop_filter.tot_requests 1484455 +system.cpu1.toL2Bus.snoop_filter.hit_single_requests 749934 +system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 11083 +system.cpu1.toL2Bus.snoop_filter.tot_snoops 113020 +system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 104758 +system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 8262 +system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2871012355500 +system.cpu1.toL2Bus.trans_dist::ReadReq 12654 +system.cpu1.toL2Bus.trans_dist::ReadResp 721934 +system.cpu1.toL2Bus.trans_dist::WriteReq 2433 +system.cpu1.toL2Bus.trans_dist::WriteResp 2433 +system.cpu1.toL2Bus.trans_dist::WritebackDirty 148951 +system.cpu1.toL2Bus.trans_dist::WritebackClean 576432 +system.cpu1.toL2Bus.trans_dist::CleanEvict 28565 +system.cpu1.toL2Bus.trans_dist::HardPFReq 31873 +system.cpu1.toL2Bus.trans_dist::UpgradeReq 70743 +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 40968 +system.cpu1.toL2Bus.trans_dist::UpgradeResp 85123 +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 37 +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 77 +system.cpu1.toL2Bus.trans_dist::ReadExReq 69812 +system.cpu1.toL2Bus.trans_dist::ReadExResp 67302 +system.cpu1.toL2Bus.trans_dist::ReadCleanReq 504002 +system.cpu1.toL2Bus.trans_dist::ReadSharedReq 263233 +system.cpu1.toL2Bus.trans_dist::InvalidateReq 286 +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1511848 +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 839363 +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 5623 +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 10271 +system.cpu1.toL2Bus.pkt_count::total 2367105 +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 64480196 +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 29463938 +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 9196 +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 16784 +system.cpu1.toL2Bus.pkt_size::total 93970114 +system.cpu1.toL2Bus.snoops 334403 +system.cpu1.toL2Bus.snoopTraffic 4908896 +system.cpu1.toL2Bus.snoop_fanout::samples 1059068 +system.cpu1.toL2Bus.snoop_fanout::mean 0.131030 +system.cpu1.toL2Bus.snoop_fanout::stdev 0.359811 +system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% +system.cpu1.toL2Bus.snoop_fanout::0 928560 87.68% 87.68% +system.cpu1.toL2Bus.snoop_fanout::1 122246 11.54% 99.22% +system.cpu1.toL2Bus.snoop_fanout::2 8262 0.78% 100.00% +system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% +system.cpu1.toL2Bus.snoop_fanout::min_value 0 +system.cpu1.toL2Bus.snoop_fanout::max_value 2 +system.cpu1.toL2Bus.snoop_fanout::total 1059068 +system.cpu1.toL2Bus.reqLayer0.occupancy 1438707500 +system.cpu1.toL2Bus.reqLayer0.utilization 0.1 +system.cpu1.toL2Bus.snoopLayer0.occupancy 79416309 +system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 +system.cpu1.toL2Bus.respLayer0.occupancy 756180000 +system.cpu1.toL2Bus.respLayer0.utilization 0.0 +system.cpu1.toL2Bus.respLayer1.occupancy 376458500 +system.cpu1.toL2Bus.respLayer1.utilization 0.0 +system.cpu1.toL2Bus.respLayer2.occupancy 3324000 +system.cpu1.toL2Bus.respLayer2.utilization 0.0 +system.cpu1.toL2Bus.respLayer3.occupancy 6075499 +system.cpu1.toL2Bus.respLayer3.utilization 0.0 +system.iobus.pwrStateResidencyTicks::UNDEFINED 2871012355500 +system.iobus.trans_dist::ReadReq 31005 +system.iobus.trans_dist::ReadResp 31005 +system.iobus.trans_dist::WriteReq 59423 +system.iobus.trans_dist::WriteResp 59423 +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56604 +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 +system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 +system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 +system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 120 +system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 834 +system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 +system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 +system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 +system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 +system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 +system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 +system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 +system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 +system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 +system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 +system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 +system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 +system.iobus.pkt_count_system.bridge.master::total 107898 +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72958 +system.iobus.pkt_count_system.realview.ide.dma::total 72958 +system.iobus.pkt_count::total 180856 +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71548 +system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 +system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 +system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 +system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 +system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 84 +system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 441 +system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 +system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 +system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 +system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 +system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 +system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 +system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 +system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 +system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 +system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 +system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 +system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 +system.iobus.pkt_size_system.bridge.master::total 162788 +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321272 +system.iobus.pkt_size_system.realview.ide.dma::total 2321272 +system.iobus.pkt_size::total 2484060 +system.iobus.reqLayer0.occupancy 48603000 +system.iobus.reqLayer0.utilization 0.0 +system.iobus.reqLayer1.occupancy 106000 +system.iobus.reqLayer1.utilization 0.0 +system.iobus.reqLayer2.occupancy 319500 +system.iobus.reqLayer2.utilization 0.0 +system.iobus.reqLayer3.occupancy 31000 +system.iobus.reqLayer3.utilization 0.0 +system.iobus.reqLayer4.occupancy 15000 +system.iobus.reqLayer4.utilization 0.0 +system.iobus.reqLayer7.occupancy 89500 +system.iobus.reqLayer7.utilization 0.0 +system.iobus.reqLayer8.occupancy 615500 +system.iobus.reqLayer8.utilization 0.0 +system.iobus.reqLayer10.occupancy 22500 +system.iobus.reqLayer10.utilization 0.0 +system.iobus.reqLayer13.occupancy 10500 +system.iobus.reqLayer13.utilization 0.0 +system.iobus.reqLayer14.occupancy 11000 +system.iobus.reqLayer14.utilization 0.0 +system.iobus.reqLayer15.occupancy 11000 +system.iobus.reqLayer15.utilization 0.0 +system.iobus.reqLayer16.occupancy 46500 +system.iobus.reqLayer16.utilization 0.0 +system.iobus.reqLayer17.occupancy 11000 +system.iobus.reqLayer17.utilization 0.0 +system.iobus.reqLayer18.occupancy 10500 +system.iobus.reqLayer18.utilization 0.0 +system.iobus.reqLayer19.occupancy 2500 +system.iobus.reqLayer19.utilization 0.0 +system.iobus.reqLayer20.occupancy 9000 +system.iobus.reqLayer20.utilization 0.0 +system.iobus.reqLayer21.occupancy 10500 +system.iobus.reqLayer21.utilization 0.0 +system.iobus.reqLayer23.occupancy 6211000 +system.iobus.reqLayer23.utilization 0.0 +system.iobus.reqLayer24.occupancy 32041500 +system.iobus.reqLayer24.utilization 0.0 +system.iobus.reqLayer25.occupancy 187899763 +system.iobus.reqLayer25.utilization 0.0 +system.iobus.respLayer0.occupancy 84699000 +system.iobus.respLayer0.utilization 0.0 +system.iobus.respLayer3.occupancy 36782000 +system.iobus.respLayer3.utilization 0.0 +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2871012355500 +system.iocache.tags.replacements 36445 +system.iocache.tags.tagsinuse 14.377038 +system.iocache.tags.total_refs 0 +system.iocache.tags.sampled_refs 36461 +system.iocache.tags.avg_refs 0 +system.iocache.tags.warmup_cycle 290037968000 +system.iocache.tags.occ_blocks::realview.ide 14.377038 +system.iocache.tags.occ_percent::realview.ide 0.898565 +system.iocache.tags.occ_percent::total 0.898565 +system.iocache.tags.occ_task_id_blocks::1023 16 +system.iocache.tags.age_task_id_blocks_1023::3 16 +system.iocache.tags.occ_task_id_percent::1023 1 +system.iocache.tags.tag_accesses 328311 +system.iocache.tags.data_accesses 328311 +system.iocache.pwrStateResidencyTicks::UNDEFINED 2871012355500 +system.iocache.ReadReq_misses::realview.ide 255 +system.iocache.ReadReq_misses::total 255 +system.iocache.WriteLineReq_misses::realview.ide 36224 +system.iocache.WriteLineReq_misses::total 36224 +system.iocache.demand_misses::realview.ide 36479 +system.iocache.demand_misses::total 36479 +system.iocache.overall_misses::realview.ide 36479 +system.iocache.overall_misses::total 36479 +system.iocache.ReadReq_miss_latency::realview.ide 41048377 +system.iocache.ReadReq_miss_latency::total 41048377 +system.iocache.WriteLineReq_miss_latency::realview.ide 4363745386 +system.iocache.WriteLineReq_miss_latency::total 4363745386 +system.iocache.demand_miss_latency::realview.ide 4404793763 +system.iocache.demand_miss_latency::total 4404793763 +system.iocache.overall_miss_latency::realview.ide 4404793763 +system.iocache.overall_miss_latency::total 4404793763 +system.iocache.ReadReq_accesses::realview.ide 255 +system.iocache.ReadReq_accesses::total 255 +system.iocache.WriteLineReq_accesses::realview.ide 36224 +system.iocache.WriteLineReq_accesses::total 36224 +system.iocache.demand_accesses::realview.ide 36479 +system.iocache.demand_accesses::total 36479 +system.iocache.overall_accesses::realview.ide 36479 +system.iocache.overall_accesses::total 36479 +system.iocache.ReadReq_miss_rate::realview.ide 1 +system.iocache.ReadReq_miss_rate::total 1 +system.iocache.WriteLineReq_miss_rate::realview.ide 1 +system.iocache.WriteLineReq_miss_rate::total 1 +system.iocache.demand_miss_rate::realview.ide 1 +system.iocache.demand_miss_rate::total 1 +system.iocache.overall_miss_rate::realview.ide 1 +system.iocache.overall_miss_rate::total 1 +system.iocache.ReadReq_avg_miss_latency::realview.ide 160974.027451 +system.iocache.ReadReq_avg_miss_latency::total 160974.027451 +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120465.585965 +system.iocache.WriteLineReq_avg_miss_latency::total 120465.585965 +system.iocache.demand_avg_miss_latency::realview.ide 120748.753063 +system.iocache.demand_avg_miss_latency::total 120748.753063 +system.iocache.overall_avg_miss_latency::realview.ide 120748.753063 +system.iocache.overall_avg_miss_latency::total 120748.753063 +system.iocache.blocked_cycles::no_mshrs 96 +system.iocache.blocked_cycles::no_targets 0 +system.iocache.blocked::no_mshrs 6 +system.iocache.blocked::no_targets 0 +system.iocache.avg_blocked_cycles::no_mshrs 16 +system.iocache.avg_blocked_cycles::no_targets nan +system.iocache.writebacks::writebacks 36190 +system.iocache.writebacks::total 36190 +system.iocache.ReadReq_mshr_misses::realview.ide 255 +system.iocache.ReadReq_mshr_misses::total 255 +system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 +system.iocache.WriteLineReq_mshr_misses::total 36224 +system.iocache.demand_mshr_misses::realview.ide 36479 +system.iocache.demand_mshr_misses::total 36479 +system.iocache.overall_mshr_misses::realview.ide 36479 +system.iocache.overall_mshr_misses::total 36479 +system.iocache.ReadReq_mshr_miss_latency::realview.ide 28298377 +system.iocache.ReadReq_mshr_miss_latency::total 28298377 +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2550650079 +system.iocache.WriteLineReq_mshr_miss_latency::total 2550650079 +system.iocache.demand_mshr_miss_latency::realview.ide 2578948456 +system.iocache.demand_mshr_miss_latency::total 2578948456 +system.iocache.overall_mshr_miss_latency::realview.ide 2578948456 +system.iocache.overall_mshr_miss_latency::total 2578948456 +system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 +system.iocache.ReadReq_mshr_miss_rate::total 1 +system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 +system.iocache.WriteLineReq_mshr_miss_rate::total 1 +system.iocache.demand_mshr_miss_rate::realview.ide 1 +system.iocache.demand_mshr_miss_rate::total 1 +system.iocache.overall_mshr_miss_rate::realview.ide 1 +system.iocache.overall_mshr_miss_rate::total 1 +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 110974.027451 +system.iocache.ReadReq_avg_mshr_miss_latency::total 110974.027451 +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70413.264107 +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70413.264107 +system.iocache.demand_avg_mshr_miss_latency::realview.ide 70696.796952 +system.iocache.demand_avg_mshr_miss_latency::total 70696.796952 +system.iocache.overall_avg_mshr_miss_latency::realview.ide 70696.796952 +system.iocache.overall_avg_mshr_miss_latency::total 70696.796952 +system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2871012355500 +system.l2c.tags.replacements 137349 +system.l2c.tags.tagsinuse 65074.387852 +system.l2c.tags.total_refs 526623 +system.l2c.tags.sampled_refs 202715 +system.l2c.tags.avg_refs 2.597849 +system.l2c.tags.warmup_cycle 103119965000 +system.l2c.tags.occ_blocks::writebacks 6578.412108 +system.l2c.tags.occ_blocks::cpu0.dtb.walker 4.009780 +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.050992 +system.l2c.tags.occ_blocks::cpu0.inst 7069.334997 +system.l2c.tags.occ_blocks::cpu0.data 6925.851965 +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 37440.638295 +system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.954844 +system.l2c.tags.occ_blocks::cpu1.inst 1513.332181 +system.l2c.tags.occ_blocks::cpu1.data 3159.920251 +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 2381.882439 +system.l2c.tags.occ_percent::writebacks 0.100379 +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000061 +system.l2c.tags.occ_percent::cpu0.itb.walker 0.000001 +system.l2c.tags.occ_percent::cpu0.inst 0.107869 +system.l2c.tags.occ_percent::cpu0.data 0.105680 +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.571299 +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000015 +system.l2c.tags.occ_percent::cpu1.inst 0.023092 +system.l2c.tags.occ_percent::cpu1.data 0.048217 +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.036345 +system.l2c.tags.occ_percent::total 0.992956 +system.l2c.tags.occ_task_id_blocks::1022 34273 +system.l2c.tags.occ_task_id_blocks::1023 8 +system.l2c.tags.occ_task_id_blocks::1024 31085 +system.l2c.tags.age_task_id_blocks_1022::2 136 +system.l2c.tags.age_task_id_blocks_1022::3 4607 +system.l2c.tags.age_task_id_blocks_1022::4 29530 +system.l2c.tags.age_task_id_blocks_1023::4 8 +system.l2c.tags.age_task_id_blocks_1024::0 1 +system.l2c.tags.age_task_id_blocks_1024::1 1 +system.l2c.tags.age_task_id_blocks_1024::2 77 +system.l2c.tags.age_task_id_blocks_1024::3 1172 +system.l2c.tags.age_task_id_blocks_1024::4 29834 +system.l2c.tags.occ_task_id_percent::1022 0.522964 +system.l2c.tags.occ_task_id_percent::1023 0.000122 +system.l2c.tags.occ_task_id_percent::1024 0.474319 +system.l2c.tags.tag_accesses 6115156 +system.l2c.tags.data_accesses 6115156 +system.l2c.pwrStateResidencyTicks::UNDEFINED 2871012355500 +system.l2c.WritebackDirty_hits::writebacks 260566 +system.l2c.WritebackDirty_hits::total 260566 +system.l2c.UpgradeReq_hits::cpu0.data 39877 +system.l2c.UpgradeReq_hits::cpu1.data 4951 +system.l2c.UpgradeReq_hits::total 44828 +system.l2c.SCUpgradeReq_hits::cpu0.data 2380 +system.l2c.SCUpgradeReq_hits::cpu1.data 2211 +system.l2c.SCUpgradeReq_hits::total 4591 +system.l2c.ReadExReq_hits::cpu0.data 3935 +system.l2c.ReadExReq_hits::cpu1.data 1496 +system.l2c.ReadExReq_hits::total 5431 +system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 137 +system.l2c.ReadSharedReq_hits::cpu0.itb.walker 102 +system.l2c.ReadSharedReq_hits::cpu0.inst 44443 +system.l2c.ReadSharedReq_hits::cpu0.data 52813 +system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 45878 +system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 45 +system.l2c.ReadSharedReq_hits::cpu1.itb.walker 28 +system.l2c.ReadSharedReq_hits::cpu1.inst 19063 +system.l2c.ReadSharedReq_hits::cpu1.data 11032 +system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 5457 +system.l2c.ReadSharedReq_hits::total 178998 +system.l2c.demand_hits::cpu0.dtb.walker 137 +system.l2c.demand_hits::cpu0.itb.walker 102 +system.l2c.demand_hits::cpu0.inst 44443 +system.l2c.demand_hits::cpu0.data 56748 +system.l2c.demand_hits::cpu0.l2cache.prefetcher 45878 +system.l2c.demand_hits::cpu1.dtb.walker 45 +system.l2c.demand_hits::cpu1.itb.walker 28 +system.l2c.demand_hits::cpu1.inst 19063 +system.l2c.demand_hits::cpu1.data 12528 +system.l2c.demand_hits::cpu1.l2cache.prefetcher 5457 +system.l2c.demand_hits::total 184429 +system.l2c.overall_hits::cpu0.dtb.walker 137 +system.l2c.overall_hits::cpu0.itb.walker 102 +system.l2c.overall_hits::cpu0.inst 44443 +system.l2c.overall_hits::cpu0.data 56748 +system.l2c.overall_hits::cpu0.l2cache.prefetcher 45878 +system.l2c.overall_hits::cpu1.dtb.walker 45 +system.l2c.overall_hits::cpu1.itb.walker 28 +system.l2c.overall_hits::cpu1.inst 19063 +system.l2c.overall_hits::cpu1.data 12528 +system.l2c.overall_hits::cpu1.l2cache.prefetcher 5457 +system.l2c.overall_hits::total 184429 +system.l2c.UpgradeReq_misses::cpu0.data 621 +system.l2c.UpgradeReq_misses::cpu1.data 247 +system.l2c.UpgradeReq_misses::total 868 +system.l2c.SCUpgradeReq_misses::cpu0.data 91 +system.l2c.SCUpgradeReq_misses::cpu1.data 94 +system.l2c.SCUpgradeReq_misses::total 185 +system.l2c.ReadExReq_misses::cpu0.data 11316 +system.l2c.ReadExReq_misses::cpu1.data 8031 +system.l2c.ReadExReq_misses::total 19347 +system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 7 +system.l2c.ReadSharedReq_misses::cpu0.itb.walker 2 +system.l2c.ReadSharedReq_misses::cpu0.inst 17901 +system.l2c.ReadSharedReq_misses::cpu0.data 9081 +system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 133790 +system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 1 +system.l2c.ReadSharedReq_misses::cpu1.inst 2381 +system.l2c.ReadSharedReq_misses::cpu1.data 942 +system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 6464 +system.l2c.ReadSharedReq_misses::total 170569 +system.l2c.demand_misses::cpu0.dtb.walker 7 +system.l2c.demand_misses::cpu0.itb.walker 2 +system.l2c.demand_misses::cpu0.inst 17901 +system.l2c.demand_misses::cpu0.data 20397 +system.l2c.demand_misses::cpu0.l2cache.prefetcher 133790 +system.l2c.demand_misses::cpu1.dtb.walker 1 +system.l2c.demand_misses::cpu1.inst 2381 +system.l2c.demand_misses::cpu1.data 8973 +system.l2c.demand_misses::cpu1.l2cache.prefetcher 6464 +system.l2c.demand_misses::total 189916 +system.l2c.overall_misses::cpu0.dtb.walker 7 +system.l2c.overall_misses::cpu0.itb.walker 2 +system.l2c.overall_misses::cpu0.inst 17901 +system.l2c.overall_misses::cpu0.data 20397 +system.l2c.overall_misses::cpu0.l2cache.prefetcher 133790 +system.l2c.overall_misses::cpu1.dtb.walker 1 +system.l2c.overall_misses::cpu1.inst 2381 +system.l2c.overall_misses::cpu1.data 8973 +system.l2c.overall_misses::cpu1.l2cache.prefetcher 6464 +system.l2c.overall_misses::total 189916 +system.l2c.UpgradeReq_miss_latency::cpu0.data 10529500 +system.l2c.UpgradeReq_miss_latency::cpu1.data 873500 +system.l2c.UpgradeReq_miss_latency::total 11403000 +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 530500 +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 127000 +system.l2c.SCUpgradeReq_miss_latency::total 657500 +system.l2c.ReadExReq_miss_latency::cpu0.data 1663618000 +system.l2c.ReadExReq_miss_latency::cpu1.data 833998500 +system.l2c.ReadExReq_miss_latency::total 2497616500 +system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 1167000 +system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 185500 +system.l2c.ReadSharedReq_miss_latency::cpu0.inst 1953183500 +system.l2c.ReadSharedReq_miss_latency::cpu0.data 1104956000 +system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 15968852998 +system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 90000 +system.l2c.ReadSharedReq_miss_latency::cpu1.inst 261942500 +system.l2c.ReadSharedReq_miss_latency::cpu1.data 124056500 +system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 846103917 +system.l2c.ReadSharedReq_miss_latency::total 20260537915 +system.l2c.demand_miss_latency::cpu0.dtb.walker 1167000 +system.l2c.demand_miss_latency::cpu0.itb.walker 185500 +system.l2c.demand_miss_latency::cpu0.inst 1953183500 +system.l2c.demand_miss_latency::cpu0.data 2768574000 +system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 15968852998 +system.l2c.demand_miss_latency::cpu1.dtb.walker 90000 +system.l2c.demand_miss_latency::cpu1.inst 261942500 +system.l2c.demand_miss_latency::cpu1.data 958055000 +system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 846103917 +system.l2c.demand_miss_latency::total 22758154415 +system.l2c.overall_miss_latency::cpu0.dtb.walker 1167000 +system.l2c.overall_miss_latency::cpu0.itb.walker 185500 +system.l2c.overall_miss_latency::cpu0.inst 1953183500 +system.l2c.overall_miss_latency::cpu0.data 2768574000 +system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 15968852998 +system.l2c.overall_miss_latency::cpu1.dtb.walker 90000 +system.l2c.overall_miss_latency::cpu1.inst 261942500 +system.l2c.overall_miss_latency::cpu1.data 958055000 +system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 846103917 +system.l2c.overall_miss_latency::total 22758154415 +system.l2c.WritebackDirty_accesses::writebacks 260566 +system.l2c.WritebackDirty_accesses::total 260566 +system.l2c.UpgradeReq_accesses::cpu0.data 40498 +system.l2c.UpgradeReq_accesses::cpu1.data 5198 +system.l2c.UpgradeReq_accesses::total 45696 +system.l2c.SCUpgradeReq_accesses::cpu0.data 2471 +system.l2c.SCUpgradeReq_accesses::cpu1.data 2305 +system.l2c.SCUpgradeReq_accesses::total 4776 +system.l2c.ReadExReq_accesses::cpu0.data 15251 +system.l2c.ReadExReq_accesses::cpu1.data 9527 +system.l2c.ReadExReq_accesses::total 24778 +system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 144 +system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 104 +system.l2c.ReadSharedReq_accesses::cpu0.inst 62344 +system.l2c.ReadSharedReq_accesses::cpu0.data 61894 +system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 179668 +system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 46 +system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 28 +system.l2c.ReadSharedReq_accesses::cpu1.inst 21444 +system.l2c.ReadSharedReq_accesses::cpu1.data 11974 +system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 11921 +system.l2c.ReadSharedReq_accesses::total 349567 +system.l2c.demand_accesses::cpu0.dtb.walker 144 +system.l2c.demand_accesses::cpu0.itb.walker 104 +system.l2c.demand_accesses::cpu0.inst 62344 +system.l2c.demand_accesses::cpu0.data 77145 +system.l2c.demand_accesses::cpu0.l2cache.prefetcher 179668 +system.l2c.demand_accesses::cpu1.dtb.walker 46 +system.l2c.demand_accesses::cpu1.itb.walker 28 +system.l2c.demand_accesses::cpu1.inst 21444 +system.l2c.demand_accesses::cpu1.data 21501 +system.l2c.demand_accesses::cpu1.l2cache.prefetcher 11921 +system.l2c.demand_accesses::total 374345 +system.l2c.overall_accesses::cpu0.dtb.walker 144 +system.l2c.overall_accesses::cpu0.itb.walker 104 +system.l2c.overall_accesses::cpu0.inst 62344 +system.l2c.overall_accesses::cpu0.data 77145 +system.l2c.overall_accesses::cpu0.l2cache.prefetcher 179668 +system.l2c.overall_accesses::cpu1.dtb.walker 46 +system.l2c.overall_accesses::cpu1.itb.walker 28 +system.l2c.overall_accesses::cpu1.inst 21444 +system.l2c.overall_accesses::cpu1.data 21501 +system.l2c.overall_accesses::cpu1.l2cache.prefetcher 11921 +system.l2c.overall_accesses::total 374345 +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.015334 +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.047518 +system.l2c.UpgradeReq_miss_rate::total 0.018995 +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.036827 +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.040781 +system.l2c.SCUpgradeReq_miss_rate::total 0.038735 +system.l2c.ReadExReq_miss_rate::cpu0.data 0.741984 +system.l2c.ReadExReq_miss_rate::cpu1.data 0.842973 +system.l2c.ReadExReq_miss_rate::total 0.780814 +system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.048611 +system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.019231 +system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.287133 +system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.146719 +system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.744651 +system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.021739 +system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.111033 +system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.078670 +system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.542236 +system.l2c.ReadSharedReq_miss_rate::total 0.487944 +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.048611 +system.l2c.demand_miss_rate::cpu0.itb.walker 0.019231 +system.l2c.demand_miss_rate::cpu0.inst 0.287133 +system.l2c.demand_miss_rate::cpu0.data 0.264398 +system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.744651 +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.021739 +system.l2c.demand_miss_rate::cpu1.inst 0.111033 +system.l2c.demand_miss_rate::cpu1.data 0.417329 +system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.542236 +system.l2c.demand_miss_rate::total 0.507329 +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.048611 +system.l2c.overall_miss_rate::cpu0.itb.walker 0.019231 +system.l2c.overall_miss_rate::cpu0.inst 0.287133 +system.l2c.overall_miss_rate::cpu0.data 0.264398 +system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.744651 +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.021739 +system.l2c.overall_miss_rate::cpu1.inst 0.111033 +system.l2c.overall_miss_rate::cpu1.data 0.417329 +system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.542236 +system.l2c.overall_miss_rate::total 0.507329 +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 16955.716586 +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 3536.437247 +system.l2c.UpgradeReq_avg_miss_latency::total 13137.096774 +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 5829.670330 +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 1351.063830 +system.l2c.SCUpgradeReq_avg_miss_latency::total 3554.054054 +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 147014.669495 +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 103847.403810 +system.l2c.ReadExReq_avg_miss_latency::total 129095.802967 +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 166714.285714 +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 92750 +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 109110.301100 +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 121677.788790 +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 119357.597713 +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 90000 +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 110013.649727 +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 131694.798301 +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 130894.789140 +system.l2c.ReadSharedReq_avg_miss_latency::total 118782.064238 +system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 166714.285714 +system.l2c.demand_avg_miss_latency::cpu0.itb.walker 92750 +system.l2c.demand_avg_miss_latency::cpu0.inst 109110.301100 +system.l2c.demand_avg_miss_latency::cpu0.data 135734.372702 +system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 119357.597713 +system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 90000 +system.l2c.demand_avg_miss_latency::cpu1.inst 110013.649727 +system.l2c.demand_avg_miss_latency::cpu1.data 106770.868160 +system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 130894.789140 +system.l2c.demand_avg_miss_latency::total 119832.738763 +system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 166714.285714 +system.l2c.overall_avg_miss_latency::cpu0.itb.walker 92750 +system.l2c.overall_avg_miss_latency::cpu0.inst 109110.301100 +system.l2c.overall_avg_miss_latency::cpu0.data 135734.372702 +system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 119357.597713 +system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 90000 +system.l2c.overall_avg_miss_latency::cpu1.inst 110013.649727 +system.l2c.overall_avg_miss_latency::cpu1.data 106770.868160 +system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 130894.789140 +system.l2c.overall_avg_miss_latency::total 119832.738763 +system.l2c.blocked_cycles::no_mshrs 0 +system.l2c.blocked_cycles::no_targets 0 +system.l2c.blocked::no_mshrs 0 +system.l2c.blocked::no_targets 0 +system.l2c.avg_blocked_cycles::no_mshrs nan +system.l2c.avg_blocked_cycles::no_targets nan +system.l2c.writebacks::writebacks 100516 +system.l2c.writebacks::total 100516 +system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 4 +system.l2c.ReadSharedReq_mshr_hits::cpu0.data 1 +system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 6 +system.l2c.ReadSharedReq_mshr_hits::total 11 +system.l2c.demand_mshr_hits::cpu0.inst 4 +system.l2c.demand_mshr_hits::cpu0.data 1 +system.l2c.demand_mshr_hits::cpu1.inst 6 +system.l2c.demand_mshr_hits::total 11 +system.l2c.overall_mshr_hits::cpu0.inst 4 +system.l2c.overall_mshr_hits::cpu0.data 1 +system.l2c.overall_mshr_hits::cpu1.inst 6 +system.l2c.overall_mshr_hits::total 11 +system.l2c.CleanEvict_mshr_misses::writebacks 3745 +system.l2c.CleanEvict_mshr_misses::total 3745 +system.l2c.UpgradeReq_mshr_misses::cpu0.data 621 +system.l2c.UpgradeReq_mshr_misses::cpu1.data 247 +system.l2c.UpgradeReq_mshr_misses::total 868 +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 91 +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 94 +system.l2c.SCUpgradeReq_mshr_misses::total 185 +system.l2c.ReadExReq_mshr_misses::cpu0.data 11316 +system.l2c.ReadExReq_mshr_misses::cpu1.data 8031 +system.l2c.ReadExReq_mshr_misses::total 19347 +system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 7 +system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 2 +system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 17897 +system.l2c.ReadSharedReq_mshr_misses::cpu0.data 9080 +system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 133790 +system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 1 +system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 2375 +system.l2c.ReadSharedReq_mshr_misses::cpu1.data 942 +system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 6464 +system.l2c.ReadSharedReq_mshr_misses::total 170558 +system.l2c.demand_mshr_misses::cpu0.dtb.walker 7 +system.l2c.demand_mshr_misses::cpu0.itb.walker 2 +system.l2c.demand_mshr_misses::cpu0.inst 17897 +system.l2c.demand_mshr_misses::cpu0.data 20396 +system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 133790 +system.l2c.demand_mshr_misses::cpu1.dtb.walker 1 +system.l2c.demand_mshr_misses::cpu1.inst 2375 +system.l2c.demand_mshr_misses::cpu1.data 8973 +system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 6464 +system.l2c.demand_mshr_misses::total 189905 +system.l2c.overall_mshr_misses::cpu0.dtb.walker 7 +system.l2c.overall_mshr_misses::cpu0.itb.walker 2 +system.l2c.overall_mshr_misses::cpu0.inst 17897 +system.l2c.overall_mshr_misses::cpu0.data 20396 +system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 133790 +system.l2c.overall_mshr_misses::cpu1.dtb.walker 1 +system.l2c.overall_mshr_misses::cpu1.inst 2375 +system.l2c.overall_mshr_misses::cpu1.data 8973 +system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 6464 +system.l2c.overall_mshr_misses::total 189905 +system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 9022 +system.l2c.ReadReq_mshr_uncacheable::cpu0.data 31749 +system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 177 +system.l2c.ReadReq_mshr_uncacheable::cpu1.data 3075 +system.l2c.ReadReq_mshr_uncacheable::total 44023 +system.l2c.WriteReq_mshr_uncacheable::cpu0.data 28437 +system.l2c.WriteReq_mshr_uncacheable::cpu1.data 2433 +system.l2c.WriteReq_mshr_uncacheable::total 30870 +system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 9022 +system.l2c.overall_mshr_uncacheable_misses::cpu0.data 60186 +system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 177 +system.l2c.overall_mshr_uncacheable_misses::cpu1.data 5508 +system.l2c.overall_mshr_uncacheable_misses::total 74893 +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 14716000 +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 5403500 +system.l2c.UpgradeReq_mshr_miss_latency::total 20119500 +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 2406500 +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 2245000 +system.l2c.SCUpgradeReq_mshr_miss_latency::total 4651500 +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 1550458000 +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 753688500 +system.l2c.ReadExReq_mshr_miss_latency::total 2304146500 +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 1097000 +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 165500 +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 1774101000 +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 1014092000 +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 14630948008 +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 80000 +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 237739500 +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 114635502 +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 781461422 +system.l2c.ReadSharedReq_mshr_miss_latency::total 18554319932 +system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 1097000 +system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 165500 +system.l2c.demand_mshr_miss_latency::cpu0.inst 1774101000 +system.l2c.demand_mshr_miss_latency::cpu0.data 2564550000 +system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 14630948008 +system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 80000 +system.l2c.demand_mshr_miss_latency::cpu1.inst 237739500 +system.l2c.demand_mshr_miss_latency::cpu1.data 868324002 +system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 781461422 +system.l2c.demand_mshr_miss_latency::total 20858466432 +system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 1097000 +system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 165500 +system.l2c.overall_mshr_miss_latency::cpu0.inst 1774101000 +system.l2c.overall_mshr_miss_latency::cpu0.data 2564550000 +system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 14630948008 +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 80000 +system.l2c.overall_mshr_miss_latency::cpu1.inst 237739500 +system.l2c.overall_mshr_miss_latency::cpu1.data 868324002 +system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 781461422 +system.l2c.overall_mshr_miss_latency::total 20858466432 +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 633244000 +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5802252500 +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 12555000 +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 362346000 +system.l2c.ReadReq_mshr_uncacheable_latency::total 6810397500 +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 633244000 +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 5802252500 +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 12555000 +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 362346000 +system.l2c.overall_mshr_uncacheable_latency::total 6810397500 +system.l2c.CleanEvict_mshr_miss_rate::writebacks inf +system.l2c.CleanEvict_mshr_miss_rate::total inf +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.015334 +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.047518 +system.l2c.UpgradeReq_mshr_miss_rate::total 0.018995 +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.036827 +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.040781 +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.038735 +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.741984 +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.842973 +system.l2c.ReadExReq_mshr_miss_rate::total 0.780814 +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.048611 +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.019231 +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.287069 +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.146702 +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.744651 +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.021739 +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.110754 +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.078670 +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.542236 +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.487912 +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.048611 +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.019231 +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.287069 +system.l2c.demand_mshr_miss_rate::cpu0.data 0.264385 +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.744651 +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.021739 +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.110754 +system.l2c.demand_mshr_miss_rate::cpu1.data 0.417329 +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.542236 +system.l2c.demand_mshr_miss_rate::total 0.507299 +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.048611 +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.019231 +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.287069 +system.l2c.overall_mshr_miss_rate::cpu0.data 0.264385 +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.744651 +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.021739 +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.110754 +system.l2c.overall_mshr_miss_rate::cpu1.data 0.417329 +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.542236 +system.l2c.overall_mshr_miss_rate::total 0.507299 +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 23697.262480 +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 21876.518219 +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 23179.147465 +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 26445.054945 +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 23882.978723 +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 25143.243243 +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 137014.669495 +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 93847.403810 +system.l2c.ReadExReq_avg_mshr_miss_latency::total 119095.802967 +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 156714.285714 +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 82750 +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 99128.401408 +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 111684.140969 +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109357.560416 +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 80000 +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 100100.842105 +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 121693.738854 +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 120894.403156 +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 108785.984428 +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 156714.285714 +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 82750 +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 99128.401408 +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 125737.889782 +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109357.560416 +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 80000 +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 100100.842105 +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 96770.756937 +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 120894.403156 +system.l2c.demand_avg_mshr_miss_latency::total 109836.320434 +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 156714.285714 +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 82750 +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 99128.401408 +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 125737.889782 +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109357.560416 +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 80000 +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 100100.842105 +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 96770.756937 +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 120894.403156 +system.l2c.overall_avg_mshr_miss_latency::total 109836.320434 +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 70188.871647 +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182753.866264 +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 70932.203390 +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 117836.097561 +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 154700.894987 +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 70188.871647 +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 96405.351743 +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 70932.203390 +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 65785.403050 +system.l2c.overall_avg_mshr_uncacheable_latency::total 90935.033982 +system.membus.snoop_filter.tot_requests 502622 +system.membus.snoop_filter.hit_single_requests 282245 +system.membus.snoop_filter.hit_multi_requests 635 +system.membus.snoop_filter.tot_snoops 0 +system.membus.snoop_filter.hit_single_snoops 0 +system.membus.snoop_filter.hit_multi_snoops 0 +system.membus.pwrStateResidencyTicks::UNDEFINED 2871012355500 +system.membus.trans_dist::ReadReq 44023 +system.membus.trans_dist::ReadResp 214836 +system.membus.trans_dist::WriteReq 30870 +system.membus.trans_dist::WriteResp 30870 +system.membus.trans_dist::WritebackDirty 136706 +system.membus.trans_dist::CleanEvict 16434 +system.membus.trans_dist::UpgradeReq 64435 +system.membus.trans_dist::SCUpgradeReq 38119 +system.membus.trans_dist::UpgradeResp 17 +system.membus.trans_dist::SCUpgradeFailReq 1 +system.membus.trans_dist::ReadExReq 39786 +system.membus.trans_dist::ReadExResp 19314 +system.membus.trans_dist::ReadSharedReq 170813 +system.membus.trans_dist::InvalidateReq 36224 +system.membus.trans_dist::InvalidateResp 4530 +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107898 +system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13552 +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 647420 +system.membus.pkt_count_system.l2c.mem_side::total 768904 +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72939 +system.membus.pkt_count_system.iocache.mem_side::total 72939 +system.membus.pkt_count::total 841843 +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162788 +system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27104 +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18619276 +system.membus.pkt_size_system.l2c.mem_side::total 18809236 +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 +system.membus.pkt_size_system.iocache.mem_side::total 2317120 +system.membus.pkt_size::total 21126356 +system.membus.snoops 127076 +system.membus.snoopTraffic 37632 +system.membus.snoop_fanout::samples 424271 +system.membus.snoop_fanout::mean 0.012216 +system.membus.snoop_fanout::stdev 0.109850 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 419088 98.78% 98.78% +system.membus.snoop_fanout::1 5183 1.22% 100.00% +system.membus.snoop_fanout::2 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 1 +system.membus.snoop_fanout::total 424271 +system.membus.reqLayer0.occupancy 88177000 +system.membus.reqLayer0.utilization 0.0 +system.membus.reqLayer1.occupancy 19000 +system.membus.reqLayer1.utilization 0.0 +system.membus.reqLayer2.occupancy 11309000 +system.membus.reqLayer2.utilization 0.0 +system.membus.reqLayer5.occupancy 970280052 +system.membus.reqLayer5.utilization 0.0 +system.membus.respLayer2.occupancy 1113160766 +system.membus.respLayer2.utilization 0.0 +system.membus.respLayer3.occupancy 7258187 +system.membus.respLayer3.utilization 0.0 +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2871012355500 +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2871012355500 +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2871012355500 +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2871012355500 +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2871012355500 +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2871012355500 +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2871012355500 +system.realview.dcc.osc_cpu.clock 16667 +system.realview.dcc.osc_ddr.clock 25000 +system.realview.dcc.osc_hsbm.clock 25000 +system.realview.dcc.osc_pxl.clock 42105 +system.realview.dcc.osc_smb.clock 20000 +system.realview.dcc.osc_sys.clock 16667 +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2871012355500 +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2871012355500 +system.realview.ethernet.descDMAReads 0 +system.realview.ethernet.descDMAWrites 0 +system.realview.ethernet.descDmaReadBytes 0 +system.realview.ethernet.descDmaWriteBytes 0 +system.realview.ethernet.postedSwi 0 +system.realview.ethernet.coalescedSwi nan +system.realview.ethernet.totalSwi 0 +system.realview.ethernet.postedRxIdle 0 +system.realview.ethernet.coalescedRxIdle nan +system.realview.ethernet.totalRxIdle 0 +system.realview.ethernet.postedRxOk 0 +system.realview.ethernet.coalescedRxOk nan +system.realview.ethernet.totalRxOk 0 +system.realview.ethernet.postedRxDesc 0 +system.realview.ethernet.coalescedRxDesc nan +system.realview.ethernet.totalRxDesc 0 +system.realview.ethernet.postedTxOk 0 +system.realview.ethernet.coalescedTxOk nan +system.realview.ethernet.totalTxOk 0 +system.realview.ethernet.postedTxIdle 0 +system.realview.ethernet.coalescedTxIdle nan +system.realview.ethernet.totalTxIdle 0 +system.realview.ethernet.postedTxDesc 0 +system.realview.ethernet.coalescedTxDesc nan +system.realview.ethernet.totalTxDesc 0 +system.realview.ethernet.postedRxOrn 0 +system.realview.ethernet.coalescedRxOrn nan +system.realview.ethernet.totalRxOrn 0 +system.realview.ethernet.coalescedTotal nan +system.realview.ethernet.postedInterrupts 0 +system.realview.ethernet.droppedPackets 0 +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2871012355500 +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2871012355500 +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2871012355500 +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2871012355500 +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2871012355500 +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2871012355500 +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2871012355500 +system.realview.mcc.osc_clcd.clock 42105 +system.realview.mcc.osc_mcc.clock 20000 +system.realview.mcc.osc_peripheral.clock 41667 +system.realview.mcc.osc_system_bus.clock 41667 +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2871012355500 +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2871012355500 +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2871012355500 +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2871012355500 +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2871012355500 +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2871012355500 +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2871012355500 +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2871012355500 +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2871012355500 +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2871012355500 +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2871012355500 +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2871012355500 +system.toL2Bus.snoop_filter.tot_requests 1013756 +system.toL2Bus.snoop_filter.hit_single_requests 527510 +system.toL2Bus.snoop_filter.hit_multi_requests 187290 +system.toL2Bus.snoop_filter.tot_snoops 29674 +system.toL2Bus.snoop_filter.hit_single_snoops 28443 +system.toL2Bus.snoop_filter.hit_multi_snoops 1231 +system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2871012355500 +system.toL2Bus.trans_dist::ReadReq 44026 +system.toL2Bus.trans_dist::ReadResp 511611 +system.toL2Bus.trans_dist::WriteReq 30870 +system.toL2Bus.trans_dist::WriteResp 30870 +system.toL2Bus.trans_dist::WritebackDirty 361082 +system.toL2Bus.trans_dist::CleanEvict 119910 +system.toL2Bus.trans_dist::UpgradeReq 109230 +system.toL2Bus.trans_dist::SCUpgradeReq 42710 +system.toL2Bus.trans_dist::UpgradeResp 151940 +system.toL2Bus.trans_dist::SCUpgradeFailReq 77 +system.toL2Bus.trans_dist::UpgradeFailResp 77 +system.toL2Bus.trans_dist::ReadExReq 50740 +system.toL2Bus.trans_dist::ReadExResp 50740 +system.toL2Bus.trans_dist::ReadSharedReq 467589 +system.toL2Bus.trans_dist::InvalidateReq 4574 +system.toL2Bus.trans_dist::InvalidateResp 3436 +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1274602 +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 317408 +system.toL2Bus.pkt_count::total 1592010 +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 35235610 +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 5660730 +system.toL2Bus.pkt_size::total 40896340 +system.toL2Bus.snoops 391148 +system.toL2Bus.snoopTraffic 15652684 +system.toL2Bus.snoop_fanout::samples 887182 +system.toL2Bus.snoop_fanout::mean 0.397329 +system.toL2Bus.snoop_fanout::stdev 0.492173 +system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% +system.toL2Bus.snoop_fanout::0 535910 60.41% 60.41% +system.toL2Bus.snoop_fanout::1 350041 39.46% 99.86% +system.toL2Bus.snoop_fanout::2 1231 0.14% 100.00% +system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% +system.toL2Bus.snoop_fanout::min_value 0 +system.toL2Bus.snoop_fanout::max_value 2 +system.toL2Bus.snoop_fanout::total 887182 +system.toL2Bus.reqLayer0.occupancy 894578674 +system.toL2Bus.reqLayer0.utilization 0.0 +system.toL2Bus.snoopLayer0.occupancy 2158873 +system.toL2Bus.snoopLayer0.utilization 0.0 +system.toL2Bus.respLayer0.occupancy 676162622 +system.toL2Bus.respLayer0.utilization 0.0 +system.toL2Bus.respLayer1.occupancy 239095357 +system.toL2Bus.respLayer1.utilization 0.0 ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini index 731f3d8f9..dc3e63c4b 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini @@ -12,12 +12,12 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain atags_addr=134217728 -boot_loader=/dist/m5/system/binaries/boot_emm.arm +boot_loader=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/boot_emm.arm boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1 cache_line_size=64 clk_domain=system.clk_domain default_p_state=UNDEFINED -dtb_filename=/dist/m5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb +dtb_filename=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb early_kernel_symbols=false enable_context_switch_stats_dump=false eventq_index=0 @@ -30,7 +30,7 @@ have_security=false have_virtualization=false highest_el_is_64=false init_param=0 -kernel=/dist/m5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5 +kernel=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5 kernel_addr_check=true load_addr_mask=268435455 load_offset=2147483648 @@ -49,7 +49,7 @@ panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 power_model=Null -readfile=/z/powerjg/gem5-upstream/tests/testing/../halt.sh +readfile=/usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../halt.sh reset_addr_64=0 symbolfile= thermal_components= @@ -99,7 +99,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage eventq_index=0 -image_file=/dist/m5/system/disks/linux-aarch32-ael.img +image_file=/usr/local/google/home/gabeblack/gem5/dist/m5/system/disks/linux-aarch32-ael.img read_only=true [system.clk_domain] @@ -144,6 +144,7 @@ progress_interval=0 simpoint_start_insts= socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer workload= @@ -314,8 +315,6 @@ id_aa64isar0_el1=0 id_aa64isar1_el1=0 id_aa64mmfr0_el1=15728642 id_aa64mmfr1_el1=0 -id_aa64pfr0_el1=34 -id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 @@ -326,8 +325,6 @@ id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 id_mmfr3=34611729 -id_pfr0=49 -id_pfr1=4113 midr=1091551472 pmu=Null system=system diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simerr b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simerr index 0b0f3b2cd..a37d266bb 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simerr +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simerr @@ -1,9 +1,14 @@ warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes) +info: kernel located at: /usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5 warn: Sockets disabled, not accepting vnc client connections warn: Sockets disabled, not accepting terminal connections warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Using bootloader at address 0x10 +info: Using kernel entry physical address at 0x80008000 +info: Loading DTB file: /usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb at address 0x88000000 warn: Existing EnergyCtrl, but no enabled DVFSHandler found. +info: Entering event queue @ 0. Starting simulation... warn: Not doing anything for miscreg ACTLR warn: Not doing anything for write of miscreg ACTLR warn: The clidr register always reports 0 caches. @@ -24,6 +29,21 @@ warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 +info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 warn: CP14 unimplemented crn[1], opc1[0], crm[3], opc2[4] warn: CP14 unimplemented crn[1], opc1[0], crm[0], opc2[4] warn: CP14 unimplemented crn[0], opc1[0], crm[7], opc2[0] diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout index acd6681ee..70e938951 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout @@ -3,30 +3,10 @@ Redirecting stderr to build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realv gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Nov 29 2016 19:03:48 -gem5 started Nov 29 2016 19:06:57 -gem5 executing on zizzer, pid 5768 -command line: /z/powerjg/gem5-upstream/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/fs/10.linux-boot/arm/linux/realview-simple-timing +gem5 compiled Mar 29 2017 18:44:23 +gem5 started Mar 29 2017 18:44:38 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 53278 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/fs/10.linux-boot/arm/linux/realview-simple-timing Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/m5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5 -info: Using bootloader at address 0x10 -info: Using kernel entry physical address at 0x80008000 -info: Loading DTB file: /dist/m5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb at address 0x88000000 -info: Entering event queue @ 0. Starting simulation... -info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 -info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 -info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 -info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 -info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 -info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 -info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 -info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 -info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 -info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 -info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 -info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 -info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 -info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 -info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 -Exiting @ tick 2905317504500 because m5_exit instruction encountered +Exiting @ tick 2905305537500 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt index ff7f585c6..7e3439f1a 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt @@ -1,1556 +1,1556 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.905317 # Number of seconds simulated -sim_ticks 2905316914500 # Number of ticks simulated -final_tick 2905316914500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1074625 # Simulator instruction rate (inst/s) -host_op_rate 1295669 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 27762631762 # Simulator tick rate (ticks/s) -host_mem_usage 582724 # Number of bytes of host memory used -host_seconds 104.65 # Real time elapsed on the host -sim_insts 112457861 # Number of instructions simulated -sim_ops 135589764 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.dtb.walker 448 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1186532 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 8969572 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 10157640 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1186532 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1186532 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7562240 # Number of bytes written to this memory -system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory -system.physmem.bytes_written::total 7579764 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 7 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 26993 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 140669 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 167686 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 118160 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory -system.physmem.num_writes::total 122541 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 154 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 44 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 408400 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3087296 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 330 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3496224 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 408400 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 408400 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2602897 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 6032 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2608928 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2602897 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 154 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 44 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 408400 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3093327 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 330 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6105153 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 167686 # Number of read requests accepted -system.physmem.writeReqs 122541 # Number of write requests accepted -system.physmem.readBursts 167686 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 122541 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10724160 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7744 # Total number of bytes read from write queue -system.physmem.bytesWritten 7592640 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10157640 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7579764 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 121 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 3887 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 9873 # Per bank write bursts -system.physmem.perBankRdBursts::1 9614 # Per bank write bursts -system.physmem.perBankRdBursts::2 9963 # Per bank write bursts -system.physmem.perBankRdBursts::3 9595 # Per bank write bursts -system.physmem.perBankRdBursts::4 18744 # Per bank write bursts -system.physmem.perBankRdBursts::5 9936 # Per bank write bursts -system.physmem.perBankRdBursts::6 10635 # Per bank write bursts -system.physmem.perBankRdBursts::7 11205 # Per bank write bursts -system.physmem.perBankRdBursts::8 9589 # Per bank write bursts -system.physmem.perBankRdBursts::9 10033 # Per bank write bursts -system.physmem.perBankRdBursts::10 9283 # Per bank write bursts -system.physmem.perBankRdBursts::11 8863 # Per bank write bursts -system.physmem.perBankRdBursts::12 10202 # Per bank write bursts -system.physmem.perBankRdBursts::13 10190 # Per bank write bursts -system.physmem.perBankRdBursts::14 10325 # Per bank write bursts -system.physmem.perBankRdBursts::15 9515 # Per bank write bursts -system.physmem.perBankWrBursts::0 7137 # Per bank write bursts -system.physmem.perBankWrBursts::1 7022 # Per bank write bursts -system.physmem.perBankWrBursts::2 7742 # Per bank write bursts -system.physmem.perBankWrBursts::3 7365 # Per bank write bursts -system.physmem.perBankWrBursts::4 7465 # Per bank write bursts -system.physmem.perBankWrBursts::5 7289 # Per bank write bursts -system.physmem.perBankWrBursts::6 7716 # Per bank write bursts -system.physmem.perBankWrBursts::7 8300 # Per bank write bursts -system.physmem.perBankWrBursts::8 7184 # Per bank write bursts -system.physmem.perBankWrBursts::9 7439 # Per bank write bursts -system.physmem.perBankWrBursts::10 6836 # Per bank write bursts -system.physmem.perBankWrBursts::11 6804 # Per bank write bursts -system.physmem.perBankWrBursts::12 7947 # Per bank write bursts -system.physmem.perBankWrBursts::13 7681 # Per bank write bursts -system.physmem.perBankWrBursts::14 7752 # Per bank write bursts -system.physmem.perBankWrBursts::15 6956 # Per bank write bursts -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 62 # Number of times write queue was full causing retry -system.physmem.totGap 2905316552500 # Total gap between requests -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 9558 # Read request sizes (log2) -system.physmem.readPktSize::3 14 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 158114 # Read request sizes (log2) -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 4381 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 118160 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 166731 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 559 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 263 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1867 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2821 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5995 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5894 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6231 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5852 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6236 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6586 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7526 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7121 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 8226 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 8867 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7085 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6554 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6505 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6306 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6131 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6216 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 449 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 406 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 379 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 303 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 299 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 287 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 253 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 223 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 280 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 242 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 243 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 233 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 174 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 175 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 154 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 164 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 173 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 171 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 137 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 122 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 122 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 117 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 152 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 247 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 217 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 117 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 206 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 194 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 187 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 68 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 126 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 57707 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 317.409257 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 186.502400 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 335.930049 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 20577 35.66% 35.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 14716 25.50% 61.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5644 9.78% 70.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3157 5.47% 76.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2419 4.19% 80.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1386 2.40% 83.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1272 2.20% 85.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 912 1.58% 86.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7624 13.21% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 57707 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5794 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 28.920090 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 588.859251 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 5793 99.98% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5794 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5794 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.475492 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.528054 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 14.935092 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5069 87.49% 87.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 43 0.74% 88.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 41 0.71% 88.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 52 0.90% 89.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 288 4.97% 94.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 23 0.40% 95.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 16 0.28% 95.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 7 0.12% 95.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 5 0.09% 95.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 2 0.03% 95.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 1 0.02% 95.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 5 0.09% 95.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 158 2.73% 98.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 7 0.12% 98.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 5 0.09% 98.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 5 0.09% 98.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 8 0.14% 98.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 5 0.09% 99.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 2 0.03% 99.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 2 0.03% 99.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 9 0.16% 99.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 2 0.03% 99.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 1 0.02% 99.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 2 0.03% 99.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 8 0.14% 99.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 5 0.09% 99.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 6 0.10% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 5 0.09% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 1 0.02% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 1 0.02% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 4 0.07% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 2 0.03% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 2 0.03% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-187 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5794 # Writes before turning the bus around for reads -system.physmem.totQLat 4572629500 # Total ticks spent queuing -system.physmem.totMemAccLat 7714473250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 837825000 # Total ticks spent in databus transfers -system.physmem.avgQLat 27288.69 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 46038.69 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 3.69 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.61 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 3.50 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.61 # Average system write bandwidth in MiByte/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.05 # Data bus utilization in percentage -system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.45 # Average write queue length when enqueuing -system.physmem.readRowHits 138575 # Number of row buffer hits during reads -system.physmem.writeRowHits 89917 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.70 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.78 # Row buffer hit rate for writes -system.physmem.avgGap 10010497.14 # Average gap between requests -system.physmem.pageHitRate 79.83 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 209944560 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 111588180 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 639494100 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 313387920 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 6674375760.000002 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 4793281050 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 418187520 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 13958691240 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 9415844160 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 682618118940 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 719155193400 # Total energy per rank (pJ) -system.physmem_0.averagePower 247.530722 # Core power per rank (mW) -system.physmem_0.totalIdleTime 2893187924000 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 788400750 # Time in different power states -system.physmem_0.memoryStateTime::REF 2838298000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 2838579624000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 24520427750 # Time in different power states -system.physmem_0.memoryStateTime::ACT 7978656750 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 30611507250 # Time in different power states -system.physmem_1.actEnergy 202090560 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 107409885 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 556920000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 305886780 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 6670687920.000002 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 4519112190 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 410472000 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 13651117530 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 9526323840 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 682932964665 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 718884016170 # Total energy per rank (pJ) -system.physmem_1.averagePower 247.437384 # Core power per rank (mW) -system.physmem_1.totalIdleTime 2894335317000 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 777922000 # Time in different power states -system.physmem_1.memoryStateTime::REF 2837434000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 2839590532250 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 24808008250 # Time in different power states -system.physmem_1.memoryStateTime::ACT 7366175500 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 29936842500 # Time in different power states -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states -system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu.inst 7 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 7 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu.inst 7 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 7 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu.inst 7 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 7 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states -system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). -system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). -system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. -system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. -system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states -system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.walks 9553 # Table walker walks requested -system.cpu.dtb.walker.walksShort 9553 # Table walker walks initiated with short descriptors -system.cpu.dtb.walker.walksShortTerminationLevel::Level1 1256 # Level at which table walker walks with short descriptors terminate -system.cpu.dtb.walker.walksShortTerminationLevel::Level2 8297 # Level at which table walker walks with short descriptors terminate -system.cpu.dtb.walker.walkWaitTime::samples 9553 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0 9553 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 9553 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkCompletionTime::samples 7389 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 10013.601299 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 8464.254766 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 6610.467359 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::0-16383 6588 89.16% 89.16% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::16384-32767 796 10.77% 99.93% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::81920-98303 4 0.05% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::180224-196607 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::total 7389 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walksPending::samples 1003066500 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::0 1003066500 100.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::total 1003066500 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 6180 83.64% 83.64% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::1M 1209 16.36% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 7389 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 9553 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 9553 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7389 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7389 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 16942 # Table walker requests started/completed, data/inst -system.cpu.dtb.inst_hits 0 # ITB inst hits -system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 24519746 # DTB read hits -system.cpu.dtb.read_misses 8140 # DTB read misses -system.cpu.dtb.write_hits 19605246 # DTB write hits -system.cpu.dtb.write_misses 1413 # DTB write misses -system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed -system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 4209 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 1622 # Number of TLB faults due to prefetch -system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 24527886 # DTB read accesses -system.cpu.dtb.write_accesses 19606659 # DTB write accesses -system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 44124992 # DTB hits -system.cpu.dtb.misses 9553 # DTB misses -system.cpu.dtb.accesses 44134545 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states -system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.walks 4763 # Table walker walks requested -system.cpu.itb.walker.walksShort 4763 # Table walker walks initiated with short descriptors -system.cpu.itb.walker.walksShortTerminationLevel::Level1 310 # Level at which table walker walks with short descriptors terminate -system.cpu.itb.walker.walksShortTerminationLevel::Level2 4453 # Level at which table walker walks with short descriptors terminate -system.cpu.itb.walker.walkWaitTime::samples 4763 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0 4763 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 4763 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkCompletionTime::samples 3108 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::mean 10180.341055 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::gmean 8232.055098 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::stdev 7311.468363 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::0-8191 1821 58.59% 58.59% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::8192-16383 761 24.49% 83.08% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::16384-24575 524 16.86% 99.94% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::90112-98303 1 0.03% 99.97% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::98304-106495 1 0.03% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::total 3108 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walksPending::samples 1002711000 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::0 1002711000 100.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::total 1002711000 # Table walker pending requests distribution -system.cpu.itb.walker.walkPageSizes::4K 2798 90.03% 90.03% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::1M 310 9.97% 100.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::total 3108 # Table walker page sizes translated -system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 4763 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 4763 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3108 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 3108 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 7871 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 115555708 # ITB inst hits -system.cpu.itb.inst_misses 4763 # ITB inst misses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.flush_tlb 64 # Number of times complete TLB was flushed -system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 2849 # Number of entries that have been flushed from TLB -system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 115560471 # ITB inst accesses -system.cpu.itb.hits 115555708 # DTB hits -system.cpu.itb.misses 4763 # DTB misses -system.cpu.itb.accesses 115560471 # DTB accesses -system.cpu.numPwrStateTransitions 6064 # Number of power state transitions -system.cpu.pwrStateClkGateDist::samples 3032 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::mean 887473262.784960 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::stdev 17466686239.333317 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::underflows 2968 97.89% 97.89% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::1000-5e+10 58 1.91% 99.80% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 1 0.03% 99.84% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 1 0.03% 99.87% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 1 0.03% 99.90% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 3 0.10% 100.00% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::max_value 499963437276 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::total 3032 # Distribution of time spent in the clock gated state -system.cpu.pwrStateResidencyTicks::ON 214497981736 # Cumulative time (in ticks) in various power states -system.cpu.pwrStateResidencyTicks::CLK_GATED 2690818932764 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 5810633829 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 3032 # number of quiesce instructions executed -system.cpu.committedInsts 112457861 # Number of instructions committed -system.cpu.committedOps 135589764 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 119894844 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 11290 # Number of float alu accesses -system.cpu.num_func_calls 9894754 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 15230835 # number of instructions that are conditional controls -system.cpu.num_int_insts 119894844 # number of integer instructions -system.cpu.num_fp_insts 11290 # number of float instructions -system.cpu.num_int_register_reads 218056368 # number of times the integer registers were read -system.cpu.num_int_register_writes 82647309 # number of times the integer registers were written -system.cpu.num_fp_register_reads 8578 # number of times the floating registers were read -system.cpu.num_fp_register_writes 2716 # number of times the floating registers were written -system.cpu.num_cc_register_reads 489747242 # number of times the CC registers were read -system.cpu.num_cc_register_writes 51895082 # number of times the CC registers were written -system.cpu.num_mem_refs 45405279 # number of memory refs -system.cpu.num_load_insts 24842044 # Number of load instructions -system.cpu.num_store_insts 20563235 # Number of store instructions -system.cpu.num_idle_cycles 5381637865.526148 # Number of idle cycles -system.cpu.num_busy_cycles 428995963.473852 # Number of busy cycles -system.cpu.not_idle_fraction 0.073829 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.926171 # Percentage of idle cycles -system.cpu.Branches 25919556 # Number of branches fetched -system.cpu.op_class::No_OpClass 2337 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 93179861 67.18% 67.18% # Class of executed instruction -system.cpu.op_class::IntMult 114520 0.08% 67.26% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 67.26% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 67.26% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 67.26% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 67.26% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 67.26% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 67.26% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 67.26% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 67.26% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 67.26% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 67.26% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 67.26% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 67.26% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 67.26% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 67.26% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 67.26% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 67.26% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 67.26% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 67.26% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 67.26% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 67.26% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 67.26% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 67.26% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 67.26% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 67.26% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 67.26% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 8439 0.01% 67.27% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 67.27% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.27% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.27% # Class of executed instruction -system.cpu.op_class::MemRead 24839336 17.91% 85.17% # Class of executed instruction -system.cpu.op_class::MemWrite 20554657 14.82% 99.99% # Class of executed instruction -system.cpu.op_class::FloatMemRead 2708 0.00% 99.99% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 8578 0.01% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 138710436 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 821157 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.816175 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 43232042 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 821669 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 52.614912 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 1078145500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.816175 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999641 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999641 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 356 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 96 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 177104694 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 177104694 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 23110946 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 23110946 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18822565 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18822565 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 392473 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 392473 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 443108 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 443108 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 460141 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 460141 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 41933511 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 41933511 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 42325984 # number of overall hits -system.cpu.dcache.overall_hits::total 42325984 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 401142 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 401142 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 298882 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 298882 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 118684 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 118684 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 22806 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 22806 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 700024 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 700024 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 818708 # number of overall misses -system.cpu.dcache.overall_misses::total 818708 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 6437831500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 6437831500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 14440805000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 14440805000 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 297461000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 297461000 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 166000 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 166000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 20878636500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 20878636500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 20878636500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 20878636500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 23512088 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 23512088 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 19121447 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 19121447 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 511157 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 511157 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 465914 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 465914 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 460143 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 460143 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 42633535 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 42633535 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 43144692 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 43144692 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.017061 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.017061 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015631 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.015631 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.232187 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.232187 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.048949 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.048949 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000004 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.016420 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.016420 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.018976 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.018976 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16048.759542 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 16048.759542 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48316.074571 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 48316.074571 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13043.102692 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13043.102692 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 83000 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 83000 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 29825.600979 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 29825.600979 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 25501.932924 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 25501.932924 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 76 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 19 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 4 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 685616 # number of writebacks -system.cpu.dcache.writebacks::total 685616 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 708 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 708 # number of ReadReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14278 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 14278 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 708 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 708 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 708 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 708 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 400434 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 400434 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 298882 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 298882 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 116661 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 116661 # number of SoftPFReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8528 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 8528 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 699316 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 699316 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 815977 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 815977 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 31138 # number of ReadReq MSHR uncacheable -system.cpu.dcache.ReadReq_mshr_uncacheable::total 31138 # number of ReadReq MSHR uncacheable -system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 27589 # number of WriteReq MSHR uncacheable -system.cpu.dcache.WriteReq_mshr_uncacheable::total 27589 # number of WriteReq MSHR uncacheable -system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 58727 # number of overall MSHR uncacheable misses -system.cpu.dcache.overall_mshr_uncacheable_misses::total 58727 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6012304000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6012304000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14141923000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 14141923000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1586831500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1586831500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 118977500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 118977500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 164000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 164000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 20154227000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 20154227000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 21741058500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 21741058500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6284829000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6284829000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6284829000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 6284829000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017031 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017031 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015631 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015631 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.228229 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.228229 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.018304 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.018304 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000004 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000004 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016403 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.016403 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.018913 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.018913 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15014.469301 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15014.469301 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 47316.074571 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 47316.074571 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13602.073529 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13602.073529 # average SoftPFReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13951.395403 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13951.395403 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 82000 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 82000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28819.914030 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 28819.914030 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26644.205045 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 26644.205045 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201837.915088 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201837.915088 # average ReadReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 107017.709061 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 107017.709061 # average overall mshr uncacheable latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 1700062 # number of replacements -system.cpu.icache.tags.tagsinuse 510.693087 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 113855128 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1700574 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 66.950999 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 26307743500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.693087 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.997447 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.997447 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 212 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 246 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 9 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 117256288 # Number of tag accesses -system.cpu.icache.tags.data_accesses 117256288 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 113855128 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 113855128 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 113855128 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 113855128 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 113855128 # number of overall hits -system.cpu.icache.overall_hits::total 113855128 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1700580 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1700580 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1700580 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1700580 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1700580 # number of overall misses -system.cpu.icache.overall_misses::total 1700580 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 24044969500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 24044969500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 24044969500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 24044969500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 24044969500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 24044969500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 115555708 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 115555708 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 115555708 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 115555708 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 115555708 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 115555708 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014717 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.014717 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.014717 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.014717 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.014717 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.014717 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14139.275718 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14139.275718 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14139.275718 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14139.275718 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14139.275718 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14139.275718 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 1700062 # number of writebacks -system.cpu.icache.writebacks::total 1700062 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1700580 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1700580 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1700580 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1700580 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1700580 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1700580 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 9022 # number of ReadReq MSHR uncacheable -system.cpu.icache.ReadReq_mshr_uncacheable::total 9022 # number of ReadReq MSHR uncacheable -system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 9022 # number of overall MSHR uncacheable misses -system.cpu.icache.overall_mshr_uncacheable_misses::total 9022 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22344389500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 22344389500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22344389500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 22344389500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22344389500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 22344389500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 745203000 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 745203000 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 745203000 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 745203000 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014717 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014717 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014717 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.014717 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014717 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.014717 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13139.275718 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13139.275718 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13139.275718 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 13139.275718 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13139.275718 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 13139.275718 # average overall mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 82598.426070 # average ReadReq mshr uncacheable latency -system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 82598.426070 # average ReadReq mshr uncacheable latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 82598.426070 # average overall mshr uncacheable latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 82598.426070 # average overall mshr uncacheable latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 88598 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65011.992508 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 4854149 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 154025 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 31.515332 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 147534324000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 3.050681 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.041157 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 9634.969504 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 55373.931167 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000047 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000001 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.147018 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.844939 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.992004 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 65422 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 76 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4349 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 60996 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.998260 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 40276408 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 40276408 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 5063 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2684 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 7747 # number of ReadReq hits -system.cpu.l2cache.WritebackDirty_hits::writebacks 685616 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 685616 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 1667781 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 1667781 # number of WritebackClean hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 2789 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 2789 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 167648 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 167648 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1682586 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 1682586 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 513551 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 513551 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 5063 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 2684 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 1682586 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 681199 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2371532 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 5063 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 2684 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 1682586 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 681199 # number of overall hits -system.cpu.l2cache.overall_hits::total 2371532 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 7 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 9 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 18 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 18 # number of UpgradeReq misses -system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses -system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 128427 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 128427 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 17978 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 17978 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 12072 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 12072 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.dtb.walker 7 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 17978 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 140499 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 158486 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.dtb.walker 7 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 17978 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 140499 # number of overall misses -system.cpu.l2cache.overall_misses::total 158486 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 1154000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 180000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 1334000 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 525000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 525000 # number of UpgradeReq miss cycles -system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 161000 # number of SCUpgradeReq miss cycles -system.cpu.l2cache.SCUpgradeReq_miss_latency::total 161000 # number of SCUpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 11899913500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 11899913500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2066366000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 2066366000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1520063000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 1520063000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 1154000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 180000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 2066366000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 13419976500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 15487676500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 1154000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 180000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 2066366000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 13419976500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 15487676500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 5070 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 2686 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 7756 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::writebacks 685616 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 685616 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 1667781 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 1667781 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2807 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 2807 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 296075 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 296075 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1700564 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 1700564 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 525623 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 525623 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 5070 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 2686 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 1700564 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 821698 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2530018 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 5070 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 2686 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1700564 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 821698 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2530018 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.001381 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000745 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.001160 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.006413 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.006413 # miss rate for UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.433765 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.433765 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.010572 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.010572 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.022967 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.022967 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.001381 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000745 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010572 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.170986 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.062642 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.001381 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000745 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010572 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.170986 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.062642 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 164857.142857 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 90000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 148222.222222 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 29166.666667 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 29166.666667 # average UpgradeReq miss latency -system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 80500 # average SCUpgradeReq miss latency -system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 80500 # average SCUpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 92658.969687 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 92658.969687 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 114938.591612 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 114938.591612 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 125916.418158 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 125916.418158 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 164857.142857 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 90000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 114938.591612 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 95516.526808 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 97722.678975 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 164857.142857 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 90000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 114938.591612 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 95516.526808 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 97722.678975 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 81970 # number of writebacks -system.cpu.l2cache.writebacks::total 81970 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 7 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 9 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 18 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 18 # number of UpgradeReq MSHR misses -system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses -system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 128427 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 128427 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 17978 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 17978 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 12072 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 12072 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 7 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 17978 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 140499 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 158486 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 7 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 17978 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 140499 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 158486 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 9022 # number of ReadReq MSHR uncacheable -system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 31138 # number of ReadReq MSHR uncacheable -system.cpu.l2cache.ReadReq_mshr_uncacheable::total 40160 # number of ReadReq MSHR uncacheable -system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 27589 # number of WriteReq MSHR uncacheable -system.cpu.l2cache.WriteReq_mshr_uncacheable::total 27589 # number of WriteReq MSHR uncacheable -system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 9022 # number of overall MSHR uncacheable misses -system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 58727 # number of overall MSHR uncacheable misses -system.cpu.l2cache.overall_mshr_uncacheable_misses::total 67749 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1084000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 160000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1244000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 345000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 345000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 141000 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 141000 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10615643500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10615643500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1886586000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1886586000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1399343000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1399343000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 1084000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 160000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1886586000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 12014986500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 13902816500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 1084000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 160000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1886586000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12014986500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 13902816500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 632428000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5895484000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6527912000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 632428000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5895484000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 6527912000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001381 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000745 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001160 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.006413 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.006413 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.433765 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.433765 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.010572 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.010572 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.022967 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.022967 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001381 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000745 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010572 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.170986 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.062642 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001381 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000745 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010572 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.170986 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.062642 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 154857.142857 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 80000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 138222.222222 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19166.666667 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19166.666667 # average UpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 70500 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 70500 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 82658.969687 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 82658.969687 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 104938.591612 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 104938.591612 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 115916.418158 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 115916.418158 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 154857.142857 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 80000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 104938.591612 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 85516.526808 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 87722.678975 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 154857.142857 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 80000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 104938.591612 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 85516.526808 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 87722.678975 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 70098.426070 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189334.061276 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 162547.609562 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 70098.426070 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 100387.964650 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 96354.366854 # average overall mshr uncacheable latency -system.cpu.toL2Bus.snoop_filter.tot_requests 5065624 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2543358 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 39299 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 227 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 227 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadReq 67226 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2293620 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 27589 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 27589 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 767586 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 1700062 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 142169 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2807 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2809 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 296075 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 296075 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1700580 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 525822 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateReq 4351 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateResp 14 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5119250 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2587830 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 11902 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 22920 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7741902 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 217676152 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96663453 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 10744 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 20280 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 314370629 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 112679 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 5336568 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 2713050 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.021694 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.145681 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 2654194 97.83% 97.83% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 58856 2.17% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 2713050 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4970033000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 354876 # Layer occupancy (ticks) -system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 2559892000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1278884000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 9216000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 17850000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states -system.iobus.trans_dist::ReadReq 30159 # Transaction distribution -system.iobus.trans_dist::ReadResp 30159 # Transaction distribution -system.iobus.trans_dist::WriteReq 59014 # Transaction distribution -system.iobus.trans_dist::WriteResp 59014 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54170 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 105478 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72868 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 72868 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 178346 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67887 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 159125 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2320912 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 2320912 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2480037 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 46336500 # Layer occupancy (ticks) -system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 97000 # Layer occupancy (ticks) -system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 338000 # Layer occupancy (ticks) -system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 29500 # Layer occupancy (ticks) -system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer4.occupancy 15500 # Layer occupancy (ticks) -system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 94500 # Layer occupancy (ticks) -system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer8.occupancy 642500 # Layer occupancy (ticks) -system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 21000 # Layer occupancy (ticks) -system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 11500 # Layer occupancy (ticks) -system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 12000 # Layer occupancy (ticks) -system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer15.occupancy 12000 # Layer occupancy (ticks) -system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 52500 # Layer occupancy (ticks) -system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 12000 # Layer occupancy (ticks) -system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 11500 # Layer occupancy (ticks) -system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks) -system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer20.occupancy 9000 # Layer occupancy (ticks) -system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer21.occupancy 11500 # Layer occupancy (ticks) -system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 6289000 # Layer occupancy (ticks) -system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 36469500 # Layer occupancy (ticks) -system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 187507137 # Layer occupancy (ticks) -system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks) -system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36692000 # Layer occupancy (ticks) -system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states -system.iocache.tags.replacements 36400 # number of replacements -system.iocache.tags.tagsinuse 1.079862 # Cycle average of tags in use -system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 36416 # Sample count of references to valid blocks. -system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 310617748000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 1.079862 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.067491 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.067491 # Average percentage of cache occupancy -system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id -system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id -system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 327906 # Number of tag accesses -system.iocache.tags.data_accesses 327906 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states -system.iocache.ReadReq_misses::realview.ide 210 # number of ReadReq misses -system.iocache.ReadReq_misses::total 210 # number of ReadReq misses -system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses -system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses -system.iocache.demand_misses::realview.ide 36434 # number of demand (read+write) misses -system.iocache.demand_misses::total 36434 # number of demand (read+write) misses -system.iocache.overall_misses::realview.ide 36434 # number of overall misses -system.iocache.overall_misses::total 36434 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 34066376 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 34066376 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 4377262761 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4377262761 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 4411329137 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 4411329137 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 4411329137 # number of overall miss cycles -system.iocache.overall_miss_latency::total 4411329137 # number of overall miss cycles -system.iocache.ReadReq_accesses::realview.ide 210 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 210 # number of ReadReq accesses(hits+misses) -system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) -system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::realview.ide 36434 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 36434 # number of demand (read+write) accesses -system.iocache.overall_accesses::realview.ide 36434 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 36434 # number of overall (read+write) accesses -system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses -system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses -system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses -system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses -system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses -system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses -system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 162220.838095 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 162220.838095 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120838.746715 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 120838.746715 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 121077.266756 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 121077.266756 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 121077.266756 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 121077.266756 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 208 # number of cycles access was blocked -system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 4 # number of cycles access was blocked -system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 52 # average number of cycles each access was blocked -system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.writebacks::writebacks 36190 # number of writebacks -system.iocache.writebacks::total 36190 # number of writebacks -system.iocache.ReadReq_mshr_misses::realview.ide 210 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 210 # number of ReadReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::realview.ide 36434 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 36434 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::realview.ide 36434 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 36434 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 23566376 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 23566376 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2564294505 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2564294505 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 2587860881 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 2587860881 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 2587860881 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 2587860881 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses -system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses -system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses -system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 112220.838095 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 112220.838095 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70789.932227 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70789.932227 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 71028.733628 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 71028.733628 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 71028.733628 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 71028.733628 # average overall mshr miss latency -system.membus.snoop_filter.tot_requests 320000 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 129537 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 496 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 40160 # Transaction distribution -system.membus.trans_dist::ReadResp 70429 # Transaction distribution -system.membus.trans_dist::WriteReq 27589 # Transaction distribution -system.membus.trans_dist::WriteResp 27589 # Transaction distribution -system.membus.trans_dist::WritebackDirty 118160 # Transaction distribution -system.membus.trans_dist::CleanEvict 6838 # Transaction distribution -system.membus.trans_dist::UpgradeReq 128 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 2 # Transaction distribution -system.membus.trans_dist::ReadExReq 128317 # Transaction distribution -system.membus.trans_dist::ReadExResp 128317 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 30269 # Transaction distribution -system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.membus.trans_dist::InvalidateResp 4315 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2104 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 433109 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 540701 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72849 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 72849 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 613550 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4208 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15420284 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 15583637 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 17900757 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 4789 # Total snoops (count) -system.membus.snoopTraffic 30208 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 262689 # Request fanout histogram -system.membus.snoop_fanout::mean 0.018383 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.134332 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 257860 98.16% 98.16% # Request fanout histogram -system.membus.snoop_fanout::1 4829 1.84% 100.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 262689 # Request fanout histogram -system.membus.reqLayer0.occupancy 90467000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 7500 # Layer occupancy (ticks) -system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1724500 # Layer occupancy (ticks) -system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 822822299 # Layer occupancy (ticks) -system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 948652750 # Layer occupancy (ticks) -system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 5614930 # Layer occupancy (ticks) -system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states -system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks -system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks -system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks -system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks -system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks -system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states -system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA -system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA -system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA -system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA -system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU -system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post -system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR -system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU -system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post -system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR -system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU -system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post -system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR -system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU -system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post -system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR -system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU -system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post -system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR -system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU -system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post -system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR -system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU -system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post -system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR -system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU -system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post -system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR -system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post -system.realview.ethernet.postedInterrupts 0 # number of posts to CPU -system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states -system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks -system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks -system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks -system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2905316914500 # Cumulative time (in ticks) in various power states +sim_seconds 2.905306 +sim_ticks 2905305537500 +final_tick 2905305537500 +sim_freq 1000000000000 +host_inst_rate 1111245 +host_op_rate 1339819 +host_tick_rate 28710628480 +host_mem_usage 591900 +host_seconds 101.19 +sim_insts 112449853 +sim_ops 135579871 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 2905305537500 +system.physmem.bytes_read::cpu.dtb.walker 448 +system.physmem.bytes_read::cpu.itb.walker 128 +system.physmem.bytes_read::cpu.inst 1186468 +system.physmem.bytes_read::cpu.data 8969572 +system.physmem.bytes_read::realview.ide 960 +system.physmem.bytes_read::total 10157576 +system.physmem.bytes_inst_read::cpu.inst 1186468 +system.physmem.bytes_inst_read::total 1186468 +system.physmem.bytes_written::writebacks 7562240 +system.physmem.bytes_written::cpu.data 17524 +system.physmem.bytes_written::total 7579764 +system.physmem.num_reads::cpu.dtb.walker 7 +system.physmem.num_reads::cpu.itb.walker 2 +system.physmem.num_reads::cpu.inst 26992 +system.physmem.num_reads::cpu.data 140669 +system.physmem.num_reads::realview.ide 15 +system.physmem.num_reads::total 167685 +system.physmem.num_writes::writebacks 118160 +system.physmem.num_writes::cpu.data 4381 +system.physmem.num_writes::total 122541 +system.physmem.bw_read::cpu.dtb.walker 154 +system.physmem.bw_read::cpu.itb.walker 44 +system.physmem.bw_read::cpu.inst 408380 +system.physmem.bw_read::cpu.data 3087308 +system.physmem.bw_read::realview.ide 330 +system.physmem.bw_read::total 3496216 +system.physmem.bw_inst_read::cpu.inst 408380 +system.physmem.bw_inst_read::total 408380 +system.physmem.bw_write::writebacks 2602907 +system.physmem.bw_write::cpu.data 6032 +system.physmem.bw_write::total 2608939 +system.physmem.bw_total::writebacks 2602907 +system.physmem.bw_total::cpu.dtb.walker 154 +system.physmem.bw_total::cpu.itb.walker 44 +system.physmem.bw_total::cpu.inst 408380 +system.physmem.bw_total::cpu.data 3093339 +system.physmem.bw_total::realview.ide 330 +system.physmem.bw_total::total 6105155 +system.physmem.readReqs 167685 +system.physmem.writeReqs 122541 +system.physmem.readBursts 167685 +system.physmem.writeBursts 122541 +system.physmem.bytesReadDRAM 10724672 +system.physmem.bytesReadWrQ 7168 +system.physmem.bytesWritten 7592640 +system.physmem.bytesReadSys 10157576 +system.physmem.bytesWrittenSys 7579764 +system.physmem.servicedByWrQ 112 +system.physmem.mergedWrBursts 3887 +system.physmem.neitherReadNorWriteReqs 0 +system.physmem.perBankRdBursts::0 9873 +system.physmem.perBankRdBursts::1 9614 +system.physmem.perBankRdBursts::2 9963 +system.physmem.perBankRdBursts::3 9595 +system.physmem.perBankRdBursts::4 18744 +system.physmem.perBankRdBursts::5 9936 +system.physmem.perBankRdBursts::6 10635 +system.physmem.perBankRdBursts::7 11205 +system.physmem.perBankRdBursts::8 9589 +system.physmem.perBankRdBursts::9 10032 +system.physmem.perBankRdBursts::10 9283 +system.physmem.perBankRdBursts::11 8863 +system.physmem.perBankRdBursts::12 10211 +system.physmem.perBankRdBursts::13 10190 +system.physmem.perBankRdBursts::14 10325 +system.physmem.perBankRdBursts::15 9515 +system.physmem.perBankWrBursts::0 7137 +system.physmem.perBankWrBursts::1 7022 +system.physmem.perBankWrBursts::2 7742 +system.physmem.perBankWrBursts::3 7365 +system.physmem.perBankWrBursts::4 7465 +system.physmem.perBankWrBursts::5 7289 +system.physmem.perBankWrBursts::6 7716 +system.physmem.perBankWrBursts::7 8300 +system.physmem.perBankWrBursts::8 7184 +system.physmem.perBankWrBursts::9 7439 +system.physmem.perBankWrBursts::10 6836 +system.physmem.perBankWrBursts::11 6804 +system.physmem.perBankWrBursts::12 7947 +system.physmem.perBankWrBursts::13 7681 +system.physmem.perBankWrBursts::14 7752 +system.physmem.perBankWrBursts::15 6956 +system.physmem.numRdRetry 0 +system.physmem.numWrRetry 63 +system.physmem.totGap 2905305175500 +system.physmem.readPktSize::0 0 +system.physmem.readPktSize::1 0 +system.physmem.readPktSize::2 9558 +system.physmem.readPktSize::3 14 +system.physmem.readPktSize::4 0 +system.physmem.readPktSize::5 0 +system.physmem.readPktSize::6 158113 +system.physmem.writePktSize::0 0 +system.physmem.writePktSize::1 0 +system.physmem.writePktSize::2 4381 +system.physmem.writePktSize::3 0 +system.physmem.writePktSize::4 0 +system.physmem.writePktSize::5 0 +system.physmem.writePktSize::6 118160 +system.physmem.rdQLenPdf::0 166739 +system.physmem.rdQLenPdf::1 559 +system.physmem.rdQLenPdf::2 263 +system.physmem.rdQLenPdf::3 1 +system.physmem.rdQLenPdf::4 1 +system.physmem.rdQLenPdf::5 1 +system.physmem.rdQLenPdf::6 1 +system.physmem.rdQLenPdf::7 1 +system.physmem.rdQLenPdf::8 1 +system.physmem.rdQLenPdf::9 1 +system.physmem.rdQLenPdf::10 1 +system.physmem.rdQLenPdf::11 1 +system.physmem.rdQLenPdf::12 1 +system.physmem.rdQLenPdf::13 1 +system.physmem.rdQLenPdf::14 1 +system.physmem.rdQLenPdf::15 0 +system.physmem.rdQLenPdf::16 0 +system.physmem.rdQLenPdf::17 0 +system.physmem.rdQLenPdf::18 0 +system.physmem.rdQLenPdf::19 0 +system.physmem.rdQLenPdf::20 0 +system.physmem.rdQLenPdf::21 0 +system.physmem.rdQLenPdf::22 0 +system.physmem.rdQLenPdf::23 0 +system.physmem.rdQLenPdf::24 0 +system.physmem.rdQLenPdf::25 0 +system.physmem.rdQLenPdf::26 0 +system.physmem.rdQLenPdf::27 0 +system.physmem.rdQLenPdf::28 0 +system.physmem.rdQLenPdf::29 0 +system.physmem.rdQLenPdf::30 0 +system.physmem.rdQLenPdf::31 0 +system.physmem.wrQLenPdf::0 1 +system.physmem.wrQLenPdf::1 1 +system.physmem.wrQLenPdf::2 1 +system.physmem.wrQLenPdf::3 1 +system.physmem.wrQLenPdf::4 1 +system.physmem.wrQLenPdf::5 1 +system.physmem.wrQLenPdf::6 1 +system.physmem.wrQLenPdf::7 1 +system.physmem.wrQLenPdf::8 1 +system.physmem.wrQLenPdf::9 1 +system.physmem.wrQLenPdf::10 1 +system.physmem.wrQLenPdf::11 1 +system.physmem.wrQLenPdf::12 1 +system.physmem.wrQLenPdf::13 1 +system.physmem.wrQLenPdf::14 1 +system.physmem.wrQLenPdf::15 1874 +system.physmem.wrQLenPdf::16 2840 +system.physmem.wrQLenPdf::17 5990 +system.physmem.wrQLenPdf::18 5890 +system.physmem.wrQLenPdf::19 6230 +system.physmem.wrQLenPdf::20 5856 +system.physmem.wrQLenPdf::21 6225 +system.physmem.wrQLenPdf::22 6586 +system.physmem.wrQLenPdf::23 7530 +system.physmem.wrQLenPdf::24 7116 +system.physmem.wrQLenPdf::25 8216 +system.physmem.wrQLenPdf::26 8865 +system.physmem.wrQLenPdf::27 7091 +system.physmem.wrQLenPdf::28 6561 +system.physmem.wrQLenPdf::29 6513 +system.physmem.wrQLenPdf::30 6308 +system.physmem.wrQLenPdf::31 6117 +system.physmem.wrQLenPdf::32 6210 +system.physmem.wrQLenPdf::33 449 +system.physmem.wrQLenPdf::34 397 +system.physmem.wrQLenPdf::35 386 +system.physmem.wrQLenPdf::36 303 +system.physmem.wrQLenPdf::37 299 +system.physmem.wrQLenPdf::38 283 +system.physmem.wrQLenPdf::39 257 +system.physmem.wrQLenPdf::40 228 +system.physmem.wrQLenPdf::41 270 +system.physmem.wrQLenPdf::42 247 +system.physmem.wrQLenPdf::43 240 +system.physmem.wrQLenPdf::44 228 +system.physmem.wrQLenPdf::45 174 +system.physmem.wrQLenPdf::46 175 +system.physmem.wrQLenPdf::47 154 +system.physmem.wrQLenPdf::48 169 +system.physmem.wrQLenPdf::49 180 +system.physmem.wrQLenPdf::50 174 +system.physmem.wrQLenPdf::51 137 +system.physmem.wrQLenPdf::52 121 +system.physmem.wrQLenPdf::53 122 +system.physmem.wrQLenPdf::54 117 +system.physmem.wrQLenPdf::55 150 +system.physmem.wrQLenPdf::56 246 +system.physmem.wrQLenPdf::57 214 +system.physmem.wrQLenPdf::58 117 +system.physmem.wrQLenPdf::59 199 +system.physmem.wrQLenPdf::60 201 +system.physmem.wrQLenPdf::61 189 +system.physmem.wrQLenPdf::62 68 +system.physmem.wrQLenPdf::63 127 +system.physmem.bytesPerActivate::samples 57696 +system.physmem.bytesPerActivate::mean 317.478647 +system.physmem.bytesPerActivate::gmean 186.529934 +system.physmem.bytesPerActivate::stdev 335.962495 +system.physmem.bytesPerActivate::0-127 20572 35.66% 35.66% +system.physmem.bytesPerActivate::128-255 14702 25.48% 61.14% +system.physmem.bytesPerActivate::256-383 5653 9.80% 70.94% +system.physmem.bytesPerActivate::384-511 3146 5.45% 76.39% +system.physmem.bytesPerActivate::512-639 2423 4.20% 80.59% +system.physmem.bytesPerActivate::640-767 1393 2.41% 83.00% +system.physmem.bytesPerActivate::768-895 1271 2.20% 85.21% +system.physmem.bytesPerActivate::896-1023 917 1.59% 86.79% +system.physmem.bytesPerActivate::1024-1151 7619 13.21% 100.00% +system.physmem.bytesPerActivate::total 57696 +system.physmem.rdPerTurnAround::samples 5793 +system.physmem.rdPerTurnAround::mean 28.926463 +system.physmem.rdPerTurnAround::stdev 588.910199 +system.physmem.rdPerTurnAround::0-2047 5792 99.98% 99.98% +system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% +system.physmem.rdPerTurnAround::total 5793 +system.physmem.wrPerTurnAround::samples 5793 +system.physmem.wrPerTurnAround::mean 20.479026 +system.physmem.wrPerTurnAround::gmean 18.531275 +system.physmem.wrPerTurnAround::stdev 14.943169 +system.physmem.wrPerTurnAround::16-19 5068 87.48% 87.48% +system.physmem.wrPerTurnAround::20-23 43 0.74% 88.23% +system.physmem.wrPerTurnAround::24-27 40 0.69% 88.92% +system.physmem.wrPerTurnAround::28-31 53 0.91% 89.83% +system.physmem.wrPerTurnAround::32-35 289 4.99% 94.82% +system.physmem.wrPerTurnAround::36-39 23 0.40% 95.22% +system.physmem.wrPerTurnAround::40-43 16 0.28% 95.49% +system.physmem.wrPerTurnAround::44-47 6 0.10% 95.60% +system.physmem.wrPerTurnAround::48-51 5 0.09% 95.68% +system.physmem.wrPerTurnAround::52-55 2 0.03% 95.72% +system.physmem.wrPerTurnAround::56-59 1 0.02% 95.74% +system.physmem.wrPerTurnAround::60-63 5 0.09% 95.82% +system.physmem.wrPerTurnAround::64-67 158 2.73% 98.55% +system.physmem.wrPerTurnAround::68-71 7 0.12% 98.67% +system.physmem.wrPerTurnAround::72-75 5 0.09% 98.76% +system.physmem.wrPerTurnAround::76-79 5 0.09% 98.84% +system.physmem.wrPerTurnAround::80-83 8 0.14% 98.98% +system.physmem.wrPerTurnAround::84-87 5 0.09% 99.07% +system.physmem.wrPerTurnAround::96-99 2 0.03% 99.10% +system.physmem.wrPerTurnAround::104-107 2 0.03% 99.14% +system.physmem.wrPerTurnAround::108-111 9 0.16% 99.29% +system.physmem.wrPerTurnAround::116-119 2 0.03% 99.33% +system.physmem.wrPerTurnAround::120-123 1 0.02% 99.34% +system.physmem.wrPerTurnAround::124-127 2 0.03% 99.38% +system.physmem.wrPerTurnAround::128-131 8 0.14% 99.52% +system.physmem.wrPerTurnAround::132-135 5 0.09% 99.60% +system.physmem.wrPerTurnAround::136-139 5 0.09% 99.69% +system.physmem.wrPerTurnAround::140-143 6 0.10% 99.79% +system.physmem.wrPerTurnAround::144-147 1 0.02% 99.81% +system.physmem.wrPerTurnAround::156-159 1 0.02% 99.83% +system.physmem.wrPerTurnAround::160-163 4 0.07% 99.90% +system.physmem.wrPerTurnAround::172-175 2 0.03% 99.93% +system.physmem.wrPerTurnAround::180-183 2 0.03% 99.97% +system.physmem.wrPerTurnAround::184-187 1 0.02% 99.98% +system.physmem.wrPerTurnAround::188-191 1 0.02% 100.00% +system.physmem.wrPerTurnAround::total 5793 +system.physmem.totQLat 4571022000 +system.physmem.totMemAccLat 7713015750 +system.physmem.totBusLat 837865000 +system.physmem.avgQLat 27277.80 +system.physmem.avgBusLat 5000.00 +system.physmem.avgMemAccLat 46027.80 +system.physmem.avgRdBW 3.69 +system.physmem.avgWrBW 2.61 +system.physmem.avgRdBWSys 3.50 +system.physmem.avgWrBWSys 2.61 +system.physmem.peakBW 12800.00 +system.physmem.busUtil 0.05 +system.physmem.busUtilRead 0.03 +system.physmem.busUtilWrite 0.02 +system.physmem.avgRdQLen 1.00 +system.physmem.avgWrQLen 24.59 +system.physmem.readRowHits 138588 +system.physmem.writeRowHits 89923 +system.physmem.readRowHitRate 82.70 +system.physmem.writeRowHitRate 75.79 +system.physmem.avgGap 10010492.43 +system.physmem.pageHitRate 79.84 +system.physmem_0.actEnergy 209923140 +system.physmem_0.preEnergy 111576795 +system.physmem_0.readEnergy 639494100 +system.physmem_0.writeEnergy 313387920 +system.physmem_0.refreshEnergy 6670687920.000002 +system.physmem_0.actBackEnergy 4809422880 +system.physmem_0.preBackEnergy 413752800 +system.physmem_0.actPowerDownEnergy 13946789640 +system.physmem_0.prePowerDownEnergy 9398763360 +system.physmem_0.selfRefreshEnergy 682626603840 +system.physmem_0.totalEnergy 719142677895 +system.physmem_0.averagePower 247.527383 +system.physmem_0.totalIdleTime 2893152718000 +system.physmem_0.memoryStateTime::IDLE 777067000 +system.physmem_0.memoryStateTime::REF 2836732000 +system.physmem_0.memoryStateTime::SREF 2838614964500 +system.physmem_0.memoryStateTime::PRE_PDN 24475941750 +system.physmem_0.memoryStateTime::ACT 8015385500 +system.physmem_0.memoryStateTime::ACT_PDN 30585446750 +system.physmem_1.actEnergy 202033440 +system.physmem_1.preEnergy 107379525 +system.physmem_1.readEnergy 556977120 +system.physmem_1.writeEnergy 305886780 +system.physmem_1.refreshEnergy 6674990400.000002 +system.physmem_1.actBackEnergy 4528240170 +system.physmem_1.preBackEnergy 413409600 +system.physmem_1.actPowerDownEnergy 13646578620 +system.physmem_1.prePowerDownEnergy 9540468000 +system.physmem_1.selfRefreshEnergy 682917113460 +system.physmem_1.totalEnergy 718894076985 +system.physmem_1.averagePower 247.441816 +system.physmem_1.totalIdleTime 2894296337500 +system.physmem_1.memoryStateTime::IDLE 785533000 +system.physmem_1.memoryStateTime::REF 2839260000 +system.physmem_1.memoryStateTime::SREF 2839524651500 +system.physmem_1.memoryStateTime::PRE_PDN 24844849250 +system.physmem_1.memoryStateTime::ACT 7384341000 +system.physmem_1.memoryStateTime::ACT_PDN 29926902750 +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2905305537500 +system.realview.nvmem.bytes_read::cpu.inst 20 +system.realview.nvmem.bytes_read::total 20 +system.realview.nvmem.bytes_inst_read::cpu.inst 20 +system.realview.nvmem.bytes_inst_read::total 20 +system.realview.nvmem.num_reads::cpu.inst 5 +system.realview.nvmem.num_reads::total 5 +system.realview.nvmem.bw_read::cpu.inst 7 +system.realview.nvmem.bw_read::total 7 +system.realview.nvmem.bw_inst_read::cpu.inst 7 +system.realview.nvmem.bw_inst_read::total 7 +system.realview.nvmem.bw_total::cpu.inst 7 +system.realview.nvmem.bw_total::total 7 +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2905305537500 +system.pwrStateResidencyTicks::UNDEFINED 2905305537500 +system.bridge.pwrStateResidencyTicks::UNDEFINED 2905305537500 +system.cf0.dma_read_full_pages 0 +system.cf0.dma_read_bytes 1024 +system.cf0.dma_read_txs 1 +system.cf0.dma_write_full_pages 540 +system.cf0.dma_write_bytes 2318336 +system.cf0.dma_write_txs 631 +system.cpu_clk_domain.clock 500 +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2905305537500 +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 +system.cpu.dstage2_mmu.stage2_tlb.hits 0 +system.cpu.dstage2_mmu.stage2_tlb.misses 0 +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2905305537500 +system.cpu.dtb.walker.walks 9552 +system.cpu.dtb.walker.walksShort 9552 +system.cpu.dtb.walker.walksShortTerminationLevel::Level1 1256 +system.cpu.dtb.walker.walksShortTerminationLevel::Level2 8296 +system.cpu.dtb.walker.walkWaitTime::samples 9552 +system.cpu.dtb.walker.walkWaitTime::0 9552 100.00% 100.00% +system.cpu.dtb.walker.walkWaitTime::total 9552 +system.cpu.dtb.walker.walkCompletionTime::samples 7388 +system.cpu.dtb.walker.walkCompletionTime::mean 10012.994044 +system.cpu.dtb.walker.walkCompletionTime::gmean 8463.653638 +system.cpu.dtb.walker.walkCompletionTime::stdev 6610.616521 +system.cpu.dtb.walker.walkCompletionTime::0-16383 6587 89.16% 89.16% +system.cpu.dtb.walker.walkCompletionTime::16384-32767 796 10.77% 99.93% +system.cpu.dtb.walker.walkCompletionTime::81920-98303 4 0.05% 99.99% +system.cpu.dtb.walker.walkCompletionTime::180224-196607 1 0.01% 100.00% +system.cpu.dtb.walker.walkCompletionTime::total 7388 +system.cpu.dtb.walker.walksPending::samples 1003066500 +system.cpu.dtb.walker.walksPending::0 1003066500 100.00% 100.00% +system.cpu.dtb.walker.walksPending::total 1003066500 +system.cpu.dtb.walker.walkPageSizes::4K 6179 83.64% 83.64% +system.cpu.dtb.walker.walkPageSizes::1M 1209 16.36% 100.00% +system.cpu.dtb.walker.walkPageSizes::total 7388 +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 9552 +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 9552 +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7388 +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7388 +system.cpu.dtb.walker.walkRequestOrigin::total 16940 +system.cpu.dtb.inst_hits 0 +system.cpu.dtb.inst_misses 0 +system.cpu.dtb.read_hits 24517545 +system.cpu.dtb.read_misses 8139 +system.cpu.dtb.write_hits 19603622 +system.cpu.dtb.write_misses 1413 +system.cpu.dtb.flush_tlb 64 +system.cpu.dtb.flush_tlb_mva 917 +system.cpu.dtb.flush_tlb_mva_asid 0 +system.cpu.dtb.flush_tlb_asid 0 +system.cpu.dtb.flush_entries 4209 +system.cpu.dtb.align_faults 0 +system.cpu.dtb.prefetch_faults 1622 +system.cpu.dtb.domain_faults 0 +system.cpu.dtb.perms_faults 445 +system.cpu.dtb.read_accesses 24525684 +system.cpu.dtb.write_accesses 19605035 +system.cpu.dtb.inst_accesses 0 +system.cpu.dtb.hits 44121167 +system.cpu.dtb.misses 9552 +system.cpu.dtb.accesses 44130719 +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2905305537500 +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 +system.cpu.istage2_mmu.stage2_tlb.hits 0 +system.cpu.istage2_mmu.stage2_tlb.misses 0 +system.cpu.istage2_mmu.stage2_tlb.accesses 0 +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2905305537500 +system.cpu.itb.walker.walks 4763 +system.cpu.itb.walker.walksShort 4763 +system.cpu.itb.walker.walksShortTerminationLevel::Level1 310 +system.cpu.itb.walker.walksShortTerminationLevel::Level2 4453 +system.cpu.itb.walker.walkWaitTime::samples 4763 +system.cpu.itb.walker.walkWaitTime::0 4763 100.00% 100.00% +system.cpu.itb.walker.walkWaitTime::total 4763 +system.cpu.itb.walker.walkCompletionTime::samples 3108 +system.cpu.itb.walker.walkCompletionTime::mean 10180.019305 +system.cpu.itb.walker.walkCompletionTime::gmean 8231.944722 +system.cpu.itb.walker.walkCompletionTime::stdev 7310.859984 +system.cpu.itb.walker.walkCompletionTime::0-8191 1821 58.59% 58.59% +system.cpu.itb.walker.walkCompletionTime::8192-16383 761 24.49% 83.08% +system.cpu.itb.walker.walkCompletionTime::16384-24575 524 16.86% 99.94% +system.cpu.itb.walker.walkCompletionTime::90112-98303 1 0.03% 99.97% +system.cpu.itb.walker.walkCompletionTime::98304-106495 1 0.03% 100.00% +system.cpu.itb.walker.walkCompletionTime::total 3108 +system.cpu.itb.walker.walksPending::samples 1002711000 +system.cpu.itb.walker.walksPending::0 1002711000 100.00% 100.00% +system.cpu.itb.walker.walksPending::total 1002711000 +system.cpu.itb.walker.walkPageSizes::4K 2798 90.03% 90.03% +system.cpu.itb.walker.walkPageSizes::1M 310 9.97% 100.00% +system.cpu.itb.walker.walkPageSizes::total 3108 +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 4763 +system.cpu.itb.walker.walkRequestOrigin_Requested::total 4763 +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3108 +system.cpu.itb.walker.walkRequestOrigin_Completed::total 3108 +system.cpu.itb.walker.walkRequestOrigin::total 7871 +system.cpu.itb.inst_hits 115547653 +system.cpu.itb.inst_misses 4763 +system.cpu.itb.read_hits 0 +system.cpu.itb.read_misses 0 +system.cpu.itb.write_hits 0 +system.cpu.itb.write_misses 0 +system.cpu.itb.flush_tlb 64 +system.cpu.itb.flush_tlb_mva 917 +system.cpu.itb.flush_tlb_mva_asid 0 +system.cpu.itb.flush_tlb_asid 0 +system.cpu.itb.flush_entries 2849 +system.cpu.itb.align_faults 0 +system.cpu.itb.prefetch_faults 0 +system.cpu.itb.domain_faults 0 +system.cpu.itb.perms_faults 0 +system.cpu.itb.read_accesses 0 +system.cpu.itb.write_accesses 0 +system.cpu.itb.inst_accesses 115552416 +system.cpu.itb.hits 115547653 +system.cpu.itb.misses 4763 +system.cpu.itb.accesses 115552416 +system.cpu.numPwrStateTransitions 6064 +system.cpu.pwrStateClkGateDist::samples 3032 +system.cpu.pwrStateClkGateDist::mean 887476232.352243 +system.cpu.pwrStateClkGateDist::stdev 17466728085.198059 +system.cpu.pwrStateClkGateDist::underflows 2968 97.89% 97.89% +system.cpu.pwrStateClkGateDist::1000-5e+10 58 1.91% 99.80% +system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 1 0.03% 99.84% +system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 1 0.03% 99.87% +system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 1 0.03% 99.90% +system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 3 0.10% 100.00% +system.cpu.pwrStateClkGateDist::min_value 501 +system.cpu.pwrStateClkGateDist::max_value 499964549884 +system.cpu.pwrStateClkGateDist::total 3032 +system.cpu.pwrStateResidencyTicks::ON 214477601008 +system.cpu.pwrStateResidencyTicks::CLK_GATED 2690827936492 +system.cpu.numCycles 5810611075 +system.cpu.numWorkItemsStarted 0 +system.cpu.numWorkItemsCompleted 0 +system.cpu.kern.inst.arm 0 +system.cpu.kern.inst.quiesce 3032 +system.cpu.committedInsts 112449853 +system.cpu.committedOps 135579871 +system.cpu.num_int_alu_accesses 119885571 +system.cpu.num_fp_alu_accesses 11290 +system.cpu.num_func_calls 9894238 +system.cpu.num_conditional_control_insts 15230085 +system.cpu.num_int_insts 119885571 +system.cpu.num_fp_insts 11290 +system.cpu.num_int_register_reads 218040023 +system.cpu.num_int_register_writes 82640385 +system.cpu.num_fp_register_reads 8578 +system.cpu.num_fp_register_writes 2716 +system.cpu.num_cc_register_reads 489710218 +system.cpu.num_cc_register_writes 51892450 +system.cpu.num_mem_refs 45401283 +system.cpu.num_load_insts 24839682 +system.cpu.num_store_insts 20561601 +system.cpu.num_idle_cycles 5381655872.982148 +system.cpu.num_busy_cycles 428955202.017852 +system.cpu.not_idle_fraction 0.073823 +system.cpu.idle_fraction 0.926177 +system.cpu.Branches 25918317 +system.cpu.op_class::No_OpClass 2337 0.00% 0.00% +system.cpu.op_class::IntAlu 93173741 67.18% 67.18% +system.cpu.op_class::IntMult 114521 0.08% 67.26% +system.cpu.op_class::IntDiv 0 0.00% 67.26% +system.cpu.op_class::FloatAdd 0 0.00% 67.26% +system.cpu.op_class::FloatCmp 0 0.00% 67.26% +system.cpu.op_class::FloatCvt 0 0.00% 67.26% +system.cpu.op_class::FloatMult 0 0.00% 67.26% +system.cpu.op_class::FloatMultAcc 0 0.00% 67.26% +system.cpu.op_class::FloatDiv 0 0.00% 67.26% +system.cpu.op_class::FloatMisc 0 0.00% 67.26% +system.cpu.op_class::FloatSqrt 0 0.00% 67.26% +system.cpu.op_class::SimdAdd 0 0.00% 67.26% +system.cpu.op_class::SimdAddAcc 0 0.00% 67.26% +system.cpu.op_class::SimdAlu 0 0.00% 67.26% +system.cpu.op_class::SimdCmp 0 0.00% 67.26% +system.cpu.op_class::SimdCvt 0 0.00% 67.26% +system.cpu.op_class::SimdMisc 0 0.00% 67.26% +system.cpu.op_class::SimdMult 0 0.00% 67.26% +system.cpu.op_class::SimdMultAcc 0 0.00% 67.26% +system.cpu.op_class::SimdShift 0 0.00% 67.26% +system.cpu.op_class::SimdShiftAcc 0 0.00% 67.26% +system.cpu.op_class::SimdSqrt 0 0.00% 67.26% +system.cpu.op_class::SimdFloatAdd 0 0.00% 67.26% +system.cpu.op_class::SimdFloatAlu 0 0.00% 67.26% +system.cpu.op_class::SimdFloatCmp 0 0.00% 67.26% +system.cpu.op_class::SimdFloatCvt 0 0.00% 67.26% +system.cpu.op_class::SimdFloatDiv 0 0.00% 67.26% +system.cpu.op_class::SimdFloatMisc 8435 0.01% 67.27% +system.cpu.op_class::SimdFloatMult 0 0.00% 67.27% +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.27% +system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.27% +system.cpu.op_class::MemRead 24836974 17.91% 85.17% +system.cpu.op_class::MemWrite 20553023 14.82% 99.99% +system.cpu.op_class::FloatMemRead 2708 0.00% 99.99% +system.cpu.op_class::FloatMemWrite 8578 0.01% 100.00% +system.cpu.op_class::IprAccess 0 0.00% 100.00% +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% +system.cpu.op_class::total 138700317 +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2905305537500 +system.cpu.dcache.tags.replacements 821089 +system.cpu.dcache.tags.tagsinuse 511.816170 +system.cpu.dcache.tags.total_refs 43228313 +system.cpu.dcache.tags.sampled_refs 821601 +system.cpu.dcache.tags.avg_refs 52.614728 +system.cpu.dcache.tags.warmup_cycle 1078145500 +system.cpu.dcache.tags.occ_blocks::cpu.data 511.816170 +system.cpu.dcache.tags.occ_percent::cpu.data 0.999641 +system.cpu.dcache.tags.occ_percent::total 0.999641 +system.cpu.dcache.tags.occ_task_id_blocks::1024 512 +system.cpu.dcache.tags.age_task_id_blocks_1024::0 59 +system.cpu.dcache.tags.age_task_id_blocks_1024::1 356 +system.cpu.dcache.tags.age_task_id_blocks_1024::2 96 +system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 +system.cpu.dcache.tags.occ_task_id_percent::1024 1 +system.cpu.dcache.tags.tag_accesses 177089446 +system.cpu.dcache.tags.data_accesses 177089446 +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2905305537500 +system.cpu.dcache.ReadReq_hits::cpu.data 23108878 +system.cpu.dcache.ReadReq_hits::total 23108878 +system.cpu.dcache.WriteReq_hits::cpu.data 18821001 +system.cpu.dcache.WriteReq_hits::total 18821001 +system.cpu.dcache.SoftPFReq_hits::cpu.data 392443 +system.cpu.dcache.SoftPFReq_hits::total 392443 +system.cpu.dcache.LoadLockedReq_hits::cpu.data 443073 +system.cpu.dcache.LoadLockedReq_hits::total 443073 +system.cpu.dcache.StoreCondReq_hits::cpu.data 460108 +system.cpu.dcache.StoreCondReq_hits::total 460108 +system.cpu.dcache.demand_hits::cpu.data 41929879 +system.cpu.dcache.demand_hits::total 41929879 +system.cpu.dcache.overall_hits::cpu.data 42322322 +system.cpu.dcache.overall_hits::total 42322322 +system.cpu.dcache.ReadReq_misses::cpu.data 401094 +system.cpu.dcache.ReadReq_misses::total 401094 +system.cpu.dcache.WriteReq_misses::cpu.data 298865 +system.cpu.dcache.WriteReq_misses::total 298865 +system.cpu.dcache.SoftPFReq_misses::cpu.data 118684 +system.cpu.dcache.SoftPFReq_misses::total 118684 +system.cpu.dcache.LoadLockedReq_misses::cpu.data 22806 +system.cpu.dcache.LoadLockedReq_misses::total 22806 +system.cpu.dcache.StoreCondReq_misses::cpu.data 2 +system.cpu.dcache.StoreCondReq_misses::total 2 +system.cpu.dcache.demand_misses::cpu.data 699959 +system.cpu.dcache.demand_misses::total 699959 +system.cpu.dcache.overall_misses::cpu.data 818643 +system.cpu.dcache.overall_misses::total 818643 +system.cpu.dcache.ReadReq_miss_latency::cpu.data 6435554000 +system.cpu.dcache.ReadReq_miss_latency::total 6435554000 +system.cpu.dcache.WriteReq_miss_latency::cpu.data 14440564500 +system.cpu.dcache.WriteReq_miss_latency::total 14440564500 +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 297902000 +system.cpu.dcache.LoadLockedReq_miss_latency::total 297902000 +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 166000 +system.cpu.dcache.StoreCondReq_miss_latency::total 166000 +system.cpu.dcache.demand_miss_latency::cpu.data 20876118500 +system.cpu.dcache.demand_miss_latency::total 20876118500 +system.cpu.dcache.overall_miss_latency::cpu.data 20876118500 +system.cpu.dcache.overall_miss_latency::total 20876118500 +system.cpu.dcache.ReadReq_accesses::cpu.data 23509972 +system.cpu.dcache.ReadReq_accesses::total 23509972 +system.cpu.dcache.WriteReq_accesses::cpu.data 19119866 +system.cpu.dcache.WriteReq_accesses::total 19119866 +system.cpu.dcache.SoftPFReq_accesses::cpu.data 511127 +system.cpu.dcache.SoftPFReq_accesses::total 511127 +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 465879 +system.cpu.dcache.LoadLockedReq_accesses::total 465879 +system.cpu.dcache.StoreCondReq_accesses::cpu.data 460110 +system.cpu.dcache.StoreCondReq_accesses::total 460110 +system.cpu.dcache.demand_accesses::cpu.data 42629838 +system.cpu.dcache.demand_accesses::total 42629838 +system.cpu.dcache.overall_accesses::cpu.data 43140965 +system.cpu.dcache.overall_accesses::total 43140965 +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.017061 +system.cpu.dcache.ReadReq_miss_rate::total 0.017061 +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015631 +system.cpu.dcache.WriteReq_miss_rate::total 0.015631 +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.232201 +system.cpu.dcache.SoftPFReq_miss_rate::total 0.232201 +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.048953 +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.048953 +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000004 +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000004 +system.cpu.dcache.demand_miss_rate::cpu.data 0.016419 +system.cpu.dcache.demand_miss_rate::total 0.016419 +system.cpu.dcache.overall_miss_rate::cpu.data 0.018976 +system.cpu.dcache.overall_miss_rate::total 0.018976 +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16045.001920 +system.cpu.dcache.ReadReq_avg_miss_latency::total 16045.001920 +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48318.018169 +system.cpu.dcache.WriteReq_avg_miss_latency::total 48318.018169 +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13062.439709 +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13062.439709 +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 83000 +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 83000 +system.cpu.dcache.demand_avg_miss_latency::cpu.data 29824.773308 +system.cpu.dcache.demand_avg_miss_latency::total 29824.773308 +system.cpu.dcache.overall_avg_miss_latency::cpu.data 25500.881947 +system.cpu.dcache.overall_avg_miss_latency::total 25500.881947 +system.cpu.dcache.blocked_cycles::no_mshrs 76 +system.cpu.dcache.blocked_cycles::no_targets 0 +system.cpu.dcache.blocked::no_mshrs 19 +system.cpu.dcache.blocked::no_targets 0 +system.cpu.dcache.avg_blocked_cycles::no_mshrs 4 +system.cpu.dcache.avg_blocked_cycles::no_targets nan +system.cpu.dcache.writebacks::writebacks 685560 +system.cpu.dcache.writebacks::total 685560 +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 708 +system.cpu.dcache.ReadReq_mshr_hits::total 708 +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14280 +system.cpu.dcache.LoadLockedReq_mshr_hits::total 14280 +system.cpu.dcache.demand_mshr_hits::cpu.data 708 +system.cpu.dcache.demand_mshr_hits::total 708 +system.cpu.dcache.overall_mshr_hits::cpu.data 708 +system.cpu.dcache.overall_mshr_hits::total 708 +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 400386 +system.cpu.dcache.ReadReq_mshr_misses::total 400386 +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 298865 +system.cpu.dcache.WriteReq_mshr_misses::total 298865 +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 116661 +system.cpu.dcache.SoftPFReq_mshr_misses::total 116661 +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8526 +system.cpu.dcache.LoadLockedReq_mshr_misses::total 8526 +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 +system.cpu.dcache.StoreCondReq_mshr_misses::total 2 +system.cpu.dcache.demand_mshr_misses::cpu.data 699251 +system.cpu.dcache.demand_mshr_misses::total 699251 +system.cpu.dcache.overall_mshr_misses::cpu.data 815912 +system.cpu.dcache.overall_mshr_misses::total 815912 +system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 31118 +system.cpu.dcache.ReadReq_mshr_uncacheable::total 31118 +system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 27579 +system.cpu.dcache.WriteReq_mshr_uncacheable::total 27579 +system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 58697 +system.cpu.dcache.overall_mshr_uncacheable_misses::total 58697 +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6009948500 +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6009948500 +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14141699500 +system.cpu.dcache.WriteReq_mshr_miss_latency::total 14141699500 +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1587332500 +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1587332500 +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 118971500 +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 118971500 +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 164000 +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 164000 +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 20151648000 +system.cpu.dcache.demand_mshr_miss_latency::total 20151648000 +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 21738980500 +system.cpu.dcache.overall_mshr_miss_latency::total 21738980500 +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6281996500 +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6281996500 +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6281996500 +system.cpu.dcache.overall_mshr_uncacheable_latency::total 6281996500 +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017030 +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017030 +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015631 +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015631 +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.228243 +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.228243 +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.018301 +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.018301 +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000004 +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000004 +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016403 +system.cpu.dcache.demand_mshr_miss_rate::total 0.016403 +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.018913 +system.cpu.dcache.overall_mshr_miss_rate::total 0.018913 +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15010.386227 +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15010.386227 +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 47318.018169 +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 47318.018169 +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13606.368024 +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13606.368024 +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13953.964344 +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13953.964344 +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 82000 +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 82000 +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28818.904800 +system.cpu.dcache.demand_avg_mshr_miss_latency::total 28818.904800 +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26643.780824 +system.cpu.dcache.overall_avg_mshr_miss_latency::total 26643.780824 +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201876.614821 +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201876.614821 +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 107024.149445 +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 107024.149445 +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2905305537500 +system.cpu.icache.tags.replacements 1699808 +system.cpu.icache.tags.tagsinuse 510.693082 +system.cpu.icache.tags.total_refs 113847327 +system.cpu.icache.tags.sampled_refs 1700320 +system.cpu.icache.tags.avg_refs 66.956412 +system.cpu.icache.tags.warmup_cycle 26307743500 +system.cpu.icache.tags.occ_blocks::cpu.inst 510.693082 +system.cpu.icache.tags.occ_percent::cpu.inst 0.997447 +system.cpu.icache.tags.occ_percent::total 0.997447 +system.cpu.icache.tags.occ_task_id_blocks::1024 512 +system.cpu.icache.tags.age_task_id_blocks_1024::0 45 +system.cpu.icache.tags.age_task_id_blocks_1024::1 212 +system.cpu.icache.tags.age_task_id_blocks_1024::2 246 +system.cpu.icache.tags.age_task_id_blocks_1024::3 9 +system.cpu.icache.tags.occ_task_id_percent::1024 1 +system.cpu.icache.tags.tag_accesses 117247979 +system.cpu.icache.tags.data_accesses 117247979 +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2905305537500 +system.cpu.icache.ReadReq_hits::cpu.inst 113847327 +system.cpu.icache.ReadReq_hits::total 113847327 +system.cpu.icache.demand_hits::cpu.inst 113847327 +system.cpu.icache.demand_hits::total 113847327 +system.cpu.icache.overall_hits::cpu.inst 113847327 +system.cpu.icache.overall_hits::total 113847327 +system.cpu.icache.ReadReq_misses::cpu.inst 1700326 +system.cpu.icache.ReadReq_misses::total 1700326 +system.cpu.icache.demand_misses::cpu.inst 1700326 +system.cpu.icache.demand_misses::total 1700326 +system.cpu.icache.overall_misses::cpu.inst 1700326 +system.cpu.icache.overall_misses::total 1700326 +system.cpu.icache.ReadReq_miss_latency::cpu.inst 24041505000 +system.cpu.icache.ReadReq_miss_latency::total 24041505000 +system.cpu.icache.demand_miss_latency::cpu.inst 24041505000 +system.cpu.icache.demand_miss_latency::total 24041505000 +system.cpu.icache.overall_miss_latency::cpu.inst 24041505000 +system.cpu.icache.overall_miss_latency::total 24041505000 +system.cpu.icache.ReadReq_accesses::cpu.inst 115547653 +system.cpu.icache.ReadReq_accesses::total 115547653 +system.cpu.icache.demand_accesses::cpu.inst 115547653 +system.cpu.icache.demand_accesses::total 115547653 +system.cpu.icache.overall_accesses::cpu.inst 115547653 +system.cpu.icache.overall_accesses::total 115547653 +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014715 +system.cpu.icache.ReadReq_miss_rate::total 0.014715 +system.cpu.icache.demand_miss_rate::cpu.inst 0.014715 +system.cpu.icache.demand_miss_rate::total 0.014715 +system.cpu.icache.overall_miss_rate::cpu.inst 0.014715 +system.cpu.icache.overall_miss_rate::total 0.014715 +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14139.350336 +system.cpu.icache.ReadReq_avg_miss_latency::total 14139.350336 +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14139.350336 +system.cpu.icache.demand_avg_miss_latency::total 14139.350336 +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14139.350336 +system.cpu.icache.overall_avg_miss_latency::total 14139.350336 +system.cpu.icache.blocked_cycles::no_mshrs 0 +system.cpu.icache.blocked_cycles::no_targets 0 +system.cpu.icache.blocked::no_mshrs 0 +system.cpu.icache.blocked::no_targets 0 +system.cpu.icache.avg_blocked_cycles::no_mshrs nan +system.cpu.icache.avg_blocked_cycles::no_targets nan +system.cpu.icache.writebacks::writebacks 1699808 +system.cpu.icache.writebacks::total 1699808 +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1700326 +system.cpu.icache.ReadReq_mshr_misses::total 1700326 +system.cpu.icache.demand_mshr_misses::cpu.inst 1700326 +system.cpu.icache.demand_mshr_misses::total 1700326 +system.cpu.icache.overall_mshr_misses::cpu.inst 1700326 +system.cpu.icache.overall_mshr_misses::total 1700326 +system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 9022 +system.cpu.icache.ReadReq_mshr_uncacheable::total 9022 +system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 9022 +system.cpu.icache.overall_mshr_uncacheable_misses::total 9022 +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22341179000 +system.cpu.icache.ReadReq_mshr_miss_latency::total 22341179000 +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22341179000 +system.cpu.icache.demand_mshr_miss_latency::total 22341179000 +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22341179000 +system.cpu.icache.overall_mshr_miss_latency::total 22341179000 +system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 745203000 +system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 745203000 +system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 745203000 +system.cpu.icache.overall_mshr_uncacheable_latency::total 745203000 +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014715 +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014715 +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014715 +system.cpu.icache.demand_mshr_miss_rate::total 0.014715 +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014715 +system.cpu.icache.overall_mshr_miss_rate::total 0.014715 +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13139.350336 +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13139.350336 +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13139.350336 +system.cpu.icache.demand_avg_mshr_miss_latency::total 13139.350336 +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13139.350336 +system.cpu.icache.overall_avg_mshr_miss_latency::total 13139.350336 +system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 82598.426070 +system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 82598.426070 +system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 82598.426070 +system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 82598.426070 +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2905305537500 +system.cpu.l2cache.tags.replacements 88597 +system.cpu.l2cache.tags.tagsinuse 65011.983372 +system.cpu.l2cache.tags.total_refs 4853512 +system.cpu.l2cache.tags.sampled_refs 154024 +system.cpu.l2cache.tags.avg_refs 31.511401 +system.cpu.l2cache.tags.warmup_cycle 147534324000 +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 3.050681 +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.041156 +system.cpu.l2cache.tags.occ_blocks::cpu.inst 9633.139334 +system.cpu.l2cache.tags.occ_blocks::cpu.data 55375.752201 +system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000047 +system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000001 +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.146990 +system.cpu.l2cache.tags.occ_percent::cpu.data 0.844967 +system.cpu.l2cache.tags.occ_percent::total 0.992004 +system.cpu.l2cache.tags.occ_task_id_blocks::1023 5 +system.cpu.l2cache.tags.occ_task_id_blocks::1024 65422 +system.cpu.l2cache.tags.age_task_id_blocks_1023::4 5 +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 1 +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 76 +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4348 +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 60997 +system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000076 +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.998260 +system.cpu.l2cache.tags.tag_accesses 40271303 +system.cpu.l2cache.tags.data_accesses 40271303 +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2905305537500 +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 5062 +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2684 +system.cpu.l2cache.ReadReq_hits::total 7746 +system.cpu.l2cache.WritebackDirty_hits::writebacks 685560 +system.cpu.l2cache.WritebackDirty_hits::total 685560 +system.cpu.l2cache.WritebackClean_hits::writebacks 1667530 +system.cpu.l2cache.WritebackClean_hits::total 1667530 +system.cpu.l2cache.UpgradeReq_hits::cpu.data 2789 +system.cpu.l2cache.UpgradeReq_hits::total 2789 +system.cpu.l2cache.ReadExReq_hits::cpu.data 167631 +system.cpu.l2cache.ReadExReq_hits::total 167631 +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1682332 +system.cpu.l2cache.ReadCleanReq_hits::total 1682332 +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 513501 +system.cpu.l2cache.ReadSharedReq_hits::total 513501 +system.cpu.l2cache.demand_hits::cpu.dtb.walker 5062 +system.cpu.l2cache.demand_hits::cpu.itb.walker 2684 +system.cpu.l2cache.demand_hits::cpu.inst 1682332 +system.cpu.l2cache.demand_hits::cpu.data 681132 +system.cpu.l2cache.demand_hits::total 2371210 +system.cpu.l2cache.overall_hits::cpu.dtb.walker 5062 +system.cpu.l2cache.overall_hits::cpu.itb.walker 2684 +system.cpu.l2cache.overall_hits::cpu.inst 1682332 +system.cpu.l2cache.overall_hits::cpu.data 681132 +system.cpu.l2cache.overall_hits::total 2371210 +system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 7 +system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 +system.cpu.l2cache.ReadReq_misses::total 9 +system.cpu.l2cache.UpgradeReq_misses::cpu.data 19 +system.cpu.l2cache.UpgradeReq_misses::total 19 +system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 +system.cpu.l2cache.SCUpgradeReq_misses::total 2 +system.cpu.l2cache.ReadExReq_misses::cpu.data 128426 +system.cpu.l2cache.ReadExReq_misses::total 128426 +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 17977 +system.cpu.l2cache.ReadCleanReq_misses::total 17977 +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 12072 +system.cpu.l2cache.ReadSharedReq_misses::total 12072 +system.cpu.l2cache.demand_misses::cpu.dtb.walker 7 +system.cpu.l2cache.demand_misses::cpu.itb.walker 2 +system.cpu.l2cache.demand_misses::cpu.inst 17977 +system.cpu.l2cache.demand_misses::cpu.data 140498 +system.cpu.l2cache.demand_misses::total 158484 +system.cpu.l2cache.overall_misses::cpu.dtb.walker 7 +system.cpu.l2cache.overall_misses::cpu.itb.walker 2 +system.cpu.l2cache.overall_misses::cpu.inst 17977 +system.cpu.l2cache.overall_misses::cpu.data 140498 +system.cpu.l2cache.overall_misses::total 158484 +system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 1154000 +system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 180000 +system.cpu.l2cache.ReadReq_miss_latency::total 1334000 +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 553500 +system.cpu.l2cache.UpgradeReq_miss_latency::total 553500 +system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 161000 +system.cpu.l2cache.SCUpgradeReq_miss_latency::total 161000 +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 11899868500 +system.cpu.l2cache.ReadExReq_miss_latency::total 11899868500 +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2066210500 +system.cpu.l2cache.ReadCleanReq_miss_latency::total 2066210500 +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1518806000 +system.cpu.l2cache.ReadSharedReq_miss_latency::total 1518806000 +system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 1154000 +system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 180000 +system.cpu.l2cache.demand_miss_latency::cpu.inst 2066210500 +system.cpu.l2cache.demand_miss_latency::cpu.data 13418674500 +system.cpu.l2cache.demand_miss_latency::total 15486219000 +system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 1154000 +system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 180000 +system.cpu.l2cache.overall_miss_latency::cpu.inst 2066210500 +system.cpu.l2cache.overall_miss_latency::cpu.data 13418674500 +system.cpu.l2cache.overall_miss_latency::total 15486219000 +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 5069 +system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 2686 +system.cpu.l2cache.ReadReq_accesses::total 7755 +system.cpu.l2cache.WritebackDirty_accesses::writebacks 685560 +system.cpu.l2cache.WritebackDirty_accesses::total 685560 +system.cpu.l2cache.WritebackClean_accesses::writebacks 1667530 +system.cpu.l2cache.WritebackClean_accesses::total 1667530 +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2808 +system.cpu.l2cache.UpgradeReq_accesses::total 2808 +system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 +system.cpu.l2cache.SCUpgradeReq_accesses::total 2 +system.cpu.l2cache.ReadExReq_accesses::cpu.data 296057 +system.cpu.l2cache.ReadExReq_accesses::total 296057 +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1700309 +system.cpu.l2cache.ReadCleanReq_accesses::total 1700309 +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 525573 +system.cpu.l2cache.ReadSharedReq_accesses::total 525573 +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 5069 +system.cpu.l2cache.demand_accesses::cpu.itb.walker 2686 +system.cpu.l2cache.demand_accesses::cpu.inst 1700309 +system.cpu.l2cache.demand_accesses::cpu.data 821630 +system.cpu.l2cache.demand_accesses::total 2529694 +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 5069 +system.cpu.l2cache.overall_accesses::cpu.itb.walker 2686 +system.cpu.l2cache.overall_accesses::cpu.inst 1700309 +system.cpu.l2cache.overall_accesses::cpu.data 821630 +system.cpu.l2cache.overall_accesses::total 2529694 +system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.001381 +system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000745 +system.cpu.l2cache.ReadReq_miss_rate::total 0.001161 +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.006766 +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.006766 +system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 +system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.433788 +system.cpu.l2cache.ReadExReq_miss_rate::total 0.433788 +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.010573 +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.010573 +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.022969 +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.022969 +system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.001381 +system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000745 +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010573 +system.cpu.l2cache.demand_miss_rate::cpu.data 0.170999 +system.cpu.l2cache.demand_miss_rate::total 0.062649 +system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.001381 +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000745 +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010573 +system.cpu.l2cache.overall_miss_rate::cpu.data 0.170999 +system.cpu.l2cache.overall_miss_rate::total 0.062649 +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 164857.142857 +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 90000 +system.cpu.l2cache.ReadReq_avg_miss_latency::total 148222.222222 +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 29131.578947 +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 29131.578947 +system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 80500 +system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 80500 +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 92659.340788 +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 92659.340788 +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 114936.335317 +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 114936.335317 +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 125812.292909 +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 125812.292909 +system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 164857.142857 +system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 90000 +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 114936.335317 +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 95507.939615 +system.cpu.l2cache.demand_avg_miss_latency::total 97714.715681 +system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 164857.142857 +system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 90000 +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 114936.335317 +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 95507.939615 +system.cpu.l2cache.overall_avg_miss_latency::total 97714.715681 +system.cpu.l2cache.blocked_cycles::no_mshrs 0 +system.cpu.l2cache.blocked_cycles::no_targets 0 +system.cpu.l2cache.blocked::no_mshrs 0 +system.cpu.l2cache.blocked::no_targets 0 +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan +system.cpu.l2cache.avg_blocked_cycles::no_targets nan +system.cpu.l2cache.writebacks::writebacks 81970 +system.cpu.l2cache.writebacks::total 81970 +system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 7 +system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 +system.cpu.l2cache.ReadReq_mshr_misses::total 9 +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 19 +system.cpu.l2cache.UpgradeReq_mshr_misses::total 19 +system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 +system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 128426 +system.cpu.l2cache.ReadExReq_mshr_misses::total 128426 +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 17977 +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 17977 +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 12072 +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 12072 +system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 7 +system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 +system.cpu.l2cache.demand_mshr_misses::cpu.inst 17977 +system.cpu.l2cache.demand_mshr_misses::cpu.data 140498 +system.cpu.l2cache.demand_mshr_misses::total 158484 +system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 7 +system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 +system.cpu.l2cache.overall_mshr_misses::cpu.inst 17977 +system.cpu.l2cache.overall_mshr_misses::cpu.data 140498 +system.cpu.l2cache.overall_mshr_misses::total 158484 +system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 9022 +system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 31118 +system.cpu.l2cache.ReadReq_mshr_uncacheable::total 40140 +system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 27579 +system.cpu.l2cache.WriteReq_mshr_uncacheable::total 27579 +system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 9022 +system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 58697 +system.cpu.l2cache.overall_mshr_uncacheable_misses::total 67719 +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1084000 +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 160000 +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1244000 +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 363500 +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 363500 +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 141000 +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 141000 +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10615608500 +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10615608500 +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1886440500 +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1886440500 +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1398086000 +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1398086000 +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 1084000 +system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 160000 +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1886440500 +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 12013694500 +system.cpu.l2cache.demand_mshr_miss_latency::total 13901379000 +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 1084000 +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 160000 +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1886440500 +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12013694500 +system.cpu.l2cache.overall_mshr_miss_latency::total 13901379000 +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 632428000 +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5892901500 +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6525329500 +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 632428000 +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5892901500 +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 6525329500 +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001381 +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000745 +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001161 +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.006766 +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.006766 +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.433788 +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.433788 +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.010573 +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.010573 +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.022969 +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.022969 +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001381 +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000745 +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010573 +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.170999 +system.cpu.l2cache.demand_mshr_miss_rate::total 0.062649 +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001381 +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000745 +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010573 +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.170999 +system.cpu.l2cache.overall_mshr_miss_rate::total 0.062649 +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 154857.142857 +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 80000 +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 138222.222222 +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19131.578947 +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19131.578947 +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 70500 +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 70500 +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 82659.340788 +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 82659.340788 +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 104936.335317 +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 104936.335317 +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 115812.292909 +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 115812.292909 +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 154857.142857 +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 80000 +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 104936.335317 +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 85507.939615 +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 87714.715681 +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 154857.142857 +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 80000 +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 104936.335317 +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 85507.939615 +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 87714.715681 +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 70098.426070 +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189372.758532 +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 162564.262581 +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 70098.426070 +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 100395.275738 +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 96358.916995 +system.cpu.toL2Bus.snoop_filter.tot_requests 5064980 +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2543036 +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 39292 +system.cpu.toL2Bus.snoop_filter.tot_snoops 227 +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 227 +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2905305537500 +system.cpu.toL2Bus.trans_dist::ReadReq 67204 +system.cpu.toL2Bus.trans_dist::ReadResp 2293294 +system.cpu.toL2Bus.trans_dist::WriteReq 27579 +system.cpu.toL2Bus.trans_dist::WriteResp 27579 +system.cpu.toL2Bus.trans_dist::WritebackDirty 767530 +system.cpu.toL2Bus.trans_dist::WritebackClean 1699808 +system.cpu.toL2Bus.trans_dist::CleanEvict 142156 +system.cpu.toL2Bus.trans_dist::UpgradeReq 2808 +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 +system.cpu.toL2Bus.trans_dist::UpgradeResp 2810 +system.cpu.toL2Bus.trans_dist::ReadExReq 296057 +system.cpu.toL2Bus.trans_dist::ReadExResp 296057 +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1700326 +system.cpu.toL2Bus.trans_dist::ReadSharedReq 525772 +system.cpu.toL2Bus.trans_dist::InvalidateReq 4351 +system.cpu.toL2Bus.trans_dist::InvalidateResp 14 +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5118487 +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2587568 +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 11902 +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 22917 +system.cpu.toL2Bus.pkt_count::total 7740874 +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 217643576 +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96655427 +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 10744 +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 20276 +system.cpu.toL2Bus.pkt_size::total 314330023 +system.cpu.toL2Bus.snoops 112678 +system.cpu.toL2Bus.snoopTraffic 5336628 +system.cpu.toL2Bus.snoop_fanout::samples 2712696 +system.cpu.toL2Bus.snoop_fanout::mean 0.021694 +system.cpu.toL2Bus.snoop_fanout::stdev 0.145681 +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% +system.cpu.toL2Bus.snoop_fanout::0 2653848 97.83% 97.83% +system.cpu.toL2Bus.snoop_fanout::1 58848 2.17% 100.00% +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% +system.cpu.toL2Bus.snoop_fanout::min_value 0 +system.cpu.toL2Bus.snoop_fanout::max_value 1 +system.cpu.toL2Bus.snoop_fanout::total 2712696 +system.cpu.toL2Bus.reqLayer0.occupancy 4969380500 +system.cpu.toL2Bus.reqLayer0.utilization 0.2 +system.cpu.toL2Bus.snoopLayer0.occupancy 354876 +system.cpu.toL2Bus.snoopLayer0.utilization 0.0 +system.cpu.toL2Bus.respLayer0.occupancy 2559511000 +system.cpu.toL2Bus.respLayer0.utilization 0.1 +system.cpu.toL2Bus.respLayer1.occupancy 1278757500 +system.cpu.toL2Bus.respLayer1.utilization 0.0 +system.cpu.toL2Bus.respLayer2.occupancy 9216000 +system.cpu.toL2Bus.respLayer2.utilization 0.0 +system.cpu.toL2Bus.respLayer3.occupancy 17848000 +system.cpu.toL2Bus.respLayer3.utilization 0.0 +system.iobus.pwrStateResidencyTicks::UNDEFINED 2905305537500 +system.iobus.trans_dist::ReadReq 30149 +system.iobus.trans_dist::ReadResp 30149 +system.iobus.trans_dist::WriteReq 59014 +system.iobus.trans_dist::WriteResp 59014 +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54170 +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 +system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 +system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 +system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 120 +system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 834 +system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 +system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 +system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 +system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 +system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 +system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 +system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 +system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 +system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 +system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 +system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 +system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 +system.iobus.pkt_count_system.bridge.master::total 105458 +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72868 +system.iobus.pkt_count_system.realview.ide.dma::total 72868 +system.iobus.pkt_count::total 178326 +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67887 +system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 +system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 +system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 +system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 +system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 84 +system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 441 +system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 +system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 +system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 +system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 +system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 +system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 +system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 +system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 +system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 +system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 +system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 +system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 +system.iobus.pkt_size_system.bridge.master::total 159115 +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2320912 +system.iobus.pkt_size_system.realview.ide.dma::total 2320912 +system.iobus.pkt_size::total 2480027 +system.iobus.reqLayer0.occupancy 46336500 +system.iobus.reqLayer0.utilization 0.0 +system.iobus.reqLayer1.occupancy 97000 +system.iobus.reqLayer1.utilization 0.0 +system.iobus.reqLayer2.occupancy 338000 +system.iobus.reqLayer2.utilization 0.0 +system.iobus.reqLayer3.occupancy 29500 +system.iobus.reqLayer3.utilization 0.0 +system.iobus.reqLayer4.occupancy 15500 +system.iobus.reqLayer4.utilization 0.0 +system.iobus.reqLayer7.occupancy 91500 +system.iobus.reqLayer7.utilization 0.0 +system.iobus.reqLayer8.occupancy 630500 +system.iobus.reqLayer8.utilization 0.0 +system.iobus.reqLayer10.occupancy 21000 +system.iobus.reqLayer10.utilization 0.0 +system.iobus.reqLayer13.occupancy 11500 +system.iobus.reqLayer13.utilization 0.0 +system.iobus.reqLayer14.occupancy 12000 +system.iobus.reqLayer14.utilization 0.0 +system.iobus.reqLayer15.occupancy 12000 +system.iobus.reqLayer15.utilization 0.0 +system.iobus.reqLayer16.occupancy 52500 +system.iobus.reqLayer16.utilization 0.0 +system.iobus.reqLayer17.occupancy 12000 +system.iobus.reqLayer17.utilization 0.0 +system.iobus.reqLayer18.occupancy 11500 +system.iobus.reqLayer18.utilization 0.0 +system.iobus.reqLayer19.occupancy 2000 +system.iobus.reqLayer19.utilization 0.0 +system.iobus.reqLayer20.occupancy 9000 +system.iobus.reqLayer20.utilization 0.0 +system.iobus.reqLayer21.occupancy 11500 +system.iobus.reqLayer21.utilization 0.0 +system.iobus.reqLayer23.occupancy 6289000 +system.iobus.reqLayer23.utilization 0.0 +system.iobus.reqLayer24.occupancy 36469500 +system.iobus.reqLayer24.utilization 0.0 +system.iobus.reqLayer25.occupancy 187505138 +system.iobus.reqLayer25.utilization 0.0 +system.iobus.respLayer0.occupancy 82668000 +system.iobus.respLayer0.utilization 0.0 +system.iobus.respLayer3.occupancy 36692000 +system.iobus.respLayer3.utilization 0.0 +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2905305537500 +system.iocache.tags.replacements 36400 +system.iocache.tags.tagsinuse 1.079831 +system.iocache.tags.total_refs 0 +system.iocache.tags.sampled_refs 36416 +system.iocache.tags.avg_refs 0 +system.iocache.tags.warmup_cycle 310617748000 +system.iocache.tags.occ_blocks::realview.ide 1.079831 +system.iocache.tags.occ_percent::realview.ide 0.067489 +system.iocache.tags.occ_percent::total 0.067489 +system.iocache.tags.occ_task_id_blocks::1023 16 +system.iocache.tags.age_task_id_blocks_1023::3 16 +system.iocache.tags.occ_task_id_percent::1023 1 +system.iocache.tags.tag_accesses 327906 +system.iocache.tags.data_accesses 327906 +system.iocache.pwrStateResidencyTicks::UNDEFINED 2905305537500 +system.iocache.ReadReq_misses::realview.ide 210 +system.iocache.ReadReq_misses::total 210 +system.iocache.WriteLineReq_misses::realview.ide 36224 +system.iocache.WriteLineReq_misses::total 36224 +system.iocache.demand_misses::realview.ide 36434 +system.iocache.demand_misses::total 36434 +system.iocache.overall_misses::realview.ide 36434 +system.iocache.overall_misses::total 36434 +system.iocache.ReadReq_miss_latency::realview.ide 34066376 +system.iocache.ReadReq_miss_latency::total 34066376 +system.iocache.WriteLineReq_miss_latency::realview.ide 4376106762 +system.iocache.WriteLineReq_miss_latency::total 4376106762 +system.iocache.demand_miss_latency::realview.ide 4410173138 +system.iocache.demand_miss_latency::total 4410173138 +system.iocache.overall_miss_latency::realview.ide 4410173138 +system.iocache.overall_miss_latency::total 4410173138 +system.iocache.ReadReq_accesses::realview.ide 210 +system.iocache.ReadReq_accesses::total 210 +system.iocache.WriteLineReq_accesses::realview.ide 36224 +system.iocache.WriteLineReq_accesses::total 36224 +system.iocache.demand_accesses::realview.ide 36434 +system.iocache.demand_accesses::total 36434 +system.iocache.overall_accesses::realview.ide 36434 +system.iocache.overall_accesses::total 36434 +system.iocache.ReadReq_miss_rate::realview.ide 1 +system.iocache.ReadReq_miss_rate::total 1 +system.iocache.WriteLineReq_miss_rate::realview.ide 1 +system.iocache.WriteLineReq_miss_rate::total 1 +system.iocache.demand_miss_rate::realview.ide 1 +system.iocache.demand_miss_rate::total 1 +system.iocache.overall_miss_rate::realview.ide 1 +system.iocache.overall_miss_rate::total 1 +system.iocache.ReadReq_avg_miss_latency::realview.ide 162220.838095 +system.iocache.ReadReq_avg_miss_latency::total 162220.838095 +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120806.834198 +system.iocache.WriteLineReq_avg_miss_latency::total 120806.834198 +system.iocache.demand_avg_miss_latency::realview.ide 121045.538179 +system.iocache.demand_avg_miss_latency::total 121045.538179 +system.iocache.overall_avg_miss_latency::realview.ide 121045.538179 +system.iocache.overall_avg_miss_latency::total 121045.538179 +system.iocache.blocked_cycles::no_mshrs 208 +system.iocache.blocked_cycles::no_targets 0 +system.iocache.blocked::no_mshrs 4 +system.iocache.blocked::no_targets 0 +system.iocache.avg_blocked_cycles::no_mshrs 52 +system.iocache.avg_blocked_cycles::no_targets nan +system.iocache.writebacks::writebacks 36190 +system.iocache.writebacks::total 36190 +system.iocache.ReadReq_mshr_misses::realview.ide 210 +system.iocache.ReadReq_mshr_misses::total 210 +system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 +system.iocache.WriteLineReq_mshr_misses::total 36224 +system.iocache.demand_mshr_misses::realview.ide 36434 +system.iocache.demand_mshr_misses::total 36434 +system.iocache.overall_mshr_misses::realview.ide 36434 +system.iocache.overall_mshr_misses::total 36434 +system.iocache.ReadReq_mshr_miss_latency::realview.ide 23566376 +system.iocache.ReadReq_mshr_miss_latency::total 23566376 +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2563140504 +system.iocache.WriteLineReq_mshr_miss_latency::total 2563140504 +system.iocache.demand_mshr_miss_latency::realview.ide 2586706880 +system.iocache.demand_mshr_miss_latency::total 2586706880 +system.iocache.overall_mshr_miss_latency::realview.ide 2586706880 +system.iocache.overall_mshr_miss_latency::total 2586706880 +system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 +system.iocache.ReadReq_mshr_miss_rate::total 1 +system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 +system.iocache.WriteLineReq_mshr_miss_rate::total 1 +system.iocache.demand_mshr_miss_rate::realview.ide 1 +system.iocache.demand_mshr_miss_rate::total 1 +system.iocache.overall_mshr_miss_rate::realview.ide 1 +system.iocache.overall_mshr_miss_rate::total 1 +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 112220.838095 +system.iocache.ReadReq_avg_mshr_miss_latency::total 112220.838095 +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70758.074867 +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70758.074867 +system.iocache.demand_avg_mshr_miss_latency::realview.ide 70997.059889 +system.iocache.demand_avg_mshr_miss_latency::total 70997.059889 +system.iocache.overall_avg_mshr_miss_latency::realview.ide 70997.059889 +system.iocache.overall_avg_mshr_miss_latency::total 70997.059889 +system.membus.snoop_filter.tot_requests 319999 +system.membus.snoop_filter.hit_single_requests 129537 +system.membus.snoop_filter.hit_multi_requests 496 +system.membus.snoop_filter.tot_snoops 0 +system.membus.snoop_filter.hit_single_snoops 0 +system.membus.snoop_filter.hit_multi_snoops 0 +system.membus.pwrStateResidencyTicks::UNDEFINED 2905305537500 +system.membus.trans_dist::ReadReq 40140 +system.membus.trans_dist::ReadResp 70408 +system.membus.trans_dist::WriteReq 27579 +system.membus.trans_dist::WriteResp 27579 +system.membus.trans_dist::WritebackDirty 118160 +system.membus.trans_dist::CleanEvict 6837 +system.membus.trans_dist::UpgradeReq 128 +system.membus.trans_dist::SCUpgradeReq 2 +system.membus.trans_dist::UpgradeResp 2 +system.membus.trans_dist::ReadExReq 128317 +system.membus.trans_dist::ReadExResp 128317 +system.membus.trans_dist::ReadSharedReq 30268 +system.membus.trans_dist::InvalidateReq 36224 +system.membus.trans_dist::InvalidateResp 4315 +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105458 +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2064 +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 433106 +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 540638 +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72849 +system.membus.pkt_count_system.iocache.mem_side::total 72849 +system.membus.pkt_count::total 613487 +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159115 +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4128 +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15420220 +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 15583483 +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 +system.membus.pkt_size_system.iocache.mem_side::total 2317120 +system.membus.pkt_size::total 17900603 +system.membus.snoops 4789 +system.membus.snoopTraffic 30208 +system.membus.snoop_fanout::samples 262658 +system.membus.snoop_fanout::mean 0.018385 +system.membus.snoop_fanout::stdev 0.134340 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 257829 98.16% 98.16% +system.membus.snoop_fanout::1 4829 1.84% 100.00% +system.membus.snoop_fanout::2 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 1 +system.membus.snoop_fanout::total 262658 +system.membus.reqLayer0.occupancy 90452000 +system.membus.reqLayer0.utilization 0.0 +system.membus.reqLayer1.occupancy 7500 +system.membus.reqLayer1.utilization 0.0 +system.membus.reqLayer2.occupancy 1690500 +system.membus.reqLayer2.utilization 0.0 +system.membus.reqLayer5.occupancy 822823297 +system.membus.reqLayer5.utilization 0.0 +system.membus.respLayer2.occupancy 948595750 +system.membus.respLayer2.utilization 0.0 +system.membus.respLayer3.occupancy 5614930 +system.membus.respLayer3.utilization 0.0 +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2905305537500 +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2905305537500 +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2905305537500 +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2905305537500 +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2905305537500 +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2905305537500 +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2905305537500 +system.realview.dcc.osc_cpu.clock 16667 +system.realview.dcc.osc_ddr.clock 25000 +system.realview.dcc.osc_hsbm.clock 25000 +system.realview.dcc.osc_pxl.clock 42105 +system.realview.dcc.osc_smb.clock 20000 +system.realview.dcc.osc_sys.clock 16667 +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2905305537500 +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2905305537500 +system.realview.ethernet.descDMAReads 0 +system.realview.ethernet.descDMAWrites 0 +system.realview.ethernet.descDmaReadBytes 0 +system.realview.ethernet.descDmaWriteBytes 0 +system.realview.ethernet.postedSwi 0 +system.realview.ethernet.coalescedSwi nan +system.realview.ethernet.totalSwi 0 +system.realview.ethernet.postedRxIdle 0 +system.realview.ethernet.coalescedRxIdle nan +system.realview.ethernet.totalRxIdle 0 +system.realview.ethernet.postedRxOk 0 +system.realview.ethernet.coalescedRxOk nan +system.realview.ethernet.totalRxOk 0 +system.realview.ethernet.postedRxDesc 0 +system.realview.ethernet.coalescedRxDesc nan +system.realview.ethernet.totalRxDesc 0 +system.realview.ethernet.postedTxOk 0 +system.realview.ethernet.coalescedTxOk nan +system.realview.ethernet.totalTxOk 0 +system.realview.ethernet.postedTxIdle 0 +system.realview.ethernet.coalescedTxIdle nan +system.realview.ethernet.totalTxIdle 0 +system.realview.ethernet.postedTxDesc 0 +system.realview.ethernet.coalescedTxDesc nan +system.realview.ethernet.totalTxDesc 0 +system.realview.ethernet.postedRxOrn 0 +system.realview.ethernet.coalescedRxOrn nan +system.realview.ethernet.totalRxOrn 0 +system.realview.ethernet.coalescedTotal nan +system.realview.ethernet.postedInterrupts 0 +system.realview.ethernet.droppedPackets 0 +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2905305537500 +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2905305537500 +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2905305537500 +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2905305537500 +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2905305537500 +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2905305537500 +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2905305537500 +system.realview.mcc.osc_clcd.clock 42105 +system.realview.mcc.osc_mcc.clock 20000 +system.realview.mcc.osc_peripheral.clock 41667 +system.realview.mcc.osc_system_bus.clock 41667 +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2905305537500 +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2905305537500 +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2905305537500 +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2905305537500 +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2905305537500 +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2905305537500 +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2905305537500 +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2905305537500 +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2905305537500 +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2905305537500 +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2905305537500 +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2905305537500 ---------- End Simulation Statistics ---------- |